我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- ~: e8 w1 D0 v7 o2 c0 ^0 S
input mcasp_ahclkx,
9 a" a" ^7 o# s4 Einput mcasp_aclkx,* V2 Z2 e1 I1 _. @
input axr0,& |/ y0 ?+ Y# Z Q6 h0 T
: X+ h) z2 }! m$ s# z; Routput mcasp_afsr,
# `* \' n% I* d0 {' m7 y; k @output mcasp_ahclkr,$ m& o q+ Q/ ^- j7 f4 _' y
output mcasp_aclkr,8 M& _. j: U( F6 o
output axr1,9 J1 ?4 @0 o" N2 t$ s( N
assign mcasp_afsr = mcasp_afsx;
2 F5 J1 G3 ]7 J% Iassign mcasp_aclkr = mcasp_aclkx;$ j& Q h3 \, `4 I
assign mcasp_ahclkr = mcasp_ahclkx;/ {3 r5 ~: u3 Q6 i
assign axr1 = axr0;
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, {4 d7 y4 X. ] i/ d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 D V. j- l1 C- M; A! Nstatic void McASPI2SConfigure(void)
0 T$ d8 C0 N3 Q: J/ L* {# c{
* w0 p% M6 [9 i7 N; Z; H" \: UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- a* N$ W8 k* z4 @ V9 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ @- ~3 H# t. {% B& R8 `4 VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 N3 J4 s! i9 ]# SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 U. m( q" |& V/ n7 T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ d9 Q9 }3 z8 `- v/ ^+ @MCASP_RX_MODE_DMA);
# i! M: W# r8 X" t3 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 C3 O' D$ w5 F3 c- n. X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% J. R# e, _& y$ u$ ?) i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 J( F1 S; u4 f4 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. g8 n+ H Z' M: t. s+ ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - U- ~+ E+ S1 I9 \/ z8 }1 ^1 v2 i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( E, x8 P0 M# \: aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# H: v9 o2 O f5 ~. eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* M0 k9 m4 s5 _! O9 Y2 `# iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 }3 `8 R* V: I3 L: ~ `
0x00, 0xFF); /* configure the clock for transmitter */
9 ]% E& f- t. b9 R/ Y$ QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 Y) j- Y1 m% x2 a9 T) b# w+ iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 D+ d8 R7 x( ?- F' g. lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! }: j1 [1 `' ~# ?0x00, 0xFF);" ]7 G/ ?# X6 y- i _
* Y( F& S" h! F- B$ ^; P, S' Q' t
/* Enable synchronization of RX and TX sections */ 6 b- C9 Y7 G6 d ^* f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 H/ l! Y+ X- DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* d- E6 x, X# J ]+ M' b% MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ \0 Q6 f9 D+ ?- l* Q** Set the serializers, Currently only one serializer is set as2 U$ a3 L/ Y' L- `9 B8 x0 {' e( m
** transmitter and one serializer as receiver.
6 H. {3 C- V6 g*/7 R! W# }/ _" Q# P7 W- d! I2 \1 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 D# [* v, X% D% gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- [3 G% ^3 |: ?+ m% O# O/ r** Configure the McASP pins / H, L) V* y' n- X0 y
** Input - Frame Sync, Clock and Serializer Rx
: W4 W& J! ~ A2 Z: Q** Output - Serializer Tx is connected to the input of the codec
6 o/ C: l% o7 v$ a3 |% L4 u*/0 K2 G$ y) Z, i! v1 H4 J1 c: A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! B7 w/ Y! h3 t: b6 ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' p3 D; v6 u" H6 Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ P# g/ z" c1 U+ ]
| MCASP_PIN_ACLKX, k5 C# R; h4 }9 u2 M
| MCASP_PIN_AHCLKX) m/ n3 T. u" g3 Q5 y' H `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, ~$ b& s& V2 W/ W9 [) R8 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( O$ x) |5 ]5 t! v& h, p4 O| MCASP_TX_CLKFAIL + a, k; E$ g4 V1 c, @) }* q. a
| MCASP_TX_SYNCERROR
" X% C3 Z% I Q2 s+ C- ~! a& g' G9 A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 l* f2 o6 n3 j) M& A5 j
| MCASP_RX_CLKFAIL
! W8 P2 T$ i( A6 `4 W3 E| MCASP_RX_SYNCERROR
! Y1 }5 y% [7 C| MCASP_RX_OVERRUN);
: l) m* }2 l4 K% L R} static void I2SDataTxRxActivate(void)
* i. W8 a+ f) U/ v. r7 F{
+ C" v0 l2 X) d% b/* Start the clocks */3 s( b. \& t! f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ n6 U# ~2 W! v( g+ N3 xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) y% y+ V$ U0 s* ^. D1 A, ?/ B* S/ V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 G9 a$ B+ [( m; U
EDMA3_TRIG_MODE_EVENT);
4 `( m" M) r0 f3 \# pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 d" c- {( W! k+ O, [. u6 j, wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 x: \' e' ?: @$ e1 ?) T% A% M$ W% A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 j' o0 S! r4 b2 V! }4 s' j% r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! Q6 t$ b. R. M: _% S" Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// Q$ h6 k5 q, W l$ t0 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 ^$ b- ^8 o; M2 c/ T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 [ J3 s+ m+ V7 p
}
: ]* I$ A& r- ?2 X* z9 p6 @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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