MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
) N& v: O* R" X* Y( F9 r2 @8 Sinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

& o# l8 ^. W. Moutput mcasp_afsr,
  m# f& b8 i6 b7 aoutput mcasp_ahclkr,
% U$ j+ J) s2 E/ H% I0 }6 Aoutput mcasp_aclkr,
& O, ]  H: J4 k: eoutput axr1,
1 S4 R& I6 d* [( p

assign mcasp_afsr = mcasp_afsx;
9 g1 R. W4 G% a$ j% Hassign mcasp_aclkr = mcasp_aclkx;
  E# H/ L" x, ^5 e& T# ?- qassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

, Y) ]# R1 P1 B8 m3 a6 l

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
. e$ w# ~8 P$ `- ]( ?( l{
+ \2 D% A0 x9 s/ E, cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; x; S" r/ w, Z/ P( q5 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
6 e& H) l: {0 W: {  t0 jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% u+ {1 r! x& m* \" EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
8 G: p7 x' {. r2 IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
/ _; s! O* t* _# W0 N; Q. [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& f% E; E' P- Y& H! V, _3 ]MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' r1 h8 i) E, [% }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 g0 w( ^' x3 C3 A, |0x00, 0xFF);

/* configure the clock for transmitter */
2 |0 S9 u* g6 y+ e. w4 F- v" o% fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 A' F+ J6 r7 v: H2 p0 Y7 T) j: }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
  A$ A0 F- r' d0x00, 0xFF);

/ M1 v! U. w1 K/* Enable synchronization of RX and TX sections */
6 G' ]! a% A3 `$ k" hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 n* a" v1 _; t# Z$ a. FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
6 x# S, `) _/ [*/
2 S% e6 M  E8 w! T8 }* G; A& P, C. EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
0 ^2 X, k) H1 T7 |" @** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
( ]3 W2 P: |5 L5 |6 K( i9 b: m& A*/
" W# |, o: w1 G  y. _  G& wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 d5 u' ]3 z7 S9 aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
5 I3 v, ~$ @6 T. J* W/ }9 B4 D- s| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
& k# k3 I' Z6 z3 K' t% L| MCASP_RX_OVERRUN);
: [9 c  R8 W, m2 E9 f% L5 a1 }}

static void I2SDataTxRxActivate(void)
{
: Z2 V2 X9 y# ?6 i2 S1 \/* Start the clocks */
' P3 z1 X; t6 k5 C" sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# J4 {1 o9 _4 w% c! FEDMA3_TRIG_MODE_EVENT);
' V3 H5 x+ o0 v) q! BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
9 X' H; g  V: e- z* g# CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 [, i5 X. f; l% O$ R+ y& gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
! c# z+ ~) L7 P. p( T5 P4 J8 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

" l) m5 v6 S; n  @1 ~

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

0 z' _1 T5 ?3 n( _