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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' d# d0 W* U- a' n' V' c" ~& binput mcasp_ahclkx,5 K% G: n4 t$ ~7 H! | b0 i
input mcasp_aclkx,
. |: V; H2 z# k n- U- \3 c" Qinput axr0,
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$ C- T5 k) h+ g) C7 |7 B/ n& Ooutput mcasp_afsr,' C6 t, y p6 c- J/ e1 Q
output mcasp_ahclkr,
" G! n/ Q2 @/ O! s" c1 O; Soutput mcasp_aclkr,
, y4 B" o \: u% Z8 X1 Foutput axr1,
# |0 O# k. G! y0 I- U1 m- r assign mcasp_afsr = mcasp_afsx;
& p _. u# ^. S% }assign mcasp_aclkr = mcasp_aclkx;
! F9 Q( f1 H! b3 n% k* o; |9 jassign mcasp_ahclkr = mcasp_ahclkx;. n/ C9 D0 ?6 n% U
assign axr1 = axr0;
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6 u- S' z6 ~& m5 I* y. K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 W" j# k" |$ H; {# s6 Fstatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! r5 [9 c4 r) ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& }# A: o. W4 z# Z1 n, y0 a ^# X2 |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. ^2 o+ l9 ? o, y5 G& mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* T9 Q) w. b" Y: \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ z, U$ J! I" p& z; `- T! c! |; kMCASP_RX_MODE_DMA);5 Z9 X: \8 I/ \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& L7 N5 k! s- O1 \- n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ ?" C* z2 u" x' [ _2 [' f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 d/ r1 p( N7 N3 E9 n3 x9 S; |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& u# H1 B. D1 O, e: R, OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 E# u A L' H# n* HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 G3 G8 g. x. E: N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) Y7 m3 f! q5 O# d. V' k" X0 W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 e' K1 R, r, S4 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 e3 c) Q V9 O5 m0x00, 0xFF); /* configure the clock for transmitter */
8 G. f* E% n, |- F& H: CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 z7 C) z3 h" U4 P# i) s3 G: T9 OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - A& E7 X6 O4 @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& j0 A5 L; o# u0x00, 0xFF);0 v5 d: t2 H- z1 o8 e$ l- }
. {9 h' ^6 {5 [; B/ _$ M' x k/* Enable synchronization of RX and TX sections */
0 X( r" S# _7 C. x- kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ V+ O, c1 |. p: J5 c: r2 W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; g& h- `( X3 s, M5 c
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% B7 \2 `8 r' b1 N
** Set the serializers, Currently only one serializer is set as
& k9 H" I$ X3 l/ y. z4 d- x8 ~+ v** transmitter and one serializer as receiver.
$ l" h7 }& f# y3 t: F*/
( U* f0 U7 V R! h, H% eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% Z3 L0 j+ s9 f$ N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* z: k; f, t2 ~1 _9 o+ y2 Z** Configure the McASP pins 3 G' Z# z* u) @
** Input - Frame Sync, Clock and Serializer Rx
$ g% ]. ~; u0 ~** Output - Serializer Tx is connected to the input of the codec & ^0 t2 Q u- f6 o: R
*/# D( O P' l5 v( v' [3 V' `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% u8 X" h3 |& yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 ]2 N: `6 q8 J9 i0 t' pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) `% C, |* q! `; z2 ?| MCASP_PIN_ACLKX* ]# O. v& f' i3 o" I
| MCASP_PIN_AHCLKX
' E' r4 d9 A& N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 R2 {& p3 U6 l( ~ \0 c2 f$ dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ h- ?- N0 J. v8 S% v# u# F# \0 M1 k| MCASP_TX_CLKFAIL / u; F4 U. t [. p, A* j9 N
| MCASP_TX_SYNCERROR
1 {; u a: T6 y% q6 h, m, g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 \7 z5 z. F: v* Z2 I! p7 z| MCASP_RX_CLKFAIL
! B4 `2 J. `& ~) o4 A' u- s| MCASP_RX_SYNCERROR 6 i$ c1 s* A7 {4 ]2 m- i
| MCASP_RX_OVERRUN);6 u% b0 H) U( h3 Q2 K
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
% C6 U5 _$ K9 }: T3 D; C! w0 PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& g1 D' e' A5 [1 H5 i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ W, K. C+ d* J$ K1 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, G7 @( m8 s8 m" z. `' p
EDMA3_TRIG_MODE_EVENT);. X6 O1 G+ Z1 H( h8 W/ u# y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" e& z/ z) E2 E: J9 IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ H. T7 \4 ]% \4 N7 ~# dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 P5 C/ E7 _ L3 }4 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: [: a: ]2 q( f1 y, L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 c) P$ S$ c' `; P9 u+ G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 S9 @9 {* E4 i2 Y7 J/ _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# d% @/ D4 r5 A4 d5 [8 r, t
}
% @5 ^4 l& @, f5 `! y7 O& S! i m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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