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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 Y5 k: Y) |5 c$ H2 h- U, f$ v
input mcasp_ahclkx," L' b, y% {% m$ F
input mcasp_aclkx,
- g7 ]* q, @' J, rinput axr0,
& g6 U5 {" p+ ^# I1 D5 s6 l* D- V1 C4 A
output mcasp_afsr,
4 A& ]0 H# \8 G( woutput mcasp_ahclkr,
- j" b9 z [1 G- p) Z5 P" ~% b% Toutput mcasp_aclkr,- s$ k4 r0 V7 M' \
output axr1,
0 A; D: C% P, k5 d# Z assign mcasp_afsr = mcasp_afsx;0 F2 m' N# i; R/ @# Q0 n7 i- |& C
assign mcasp_aclkr = mcasp_aclkx;
7 i9 u' I( N7 n% A) I* Aassign mcasp_ahclkr = mcasp_ahclkx;; M* {% G8 D# `( d- L
assign axr1 = axr0; ; i8 f% F! }" H: e$ P. `
) }3 p5 q: V: F. P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 |/ d9 Z4 w# w% T8 m6 H: |2 zstatic void McASPI2SConfigure(void)% X: m) E0 b+ b- }1 {( K! K
{( S, c* G8 T2 U- d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! F# f9 T$ X( ^+ uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 v) a+ y, o( _: F% }- Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: P* `0 z5 g; j0 }1 SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 I' N3 W' q4 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 ?4 H8 i& M; @) Z' }MCASP_RX_MODE_DMA);% t I' b7 _6 c, Y( `* f6 z; W- v3 R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. u' b+ A! U3 v# L* b9 O4 e: C# nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ c! R Q0 J. y1 i7 i. FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& N l; k" U5 D& |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: R% R5 _ X W) g) J" c0 yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , b( y5 D, ^3 B2 Q* }4 g
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ z2 ~! Q( c9 s2 k6 m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( [, h( W2 Z( O! N, J$ o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + L2 s0 O& x6 r( |$ G/ Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 m7 t I$ F: v' C0x00, 0xFF); /* configure the clock for transmitter */
. ^& }# O$ p1 O5 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' U7 b: U8 `1 s, `. W# b0 Z8 d. `) _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) T6 c$ M4 f% o* u7 e) u" b9 kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) c) y( c% o h% U+ f' O
0x00, 0xFF);
9 t8 W+ ]& ? E Q3 a+ _( |' m2 p) A9 G0 A) M$ T* F
/* Enable synchronization of RX and TX sections */
2 s3 r, n; E" j5 [5 @6 |8 cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
m0 |, `8 s9 {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* R0 H% C6 H4 i' b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) j' | y8 m$ L1 R8 i
** Set the serializers, Currently only one serializer is set as G. y; b r U) ]& E
** transmitter and one serializer as receiver.' j+ n' u2 k. N" G
*/" o J/ a9 F4 v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 k! y- |0 p: _$ c% I9 j5 j% X0 ]9 OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# k b6 |% o6 N: G( u& i- w# L4 }
** Configure the McASP pins - F; ]0 v& E {0 N, [+ h
** Input - Frame Sync, Clock and Serializer Rx
) |$ ^+ n. g4 Z2 B9 t0 C* W' H** Output - Serializer Tx is connected to the input of the codec
$ E$ a. |: ~, X: H# r' M% a*/1 M( J r: m: F) L' {. {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 k* u( ^2 F" a8 N F a* F, G/ _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ ^' A$ h* i) Q. w" d% A- c; b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ u: e t2 o: r+ _) b Y
| MCASP_PIN_ACLKX" T4 ^# ] B% g" _" e; z
| MCASP_PIN_AHCLKX+ l" F; C6 a; o2 n0 {7 ?% ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. j* o! V \. v7 I# B# G" TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 @' S( p* a- K* m3 d& C, P1 \$ r
| MCASP_TX_CLKFAIL & O4 x" R. d. R' j
| MCASP_TX_SYNCERROR
' d" O8 ?3 X& l! n$ i- G2 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 |3 O& M, z# S+ t| MCASP_RX_CLKFAIL
" ]7 e) Z" g4 V0 Q9 Z7 G| MCASP_RX_SYNCERROR 9 Y+ Z1 e% N4 [& ?! j5 K& o, j+ ]
| MCASP_RX_OVERRUN); O B2 t( [( X' q5 k E; `' ]* Y
} static void I2SDataTxRxActivate(void)
, D0 s4 {* i8 f8 c{- j. L% T8 l9 c; r2 A9 Y Y
/* Start the clocks */
! Q1 R- s) d9 C- ^4 oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 |! Z( K. G9 ` a! h4 @8 P% w0 u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' c+ ]$ N4 Z7 M: Y2 }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ N: Y8 W# U. T% U, |1 q2 S
EDMA3_TRIG_MODE_EVENT);
6 {8 \" {1 ]! B+ P. F2 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 f0 b5 }' l; C+ S I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, s8 C5 z3 S3 W1 R7 U V; z! }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# }' e5 b$ W2 r3 _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% G! g! u9 V; H: H$ e7 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 r4 p. M& L5 l' a( \# dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) U2 {2 G* @: d1 p) Z# ?8 U, G3 M' _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 Q4 j7 U2 [6 d3 J) \}
% m9 g2 n! m3 `( B: k2 t5 X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / ?1 z( n5 P" u( e$ T* E7 Q
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