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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 H% U6 N8 g8 W: a" S0 U, x& _input mcasp_ahclkx,
/ `5 j8 w9 u) k2 ^& y2 F: finput mcasp_aclkx,
4 {* b- ?* [2 m) E8 J/ }# Finput axr0,: C) r& o0 r4 y1 Y& p9 z
5 |3 U5 K. I8 c. s) Youtput mcasp_afsr,
4 Q5 I( k1 U. B9 Y" aoutput mcasp_ahclkr,
3 k( ?8 g* C( d) `$ H6 loutput mcasp_aclkr,
3 H. F+ S6 o% R$ c, f: }& T$ moutput axr1,
% A1 k, c- b5 z9 O2 b2 z" L' o( U assign mcasp_afsr = mcasp_afsx;
- l5 x+ p5 L9 O: w4 I) Uassign mcasp_aclkr = mcasp_aclkx;
) S; ^. v6 E$ o' x. }assign mcasp_ahclkr = mcasp_ahclkx;6 \7 p( l, Z, C: k5 ?& o5 w
assign axr1 = axr0;
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3 \) g9 C7 n3 z9 Q/ ?7 ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" y: G# H U6 m8 ?static void McASPI2SConfigure(void)# F f' \- m8 `" l& `+ k; w1 R
{
$ n+ o1 S; f# T& s5 i- @7 cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' P, w+ ?% I, v* V2 ]& E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 B D6 Y7 y) N0 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 A: _* `. ]# p1 F/ ?$ kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, ?6 I" J5 w7 I9 _' a$ a+ Q% z5 GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# B) i- r# [+ d% ]; UMCASP_RX_MODE_DMA);
" t& G8 k3 }- A0 d% v. dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ k# }/ U3 Z% j4 t/ EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 l+ @" U, f+ d3 bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 R% z$ d# b; B9 sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 f8 j& L# ]9 Q. n! M& L2 QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 N1 t, q7 L' x" e! B; Z4 A WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" J5 ~) i, {1 i( e2 g, x. nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% e4 E$ W' F, ]$ R) n7 N: d) QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 P; u1 n; N& ?0 n/ D; {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: h; B" t9 F$ L$ t
0x00, 0xFF); /* configure the clock for transmitter */
* K# W" r- [+ V p! {% E- sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 {5 e* R% q4 R q- ]; J$ c0 hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , R! {, I0 ]( M, g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) D% Y+ ?0 @ E; j1 q5 z0x00, 0xFF);
1 Z' J& h/ `% p
$ J9 ~0 L* W2 M! ~0 Z: h$ ^/* Enable synchronization of RX and TX sections */
7 A7 `5 R1 a/ cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
A* Q' R$ l. uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 g8 T: U1 a; E& K, x2 J- ?' GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. t- `9 [! ?0 s4 F
** Set the serializers, Currently only one serializer is set as$ n. [* q" t7 s, ~& b' A3 {. [6 u
** transmitter and one serializer as receiver.
6 |6 s' @% ]4 |, u: O*/
`) z5 P, e T; vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. r. x4 z- ~. p2 [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** L# c4 ]3 h$ j/ V: p
** Configure the McASP pins
' r+ u7 R7 K! G2 ?4 G" ^** Input - Frame Sync, Clock and Serializer Rx3 i% m! p' r+ S/ o9 a* h, l
** Output - Serializer Tx is connected to the input of the codec
8 ?% g( W+ Z+ ^$ v*/
" g+ N) W( Q0 ?/ Q0 @! @# RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 b& _0 K5 u2 |" k |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 c. a0 d+ n. ^! f! r) M" DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# F) P, z' {3 ^" U, K( i
| MCASP_PIN_ACLKX
3 Y4 v( Y) O6 q/ H| MCASP_PIN_AHCLKX
1 h. m; n# \1 z% C2 @7 L4 N3 O# F- v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 t6 Y( C8 K& [: D7 G# B/ k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # f, C' V) C8 ]
| MCASP_TX_CLKFAIL * X1 M0 N3 b& W( {. J7 k# s
| MCASP_TX_SYNCERROR
8 `( O* L- W. C) A6 v" `( M3 r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 u$ U [+ s# G9 ]9 k0 c$ t
| MCASP_RX_CLKFAIL+ o& u# l! z* Y4 x
| MCASP_RX_SYNCERROR 9 g7 B, m5 F; Z4 r, p& I& c M
| MCASP_RX_OVERRUN);0 A1 ]' \+ k* t G0 S; V! z; x/ A+ ?
} static void I2SDataTxRxActivate(void): c* y4 v2 `' Y- e3 W
{
! e0 W6 U% m! O3 s0 q* x7 E/* Start the clocks */
; C5 T( I' M6 b# r0 SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 e, m) N! r4 j* x5 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. W% D% [# f! N4 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 `( i" X8 }; L/ p, aEDMA3_TRIG_MODE_EVENT);
2 ^ C/ V% i, x4 ]$ N$ AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & ]1 L3 k8 o1 S( ]% c% T+ H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# z/ r8 M. h1 J: I" K3 Z2 t5 S7 s3 rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); @/ b) _) l) B8 j+ F& w1 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 S0 c3 x5 \2 {+ i. G: cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 k' ~ a; Q* ^4 c; e# M% xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 o! |* i+ |0 Z3 s2 t0 ]8 {) U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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