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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: o1 E" T: h9 E$ jinput mcasp_ahclkx,$ |/ C. ^) N. ?# j
input mcasp_aclkx,5 W1 q2 s8 {; h( y* [2 _7 K L
input axr0, f6 m+ S1 q& L1 G. _
: T, r6 s, M1 Woutput mcasp_afsr,
/ o- ]! c6 t# o, s+ Y: doutput mcasp_ahclkr,6 P5 E" b- U3 O! t
output mcasp_aclkr,( U4 O. U- @5 T3 y
output axr1,* U) S$ }! Z: S/ N% g J3 A
assign mcasp_afsr = mcasp_afsx;7 P' @& K; r; t0 j
assign mcasp_aclkr = mcasp_aclkx;
: Y! k c& L6 S& Jassign mcasp_ahclkr = mcasp_ahclkx;( i) k" m3 N+ t7 V, P9 L( ^
assign axr1 = axr0; ; n3 u x, C+ G
4 [# W8 S; R4 o. L, a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 w5 p' h" H# ]( z$ _6 v
static void McASPI2SConfigure(void)
7 S [/ I! g* ~& b& T, W{
' Q9 b' Q9 q$ R6 TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 R* \3 O& Y) R5 R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, \) z: v5 I6 ^* Q6 a7 A% rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: ^. M4 c& D) c" U7 ^. i9 R6 H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 y! h6 e: _1 b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& C- i) N1 h; i R# Z
MCASP_RX_MODE_DMA);
; V$ ?( D S- n0 A' w8 j1 o0 v# s% MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 x5 \3 \ | S4 \4 z1 X$ Q* h8 EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% u( P i, Y1 ~4 t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! a6 M# w0 M; I; A! | ^9 K# }7 L7 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 ~; S: o$ H8 z8 s8 SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & B! c* W$ x$ _; u/ b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ M2 s1 i; H! NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- @* @8 F% k9 Z# f# N, C7 z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 j4 u* [0 i; E1 f+ h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: x1 s( b$ @6 e1 a0x00, 0xFF); /* configure the clock for transmitter */6 I) P) o: k4 j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- C5 g7 q8 u4 x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 `/ L: [$ _5 F5 j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 k3 A6 `, {; B1 F K9 Y4 O6 T
0x00, 0xFF);) X. N {! X' [& L2 p
* X7 \) d" ~% Z& {3 H6 j
/* Enable synchronization of RX and TX sections */
, b$ c3 O+ c" C$ {. e. z; f; yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 Q/ k% D( `! m% [5 yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 w6 w% X7 Z: z/ N! k. Y' ]( jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, @& z! P; e: Z4 l5 y: y
** Set the serializers, Currently only one serializer is set as% K6 s% b( @+ d
** transmitter and one serializer as receiver.0 \" v( I9 c5 j7 g
*/
$ v: d$ `8 h. J, r( O/ F, UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. p. c3 S5 \# @" ^+ vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ M' Z/ M) M1 K |6 h/ | j1 d) r
** Configure the McASP pins
D6 f, A, j% f* @- K4 @** Input - Frame Sync, Clock and Serializer Rx& C% b; D; w: T8 K% l2 g1 E
** Output - Serializer Tx is connected to the input of the codec + R' ]9 v1 m9 U; H- y2 ]- F0 h+ B k
*/
H+ n0 }5 B" ]& LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( E5 m! `8 v' Z3 Z5 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 e8 k! k1 @, n f! FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# N; p# h/ h# i( u( r' q: d| MCASP_PIN_ACLKX9 C6 D* w7 I6 x4 @. Y+ X
| MCASP_PIN_AHCLKX$ A v0 f' T K+ H1 E( _# h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ a6 A7 V' K* d0 X! F4 e! {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: u; R, Y; T4 C- S7 P$ ^* d| MCASP_TX_CLKFAIL
8 ]" }* @" I; o9 }2 n2 W| MCASP_TX_SYNCERROR. E. w8 F3 y- ^4 Y4 t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 k9 g2 T7 Q7 h/ d; Y8 v# A| MCASP_RX_CLKFAIL
! L3 b! [- k+ _* u0 w| MCASP_RX_SYNCERROR
4 Z1 A1 O& ?" I) m# o| MCASP_RX_OVERRUN);* F/ a& ?0 g! {, k* T/ h: s
} static void I2SDataTxRxActivate(void)
) g- _" {! \# G4 e' n [{+ p7 Q3 S. L1 {) v2 L& _
/* Start the clocks */
" ?. h6 ]( z% \6 S7 O' C) EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 F* t8 v1 p8 O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 D7 W2 z. {1 c4 W6 e0 s$ u s1 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 k7 g& k' H7 Z8 [6 l
EDMA3_TRIG_MODE_EVENT);7 l9 O- z4 t X/ V+ R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - X: C7 r* U- \" a6 z+ g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ m) C$ C( e# v2 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" R' B) V& c0 X+ s; Y3 F" L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 I) h4 h$ n# @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 h8 O$ a9 D" _& p: E4 s6 r1 K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, H: p- Q' O1 ?) R- S3 o- o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# O- d7 i& j) t p% y
}
* `$ T8 p R G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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