MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
/ u4 c# w. w" c  X5 e3 N* q2 ]input axr0,
6 s( i; `# X/ I0 V; j. D) i% X
output mcasp_afsr,
output mcasp_ahclkr,
% J: m8 d' @& v1 v: |0 ooutput mcasp_aclkr,
9 r6 r% ~5 E. F% }! C0 a/ Xoutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
5 f+ S& r' G3 g" vassign mcasp_ahclkr = mcasp_ahclkx;
% A4 q8 h/ h' r6 b) zassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
* H0 H# j/ b. u" a: H! h{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 X+ Z2 ]4 h+ G$ [+ jMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
$ D% m( s- E' j& k5 d8 G# l& V0 k6 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! S  {  w# d+ V" ~4 {3 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. \' c' a6 f. k9 y7 d& T' y: S- _/ sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
. B4 n: w' y# |8 ^: JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ N/ U4 X9 W3 z' S# z0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 F, d5 @0 Q6 o3 E3 q: [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

! S5 ^2 f5 M. a# W$ W/* Enable synchronization of RX and TX sections */
4 R7 J4 Q, e. B6 {) tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% Y4 u! j2 z# q& G+ ?! @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
/ A8 T- w% _- R; z* }& W6 Y+ V** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 z$ M* x* w, z- h, dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
- p. {% C# d6 J6 t, ^0 O** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
1 ]4 }, @+ K( _*/
3 ]; H/ Y' p6 V4 u% p5 }( CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! M- R1 e) g7 G' w  X8 p8 L" d8 V) NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 T8 _* R! G' E/ P6 l4 |  y, z; H2 _| MCASP_PIN_ACLKX
5 Q9 P; Y8 g0 F6 N( S, U! X| MCASP_PIN_AHCLKX
1 i3 U- Q0 s' N5 C, s. v. i+ Q$ z9 i| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ X% K8 j5 r/ |: k2 @| MCASP_TX_CLKFAIL
' R$ H6 W  Q+ _6 C| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- E) D: e) l! E/ N2 B| MCASP_RX_CLKFAIL
8 r; B% g% d( J: }9 e! w| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& p6 K" s0 U. t5 lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
1 p3 ^' Z8 G/ `. Z' J" f# n5 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* p/ b* q; |4 O; x) V8 aEDMA3_TRIG_MODE_EVENT);
, I4 s' C& M0 u% P6 n' X: k4 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! w3 A/ J" s; dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
# @4 @2 |% q" k, a, }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
" u% ?5 b0 Z: ]. Z5 B9 Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
0 s% Y5 k8 `/ D/ G, h& KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ Z6 {) L( v# B0 R2 R3 ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% j5 ]; \# `# ?' o' y7 x; F  y}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.