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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 Z) y) [, ], s3 l$ q$ \. sinput mcasp_ahclkx,
# ~7 s9 [( U8 G9 Z3 }& Y3 `input mcasp_aclkx,' F) m* c' [' l: L8 d
input axr0,% n& }: |3 ~, k5 N8 p0 y
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output mcasp_afsr,
$ m) i B+ W; A8 ^! h8 B& U' joutput mcasp_ahclkr, Z. n, h) h p1 g/ R1 W( k
output mcasp_aclkr,9 ?7 {0 G- A2 Y3 \/ X$ j
output axr1,- C) X5 k+ L6 {/ T" w3 m
assign mcasp_afsr = mcasp_afsx;
8 r% i( \9 j: Rassign mcasp_aclkr = mcasp_aclkx;
$ e9 c4 o/ F' x# Q. ?1 G0 I( Dassign mcasp_ahclkr = mcasp_ahclkx;8 T5 Q& s9 n& W8 M4 J X4 t) f
assign axr1 = axr0;
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9 [" z, @& K7 ?5 C+ R1 R) u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . Y# e6 i% `/ R" d
static void McASPI2SConfigure(void)( h; }& P* y/ C0 X. r, R( x
{
" \. z" I% w6 R F o! L5 [. @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 d- s- N7 {" J9 ]: K: s/ |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. `& `- `/ q3 I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 `. v. g2 r0 b2 }) e9 u; Q' |1 IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: v5 L% F5 U6 d; |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& R8 _) X7 b. A+ k1 s2 D& JMCASP_RX_MODE_DMA);
2 s& p+ `5 s2 i1 x+ X1 @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 S4 @) v( B8 T. e9 aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 ]! s" n- C1 V& g7 {7 yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% X) h& y$ e, A5 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 t) h! u, R# |- U. h* Z6 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ o/ J) B+ G" GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 w: G, R9 L2 W. G- t( o- n0 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' R4 |& ~6 S8 u( J2 B# w8 k) d, x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " q F0 R! C9 v1 C) p0 t. B; z$ ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ L2 ^: R J. B0x00, 0xFF); /* configure the clock for transmitter */$ Z$ g4 M) I( r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 V0 l5 l8 T; i5 j7 h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( K% W5 |9 u/ \; N; G1 lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 ?$ M: T. P% c8 j( Z1 r0 L5 Q0x00, 0xFF);+ `) @7 m S) v2 @
( `# \) h; U8 u4 j4 c5 z* W/ e5 y. M5 z/* Enable synchronization of RX and TX sections */
0 U0 |4 }! p1 Z( ~; h F/ ^) oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 e6 b$ ~* x0 A0 p, C% DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 S5 C g" C1 D5 u% U2 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; a2 c+ b/ h5 P+ k' s** Set the serializers, Currently only one serializer is set as
6 Q8 ?$ t. N( Q2 [4 z9 x1 G5 L3 _** transmitter and one serializer as receiver.% l: T1 z3 l8 l4 h
*/
/ X3 V" M& S# Z5 F9 T- b$ r/ ` iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! z4 P1 R! F2 \" H. d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. V$ u0 W, V$ F2 ?7 A** Configure the McASP pins
# l/ z6 r; M* \' n4 Z$ U( C** Input - Frame Sync, Clock and Serializer Rx L3 }5 a8 ]% l c9 |: C/ X
** Output - Serializer Tx is connected to the input of the codec " p9 A) n4 \+ _6 L$ X: U3 A
*/" h; X3 K* F( B9 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
V& V. W5 C5 ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 v8 f1 N6 w7 H! ^! a7 h7 ?3 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ R5 J: a! w3 s% u0 F( w| MCASP_PIN_ACLKX) l+ B- V9 e A+ j# Q
| MCASP_PIN_AHCLKX0 j5 [) j( A* e2 ]$ |2 [$ e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, p! Y! y& [1 k' zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " L/ U5 p& q- L' E8 e) z& H# Z
| MCASP_TX_CLKFAIL $ L: N$ K& Q; T) n; u
| MCASP_TX_SYNCERROR
; v8 n3 x3 y; a: x! A; l9 i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 n V& k$ `. `2 t9 l| MCASP_RX_CLKFAIL- g W* ~2 v5 X$ c
| MCASP_RX_SYNCERROR 7 e& p5 Y, @0 I4 B
| MCASP_RX_OVERRUN);
K0 S5 ?' N' D/ o8 _5 w: ^, U7 e} static void I2SDataTxRxActivate(void)
7 {" ~; E, [) o{
! m$ j+ } K [7 `5 q5 I/* Start the clocks */+ ~" Q! x ^, e2 ]9 v% [; x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 u. W/ |! a6 T8 bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. {4 q! q* W7 e( _+ |) r* E$ ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) `7 F: z( }: z& |EDMA3_TRIG_MODE_EVENT);
, R3 W5 T/ b6 l9 C- S* W4 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 G9 k. k# o& _1 @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: H" |- U$ I+ ^. j& ?' M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 B2 w% B% b; h+ V; z& W7 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, }" H/ ^: S) T7 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; ^) Q& g! W& |, Z7 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 e5 S7 ~% \) X1 s0 b; n& sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 t) d8 R/ l ?8 _9 n, }; K! n
}
+ A) R- K) ?$ [; I( U5 a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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