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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 f* Z2 l3 O1 c( G8 v$ j" ?
input mcasp_ahclkx,4 m8 L: E8 m( K7 R, o8 U) T
input mcasp_aclkx,8 y B) u; J# |3 K1 V9 q+ A
input axr0,
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output mcasp_afsr,
( y/ N6 |) J; L$ K Xoutput mcasp_ahclkr,
! D) c, [; I8 X9 _- q$ {output mcasp_aclkr,
, V' o- e: P! G( g; Routput axr1, M& R) _ Z* h- A) }
assign mcasp_afsr = mcasp_afsx;0 O' A# S5 B3 x8 t7 B
assign mcasp_aclkr = mcasp_aclkx;5 a: c0 U" U& U1 T( E' |
assign mcasp_ahclkr = mcasp_ahclkx;# [* _0 s% g* N, D$ w, Z
assign axr1 = axr0; . K/ N7 j+ F" F9 H( U; v& |+ ] D9 V% H
* e* i9 B* o$ c4 \; c/ \( z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - K: Y. n% ~8 s# i2 c5 l
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 n$ |. w$ X) ?$ s0 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* \* ?5 O: U0 ]4 jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! x: h# m( @% [2 m2 {# a1 X9 {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" B5 U1 n% u. i3 LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' F3 e* c) w j: b( Q
MCASP_RX_MODE_DMA);0 j+ {- D! p2 g# s8 W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, T# C+ A- ^; M6 p" p5 H, H* }& F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& r. _4 J* G' ]' f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( ?4 \, G. V8 _2 O# F$ z4 L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 L5 e1 l2 c/ z% Q) A+ e' V+ U' c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
l& H2 _9 L$ R- P2 Z" r$ n1 Y9 p7 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. q7 g @4 C4 V5 |2 c8 U# wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" V; B* z7 v& @% {/ e% E, AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 z: y- W1 I# }- L$ w8 @) bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
W- L. \ c( ~: d0x00, 0xFF); /* configure the clock for transmitter */- l1 @ j, u. w- f% j+ ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 C' w0 l8 e' P6 z6 K6 aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 l+ P1 B. v/ p; nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& Q- K; ?% E) ]% \: {0x00, 0xFF);4 |3 O% i2 ?$ l+ X2 A* q* m( z% U8 _
0 Q3 Q+ d/ K1 Z' ~3 E/* Enable synchronization of RX and TX sections */
' K9 p O, K1 ~+ s% k$ YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. ?' h7 H: O- yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* n2 G# b/ p" J! oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) Z9 @" k/ t8 \** Set the serializers, Currently only one serializer is set as
3 |$ G/ `, U( B- r) Z8 O1 @: ^** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" G( H% ]9 a N3 O& U2 H4 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' @8 s/ u6 j6 ^3 ^$ B* M' [** Configure the McASP pins
9 \' }- F4 d b) p** Input - Frame Sync, Clock and Serializer Rx4 V7 Q! Y* s/ i3 m( \/ C v
** Output - Serializer Tx is connected to the input of the codec - @4 T% Q6 a5 \( \: n1 C2 Y1 K$ A( S$ l
*/
7 q* Z% ^$ Y/ o$ A+ z' R5 pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 ~7 c- M7 z/ Z" d( b9 O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 C4 X9 R# C; ?1 g/ T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 z3 ?) E; Y' H0 U5 T5 Z| MCASP_PIN_ACLKX# S' ~4 O+ s X9 i6 t! r
| MCASP_PIN_AHCLKX
7 D. M* A, i' d5 n+ k, Z7 K# v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' ~) m; k" t# f- s5 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 B5 E* K4 C! ` Q# ~7 U3 K| MCASP_TX_CLKFAIL : G9 K' |3 _; m
| MCASP_TX_SYNCERROR0 Z$ G. x/ _% l" @: y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; B3 L+ ~4 B( q, H# V. K p# o& e| MCASP_RX_CLKFAIL" O, c( w; U* ^$ _/ d( W; D
| MCASP_RX_SYNCERROR % Y% f2 t7 C: U
| MCASP_RX_OVERRUN);9 B, Q0 e# K1 I9 Z/ y* k
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */1 b- V: O3 b' r w0 f: N$ r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 C( H. B4 z9 b x7 s" T& _9 v. |. |( p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 q: G+ x$ x# s8 l3 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# e; L; a4 c6 R0 i3 J3 lEDMA3_TRIG_MODE_EVENT);" o! _; H' {% { g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 W7 y6 w d% U6 R" S. [& t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& y- O0 j7 D+ K3 w, G% o- s( B' Y4 u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 Q9 P2 u7 P+ w W) A1 c; w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- B' }% A( ^1 T* R: o8 W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" E' L2 K$ M. j( _+ _0 D; h$ bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 h& U1 B6 k( `1 i3 n5 XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
]0 C( w6 r% L5 Y3 k! J}
; A5 t+ }, P5 q/ ~* r1 Z: ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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