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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) O: S4 z# K- A5 U5 z& a5 B6 B0 S
input mcasp_ahclkx,
& g8 L9 B$ J1 k# tinput mcasp_aclkx,$ D. S, m; Y: G
input axr0,
" p# V/ Y# R, \2 x& R# l% D
' W9 x" W2 I: \! @8 Noutput mcasp_afsr,
% T$ n: b4 R; c- noutput mcasp_ahclkr,0 z5 P3 H# Q' l6 J4 Q; i, |7 {
output mcasp_aclkr," E% z( l& a+ S4 z4 ^1 u
output axr1,
0 L' r, N4 r( u assign mcasp_afsr = mcasp_afsx; G+ [: P. C9 i! Q7 e# D) j3 N- X
assign mcasp_aclkr = mcasp_aclkx;
- y* j: r3 U$ U! S `2 G% {assign mcasp_ahclkr = mcasp_ahclkx; F% `* d2 C7 c( `( S$ @6 _( h
assign axr1 = axr0; " a) {' O& I1 p; h
) u+ W! }( [* `- [ `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- ?& m2 c" I0 j' ustatic void McASPI2SConfigure(void)
5 ?- z, I/ w' ]# g' j7 d3 s{% k* w1 P3 [: h6 m: g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 \, X! M: d% P* f o; W% | t+ k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 z. w5 B) q$ s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); k9 M4 A) E3 r h t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- i( I& o" @. c1 F% M% S; sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) W5 h+ n& `8 Z1 W+ I
MCASP_RX_MODE_DMA);
3 K" g& o9 I7 |5 \/ f* kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. O2 t z: r* r; ^& W rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% J, P/ e2 r j+ ?" u d1 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, Y! w6 P. Q+ I* ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' J& `$ e9 p- ?# [' H$ f7 HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
d5 @3 e7 b3 Z) ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; s6 E9 K0 X. H( `' K/ o1 q+ }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) V0 {: o7 i, A' J; XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ ]/ ^: V& k( N" p6 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* \: M! d% t2 A/ [& }0x00, 0xFF); /* configure the clock for transmitter */
3 J$ u9 Q! T$ \7 e4 `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 u& `! w* Z9 _: z9 W8 C1 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * |) t4 Q2 K' c' `$ I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; p, i. r* L6 h% P: R' W' s0x00, 0xFF);1 i6 D' H+ f6 r7 D
! O+ ~) S: e/ ~% I2 ~$ w/* Enable synchronization of RX and TX sections */ % N: l/ W X$ i5 D$ I4 B3 S+ |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( e' s6 a; t' X: f) ~/ y o$ |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 @ N/ d% v) {' V Z' P% \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: v" Q+ H# M6 P, Y
** Set the serializers, Currently only one serializer is set as4 L' V" }6 f9 g
** transmitter and one serializer as receiver.
: w& ]& i& @+ E9 @* L*/
* _. A0 g8 L3 i7 kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; k8 }) y7 s1 C* ]$ H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 q8 K5 g, u: o* Z* s% \** Configure the McASP pins 3 l% D+ p% q8 z. s2 e9 w5 L
** Input - Frame Sync, Clock and Serializer Rx# B4 z: F, a2 ^2 X- ?4 [( e
** Output - Serializer Tx is connected to the input of the codec - m, k& m/ M# W, K: c0 b8 f& q
*/
/ c7 \% f( }0 f7 ]* MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# }. L+ G. f# y6 \1 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( `( y% O1 T3 K& H& Q" X8 W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ J1 A$ x( i9 n! T2 h( _# \
| MCASP_PIN_ACLKX) K, H6 z0 m+ X4 L x
| MCASP_PIN_AHCLKX
- y: ?4 H% k+ g% ^' D9 o; j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ H& i' a ?+ G. S# k5 kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 y9 e5 q4 T4 H$ G* c/ t2 D: F| MCASP_TX_CLKFAIL
/ X+ ?4 t, v9 a8 _/ o! R4 J| MCASP_TX_SYNCERROR
. M# Q l: C- _$ w$ R7 T9 B- E6 k- F7 `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . `+ E, P9 u& [. I+ O
| MCASP_RX_CLKFAIL' w' J1 D. U W/ u( c
| MCASP_RX_SYNCERROR
4 z' _/ O2 C7 t5 i| MCASP_RX_OVERRUN);' I; `# ?' K7 h( W* O
} static void I2SDataTxRxActivate(void); I) ~; g) R% B, ~( ?
{, V; R5 r# \9 N( `3 N
/* Start the clocks */
c# Y- v4 R3 x9 o2 h) C. I fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 O( A7 }, m0 Z& g kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. T/ Y! j4 U+ ]: }* u4 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 E/ B7 q+ a2 k, F
EDMA3_TRIG_MODE_EVENT);
: Q6 h$ x* X, jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 O b# s9 u" r6 m: u- `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& r5 f: ^) ^) a i9 ^5 ?7 D7 \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) Y7 V4 O5 ~8 o( c2 X& IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% k K# Z8 W' V5 H8 A; Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. m- q9 E: |/ v2 C. h/ S( oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 c3 V" L9 h; _ ^( g0 q2 I/ B( K; b2 ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 W2 T5 p+ r2 K
}
8 r% i5 ?% f: I" J/ B" H, h+ M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & G( C3 Q7 e5 Z4 m \! F: \8 P2 c
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