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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% {7 [; M) H0 T( W; hinput mcasp_ahclkx,! u7 r1 p# x$ ?( g& u7 V2 q+ g
input mcasp_aclkx,
" G" U% |) `! E; yinput axr0,
) t; T: D; J: t$ v) N2 ]- G4 k' Z! r
) m5 @" w% }2 ^' C( X4 F, H" goutput mcasp_afsr,: e- Z. G) ]( Z. s" g! k6 h
output mcasp_ahclkr,
& ^: ]) d. i+ _5 koutput mcasp_aclkr,
k- [5 ^: T3 a" ~ houtput axr1,7 |# a: A# k+ S- W& d) U
assign mcasp_afsr = mcasp_afsx;
% Q$ b2 m8 A) y) _; w z8 r% wassign mcasp_aclkr = mcasp_aclkx;
9 F" U4 p! p* Aassign mcasp_ahclkr = mcasp_ahclkx;6 B0 X- t( d" O' d0 s/ \. U4 q
assign axr1 = axr0; 7 P$ g! o ~1 F9 C" M) N
6 h/ P- c3 p" L7 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( }2 V2 m3 e' x N0 E1 @* Z& y+ ystatic void McASPI2SConfigure(void)0 }7 a* r# o; h7 B! u& Q
{
* |: n9 H7 D) _1 [: fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. O) W* H- E/ a6 W5 V: w6 i6 aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 X+ q6 W8 G' ?: H) D hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, |$ ^% E: o, b' k6 e* t; f; a y0 f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 L& o. }8 r; H& o$ t$ C' `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 ~) E; t4 i) X6 E# n0 |
MCASP_RX_MODE_DMA);
" q5 H9 c& t& X) VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 `" Q N3 `2 ?9 K2 X/ w- mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# b7 D; G& C: [/ h" a; C- mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 v3 q1 u: b, \4 R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: }# _* [! X) r$ V9 C" {! yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; F; e5 T4 i. A, p3 qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: C, m1 |. j$ R3 N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 c& U5 ^0 Z/ M# C$ l" z; Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 |* D q) s8 q# i* d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 S' k( M/ G: P& h0 p: X
0x00, 0xFF); /* configure the clock for transmitter */5 J0 l1 H0 d- H! v7 E' w2 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ F2 z9 r& Y/ S+ \ K6 u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 X+ d2 f" r+ P! B! u0 z4 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 \$ j: [* i3 P1 v
0x00, 0xFF);" H* T. e& }0 |! J; Y$ B. @
" n" O! Q, A" Q" {3 H" }8 u) B/ q
/* Enable synchronization of RX and TX sections */
+ M+ q+ |: o1 |9 Y3 GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" h" W& M* u) E0 | H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& L( @7 B: O9 h! J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 V9 z* z0 {- z7 z, G' C+ X, ~** Set the serializers, Currently only one serializer is set as2 H$ X& _; [9 k- J
** transmitter and one serializer as receiver.
! J& n/ c8 m% I6 B& Z*/
5 Q/ {, J2 k6 W& W8 P6 pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 z0 L/ J; M. R. m: iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% W$ i$ I+ Y: c! A, z: J% \
** Configure the McASP pins
- C0 v& Q6 Q" G" _1 @& M5 q** Input - Frame Sync, Clock and Serializer Rx/ N& B1 i& M( c
** Output - Serializer Tx is connected to the input of the codec
1 I+ H3 C) {* ^ v( [*/0 A0 B; I# \- q4 P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- \( G! B# B; w# s6 f6 H& x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 m) d) w- U& [6 p/ yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! {) b9 a( q* t: U# N# v| MCASP_PIN_ACLKX
7 |+ N' D4 l! d8 Z1 g+ {. A| MCASP_PIN_AHCLKX
. a8 E! Z' N1 m' ?# D/ F( p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 e4 ]2 h3 A/ l- K! [3 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- ]* U% ~( s# X3 a1 V: a" D| MCASP_TX_CLKFAIL * x; P8 W' _+ @* s# P% f
| MCASP_TX_SYNCERROR
# u" d" r3 @+ E+ }3 {- t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 b. z. d H; u| MCASP_RX_CLKFAIL
5 a3 K f v% O0 z* ]& k( R| MCASP_RX_SYNCERROR
6 Y1 a8 ]$ G" K" _" o9 i| MCASP_RX_OVERRUN);$ [8 T- e9 }* P+ a; q% `
} static void I2SDataTxRxActivate(void)
: {% l, I5 B3 j* @3 \- Z{1 X$ y* h/ {, q. E" f' Y: A* B2 }
/* Start the clocks *// S( h; z: R/ u. K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; Y! N/ O4 D, }5 [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: G% g% p7 p- D! G% s+ ~8 g6 Z; XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* C4 F3 z$ M% k. e/ Z/ B
EDMA3_TRIG_MODE_EVENT);4 C' J. D1 S; c7 |1 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 h8 v, A' m1 G8 [& OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( x; a" v% x5 j: HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) B1 x4 X( N( V- z2 q0 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 R& ^; F" N! y: D9 `, \; ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' E6 T. V3 Q) @+ _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 k9 K, q$ |1 C; XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" U7 ^' Q' C$ ]0 J8 y- z} 9 ]2 H' w% ]& k+ ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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