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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ J: ?5 ^7 `' G4 E0 i& Linput mcasp_ahclkx,
/ }: f# h( z0 G) G( U$ O$ d tinput mcasp_aclkx,3 b) T: T) y" R# l
input axr0,1 }1 B9 R6 j( B( i6 e5 B
* F6 L* ?7 F5 _6 h, l
output mcasp_afsr,; G& I; }% s' h p& d+ o, D# z
output mcasp_ahclkr,* Z. [* @. H3 S; C! o' T
output mcasp_aclkr,
. k. x9 u' Y3 F* @! c" T: d9 D, @& Koutput axr1,. {# S: f, f# v) ~
assign mcasp_afsr = mcasp_afsx;
7 H6 h* z6 Q9 Q3 I/ H# {assign mcasp_aclkr = mcasp_aclkx;
+ T1 E, [" X( P. b2 H# f2 ~6 |assign mcasp_ahclkr = mcasp_ahclkx;
* {9 g( N, D' Cassign axr1 = axr0;
. D5 T* e2 f: r2 G/ E
& P4 L! p' k* m! m2 R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 t& a/ o; I& w/ r2 V% m) W
static void McASPI2SConfigure(void)0 A0 u% D8 |6 U# N- ^0 E
{
( C' o" S. v2 X0 c; g9 ~2 qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( T/ H3 |/ u7 S* B. dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 H$ X6 N: w6 ?9 a; sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' B- \" J$ D# r" `2 ]" d8 t; A# n! kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* m% p, g- N% E Q$ s1 E4 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, X- ]( I5 h: q5 E& Y, I
MCASP_RX_MODE_DMA);& W: w; ^& a T" ?5 c$ c/ C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- C# a/ ?, k6 K# ^1 a8 c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. s0 M0 W, y" M- {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, u1 n. b0 a2 Y7 ~! s8 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 \8 o; u; e* E0 }1 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 t) c% H$ C8 f JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' M# ~8 q% k; g2 I1 vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 m1 k; p A6 b" t2 j7 r& ]+ qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 V+ c: P: [: E0 eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 E8 z" ~: E [9 l$ [, F
0x00, 0xFF); /* configure the clock for transmitter */
" c, Y2 K7 Y# K, a: ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' p9 h* n2 @2 k& _) K T/ }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 A% o8 @$ p$ a3 y) q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, @& D B) w- E; G7 S
0x00, 0xFF);$ I# T+ ^; O7 R* |
: ^) G& x8 r: ^, D$ _/* Enable synchronization of RX and TX sections */ : U6 |$ m% z' y" l8 _, {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
?) L0 R8 X$ a+ x& z$ _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 L% Q. \' T: [3 I' |$ z2 A, _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" {+ P! U% z5 |% Q5 E+ N* s+ }
** Set the serializers, Currently only one serializer is set as
2 w& k* G5 M& k- P* Q" D** transmitter and one serializer as receiver.$ R' L! _4 X) K/ y* O
*/0 C- D7 Z5 R8 u( q! r# d9 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- ^$ f$ C3 J, K- n" vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ X8 { q W& e m" l; D** Configure the McASP pins m$ t% _' y F( _- }
** Input - Frame Sync, Clock and Serializer Rx% ^# A1 j& G2 _" C. H* g$ z
** Output - Serializer Tx is connected to the input of the codec 4 }" l4 }+ @, |' X$ P2 m& `9 G
*/
4 ]# X2 k7 o9 ~: g, v1 {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 s9 g( M" y1 I1 U8 [8 |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ _' L" p8 F6 C) R* T+ [+ M3 hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 r R, v; r6 Y5 B# d! P| MCASP_PIN_ACLKX
. w3 a% d8 d! |5 i5 v7 V/ m| MCASP_PIN_AHCLKX
/ }: O: G( q1 O: S( o& i/ B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) p& P* B5 W% B, Z' C9 U4 X) sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ R; }+ `7 [5 x ~# f' ^' H| MCASP_TX_CLKFAIL " e* |, M! X1 v8 ^2 d5 P
| MCASP_TX_SYNCERROR
" @1 C0 m# C- V& E1 M& [' Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ s: b' q; |, [: e1 f# @/ L- @- [| MCASP_RX_CLKFAIL* B* {9 m# l+ {5 J
| MCASP_RX_SYNCERROR 2 g* a$ i; O; L k
| MCASP_RX_OVERRUN);
3 Q0 y$ S3 b- T" v} static void I2SDataTxRxActivate(void) H; y0 X/ ?$ m: l% `
{
! H6 \; X. U& k1 V a/* Start the clocks */
' {) ?# Z. v+ |/ J9 Z1 w& K, HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' H5 l: z% C& s0 o* o- }7 E! i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' c* y, c& Z" ] `7 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; {% ~/ Q" g( X2 _: T- |- r. \
EDMA3_TRIG_MODE_EVENT);
' i6 R" n0 ? w3 D; ^! s8 k6 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - O( R1 u/ E. w) `; N3 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) ^$ M. u% U2 xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. W8 n- b: A; a: X9 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 T$ D8 a( f8 x0 _% ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# S9 g! @3 V9 D" [7 N. o. v% G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ ^+ ~+ N0 G8 p7 dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 |0 B7 r. q) M$ k} & g( Q& N/ @3 C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 P u" ?0 W- ]9 l
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