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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 ^7 P* _. @- @, e; H0 w% Finput mcasp_ahclkx,
6 Z* q9 s# E7 @0 K3 Xinput mcasp_aclkx,; W' I+ O4 @9 C3 E: M
input axr0,9 _+ Y. |2 @! y8 C2 K8 b
5 i& a1 r- w7 toutput mcasp_afsr,1 S5 w; B2 M. m$ }: u) C
output mcasp_ahclkr,
9 Y- V7 a6 L1 ]" i! doutput mcasp_aclkr,5 [* O3 |# ?7 s/ A5 G/ y$ P
output axr1,
1 [, z+ \& W5 E" r. A( q8 q assign mcasp_afsr = mcasp_afsx;
" n1 r9 I6 r6 s* ^2 M5 v9 |assign mcasp_aclkr = mcasp_aclkx;( f* K" A/ o. b! I& Z! K M
assign mcasp_ahclkr = mcasp_ahclkx;
+ G0 X6 @/ V7 Dassign axr1 = axr0; ! s- ~" G0 _/ K: U5 V1 G
3 W- F/ u0 P0 p0 J1 C' K. P( J5 g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) m2 t5 ]8 |9 K, Fstatic void McASPI2SConfigure(void)
/ ]: q1 p7 X; g: H: |3 x3 ~- M5 W{
2 q, R- x a7 ^; I& E2 LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, F& d$ c% a$ w; U& [/ a; UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 W) a4 W$ V/ G8 D3 Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! j( ~% a1 Q8 Y( h6 c( fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 b7 d2 j. e) kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: q. l( _5 Z4 y5 z" O
MCASP_RX_MODE_DMA);
5 l) l* J" D# w3 w: z5 gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% C( Z n1 J6 k0 }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 L/ y- w5 ] Y0 C# I. z) PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 H: n7 J- E1 I3 L6 l1 _. Z9 YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. g) s9 j/ K* P% x% X" G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # z0 l: m, J$ H8 D/ b7 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 a! c6 Q( O5 W, e* fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- d5 U- ~! ~- T0 kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 F0 l' T1 H: Z$ [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: i7 P' q9 v9 e2 o: j3 l: p
0x00, 0xFF); /* configure the clock for transmitter */; D$ R/ C) W5 {; Y: E% e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& p: S0 |8 ?. c7 b) {2 n" `' k; V) ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); O7 D: j$ E8 h9 M: Y7 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, @7 \7 r% P, C2 v: n$ x" t
0x00, 0xFF);
" p2 v+ ^. v8 v, c7 @
4 a! S( }( K; o/* Enable synchronization of RX and TX sections */
# p5 j" y: e& vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% _" G' R) |8 u0 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: j J& ]/ n) q: C# [. r6 M pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 d O( X( y8 J7 m; G
** Set the serializers, Currently only one serializer is set as
$ O5 i g+ O3 M9 P** transmitter and one serializer as receiver.8 P) l: `7 t; [7 ~
*/: T2 ~% y/ P/ @8 H' F9 H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" X! R8 S0 B2 {( b+ E. Q8 |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 f/ F3 S2 T% T* {$ m5 S7 X# u, ~
** Configure the McASP pins & k2 c) V; I( o Y' Y K, @% t
** Input - Frame Sync, Clock and Serializer Rx% h1 F4 b W! p* h; @5 M
** Output - Serializer Tx is connected to the input of the codec
3 E3 w+ `1 y: Q+ c% c0 q- V*/* Z0 N) y; }5 ]0 w! l8 E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( u: }2 F' ^8 Z; p; o" QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) l! J3 v% z' ]( K. ^$ _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% f* M6 Q( |! l" }( T1 [
| MCASP_PIN_ACLKX
1 ?" w+ ~; w% b/ U| MCASP_PIN_AHCLKX/ x2 L7 l6 ^: d6 f2 ?# E, @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ {% j, J* t4 I/ t5 r- r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 Y+ l. o6 M# R. g5 U9 D| MCASP_TX_CLKFAIL * ^* ?; g" ?; O ]# U
| MCASP_TX_SYNCERROR
5 y0 w' N* y5 x. B+ i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; V+ m! H8 V. A- o# u
| MCASP_RX_CLKFAIL) I/ G; d+ `# [& e5 i% F8 T: B
| MCASP_RX_SYNCERROR ; F; O m! Q% A' g* [( j- L
| MCASP_RX_OVERRUN);/ D) e" o }& r% w J3 `
} static void I2SDataTxRxActivate(void)
* c$ V$ N& U+ v' q) H+ u" h4 A3 ?) p{6 q3 c r8 n: J" |7 i
/* Start the clocks */. W" z/ w' G/ Z1 U. D) m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" L/ y: y5 S( b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- X$ ?. ]( w8 K2 ~- a' J# KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 A7 F6 j8 _- E+ @
EDMA3_TRIG_MODE_EVENT);( t8 _3 j$ G& c+ h) D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, G' G; L+ s9 \/ U1 _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- o! d1 x" {- L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ P& Z b$ ]: |* n7 K% H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
r0 \, z- C! ~$ v- Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" u$ f3 p* i cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 p! R9 I1 x: y2 k+ b xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS); w9 O+ D6 F4 G2 a- ~* n, s
}
! C" V/ C3 ~5 k! y4 R V1 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : f! k* {; T4 q% v5 \
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