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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ B- n# W3 ^0 ?4 Z0 D8 }$ O. `, {input mcasp_ahclkx,5 y; X [8 e) ~ W. ^8 t
input mcasp_aclkx,
. [, {/ I; Z8 ^( p! z4 Pinput axr0,
a/ a. @& A" r0 D( Z
$ i" P% @: I! [* |: \& |: Ooutput mcasp_afsr,3 G; k P5 X$ v( Q# y5 ?
output mcasp_ahclkr,
3 S+ l4 `( ~ x" ?output mcasp_aclkr,4 V+ J7 h9 n& V5 X) O
output axr1,% w; \9 i' J. S- N2 o* h5 [2 r/ v
assign mcasp_afsr = mcasp_afsx;
3 j$ L% K: T+ y0 T. qassign mcasp_aclkr = mcasp_aclkx;1 @6 W6 _3 @8 e' b8 J% v F+ X9 H
assign mcasp_ahclkr = mcasp_ahclkx;
( Q: }- J5 a3 _1 R2 o; i5 v& nassign axr1 = axr0; : h( @$ v3 q. T" @6 _
9 V1 z" g0 y8 O4 {4 E8 T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) Z1 ^9 X9 T6 l: d+ F" Pstatic void McASPI2SConfigure(void)
; I- N& a+ C! P' ]3 j7 ]{
3 s/ d. B+ w: W2 C- S0 H8 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( W" Q L1 e: H2 V, ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# n1 t6 `! V! ~) K) s4 {$ yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 u1 ]" q! C% S$ v( F9 jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ j' Q3 G1 P6 Y, f3 |; uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 H( e' W# m8 h- ~! B7 _0 ]
MCASP_RX_MODE_DMA);9 }7 p* X1 q- _* M1 A4 {9 }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* p. f j: d- w2 B4 ~$ HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* v: _" G. n6 `9 K" g) J. K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 g$ e7 T$ a! ~ O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. `& D E! n1 D. J: m% i k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, v# W! k2 h j% G2 M: cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 w4 F' v. ]. {- \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ o' m6 a" h/ O( u- D. h. ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # v+ O* y6 n) h& Z' G( \. s# u4 N' {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 v! }8 u1 J4 M7 O0x00, 0xFF); /* configure the clock for transmitter */
% t# U9 L; F1 [1 [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; _' U: N4 V6 g, VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 S7 K" u! \1 w8 n, D6 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," w( j1 A/ n6 ?6 J, c
0x00, 0xFF);# N9 E$ E: S6 f k: n- [, R/ \
2 c1 e3 J: I( o2 p8 z/* Enable synchronization of RX and TX sections */
" k/ F) ^7 G# r# sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 S5 C+ `6 L1 R7 `% @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: i9 i5 g! u; o j6 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! f4 B4 y8 C1 R% `" Z
** Set the serializers, Currently only one serializer is set as# ^. `8 l- [& G1 Z
** transmitter and one serializer as receiver.7 w, ^8 J. u2 ~% i/ ]
*/1 b7 f8 s5 }2 S7 _1 X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; g Q8 X0 V* U2 }) W! c$ D7 o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; [5 F4 k+ v% r$ A, d
** Configure the McASP pins
- @1 I/ v( N/ M8 r$ q9 c- v** Input - Frame Sync, Clock and Serializer Rx0 ?; e R$ {# A% I( D8 ~
** Output - Serializer Tx is connected to the input of the codec 4 E% Y, u* [* S @
*/3 f9 A! ^: O: q6 P% @9 P* Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! |) [4 c* L0 T8 FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 |5 S+ r& B2 I$ L$ YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 r: ~* q! H% R) V8 {' g. ~
| MCASP_PIN_ACLKX
# e4 ?4 `& D) G" ^( v o| MCASP_PIN_AHCLKX
- v" W% S' Q5 X& S7 O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// q8 L. L) D+ ?7 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * B" k. p- o2 T% J) G- x$ I w# T
| MCASP_TX_CLKFAIL
- E5 l2 r& b' ~7 T6 A| MCASP_TX_SYNCERROR. O# l2 Z- I9 a& M0 A4 Z1 u9 c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) l% u, p: [2 ?' g3 N
| MCASP_RX_CLKFAIL
' g5 y$ U7 o4 u$ N) h| MCASP_RX_SYNCERROR
& S. S' B+ o4 {( X* p/ o6 j) Z| MCASP_RX_OVERRUN);
: x; c% l# |& [! G+ F0 `} static void I2SDataTxRxActivate(void)
2 a1 U! N- `8 D# x2 d8 `{5 L2 P, ^! m5 }- g: L- q
/* Start the clocks */
! R- ^* k5 V) [0 |" T' uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 M h& [1 R- C `$ ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# c+ s/ L [/ ^( K( M4 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 @- i8 J* ~; s4 g: T% J
EDMA3_TRIG_MODE_EVENT);6 a+ ^: s3 H z. F! W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 b' F$ T8 j# `; {- {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ b5 p# m* k% V' ~. `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 u# X% h X8 V/ q! G! N p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// M( y' k* v! _$ [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 k7 ^% ?1 X ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ x/ G: ~+ @- \) H7 g1 Z/ Z$ O1 x& DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; ]* v) L6 a9 [; V
} 4 T9 r, F: ? t% J# M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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