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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; q5 K7 \( {+ }, h8 G) K3 Tinput mcasp_ahclkx,
, H+ J6 ~* X. [- X, Uinput mcasp_aclkx,
) R- v @4 q7 c& O; Pinput axr0,& b) F) w" I8 j. U; R
" j# i4 [7 j1 ^9 [( Q: u
output mcasp_afsr,& U3 B6 i+ a+ g9 @3 C
output mcasp_ahclkr," ^8 Y6 H0 ^0 H0 ~$ h, Z
output mcasp_aclkr,
3 M$ O* M0 X I+ V# e5 z. noutput axr1,
; q1 F; o. z" h. ~ assign mcasp_afsr = mcasp_afsx;
7 `6 B: ?" @+ t Xassign mcasp_aclkr = mcasp_aclkx;! b& t6 A, y8 c5 @/ V% R
assign mcasp_ahclkr = mcasp_ahclkx;* T1 D" ?7 k5 Z
assign axr1 = axr0; + c3 C3 G8 J" a6 K' U! U! ? O
- x$ }# E8 L" b- D' _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 \9 Y4 f# S( J6 b7 N- x H- r; rstatic void McASPI2SConfigure(void)
/ d1 S7 X0 x: e0 S{
( K% O# c/ K9 Q' uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 o B z3 {5 H4 KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ e4 H4 y* b/ |; b. HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' l7 H1 g% ?8 o) cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) \" r7 K _ ]! I; Z( L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" ?# I9 K9 v/ f/ W A8 r' uMCASP_RX_MODE_DMA);2 [) \8 Z/ D9 ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. E; J* H. i* b' o* c- eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# g# b: Q' k# I2 w% \9 [0 ?( dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& v$ j' f; b, WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! Y# {* f1 y* T# s# u- v) gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( x" z3 h/ C$ u: T, lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* n/ p; }: X1 O9 j8 g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 L, ^+ F: r, j' }. P" k l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ y" `! n0 Y& v, g8 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 p; v# Z# V3 Q) r5 T9 g; h/ ?$ n% {1 x# v0x00, 0xFF); /* configure the clock for transmitter */
8 W8 h( l- x% r7 m7 L$ l7 ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, _3 w2 X: a6 a) fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' y' B1 C+ P* u& e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! Z# |9 X/ Y6 p2 ?" ?
0x00, 0xFF);
- v' f1 D9 B9 S; Q1 e: I4 ^# X& ` b% B: d }0 B8 a# {
/* Enable synchronization of RX and TX sections */
9 G! ^" N4 ~0 O$ i- KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! c! F- G. `5 c" ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ c$ Z2 V( Y2 Z" d v" }% w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 |5 F: G8 t$ g* q& I7 s** Set the serializers, Currently only one serializer is set as2 F6 n8 c9 P0 h: L+ L
** transmitter and one serializer as receiver.
2 A- `) T" I& k/ A `3 J _/ g+ q*/
o( \( M2 L# |. `) HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& G( }( @4 t8 ?/ Y k6 e6 W( B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 n7 q: h$ l$ a* k6 o** Configure the McASP pins ! ~) i/ ]. b+ B1 y9 a( J, e/ |
** Input - Frame Sync, Clock and Serializer Rx
: U _3 ]. s5 U** Output - Serializer Tx is connected to the input of the codec
0 @! n7 J+ B1 A- w6 d" s5 o*/% o9 H m- _% v" Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 x/ J0 _# c, m9 x) s; r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); O- g& k5 S6 H: V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ J7 J% g+ Q; O$ q6 w. K1 R| MCASP_PIN_ACLKX$ ?3 U9 {( t M1 p0 z4 I
| MCASP_PIN_AHCLKX3 l- ?7 y8 r# M* X2 J2 N- y+ E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 Y9 s9 K* H8 o, g; @: l" H; @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& C0 r: t7 @1 `| MCASP_TX_CLKFAIL - d$ t4 Q: J3 N0 V4 p$ e/ N+ V i
| MCASP_TX_SYNCERROR
+ W0 q$ v& {5 F/ s% N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 x4 B; P# w1 c! _% R& ]+ w7 z| MCASP_RX_CLKFAIL y* [6 R/ w* P
| MCASP_RX_SYNCERROR
% u* J1 M) ?/ h9 y, Y$ r) N| MCASP_RX_OVERRUN); [/ r- }" O% A1 ]4 d2 @! I
} static void I2SDataTxRxActivate(void)2 A* L) l8 o% v3 e+ M p
{
9 T) _- R. c% T5 Q5 e4 ~/* Start the clocks */
6 A' x! \8 h2 _$ |3 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# ^) i, X1 L0 i/ T5 X) w* X% YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! I% u5 Q3 a; V M1 L4 H; ?2 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, u1 P6 w4 f8 q# c# [. q! p. V1 `EDMA3_TRIG_MODE_EVENT);, |- x# |$ w# g' x* {3 u; j& G; S2 G; ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, p! N1 n5 R* o* e+ Q# ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. F/ M# C. F$ z& h: X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ _- l0 Q5 \* n+ zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 r3 k4 j" m l( N e. w9 gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// B$ \& r4 q# R5 x4 T3 d& Y# Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 e+ ?# L: N8 r1 X, e' W: l+ XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 L0 e( M9 c4 |* I+ F' U} 8 h8 V( }( w. x7 B0 w0 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' x3 a2 a# o3 j. ^( b2 g5 B
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