|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 H- A' E0 r3 w4 t( s' Ginput mcasp_ahclkx,
8 y: _% C0 c5 R, pinput mcasp_aclkx,
F" B+ m5 {4 }# a8 ` ?input axr0,
5 \8 @+ W: l2 o& \* a) C$ _8 o/ v+ D) b0 e) y% o
output mcasp_afsr,
7 R0 s# y& }+ p+ J- s7 s) `output mcasp_ahclkr,
6 K. i& C) h! boutput mcasp_aclkr,, p7 n; R, Y( D" W: j# z% Y
output axr1,5 q! v' X' I* l# K" W; g
assign mcasp_afsr = mcasp_afsx;+ D* x1 Y: }; \% x2 r1 d2 W
assign mcasp_aclkr = mcasp_aclkx;/ A/ |) C/ u% v5 \% B
assign mcasp_ahclkr = mcasp_ahclkx;
6 [9 e7 n n- k, q' \6 u6 |assign axr1 = axr0; ; m# o8 {! V9 o/ o% [) t7 J* u( F) y
. i% ~% J& x; C" j$ z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 `2 G2 f2 j# J( }' u; g$ d* [static void McASPI2SConfigure(void)' w, Y7 Q' U" k, g
{
% ^5 ^+ p& g! D+ H' o& c. N* Q0 F" ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' ~9 c! {* ?* j5 UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ h+ m+ W( L; ]$ lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 G9 C$ U: l* m3 \& T7 X0 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 m7 d. Z; H: k- v/ }( ?) sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' g0 v( {, x9 ~& N* w
MCASP_RX_MODE_DMA);" M5 Z9 R/ Q% u3 [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 z4 f7 N7 ~/ z4 P6 T" j+ x: R& N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" o' J1 d1 ?% N W/ \/ r2 P: gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# L9 x2 }6 T; D7 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 f p* f1 @3 e: Y6 B: y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # @# p& F% ~! K7 ]' h6 i8 I F; f3 }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' d* N; _# E/ n6 \! z1 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 _" t( P. I* d, v8 S, X, {+ PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 d1 l( E3 {- A& M4 E/ @& |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 L8 y: e" f; g0x00, 0xFF); /* configure the clock for transmitter */- P; y3 p2 t# R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- h- |9 x4 H- O _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 a, s: G2 F3 \1 xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 E$ q6 K5 w0 B1 k* q2 \0x00, 0xFF);
0 R4 q: w$ Q/ |% @ B! Q/ ?& a. f4 G% U! a1 X7 `# M
/* Enable synchronization of RX and TX sections */ $ j( g3 e$ j4 _3 v9 T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" V( ?# |1 \4 a5 `2 }9 y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 c- G! h0 A& q6 _ f$ s4 `* G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; E! m1 M4 D' p+ u8 s: Q' M** Set the serializers, Currently only one serializer is set as$ t2 n$ e8 _% d3 |: F
** transmitter and one serializer as receiver.* f* v' Y* U" [% J5 i( B. k
*/; M! W0 e) f8 y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 Z5 _ P% e/ M1 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 M) d% M- P8 w- \" H5 ^** Configure the McASP pins
9 Z8 z# _2 M9 w6 R% y) A D** Input - Frame Sync, Clock and Serializer Rx4 w0 P9 U9 C* W; d$ k: I' R
** Output - Serializer Tx is connected to the input of the codec
" ?" R4 W5 u5 Y5 L$ C*/$ O5 Y! E, _# \6 _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 r( G9 K5 U; [+ |5 t) Z+ PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; z: {9 q2 o" J5 O$ g p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. u& z) v* L- j+ N; l% @) U
| MCASP_PIN_ACLKX& R+ X: ~/ p% S9 H+ U
| MCASP_PIN_AHCLKX
& ?# ^1 v1 n5 q* b _, S! s4 ]6 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( B) Q( _& s9 D. R" J! g( a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" b( K( u3 }4 }| MCASP_TX_CLKFAIL 6 Q/ N! g6 p- H. q) G0 z$ Q/ ?
| MCASP_TX_SYNCERROR
" q: _( z0 N7 c( `- S( n, [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ m8 G: F) l% p" W| MCASP_RX_CLKFAIL
$ w1 ]$ u# ?" Z9 J| MCASP_RX_SYNCERROR ( z% h; H# S5 |" R
| MCASP_RX_OVERRUN);: O: H) f# f! m3 g
} static void I2SDataTxRxActivate(void), H2 v$ O) r/ Q3 i' ^2 Q4 v
{
% q' B& q& L8 L( ^* }% x/* Start the clocks */8 |) J0 i' X9 I# S% H- D, _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# |6 [% o/ P; F* s& M5 b$ }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ T+ a/ P& I4 {$ G, B2 o8 M* z NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' t6 L/ \( X/ a- o
EDMA3_TRIG_MODE_EVENT);
" h' k3 B/ z2 z3 c/ XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ I' \) b0 q% w* p( u5 D3 ~3 A. cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, E) j- Y/ e. j. H% T) p/ d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: w7 E& C1 O2 ?7 w. t) `2 U! Z1 [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% M- J( {7 X1 v* b; P" iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. {" f* J( ?( G* BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) l$ L6 B/ N4 D! xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 B. E6 v0 }3 a; {} 0 _" G" K0 W* {1 O0 z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . g! v \' b6 i9 F+ ?9 Q
|