MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
! H& `1 m) Z% _8 qinput mcasp_aclkx,
$ z! D: \, P$ E" D5 \$ N' j9 c! A8 Kinput axr0,

5 o9 w3 c. v8 Y7 ^output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
: M- j" b! T. D  u4 w( M+ l

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
# a5 X, @4 d" Gassign axr1 = axr0;

1 C4 e- b/ n8 {) X

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 n2 V3 g: h5 h+ Q+ J. ~8 q8 NMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: q, V9 S, X8 \! _) tMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) o6 v1 b. N1 w. |: w( @6 K6 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 `! }! A* J" ]. p" s; ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ f7 E, K% M  b: x0x00, 0xFF);

/* configure the clock for transmitter */
0 m+ e4 V1 ^. S# D# HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 P% L1 ^; F- D) {" }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' B" A- c; s. J  v0x00, 0xFF);
% Q# h% C7 ?) @& T3 T
  x8 g7 q2 U+ \; r7 f. f/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
; D( q% q- ~' x, {  K2 _( J" U0 QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
6 u6 Y2 }2 O8 E' ?" F( I* ]' x** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
6 f/ y; g' I2 o0 q% B*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' b5 z; g5 x* q' q2 b' z3 zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
$ i9 C8 ^# r1 f7 n# z** Configure the McASP pins
9 ^( T5 _- l! N: G( Y" F** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
/ H9 Y5 h* x5 j+ ]" N2 j) a*/
2 g6 u8 a8 E" i: V5 |) p$ C$ rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 R9 j. {7 c) ?1 x2 vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; \4 n! e5 b3 Q: C: N3 FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: i* N- ?$ U. ], L+ ~) `$ L| MCASP_PIN_ACLKX
' |/ Y; E8 Z  A' C( A; c5 {' z| MCASP_PIN_AHCLKX
; W+ }! b/ v1 v% ^9 i| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
% k5 h3 e  \: E6 N3 l7 j, D! w* s' Y3 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% V/ z. B3 C+ a| MCASP_TX_CLKFAIL
% ~: D0 l" c& W0 t| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
5 S7 e$ H# l3 j" i1 D}

static void I2SDataTxRxActivate(void)
3 y5 y" d& C+ I* S{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
6 K. |* X  ]; A0 Q% @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ H6 Z3 Q: A( c5 VEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% Z- b8 }7 x3 v' `) B0 Q5 jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
! j+ @7 B0 v2 u% ?7 UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' H6 r7 Q" L/ Z, Q& eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
0 S& _0 w) J4 mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

2 g1 @  u) p  Z4 ], z  c. B" P, K7 E

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

$ i# \- A' @0 w$ b# m$ D# _