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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. N$ O- c. c( G* R/ a( T7 N& Ainput mcasp_ahclkx,
- o. ]# i; S$ ^3 b. _9 r- winput mcasp_aclkx,
* U& B& ~" ]! `. B$ B9 i1 {& z5 yinput axr0,
& N! E) _4 \7 n9 {. n. ]; h- I
$ t! E" E! W7 m4 ]3 L% X' _: Noutput mcasp_afsr,: ]2 v2 u6 [# U/ E) X/ @
output mcasp_ahclkr,
" ^+ W0 h& s! Q7 U: j' joutput mcasp_aclkr,
4 z2 d5 R6 q9 A. O* D5 J A# n% Ioutput axr1,
- G% {& |& }% D$ ` assign mcasp_afsr = mcasp_afsx;
$ P0 o; ~5 c! ^assign mcasp_aclkr = mcasp_aclkx;
: }& X1 J2 R. Bassign mcasp_ahclkr = mcasp_ahclkx;* w7 V) Q. B6 b6 P
assign axr1 = axr0; & v! K( y' g6 |# e. X/ [3 _
' L6 a n. L: g4 L0 p u: g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 r" v6 c( W+ D& {static void McASPI2SConfigure(void); ?; E3 p1 @" n0 V7 G, Z
{7 Q/ E+ c# S3 p l6 h8 V& W) T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 E+ n2 S# J' X# wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 y) B/ O& g7 Z0 D) }+ w. v% j4 M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, |1 W& S& [5 R; X! e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( v. n! K6 d3 p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 g- t, Y& W$ ?+ H8 x
MCASP_RX_MODE_DMA);
& p q6 L. f7 cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 `# x( M! X9 K2 Z; K6 G3 N$ cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; O% I K8 `; @: i+ Z2 VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: a5 k1 }4 ^' y; N+ Y& o8 ?! P' K, oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 c+ [* ]; X- G. I7 ~" s1 ^) H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 ^; v5 Z3 O4 r2 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% A) ?& ~8 W% K7 x/ V& P9 q/ V9 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% [ m# `6 I9 W) b; ?) E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" ^0 ~" ^2 |' r; zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' ]. |+ q0 P) u3 |, i. J/ l0x00, 0xFF); /* configure the clock for transmitter */7 `) a0 ?* R' K+ I7 d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 n7 _0 z0 J3 W, m; h9 l5 }/ }3 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 P/ J4 Z1 ^7 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( d- W/ D5 ]& D- Z$ B8 `+ G _0x00, 0xFF);4 L9 q& Y2 r8 @& E0 E
% ^& f- C# E. m/* Enable synchronization of RX and TX sections */
! a* }# H( u8 Q) ]9 QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" ^- f8 f y3 ^( T* B$ `+ gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 |$ W5 d5 ~( z' D% U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& ]: r" h' V+ {( S
** Set the serializers, Currently only one serializer is set as
- y2 h" S$ k! M7 c** transmitter and one serializer as receiver.9 ?; I$ Y% R4 O0 d2 ?; n& X
*/; r* F K$ {) G X: P' O2 O) @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# h9 j6 D" H; r7 lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' c- h( E# |% {** Configure the McASP pins
' ]( G2 ~) ^- e; S Z B8 @/ w** Input - Frame Sync, Clock and Serializer Rx
9 ^+ M6 N# e# Q! J& P& t0 c** Output - Serializer Tx is connected to the input of the codec * c4 F0 X3 B; _# r! k
*/
5 l# m1 l1 V) sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 r+ Q3 s; L9 c$ T# o6 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* d6 F5 S5 v8 C% I1 G8 |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: R- V) u( Z" Z I' B. H8 q
| MCASP_PIN_ACLKX1 i5 D l$ ~# p7 l8 q
| MCASP_PIN_AHCLKX8 c4 _. ?& V9 f) X5 t3 f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 C) k. T+ @& p* S# k. r' I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 A" a: L2 W" x$ e
| MCASP_TX_CLKFAIL
- R5 C l& o U% j( c| MCASP_TX_SYNCERROR: a* Z0 o) M$ c1 k+ x# t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 i8 D% {, s' M| MCASP_RX_CLKFAIL; s- e# g3 L6 k, [
| MCASP_RX_SYNCERROR ; L0 b+ y# m6 G
| MCASP_RX_OVERRUN);$ D: S6 M, Z' j& f. x( b2 |
} static void I2SDataTxRxActivate(void)
8 w* y. ?& c- s: j7 I) m: @{+ x- D2 m7 u! d- s
/* Start the clocks */ S- @3 Z8 s) }0 M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 _( C; P7 {# R6 W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
j9 W% h! K0 U: F% P" m5 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; a2 [( e4 r- D8 R0 j/ eEDMA3_TRIG_MODE_EVENT);; F$ x5 k1 l' z$ g/ a" h! m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & g0 w+ B# j; w0 l6 ?7 K1 j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: C8 s' ~& C' rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
a4 ?7 Z, @) X5 n& X Z gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: v& _1 z, }% X% |& \: g% y0 y1 k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) d9 P& R: D7 K/ ^$ A5 f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% B, }+ q' }; u& v5 V7 T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 c6 P3 j8 S% m
}
! g# W9 u' ]7 L3 I% s3 p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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