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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! ?5 X9 q. K& r4 z z; V
input mcasp_ahclkx,4 e' v3 }" @1 X! c
input mcasp_aclkx,5 a. a" u" T, i- O9 ]& [% i# ?
input axr0,
* e1 V- S" Q2 z/ i2 F+ \* h, F, k& g* ^2 H% `9 s v8 k
output mcasp_afsr,
6 i) G2 D! C/ A1 F; Qoutput mcasp_ahclkr,
+ M2 K4 Q& D' N2 u1 Voutput mcasp_aclkr,
5 w8 r2 N6 [! _; F" Q6 Coutput axr1,
) Y+ M% ~; q5 O6 R+ A7 q assign mcasp_afsr = mcasp_afsx;
0 C3 r: B' ?( p' Cassign mcasp_aclkr = mcasp_aclkx;: J C! k: M4 o5 W
assign mcasp_ahclkr = mcasp_ahclkx;
% M2 r# G, \1 v! rassign axr1 = axr0; 6 V7 G: J' d# E- v* ]3 |
( J+ [$ ]/ ~6 R3 j9 o# W3 ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / I: {9 ~/ w5 d5 w2 J4 I
static void McASPI2SConfigure(void)$ ?7 }9 P+ ^' s" t
{% T/ u/ w0 d. @$ A9 E4 C! ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. s& _6 [, B# D0 t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# \. \5 ^4 T: g( E3 @7 ~3 I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- x+ z6 ?1 r* v3 FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! z' [- l' ]" s6 s, |; _2 h, Q7 l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, r2 h7 \3 I9 f+ ^: j" S. c
MCASP_RX_MODE_DMA);9 P: P; F9 I. n& q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ~9 p+ u8 z6 W4 ]9 f* ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 |7 ~7 L: d6 B9 F& O0 b: c: y6 c# lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 a7 I/ g" `& `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 Z. k" c$ l! A# I' w% ~" XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - B; }: L2 h" w' N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ Q+ H3 G2 ~! W+ g/ FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. J" B( Y# ]: f9 |2 b* VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# m3 c7 r: t' C5 vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# Q" a+ ]' f2 x/ Z0x00, 0xFF); /* configure the clock for transmitter */
. ~- v; R; r y3 iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 D! B) z! N; Y- t- R0 X4 K- qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 q& K; x; X7 M3 U, M2 _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! X" ^1 H' Q# E0x00, 0xFF);
9 o3 s: c# q$ H: D- g
7 |; M3 j4 P' h$ n; Y5 g/* Enable synchronization of RX and TX sections */
: P" x# ^+ ~3 V9 _7 _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 Q7 L1 Y7 S) L3 MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 ~! c# O0 v, V! S' c W8 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! B. ^: Q+ T/ J7 }( |! N8 G** Set the serializers, Currently only one serializer is set as3 A7 G9 s5 k( v& C# e: v' n# r4 W- ?$ l
** transmitter and one serializer as receiver.
) f z5 O7 T; \7 [8 J5 j8 l* R*/& u6 q: e) R+ M/ O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ P1 S9 U% X5 K9 t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# r) ?& w1 `1 Q( J
** Configure the McASP pins
# V" x* h4 y# A) H8 g1 c! b/ Y** Input - Frame Sync, Clock and Serializer Rx8 Y% Z. k. v0 W5 \" L
** Output - Serializer Tx is connected to the input of the codec ) q- `* x, d1 H8 ~
*/: v/ F. K, D8 ~9 c; _. @3 ~+ z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 E, I) ~2 C$ x3 o$ w- ^$ ] C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) A* J. O/ j- p6 `" o: V( h3 S5 hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 o& E7 I! `) F, i2 W| MCASP_PIN_ACLKX4 c0 c+ y) l8 u$ U* X9 o
| MCASP_PIN_AHCLKX
0 b3 t A+ \% F. A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 C4 z, G2 B' B# K2 m# y2 y& C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! e- Y4 r5 ~8 f) q0 r. G| MCASP_TX_CLKFAIL
f0 m% b! [6 o/ r3 A$ S: K# D4 ^| MCASP_TX_SYNCERROR) j/ Y" E6 c' w: v; c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' y6 c2 O) z% I0 M
| MCASP_RX_CLKFAIL! }3 E3 ~" x% e5 \8 U% ^6 Y
| MCASP_RX_SYNCERROR 8 L6 k6 d% J0 }0 ^& @8 P
| MCASP_RX_OVERRUN);
2 Z+ v1 q: O1 i( b! \$ U} static void I2SDataTxRxActivate(void) {2 [& s7 v' W- H
{: E- J. ~" j9 ~2 n
/* Start the clocks */5 I/ C& Y9 J2 x0 t3 {5 V1 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 X' M7 m2 j" w* Q g# SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// q1 S0 A6 c/ v+ C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, p5 a6 r& L3 WEDMA3_TRIG_MODE_EVENT); l2 v% y. l! i ^( [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( O# ?1 M# Q$ z& Q% _7 W$ nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# V3 U% B0 ?9 f; Q \7 i* C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 M9 U$ Z& \1 t: G" @6 ]; ]) ~/ Z M- y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 S0 Y. _% y8 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% J) }+ t: }% J3 EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 C$ U1 @4 C7 m( f# [- uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 e) y1 H6 D1 B2 y% h
} ( m. o P1 M r! g* V* b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( Z( y; d) @( p8 |% {7 I9 b, S8 R
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