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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% x& U/ k; M6 a! N' n$ x
input mcasp_ahclkx,/ E8 z+ N2 \% D3 T# `9 H/ l! }
input mcasp_aclkx,
8 b" t. j5 f. ~! ^/ Qinput axr0, L2 c5 R. D; J1 M6 t; S( h
6 u: k/ A4 y, G7 r4 O" \output mcasp_afsr,
+ I8 B6 L7 W7 g( Ioutput mcasp_ahclkr,
& E0 v$ {. F( M- k' moutput mcasp_aclkr,
4 K6 Y+ M- s1 N1 L5 ]output axr1,
, u3 s9 @; Y/ J" V, }5 E9 v assign mcasp_afsr = mcasp_afsx;) h& I2 {! Z! X: O: Z* Y
assign mcasp_aclkr = mcasp_aclkx;7 H9 q; x# {$ j0 Q0 s
assign mcasp_ahclkr = mcasp_ahclkx;3 I9 H8 i- k* W% l4 a
assign axr1 = axr0; - f. o3 `/ T/ A
- B+ D4 ? A& s8 K/ d+ U o6 ^' b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
s) p2 i7 r$ ~* B5 G, ^9 { N% V# ^static void McASPI2SConfigure(void)
; Q! g0 v, J/ z; `* U" \8 ]9 o6 |{
2 @; \, w, H# w4 c) H% OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ n# t0 T! v2 ?- N& @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 l& G/ y0 \" A* a5 p& T J1 I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: L1 i4 L' f1 c1 L- a- \9 GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 I" \% m; J4 K1 W/ \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( g5 f, }% O$ Q* E: a
MCASP_RX_MODE_DMA);% V/ H$ K' t9 i6 r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: \8 I1 |- c% d+ z M9 }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# p, P! S- ?) W; nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ |6 G1 E5 \8 {6 p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: ?8 a7 f8 X* W% [5 T' tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ K% D( V W7 hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 B% g( W2 f. @, E+ s% rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' {$ Y' a2 O2 [& X- I: `8 VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 I, o: r. K+ s, a. hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, |, k5 T& K0 F
0x00, 0xFF); /* configure the clock for transmitter */* _( x5 W0 Q% |7 t" w# J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 x' q& R$ F; b0 e1 @( k& {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 Y1 p; M8 b. l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 a8 S+ e m ]" S- ]# ~# [
0x00, 0xFF);
3 M! W/ H4 |6 X2 x m! K
* w& j/ [0 ~6 P4 A( g9 X/* Enable synchronization of RX and TX sections */
. \* `5 k" W5 s7 _- D3 A# `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 ?% F% }. K$ g5 W( g% y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' W9 [) T7 y# h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 E) N- b: \! O
** Set the serializers, Currently only one serializer is set as8 P6 X. i% t8 A; U$ F' Q/ R
** transmitter and one serializer as receiver.
2 V" K0 |2 q4 b" G*/: p0 t4 i* n R) a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ b: X4 _ j" ~; X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% h0 H( ^- f8 G' a/ }" q& v** Configure the McASP pins # P) w8 A5 d, Z* w' e J7 a: N. L
** Input - Frame Sync, Clock and Serializer Rx
' U) F' T! a7 o** Output - Serializer Tx is connected to the input of the codec
' s! T/ L, k' V2 S P. ?*/
8 k$ W: X8 y$ {! _, H- b4 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 l5 y. {- Z% }4 R; \1 w- t& }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 N! q9 K2 x. y( z3 {' N o' gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 I+ E: q* g; Q' x; Q( u! D: q5 n
| MCASP_PIN_ACLKX
1 l2 m9 F8 b7 W- `4 Q| MCASP_PIN_AHCLKX" \1 T' Q U5 ^! Z! N+ {7 l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 r! I2 v' b' T- {2 _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) S$ }$ H+ v- [' m0 i| MCASP_TX_CLKFAIL " l0 i; w8 t" y/ ]2 h5 G
| MCASP_TX_SYNCERROR2 Z+ E" V1 b" _! D' m- P, f' i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . ~. ]6 y) R: b3 J, d1 P3 T
| MCASP_RX_CLKFAIL
0 J, T. L" H5 I, T! R" U| MCASP_RX_SYNCERROR 0 U2 U& a; a) P8 L6 a
| MCASP_RX_OVERRUN);: g7 D$ f) F+ }* \0 v w" C( o( p
} static void I2SDataTxRxActivate(void)4 S! A2 |- u2 u# P) L" ~3 w6 @5 k
{
9 g5 G- Z! f0 M; V/* Start the clocks */ p$ k; l, [5 U' E B; Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 p& Q7 z# e: M7 W( G% ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 b. y5 A* t! m' A( F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," H% R& }* r: K f2 Y: c
EDMA3_TRIG_MODE_EVENT);
* U7 L) [' @5 S( AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( ]# H u" w2 J Z3 M3 c3 N. I: @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( f1 r* s' q3 kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* F" J( j, l. ?+ M9 Q- s5 a, |( tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, g/ \) _, E1 p5 M$ P3 z$ D+ N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! p& Y3 V! v7 k: Z) l- n s! I1 o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) T' b' E/ j( a- c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, M9 r; `3 M9 m+ o0 i% F) U
} 4 I/ A4 \( y4 q- |3 S4 m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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