|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 O3 S8 S3 o$ H$ `: N5 y% l2 d
input mcasp_ahclkx,
7 @8 C3 ?: V. O" D: m4 ?input mcasp_aclkx,
% e% l! Q! z0 b, t& Minput axr0,
! B; j0 ~/ X9 k" H) Q- b B+ }4 O6 K; r# x0 I
output mcasp_afsr,
% o B# _* }. r* _output mcasp_ahclkr,
- J% o/ S% v0 H2 m/ Y7 p( i1 xoutput mcasp_aclkr,' B6 F: u# z+ ^7 Z
output axr1,
g6 Z4 `- G/ z assign mcasp_afsr = mcasp_afsx;
i% P$ G8 |& {: g: Oassign mcasp_aclkr = mcasp_aclkx;
' q; [# J! @+ \. ^assign mcasp_ahclkr = mcasp_ahclkx;
8 B/ A2 O: @; J9 r# P0 R2 `assign axr1 = axr0;
" z4 f9 C& W3 R& N P
3 V1 c9 c* L' u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
T% B; m2 Y, k! P, O9 j2 T1 wstatic void McASPI2SConfigure(void)& f1 m M/ {* [( o
{+ ~6 c; O8 @, Q& F( `. U+ x; }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& F- g8 B5 \$ C d. N! I0 @' VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 F8 {7 A+ ?6 ?4 ~ A7 U2 r+ M9 g) x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 Z" M" L8 q5 L+ u" f. xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- _9 {% n! ~; M. O m G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ i; C, F, I+ }: T
MCASP_RX_MODE_DMA);: ?; B" ^& n. x( X( ?* w: ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( O, a# T0 i5 RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 h" A* }$ r: Z- d" m! f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ L; o' D6 ^" Y2 v6 P' i$ a( m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 R6 {4 [" ?1 W8 K U4 |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
|/ j& S4 I. c- ]0 HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- e% R1 |( N" _* d7 n* y; S" V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ u2 f( Q5 z9 P" V8 F0 \7 z: V* AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + Q& m* K2 Q& j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* R+ d7 V5 b& @% o& q5 E
0x00, 0xFF); /* configure the clock for transmitter */+ |* M: ^. t, v8 R- S: x$ B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* H# ~, f! \+ P0 hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 Y v. S) g @; G; L$ j7 v& gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& z5 I9 M. l Y- r3 u* v R# O, [' j
0x00, 0xFF);% l& N' V; z3 F1 u p, s; y; V# w
' A! Y) Q N$ r; R5 ~
/* Enable synchronization of RX and TX sections */
# v% u" A# w8 q* HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ O1 }7 S. b; f8 L% t) Q' BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" d5 ?- B3 q1 t' q* y. K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** D3 u. e# C' |6 H0 }. {
** Set the serializers, Currently only one serializer is set as' t4 l: {4 K# L; V
** transmitter and one serializer as receiver.
% s0 S' y& J( W; {' E*/$ u! f. s a" l) U( O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* i3 q! k/ b4 X# C4 l7 Z( a5 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ l/ u$ H6 B- M6 f2 z
** Configure the McASP pins
: a2 _6 j. e1 G. N** Input - Frame Sync, Clock and Serializer Rx6 u, \6 X( K4 D8 }
** Output - Serializer Tx is connected to the input of the codec
- ^$ O# f8 S* X( ^: ^: f* \2 |7 f*/
3 c) r+ u' G: g7 r" RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. R6 a* v5 P; z! Y5 s2 `5 ]6 UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 f, w, E6 ?( H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 o4 U- _! Z9 P, e| MCASP_PIN_ACLKX! O- x- \9 P. @- {# \
| MCASP_PIN_AHCLKX" g* o5 Z% L6 {* H' O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 J5 X# W) u1 w, MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 Y: }+ C' ]; P7 x' G$ o% W| MCASP_TX_CLKFAIL $ g) y$ v+ t( Y+ g$ |
| MCASP_TX_SYNCERROR
: ]$ X" u7 C# i3 o) O/ r- {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. J( r' v5 w l" x* k- }| MCASP_RX_CLKFAIL p b8 O `0 o d* e. H$ O% H6 Q
| MCASP_RX_SYNCERROR
. E9 a6 [0 z! K' l: w| MCASP_RX_OVERRUN);6 s; T) G' R: r. B/ w/ R
} static void I2SDataTxRxActivate(void)
8 q- e' \2 t% I{
/ l5 R) L: ^5 x2 J5 Z" f/* Start the clocks */
% y4 I; h8 L. |3 Y. EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 R8 T' o; } _8 O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 J! E1 e3 i$ l: F% E# P0 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( \; ]+ z5 i& r* g7 Z. Q+ PEDMA3_TRIG_MODE_EVENT);
1 V% @3 v' b/ v8 Q" ~8 p4 F- D4 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- a* C- H3 d0 gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- e/ D4 ^/ p* I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 ]2 }/ P1 m4 u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ P3 R4 g7 n, i, M5 O6 X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 ? O4 }8 I, f, ?. Q* |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% t# W* ~' R+ {2 s: ?" FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: ?- ^' H$ s- z' @, V1 F
}
' }- X8 p5 N9 V. h% f/ h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- `, {7 ]6 o. z |