|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( a5 [% S9 B/ O& ]/ I3 G2 W
input mcasp_ahclkx,; {6 L! l5 ` f
input mcasp_aclkx,
+ v3 L! H* e( ]# X$ J& w; einput axr0,; F, `' R' u- r7 E( H
' `8 c$ l- Y4 G+ s0 H9 {
output mcasp_afsr,
# B: E3 `% w* X _5 _output mcasp_ahclkr,7 N, J& K4 w- U( `3 M3 l
output mcasp_aclkr,
: M5 A7 N% i* t8 J# m1 A/ O6 Soutput axr1,
3 k0 b4 G3 n5 R2 s0 \0 u, ^& ] assign mcasp_afsr = mcasp_afsx;0 @# v% |* N5 }, d. u
assign mcasp_aclkr = mcasp_aclkx;( s% S/ t4 j2 z& A4 s
assign mcasp_ahclkr = mcasp_ahclkx;
4 Z3 x7 C9 m" N( q1 J1 cassign axr1 = axr0;
4 Z" _/ c' G, R' w. X+ k& U# c8 h$ o) ^: M' }8 s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 J. a% L0 [. G! b, K9 d
static void McASPI2SConfigure(void)
1 f# Y/ }6 y- Q{
5 L; m* K" |$ l5 HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, A* O. {: w" ]8 E% r* h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. w( ^* k- C" K& q* D5 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# c; X v9 o' U* j" m6 y( R3 B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" C7 P* [1 P" r& g; IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) w) s, Y" N& S/ A- cMCASP_RX_MODE_DMA);
! T+ E4 _6 ^* z5 t! ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! q: L# d- Y4 r, M( [2 XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) p8 [$ g0 D8 L3 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, D# _1 V! X5 u0 xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: W) h4 K U- b9 k1 p$ \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 ]6 x- S: P5 |2 m/ [, gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 U4 ^ i8 m( I& Y' D$ H+ {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; r% I' f6 U3 I" F' g* `9 C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 O2 b! Z0 F- R% RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! \* W' K6 R* @7 S1 n9 `
0x00, 0xFF); /* configure the clock for transmitter */
! C9 ?: G$ ~, n4 Q% h. a3 f ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- I" x( I0 m5 S. ~7 A, rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # t" Q- G# n- |( e8 i6 ^! m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ B& g$ a1 n/ e+ v0x00, 0xFF);6 C+ @8 k3 S9 p* k* s o
* ]" }( L" {. o/* Enable synchronization of RX and TX sections */
9 }# A3 m- ]& y3 Q0 ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, ?: i Q, p4 ?! Y7 ?4 gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 c( M6 E+ z K! f/ h/ o: b, o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 F$ F d$ Q8 D# _
** Set the serializers, Currently only one serializer is set as
4 `$ ]: \1 a1 P, m** transmitter and one serializer as receiver.
' @9 q+ [' F4 k*/3 d% g5 D; Y. R( S8 G6 [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 f$ Y1 v8 {& z0 U% yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* k, j. k) }2 F! W; A** Configure the McASP pins 2 q1 R' |" i: Z9 d s# W0 x
** Input - Frame Sync, Clock and Serializer Rx
" h' Z* g8 ]5 U W; ]** Output - Serializer Tx is connected to the input of the codec 0 F9 _+ N) {2 O
*/
% \# F. \) q" u H! T1 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
C$ a4 Y. [5 N1 }+ j4 h% jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( J- A3 B) r s& [$ E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" s# P9 y+ Q. H) l9 Q! m" c
| MCASP_PIN_ACLKX
6 Q, h9 ^6 r1 h% h: y| MCASP_PIN_AHCLKX
* y' ?. I# m$ [6 ]9 {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 f, {" V! q1 U4 L5 sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 _5 G6 U- [) P: H! I7 r2 ?% t
| MCASP_TX_CLKFAIL 8 G9 c7 g* b8 I' X. l' {
| MCASP_TX_SYNCERROR; w8 E' C9 \: _8 d" j, {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; `. W. L$ w" R! M" R% C* D2 D
| MCASP_RX_CLKFAIL1 |( }8 \. E3 y8 O3 j6 L, h, o, u
| MCASP_RX_SYNCERROR
% P' t, d9 a* i7 k| MCASP_RX_OVERRUN);
. S0 o3 ]+ q& d D# ~+ w! Z7 ^, \} static void I2SDataTxRxActivate(void)2 g5 P# I' m) f. Q: N; S" V
{
4 d( s r& }! k- x+ B- }% j/* Start the clocks */
# R9 L) Y" C' {+ Z2 p( [8 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 o! y" o$ j3 d; ^" FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 Z: k, u' A3 z0 u( \. ^ T' |2 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 n8 _ x% z$ W; y, G$ c0 R% w$ U
EDMA3_TRIG_MODE_EVENT);# Y+ a$ q2 H1 v d" |3 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 ]: q! O$ a- L5 X, FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ T2 n5 A1 V+ _1 V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. M0 m! [- W! s J2 r3 |' ~7 pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ n, I+ b- I6 t4 M3 [0 O5 Y, W% j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 j' p/ i% o' r1 _% ^5 P6 K4 A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ C) M: b8 w, n, g# l9 s1 r; NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- P5 X8 z. I+ u0 E
} 6 } i, w: J. m+ b2 O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
& T5 X% s* A6 g0 ] |