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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 E3 s5 D/ h1 u) e% a/ g
input mcasp_ahclkx,
, W- b( ^( [: |# I% E O: ^5 jinput mcasp_aclkx,
) j' ~+ i) ^7 Uinput axr0,
c' b4 i, u0 v3 |$ h
2 {: n8 z) F: t2 R1 i# q2 d% M% m- Loutput mcasp_afsr,6 E) a; U5 `- j3 C. s6 i3 P" W* y" a
output mcasp_ahclkr,$ I3 V8 j3 z. q* v1 E' K
output mcasp_aclkr,5 U$ t" ]! _1 L
output axr1,) V# @# n" Z- W& G; Q
assign mcasp_afsr = mcasp_afsx;
4 z* J. r: g0 x% |assign mcasp_aclkr = mcasp_aclkx;
9 Y. S( ]1 ?0 I7 l* N# V% Z; fassign mcasp_ahclkr = mcasp_ahclkx;& x p5 K! K, I7 q7 C1 S
assign axr1 = axr0;
7 x$ {* v8 X, B, t8 E# D
. M m5 t6 f6 k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 L [$ J0 `5 ^# p
static void McASPI2SConfigure(void)
, b$ x. j/ u. [0 f{1 ?$ d7 G, x2 j* e5 ~& G2 S& h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 w+ C9 x1 H+ R. t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ ^3 p/ i9 J1 c9 S1 I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ ?9 h8 B$ Z# |; z" C X3 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) L/ o3 h& v+ e8 K+ U, i0 ~* V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 M, ?; M0 ~8 \2 e4 z; E
MCASP_RX_MODE_DMA);
9 J) ]) \6 u$ bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 j8 P |) {0 K5 x$ LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ I; M! V3 \ s, A9 B+ wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 F, F, z/ ]1 i" V# PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 n/ @5 L9 \3 \9 \7 cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ a! C7 x" P! ~3 vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* V* g; T5 H! C; t0 j. S2 }, u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 ^' P2 P) a$ s1 O. ]/ G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 M ]" z9 Z: R$ W, d2 o9 C' v7 m5 IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, `: b2 Z8 R ~) |' K) ~1 p
0x00, 0xFF); /* configure the clock for transmitter */3 f- Q* T$ P7 P3 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 T4 l w/ P% J+ M3 e% Z; SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 |3 g' T8 }1 g2 d2 J9 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( [# Y: P3 m0 t8 h" E
0x00, 0xFF);
) `1 L' \, d/ r# y1 ~" _3 S, J: g+ X, Q, u# P0 T# M
/* Enable synchronization of RX and TX sections */
, ^# u4 h: t9 n9 U4 K. U3 nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% e7 }/ ^1 x: J j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 ^/ E2 @5 y9 U, t* ?3 m2 }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, p' n+ B7 Y3 U5 \** Set the serializers, Currently only one serializer is set as
+ s0 y: |" l% A/ ~** transmitter and one serializer as receiver.
- A# [$ u" j* g O% P& A*/% s* z9 w$ z' r. ^# w; s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ K6 K* \; W2 {% n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ x1 v8 x3 M. n. @
** Configure the McASP pins
4 o/ n4 B) J N/ f; ], N5 E** Input - Frame Sync, Clock and Serializer Rx
! B6 B# M0 x4 k9 M* E- R** Output - Serializer Tx is connected to the input of the codec $ u9 g. i2 a$ I4 P
*/
" i% c- G) j. t# K" Y" |( K2 XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 w6 B5 ~8 \) S% z( EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) b0 ?% `' N! d3 @$ e; ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 D) c% p! w5 G/ ?# y. X
| MCASP_PIN_ACLKX
, _9 Y0 z/ T$ _* || MCASP_PIN_AHCLKX' r! _2 Z/ @9 J1 ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% }" A7 H9 X, L# X4 r7 p5 kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ q+ o4 Z! Q3 t3 _4 u* r| MCASP_TX_CLKFAIL
: f5 p; c) O3 Q0 k8 \1 W6 [| MCASP_TX_SYNCERROR
6 q# |# E; o8 N5 `. e, T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : G. O @# D% V$ \3 f4 C X8 ~9 }
| MCASP_RX_CLKFAIL
9 W8 w# m7 U1 [7 V| MCASP_RX_SYNCERROR
' c4 x- q0 D: P+ ?5 Q| MCASP_RX_OVERRUN);6 ~5 G( Z* S. c6 V
} static void I2SDataTxRxActivate(void)8 `+ S. |& H2 F+ ]! L
{
Y \6 u8 w" n: q2 z1 L/* Start the clocks *// \- i: T! H) H7 N, e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% ~: P6 ~! j" G W x* b2 u: n1 xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 z, x' r1 x2 J. EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 y; w% U+ D' Y* q# o2 ?0 f8 S" W- ~EDMA3_TRIG_MODE_EVENT);0 z( q, q8 F! L: `) Y: i. n$ D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ b: n+ O% t7 g9 b7 Y6 H2 ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( l% Q8 S2 C& [0 m4 X( ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 J) N& T' B1 G* K% T+ h' kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# S6 | e" \0 W* y2 e' e2 j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 }7 k7 h0 d8 }; g# t9 h0 M& V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. q: J; V$ r4 }7 D) P6 N; X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% p4 ]/ E7 y+ ~0 E7 E# e} * t4 G1 \4 p7 M2 q( w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 u3 ~! }; N( p7 E" s& o |