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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 x6 b ?6 C; ^6 y$ ~8 q" Minput mcasp_ahclkx,7 r- a R; F2 U {4 z- U, v. x: I
input mcasp_aclkx,8 v$ Z; H9 V; |$ E; D
input axr0,: a! ^' Q6 z( m' \: B
* {6 d9 [$ ]+ u- g2 S
output mcasp_afsr,0 V5 H: q& B6 K8 b! F
output mcasp_ahclkr,) g) K, s9 F2 k& E
output mcasp_aclkr,; j0 K t- C+ O, j$ Y4 i
output axr1,
6 t8 \! O9 O: F# v& F K7 O assign mcasp_afsr = mcasp_afsx;& n3 F* N2 s1 m
assign mcasp_aclkr = mcasp_aclkx;: f' _- Q; v8 R# \7 o! j* g8 g
assign mcasp_ahclkr = mcasp_ahclkx;
- G$ j5 C0 g% q) v$ Jassign axr1 = axr0;
3 P0 j. O0 o! i
$ b0 e L. Y6 M4 x+ P9 s. ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! Y5 L3 T( |) v- }* V% ]2 O kstatic void McASPI2SConfigure(void): U% [) P @! |6 `( _: u3 o
{! X$ U. B' @' A! a; |$ b6 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS); m4 h' s5 V5 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 z0 e1 o( I5 Z+ e) ]' W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- z$ o1 M9 C' k6 T; E- `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 c4 C; x/ b; I8 }; D1 ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ m3 a, p5 E+ n( _
MCASP_RX_MODE_DMA);3 H- N( N j+ n7 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# A2 t- f7 l$ j% Y7 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) A9 g0 G, w+ G9 A% c8 h7 l5 @( E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 M/ L- k# b1 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: a+ b h0 k& o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 V/ @4 v( c" E) B! s) z# r" ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 v' ~4 b9 _$ yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 M& u8 w1 m# T& m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - S' a; y/ F- u! F7 y+ I0 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* J' f V( J' d, {0x00, 0xFF); /* configure the clock for transmitter */
# P- @8 @4 l, h. K0 f9 a7 k# mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' ?+ K# `1 C: w: \' dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 y6 Q/ ?/ w) c# v- U8 IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 b) j( ?1 ^6 A, ?
0x00, 0xFF); I- E3 `4 S* d/ w1 o; [0 \& Y5 s
- r! C$ H. [- T7 I W6 I
/* Enable synchronization of RX and TX sections */ . u& t) V5 N$ @ l9 v# B! n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) d. ^0 s) l: j- @( Z: @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 d7 ?- h- H( P' P$ F1 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- T1 S9 S; l& Q( {' V f
** Set the serializers, Currently only one serializer is set as) y) J2 U2 w4 |! [; X
** transmitter and one serializer as receiver." Y4 y: Q. _" z
*/
% ~4 ]+ ~( c9 F9 }8 w# TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 }6 m/ |2 {/ U! A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 j4 _9 I: L5 j2 t" n6 H
** Configure the McASP pins / a' n" Q$ H9 {2 E" v! R1 W. z
** Input - Frame Sync, Clock and Serializer Rx
' A3 }7 q3 m0 z+ ~** Output - Serializer Tx is connected to the input of the codec / ?, L3 i# w. V! ~" ]- R Z1 I
*/, S" S" ]$ r% H. F7 A i& G9 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 z4 d8 ^1 R& H! q( G; c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( `/ o+ e- u5 [. R9 @! oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 m" p: M% E, F$ @
| MCASP_PIN_ACLKX: L- q' N6 `3 W% K
| MCASP_PIN_AHCLKX
! C+ G& t# j) q8 W5 U/ r' E _) i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 w8 t6 C) }: I( H6 [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 P$ ~: f) K7 L| MCASP_TX_CLKFAIL 0 w- D* W2 }$ {2 B, Q; Y
| MCASP_TX_SYNCERROR
8 t& ^' Y& n) T: ^" q1 n/ Y+ @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 k# r0 w9 V$ e- S8 B6 a
| MCASP_RX_CLKFAIL
4 j% u( X( \/ ?# c| MCASP_RX_SYNCERROR . n! F! _" q# B
| MCASP_RX_OVERRUN);
: V0 a( t- v( M4 F( ]1 ~} static void I2SDataTxRxActivate(void)% ?. [- |1 |. L) \ m# s4 b2 |
{
$ m& v% o5 K0 o. Q- h9 { O/* Start the clocks */
& C% n: k V( ?! N) d" [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: A3 \# N( @8 \, c3 W2 rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' g1 l8 q5 n- xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& K5 }- z* _" Y- y4 Z1 AEDMA3_TRIG_MODE_EVENT); ^; h- }, Q g9 g" }- _/ U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + q, s0 E: g7 P( l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% U9 ]* `% ?5 }- |4 n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 [* Y$ q# [9 n# r& Y+ {$ ] K$ Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 P: W. B; N# O- ?" F" bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& T/ t0 Z4 t4 E, q& x0 V \- I f0 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# b- }# l7 M: Y( Q% T, W/ h9 R- XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 y8 a" H9 k% {: j+ `2 c+ B# \4 r} ; Y( J! W) e- F3 k/ N" ^ Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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