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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) J5 K+ O( ?9 z& _- }3 C5 V/ dinput mcasp_ahclkx,
( o! R- V+ B( i2 D Finput mcasp_aclkx,
. N( T6 i/ t( Iinput axr0,
0 V' T0 S! r5 L E. P Z e9 j# ^4 S6 o t n- u) ^
output mcasp_afsr," ^4 V% x7 p4 V1 D4 u, T1 j/ S
output mcasp_ahclkr,& t. B; t# L3 O- ?: T& P
output mcasp_aclkr,
- g# M% R6 D- g. N( F4 Poutput axr1,6 R2 P5 D8 h G: R1 l8 j
assign mcasp_afsr = mcasp_afsx;+ O* E. U: F: Z8 A* M" F
assign mcasp_aclkr = mcasp_aclkx;
: Q2 l. _5 m5 P7 h. A9 L6 u: tassign mcasp_ahclkr = mcasp_ahclkx;
0 P7 D# h1 B. ?. `assign axr1 = axr0;
5 U6 O. m4 C' B6 L6 i3 Z' Z% t
+ C& J9 b/ q! ]% N8 B1 W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * G2 {. I& S7 k! ]- Q
static void McASPI2SConfigure(void)
0 Q% ?% ~& _; N4 e, u$ s2 O{
& s' c# l* V8 V. _- l% ^$ \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, h: D( _& q1 W( GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 O# x" a" ]* D* V$ q* Z4 a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: l6 j7 m& J6 k# K. S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ K8 P$ ^9 I- u! ?. z, H5 v+ ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* ~# F% H* O& e8 I! r' u7 J1 ^. R2 C& nMCASP_RX_MODE_DMA);
& Y5 t9 M. }9 u" B- OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: g; Q M( u F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ M! e4 ?3 X# i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 W4 e) a }2 y \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* y e c" M& ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' I3 s4 {2 N$ ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% f' q1 U+ @! x' i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 m5 j/ C. e7 K7 `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( e h7 l0 ?8 ^; v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 O' l4 x# [+ K/ Z( c" q+ d5 O0x00, 0xFF); /* configure the clock for transmitter */
# D/ }, t& A* Q$ d0 eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- I ?" }6 Y% y1 U+ b+ o8 \: m7 \+ B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 _) ]( c- v. w4 G0 j* I7 G1 F. GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ D' f. O7 q% i0x00, 0xFF);: A+ p' |% Y# s# L
) z' {, D) R: k5 D/* Enable synchronization of RX and TX sections */
3 F( G! A7 h4 @3 ?1 lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* L; I( y4 o$ U" S3 ^$ F. ?& JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) C$ R, g8 [* u9 P2 q. o2 S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( Z# G3 S: }6 Y$ w' X% z8 z** Set the serializers, Currently only one serializer is set as# {+ T: n6 R" G) T
** transmitter and one serializer as receiver.$ E$ s: E6 |; x0 {# a) a
*/% q {( z, X) b9 L0 a) ^% ^9 L9 q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 d4 V E; `: }- v2 U* `, H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 }% X8 I' O8 H& Z5 e/ `
** Configure the McASP pins ! j2 \ q' G/ U$ }; K
** Input - Frame Sync, Clock and Serializer Rx
v- T! A/ L X' E** Output - Serializer Tx is connected to the input of the codec 1 t; V' r- q( W! ~* y$ @
*/" Z6 a1 F2 P C y- q- m0 ~5 p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: I* \" K8 c* W% L+ f; Z. y% SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 z5 V1 p( g3 ?) K0 v. `; U6 |" bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. p$ p) s/ |, Z% A; F
| MCASP_PIN_ACLKX+ ~: S4 K# }( D! K' S n! j" M. l
| MCASP_PIN_AHCLKX8 } ~( B! N9 @7 {7 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, X( D/ x M& n; m0 {7 q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / b5 k. A. `( u9 O" v
| MCASP_TX_CLKFAIL " P9 Z) B" B5 v! x* S9 ?0 `9 b) G
| MCASP_TX_SYNCERROR$ W$ O9 P2 @# F; m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. V. n0 M0 F7 l) K4 Q1 r; w| MCASP_RX_CLKFAIL( y+ @* b4 ?* x2 O. C
| MCASP_RX_SYNCERROR
! L8 E5 R2 V- E# m2 `| MCASP_RX_OVERRUN);
8 P) r# t3 r8 x7 Y: \} static void I2SDataTxRxActivate(void)# ?. b: [+ p3 ]% {: a8 U' K
{
: z; h1 D4 R1 r( \9 P; G; C$ D/* Start the clocks */
9 H/ ^+ d7 Y- _; E/ qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 _/ m. |. j* g9 |0 O% MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" a" v" T( B- ~& T; [* `# wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ c5 e6 s4 E! ]: e& F2 g1 H- ^' O
EDMA3_TRIG_MODE_EVENT);
& Z& F8 c( m4 j- I7 ^* G4 Y7 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 R( }8 r6 K. ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: V7 u2 I- R5 C- L; }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* }3 L2 v, o* S3 B( k, h# ^; ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: V+ ?/ e: T' {7 R% C. Z2 @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. m& {4 u, P/ Q# h; r5 C% mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ z- Y$ r) b0 E8 k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( |0 } W) L6 O* u0 {
} ( x3 ^8 o2 O! e; y( u! z4 ?5 ?0 E: {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 f) N! D; [1 Q2 v' n& |2 M/ T
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