|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, A( I- D1 e5 ]3 ]$ ~
input mcasp_ahclkx,! U9 Q% r& _. x) Y1 T9 U( W
input mcasp_aclkx,) ?9 i% M' \4 [ w! c+ {
input axr0,
0 {+ P& C$ R' R# J2 w1 g2 V$ E( F8 z# r- t" e# _1 a' j
output mcasp_afsr,
7 q9 q" j9 ~, _output mcasp_ahclkr,! h9 T% [& U+ H* Z% l, M; q' M
output mcasp_aclkr,
% C `: b% U; C/ k* H/ x' Aoutput axr1,$ N$ F0 C( v I( h
assign mcasp_afsr = mcasp_afsx;
5 ?$ [, M) m6 ]- c/ Kassign mcasp_aclkr = mcasp_aclkx;, T$ L3 E9 v. Q" G! J4 o/ f, N8 f
assign mcasp_ahclkr = mcasp_ahclkx;( `6 g* R/ {4 b9 b
assign axr1 = axr0;
& g t/ v$ V/ c) L! p1 L1 L* L
9 d2 v; P- q, e9 n% |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# O9 o0 U1 l# i( w2 v; _& R5 p* J2 ]static void McASPI2SConfigure(void)
. M' S" M" `0 k! [{$ M. I, `8 B$ d9 g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 |: R8 _5 U7 k& c# H% bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" K& I. @; g: z) g, WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 n$ ]$ j, v" _ }/ @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 \( M2 [5 Z& k6 A1 g3 ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 R B$ U1 Q" s) Z( }5 {
MCASP_RX_MODE_DMA);4 G. E: H: f M! u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," }: V+ M, j2 t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ {7 }7 d2 i) k( U) M vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# i, a" c1 n- YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. q% O& |3 h: @# qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" [5 V6 Y4 S4 K! f# WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: p; t# f; G8 c( X5 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 B% s2 D3 Q6 r/ wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ }: T; P. Z; ~ O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 Z+ w( V+ N% p7 M/ i0 N" ^0x00, 0xFF); /* configure the clock for transmitter */: A, e7 S8 R" b9 K" H3 b$ ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 w+ d0 V6 Z8 X5 S5 EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ E- I0 b* r3 ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* M. L% q) ?5 n% k
0x00, 0xFF);% y0 b; X1 D! V$ \& T
# U/ Q1 J* w v/* Enable synchronization of RX and TX sections */ 1 f3 V7 X, Z6 y. ~: l) `2 }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 U& P2 E$ \( D8 B1 ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' U. L' ^7 f5 f7 n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 R# g% v, r5 s) ^: n0 `
** Set the serializers, Currently only one serializer is set as; S0 W3 X* Q5 T( ?7 [
** transmitter and one serializer as receiver." Q& j2 k3 s4 |! d/ s( U% ^8 f" g- g) R
*/
* Q% Q; i/ M7 {( F) m6 J0 O O4 tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ x. Z! L3 }) h0 h$ EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ _3 i& I- x' ?" ~! K** Configure the McASP pins
6 U( J% k/ @* l3 n, s+ i** Input - Frame Sync, Clock and Serializer Rx
- P i, j4 A* J* O7 i** Output - Serializer Tx is connected to the input of the codec
/ _, x1 o1 G- ], D( |$ x*/, F6 M; i8 `: C; H7 r- F: @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! w2 _* b" s. r% }8 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 V+ `/ \6 E6 ]) S$ K0 W. CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# }6 Z9 A9 D+ f% A, D1 Q
| MCASP_PIN_ACLKX* \: B: A9 H9 f }; T% H' X
| MCASP_PIN_AHCLKX
( e3 d7 d& p4 l0 x( `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 \/ u2 G, t0 E. k/ W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
n( ~" O; h/ ]8 p| MCASP_TX_CLKFAIL % f6 t: c0 V' Z' F
| MCASP_TX_SYNCERROR
% w) J' r8 R% c& L, ^+ L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( u" B" i; f# b4 I2 ?8 x! w; h| MCASP_RX_CLKFAIL. V2 N. b0 a; h( i2 ]
| MCASP_RX_SYNCERROR 6 }; r1 }/ [3 Z6 ^# O( A3 S
| MCASP_RX_OVERRUN);. d9 f9 U ~- Z# _0 N( X- l) c+ y
} static void I2SDataTxRxActivate(void)5 ?( ~! H$ A4 t$ S: P! o, _; ?
{& B0 S0 p4 |" q
/* Start the clocks */
/ a1 U; T9 B( \6 B- k9 P; rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 v! L9 ]3 m& X9 q# X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: i7 ?" n0 ~7 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* v1 g+ ^* B v! r) _) h6 fEDMA3_TRIG_MODE_EVENT);
7 r* F8 M0 _( W. j; G( n/ K; y9 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! K' i/ {6 a0 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 a0 T+ E6 }2 v8 U/ a9 j+ u$ W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# e8 E0 f H' y- n& c# n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. R4 m: o) S3 G; qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. |& q; z( J+ A: j; Z7 v) L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, \( p6 g2 }% C. v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 ^, Q* T2 p: {' _0 o1 G$ \
}
; @6 r9 f) j3 k' n7 f3 q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. z/ E1 _; k/ Q
|