|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ g0 F" `0 s( M4 A
input mcasp_ahclkx,. V$ h$ g" R8 u& ^ V
input mcasp_aclkx,7 l% t7 L6 z! i# Y5 T( L) Q& b
input axr0,7 ?( y% H$ W% }
; e3 J! n7 v( O+ Xoutput mcasp_afsr,$ x# Q1 D5 e9 ]- {( p
output mcasp_ahclkr,0 `1 D1 k# K# Y z9 P' X9 o
output mcasp_aclkr,# i9 ]8 ?, L. K- ?1 K
output axr1,
. h. _, G3 a* Q' e+ L# t assign mcasp_afsr = mcasp_afsx;
5 I; s. [: E: e- j8 Dassign mcasp_aclkr = mcasp_aclkx;1 I; n; N4 s% L r' n6 v! S
assign mcasp_ahclkr = mcasp_ahclkx;2 Z" c: |' \' W' W* A- i; o
assign axr1 = axr0;
5 B0 I( Z1 H5 h. k& b
1 O$ q" r( S$ j) c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( o, r! i: s/ W8 j0 I) P7 Z9 N8 Y k
static void McASPI2SConfigure(void)4 w6 y* [& D3 j
{% @* H" T+ K! g1 w# u) `( w( u5 ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; J% @; `- ~7 e3 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 T+ [3 n- X4 F7 q5 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. W& v$ t. w# c1 v3 f4 d. b- R/ k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, _1 q; Q& r& \5 { k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. f) [" d' ]8 j3 n$ h+ P6 b0 w+ a% |
MCASP_RX_MODE_DMA);1 }1 l0 W+ c) U- z% ]* D' ?% ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' e; U- V0 C6 l, mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% Y8 n4 l" K& o2 \" f4 F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; M% r; ^7 \+ e( i F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ W8 M" `- P$ A' }! A. \) `" X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 N) c* R, j2 F& _8 `4 f2 M) `* N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 A! L6 O1 e7 U, Z. xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' O0 R& P" M0 i* G6 Z6 k8 s- RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + }/ U3 J E7 {) ~7 t# T1 l3 H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 s% ~/ q; _" M; j& N6 K) m
0x00, 0xFF); /* configure the clock for transmitter */
0 a4 V4 B' y3 t: nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) C% Y( N- W. r5 T) y7 bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , @$ W% n4 Y6 ?" m2 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& h0 s+ y" m5 V. Q( j" s3 r0x00, 0xFF);$ j! W' |3 }* v- N
* c& p9 x7 N5 @( E2 i& n( j1 t
/* Enable synchronization of RX and TX sections */
( Q/ L- n% K% nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% [- F' S( ?3 f ?2 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 v! P" u( { r+ ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 W( h, _6 m* ~" K** Set the serializers, Currently only one serializer is set as
, l2 j) k- A5 h** transmitter and one serializer as receiver.
* V* ~1 W: s' C6 j0 R*/
+ m5 n7 I. f4 F+ }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 b; ~; x6 q; l, z# t& j# E3 ]( v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; Y f0 }: O. N& X2 o [; }2 K
** Configure the McASP pins 4 i J9 U1 p' \4 p
** Input - Frame Sync, Clock and Serializer Rx% ~" Y* ]$ T" b2 o4 C
** Output - Serializer Tx is connected to the input of the codec 4 E) _% C$ a+ h- R: m2 c* W
*/5 F' H! i0 d( ^9 I5 N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 s" p5 d4 Z) E/ x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 Z* R3 d( U# a7 `# H5 V! u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) _, [: A5 g7 j3 `6 C A% }
| MCASP_PIN_ACLKX& F# {2 \! }' Q
| MCASP_PIN_AHCLKX; o: C+ n P% s# Z; Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* @5 r/ A. C& m( d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . E* l3 i3 g1 p" z
| MCASP_TX_CLKFAIL
5 F6 q3 o0 o6 A" || MCASP_TX_SYNCERROR
- q5 W. \! S( `7 b, c3 F9 P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + S6 N9 d! Y: |1 p( m
| MCASP_RX_CLKFAIL1 T/ [8 i! D+ Y' L) |& m
| MCASP_RX_SYNCERROR 4 }& C8 z% q& I \+ V! ?/ I
| MCASP_RX_OVERRUN);
) B1 B6 D1 b5 H2 I4 h# X} static void I2SDataTxRxActivate(void)
P5 l4 b9 s. d8 o( V$ l( |{
) n# }5 k% S8 ^/* Start the clocks */* u3 P7 V2 `0 e6 {: o9 i. g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 c2 ~+ n$ R2 h, JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 R2 Y7 A P" d; r5 x/ {8 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 Y. f3 ^, L# I8 J# nEDMA3_TRIG_MODE_EVENT);
; T3 A' R+ \8 C. U+ e5 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" g- u0 w* I* W. b, kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! t0 i2 W! G: {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& m1 g4 y0 q7 ~) K0 k/ S; S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" g) I# y. r8 ]" i, \" Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 ] D" H( Y/ L( o# ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) I1 A: Z6 x; }. n9 D& T) I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) {1 n! e( e+ ^} # s: ^7 B7 F8 K/ G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + o U1 I D: k7 W+ E- N- {
|