|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 j8 v3 _. a- u$ finput mcasp_ahclkx,4 f7 q H/ ~) _: L1 y9 J) w
input mcasp_aclkx," I9 J. t0 ?, w
input axr0,, @' t' l5 t* F d, s3 Z( o
) R( a, {2 P4 e/ O9 i/ \
output mcasp_afsr,
7 A4 c3 P: D# N3 @output mcasp_ahclkr,
% l! M: p4 q! e# C0 H/ S; Foutput mcasp_aclkr,
) |9 V1 W5 F5 d0 @output axr1,
+ B* E" d( @3 f. u7 ?' C assign mcasp_afsr = mcasp_afsx;2 P) d+ }3 m5 L$ y: ^* ^$ M4 F2 \% s
assign mcasp_aclkr = mcasp_aclkx;3 Z, [% h: s% Y% C( G: X
assign mcasp_ahclkr = mcasp_ahclkx;
9 \* w0 E$ @' v5 w+ d, iassign axr1 = axr0;
+ |9 ^4 R6 l9 e B( o/ p& X7 d, g4 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 L: C- I, Y& o! `% g9 C. d$ C0 }
static void McASPI2SConfigure(void)
& w6 @% x& T! N4 g) H+ f* r, C$ M{
2 ^/ y5 V" I9 ~9 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 O: H+ U, }7 Y# B! I! q: h. s/ k: rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 Z' M& d! z7 k( E! r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 I# L$ x# ?( B* v; M( c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ ~; _) U& r$ D& l) i/ j6 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# t/ w3 f: c8 k0 X
MCASP_RX_MODE_DMA);
7 D1 d& Y3 G: ^3 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ e" y# J6 U' k# g+ wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! _5 ?$ ~8 N" d; n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 o7 l. `' n' t1 D+ [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 [) k( n! X0 `% j' f9 S1 V, f( sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 [2 R) |4 k6 f) ]! Q! }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 `# m1 d) U+ y! X7 |7 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' T' {0 @) n1 m7 J; M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , g L' x: y/ o: O8 j/ F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' g2 D) }( k+ K) h$ a3 V% z/ f
0x00, 0xFF); /* configure the clock for transmitter */; V2 U# ~2 _' U1 c) h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: R, q! ?$ g% H% M/ ~! g7 g/ G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 `+ P$ _5 [1 z7 a" \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: P3 ]1 u' p! D4 T, h7 ^7 r3 U0x00, 0xFF);
( p4 P: f5 a& S* D( s& k' P( [7 J4 M1 \9 }0 K/ ]8 Z: l9 K$ a
/* Enable synchronization of RX and TX sections */ * M4 P% u9 {$ v8 W* V5 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 o* [! F3 R) | Z% e7 h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 q9 a0 `# j/ i' GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- a+ b9 q; a# y. I" ^% s3 F% ]# Z' A2 f
** Set the serializers, Currently only one serializer is set as1 h0 m8 C L" H
** transmitter and one serializer as receiver.
/ q! L6 i2 Z9 @7 I*/1 Z6 Y7 H% x4 u6 y9 I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; t) I9 x- S2 e% m& Q& v. |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" u: G7 p" n4 [8 g& x** Configure the McASP pins
: Z R! R! u& Q/ j" E( z" g** Input - Frame Sync, Clock and Serializer Rx8 H: B/ ^+ _! e2 m
** Output - Serializer Tx is connected to the input of the codec
) K( F# A* u& W* u*/
. I7 u. {1 l1 _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 G! Q- j* K6 f/ b; JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) u6 Z }( R0 M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& A8 O" J- p4 m: P5 j! c: @# P3 h
| MCASP_PIN_ACLKX8 `8 N, L& m3 }; I8 A1 K4 P1 e0 h
| MCASP_PIN_AHCLKX
! t3 [: Q8 {, S0 c% `$ X) b8 C) g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( c2 z& Y4 x; P7 T' Q2 `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; e, C' }1 G7 Y6 h, X f* f! t
| MCASP_TX_CLKFAIL ! a: w3 U$ }" a+ s+ b
| MCASP_TX_SYNCERROR9 G. @1 _- R! ~5 \1 L+ }0 d, C/ ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 x$ S& A2 T" d| MCASP_RX_CLKFAIL
! P9 H) T! T/ A( U) P- O| MCASP_RX_SYNCERROR
8 g0 D' g4 x3 `0 ^6 a8 x| MCASP_RX_OVERRUN);" X* A$ o2 i1 R- D K2 [ d
} static void I2SDataTxRxActivate(void)9 ]8 o2 R( N% o
{
: ?& l; `: b4 k6 \, I- I! I, K/* Start the clocks */* a0 D' P" r# r; U k6 B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 b, f \: R0 ~# w6 u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- W" Q" a2 b2 K8 y( @! N2 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ A/ c# {% s: w8 G/ t! t* B
EDMA3_TRIG_MODE_EVENT);8 q7 u* e( `6 y2 ~2 {: ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ ?5 ~' t) b/ o: j6 W/ L) L1 I$ \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 R0 x; V# a9 C6 S5 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 O. w$ [. O6 ~9 t. mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) f1 g5 D( c9 I- q2 e5 [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: w9 ?. L1 S5 f& ^: V AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. p3 v1 q1 g. A* H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 {/ u" Q) G7 ^8 O6 t" V& h}
; h0 X9 x. L3 _5 L' \; }0 Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 D" {2 I7 r/ y- J
|