MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
( A/ {5 ]8 b% b3 O9 einput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

1 g% N  d! y- Z( r' o1 T* h- qoutput mcasp_afsr,
output mcasp_ahclkr,
) q. ?+ ^& d! q, ?) H. Loutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
3 u: K, f1 G& w" oassign axr1 = axr0;

- F/ v6 e* j$ p1 ~. b$ \

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
4 a" i* e/ N' }% H- R{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% g$ p. I7 M9 g  S! N) ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
* F. |  T& e, |) z$ w( MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 `3 ]8 x+ V: O/ Y9 ~MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* T3 S" e. V) v* [3 `9 @' y. pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( l' R& ~" q6 Q4 d( pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
" i) G; v& A5 [  T" Q; o) Y& V: ]; JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# k( G5 B; K3 v+ [( t/ NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
% u7 f* d$ `5 m& L& UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, i; ~1 J0 M2 ]9 C9 v& V+ a" {' y  N% w0x00, 0xFF);
8 Q0 D2 F( P7 U' @0 ~6 v
2 d3 z$ a: S4 x/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
5 ^* ?8 u9 G* h" J  j. k# n** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
2 f8 s4 N2 Q) G. A) |+ X6 Q: B*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 U$ Q' I$ ?* S* ^4 ~# WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
/ L2 q- A( Y4 i+ a2 L& J2 M** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
5 g' p0 D% w' UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 N5 B& C* U( X! m# h; eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% D# i& ^, P* N+ |/ O6 o| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
7 i1 j* Z4 p- H1 hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 c* C- }7 F: B. W. a| MCASP_TX_CLKFAIL
* O& `$ u9 L: s2 B( N5 v! K| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
! ~) z# I" A7 U| MCASP_RX_SYNCERROR
& E  f5 Q* b; a# Y- g| MCASP_RX_OVERRUN);
+ J. A+ Q8 P+ w5 v& F( `0 i+ _}

static void I2SDataTxRxActivate(void)
/ ]& v. }5 D' r7 q{
8 n8 g/ e5 u5 `# h6 C5 t2 g7 ]/* Start the clocks */
4 j9 ~& l/ U) qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! C) A7 v2 N! \- XEDMA3_TRIG_MODE_EVENT);
. L/ K6 H9 V. i: f# m# n3 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) c# s+ y) {# |/ a6 @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
3 D8 m) d: I3 K4 z* l9 K* LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( R; A$ e: ~4 h! DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
0 U+ X4 r8 W; c# o) d) [3 X. S, xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

6 F7 O$ E+ i- |$ `6 n# G0 v) Y; \7 u