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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, {. @) s% Z+ s- N1 {input mcasp_ahclkx,
) e; J/ M S0 w- {input mcasp_aclkx,
7 t+ ?9 Y; r/ s" o8 t; S% D% Pinput axr0,
" S4 J8 R$ V, f+ t j
/ X9 O# T- m) ~& I7 a: D! B! Foutput mcasp_afsr,* Z& `% I/ [: h) ?
output mcasp_ahclkr,
2 X- ~; `8 U( A+ ^! qoutput mcasp_aclkr,: ^1 W' z4 `' W3 w: P+ v" {1 H7 D
output axr1,
7 _0 @% W Q% r$ |# ~0 H0 {, a assign mcasp_afsr = mcasp_afsx;
8 o8 @- @$ D& Dassign mcasp_aclkr = mcasp_aclkx;
" K" R, ~ V7 g! O7 Z: V2 Bassign mcasp_ahclkr = mcasp_ahclkx;0 _. F% A% [% ]
assign axr1 = axr0;
3 ^' |3 F& F! d3 _* c. q8 K9 r Q% `' P/ I5 ~4 t; Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 c& D9 S& E8 s9 C3 fstatic void McASPI2SConfigure(void)
& I1 [+ X! |5 r$ _$ V0 y& n{
8 ` E* `1 z" E |$ X# @; S' Y2 |McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 `/ o/ \4 ]5 f) {$ @/ J' F2 k# {3 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' N+ P# c% j- ^7 j/ i* A, Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; {: V6 P# |3 O$ R! T& z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ a) g5 m2 s+ q, I8 D+ e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. N1 w+ \$ J$ E% q2 U5 \ J
MCASP_RX_MODE_DMA);; r. P! `1 a: F- }6 r( v, B' y. _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ Q1 J$ ^# g+ U# h' [* x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 g8 d# w! w# f9 E/ PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ j. F3 N8 o" n V2 I6 }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( S% Y8 D4 R! O. SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) r3 ?, n/ |: m6 o: T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ ]; N% Y5 C0 m* H- e5 W8 SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
K5 ?* d& N0 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + s' m& v3 I1 @% p7 I/ ]6 |$ Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ J' B! z% c0 B
0x00, 0xFF); /* configure the clock for transmitter */. z* z2 M. i! W( z. Y- X8 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 h2 T- N/ L! ?: C8 UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 J! ~2 A- Q$ D$ O; J% {, t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( m- K2 Y; a4 o9 z0 I: l- k
0x00, 0xFF);
5 R% P, X+ f! i5 a) @
3 e0 Q9 s. @; V2 [/* Enable synchronization of RX and TX sections */ / x8 x% w- m! U2 w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 H2 O# e. Z8 C9 p( {+ q4 C8 |- IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 _& v7 w/ L; f' J8 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* F( A/ Y/ f8 ^2 y9 }: D
** Set the serializers, Currently only one serializer is set as9 D% ?% D( R7 L7 C5 @
** transmitter and one serializer as receiver.! n+ B: W0 e4 f4 D/ i9 r7 M
*/
3 h' u) T! W/ S& x9 AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, t- e* Z4 {9 E' L& Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) j" @) h# h! ~( E q' X2 ~+ u
** Configure the McASP pins ! U3 G, U& ]% W F8 y
** Input - Frame Sync, Clock and Serializer Rx
; o/ u x f% E# ^** Output - Serializer Tx is connected to the input of the codec
; o( i K) a2 m" G0 u; r2 W*/( K' M4 u/ L9 `0 F! z5 d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 k; L* f1 O, Y |7 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ s. ?4 z+ S/ y: p% U$ E) h e4 DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 U( `; t! n8 t! { N8 j
| MCASP_PIN_ACLKX
3 f# X1 X# o1 t7 {| MCASP_PIN_AHCLKX6 _8 u2 u. J# P3 b# ]; `: h: @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 H$ n2 a \0 ?8 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. U- W; ~. i0 ]' T5 s; i, Y| MCASP_TX_CLKFAIL 9 s. F7 H+ y3 C
| MCASP_TX_SYNCERROR
Y& ]' K0 h9 f# f4 \- ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 v2 U4 v" G8 D| MCASP_RX_CLKFAIL, v: B" H Y' h- l
| MCASP_RX_SYNCERROR
7 [3 X9 {% i' z3 T" i0 L| MCASP_RX_OVERRUN);; U: x" b: P8 B
} static void I2SDataTxRxActivate(void)
( B" i# _% a( n# G; z( T( w{
/ F5 G8 f1 ^; U# {$ Y* q; S/* Start the clocks */
9 m# |7 y$ [+ H8 d0 y! m3 M k+ M3 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; `* e/ b0 ?+ z$ v) eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( n6 ^3 x8 z$ _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% s0 w/ W: g# |. y$ m- Y3 H/ X* _$ o
EDMA3_TRIG_MODE_EVENT);% A5 |1 w- y6 V2 ]3 w* g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! _- l2 [+ J% U8 {6 }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& w. A0 Q+ {4 J2 O, N6 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# ~% h8 x9 ]/ W( l7 L" c/ RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 I& J9 C- w# J/ H+ Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; W8 X' ~5 _) N( O* [/ G6 k2 f3 @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 Q0 o3 B; M* N: m1 [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 [. ]: J8 D k' @} - M' n8 M8 R& _4 q3 k% f$ p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . Q1 t. a4 d5 p, u
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