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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 P% B. ^* |; C3 q9 i
input mcasp_ahclkx,$ G) q2 ^7 @' V9 ^8 x
input mcasp_aclkx,' P. n9 o7 c, e& q0 `; s! g- ?5 x
input axr0,
2 t; s) D7 H, y8 @" \+ l, s
4 t* [$ y% ]7 Q; X9 |! Woutput mcasp_afsr,4 k5 s( H* ^; X
output mcasp_ahclkr,
6 x4 Q8 k) _1 t* |' W0 K# soutput mcasp_aclkr,
6 ^4 i; y9 v/ U9 U' k! g* Z& G2 Aoutput axr1,
: s! k$ o! F, l4 k$ M& b _/ r assign mcasp_afsr = mcasp_afsx;% N3 O, Y2 }9 h) t
assign mcasp_aclkr = mcasp_aclkx;. X( \/ o# ` X6 d0 e E/ G# ~
assign mcasp_ahclkr = mcasp_ahclkx;
* x% j/ n. G- H: Q6 Aassign axr1 = axr0; {) k1 P4 A$ N8 c5 Q+ W
/ U+ R/ E3 p" c J: D8 ?- a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- m% |) K4 B2 y% }0 B% z, Rstatic void McASPI2SConfigure(void)0 h& Q1 x" M& J% [: r
{
* G+ R" V8 y! W2 I1 f* oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 B% J+ l2 Z8 k7 M' AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& X9 |. E/ h, V' g7 ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- z: Q4 m$ i9 s# o- j4 [3 l$ v( e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" `( {" S/ ~2 T, v) W9 X- ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 E7 i$ Y& d/ d7 U' c% rMCASP_RX_MODE_DMA);
! [ ]4 o, I/ m( AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ?7 s% B; E& ?' n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# ^! C- c& ]4 N( S( @5 B O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 j4 ]1 y! \0 O( `9 m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 t- |' i, L0 Y2 k7 @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' ^8 ]5 n& S) A! _- V9 H3 NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 m% x! ^/ Y. D- X; T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- t2 l& C* e, {" n: i( d- \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 P- H, N, E6 y( o3 a# L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, a' K( m2 m% v/ w D, M
0x00, 0xFF); /* configure the clock for transmitter */
/ F' v" c5 z! wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 j! X+ n8 o1 H6 nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 q2 x" F' B" D! Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," B m7 `% y$ |4 o/ F5 T
0x00, 0xFF);
- N9 `% n) T/ ~# A9 Q
T) f$ u" Z' {2 Q2 d6 k' M2 i* V, B/* Enable synchronization of RX and TX sections */ 0 j8 y3 V9 X8 Q* c# ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, A% b1 c- L2 _! E+ B" oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; O: ^$ j, w2 sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ G6 K7 [' j* T8 f* Q( z8 M
** Set the serializers, Currently only one serializer is set as
4 e! R3 W2 Y5 C( S6 j0 [4 Z# k** transmitter and one serializer as receiver." i* t8 m1 u; j5 F' _
*/
' A3 ? Z! f) V3 ^* o% hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) s- _& j( z2 C" _$ p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# `9 }; Z8 L' l% J7 P
** Configure the McASP pins : f) D* v1 ?- S- E0 s d/ r0 ?/ A
** Input - Frame Sync, Clock and Serializer Rx% X! Y- W" f P- f% z
** Output - Serializer Tx is connected to the input of the codec
]6 |$ |* D5 Q*/2 f" R g8 {! f: p% _1 i1 _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 [3 l( H9 G0 X) N: b. dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 V2 _5 Z; X# M2 w6 E9 X1 ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 b" w1 \( R& k* _4 X
| MCASP_PIN_ACLKX p3 L, O, H- O- T; s, ~
| MCASP_PIN_AHCLKX+ u; R) k( g- w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 {; D1 n# O% C/ s! b B1 t' UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( y5 {! c# s+ M! k. D
| MCASP_TX_CLKFAIL 1 u# c0 H) X# l7 K5 K) N+ _& s
| MCASP_TX_SYNCERROR& J2 X k( @7 O a3 [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; P) r0 ?; i' R' u% u
| MCASP_RX_CLKFAIL
/ q, G! Y& }* t4 G| MCASP_RX_SYNCERROR
: s2 |9 R- p1 L: T| MCASP_RX_OVERRUN);
9 I5 H- o/ o$ S} static void I2SDataTxRxActivate(void)4 @* J! t5 e7 a- Q& _# v t( y
{
. c) ^ h* r9 P! h. T2 N/* Start the clocks */
. u. ?% h& H# t, k) E5 [ ]- |$ jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; i: c5 n/ G0 e& `" R. ~$ aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 `4 g; `# A7 J4 T3 i0 H0 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' ^7 ? f3 J5 X1 A
EDMA3_TRIG_MODE_EVENT);
6 g, K8 o& A" ?; I' m/ Z$ L$ r# oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! X3 `( `) E" x" y* F- K* DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* y9 q# n; X4 s/ i. M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 {' `( L, L" U! o* e/ F2 i" u( W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ w3 u" p7 v1 _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- o6 n s: `, ]5 N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 R! Z: T6 ?- B3 P, qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 W. J/ h, p9 X* G# `, u$ F
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 v- Y$ z2 m/ S+ z
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