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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 |9 Z' _: A0 b$ @* D6 }2 }6 h4 R
input mcasp_ahclkx,
0 |4 J z+ @) g$ Z1 linput mcasp_aclkx,
3 ~ I5 f' T2 T! d$ }$ n" J' winput axr0,
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output mcasp_afsr,
! ~- A1 [7 v# H- P1 aoutput mcasp_ahclkr,/ Y% R" {: R0 u& Q) W
output mcasp_aclkr,! N+ |& E4 u) D( p
output axr1,+ b, A' Y& h0 Q Y9 j
assign mcasp_afsr = mcasp_afsx;
# i4 F" z; |! lassign mcasp_aclkr = mcasp_aclkx;
, M2 H9 d9 T: L$ L r4 gassign mcasp_ahclkr = mcasp_ahclkx;
4 P1 d" b+ [4 m& p8 b% k' M$ g5 Sassign axr1 = axr0; / i' }8 D9 T4 q3 e4 Q
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 o. l2 h: F4 s- M$ r9 k2 Y9 P) B& w
static void McASPI2SConfigure(void)
- [! E' T7 u0 \% F2 m{+ y- M1 c2 y1 a/ z* Z% ?0 O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! \+ w5 t! @ \7 W1 C8 `6 ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ {0 B" y) }% S/ N o1 @0 S+ |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ P% n7 f5 h6 G p" F& mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: x* O H7 A' T: qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ i7 F9 O' K2 F; IMCASP_RX_MODE_DMA);8 _; a) u5 q% C- n+ A; y; ~0 G. y$ i& P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, w; n, m5 |* _2 ^0 \$ x+ [9 G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& k# ?) ^5 n) o' B5 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& x( e$ e4 H( i5 TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 \ P, k* T5 c8 `; AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: }+ O6 @" o) sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: T! G- {; T+ K) [& Y7 ?& `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ n: F* t$ F" @' p$ j8 t' y3 PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! K& j# n) `9 K5 V" P. S$ c- UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ z, ~! B% L5 H+ B! m5 K/ n$ h* p0x00, 0xFF); /* configure the clock for transmitter */
' y% s/ K9 n1 F2 tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" N: R% M+ p2 x/ C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % y# F% W; H" i9 s' Q5 a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, O' ] N( P# n$ K! W7 `! O
0x00, 0xFF); u' o& `8 S9 y; b3 F
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/* Enable synchronization of RX and TX sections */
- S* R8 t: M5 L) s# G4 M5 {* h# xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 c. L3 ?! z/ ^6 J# j" k3 ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( V4 D5 b0 I1 K/ B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" q0 K& C7 g% a# |
** Set the serializers, Currently only one serializer is set as
3 u6 J8 q5 m8 h, \1 ^9 ]** transmitter and one serializer as receiver.
# v7 _) a9 g9 Q6 q0 u8 o# R*/1 R0 T2 S* Z; u3 n# X% ?" x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ u! l: X# c. Q9 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" T6 p& e% l: b) [# ~& v3 Y! C* j& h
** Configure the McASP pins
9 R! [$ m9 m( O1 H- U8 z** Input - Frame Sync, Clock and Serializer Rx) s' u7 u$ Q7 E* G* n
** Output - Serializer Tx is connected to the input of the codec
, Y9 s. k* h; j }+ U4 \" }0 {*/
% p- G1 z% f; SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' w* E7 C5 V; \4 \# P) rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ X! x& C; d; `5 C) RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& E. ^2 J( M" _, e$ Q| MCASP_PIN_ACLKX
; k$ {4 t/ L4 z. A| MCASP_PIN_AHCLKX F) e W; N, ]: ]9 J& p2 O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! T9 M8 h" E0 h' M- S! z9 [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ b: L6 f: C6 }1 |
| MCASP_TX_CLKFAIL
% x: O* B, {( ]| MCASP_TX_SYNCERROR4 f3 ^" ^9 |9 r2 O3 ?4 L: l# L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * |4 |# k) w0 E; V5 ]2 z1 ^# A& C
| MCASP_RX_CLKFAIL& x9 t9 q' ?0 f/ u
| MCASP_RX_SYNCERROR
+ f! L2 p% v3 G| MCASP_RX_OVERRUN);
4 Q- h; g$ `% c Q& D+ A# w* h- u} static void I2SDataTxRxActivate(void)
' R- j" X% R% v( n1 W) [. u{
$ o. K2 k3 V L2 B" E/* Start the clocks */7 I- Z& {. q$ g' W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. G# ]& T5 q- yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, N1 o2 f8 K8 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 R+ ^8 n! V @+ B2 YEDMA3_TRIG_MODE_EVENT);
, r' ? [3 I0 T& z5 ~9 N( C' P( GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 Q2 H, y1 \9 D3 D M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# O6 E; o; M( d' C) p# X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ x$ i5 q& ~% Z9 q2 P# P2 z! PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& ?- @0 L1 ]5 Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ k, y* b w/ A5 F' }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 `4 [0 U" b3 d( y! n/ \" \1 x6 eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) \. f. A) ~% r9 L} 0 _6 m% Q/ z L# O7 v6 H: L6 d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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