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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& y+ Y( W7 F8 n' h- Q
input mcasp_ahclkx,( W+ Y" e: q) [8 q% T X
input mcasp_aclkx,; u+ j3 z' [% c9 ] j! t
input axr0,# w; u7 X3 l1 n# M
1 H4 g" r9 `0 }output mcasp_afsr,5 U" s6 C' @+ K# ] z
output mcasp_ahclkr,+ K, O( s1 b$ O0 f; ^4 y
output mcasp_aclkr,# H; g3 f* r+ W/ i6 h; i% r
output axr1,
& f5 M- r/ E9 t5 [+ r assign mcasp_afsr = mcasp_afsx;0 \" u5 d) E3 U& S% V
assign mcasp_aclkr = mcasp_aclkx;
. P) h1 Z+ c* O: z* |assign mcasp_ahclkr = mcasp_ahclkx;' T* A# Q: G4 j1 w* s9 s0 l
assign axr1 = axr0;
0 P0 f) _! Q$ J: x0 T4 W4 x3 S, n( i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # ~/ k6 J. c& R& d2 a& ^
static void McASPI2SConfigure(void)0 X) n8 o) a, D8 K6 u: o
{8 x) D- c- N3 V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! \0 Q& w" N4 |9 f7 RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) E) n; J8 U3 n- o M) I* z, h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# o1 Z9 Q" F i' @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) ?& m4 X/ T' ]) U' I2 c8 r" @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 A% f- g, ^( P' t' J0 [8 Q# y8 [) M) d
MCASP_RX_MODE_DMA);
! E4 M3 N0 W& q: i: kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: M \" }1 P/ c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 K/ P; g$ q# g4 Y6 m0 K8 R) w" u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! H7 s. q* r: WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: j+ `& _3 W4 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . N9 S1 [5 V2 `# Q# M9 o3 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 p- d* g; j* T) J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. d) x! ?4 p Z+ x$ ]0 VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. S! D6 r" z% ^' BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," x# F9 [' k: D8 s) K- _( j6 O
0x00, 0xFF); /* configure the clock for transmitter */1 P* O' r) z5 [4 i, _* V. ]2 t b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 f! u7 P- i- w8 _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % V+ P q! I, Z8 h! W+ H# s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 [7 H4 y3 \$ @
0x00, 0xFF);2 K% M9 R7 \7 O
) R& s2 q" u; q% s5 f( l$ z
/* Enable synchronization of RX and TX sections */ / f8 d& d) n! ?6 Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ K6 p! h9 I, c3 o4 {' w" OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 I, L9 x4 }/ t# ?) S/ S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% {# ~, v8 m3 Q- ?* |+ J( K& F
** Set the serializers, Currently only one serializer is set as6 U0 i/ @6 e8 Y+ R0 Y* l( M6 e
** transmitter and one serializer as receiver.8 `* a8 S! h4 F( H
*/
& n) U6 M) n. i4 fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ V: \& e# J8 C6 C& x. QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' Z& B9 K8 Z1 @8 d
** Configure the McASP pins
0 k' q7 X; Q# p) k** Input - Frame Sync, Clock and Serializer Rx
+ n' I! g2 ^- [# ?2 S** Output - Serializer Tx is connected to the input of the codec
7 X5 Z& W: a8 f! @; G2 l d*/8 l+ }. q+ i2 y! f; F6 E' k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' V+ K* _; }: t7 U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( p( l. r+ K6 d; O, b. YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- P3 W" H2 J+ E) {| MCASP_PIN_ACLKX
9 m) r1 ~8 O# l( s: f) g1 p4 R( g| MCASP_PIN_AHCLKX8 y0 b5 s0 \2 d# E6 f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( `7 g! ?* l/ j) ^# BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ p- g2 m- e! L# u3 v| MCASP_TX_CLKFAIL
: b$ N1 ?6 }( J; t& E0 D| MCASP_TX_SYNCERROR! a7 p1 l+ f" y! z& u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) Q4 O* x3 P) ]: u7 a* [| MCASP_RX_CLKFAIL4 D4 j3 i5 m, v+ X G. G% n8 A
| MCASP_RX_SYNCERROR
' v- Y7 u8 {! r' x4 ]| MCASP_RX_OVERRUN);) \5 ?3 U4 x. ]% k% k
} static void I2SDataTxRxActivate(void)
9 E" q2 X& x: N. R6 ^- i{5 u4 E) A z8 b& N$ ], B
/* Start the clocks */- z+ a, J7 Q! M. d# I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 \( m8 V. ~- I% l. iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 P. N! `7 @* {: {( C5 o. \# c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( v$ |1 F. ?. O; LEDMA3_TRIG_MODE_EVENT);
) n" H4 C! h( r/ F5 N4 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - T U% f2 u6 c- h- D" ]2 j: V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ N2 u! i0 I7 c: q' N: d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; l* J' I4 }2 ~8 Y9 W" |; a! ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 T2 r3 e2 u0 V- a9 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" q- I1 ~- z& G6 i$ r& ~: q( EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); A! ~1 A- c( `/ Q! E4 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' _3 Y3 C z* t# [+ p# S
} " D6 m0 ?# ]* w$ n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ ^+ Q: t5 F* g
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