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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& d3 }8 e% r7 l1 K, [& ?
input mcasp_ahclkx,
, Y. p0 J% a8 `3 K- Ginput mcasp_aclkx,
4 v! Z' |+ P/ z8 i( @input axr0,
0 G" W4 `. n$ z5 V/ e- L H" O' j( L- z1 h# _& B$ o; \3 b
output mcasp_afsr,5 I" q- X; l$ N3 q1 m2 G2 \8 r
output mcasp_ahclkr,9 V6 _+ v) E z/ a
output mcasp_aclkr,
: E! h$ ^& J1 V' Houtput axr1,0 R- x6 _% s) O7 I6 z0 B! S
assign mcasp_afsr = mcasp_afsx;$ m8 R4 p# w9 B- ?+ v) X6 q
assign mcasp_aclkr = mcasp_aclkx;
' n( { G% L7 @( A! x8 ~% Fassign mcasp_ahclkr = mcasp_ahclkx;$ f- y: Q/ T4 h! y, P
assign axr1 = axr0; 4 z0 ]( P9 [' }
; y% }' \( V2 m* T. S& M+ P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" a2 N- h' K9 F. istatic void McASPI2SConfigure(void)
& `; l8 P7 \2 U$ t' w% \{( h/ ?, i; Y% S+ E- o4 S% Y# B7 Z" B3 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 e/ _( Z% E2 n) R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// b8 X/ [6 X1 P" P0 Z3 K) S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ S. {' [2 M1 G# j' t7 D0 [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! U$ e" n6 e( `4 F# e1 p jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ p! ^* M$ a5 d4 E5 cMCASP_RX_MODE_DMA);5 G/ j2 K# A) [5 K# b; t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( C2 e- A9 W# c9 B- {: g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 x1 [7 q$ H r5 {- L! a( k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ a0 p9 R) S# I- qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: C7 B+ l D- n$ @$ ~, P5 j% p5 Q6 @" ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# j9 ?$ Z# I, Y( [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% C( P+ |0 B: @% D! [9 o1 oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. b# u% u' Q, N, K( O- b% aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " ?3 g- `; m: s K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- s% \9 l7 X/ Z, f; g+ O2 g$ \7 s
0x00, 0xFF); /* configure the clock for transmitter */
) T: |' Q2 Z* D0 cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; U( B+ @, g x M- ]% pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 e* i9 w* y$ ~' O o" e9 p" N$ QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; J9 o: I+ D# g8 }
0x00, 0xFF);. n, q, F& {2 n* Y3 Z
% z1 a9 U5 e/ c: g4 D; Q
/* Enable synchronization of RX and TX sections */ / s% \8 `# p1 w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% A; |3 E( \& h3 v* v& U! L1 MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# F0 h9 c. Q" UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! l- A$ _1 E( g+ T, k9 P6 l
** Set the serializers, Currently only one serializer is set as5 b1 R7 X+ h7 P( m
** transmitter and one serializer as receiver.6 \( h- ^" B$ V
*/
6 ?* T6 M0 b9 l* ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 E3 D# z6 F+ d, F( v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 o) N0 N `$ t; S2 _, o8 T
** Configure the McASP pins 9 r0 O2 D" r @$ B0 K1 h9 C
** Input - Frame Sync, Clock and Serializer Rx
7 v" k% H/ O( y$ |) l** Output - Serializer Tx is connected to the input of the codec $ Z4 }# s" ]6 ]( x
*/
1 W2 {1 f8 ^+ X! i/ ]- s, hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( x% O5 p: ~) |$ c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' } V1 q; o! v W2 H) q8 eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" d' S. A' e J& o9 F5 h9 b| MCASP_PIN_ACLKX8 R v. p0 }" m0 T
| MCASP_PIN_AHCLKX
5 D) [6 g+ ]: v9 V4 U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, K' H4 p2 c7 Y4 ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 Q D7 @4 k: y* Y| MCASP_TX_CLKFAIL
6 Z7 }: f5 Q ^1 K' D| MCASP_TX_SYNCERROR
0 y0 J4 \5 ^0 }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & z$ w$ k# h8 T8 i' F" z* i( M
| MCASP_RX_CLKFAIL% Y4 t% c# }7 Z+ _' _
| MCASP_RX_SYNCERROR
7 E! Y$ }$ j: ?4 w C/ ~9 |: N" w/ u| MCASP_RX_OVERRUN);
7 p3 j7 x6 O; M9 K* B* ~4 J- P! j/ d} static void I2SDataTxRxActivate(void)' T/ b2 ^: P4 t; Y: M
{
4 F; o) I1 d. X2 L/* Start the clocks */+ g( h6 v6 T% p9 g7 c$ H7 J/ C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* m3 _& H! g- e% t7 kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# W, a4 D1 R/ L& F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 r/ z( t/ V, aEDMA3_TRIG_MODE_EVENT);
* y+ o& U# z: x( a5 A7 s8 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 p' X0 G: \: @5 K; q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& p) N% }6 ]' i) n7 K3 `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) L& n, i @! GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% P# B; M* e: jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 D: V% C. ]' ~+ f5 oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 ^/ A: [7 K& k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ L0 E# G% U E. p6 V' Y% X
} + y! |, F0 B3 D3 t8 Z8 u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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