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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& v; `1 z! ~+ e' s9 \4 U, s; S1 Finput mcasp_ahclkx,# ], l4 k' \6 E+ I- L8 w
input mcasp_aclkx,) s; K$ z0 O5 c& e. }, {& W
input axr0,: J/ C. j) S6 N$ j3 [/ R
5 D+ u/ D+ {! D+ a; B; loutput mcasp_afsr,! k6 q4 a% b* Q, g! t& s) u
output mcasp_ahclkr,
- y9 x7 x3 n% x7 g1 Toutput mcasp_aclkr,
/ r4 v6 Z2 @* l0 eoutput axr1,
' `4 q; I# ^, ]9 v2 F' M assign mcasp_afsr = mcasp_afsx;
* r% I2 K: u, \; H, Z5 D7 oassign mcasp_aclkr = mcasp_aclkx;6 |3 a2 g, T9 S Y7 w
assign mcasp_ahclkr = mcasp_ahclkx;
( f5 s+ O! v3 R9 F$ w. G9 Vassign axr1 = axr0;
: c" L- t1 l5 m3 s3 I; Y ?+ c2 Z7 u% J2 v& q' y6 Q* K# V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - G; s7 ^/ v& F$ x& j) o
static void McASPI2SConfigure(void)5 M3 q, p5 Y2 i. Z: [1 b% H
{
1 J5 V" |0 Z z% K/ V. i: k8 AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
W' H3 b6 p9 s, t! zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, R7 g$ p/ U+ j2 E- u9 d8 q2 dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, u7 F" p1 {) |1 u" w7 \2 r7 `7 t: XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- Q2 n9 n$ ?' W- |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. Z" ^* g( ^/ d0 g7 T7 h8 `
MCASP_RX_MODE_DMA);
4 `9 O' Y2 f( o) wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; E+ z B1 m, l wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 U* t1 c; l L# SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 U) v/ w) F) d1 ?) ?4 l3 gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 |* A5 n' E; _/ TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 H5 x3 s# e) D+ G4 t. AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 Z, `3 `4 r% x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* C. H1 E) s, J2 X7 M' {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); g) @0 g: a6 F3 j- B4 z3 r% @" p# }' X/ S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 r4 z, o; w" Q7 J$ E
0x00, 0xFF); /* configure the clock for transmitter */3 b# L S# u2 b( f0 x: i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 L+ {2 {; ^ Y$ IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& F5 J; f& s* e2 oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 M3 q# T2 L% m( \$ C, U+ G
0x00, 0xFF);
6 r8 q: x) r$ U/ V& p% ]" i" ?% f) w$ |* |+ o: A) f' Z
/* Enable synchronization of RX and TX sections */
! u4 r9 L$ B/ x% {! w4 DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ G+ ?6 K! q6 Y- y+ e, R# e. tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 z$ `. p3 `! j6 l5 d, P9 gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- K0 ~" B' w: Z8 K4 E
** Set the serializers, Currently only one serializer is set as
5 h; g0 L6 Q# D1 r4 F** transmitter and one serializer as receiver.
7 k" m* ~% X# s' R*/
! _1 n: h' [9 T: ^ ^$ JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ t: G/ N y4 M( P* j. K1 JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' a4 h8 @$ P4 c5 \# Z$ W( V" s** Configure the McASP pins 0 E2 z7 x" g6 {
** Input - Frame Sync, Clock and Serializer Rx
. j' h7 t% J( n/ B0 \; E+ E- M) W** Output - Serializer Tx is connected to the input of the codec 5 v+ _7 J0 A. x* |. M1 T
*/
$ I$ l6 y6 b: d# B" T1 w- ]/ HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 H0 A$ u6 h1 g2 n/ b vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) q5 f3 H' t$ a9 y0 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 X( B$ ]' E- b| MCASP_PIN_ACLKX
6 g9 [4 D0 ]4 ?% M5 ^4 s| MCASP_PIN_AHCLKX
6 u9 C; h9 S& V9 ] n+ w% h# `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- |' n# h+ o/ C6 }9 W! d7 ]( P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! v8 d1 s+ i4 N) P| MCASP_TX_CLKFAIL 0 B1 O4 p) d- R4 p4 }
| MCASP_TX_SYNCERROR5 h9 l7 @: P7 e3 P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 x9 c& _7 |0 O7 H4 a/ F7 Z4 G
| MCASP_RX_CLKFAIL
+ k4 h3 b p/ L( Z| MCASP_RX_SYNCERROR
+ l+ t1 `3 m$ L| MCASP_RX_OVERRUN);
, w: T# j5 W* ^- ?: I} static void I2SDataTxRxActivate(void)5 }/ K; ~3 C, T6 c+ l( a( ~( s
{3 J3 x& X2 h+ |4 G; X6 C
/* Start the clocks */
: x8 Q0 \) _ g$ [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
p3 ?3 S" t9 h( r& y, {" CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 L0 E% n) \& a1 I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; V6 T/ H7 r$ ~EDMA3_TRIG_MODE_EVENT);
0 o) @0 z9 v3 u9 a" E4 ?6 a! M9 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - R# y) m) R% _: I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. E9 O' X$ z' o2 M, D6 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 J! g( s+ {( v4 o7 D. B0 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 x( m& C( ]* X- Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- L3 V% B( Z1 E: ~6 l, S% a# a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- s- \) V5 [( E# A6 p. v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 |9 p4 G* r6 E8 M& i}
2 i: H: K! f: Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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