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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 i! o! r; z8 a' b& @3 b8 ]input mcasp_ahclkx,4 ?& G6 J0 I! p5 }* g9 c
input mcasp_aclkx,$ Y5 I# o2 h, A" K! ?- l- }
input axr0,
8 F& p% C. k( c' K A" }9 w6 W* T/ q( x* J5 u
output mcasp_afsr,7 f! B' p$ R- U9 O$ Q5 Y
output mcasp_ahclkr,
2 h& a$ q5 w+ O* n, z' eoutput mcasp_aclkr,
& [6 [& G2 W+ s/ o4 soutput axr1,7 A- n) l; c, H. Y/ V1 y, P2 h
assign mcasp_afsr = mcasp_afsx;& @$ z2 u5 E0 y8 f
assign mcasp_aclkr = mcasp_aclkx;
( a2 f' D; ?7 B5 Aassign mcasp_ahclkr = mcasp_ahclkx;
. X3 h7 t- r, z' c" z; Uassign axr1 = axr0; 8 @* y# b) a( y7 @( I Y/ x5 u
+ K( u7 B$ B) s0 _5 {! p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 u% P3 D( D I3 y
static void McASPI2SConfigure(void)$ V+ h1 B7 L2 y9 b. n
{
6 F: T6 ?; d4 _% k% _5 S) ?8 p mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 d- P1 u. \- gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 h4 q, H/ ?- `2 {, N0 ?2 {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% ^4 U. H' R( J4 G( Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* L3 a5 k, H& T$ A# B5 NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 d# ]$ G0 w1 m. a& F. wMCASP_RX_MODE_DMA);
0 u: d" ~3 W) RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- Q4 T& |+ |* Y7 X$ V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) f6 g6 W y/ \7 W( uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : G9 Q7 s/ f3 ~/ I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); M b6 A7 T( I: s+ l! \3 \/ M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , h1 S: z: v% {0 O/ u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 ^( \ t( t$ F4 b% B' S, g. `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 I- l l$ ^% w& r( W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . c/ h# J) F9 e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% D( w$ x; a! y) @+ E' ]* P; z5 F0x00, 0xFF); /* configure the clock for transmitter */
1 M7 Z, c" o0 F( UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ B& c6 T- b: f; J! Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 u% f& S$ f( R1 v' aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ B9 n2 k* z; B6 W9 `
0x00, 0xFF);
( A# e4 M% s) E# U- C& C7 i% ?6 |+ B+ r6 B$ R
/* Enable synchronization of RX and TX sections */ v) `6 e5 l9 k4 V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* m# w2 N2 ` G- N, R; U- ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. V8 L" v' v7 b t9 |# N# [5 ]! ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( }5 [; E" t5 R9 ^ E** Set the serializers, Currently only one serializer is set as0 Z& H+ I- _1 r+ i
** transmitter and one serializer as receiver.# V H7 ?3 o" O* w% q8 s2 S
*/! ~# a* u9 X% D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); J) \6 a4 ]( ^& F; ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 z1 R" e! C8 X( V** Configure the McASP pins
" k& m- H- J4 a& y/ ~** Input - Frame Sync, Clock and Serializer Rx
; D/ r; V& j4 M4 E3 C- D, A; O" I** Output - Serializer Tx is connected to the input of the codec 2 I( P) Q. L# c
*/
9 N4 F c: r3 X9 T1 i' K* _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 h8 R+ Z2 s+ r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ \2 D8 @7 o& OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 P1 ~4 C+ [/ y4 e! |/ N2 I* t
| MCASP_PIN_ACLKX& C8 j! p I: Y
| MCASP_PIN_AHCLKX+ k5 i A3 e! j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ ~: {8 `0 c( r- \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 [+ s! v" B, L, X. |# k| MCASP_TX_CLKFAIL ; R, u/ y% P& U+ h& o
| MCASP_TX_SYNCERROR
' B6 o- f9 n. l6 {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- i% \* W, x/ j B! n| MCASP_RX_CLKFAIL
1 k6 \" \) m+ ^0 Y9 R" m| MCASP_RX_SYNCERROR # [" x4 s% P) r+ z: m* p* I
| MCASP_RX_OVERRUN);
& H q2 G) Q, D$ A. I} static void I2SDataTxRxActivate(void)
) w9 L' z9 Y& u! n; R0 N9 `{) s8 S4 A* Z: A
/* Start the clocks */
- ^! ~% G0 q' d9 g9 l$ PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 o: H. [" V4 m; Z r/ s- _5 MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// p; j8 [5 x$ S, O: P2 I, @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, E( b& V" F; bEDMA3_TRIG_MODE_EVENT);
8 T4 c4 y K+ gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " C l4 {" w) U6 u/ q/ t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% T4 o2 w9 k0 |# {1 }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 {) u- f) z7 O9 [6 U3 sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
e ]$ f' r! g- {6 \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ H K0 r' X% p- j# G8 W; B( `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* |$ p4 b% X+ Y# K% k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); r/ j j( h# u
} ! x K! C2 x) a% c$ V4 |! A# x2 J2 S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) G6 N5 Y9 H) u! L8 d' j
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