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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ N+ k9 T* e4 y0 Q/ X9 R* hinput mcasp_ahclkx,
# I3 f! K! N t- `6 {6 U2 binput mcasp_aclkx,
9 `' l3 | x& p) c2 M9 d0 Pinput axr0,# A" P6 ^$ U0 z# _ X' D5 n
4 O+ q& v/ n: P$ Q# j, voutput mcasp_afsr,) O' S6 E* ^1 ?# t; r* m
output mcasp_ahclkr,
3 Z3 M4 _" S* B+ r9 ?output mcasp_aclkr,
( h8 `# l& m% Z2 b* Joutput axr1,
( _1 R; X* p% ` j$ C assign mcasp_afsr = mcasp_afsx;
8 M; X4 Q7 F) d! L2 X l' cassign mcasp_aclkr = mcasp_aclkx;
/ H4 N h6 [4 p" D5 \assign mcasp_ahclkr = mcasp_ahclkx;
$ V4 y: g; {% _( c- sassign axr1 = axr0; % @1 W& a' q* @; t" ~$ N% c
K0 s( X4 c$ `( U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, q% _, O. A0 g+ V8 g1 Astatic void McASPI2SConfigure(void)
& U- S) j1 }" v/ [2 [6 |- l6 N# v; I{
^3 u8 _7 \+ ?3 C7 hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; A' |6 I( q6 {0 m# U( sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 R) A6 W, s4 SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! O1 z+ D; Y/ d* h B9 E8 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& x0 X4 I' j; D7 Y. b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& c/ t( Z! B2 u* nMCASP_RX_MODE_DMA);( ]; F8 \7 l" T1 g1 @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# }) Q2 y# |$ {) o$ X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// M n! E- w L4 p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * F3 J5 @ F: \' Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ u H: J, ^" E; YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 `- ]/ Z, ~5 e. E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* Z$ c! V) u5 t& k5 v6 U+ QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 |* w8 Q( O8 V# \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # D. t" Z) [% x# R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 A g. U* z, }% Y+ k3 M& B7 p3 |0x00, 0xFF); /* configure the clock for transmitter */) N% A. b. T& b0 y6 k: e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ O2 ?8 M8 y- q8 P8 _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" v) s; }" t' `! U2 \2 |, }0 Q/ AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 a' R" B& H5 p: d* T/ Z& o; W0x00, 0xFF);# u6 a) b% L9 u* e9 m9 U
& n. H& N% z2 Y( t7 [
/* Enable synchronization of RX and TX sections */
7 Y% Y* f" Z% X9 }6 d$ \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" X' R( b; |. B% _5 B% A: XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, Q0 i4 @! s8 [( u# qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ h" A% l1 b9 v** Set the serializers, Currently only one serializer is set as X( _8 I6 M4 G1 ~9 V4 Y; _, B
** transmitter and one serializer as receiver.' W- w$ n) x+ a ]$ k& y* y
*/
% l' C" |- A$ l; f( c# rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* @3 K! r; p9 J, g( U! y) M4 I6 w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! v& n# ?1 e1 O** Configure the McASP pins ! W1 s- Z# n; @( ]7 |/ u9 H
** Input - Frame Sync, Clock and Serializer Rx
}% u' e1 S: i3 y! K' R** Output - Serializer Tx is connected to the input of the codec
7 X" V6 u% P( G*/
! ]! z ], }" [5 i6 @3 i; p; nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 r2 V" ~$ I$ A& @0 r4 }& [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' r: S f4 S3 ^& j5 I7 hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 ^' g. s! v) g& y4 X7 N* @| MCASP_PIN_ACLKX0 ^8 {7 m6 _8 C0 |& H
| MCASP_PIN_AHCLKX, ?) \0 c7 x$ u* u2 ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ F- ~& O! [% u, j! X0 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 q5 N+ B# H6 \) v0 E" {2 `8 n$ v| MCASP_TX_CLKFAIL 6 D% `5 K- [3 d; I4 f8 |
| MCASP_TX_SYNCERROR
$ A: T2 V% A" w, c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( I' E7 I h: y* _: y# O" z8 y P+ {| MCASP_RX_CLKFAIL7 z9 b) \7 V; q( x( G( D' ~- a
| MCASP_RX_SYNCERROR \! ?# G) y- J1 K0 O
| MCASP_RX_OVERRUN);
- u/ f0 A3 {9 ]} static void I2SDataTxRxActivate(void)
- k1 z$ r _/ T1 ~/ z+ V5 j{
+ _& G# A+ i+ n. ^, p/* Start the clocks */
l; k& I6 U3 X3 O" R/ w; `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& r9 `- s4 U' y4 T+ Z8 o6 IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 Y w$ I- |! K0 g' R& m, sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. {6 ] @0 p) W5 d" y/ i1 W2 \EDMA3_TRIG_MODE_EVENT);
: x" a+ k4 m5 {4 g. z4 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' g; `+ {4 r5 f- Y5 R- b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: T4 L+ J1 {$ ^' G2 d6 uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) b% h+ N t, |5 Z. Q1 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 G4 {2 j% O7 |( F0 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, _/ k/ S; M2 V z5 \4 q; P3 L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 H% U0 _8 E# n$ r5 ~7 v2 s% j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 d9 p( @! X/ E6 k9 a' k& \} 5 n+ P `9 O1 a1 ]( H" F, w2 u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / Z" f) k) [6 f+ ~
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