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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( [/ s" n% ~0 h1 V
input mcasp_ahclkx,
& j: d6 l5 B9 h% R5 Rinput mcasp_aclkx,
! a% g; h. n2 L; ~- K- pinput axr0,
$ n @; o) p& o9 D; [9 J T, Q, ]3 D$ A. v, |
output mcasp_afsr,$ P/ A; R. K) o. u- ?
output mcasp_ahclkr,. Y- N0 s" {1 V! {" R X! q' f
output mcasp_aclkr,
0 e& c: E7 K# b5 Foutput axr1,
, P( E8 s! a% j assign mcasp_afsr = mcasp_afsx;
/ U x0 v5 N2 ]7 v. T4 Massign mcasp_aclkr = mcasp_aclkx;
3 e" `5 I! E# lassign mcasp_ahclkr = mcasp_ahclkx;' w" D& [3 y4 e' Q- m
assign axr1 = axr0; + c1 E4 ? v4 v/ [( s% t- u/ Q
! L8 g& ] `4 L' T3 o. w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; B1 _; ^8 q4 Q6 \" C( J0 {; H1 K, z
static void McASPI2SConfigure(void)
- h( t( I- F9 K# `5 B{
4 V% `# J5 c6 [$ J9 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 G. y: K2 @4 z) N! O5 Z+ X3 eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 b0 P" G$ _8 M) L3 {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 y, Q" w3 `' f$ Q& tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 @. t @2 h2 I) E' {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- i/ O f* X/ X8 e6 {
MCASP_RX_MODE_DMA);
+ [& b% X/ s, ?* mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. S! t4 p8 G, X2 R) O( l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; f2 w$ y: n" W/ b; f/ l0 x! [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . [% T+ Z9 h+ \2 ]& q" U$ z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# {( D4 ]' [( L$ O, yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' K6 E; v$ P+ r$ ~9 n: uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* X) j Q* G( A# a5 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) x8 @. Z0 [1 l6 ~: e( ?- E; QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 \' ^ L: P& ]4 Q* C; n, LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) n) s0 \2 p6 a* X# E! l, r5 o0x00, 0xFF); /* configure the clock for transmitter */- G, q% e V( O+ x4 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 h; _7 u! d* w/ i6 ~) k0 MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # X& o8 q/ d( }/ a" q |( ?' q% }7 t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; B* w# l2 x& x- x' n. ]
0x00, 0xFF);& a- a8 V: a1 f( z+ x% Z6 H% o# u
, `- l/ I, |7 \
/* Enable synchronization of RX and TX sections */
0 W' s' B% I$ t( m$ A5 E- {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% ~6 V p) n5 I2 g: e8 k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' o; R5 c ] O& O# b( t: V/ @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- W. a8 T0 a4 \0 P7 _** Set the serializers, Currently only one serializer is set as
4 H% n7 r5 X' z) t** transmitter and one serializer as receiver.4 ^+ D+ s* A7 |& ^
*/
% F& O& |" m3 s5 g# b. `: yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* _/ |5 I. p1 R; {( D5 H9 l |) a# _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# K; u# k) g8 h, U% Q** Configure the McASP pins
+ ?/ n& o A8 j, u& f** Input - Frame Sync, Clock and Serializer Rx
6 ^5 m% D- h- J** Output - Serializer Tx is connected to the input of the codec ' ~3 } M6 g; v, u: Y2 U
*/" V3 F+ |& H) \; r: t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 U* ], v% u) @- A: M% D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 L' e& g2 K! F. X0 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( \# D3 Q1 d: n& T* J) A* O
| MCASP_PIN_ACLKX
6 X/ D- e& Z5 V' @& n3 W5 X j# N; ?| MCASP_PIN_AHCLKX/ u* ~: @) L% r$ V) `* n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 G- A" S, O/ Q9 ~! w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 I4 Z) T: _ u: n v/ o| MCASP_TX_CLKFAIL 2 J4 B- X% \# B2 a
| MCASP_TX_SYNCERROR
. P o; d' m ^* || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 O# C2 Q% Y- [/ V! g; E7 F" K- h# t: u| MCASP_RX_CLKFAIL
0 |7 N9 ?# k2 z" E' l| MCASP_RX_SYNCERROR
- k0 K* S0 v( M/ x! r' M| MCASP_RX_OVERRUN);; \; N5 E" W9 N
} static void I2SDataTxRxActivate(void)
0 R/ j r& G- M4 f4 w. u4 g{$ y: k f' K3 E2 u7 M( ~" n+ ]
/* Start the clocks */
- q: E0 C7 T; Q Z4 g) [. T8 H/ L; xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* e1 ~2 G! h( }3 X' a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 U6 _! \; k3 e' U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' C3 y) z F6 t1 Z' j& R0 o) ^EDMA3_TRIG_MODE_EVENT);5 Y% m+ x. `4 m4 K$ h# e t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# B+ S% P& O2 mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 N$ }# s3 a4 i7 U4 b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 {' i# x, N" `) h+ J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" O" L- Y% V; v' {( [. fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& y( N. m& C; y2 ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# G) f: a& f4 p9 N' b! Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* O* x2 T5 R/ ]& ?, |7 h$ o/ I
} , D: d+ i8 X+ z) c7 w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! l0 `# s9 D! l) {
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