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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, v3 v% p& [* |
input mcasp_ahclkx,
3 d6 e" c0 F5 O0 _" n7 ainput mcasp_aclkx,
3 U2 K3 U5 [+ v6 linput axr0,8 C. U9 s6 ^5 V9 g/ V, r
, C! ?% \: `" i. q0 ^; |output mcasp_afsr,7 \% ~' k/ v6 D- `9 \, M7 c
output mcasp_ahclkr,
% F# Q5 M2 M6 ]/ w- g3 L8 o" ]output mcasp_aclkr,
/ D4 u7 F" m1 Soutput axr1,
3 m+ W5 o3 H3 ^; `# t& n3 n( W assign mcasp_afsr = mcasp_afsx;4 E! a# |0 a2 {/ D1 P
assign mcasp_aclkr = mcasp_aclkx;3 E+ D; w A# B
assign mcasp_ahclkr = mcasp_ahclkx;
5 f1 O! A$ i8 `! C$ s" wassign axr1 = axr0; + H$ i" L/ @7 \
5 ^- i8 a2 I, M& E& A& T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + D1 X% W3 X% `/ N& ]
static void McASPI2SConfigure(void)
/ x6 R6 f$ x, s1 z2 B+ K# k' o{1 h! j6 S" p, ~ E" ]5 z: C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ U& ]3 D. C1 d6 |% k) O% q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 A1 Y j% i5 w/ [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' x* e( V! |$ D9 u+ N' y8 f# O2 o. QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 t0 C' W* v/ @8 R$ j% nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 c2 \$ Z, d( L
MCASP_RX_MODE_DMA);
0 Z1 L% ~2 n- aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 D1 d4 M" J1 T; n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" A# T1 X& A% F; H! u; T( SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 l9 v0 P/ g" b; u6 V$ uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, Q9 F6 a8 v0 Z+ t* W, S6 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% d* d# G' f5 G4 G) |, A9 p4 x0 B1 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 t( F" d Z/ ]1 G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& m' U+ E f! D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, @1 [; N2 `7 j2 I5 t! A% ~" R2 k* YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# _( F! `& T1 v- i' J/ @
0x00, 0xFF); /* configure the clock for transmitter */
8 |0 L" b0 e3 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ Y$ j* N( u( \$ d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 O5 A0 d3 v6 N% f7 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ ?5 P% j# v( e0 X0x00, 0xFF);5 c- X- r& _( }1 a' v& c( Z* c5 t) Z
( `# y# r+ \: X$ ]8 @/* Enable synchronization of RX and TX sections */
& z$ N' I, n% y" w) SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, r; W4 Q' h. j; [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- S- g. H* z" i2 R/ o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ t' o! w3 _7 V, V
** Set the serializers, Currently only one serializer is set as3 U# s9 K+ O" s) j4 Z
** transmitter and one serializer as receiver.9 G+ I6 T! Y9 p: q$ \
*/9 k0 q! x+ C; r' T- g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); ]# n8 i9 X$ H: y8 F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 R; ?; A& s5 a/ Y2 X** Configure the McASP pins
9 L9 U% X/ g' w1 M1 k; T** Input - Frame Sync, Clock and Serializer Rx2 O- m r# Q9 n( w$ Z+ }
** Output - Serializer Tx is connected to the input of the codec ' j) K; t: {1 X6 E0 P9 ?
*/; \% E0 \" H: l6 M7 _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# `$ y* J% z* S* q9 ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- \2 l2 v! |0 m: t. v4 B+ `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 t( ^2 j8 {: ^5 K4 m4 S+ i G/ }| MCASP_PIN_ACLKX
: x. ]: Y: J3 v2 T) ~| MCASP_PIN_AHCLKX) q8 O' I+ k H& S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% c& N( Z6 W! p) c, S3 P7 gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . P" R3 d" o1 z, ?8 \, e9 x
| MCASP_TX_CLKFAIL # U" \' I+ Q' F0 I( Y7 e
| MCASP_TX_SYNCERROR2 Z: `; g1 u( V; ?2 l) K# [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 ^4 A8 ^5 o9 g: g# X3 n
| MCASP_RX_CLKFAIL5 Y, [2 ~) v0 [2 [
| MCASP_RX_SYNCERROR ( }0 ]* B- j, m
| MCASP_RX_OVERRUN);
" ?! B( Y+ |" c0 G2 L& r} static void I2SDataTxRxActivate(void)
1 O4 C& Y: Y* q z# ]{
- t0 _! s2 @: E! C( U# D/* Start the clocks */1 K X/ N }! }- ]! ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 m+ e/ Z# b: Q, j+ M. N2 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& ?$ [8 G1 a9 t6 H( G7 p$ g$ a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, b# y6 h. V$ I2 N2 j6 _EDMA3_TRIG_MODE_EVENT);
0 K2 N' A. b& b2 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / M3 D% K# D' a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# m" |2 o7 [, ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' p; _9 o( \% F+ g8 X% x) J X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! I3 Q0 e/ ?4 z# J/ Z$ D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ K5 O/ \# F( g, l( A0 o4 w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' |1 K2 c) a- UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 h5 o: v6 }5 d4 \. U" f}
- ^6 h4 y7 X; [" ^+ ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( ~4 R! h# c7 j$ P1 P% w! p
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