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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, x9 p0 j/ o l. P. Ginput mcasp_ahclkx,) j4 x% T9 e; L: ]5 o3 q" l
input mcasp_aclkx,
8 U w8 L; H2 U8 yinput axr0,
9 r8 a' t* X. A, }" H' _4 m0 n8 F: q; @( c, X7 n. B/ |! [, Q
output mcasp_afsr,0 j$ R! E3 | b( B3 a* c6 p
output mcasp_ahclkr,' q4 w g' L( d! E Q# M' a0 s+ J
output mcasp_aclkr,
6 c( \, M. {8 T+ O4 ~! o- q, z7 youtput axr1,
* ?' J" }) f0 Z- K3 @ assign mcasp_afsr = mcasp_afsx;
& K u1 R/ r( E8 bassign mcasp_aclkr = mcasp_aclkx;( S* T2 G* c* ~
assign mcasp_ahclkr = mcasp_ahclkx;* o" P1 ^2 \9 F# t9 k, t
assign axr1 = axr0; T, x! o8 [; u: X9 Z
; F1 i# i$ Q G U8 o+ m1 i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / {$ Z }: C, f( W; w
static void McASPI2SConfigure(void)6 Z0 |0 P: F# P: b
{
5 O( f, k7 n) z, _6 P' \McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 }" B# }+ m5 n# i7 P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: C2 x% p3 O" H) o8 Y( D3 {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ w. i1 H1 J6 @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 M; R8 D1 ^5 h1 j! Y. O2 v1 c* |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 @2 l) {! q' K. o: v1 r# F: m" mMCASP_RX_MODE_DMA);
) E7 ]: |- Q# y* MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, U3 w- f; ]' O" {2 W- q. U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" [! @. J: `5 n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' A0 j* _6 \5 p+ h( t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. P- A+ i& b. \1 w+ H4 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( G% A+ l; L5 F5 g- XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// F* |. x: u! s) H1 G. V4 j' _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' Y- [3 D( }% Z6 ?" b6 Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & w1 Z/ E! U3 [2 G+ w+ F' r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( X8 U9 u% O* y0 t/ q0 R: M3 b, H4 E
0x00, 0xFF); /* configure the clock for transmitter */
& y4 r8 ? l9 @! Q `6 w6 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) t1 w0 o* w$ { a$ p; E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ Q0 Y U2 @: B4 }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; @8 o+ W7 {: D
0x00, 0xFF);) |9 X: s! w' M: i" S) m
, H* ]1 @$ E6 r( v/* Enable synchronization of RX and TX sections */ ' T" y) X% P n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) j- C$ n. p4 _' g8 E: CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ H* b( J. _. VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, J3 p8 w. Z# ^) C8 f- D
** Set the serializers, Currently only one serializer is set as
" z0 s# v0 x5 W1 f$ q** transmitter and one serializer as receiver.1 {# N- l: q( D/ E5 y; \
*/
+ r2 i3 y8 u0 Z7 \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 C8 X; ~% K) Z o) |! ]4 W1 M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: c0 \" P2 h) N9 e7 Q' b
** Configure the McASP pins / B) c- ]+ |: }- ^& x* w0 h2 x
** Input - Frame Sync, Clock and Serializer Rx! ^. d/ R" y1 o X% d$ i
** Output - Serializer Tx is connected to the input of the codec
6 o: {3 s' {6 o5 ~$ E/ w' s*/
1 \3 r9 V8 [8 F% `2 H1 _. XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ x% ~4 ~4 k7 J) b% a! u2 i- O/ l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 F2 ?6 r9 E5 Q- ]& ]2 xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 m: Q: ]9 j0 E0 |. s: g4 ^
| MCASP_PIN_ACLKX* u2 K& u2 w i$ Q6 L& S& e
| MCASP_PIN_AHCLKX, M' \8 T7 K K% @3 o/ [; o' C+ y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' l/ I& a6 \7 G* t$ s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; Y' S; h6 Y7 E( }! Y( ^$ v! G% I+ K| MCASP_TX_CLKFAIL * A9 w1 z0 @- T1 h
| MCASP_TX_SYNCERROR
! r0 U) F2 U0 G0 k% s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 E8 x$ o0 P/ A6 ?| MCASP_RX_CLKFAIL
; D! z# T! T" C| MCASP_RX_SYNCERROR + H' B6 L/ F; m" X/ T6 Y: a
| MCASP_RX_OVERRUN);; ~% T. x" Y, Z n( A: a
} static void I2SDataTxRxActivate(void), ~$ R* \. j7 i& @* r
{, V; ?) z, q3 g
/* Start the clocks */
. h1 f, e n) xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 a* g e' F3 t, T( @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 C8 l! I' z6 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' j% t( P; @8 M8 R. x$ T- PEDMA3_TRIG_MODE_EVENT);
- s+ G A) m7 O1 s# o% vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 r6 J. c# O. A) J# N9 \/ dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" E5 G7 E/ p0 [% m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ W7 Z2 E" Q( \) L1 o. c% V: t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 T& p6 ^1 G/ ]( C! S) Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 A4 S' q w3 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' Q- m% Q. L" E: _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 t$ V$ W0 Z6 Q( J" B: l
} a4 O" Y0 `- H5 t: V1 J; s4 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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