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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 G( |# e+ i4 U! I4 h# d5 J7 g; ginput mcasp_ahclkx,' o! N) R% n! }+ C5 F' U
input mcasp_aclkx,
0 k( U9 j5 g- c' O. _3 t% n) F+ Kinput axr0,+ Q& } b$ I6 ~' ^# t2 f& |9 I
6 B1 G! ]: x! g5 K2 J2 {
output mcasp_afsr,
6 v) ~) b5 r- d9 d* poutput mcasp_ahclkr,
# U5 E; \' v" j& Soutput mcasp_aclkr,
" t! D+ d0 k. o$ \8 Y: Youtput axr1,
& V7 g& l/ A4 O8 w assign mcasp_afsr = mcasp_afsx;+ C" Q7 E& l- m8 Y% m! h) L
assign mcasp_aclkr = mcasp_aclkx;
9 N( c: w7 `; Tassign mcasp_ahclkr = mcasp_ahclkx;
7 e; T/ ?) z2 Iassign axr1 = axr0; # b. X8 R: K: ^7 {" G6 W
1 U) z# `; t: l9 B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( ^+ I$ N7 ]$ ~% S+ o9 u+ @% i6 i
static void McASPI2SConfigure(void)
% A- ~, P! y4 P7 f: W9 D{
8 P5 O" N) [. KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ f( L" X9 K5 }! |4 }/ X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ b* F4 N+ k- s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 m- l& ]( Z, Z. f. t! Q. B' WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& s% ?$ \% Q6 B; e5 e' gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! N4 t7 l0 G2 L& P; aMCASP_RX_MODE_DMA);& Q' k2 n1 E O, Z9 u* T; w( p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ \5 M( X a6 S e. j+ q9 YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 | n e6 O3 |; k' A4 A' J$ ?2 L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , d' n: @5 W/ v/ V% ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" X0 R$ a e0 ^9 h5 [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- O5 D7 T0 x- [# d/ fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 L1 }& e- ~0 p3 m/ H, S) hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 G% D/ s7 `/ [, K% M3 z OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: b' ]7 q' F" o' V Y6 sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 z# l x6 h5 i* J
0x00, 0xFF); /* configure the clock for transmitter */7 y: \; z6 a8 O/ l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 \# q! ^ P' ]) u T( z ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 W; u, I* V* Q& @/ z! l7 `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, B' l% i0 \/ {7 `, U& o4 e
0x00, 0xFF);
/ |" X# O3 r, E2 I* s9 d% p# v" Z8 c6 |! e' n) C: i( u' N$ ^, j8 n
/* Enable synchronization of RX and TX sections */
- B/ Z) [1 G: z2 E: n4 M6 |+ QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: L9 w3 G* q7 Y" c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 r& `4 N" T' A& {$ ?" ^0 M& {4 r- E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# X& H- m$ u3 k" R8 x
** Set the serializers, Currently only one serializer is set as! Z J4 G3 V0 M- m
** transmitter and one serializer as receiver., o8 F: A! O* y% C/ z; Y3 l0 d
*/; ]8 \1 U$ [; T, R. L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ O" K9 T U0 R8 Y5 |0 a P! I! t6 |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 G4 f! Z; J+ m8 o. s
** Configure the McASP pins ( A7 `/ f( @/ J, @
** Input - Frame Sync, Clock and Serializer Rx
& Z# Z: _- I. _; q, R, W! K4 l** Output - Serializer Tx is connected to the input of the codec
9 L6 v2 V' a2 r8 I*/
& k2 Q, Y& A- d9 rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ j3 ^# a4 h6 f* k: f! f& YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 Z: z) A& q+ v, \, G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ K" w0 q0 K5 n| MCASP_PIN_ACLKX& l0 O$ R, G3 M5 }
| MCASP_PIN_AHCLKX/ J O( \. o2 y+ S+ j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; u* ^$ ?0 D2 v- \+ _. V# h3 c& uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 m4 d8 J& q' i: d( K! @* C| MCASP_TX_CLKFAIL ( \0 V$ w# c! i* n$ _
| MCASP_TX_SYNCERROR
" k- f, G: y' J# ?5 {# D0 G+ @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' g& K9 S9 [ V; w; C! `) D
| MCASP_RX_CLKFAIL
. c, H# w. q0 [+ c: F$ [1 A| MCASP_RX_SYNCERROR 1 X$ z8 M8 \9 `$ T
| MCASP_RX_OVERRUN);/ {! y# s+ h" |) x$ w4 Z6 f
} static void I2SDataTxRxActivate(void)
/ H, z7 s% P4 |0 |& Z0 n{
. q+ e$ T( o- a7 V7 f, c! p1 m. I/* Start the clocks */
) s( S( {1 Z" e) s' ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; s; X! O& u2 U3 \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 {% \5 ?9 S0 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) o4 b. W9 K+ w9 F9 n6 k5 ~EDMA3_TRIG_MODE_EVENT);
* t A$ Y f1 F+ tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 T1 a/ @# M0 k; ~' SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# a5 n& [; |8 W) eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ O- |' p% c! y+ i) K8 X! ~- o( @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) d3 f+ a9 x9 S& \6 ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; M4 L7 w' Y5 n4 YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, T# q- n% k+ }9 U, NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! J" E! t+ I. l! Q7 ?! Z
} 2 Z. P5 l: [9 u( K4 A+ `% T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 |, j9 P5 D- U& v
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