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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ Q! U7 B; p. D; ?
input mcasp_ahclkx,
$ c8 {0 g2 v8 a- i( ]input mcasp_aclkx,
9 W! c. A; }7 Qinput axr0,6 Q# g# l A2 N, a; m
# I2 Q' S/ Z: Qoutput mcasp_afsr,6 o5 D: b& b U
output mcasp_ahclkr,' m1 T1 C X! F+ l) X2 o
output mcasp_aclkr,3 x. w) m0 j! H8 H
output axr1,6 j8 n X3 _$ n5 m* z* w& R
assign mcasp_afsr = mcasp_afsx;
1 R# k* [! i, E8 C& T) Zassign mcasp_aclkr = mcasp_aclkx;' i0 ?7 |2 Q/ t" B! M
assign mcasp_ahclkr = mcasp_ahclkx;$ M: V+ o. A, }$ V% M1 M% c
assign axr1 = axr0; ; C9 \ O3 k" G# d; v
) J' d9 J, w6 f( T6 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 E/ L# y9 _6 b* pstatic void McASPI2SConfigure(void)
" Q5 u. L* K: y; Y1 [{1 g& j3 ]+ v: F1 `6 E1 Y/ e# O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- F1 v3 Z5 @) M0 `9 AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 ]) l# X$ g) Q3 a' y0 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; [9 A. B* x2 h3 x5 n, U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 q0 g7 _/ c# ^* F1 |6 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 M$ u( w; _; l" ZMCASP_RX_MODE_DMA);# y/ K8 J4 Q* h. I9 ` r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 p: Z' j: B! D0 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 _+ B# e: Y8 Y4 }# h M& z; i, bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) u, L( N1 Y" M% L1 ^/ M7 q5 E3 b* P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' t: ]- @9 E3 F2 H1 D7 J; g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: G7 y$ N8 R6 X4 C5 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 b3 Y( i: Z2 r) Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% Z3 g% E" \& ^$ f9 `& B7 zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - |. m" b% } m$ R6 t, [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ F& L" {9 r! s |% L0x00, 0xFF); /* configure the clock for transmitter */
6 ~& g& o% j( Z- y! d5 Y$ a2 JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 `2 _+ C& C C: p) _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' o: T4 E6 Z7 B: R' G; q) D) S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 {& G' `$ N) ]" M0x00, 0xFF); i9 \% r+ e' L. n/ }8 t- p- Z- V
9 i6 i% ~3 L8 x; s2 z" E
/* Enable synchronization of RX and TX sections */ ; @7 a" k d& a1 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 Q) c) A' O7 n \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; Y- E' ^0 v. ]& s+ ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 f/ d' G3 R* g( C
** Set the serializers, Currently only one serializer is set as
! U( T1 G+ i I9 w** transmitter and one serializer as receiver.0 y% \, ~' C) E, z Y6 i2 @
*/, K4 l! K6 G( m5 F/ q4 |' f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 A/ f' T( W6 e E" X) m7 }/ qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 T- m2 ~$ T7 d, w; {+ F& _% L
** Configure the McASP pins
- }5 M9 w# j9 F% u** Input - Frame Sync, Clock and Serializer Rx$ q( c& @6 M8 S- w; S) s" [
** Output - Serializer Tx is connected to the input of the codec
/ ]: e% V* V1 }*/
( U0 h$ g: E' q/ f7 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( }1 `. u9 ]6 o5 YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& V# x# e8 P2 e* Z5 @6 Z/ Z, S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 y/ p6 x* `$ Q4 g: I( `| MCASP_PIN_ACLKX
! O. _' C2 }; m! C! c! z" F| MCASP_PIN_AHCLKX
0 u+ ^) D& v3 n$ N, i! B$ i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ P2 y5 _" m _! G& ], [$ c1 JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 C( X3 S. m) F2 E* q| MCASP_TX_CLKFAIL
3 ^- B O9 B0 |2 P. c| MCASP_TX_SYNCERROR m+ b( G' y; s( O2 g' L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ }7 }/ a* Y& e| MCASP_RX_CLKFAIL- B9 ]; c# w' l' a, f' L
| MCASP_RX_SYNCERROR ) f5 P% \+ m w8 |- Y) f# p& z
| MCASP_RX_OVERRUN);
! h/ e2 M+ X6 M {8 T# |( s4 i( o} static void I2SDataTxRxActivate(void)
2 F% C$ u$ V4 }% \4 ^& h{
* ?5 K6 P4 h' ~/* Start the clocks */
! \3 I7 T3 I# |& w6 N% yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 P/ n" n. i/ b" {9 g) k: k! B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) Q4 `$ E! s4 M. r% R4 z5 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! C2 q2 _" t7 W( p" BEDMA3_TRIG_MODE_EVENT);
! [, N M2 P9 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ `2 N" T9 m- D8 iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" w Y9 W+ w; r0 [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 r1 G8 P& I7 M' j( g8 \+ }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 w3 V; R, K5 L! ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ b3 ?1 Z s% dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 m0 k S/ e* ^1 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 k# v. `! A3 l" Z3 L} ) d/ u- [ q- O+ J( J; t* B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + z' y8 I& C. N& t2 {
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