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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 v, r( Y$ W3 w0 y4 Linput mcasp_ahclkx,
) k8 A. I! b& qinput mcasp_aclkx,
) G3 ~7 T8 d7 c, y/ _input axr0,
& I8 y- K. `; u
! u; k1 x0 F- t& ]$ Toutput mcasp_afsr,6 H8 D$ `& ?( N4 {* m: r- w% {' e
output mcasp_ahclkr,
5 A5 s' {3 F6 H( W8 Woutput mcasp_aclkr,
1 c: g" q+ m) h1 J5 {5 foutput axr1,
2 [# U7 \3 ?; h* F assign mcasp_afsr = mcasp_afsx;: x: \: k8 G& C2 q- Q
assign mcasp_aclkr = mcasp_aclkx;
2 u1 `* ]- [4 ]0 D/ X7 m0 zassign mcasp_ahclkr = mcasp_ahclkx;" |7 L I; v2 r' v+ k
assign axr1 = axr0;
; D! f0 c2 }* s! ?( {
) F x0 b4 r d- U$ ~' O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( W9 N7 W0 r" {3 s% w
static void McASPI2SConfigure(void); Y; x4 a5 n, }$ g; n
{; U- z( Y7 P9 ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 R4 k0 `; D: _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! v! D" r5 N; h7 z% O/ r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 j4 ` a. T& A+ n! S# }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 B0 r5 H! J) a) G* { AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; D8 d% H/ t, ]5 c
MCASP_RX_MODE_DMA);
6 l1 n4 y* ]9 ^6 U( x0 c1 r" NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, \% G6 w/ ^& v1 d/ t- E+ qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ p+ E- R- J; a* M3 v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* X4 ?+ `9 e5 L; BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 h* H, y+ p. Z1 pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
w6 |2 E: f9 {8 y" k5 SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% [ C$ d% _# xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 d; f g: X9 S2 v: C3 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 E% O1 a- I7 @9 S/ b6 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* b" e% \0 m# n) J" [3 b1 x0x00, 0xFF); /* configure the clock for transmitter */
1 U4 F" B# `$ Y) q3 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); ~# r" Q2 ?9 T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: P+ q7 W3 I0 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( `( W! G5 P% ]; u+ Q4 L
0x00, 0xFF);
" S0 b) Z! ~) f; L2 A% K6 ? D/ ]! w& g
/* Enable synchronization of RX and TX sections */
5 Q q. U; A) ]8 y/ u+ T$ }; h" wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
J" L" b4 K7 |5 LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: b5 c1 f3 q/ `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* k; W4 c6 @0 I! g$ \- y2 n/ [# j# w** Set the serializers, Currently only one serializer is set as
& J! t* H* x$ o W, L. B: }** transmitter and one serializer as receiver. j1 w. z: e" M$ w/ w. A) ]
*/
) R# U- z2 R8 |) I4 YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ {5 k( x0 B2 }/ i! n% DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** Y8 V+ d1 H1 G$ M+ z. E
** Configure the McASP pins ! [0 Y! {7 Q3 F! w2 e4 Z1 `: L
** Input - Frame Sync, Clock and Serializer Rx
& b: s* T4 o, r+ F7 v& e3 s** Output - Serializer Tx is connected to the input of the codec
% W- f$ h! d+ h3 @) r {+ t*// B& C+ B0 B( l: e$ b1 J- _1 d( w" i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 `- \3 d K: }2 i0 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 Y- b( R+ o2 [4 s; fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 v g. q( K& j2 m+ Q9 s| MCASP_PIN_ACLKX6 `7 ?" c3 w2 l0 n/ e3 o; G7 q0 T' ?% l
| MCASP_PIN_AHCLKX& Z6 o& `7 h7 L4 x3 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( k$ C' I+ P. c% c E7 n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ t0 L" f6 \7 N5 j( x" b| MCASP_TX_CLKFAIL
$ Z# B+ I# S0 G( a| MCASP_TX_SYNCERROR! l9 x N: X; z; ^: o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' |2 E' z. W+ o3 J5 A8 S' u| MCASP_RX_CLKFAIL
9 S' G6 P9 _) x7 {3 R| MCASP_RX_SYNCERROR
9 j7 V4 m- L$ l| MCASP_RX_OVERRUN);
$ s4 [4 g1 w6 `} static void I2SDataTxRxActivate(void); ~# e( G0 x7 Q1 E
{' W' N+ T3 P6 V2 T1 ]
/* Start the clocks */1 v* M' l: E! S8 L. \; J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 \8 M/ c* I8 d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// ? b- t3 w6 Y' Y3 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 Z' ^: V" D4 J3 [. U* o3 [$ q
EDMA3_TRIG_MODE_EVENT);- D5 k* p) [. H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 l# H; K3 ]% f3 B o$ q$ sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" X5 n" C" l, J6 r# [% JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 p- z( `; d5 y( U( \% D) F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* ]5 v3 n! |6 e# {# J1 a' s3 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 d) Z8 m0 e" U3 R _! I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); x m8 R0 ~& {; T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& C" p4 a, ^+ I}
, {( ]: Z$ h: h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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