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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& W8 n+ ~% d+ ~/ q4 e* T1 c+ X
input mcasp_ahclkx,
. m9 M! f) X3 N+ Z. Tinput mcasp_aclkx,( l3 b5 J7 Z; d
input axr0,
2 v+ W; l) ~# w) o) a1 s& A: ~' V" {) v" q
output mcasp_afsr,+ h. u% u" b7 K0 E8 P
output mcasp_ahclkr,
6 u# M% w) @" _1 J: o3 {. G0 L4 `( Eoutput mcasp_aclkr,
4 v: b& @' q2 w5 Q2 _output axr1,8 o F( p) {. N7 n" b4 h5 C
assign mcasp_afsr = mcasp_afsx;
. Q( X, R7 S6 h/ H, P! `% Iassign mcasp_aclkr = mcasp_aclkx;! z8 P \! e4 ?- n+ R( n# E
assign mcasp_ahclkr = mcasp_ahclkx;: C2 c! }7 f9 N/ s$ Z9 z \# O7 S
assign axr1 = axr0;
' c/ K* P7 {# l, S; t
! c9 ] S) X+ P, p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # A1 F. T6 O: j7 [; r
static void McASPI2SConfigure(void)
( i- `+ T6 W8 i5 b' X6 \* W{; | U' U# t/ K; f4 }* V1 S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! W3 M4 _0 H% s: W OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' Y3 _6 T% R. O) Y# vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& B. q; H& n1 K; b) d. D9 ?5 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 ]% m% `; e3 U0 {! P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% Y3 d5 _: }: h- h8 A
MCASP_RX_MODE_DMA);# @3 J' A g% i& U0 _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* L* S: Z' F2 w" yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- R1 x% U6 ?" z1 w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; I' u1 n' R: l1 c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& R+ T) H. C" m& `* a" R% TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 w" V: s' x: ?1 g; F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ S* T( W, Z6 G) z) m, f2 m. m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 X/ Q y0 x7 h/ h2 OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! X ^ Z: {! ?" p7 n# g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 g) I9 K4 _$ \9 ]4 M7 K2 @
0x00, 0xFF); /* configure the clock for transmitter */% e8 v( L0 z* W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& z7 t- z' M$ w- x4 H6 e+ hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 e; E* @" L* q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 `7 X- K% J& E2 [8 ?
0x00, 0xFF);4 D9 g- k" O5 y4 F9 n1 [. r- s
* `% b6 S! x. y. V) }7 l0 c/* Enable synchronization of RX and TX sections */ - Z0 t- E& s! M0 q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 h/ G1 {2 s A1 m9 J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% p# @$ c9 y: C1 E- @, p7 XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" t) l% ? t. I3 q7 y. {6 O% [** Set the serializers, Currently only one serializer is set as
3 B0 x; V( @0 ]" l; [# C5 d4 m% F** transmitter and one serializer as receiver.
# Z$ M8 E1 c; H0 t3 l; w*/
1 T. w6 V' p9 h4 q4 ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% A ]2 I' z. G( Y/ b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' e+ A8 f S% f- r' {. V
** Configure the McASP pins
) I6 h: @ _0 a! n3 M( |3 }** Input - Frame Sync, Clock and Serializer Rx9 b% e( s3 i* [; u
** Output - Serializer Tx is connected to the input of the codec ) l- h9 `$ \. r ?4 }% [8 L
*/5 P) Q3 R6 `3 A+ ~! S# a# v/ X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& J6 G S6 ?- w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, S B! w9 n' UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- E1 O, B( Y: G% h
| MCASP_PIN_ACLKX$ }( f; ]+ l2 k) k' k/ U. s
| MCASP_PIN_AHCLKX
/ x9 z1 ]4 g- G7 I8 P6 Y4 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 w( C5 u$ E8 L+ SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ y5 Z& i3 K/ i' P% B! Z
| MCASP_TX_CLKFAIL
; o, x4 C6 e8 z' e| MCASP_TX_SYNCERROR
8 A6 {0 q! D! h5 E. M7 X+ R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! w: ~+ m2 A$ W# @, P4 B) v* J
| MCASP_RX_CLKFAIL( R) Z+ y$ b9 R |# m% W0 i$ J
| MCASP_RX_SYNCERROR
/ P% D, |% W0 x" l0 `* b! h| MCASP_RX_OVERRUN);
4 Q( ?' f. `$ K& a9 t$ S; d8 o} static void I2SDataTxRxActivate(void)5 \; B9 S: E a: j# Z
{* A" f y% @3 `# X7 L) ~
/* Start the clocks */
& A* t I# q% D: r) NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. B' g" c0 q! C9 o H; ]; V: }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" H$ Z7 |; S# H. \. n: e, l% z- E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, N. G4 g! s6 I0 A9 O
EDMA3_TRIG_MODE_EVENT);
. k% b6 \. B; }; T: OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; j( F" U. B+ o1 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* L! S5 i( {$ C1 z C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 @" {; P4 E% U! T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 E" W# m9 b5 T6 u/ y; x: ~! Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% F; ]2 K+ l0 D8 r. KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: s, {; s7 T6 d& i" q/ U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 @) `. s; k& f# F! Y' e} 8 m% F* B: W% R9 @) O: r! S7 l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! R# z5 a2 v) Z8 x" A F
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