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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& ]- G6 T5 w F) [2 O- dinput mcasp_ahclkx,
7 G5 D4 X5 v/ M: k* `input mcasp_aclkx,0 P( k1 q" G! O( s3 w5 Q J
input axr0,
$ k/ G" H' m2 t, [0 |5 u
9 N% e7 n1 I3 L6 Y0 v$ }output mcasp_afsr,
/ _' @2 I5 |: O9 Q' N) ^output mcasp_ahclkr,9 h, j/ Q2 Q0 F% {8 Z t% m
output mcasp_aclkr,
e. v& t; Q6 L; B$ V$ s: m# Y ~output axr1,
$ ]* z2 ~' y0 `5 O' I$ ]- i1 n assign mcasp_afsr = mcasp_afsx;
4 i: `( k' m! M$ uassign mcasp_aclkr = mcasp_aclkx;
& S0 [" i w# ]6 P5 p! Uassign mcasp_ahclkr = mcasp_ahclkx;
$ h& ^2 G$ Q; Z. ]assign axr1 = axr0;
. r9 u. X3 L* D0 }* j# j9 w( J; J" _# g8 v0 \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ d( J, i5 W- o! O. Ystatic void McASPI2SConfigure(void)- J+ r4 V% R0 M, J
{5 a6 l( Z9 U" I% t+ _6 v/ Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 X- e0 S4 ?$ {! VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# d% s ^6 o+ e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
z/ t/ Y0 V# Y8 B; [1 ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 L# @3 E( C# T& P7 c8 B1 W$ oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- ]+ J9 o0 @ p9 A) [" Z+ mMCASP_RX_MODE_DMA);
" f, U* j1 M& Q# c0 l* UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 n0 ~4 c- }6 _4 B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 D5 m/ [/ F6 e* c7 X4 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 M8 e( l9 t3 }5 V8 S% X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' \& {) I7 N Q' Q. M" u c) o& FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 p7 b% }6 ?! u% T! A, eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// S# T" e( @7 Z( u( G; J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& _; b2 v1 A8 D% ]7 d8 s, K: ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& Y" o y6 o, f1 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 F- e$ E* n7 [9 \/ _0x00, 0xFF); /* configure the clock for transmitter */+ J+ f# E9 D* V+ Q* `, P) b8 p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); I V! ~8 ^+ c f3 X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 l2 k% K1 W8 t$ }0 @- M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 \9 I p* z7 m/ J+ C7 P5 e* P# P
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
- x) o$ \; k9 o0 h1 o( {/ v4 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* M+ W- ?5 r# m: D$ O6 T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" \( N6 W: y8 ]# c+ ~# O& DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, {: J F o9 o( B0 ^** Set the serializers, Currently only one serializer is set as
4 D8 u* J% b8 `. c. w** transmitter and one serializer as receiver.
. ~, x% Q4 B7 l*/
. a: y2 z, z; u* `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. N% W+ }. H) F! [& P) t7 ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# U! V; S4 P# E** Configure the McASP pins
. l, v9 b& g4 U n# \! J$ z/ `, S& Y** Input - Frame Sync, Clock and Serializer Rx
2 D3 u4 w+ Z* ?' M5 X/ m** Output - Serializer Tx is connected to the input of the codec : i5 @6 p2 I& x$ w4 _9 F* W
*/
! q- U9 R# e" M. A' |* S1 z0 `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. n1 a$ p# O# Z1 T2 M6 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ z, F3 ~# G: X% b$ J0 R, v" x, u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) _2 n7 X' m% X: n| MCASP_PIN_ACLKX u$ {6 q5 s9 w; w9 r$ Z
| MCASP_PIN_AHCLKX" A" D) k" _% J7 L( ]7 }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 q4 p0 G" W6 d% ^: W9 a: CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " F5 _/ X8 C3 r" V/ Z7 V
| MCASP_TX_CLKFAIL / f" G2 ]: F/ {! [1 k
| MCASP_TX_SYNCERROR% f) } b, y- l! W! ~: [: x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 g; N! ?( h; l* X' Z| MCASP_RX_CLKFAIL& u: c+ g7 \; a% i" J4 l$ Z
| MCASP_RX_SYNCERROR
, G) d5 D& E0 h| MCASP_RX_OVERRUN);' Z8 W2 u" X6 ]" e' g4 B8 ^5 C# n
} static void I2SDataTxRxActivate(void)
- @1 W% l& r0 Q4 x) F! |$ t; M$ L{
F, k3 d% w+ Z/* Start the clocks */: x. R0 N Z: o4 U8 Z6 m% O* S6 B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ X+ ^4 L9 e Y8 }( }6 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ x0 {( e8 {6 \" ?8 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* K# S9 W5 w% U
EDMA3_TRIG_MODE_EVENT);
- l% L: y% ?, HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
_7 j3 a: \0 {1 R$ H! b; GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& l+ E2 @7 H+ u# Q& [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 |4 v$ T+ S. p0 Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 R% ? C6 d6 t- {, Q( j* O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% q6 j6 U# X1 ^: P1 y- r- z2 y$ A; f5 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 h% q: ^5 x4 w; m' EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: t/ c" r3 u* E$ _9 u2 j} ' x9 j0 c5 x1 A1 F" X* o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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