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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- o; q- q$ v& g1 a; Q) A
input mcasp_ahclkx,
" P: O; B4 K: P5 ^& v, b6 Yinput mcasp_aclkx,6 y( q; c( B) j6 a( [) Y5 |1 [
input axr0,8 `, \* _# v7 S
9 F: i& |9 \5 C, \9 _ d( |& houtput mcasp_afsr,; V. o% E, A8 M7 o
output mcasp_ahclkr,; o, c- }6 b$ s A
output mcasp_aclkr,- p" ]! K% ]8 a9 o: m B
output axr1,0 a" U: j G8 \) e
assign mcasp_afsr = mcasp_afsx;4 l. a& W/ w# d" d4 r) F# v
assign mcasp_aclkr = mcasp_aclkx;9 ]# b8 W* R0 b3 ]6 c7 `' m
assign mcasp_ahclkr = mcasp_ahclkx;
/ w- T* m' `% r/ t+ N) _assign axr1 = axr0; . n- {( k1 ]! F8 K& T
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 h/ }$ ^& l5 @+ k
static void McASPI2SConfigure(void); G9 a4 \' ?2 u4 W4 V+ k0 \
{8 _: s0 [9 C& F h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 `4 |1 a! f6 I q$ XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( W+ p: V0 h! ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 i1 T( k" a+ ?; j* e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 X6 p: H6 b+ G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( f) _. [5 |% p* a: C/ d4 Y: D" I
MCASP_RX_MODE_DMA);: C. @/ n& P$ H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- n3 i1 B* | |- h, HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 J2 _9 s/ B3 W& X" h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! Q0 D5 q7 I1 ]$ q, C' [9 c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: ~3 ^/ L6 j3 l' D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, T# r$ A/ J* d: c: \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// ~; _, t, M$ L1 p+ f( t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); d) _; Q5 a0 }8 a: J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 H# q4 f' |% I, U0 `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* W. a. H. d9 ?$ y5 p
0x00, 0xFF); /* configure the clock for transmitter */
6 a1 L6 R; M7 U. M/ ^. gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
b& c& D6 |4 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 i4 k& W. V( Y3 hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; M/ O5 y4 P s! M
0x00, 0xFF);8 S8 s% p& s. F( z
k7 T M& u+ j& ?- p2 n/* Enable synchronization of RX and TX sections */
/ o2 e: y+ R4 U7 {) ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# h9 O3 r) f. |& b/ gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 j' t5 a3 _* E5 h% S M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 N; h r K2 Z5 u$ @8 V- w& T** Set the serializers, Currently only one serializer is set as
- O: S9 D# S6 G' e& S$ O** transmitter and one serializer as receiver.3 E4 K$ A! L1 p+ O! e
*/$ {6 c6 ^5 W1 f/ H2 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) d) D% D1 m' N7 @7 pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% q" f& u/ n& T( C" L K9 M. Q
** Configure the McASP pins
) Y% E q6 K7 t9 k, n8 }** Input - Frame Sync, Clock and Serializer Rx# A7 t b" B$ Z) e! V
** Output - Serializer Tx is connected to the input of the codec
6 Z7 I' f# v m/ h/ I% P*/
0 _4 d2 L" b- d6 d2 MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ L+ d/ m5 y* M9 n; f" G8 x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& l" F; A" ^/ f$ e5 c) i( T- ]/ h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* {4 T4 q: K8 b6 _ M6 || MCASP_PIN_ACLKX
7 r- w. F! g* T/ y| MCASP_PIN_AHCLKX
3 i/ @6 w2 I. F* U! j5 ]5 l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 u9 q2 n3 Q* ~/ _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 u8 K% _8 \0 y( w
| MCASP_TX_CLKFAIL
3 A+ Y5 a/ z) u4 q5 g6 C1 b| MCASP_TX_SYNCERROR5 L9 u% F% N" H% ]; Q/ Z: L, e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + s Q! p0 E( I( g% j6 J
| MCASP_RX_CLKFAIL. U. ~ O$ P/ j/ L. p1 S% o
| MCASP_RX_SYNCERROR ; E. _2 B8 F2 T
| MCASP_RX_OVERRUN);; \0 p& G9 r( k" B
} static void I2SDataTxRxActivate(void)( l& A5 T( z6 c, q
{6 I4 s d2 _, @+ ^4 l8 ?. i% Z
/* Start the clocks */. h/ Y3 T/ J( d. o1 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: m% C. Z9 q+ V6 v" {; d# ^9 M3 rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) \% j9 z' W0 d% lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 o- F7 W) l; [- k& q
EDMA3_TRIG_MODE_EVENT);
) X1 n2 z6 I/ s: B" |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( f1 T& @4 @0 S0 o7 kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 U1 }- B3 s% g% K* o" MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
A# j" `# X5 dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' j3 M4 ~" t( p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 q% k4 t# b0 t: _: K _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. a1 ]( }! C3 K5 o- VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 z% ]9 w2 Z( l( ?) L2 S( f
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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