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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 w! Y G3 F& f% K
input mcasp_ahclkx,
/ t2 ]' L4 j" [input mcasp_aclkx,
O2 S3 J z7 _! [6 S+ t8 Sinput axr0,
( T5 {! ^% D! H; T) U1 Q5 E& v! N) C) ], V: m. O* H: @0 H8 I7 p
output mcasp_afsr,; M" _- X3 u2 e, E
output mcasp_ahclkr,1 N# b4 {2 e4 z
output mcasp_aclkr,& S* v' j. ~* a! [ V7 I
output axr1,
# L6 e9 ?; Z5 {% ~! e assign mcasp_afsr = mcasp_afsx;
/ b; r! A0 h) p3 T0 E+ ~, Fassign mcasp_aclkr = mcasp_aclkx;% V2 W) `$ m: C8 A, ^8 \/ a
assign mcasp_ahclkr = mcasp_ahclkx;; n: v2 u$ g+ C
assign axr1 = axr0;
- }- p; m3 c! ~* w9 x. k; A) F) C" h$ O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % k2 v) N7 A; `% o. ~2 A3 g- R
static void McASPI2SConfigure(void)
. W% ^4 x0 {) v ]7 ~2 ~- E6 u, I7 O{. S+ n: o8 h* @, \+ A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 d' r: y* ? M2 L. t6 [& u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* `/ b9 N$ X: a. D4 `1 U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 g$ p u" f) E) o# z$ k* Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; I+ M, ~. \) \3 Y* C. x! t* o( Q- UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- R; Q! ?7 P8 D8 u7 |6 QMCASP_RX_MODE_DMA);) J' m2 N2 F2 i, F* l$ u$ {9 I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# B3 W: f$ T7 R8 l' [- lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 E* V* q" s, T/ ~4 l Q4 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 A8 W4 R, n' s2 u2 u6 T, u! HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 _8 s6 C! Z; ]; [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 W M$ n6 N4 X4 ~# {4 h9 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; C- q& v+ z* R: g2 s4 f- h5 N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( u' ]9 \/ s @6 I; C: |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 x( r0 g* y. M$ B/ ^* i+ V0 w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, H2 K, g, \, A: a$ M
0x00, 0xFF); /* configure the clock for transmitter */+ z! O& a. R. e1 j j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* g% y2 b$ ~) W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# J0 j; V, B# K5 g( jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 a6 o( Q: L3 ~: A5 \ A0x00, 0xFF);
% ^/ _- p5 _2 @& m1 A; a
2 A9 a. t1 ~, a8 L% b; C/* Enable synchronization of RX and TX sections */
2 f2 g3 {1 N% N3 lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 g7 N, p" Q) T iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# G9 [ e* Z! [; ?* d) ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 E3 L! b$ H5 q4 O) G: a' N! l
** Set the serializers, Currently only one serializer is set as- u+ _9 U% n A7 o4 K
** transmitter and one serializer as receiver.
) P( [# B2 p! g8 O. i*/
' [9 r; J; K3 [' u8 RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* P1 D; O+ A8 N5 A1 f2 l9 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
n6 f3 I: [4 J, \+ |** Configure the McASP pins
* N+ i5 t) s% m: c2 A# o' v** Input - Frame Sync, Clock and Serializer Rx: j0 j! B- f8 l1 o+ z7 H) b
** Output - Serializer Tx is connected to the input of the codec
' ~ m' F- c) Z$ a2 I8 @/ v*/
: R5 {* J. f7 [9 }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# t, _% Y7 I# s: t/ qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: J* k4 q! z7 o( l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; X* n6 Y3 _* ?8 G| MCASP_PIN_ACLKX% U4 }, K8 }/ D M1 k7 W6 c a
| MCASP_PIN_AHCLKX
6 I% y+ F" k# A1 }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' h- ^$ K. r! S" {8 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , H0 X; t% @% W% E/ e
| MCASP_TX_CLKFAIL # o2 l w* V4 R
| MCASP_TX_SYNCERROR
& L4 I- V' Q6 u- V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 t( @4 J+ H2 H0 E
| MCASP_RX_CLKFAIL3 @ b; C/ V* [2 H( y1 ~% g3 p
| MCASP_RX_SYNCERROR 1 q- o& }; L8 M" s: X/ @2 u
| MCASP_RX_OVERRUN);
/ ~6 Q$ v' y* }/ l6 O} static void I2SDataTxRxActivate(void)4 R: i0 P' y& s4 H) b
{
P" [+ U3 l1 h+ N# l3 c/* Start the clocks */
8 Z3 _' e9 |/ q' jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
i O5 Z7 \) DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& ^+ R+ q4 c" G: B" ]4 L- n: h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. A, C* {! m( u, T0 @% e! EEDMA3_TRIG_MODE_EVENT);2 q3 Z6 W; n* r. c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 l0 U9 u. X# G& b# y/ lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* H( j3 b* `" M. {6 e: J$ P% @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 J- B$ a, `5 t9 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ m% |5 L' s8 D1 o4 H! T1 ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: z- l* P, w; ]/ j' yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% s+ n0 \% ], W( ]: E0 H, SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 @, D2 T# o; O! ^9 `- y/ t. N} , ~/ G+ B9 `* u9 x' `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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