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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. J2 O: i3 r: j0 O8 _4 L
input mcasp_ahclkx,8 P) Y- Z: M5 R# ?, I. D% G
input mcasp_aclkx,
# I7 \$ |1 r% c7 ^, W6 J2 `5 finput axr0,
+ I6 T- v! x+ x3 R, ~
9 N4 g8 Q) E) X! _3 F7 X p0 Houtput mcasp_afsr,
5 G, @4 j9 J7 n3 R. O: E. loutput mcasp_ahclkr,
- o# d# _* c; W: x3 zoutput mcasp_aclkr,/ b% w: `, f: Z* `2 c
output axr1,9 l* |4 t1 R' G
assign mcasp_afsr = mcasp_afsx;
: S- N' l2 F9 Fassign mcasp_aclkr = mcasp_aclkx; G3 u3 ?$ i( |& x
assign mcasp_ahclkr = mcasp_ahclkx;6 M: S2 O! X* I' D) o
assign axr1 = axr0; 8 g% s5 n7 o0 D& `; M
% a G7 l- H5 X, ]+ W" s. D( w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & n% j: l0 g, y! D) R
static void McASPI2SConfigure(void) o9 `6 m$ Z' q, g
{8 C" z6 u: K9 E/ q6 T* }- n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. K# K% S& K: }9 EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( c0 V/ S$ S0 ~* `' P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* ^8 p j- S6 X! b2 M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( w& A) S9 f0 G2 w/ E$ G5 ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 O+ [" O/ `1 LMCASP_RX_MODE_DMA);0 ]5 G! x' k( G: ]1 `# k; F0 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 v) b7 ^. f0 ~7 k @: J2 p5 _5 g3 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 | p, E7 g6 g% g; J- ?; q& Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * p9 D" U; V$ B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 s9 C9 K8 r$ s6 m6 K- V, M# YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % Y8 a) r/ z, b* ^) i3 [0 G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 w0 |3 v3 n" B- mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 S0 X" s2 I/ k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" x d8 g- f, {2 h1 b, W* @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 ?3 u- `) O$ N
0x00, 0xFF); /* configure the clock for transmitter */0 @# |( k: z% i! z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: e& g3 {4 |+ J5 E' P h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% B5 ~0 G: |8 lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# G+ Z0 Z2 R, N* H1 L0x00, 0xFF);
3 i, G7 k- ~- h- |/ ]/ Z+ V7 a! P8 j9 O/ R/ w8 [
/* Enable synchronization of RX and TX sections */
) Z+ {3 o6 Y4 R1 p6 xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! x. T# F& M& w! NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 o) y8 Q' G6 i* O) \; {6 l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, o6 m" W- |/ b6 f0 j& W** Set the serializers, Currently only one serializer is set as7 R1 A$ A( v! q6 h
** transmitter and one serializer as receiver.8 ~& J9 c, U# F* a( |# A3 y/ N! u
*/
/ k7 {0 Q, j( d; x0 v3 LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* q! m$ O. N& q2 oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 C: G# o! k1 z2 a9 n; A
** Configure the McASP pins
1 Z$ Z; i0 a ]# x** Input - Frame Sync, Clock and Serializer Rx
* ]- j5 I% ~8 Y1 [** Output - Serializer Tx is connected to the input of the codec / j- D k& C3 e$ e6 O& Y+ ^
*/; c7 J2 v9 e5 U z6 q7 L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ A* v, ]+ t" `; oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 L- N: o; `& T5 i4 s- g, @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# Z5 i) F. v9 M| MCASP_PIN_ACLKX
! U9 o5 f# P8 b- i0 f4 q* T| MCASP_PIN_AHCLKX
: u) h; I8 U X# w1 Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 G( ^2 ~) D, x& S2 a i, H5 ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& I# [* t2 s, A- L- E' D# N| MCASP_TX_CLKFAIL
. l. w. w/ k" j+ G| MCASP_TX_SYNCERROR
' T1 @! S0 ^& g/ w% P! g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ ^% t6 C# r) O, z; G4 y" a3 ~| MCASP_RX_CLKFAIL
6 _3 ?7 p: c2 {| MCASP_RX_SYNCERROR & c( U3 c" R" W* x- q. X
| MCASP_RX_OVERRUN);* E5 Q. L( O- G+ J6 ~
} static void I2SDataTxRxActivate(void)/ f/ M; d& M( ^% N2 `' j
{
( n- a2 |4 L! m5 S u) w7 a/* Start the clocks */
4 e+ M/ J% m, h2 M0 R0 CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 M; c: V8 w0 o: l. Z% q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- p0 ?. k& z& r: lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( S: M* u2 | ]8 `" LEDMA3_TRIG_MODE_EVENT);
3 c4 x4 r9 ~, G. p- g# ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 a6 D0 N6 c q% OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 M9 W+ U, d3 S* B! d+ J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 L1 `/ N$ m; w0 p3 K D# I2 qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' G9 ~ Q: X5 e+ n$ A- ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; o" @( g z! J# {; h4 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. D2 q" `' z+ V- p3 P, R- QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 a; j' n( C" M) h8 r b
}
0 g3 k; w* F {6 J- z- q/ `, v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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