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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 Q( Q5 ~; Q1 \* s, c
input mcasp_ahclkx,
$ X0 B# R( x! t- ?input mcasp_aclkx,% E! }" U8 T4 g. s! F
input axr0,; f8 A9 K7 x: J& O. L
6 m4 O! ~7 |0 `* Y; Z0 E2 L7 |% eoutput mcasp_afsr,
[' P3 O' r0 L) I% n0 E, Toutput mcasp_ahclkr,. j5 x: G: c) s' ~! o$ x
output mcasp_aclkr,. J5 \& s5 f$ J2 f$ y2 e3 E
output axr1,
% Q3 g$ F# `- ] assign mcasp_afsr = mcasp_afsx;3 S- L" J4 `& i9 _( f# H, c" n: N: }
assign mcasp_aclkr = mcasp_aclkx;8 }0 j' X" l6 m, f% b9 n# _2 f0 [
assign mcasp_ahclkr = mcasp_ahclkx;! D" [, c6 ]7 q) x$ u
assign axr1 = axr0; 7 \4 C% G+ |: T% M; [5 d5 A8 R" g, K
6 O6 U; P' C! R- U: {3 \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 O) H% |4 U: f% q) k+ o+ I
static void McASPI2SConfigure(void)
; u- q- x' F7 t{
; k6 a# G1 J2 _* {McASPRxReset(SOC_MCASP_0_CTRL_REGS);& o. z4 V6 y- C# w X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 h3 R. r7 `+ Y# S7 N( [9 s# TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! F' H; `. p% B# n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 a: O0 `, h- |( eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* @( {+ T. M5 Y9 } h! f7 r. ]MCASP_RX_MODE_DMA);) F3 f5 z) v' L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) g: l$ b/ O! A8 W& U$ [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 W$ s5 B) i, ~5 a, |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 D; B3 J4 n9 ?% K) I9 Y7 X8 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
[6 k# j+ @$ I( q/ }8 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; ]3 q& m- O% e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- ], ]! Y3 s* x, Q4 B' E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% ^; `: {; S& [9 B4 OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 F3 J/ c& G5 d/ n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' h4 ?+ \7 F2 j7 p9 `0x00, 0xFF); /* configure the clock for transmitter */- p/ f1 g) p$ k* }' z9 `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; W3 Q+ n6 e4 X N2 A1 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . p2 N: x, C5 @4 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# }1 I/ v. R3 f9 @* v6 n+ E
0x00, 0xFF);
% y4 d; J$ S# C
. b: n* s1 n9 p) r/* Enable synchronization of RX and TX sections */ ! f& V$ _) v/ ?) g1 B0 v+ W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ O/ Z( K/ A9 |9 X/ g( r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 J- ?8 Y7 k. ^- t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: k( M0 @5 q( {/ T
** Set the serializers, Currently only one serializer is set as
. }8 F$ b. P% E4 _2 M** transmitter and one serializer as receiver.
3 c0 a# C; m1 k: ]- {*/
. m. B b6 Y0 S8 MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 J$ }6 M) `, i" {# _; h
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! S: v) g' b3 c3 ]7 L** Configure the McASP pins
8 | t1 t0 v: d+ G, t, X** Input - Frame Sync, Clock and Serializer Rx) A# K8 t8 H. b4 V$ g) k) `3 l) J
** Output - Serializer Tx is connected to the input of the codec
9 j, _$ f8 S; G' y/ r2 M5 E- X*/: b Y. q1 m: _6 T5 n, ^# }0 W1 D* D5 P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ a0 ^% k% I( ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* v& }# u! A% h) D' i0 a& M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( v6 z/ l) w- H- || MCASP_PIN_ACLKX1 N: w5 X+ H: [( f6 s- Y- H- I$ c
| MCASP_PIN_AHCLKX
9 C8 P2 ]; s& M2 N# A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) ?3 M$ O3 I. e- J8 }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ B6 S: b% T7 v9 i+ K| MCASP_TX_CLKFAIL 0 g# [0 Z6 C/ [+ f5 e! v# o. }- \
| MCASP_TX_SYNCERROR
6 H# o; Q- q1 R& e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 x) k: ^5 |; [7 t| MCASP_RX_CLKFAIL- s9 N/ `5 ]% y1 F8 p$ k$ _# Y
| MCASP_RX_SYNCERROR
4 l, M/ i+ t: i0 k% b4 I+ k| MCASP_RX_OVERRUN);
/ q* w* x- Y, J3 h# s0 O$ f" Y} static void I2SDataTxRxActivate(void)9 E6 v4 g7 Y$ U8 T
{
$ B. w( d0 v8 q" k& C; @5 d% o. k0 C/* Start the clocks */. t$ v; t( }" f2 @6 m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ k( ?* d5 L2 {' H3 i2 Y( k8 FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- F$ ~. R( E% [3 X3 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( U. k, X' I1 L, m* ]+ N1 K7 Y
EDMA3_TRIG_MODE_EVENT);% G0 Y) ]! g' ^$ q0 n( y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 k9 \6 T* g0 S1 N; TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" I- c' ?. ?7 S+ p' {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. ^+ x6 W$ _$ U* j5 k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 c0 [% z* ~5 P3 C: ~3 Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# G$ ^! @/ c1 C8 t% u* x2 ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( U6 d' J" l) U; _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ T0 `. k! @) _' V9 K' B! E
} 0 Q. K8 Q5 p% ~4 k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 o3 G) P) q5 b9 R- P6 [/ h( K
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