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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, n4 I7 I. {% G7 p
input mcasp_ahclkx,
# u" e$ ]5 O! ~ u- l! Vinput mcasp_aclkx,! r9 d+ V2 o, A, j/ b
input axr0,) U! I% g5 u. w5 b$ e
( l( w5 }+ Y# m; r; m
output mcasp_afsr,
" {' K7 Q7 V/ o% n8 w0 |& \output mcasp_ahclkr,2 e; F R+ s3 Q2 D8 P$ A, X
output mcasp_aclkr,' U z k+ s8 v
output axr1,( y) b: W+ R: y# X! U
assign mcasp_afsr = mcasp_afsx;) d3 ~8 m! T0 }* P( e
assign mcasp_aclkr = mcasp_aclkx;
W* E5 |( r( b% Q# h6 Jassign mcasp_ahclkr = mcasp_ahclkx;1 p \ Q$ M1 U7 z7 W1 K6 b3 p- g% h
assign axr1 = axr0; 3 f' G6 Y* p; d
l( U/ h) @* S/ e( W4 g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 w2 W4 t1 n& mstatic void McASPI2SConfigure(void)
6 |* f& l, z+ f* |4 {! N{1 ~* q6 z3 {( ]; P/ o0 |* r/ x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 p! s# N* w+ w \: GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, i. U! W- t' T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ N+ L/ D6 v0 G e0 p$ tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 P. `. S s% n& i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) X+ a1 c l5 i9 qMCASP_RX_MODE_DMA);
$ O) N! ~0 G K$ S4 QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: W, q0 X" o% @: u2 P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ y @1 W F% C/ C8 vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 ^# M' P+ P* B3 G& z7 CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! i! _; N9 _3 o, h4 t' r2 ^* [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 k: N( N. Z- [1 t& q, `1 V# Z" }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 W+ H+ Q, e8 J9 u0 ~$ B0 M/ _" J5 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ w' h' _7 N% H- SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - c7 Z1 E4 T' T: I1 S. u2 L2 H1 V: L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 C+ j6 [9 B& q1 X5 T. B \% V0x00, 0xFF); /* configure the clock for transmitter */* l0 {7 W0 C4 x, K* o6 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: Z2 p7 `, r. O2 ]* e# @# t- r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ N0 D5 v9 b% M0 hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ N |* X/ m0 q/ J6 P( P0x00, 0xFF);
7 b8 B* ^) b2 N$ \. X4 a0 i
s# k7 a- j# U: k. |/ D3 W; h/* Enable synchronization of RX and TX sections */ 2 E7 V( I6 O6 ^1 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ V/ J; L8 d b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- b2 a4 L+ V& r/ Q2 P) j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 t" L" R' j7 Z8 {' S& O** Set the serializers, Currently only one serializer is set as i0 s x; _. f- Q# t
** transmitter and one serializer as receiver.
$ y$ d5 y- a! T( k*/
, @" M3 y. t) R G2 b9 J7 kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 y- z$ i; m2 `2 k0 Q; K( M; x. _5 P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! y# _8 t& d1 k; _7 t% G: K* r
** Configure the McASP pins 5 k5 }8 ?) e3 ^3 w) S
** Input - Frame Sync, Clock and Serializer Rx
! K2 R9 c" q0 g7 w** Output - Serializer Tx is connected to the input of the codec
6 I! E& D! ~5 q$ w*/
/ u \" H8 x- v3 c+ l" p) \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: V9 c8 y. Y, R. }& JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ }9 e3 T2 M( ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 A0 e1 I, c9 F; i% W| MCASP_PIN_ACLKX* G+ N" G% ~$ g+ i& L) M. V
| MCASP_PIN_AHCLKX/ p/ i, B$ X$ P5 m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 O& K7 B9 r% r3 @. P \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 s7 d, k8 Y4 s. A, v| MCASP_TX_CLKFAIL ( `) D* M: J' H4 W8 R9 G' G
| MCASP_TX_SYNCERROR
9 V7 J7 i* b4 Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! F$ D+ a( E! R' K9 S. r, x| MCASP_RX_CLKFAIL
; \( _; F: ]% o% s9 X" u5 ?# G7 [| MCASP_RX_SYNCERROR
- l9 ]( u+ ?1 F/ F1 u| MCASP_RX_OVERRUN);
' J# E# z$ ?2 B7 g. m. l* T1 M} static void I2SDataTxRxActivate(void)
`5 J; {$ ~+ f3 {" v{
) {- D( G6 L$ s f: j. [5 v/* Start the clocks */( j+ f; G0 x g' |4 r$ i/ f. s3 w9 I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: o0 @- R- g4 P! }3 D% mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ i, a+ w4 r! I/ NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 X) v& s" _2 {& U. E! @
EDMA3_TRIG_MODE_EVENT);, I7 b3 l" Q2 h9 \+ S7 V" ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 ]( x( P7 v' @' o1 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 Y1 ?. n$ h9 q- `3 P* f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ C! g$ I G# I0 x% V0 H. c5 v8 \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 J8 Z5 }4 f5 _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ S6 D' B( I2 ^, x* ~! q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. p5 A3 B% |( GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 {9 K& A: e1 z+ u9 B2 Z) E/ t}
2 @( Q8 X2 O8 ~) P6 x. r: G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ k; K/ Q- k6 O: g9 C! n& i
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