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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: q5 C7 l- F7 W/ L' Q+ z0 Y0 Z
input mcasp_ahclkx,
; o; m& A; a2 }& {. b5 y/ Ainput mcasp_aclkx,
& T% N- J, I7 G& c& f) U) kinput axr0,% j; _( S" J1 l( V# Z
2 r* B5 b* i6 r T. i) a9 Q% ?output mcasp_afsr,# E! t8 L; k1 w3 ?1 I9 g
output mcasp_ahclkr,
# f) Y9 y. q; V2 houtput mcasp_aclkr,
) x7 C# N8 m1 F4 Q5 i, Q+ ooutput axr1,. |* s4 f8 |' C- P0 K' X1 n, w
assign mcasp_afsr = mcasp_afsx;* H! `" R# K. o% T- t: C
assign mcasp_aclkr = mcasp_aclkx;
7 H7 ~0 v, T: V# Y( O ]/ V' xassign mcasp_ahclkr = mcasp_ahclkx;, T- W' s% O- U4 t# S" x0 A! w& N( w
assign axr1 = axr0; % O# z- O" f/ B1 p) Z9 }5 F
+ D7 Z8 W' l% j4 p/ j) d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- A% C( c5 E( rstatic void McASPI2SConfigure(void)
/ M; G8 M( F0 a0 s: m3 K5 S{
3 u% S( B5 ^* RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; b% U9 f1 y: g: D0 A/ J7 zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* B4 i, w* S; ]( |: Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' p/ X- c+ p- J) I6 c! i1 `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 x% I7 v, X0 k7 T( zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; K* k- W8 r+ C' u8 x
MCASP_RX_MODE_DMA);
( ]; z/ J! F- D' {- ~# q9 ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 T1 C4 W3 v( ]; h- xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ o$ [1 Y3 }# S- y: Y' }) m* ^2 _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, B! C1 S1 W! }/ f7 a' ^4 w4 k0 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ P6 k: @9 u3 \% P* k1 R7 B/ n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : W: y- k( a1 r) I v: |3 u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 v6 x& q/ X# e( w2 F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( e/ u. \" ^+ S) K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ w2 f! z& t( c) V" z1 e' G
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) F0 Y& f* ~7 y( |. h" Y* N
0x00, 0xFF); /* configure the clock for transmitter */
" ~" x4 M: w! u# X2 S, ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* _$ B+ y2 k4 {8 Y d& BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) ^( H$ y+ p, y1 [/ e" X" h) }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! J0 e/ u9 ^( A/ z3 ?1 B$ d, b; m4 `0x00, 0xFF);
, f* Y1 J& {0 _0 v) y
+ E+ C$ y$ J# c X- E/* Enable synchronization of RX and TX sections */
1 k" f' }( |, j d* sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 Z/ C0 r: J& o8 X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 Y$ X, v( C, P# d& n" W& u: i6 bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 u" z' C; V1 a. E. k** Set the serializers, Currently only one serializer is set as, r9 F& X& h- \, H% r, {. d, h
** transmitter and one serializer as receiver.
6 y/ F" H- R3 r6 [: k' v: Q*/
; ^! ?5 z& \$ I b- qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. Y1 L9 @( q" ~4 u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 J4 O! j2 E- @: V9 P
** Configure the McASP pins 4 ~ O) F' c2 k! c r& v% k
** Input - Frame Sync, Clock and Serializer Rx
q% Z, e- F* u; C** Output - Serializer Tx is connected to the input of the codec
8 E( @4 _! b3 u7 Q; ?# K1 Q*/
& a1 u; K: z( G" E WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ n. o. S8 c, R/ S- V1 i0 p; @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* u% K# }9 c8 e8 E( [% |2 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. ]7 F' b, C7 p( m; u
| MCASP_PIN_ACLKX5 v$ z [9 m+ L) ]
| MCASP_PIN_AHCLKX# M6 R3 ]+ u0 F! z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ D, D3 j2 Q8 A1 E6 a6 G9 R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) N( v# m! X" O$ _' R( [0 D) M- n
| MCASP_TX_CLKFAIL + G8 J' l5 B6 `% O! I
| MCASP_TX_SYNCERROR
4 j) p$ Q9 w0 W) v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % M5 k& A( T" P
| MCASP_RX_CLKFAIL' t7 I* Q: a# h
| MCASP_RX_SYNCERROR
0 J6 W7 j1 J8 x/ o; {2 F& }* D| MCASP_RX_OVERRUN);
4 e k) x- |; `# ]% `1 U0 T} static void I2SDataTxRxActivate(void)4 |% O$ ~* u$ q
{
, }# c3 _0 R3 I2 K% k/* Start the clocks */. a( |7 |, I+ d/ h& {$ N P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 R9 [# B% L x4 s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, Y. o) j7 {, W: k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. X) d! }" F' ^EDMA3_TRIG_MODE_EVENT);9 I+ [& m& \1 p7 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 Q7 m3 r2 x; F9 t/ h8 O0 eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! J/ G& w, z' o! [ h, j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% ~: Z: t; m( y# UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 z5 ^. D& V$ j' t4 q. ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& Q* x* d' \, H! Q3 b( c7 V8 ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# b* G0 i' ] t5 m9 U9 y* y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& `5 O- c2 ~& R! f6 k
} 9 T: v1 w6 k9 W/ L4 A! q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* J- s/ \( i* \# Y; B" k |