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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' _) L# N8 U8 g' ~1 v
input mcasp_ahclkx,+ w1 J$ v- g0 r+ R7 X G% Q
input mcasp_aclkx,4 m, M. L; n: y8 w/ b
input axr0,
0 i/ @5 W# o4 @# M/ p) C$ O% v
output mcasp_afsr,( |+ {: W- k7 E z7 f2 F
output mcasp_ahclkr,; W0 t; R: p- m& M# V0 J
output mcasp_aclkr,
2 M/ C v+ C+ `/ T0 i( _3 S; Joutput axr1,1 \% b" Y3 E, h- C) B1 n
assign mcasp_afsr = mcasp_afsx;8 G: Z6 d$ |7 _/ C9 c
assign mcasp_aclkr = mcasp_aclkx;
( Y+ t# ^& |0 }8 \" ~assign mcasp_ahclkr = mcasp_ahclkx;
2 P) B. R; S. m+ iassign axr1 = axr0;
4 p. d- e }" N8 r( e; H1 K$ \% U& i5 ~; P" _' ]3 K$ Z2 k( ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# \5 y3 E1 q- [! |3 bstatic void McASPI2SConfigure(void). N b% o- m& C6 w7 i1 W
{& g/ y" l+ f6 L) L8 w; E/ z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% g% g% W+ D& }# U0 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 }( g! q e/ a& nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% C* U8 E c' j/ M" wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 o+ O$ z0 V+ s& p1 KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( ?7 b% C) P5 h
MCASP_RX_MODE_DMA);
7 O8 b2 j" n/ Q7 k4 C1 G7 UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* G0 M0 ~+ U2 N$ L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 d. P; F% v. KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . z2 _9 C4 i x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ b/ q- M* b4 l% m5 Y1 X! R- E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # x8 V2 G- z0 d' ]1 V, m" ]" |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; O2 E! h- g7 U$ ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" k2 Y% s y$ U. U$ `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 T8 S0 ^2 i1 Q7 U, _: xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 ~4 `3 Y/ t& h" p7 k0 F
0x00, 0xFF); /* configure the clock for transmitter */
6 L- ?8 x/ F. F) Y. H4 s+ VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 \' }2 S u# q# z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 t4 T( a! H2 w& u0 x/ P, v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% W2 t% {1 l/ w7 Q2 W2 \6 }
0x00, 0xFF);
8 w& r+ {' e- y" X* O
, b' q3 r$ c# M9 h& a3 c/* Enable synchronization of RX and TX sections */
% M/ _& D7 s Z3 H5 RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 \ Q" a8 X! F0 U5 KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 U3 L0 Q1 R: ^( {" s9 g4 Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ Y% J' `2 W) n** Set the serializers, Currently only one serializer is set as
( R5 y0 O9 f. q G$ p+ ]** transmitter and one serializer as receiver.+ j, N, a2 o0 n2 ]/ G& W
*/
]' Y8 E. m* i9 c, Y" r( u. b) zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; i! \: O5 f. r4 g2 g7 a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* L5 V' j+ @" X
** Configure the McASP pins 9 `# l0 [. x+ E) @! g
** Input - Frame Sync, Clock and Serializer Rx0 C" {1 V# z6 p. d5 J
** Output - Serializer Tx is connected to the input of the codec ' ?- d$ i$ K" @
*/
6 h$ Q6 B) \% o+ q5 K# g* n9 f# EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 ?) e- p" I7 [7 y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ J3 Z0 I z7 [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 c+ h; k4 M, r6 L; Z5 B
| MCASP_PIN_ACLKX
3 C+ E+ p; ~2 b/ c/ j' a" ?+ a| MCASP_PIN_AHCLKX
$ P1 V) J7 u1 o: D7 T' b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( t+ R) G" ]# c) B4 {6 n% l5 `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - O8 G2 B+ ?+ E+ V
| MCASP_TX_CLKFAIL 0 ^) M+ O2 N9 z) d
| MCASP_TX_SYNCERROR
3 [7 N2 w$ A2 K$ k- u% w: `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ e! \5 R0 s: W; T, S2 p2 N- O# L
| MCASP_RX_CLKFAIL
6 Y# j& h$ @, n$ \5 K$ e$ S8 m| MCASP_RX_SYNCERROR ; a1 \0 @. K# i2 D
| MCASP_RX_OVERRUN);: v& ? X$ z; h# B; g( k* Z: E
} static void I2SDataTxRxActivate(void)) @; T% f) C2 X- j% X$ ]
{! R8 G H: D2 r8 W
/* Start the clocks */
! n) R7 x2 y) r* {( E1 x3 V! nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 D5 p( _2 @( ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 P* \9 Y! C. a5 C2 i' s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 ^% L! \( B( N9 S8 m
EDMA3_TRIG_MODE_EVENT);* l$ X0 ^$ t3 R9 A0 }2 H' q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' f7 l! `0 Q! ]/ S3 S# Q' T) EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% `. C1 |8 ?& v" y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); h4 f( {( z' W' F* j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" u8 o- Y0 g, k X5 J3 |( K2 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# s: z, v! Z% I; ^- h- L7 }% c5 g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! ~6 Y- O Y+ @, f' Y7 R% U) B7 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 x% p. t! r! Z% r7 z% D4 f} # s' j) e, B- Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! _- S& N, W" o3 R% Y P
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