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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 p5 m* w6 H" p2 N
input mcasp_ahclkx,
: ?+ i9 C2 N m& i# P% e3 Vinput mcasp_aclkx,
U# m* S( _" z( H- \input axr0,' J9 \. O/ c1 s1 Y4 L2 _
2 I% `4 y5 D" n0 c# ?
output mcasp_afsr,8 y" \4 P: w- r5 Q d; J( N
output mcasp_ahclkr,$ ^$ x d G) L0 E
output mcasp_aclkr,# z9 l/ \" k7 b; u( Q9 p5 O e M
output axr1,9 z6 O# ]/ r% B1 l
assign mcasp_afsr = mcasp_afsx;
S. d- X: g Z M a; ^& l3 lassign mcasp_aclkr = mcasp_aclkx;
+ ~: O0 O4 A6 X `2 d% Q+ X: lassign mcasp_ahclkr = mcasp_ahclkx;5 O* Q) q9 U* {! G) c2 @6 _ P
assign axr1 = axr0;
( ?6 H+ q, G$ A3 G J/ O2 d: u& A3 D4 s" B Y$ P) [3 Q$ e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 F% b: z7 A5 R" s3 Kstatic void McASPI2SConfigure(void)
( d' Z6 ~' O8 {, K# [ N{2 T7 f2 E* r' W$ @6 ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 Z) n" c, a* X. B$ t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 K! ?# {: t4 N; {1 H3 A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- w8 |+ K! J+ {2 B9 O6 t6 ]2 zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* ?* u5 J8 b- [* j1 S8 nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: u1 d6 x, z1 v3 RMCASP_RX_MODE_DMA);" t3 E4 L O( g6 E7 F0 }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 u5 ?+ R8 w: ^7 z4 zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* d- i' I; Y* k( y4 H- j2 L% kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 V' [) t+ ?' \1 g+ o9 T6 K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 W) F" D4 y1 l u- ^# L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - v6 w$ a% E" @0 k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 ]' s" v+ W0 Q+ G7 ?! t, rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 k4 c9 ^- \9 U8 d4 {! H9 N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 z' p4 v3 \! ^! P! w j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 C! R8 u/ o. Y" i0 M0x00, 0xFF); /* configure the clock for transmitter */
9 o+ } N6 w0 h: ]5 mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" @9 W/ D/ W+ MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 w6 H: G# A" K$ q% n& HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, A9 W) a) U' t: ?8 W7 F2 ]/ ]
0x00, 0xFF);; ` x0 h. }6 v
. g! v5 `: }( n6 `4 c
/* Enable synchronization of RX and TX sections */ ' P/ H. r: ^; L6 R6 z9 c5 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 u8 E, M9 l8 c' ~" ?1 C* g$ d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 e) O5 B1 \. U, LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% c! c! \& m% f' E1 a \9 q** Set the serializers, Currently only one serializer is set as
4 ^2 M5 h: L2 z+ f4 Q7 b** transmitter and one serializer as receiver.
5 L$ y% d4 g O/ A*/
+ V1 a2 s6 S! _6 XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 [. N( U" |! p T. R0 y" }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ A% n! h7 @# w$ K
** Configure the McASP pins
; h+ W% G, |$ }3 Y** Input - Frame Sync, Clock and Serializer Rx% k7 F3 U: @: b! X4 H
** Output - Serializer Tx is connected to the input of the codec
; \! Y o+ q( h0 ~2 G$ N) U*/6 q3 C, A% `' H* K6 ^* y# a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 X' U+ S# P k3 R4 c6 k) c% S% i) LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 d% W. L1 z) zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ X' u( i' ^! ?$ x8 B( l| MCASP_PIN_ACLKX
8 m1 \% G0 S' c* Q5 ]1 l2 m" H| MCASP_PIN_AHCLKX
. v! Z9 h0 H2 X! L( k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# e- Q" i) C9 m. X9 F! X! D+ {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR \& d4 _) m2 Y0 ?3 \
| MCASP_TX_CLKFAIL 3 N) H- \# P9 l% M
| MCASP_TX_SYNCERROR. \" F9 ?! V; _! c! u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) c6 n) @. W! H7 ?, R| MCASP_RX_CLKFAIL
0 \. `- d6 s3 r4 G| MCASP_RX_SYNCERROR
. C! u6 q! d! B) Q) q| MCASP_RX_OVERRUN);" Z5 o5 b8 @( D0 I+ e
} static void I2SDataTxRxActivate(void)
" m! t8 O- i5 C{
l! m0 l, n- \& a/* Start the clocks */
/ ]' y- M3 w- t F( d+ `+ PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 t" y/ C3 M1 f9 R+ S2 K! EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' s' {* N7 Q# T' FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. T$ V" }- a Z
EDMA3_TRIG_MODE_EVENT);, [/ S9 O2 M1 j9 P' V- c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 H R' r- e* D- \4 d2 W* pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ r- X* [) Q6 T! \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; b9 _% Q1 A2 L" y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 @' u9 E; c- o. f# ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- U. F# d: h3 h# `# d5 I$ y& qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" v3 u. m8 d2 x. ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 b' ]. z$ l+ A. N6 y M9 d}
5 ]" Z8 n6 d7 q' b& E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 D$ i/ ? M3 ~9 B+ Y
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