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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) F, u6 B- e4 ^! |% N; N* Z4 _
input mcasp_ahclkx,
/ z' C. w- W# O# ^% T) G' F: Hinput mcasp_aclkx,
& Z1 i+ ?5 Y5 G; c/ M) R; A) Zinput axr0,5 f s- p4 ^; Z0 `+ v6 g/ u6 E* |
3 M: K4 \3 e: l1 Zoutput mcasp_afsr,
& |- q6 r& R* C& Z4 ?9 N% Moutput mcasp_ahclkr,# O4 n7 k( H7 o5 ` c0 i
output mcasp_aclkr,3 P S/ X* f+ `! y% [3 j% r2 ]
output axr1,
: G/ i7 }. V8 L3 m2 ~9 P/ \) e assign mcasp_afsr = mcasp_afsx;5 N6 S+ n: _- p* m: `
assign mcasp_aclkr = mcasp_aclkx;% K+ x4 |* f; v% A$ H R8 j
assign mcasp_ahclkr = mcasp_ahclkx;3 q$ S8 R1 x: ^2 x
assign axr1 = axr0;
, R. L- w+ D$ A( w' y1 s
& z. w6 P4 D% ~3 G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, x5 B' g. I+ n! ^3 y3 `static void McASPI2SConfigure(void)
. n- v/ `3 H( `# h7 D$ B{& G( i" [# G$ q8 F' m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# B7 M& |) W0 g1 C* Y+ a) dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" N+ S/ _' h- I+ _0 d4 NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' f5 L8 a# C0 s& ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
n; t: b) ~; J; w! W, OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, P" s4 ^$ T1 @1 Y' HMCASP_RX_MODE_DMA);4 @" M% g4 J: V+ I1 k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& Z, O" B2 |/ Z$ w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 H$ F" o) q( l M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; L1 s9 d! o* F9 u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* i$ N! D6 V. o4 G0 A1 tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , l5 `4 R# }1 c/ l4 G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! [ g o1 X: [3 H) l* M" i) T- oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- `) P$ N: a$ d# O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" i Y3 {/ I* F/ e" b5 E7 Q* r! UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 k* }4 D- j4 Z1 J
0x00, 0xFF); /* configure the clock for transmitter */
$ h, E& o8 {9 s9 V$ H% o3 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" B2 \% F) h$ `5 }& KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 K* {0 n# u6 a9 I7 o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- Q. B! l& A! x5 {0x00, 0xFF);
+ ~& t$ t- d+ q5 f) D3 ^$ I# J0 Z) x
/* Enable synchronization of RX and TX sections */ ' E+ P1 E6 R/ l0 ^( M) M0 }) h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* I5 d1 D* ?$ e1 W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* U0 g' U- G+ z3 P$ r9 {+ |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# x6 x8 M, y8 q+ B, \- @/ ]** Set the serializers, Currently only one serializer is set as
- J' C) r" @, M: V# I3 y4 f, e** transmitter and one serializer as receiver.% I- `4 ~4 m) m" u% d8 w/ S, z" {
*/
0 r/ L C+ G8 E: C* [$ sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) q( b3 a8 S2 \8 G' L8 R# c6 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' Z2 g2 U4 @2 m! w** Configure the McASP pins
' V* l8 J3 X- ]2 Z' O( r** Input - Frame Sync, Clock and Serializer Rx
& e7 W, u0 C$ N2 y" u** Output - Serializer Tx is connected to the input of the codec + c d5 a' w1 b8 T6 w
*/
5 ~# h A) M7 \9 J* A: oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 B( r# |, y3 O3 E" g. _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% f; v! U+ h! n2 a" BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# J- _3 R' N+ I3 j7 {, ~| MCASP_PIN_ACLKX3 C% A6 Z& `0 ]& t4 m
| MCASP_PIN_AHCLKX! J. |( `$ H, D1 M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" p* R" g( @5 |8 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: L& \& G- O k% v1 J) s| MCASP_TX_CLKFAIL 8 P6 y [ e9 U1 N2 c! o
| MCASP_TX_SYNCERROR% Y5 U1 t1 q9 ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. f' W2 Y b! G| MCASP_RX_CLKFAIL8 A: k8 {1 O6 g+ K/ y8 {6 F: r
| MCASP_RX_SYNCERROR $ Q2 X) @1 D$ {
| MCASP_RX_OVERRUN);4 D1 A' C3 f. l0 g3 l2 y7 p5 V
} static void I2SDataTxRxActivate(void)) g9 e; l( P2 H4 Q. S" y
{
! r6 }+ i7 v2 B+ k0 F* Q2 _/* Start the clocks */9 X( _3 n+ p( `% Z8 P. Q" p6 ^6 _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ D4 u" m/ B4 |0 p3 p5 z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 y! A* y" S0 t) a% |: B/ ]1 { n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' F4 h4 d3 y: d- y% h5 Y9 i7 iEDMA3_TRIG_MODE_EVENT);
* P, O5 z& B& j8 [7 Y- Z& V2 f8 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
L5 }/ `; ?: L7 Q" Q- AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* O3 ]% w9 X7 _$ C- [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 `7 a! l) k1 D4 t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 C; M- z4 Z! ^- x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, i8 m( [# @# b$ y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, N- f& n7 f$ P0 JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 l C- ~" ]" r+ B: ~1 C}
% V# q( o1 Q. p+ [( }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 P4 \4 A0 P& N: h
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