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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. V7 [/ n1 ^7 u9 {0 b4 r& [7 Hinput mcasp_ahclkx,# |9 M* w$ ], [4 J. {
input mcasp_aclkx,( G, y4 C: I3 a; j. i) b
input axr0,+ O: `/ i3 o& c# k8 E- i
" g7 @5 r" A5 Houtput mcasp_afsr,& [9 }- n" r3 ]1 y6 P+ s
output mcasp_ahclkr," T. T9 E/ ~% n2 }# H: d
output mcasp_aclkr,5 W/ }2 F" ^2 c" @% | `
output axr1,
% g3 |1 Y/ { ]9 j assign mcasp_afsr = mcasp_afsx;# e! m6 \( K" u" h3 {: J; q
assign mcasp_aclkr = mcasp_aclkx;
/ @1 z6 q4 C5 h) d+ d8 kassign mcasp_ahclkr = mcasp_ahclkx;
* j0 Y6 L/ w$ q5 h' Vassign axr1 = axr0; 0 q" x# r/ B; g
- Y' ^% q) F- R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 r# x. Q8 h2 Z( g# \; y3 E
static void McASPI2SConfigure(void)% {; X' C" y/ \, z' o: d: z
{( r; f! Z$ e h% g, `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 ]- U" o8 D4 D; w3 B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ K- }3 C0 w; I! j" }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, g9 W2 }( @, Y% H1 R; o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 I) r! G/ h/ n5 h Z; fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ V, f, I8 g3 S% P( ^" d6 q& [9 nMCASP_RX_MODE_DMA);: @1 k' I8 j& g* G8 z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# t% i6 f' M" c% i4 LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" W. [+ M. x, V0 n1 H% @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 U1 B, j8 D& u) ~- ]; r# H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" b2 e5 ]8 p' D1 T* J, e$ K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, c3 ~' Z+ b6 n3 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 m. G$ M! M& P. @- D% e8 r9 k* x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: }8 y& m3 ^% dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 X" q& E9 ]6 y( T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* {! h- W$ d" t- D0x00, 0xFF); /* configure the clock for transmitter */" o+ C j: m0 j ^0 W* I9 Y) c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 M$ c! R: k+ o2 O: YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# @8 @. Q8 w/ R2 }2 Q0 k3 IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% {. ^( P5 I! M
0x00, 0xFF);+ y u5 ?3 U) M
$ Y3 K% r3 `9 P. ^* ?0 e, J- f
/* Enable synchronization of RX and TX sections */
# ]8 T X! }) I0 |5 MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: p) [3 `; e% i1 o, T' j( k: R/ T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 W; \: q ^6 L% d4 p6 ~ E$ H6 C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; |" f/ M1 \% }5 b5 i** Set the serializers, Currently only one serializer is set as
, k" E# ]& e3 o. I a& B9 P** transmitter and one serializer as receiver.
( w6 L! \" u, E*/4 m9 R; X7 }3 `- s# f6 @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 F8 |6 g2 t/ _& ]9 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* s* i, O( X" W** Configure the McASP pins
* Q' w1 l2 J8 u** Input - Frame Sync, Clock and Serializer Rx' o* Z- i' ]4 J4 n& t
** Output - Serializer Tx is connected to the input of the codec o/ J( L9 d" r1 }
*/
* e9 c3 H6 j2 H& qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& L/ ]! a8 q- b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" v2 F: N6 f/ E+ K: k# G* r/ J$ f) `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
M, O) D2 a0 i/ l6 } W| MCASP_PIN_ACLKX' R ^: X; B# Z- Z# h4 e
| MCASP_PIN_AHCLKX
' C4 b l$ Q7 q: `" d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- B% p1 E( B$ x/ i0 rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 r: g, \# J7 X2 y4 S- c! n4 F
| MCASP_TX_CLKFAIL
5 |9 u$ s2 m+ q' b6 E| MCASP_TX_SYNCERROR6 Q- Z- [+ z: Z6 p; E( }2 O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 K4 B8 z& S) ^% {1 N
| MCASP_RX_CLKFAIL
9 b. j4 u6 h( I5 a0 c; }6 a+ B| MCASP_RX_SYNCERROR - Q2 k* F( y3 q w2 A/ T
| MCASP_RX_OVERRUN);
M: d4 X: H) v, u4 ^. |} static void I2SDataTxRxActivate(void)
- A2 @7 V" |& E, f6 k; c& K{
+ I+ [% Y7 h) y# {1 R: E3 E/* Start the clocks */* L' I5 \' W" b% a! \ V2 K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 I3 Q8 b+ \4 |$ _$ KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ r5 A: T) ]" }' M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, F, Z$ l( D" p. P5 R! \' l- K
EDMA3_TRIG_MODE_EVENT);3 N3 y- J0 x( a$ H) q9 f6 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 t* D% U0 |! Q2 IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& m1 V4 H' l3 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; K$ d$ G, H9 `* [+ @$ }- s }% EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. }6 l. J3 p" h, ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( ? p3 n4 A# J8 S2 {) j! hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! A$ X% \) T% D0 q+ P7 h+ D AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& z" \( x( Q% I1 N* B# n
} + Q$ W$ h+ x. L+ n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 |. ` y* }6 F6 I' i
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