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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 V8 T' O" G" m6 [) {7 U9 T* m
input mcasp_ahclkx,
- s3 p+ B0 p& _* S0 ainput mcasp_aclkx,
, h; h. Z+ Y! g0 j/ c* D- kinput axr0,
3 T% i5 J' y2 D# c3 E6 ?# y, E7 x- R2 F
output mcasp_afsr,( k# x! |' o+ l* r m/ S
output mcasp_ahclkr,* ^5 D0 Y+ m2 z: n5 u: H! [# b
output mcasp_aclkr,
! E N0 m( i& R. uoutput axr1,
# x2 @; b4 D& a' c' K( u2 ~8 A assign mcasp_afsr = mcasp_afsx;
; S2 j! r- P/ g& u) S8 B Uassign mcasp_aclkr = mcasp_aclkx;: H- c+ J! j" F6 S: j1 V
assign mcasp_ahclkr = mcasp_ahclkx;
: ?* g/ E+ G9 z: n gassign axr1 = axr0; 2 u. ]/ r! j0 c9 _
( K, K; O* ?* S) J- W Y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % E. D) I8 o0 x9 z4 Y7 L
static void McASPI2SConfigure(void)
0 p& h2 Z y8 _; ?0 z6 W% j{
6 g8 N5 t* @( B$ W7 ]) rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 C" C- R& i& g# U( p2 N5 n( \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ p" c6 L4 b+ V/ M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, H" [: Q7 P/ Q1 g, S! x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ b/ a; B! `& U5 z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& c( I% m2 O/ B+ ?* aMCASP_RX_MODE_DMA);
( ]' I! R2 o( n" l( C: r @; s# YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, W8 ^4 H5 y9 S! B9 l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 r2 o, o+ Z/ o% F' {9 l! a, s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) O$ g1 X$ Q/ H5 i. N7 WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 z% X0 h) d- [( n2 jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + [# k! q. b- m6 k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 `# W: t2 h4 c7 Y. k$ c) {. WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* I, \7 |: C0 R8 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 F3 ~. F+ Q4 g7 B- B3 [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* Q' n; m. [* K t- I0x00, 0xFF); /* configure the clock for transmitter */
% s( T' P$ g3 }( h: {6 iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* V2 {5 Y' K: Z* x4 J; SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% n6 k* c& X0 g: M( CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 b' x5 }4 ^8 V& u0 V# F2 l8 k) q1 p0x00, 0xFF);
, _! X! a$ P) W6 i4 m* B5 a. N! v9 Z3 e0 C s4 Y# L: L' ^
/* Enable synchronization of RX and TX sections */ & d' r L6 H, H0 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 D4 Y# ~: K# _/ x3 w6 t; x7 t! v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
I/ H: R: O+ ~2 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. y: H1 o4 @7 P+ Z, [, D% Q, q** Set the serializers, Currently only one serializer is set as
! ^2 J3 s5 H( m/ w7 i8 O* e** transmitter and one serializer as receiver.
8 P# F5 }, e2 W5 ~+ G, R*/: x# {' I* X8 d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; l, ?! C: o h# E* I- k' |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 u+ ?2 Q! p. M" i** Configure the McASP pins
) ?) B' V; T& J* b$ m: M** Input - Frame Sync, Clock and Serializer Rx
+ B# |% k8 Z& d, ~9 v** Output - Serializer Tx is connected to the input of the codec 6 A0 v' A6 g9 ^% E3 m( e" Y: c
*/4 i% f; q7 ]: P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ C+ w3 n7 i( ]5 o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. j- r8 a0 e1 p$ E/ s7 U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" o: w, g; Q- S# ]3 I8 D| MCASP_PIN_ACLKX' d( x- d" _2 B( a! U# S8 M
| MCASP_PIN_AHCLKX! n3 w; D% J7 M& d: c2 x" m8 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; Z1 @* g1 s2 g# I+ p) _+ l' pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # l8 n7 ~" i3 x* H8 ]
| MCASP_TX_CLKFAIL
- a) t6 a/ S0 B" R6 |0 A| MCASP_TX_SYNCERROR T: P0 r- b: O/ \. H2 _6 M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & I# n$ G& P2 P
| MCASP_RX_CLKFAIL* K5 H! i, G7 S* m7 x* e8 z- l
| MCASP_RX_SYNCERROR 6 k9 Q/ A* [3 a; P# W# K
| MCASP_RX_OVERRUN);
; s6 k5 @/ M& b7 \; |: q} static void I2SDataTxRxActivate(void)1 U3 i+ U _8 Z4 V) d- w( k. a. v9 @
{
' U6 K% ?3 ?% i& J3 r3 z/* Start the clocks */8 k, c6 |5 V2 V* U7 \. v" {( d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% r, b7 s* K1 N, T5 j3 h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 U& j& V1 \ ^/ }- I& i. E) x& qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& B6 K, |8 U8 Q0 y, GEDMA3_TRIG_MODE_EVENT);7 s% P2 k M; p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; n# P* V0 f- v6 n" |( |$ @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ P6 H. P6 W% W& \" ] B) T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* C( {0 H v/ h3 l4 u6 MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 x/ ?6 U, [; Y$ t9 u& p/ O+ Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# `- M& L, |" d. [3 G& ^; C8 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 }4 a* M: r; ]: `, i3 [2 j' r1 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* U, N9 Q% b$ C
} - D. s0 }- U% C0 e! ~8 B, e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 c |9 |# p3 w7 K
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