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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) e# v& h; S) j' W X4 |! |input mcasp_ahclkx,
9 \7 N: _/ N3 _9 A0 L- Binput mcasp_aclkx,
) K3 n B$ _( tinput axr0,& B/ p% H/ @! y
5 i: Q5 A$ |$ v( r; s# e" V
output mcasp_afsr,
! G- ?7 ?0 i# o; R4 C/ z; P- b/ zoutput mcasp_ahclkr,6 i3 ~ _' C9 \ H4 @
output mcasp_aclkr,0 U; d" q) C ^9 I8 J$ b
output axr1,$ {, t+ Q$ D6 p- H
assign mcasp_afsr = mcasp_afsx;" B5 i) S( t- Y2 A8 s) a. y
assign mcasp_aclkr = mcasp_aclkx;
4 ^/ d# U' s7 `" uassign mcasp_ahclkr = mcasp_ahclkx;$ l7 r# U6 A, v1 t1 _: ^1 A) F
assign axr1 = axr0; ) e0 A+ Q, K U9 ]2 p/ X Z( k
4 c! ]7 u+ v- C. i! m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ z3 c6 a) s) s. b
static void McASPI2SConfigure(void)
/ G. P, P% U% T5 [{9 o2 E4 `: e3 V7 c+ q5 G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 T% H' D/ E; `0 I* KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# r% Z# q' S5 y1 s6 z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# b/ m; L' q; G$ tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 c! V9 ?: g- H5 AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 Y: e" G0 L |! N" ~: w4 w
MCASP_RX_MODE_DMA);# {3 ~- [ j1 e5 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 x# r! k; s+ ?( e$ Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& O3 h0 b0 H; W' dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 Z; g3 W1 n3 W# WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. b8 d- m+ q9 l; W/ H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 M, `9 b- [* H0 ?% F; H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ @' v# n9 @. w+ ]' p4 W& n! PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 z# g3 ~7 h. \/ e3 _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& V, a6 g/ O% z) f% J8 \2 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 E3 N* R: S1 _0x00, 0xFF); /* configure the clock for transmitter */
* G# H# w' K% b" r: m% m* O. kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 ]6 }/ A7 ]7 S/ a/ H4 `- _% _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , Q+ @2 Z6 I; @8 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ }# X* w- {7 c( E$ h* x, b0x00, 0xFF);7 c9 Y0 n" ]. e' R2 v2 b
$ \/ X% G/ S0 l* d: Z( q7 P6 m/* Enable synchronization of RX and TX sections */ $ X: I1 q' L/ [ H. T2 M3 @% W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 H! A7 t8 j& _ e+ A9 q) a V" v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, {' ^* g( p" P. V! `% b3 {' ^- ~# TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 I3 _( N% n+ ?8 I% s5 V3 K2 U
** Set the serializers, Currently only one serializer is set as7 F* @' H& q: X/ o& S
** transmitter and one serializer as receiver.0 y3 ` m' E2 j. L8 T
*// n7 n' V) s" E* w0 y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ @" H8 b) S! y @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# e% G# Z9 Z; `
** Configure the McASP pins
9 E6 f3 r3 ?. [- [** Input - Frame Sync, Clock and Serializer Rx
# y% Y$ A# p! B# ~** Output - Serializer Tx is connected to the input of the codec . ~4 m3 H" R/ d) |$ u
*/
# E+ Z: H( G3 t5 f* { pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 V6 K% ~! r/ K, Q& I- |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ w1 E7 m A" n# u' ?% }; Q! aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 }3 x8 D2 S- }& l" H0 h/ v5 |
| MCASP_PIN_ACLKX5 m# H; m3 |0 e C) G5 q: m( x
| MCASP_PIN_AHCLKX
8 ~9 j; T# }$ x3 \% M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' x! @* O) ~/ d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* _; l8 s$ w% z( p5 ^4 Z! e; E| MCASP_TX_CLKFAIL ) e" c' l# A& j8 _2 o
| MCASP_TX_SYNCERROR- O1 l: ^: L3 q) R! }3 Z1 B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 [0 | W" v6 j: h; X7 A# x7 m
| MCASP_RX_CLKFAIL4 U5 ?4 u% ^1 R% p! Z
| MCASP_RX_SYNCERROR
& R, i; |/ R* G9 |# c9 @| MCASP_RX_OVERRUN);# D7 ~0 z$ {1 N! x, _
} static void I2SDataTxRxActivate(void)
p! E* S4 Y/ @{
' N. o8 ~" \9 ^7 j& I$ f/* Start the clocks */
. z4 k. @% W! W0 [, XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ @. b. B# }2 ]8 g4 R7 gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# Q' R2 F! y$ i* a5 Z/ I) [1 v$ X8 ?% lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! s6 f3 ^1 z3 r, M4 M6 e+ ~- K3 gEDMA3_TRIG_MODE_EVENT);
8 I( S2 K/ s% `6 I( ?( h" ~0 Q$ i$ YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% n0 m" f+ @5 CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% M# \3 k0 |% m1 m4 s& Y3 [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 n0 a( _1 G b( z! ^6 A% C1 u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ K* D b7 O2 P: H. v/ v7 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 [( z* |/ c$ o7 Q" N8 q9 M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( H: N. O: }: nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 v& E3 t1 I4 r' f& `8 c}
: ~, F$ J: ?4 r( g( I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 h: c/ a3 q" V" C4 G5 _: S
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