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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: J, L+ I, d% t: U" U. [3 P( O. Yinput mcasp_ahclkx,
3 p z: V& W$ N+ y9 @/ ninput mcasp_aclkx,
+ N1 H6 Q% C3 [ ]* linput axr0,+ \2 W* i. \! W3 t% A; q
9 }/ T0 Z( ?1 H$ noutput mcasp_afsr,
' ], b& |5 m2 k+ {& a6 O$ N7 foutput mcasp_ahclkr,
5 L6 b; |6 L& g% G6 ]output mcasp_aclkr,
( j9 S+ H# w9 I) }, D6 coutput axr1,7 k( y1 X, M# m: l* f, D2 s
assign mcasp_afsr = mcasp_afsx;7 W# D' L5 Y' y2 ?
assign mcasp_aclkr = mcasp_aclkx;% T$ F- t2 @( ^- T
assign mcasp_ahclkr = mcasp_ahclkx;! p+ W5 G) m( s o
assign axr1 = axr0; 3 K, I7 \1 l1 }2 g8 b F" I# |+ H
' C0 R, s" ]# {, i7 b- _. ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 T/ Y3 `. B: O$ g! k: O/ T# Z
static void McASPI2SConfigure(void)0 R- z; N4 b5 j( L
{
# x* j9 t. j2 @+ vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. F6 q$ a1 N: ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: X9 E+ q% r5 t5 k/ W3 R# [( [) T6 LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: O. {1 R' j6 Q+ Z/ B% i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) u% P" u) r: U* pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ s( K1 u1 j2 k5 t: G& r# T& V; \
MCASP_RX_MODE_DMA);
1 @0 o* X' \1 Y, c: g7 zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 b0 p- Z0 T+ Z# ~* V0 v' ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" q8 N. z( o' AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 d- e& W% Z* c; P& w6 p! m8 d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 F' w$ L9 u% y( oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 W4 T9 z8 M3 P u: n' z/ H c- u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 C5 z4 S0 x3 s- N7 Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 J, U( k; r) J" S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); C: \* n6 |+ P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, {) H; g6 E8 ]; l0x00, 0xFF); /* configure the clock for transmitter */
& a7 s- t0 z6 MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' s- U* L$ f t2 EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 W/ b: w0 ]( LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, f) R+ _4 G( }; J
0x00, 0xFF);
) Q5 q6 I! _! ]0 ]% n0 z* u1 B2 A- @* z: w% ?. O' _2 F3 B+ h, b
/* Enable synchronization of RX and TX sections */
+ e" A3 {3 `7 v) {0 f) w: P) m- bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ w5 z! i2 E |$ g1 Y1 s- P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! ]+ N2 F3 \. L2 {8 F; n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ |" A8 L; z0 X& h$ E5 o& X
** Set the serializers, Currently only one serializer is set as
1 N/ U# c/ o+ Z** transmitter and one serializer as receiver.
7 K" x) E+ z9 w8 X/ y# z*/- V( @" o1 W3 i4 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! H1 a: ]7 z) N9 B9 _6 H: @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* L/ {$ D& q8 K$ f% M
** Configure the McASP pins
! I# u" M& G! R6 x, U8 `** Input - Frame Sync, Clock and Serializer Rx) U V* C* Y3 S3 A0 g3 D
** Output - Serializer Tx is connected to the input of the codec 3 C- d5 a$ Y: L, b x
*/$ T3 l: T& |# L) u5 `' v* i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& Z! s B% ]& S! z; b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% k# @; S# ?- W/ XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( ^8 G5 ~( H7 l. E; Z. I' a
| MCASP_PIN_ACLKX
, U6 J P( h7 p5 P) m9 @( D| MCASP_PIN_AHCLKX! |( j' r& C* j+ H# g' W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 n3 U* U' I3 K* lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# u+ t0 J' Z1 e: H- V! V( w7 p| MCASP_TX_CLKFAIL
* w) ]/ o6 e/ i: P8 X2 v4 E| MCASP_TX_SYNCERROR
0 D3 |6 f9 ^, W6 v' e }( r( h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : q/ d9 X( N7 e5 D8 p
| MCASP_RX_CLKFAIL# m, P. M$ V& g! ?' t4 u! T- p
| MCASP_RX_SYNCERROR
5 }! d. M; @7 b: B# r. L| MCASP_RX_OVERRUN);
5 H! D: [0 K4 d. ?( h/ d `} static void I2SDataTxRxActivate(void)
- d8 m1 e% k8 p" x: R$ N A7 u{$ }8 h% I+ l/ X% W: C8 I& ?5 S8 _
/* Start the clocks */. [( l0 b1 g+ c6 b9 e4 p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* N4 A7 o0 t" n" DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 Z# `" ?5 Y1 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 P) u9 T. G4 C& Y0 l M0 b
EDMA3_TRIG_MODE_EVENT);9 a/ f' s3 j% N4 W/ b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( v. \+ F) H9 Q0 Y0 b" P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* A: X$ f' `4 uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 W. \- Z8 u/ h0 _! m; {+ [* f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ k0 o( `6 F$ \9 s% ]5 `5 Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( A4 ^5 \& u5 G7 b7 k5 @4 XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 v! g! w! A6 p' D/ `( [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ R2 t6 g+ j. j0 B7 R1 x& G}
# i b, e+ d- l0 v/ e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 J# _0 g2 j( {" m$ m4 C0 ?+ k |