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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; X* o# H: P8 W' minput mcasp_ahclkx,/ D( j' F* |# n4 o- ?
input mcasp_aclkx,; }- L: n: G2 Q7 o3 s, D
input axr0,
8 V6 Q8 Q5 V3 U b ~! v# N- u1 b; J. }5 ]' o3 G
output mcasp_afsr," v6 s X+ ~9 D( M
output mcasp_ahclkr,) d5 L6 u, t) O7 X% p' \
output mcasp_aclkr,& m" j4 `% a$ P5 E
output axr1,1 H% X3 G! K1 C, C: {1 x
assign mcasp_afsr = mcasp_afsx;
# Y" P4 y) B9 g* `0 `assign mcasp_aclkr = mcasp_aclkx;$ F2 z" |: J1 m( D
assign mcasp_ahclkr = mcasp_ahclkx;; E* y! u' N/ O# K0 P+ ^
assign axr1 = axr0; . F9 K F8 }) |+ R$ A% Q6 x# q6 E
& J0 V0 g" I% u3 ?6 y- q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ s9 q9 u1 Z' K4 Rstatic void McASPI2SConfigure(void)
& H4 {# {" M+ n{' k( V( J) h; p- c2 k3 U, P T9 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 i, @* a) W1 T- L6 u: oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 z, R$ o) B& U+ V. E4 z* e+ c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% B' v' g! K7 V' O6 z, _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ |+ J3 V+ Y4 @) d& C% ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* L! Y# Q( P+ H* l+ u) _+ |, lMCASP_RX_MODE_DMA);
7 Y, q$ v" ]4 B9 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& L. x: E; |; m; ^" y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 R0 q$ n. q5 w& X, P. `6 D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % o; w. s5 ~- a# x1 S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 Y; U" ~0 b* H8 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& k3 b! ?* N& a( m7 rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ `; F# `! r4 d9 r3 q- J" ^3 b' W7 I0 bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# t7 F$ w, S2 p& O0 T M, QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 W/ Y2 a, @) Z* ^( I- E4 o" j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: i+ b: I& j9 v% C0x00, 0xFF); /* configure the clock for transmitter */
0 u- F# @! i( [" A$ I5 TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* R% ]2 l$ l2 d; _, a- \ F' QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& G$ ?$ ?! w# _7 M5 ]. [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ i$ S0 H7 x! ^" M+ j8 C
0x00, 0xFF);. X# j: R: P2 [* _6 y, M9 U# Z f
$ b, s3 G, `+ l; _3 T/* Enable synchronization of RX and TX sections */
. R/ ?- E% k0 d* b" J. gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. E3 w6 ^6 g. s. R# ]5 R5 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 R) n* E( O# b" Y# s# }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 C$ N3 e1 ~% r' Q( R0 }** Set the serializers, Currently only one serializer is set as
8 u- D9 U: l8 w7 A& d3 [** transmitter and one serializer as receiver.) Q3 o5 a6 H& R/ ~- J7 t3 y5 c
*/
: j2 C7 c2 u7 U; BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. R% F9 z( ]3 \9 X. b7 A9 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' o' o1 |& h( A. U( E S
** Configure the McASP pins - ^( H2 {2 ]# n
** Input - Frame Sync, Clock and Serializer Rx
8 _- [+ G0 x# C% q5 Y, W* f9 o** Output - Serializer Tx is connected to the input of the codec : K, a0 ^+ U& g1 n$ k& J
*/. K. S/ @; p2 z" j7 y( \1 |. n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 @) b* m4 w7 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, f4 G1 i! Z' A; E" ^ e5 V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: m1 m; X! {/ J
| MCASP_PIN_ACLKX6 M k9 |& o3 [' f5 |* H
| MCASP_PIN_AHCLKX
) g( Q; k; A- z( l, q2 M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
{) E" y1 v( |7 x: o, `$ C% uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - G; c q+ Z9 v
| MCASP_TX_CLKFAIL {! e9 ^: f/ ~: Y' R! p
| MCASP_TX_SYNCERROR6 O. p. S, n2 O) S& a8 ], |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 V- I# z9 Z+ C; Y f5 l" ?| MCASP_RX_CLKFAIL
/ r& o6 u* m \( z" o' K5 I) ~| MCASP_RX_SYNCERROR
: o1 r0 m( P- u/ g) ]| MCASP_RX_OVERRUN);9 v+ v9 n$ V# y* e4 d; J! H* b
} static void I2SDataTxRxActivate(void); _) k$ m/ X! E1 C4 g( V" J
{
. C9 w8 \3 B. o _1 g f1 [1 D/ c3 ~7 t/* Start the clocks */* D6 c5 i+ [3 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' U' Q* j8 A- @0 N$ p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 y1 |& r/ H1 }! A+ ?' F9 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 P4 y" p4 Z5 \. o
EDMA3_TRIG_MODE_EVENT);' ]) `5 v, |1 B( D+ s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - b6 q, }# B7 L: M6 Z" z. Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 v) o0 k3 I3 J7 lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* D& U5 k& ]7 H( ^' z! N2 @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* [% \1 K6 m6 _3 e' e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; {* g& ~% a; }1 E. ?& C: j# SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( ?4 f a; Y- y& I+ F* f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 ^* y; t U, K, K
} ; h8 R1 p" A, u2 M8 ^& X# Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' x' }, \( H {& V
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