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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) x0 h/ K& s5 |, t. ?& e5 R/ finput mcasp_ahclkx,0 {" u% ]* _& {# N# U7 m* T8 e
input mcasp_aclkx,, ?; }2 ~: Z% T1 B! Z9 c' v
input axr0,+ A i+ X8 z8 Q8 E. J
5 P7 e; z4 R7 o' b( }4 `output mcasp_afsr," I4 j+ s, `: r/ W2 U( X
output mcasp_ahclkr,
- |( |+ W2 d0 Q: aoutput mcasp_aclkr,
" e0 V1 s& Z' y- R) m* ^/ Boutput axr1,0 V1 J5 o1 c. V2 K
assign mcasp_afsr = mcasp_afsx;
, `0 j: A. C _1 Tassign mcasp_aclkr = mcasp_aclkx;
) C2 d7 W% l4 t3 A6 ` V) A( y1 Rassign mcasp_ahclkr = mcasp_ahclkx;
) ^3 _- L: E' m7 ?/ tassign axr1 = axr0;
6 `. ~6 U4 \) y; `% K) b# q3 x7 d" O0 P: C5 g1 N2 b4 O: g8 n6 K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& H- K2 J% w$ p+ K3 u: ?0 q3 |static void McASPI2SConfigure(void)+ @, T+ ?' O) X$ p f$ ^* t% V- a
{
7 y; G6 I3 b5 o# R3 R t7 \6 m% \% P0 m" K# IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ X( F, w0 Z; M4 n: J; D4 h7 u6 T% ]1 V9 fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, j' d7 r9 z) {; C0 K6 j1 d. z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& d5 i* ]; G, ?, K' v. KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) O( g5 [! m1 E' q. N2 ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# t8 l# r+ |) i, {9 o
MCASP_RX_MODE_DMA);3 }3 H" g7 H2 Y3 l4 M' k% p: A3 H0 M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) C6 ?/ S$ ~* x7 h. ]- TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" B/ P S3 Y9 i+ n& e1 Y6 O; G/ GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 _0 Y5 g* R$ qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 q& ^' p& W% k' Q4 E9 ^. e/ D- Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! h! d9 r5 Y @& M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 S- y* [* P$ g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 D( t8 X' C- @/ C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " ^; `3 I8 N- D- t7 h6 H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ Z* X" {1 G, Q$ M. }1 T0x00, 0xFF); /* configure the clock for transmitter */6 O. N: O$ L- q" Q2 V+ Q1 M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 l2 n8 q3 h2 c/ |8 bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & X; Q" A( v9 {5 ]8 Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% O# Q8 q: P% G+ H& G9 y
0x00, 0xFF);
8 ]4 g5 X; N c" V7 o! C1 V9 x+ y- c- a
/* Enable synchronization of RX and TX sections */
+ J8 [. U" j8 EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: C: b- S+ _( L" z2 o! IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 c5 w+ z2 M( L! h: FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 h# ?- ^: z8 h3 ]5 v
** Set the serializers, Currently only one serializer is set as; \9 k2 X7 X3 n( e; R, v
** transmitter and one serializer as receiver.
; {* \5 v1 P% q. i- k*/( O; r# z" y& {: Q7 t% V# ?. o$ y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% v/ L' v! k& R. y7 P7 t) AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ E0 a' D- ~+ W) v9 j
** Configure the McASP pins
, ~: S$ I5 W' O1 B3 a1 d( b** Input - Frame Sync, Clock and Serializer Rx
! a; ]- ~- f/ y K) d( N/ b& Q" a** Output - Serializer Tx is connected to the input of the codec
( ?: z4 M/ q! i& g6 O) G) D+ Y2 w; v*/
" O& w9 T1 K7 E& h: |1 {8 W* OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' w/ E# s3 e/ ^1 }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 l/ k8 u5 C- P' `5 N' V& z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. c( w8 W* q9 W: t# v
| MCASP_PIN_ACLKX9 q3 |! o I; D- t- z
| MCASP_PIN_AHCLKX( Q# Z: K2 x5 o1 Q! m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. [4 y: ^/ }& _- J/ N C) c) P0 q7 R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 a6 \8 c# H: n! g$ v* l3 I2 d" K
| MCASP_TX_CLKFAIL 0 i% \' a# ?6 j2 [7 I R
| MCASP_TX_SYNCERROR! `* Y& n% X, h; O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & F& u& _/ B# P7 N5 }7 ]
| MCASP_RX_CLKFAIL2 y. ?; e/ v" }* D2 ~" p
| MCASP_RX_SYNCERROR
: h f+ v1 K. {| MCASP_RX_OVERRUN);
2 a1 m* t4 `& Z- O} static void I2SDataTxRxActivate(void)
m! {( O- S" v j* P* r6 X/ D{
! [ x5 x4 e/ S4 o2 l8 |& }/* Start the clocks */1 c `4 I/ w6 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 ]) B0 k5 e0 i0 `. {9 _6 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ G1 W$ Q; n. NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ \+ w/ S& t ~2 H4 R, B# qEDMA3_TRIG_MODE_EVENT);7 G: S7 \6 Z1 u- K3 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. m7 n9 p0 O) S0 M( o- i2 jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& J. Q4 N1 u N6 W" T+ q' t8 S2 `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 h; |% A, E- u$ r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. W+ Q5 ^9 y% P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 ]4 x5 v( J0 S% n4 g2 R7 oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) S4 t1 ]% W! U6 ?0 G0 S+ iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 p4 l' M; v! y% w}
1 R- m# P0 y$ c% ^+ O* [" B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 h1 f- A9 t0 P: Z1 Y) s8 c
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