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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ d1 l. y4 z( X' ainput mcasp_ahclkx,) I0 l& `9 k, K; [! G5 r
input mcasp_aclkx,
% [% X+ P) a* @/ ]: U, }input axr0,
/ e e4 H6 y. B1 O& o+ r5 V X
4 X ~, S y8 F6 s' x' O8 Ooutput mcasp_afsr, o% p8 T ]# {& o8 Z
output mcasp_ahclkr,
' S7 ^! v2 _& R2 Q+ ~$ n& Doutput mcasp_aclkr,* x$ k: d% h6 I4 Q& l4 c8 [. K6 |
output axr1,$ Y$ I# V: [$ Y4 H6 ^. l' a! l
assign mcasp_afsr = mcasp_afsx;
+ P0 O- R, V/ F4 W* S" X7 Massign mcasp_aclkr = mcasp_aclkx;& @+ T% @& M3 I% Q" e
assign mcasp_ahclkr = mcasp_ahclkx;
( `+ l/ m& B+ |0 @. W+ `assign axr1 = axr0;
, j; Q( y* g4 }" K9 t( @" u0 D; G
5 m7 G+ P6 \( k4 V! M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' f: ]) e; J' l& U- Z
static void McASPI2SConfigure(void)2 p$ i2 i6 ^9 ?7 H
{
2 ~& S, v2 ~4 mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 _: s' f5 x. `0 e- ]: qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% Y1 |& p2 L& V! m! dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ _8 m6 K4 ^- TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- m* k3 z. {1 S' {+ N; cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 D" \7 f( C, [' c+ ?- \
MCASP_RX_MODE_DMA);& D3 I( T" K7 F- y" v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) x1 q& J k, b5 T. ~1 wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 K# W: H3 ]; A, \5 ^. Q: [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 @- L$ U a) L' t' G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& o u: S, T( T& @8 T! _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; B Z8 b1 {6 iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ m0 O/ d; Y* q$ l. z. k2 bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% R, W/ ^; g F o3 a1 t: k8 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % \( E* N8 k) w' f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; U: A' L u, m1 |0 m0 X6 `* q
0x00, 0xFF); /* configure the clock for transmitter */
# {% E' ~: Q+ LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ e4 d Z( P# T: o2 \; s7 W7 v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , X+ w! h8 u7 j0 d2 \6 x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* S' \, F+ t$ E& m& X5 l% v0x00, 0xFF);& ]. R1 x! l* k7 b/ S9 f, b5 n
& }5 r( S6 \9 p: {5 ?# o/ b* y) o
/* Enable synchronization of RX and TX sections */ * J# S9 S3 R M* W) Z, s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 w- G- P( y) ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 ]) E5 s* w; {/ E5 ~9 R% }) ~9 l; N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 T8 j% d1 {( [1 ^
** Set the serializers, Currently only one serializer is set as6 r# B7 ?& I; r& [9 u. ]' H3 v3 x
** transmitter and one serializer as receiver.6 }. i; i, ]" n/ s5 g
*/0 @& s7 N9 s" M' X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' o' r2 ~% ~$ A* o+ _5 b3 k9 g; HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ A+ K9 N( G8 u6 w) a8 X+ H3 B
** Configure the McASP pins
1 `0 s( c6 O3 M& K** Input - Frame Sync, Clock and Serializer Rx
7 X* R1 h& U* H% B( `$ y% o** Output - Serializer Tx is connected to the input of the codec
, O2 }5 v/ o$ P9 T*/
& v2 }9 T& a0 b! TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" y6 d3 j' _! @! rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* ]% w# L( o* O8 e6 q) [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 E7 z, m/ f% r. F
| MCASP_PIN_ACLKX
- [, P& v- _4 H7 [, Q| MCASP_PIN_AHCLKX9 d2 _ j0 ^( l7 \* D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 U3 y7 Q2 L% P! W+ Y3 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; Y- h: E, S- {/ F) O! q| MCASP_TX_CLKFAIL
) w" N9 V$ t( n5 G| MCASP_TX_SYNCERROR9 G3 @! M$ C* o- h, \ C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ A- e7 M$ S' c$ \" O: T3 o2 x| MCASP_RX_CLKFAIL
4 N, F2 o8 f% D, M| MCASP_RX_SYNCERROR , f, s3 n& |, F& J6 t
| MCASP_RX_OVERRUN);
5 d3 n9 f, h2 C, J} static void I2SDataTxRxActivate(void). s Z( I2 n- b
{2 i" e5 @4 q( J# a5 C
/* Start the clocks */ U4 J r( `" ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ {/ U0 y! T) o" t4 J/ r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% d3 W4 q: j S0 S1 Y4 c4 T5 g$ K9 e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. u+ j( U. e, S, y) H3 ^
EDMA3_TRIG_MODE_EVENT);* S3 ` w. r3 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : M d W) @) k% k6 g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& Z$ x+ G6 h- X" Q% K! o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. g2 T, n4 v( l' P; s& o4 o6 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 F/ h2 O+ f3 I, v8 O4 T _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 P4 H. A3 o+ c+ `" z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 J- g, @% T( r3 }% L7 d+ m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 ?7 h% `! Z6 M/ W} 4 k, ~+ M1 o4 ^. \- J. G8 l& }+ s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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