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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 Q, p6 V: V" n3 X- L! R
input mcasp_ahclkx,
3 P& e& p# C; F$ @input mcasp_aclkx,
$ {: p+ w' k. A7 J, A! Q1 Ninput axr0,
3 \* w: y8 i2 w/ V2 G5 w& ? a
, P& }) `9 ]2 ]) Doutput mcasp_afsr,
$ E5 B! T& n, M( Q/ M- u2 D& h2 youtput mcasp_ahclkr,
+ A1 L0 S- L J/ h1 joutput mcasp_aclkr,
2 p! ~. ~- I& G. aoutput axr1,
( w' a. V: z' [7 N2 l6 D assign mcasp_afsr = mcasp_afsx;& X2 F- \ O C4 a& C
assign mcasp_aclkr = mcasp_aclkx;# v' J) j. r$ y% I
assign mcasp_ahclkr = mcasp_ahclkx;
* I7 ]: `2 D& gassign axr1 = axr0;
' L; {/ |1 _% s2 V" V+ \( @
7 p% P) U6 t" g) O1 d( n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 G7 w. j! q% p9 _# estatic void McASPI2SConfigure(void)
% Z7 u" D! a! s{
/ b: L, q$ G: A: E& \7 N1 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 h; F' H4 w$ B% i' \ wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% i! Q# F# a) N- c# _1 a" dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 p+ o J# ]: \( q& WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. i" E& a6 W0 x+ BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 U/ n0 J/ M+ k1 |
MCASP_RX_MODE_DMA);& ]' c: U' [. Z( C3 ^) \( d1 q U* D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 [! W, o5 J; e/ ?# t% \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 c U6 r3 P. }' x; {4 F% y$ K) z2 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 W( t& T8 o5 H! `* Y, [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 V0 |6 U: c/ T& k Y8 k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& ?- S" \% m; l8 XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; Z+ F, T; ~3 p: u' Z5 V" ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: P+ m; |0 o* N, Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * I( F: M n) f! C# t- H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" ?6 f, R# t/ P9 v0x00, 0xFF); /* configure the clock for transmitter */
( L6 T3 ]- Y3 N: K EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. R1 ^+ `* a9 ^; ]9 n3 i2 DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 Q8 d7 T& \8 V4 G. V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! C: C0 W: W' |7 L
0x00, 0xFF);
1 e& p7 e2 A/ q R) N: c
) n. p1 P3 |# A' G- @* P/* Enable synchronization of RX and TX sections */
* v" G4 b/ M1 U! o5 j( L5 zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& }! ], _- ~* O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! y1 `( G Q& h9 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# ?8 F5 r! N+ h1 D7 O$ t- W
** Set the serializers, Currently only one serializer is set as
, t- @; k& {( c! s0 {/ V L** transmitter and one serializer as receiver.6 v9 X5 d. F& c/ m1 Z( y
*/2 E% [" o/ M e5 g/ l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. K" Q0 ~3 j. i T) g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 U9 m$ i4 m) n/ k** Configure the McASP pins / I) w0 K1 N. I% J
** Input - Frame Sync, Clock and Serializer Rx! e' g9 M; ~. D0 H% B3 u2 \# _
** Output - Serializer Tx is connected to the input of the codec ' H$ ^5 X# b) F0 P. l4 W% h8 Z
*/
/ y1 z& o" Q" N1 M% _/ u! pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 q* s$ ^- V" a: [2 `! _+ s# AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" Z) `/ x4 C' d% EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ T) G) q, B; i1 F, }
| MCASP_PIN_ACLKX& V: O# f) X8 ?
| MCASP_PIN_AHCLKX7 O3 e1 z! p1 R8 h1 t4 o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 I& z5 x: X8 i) r# J, o, @* pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 _1 _6 x8 x2 S, f/ F4 ^. h3 i' W| MCASP_TX_CLKFAIL
9 u/ v D4 w) f4 O7 E- F| MCASP_TX_SYNCERROR, |, }6 F6 H* r, i% B+ `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 K/ A8 [9 ^5 {% E
| MCASP_RX_CLKFAIL3 ^' K/ S0 ]. Y- r
| MCASP_RX_SYNCERROR
/ `+ p5 H8 J1 e. [| MCASP_RX_OVERRUN);
* S) m6 x+ m. i7 d- ^7 u} static void I2SDataTxRxActivate(void)
6 r1 d) B* l( G5 N{ ]. g) n( _, u9 U: N
/* Start the clocks */1 H0 q; W0 W5 r I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 [+ E/ }& o3 O7 V$ @, A/ M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; V- N$ d& M+ a$ f, R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 ?/ t, K- n7 Z4 d _- g2 k, q
EDMA3_TRIG_MODE_EVENT);
5 A3 {, w' {; q( {) n4 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ d/ q; E9 C& p2 S4 C9 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 |/ ]: L4 U0 X2 Q; R7 @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 X4 }- p% i1 C5 F+ i+ x* ^* |7 o E( d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 N! C1 C( C) s1 ^: B8 v- pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 A+ H! X3 M0 Q; yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ _0 s1 z& c4 d3 d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" C% P! u$ u9 H8 R6 t} j' a$ b3 W" ]% k9 M# V$ M* h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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