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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 Q, v7 p: B0 X# V0 Q5 }; c
input mcasp_ahclkx,3 S' I: A; A* a% B3 Q f
input mcasp_aclkx,$ v8 Z$ V3 y' ^! D8 m r
input axr0,
9 e) A& M5 t; W- U" f/ G6 j0 J \# _6 k. H5 ]" @$ r' j5 ]
output mcasp_afsr,% I4 l( ]6 ]2 D1 }+ x
output mcasp_ahclkr,
& }! u& A; E$ ^# ~; w* t# l/ Youtput mcasp_aclkr,3 y; X# n2 j: n# D# w
output axr1,9 b, S) O: p9 M3 L- y' v4 d
assign mcasp_afsr = mcasp_afsx;$ @) O/ m& w3 z
assign mcasp_aclkr = mcasp_aclkx;* E) E3 p, a$ a7 v6 _1 B
assign mcasp_ahclkr = mcasp_ahclkx;% F+ G; W' Q& U% h! ~
assign axr1 = axr0; : \4 x: ~& M3 q1 O b
( J( Q ]! P$ F' q$ {4 T& Y) ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; x/ R1 g: u: U% C" L3 u0 Wstatic void McASPI2SConfigure(void)
+ d1 ~/ T$ ]8 s( ~{
7 V) [- d0 h0 O1 u9 e! ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; G- q& K7 }+ ]5 c6 O+ c" rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# m" S7 x. K3 I. F: x7 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. d+ c, r! @0 L/ d7 }2 X$ |# L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; _5 F" b0 N; I; @( y y! cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 j7 a1 w6 P% V% S0 T. q4 z$ bMCASP_RX_MODE_DMA);; z& M$ m/ o# G6 m% ~# O/ ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! ]. C: Y# W0 z$ b" a5 f6 Q0 ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: K, b' t9 z) y% J# Z, ]; N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 |$ k; m& z7 M9 D Y% HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# P M6 K* t, ^- S0 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 |, j# ~" }' [8 f- W2 w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) x- z7 {' E* `" D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 y( z$ E. y& k |% TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / m8 f* Z; U+ T3 a5 V" T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. Y, e ?& {9 j
0x00, 0xFF); /* configure the clock for transmitter */8 P9 i8 ?2 g3 A3 k$ Q2 q3 Q" T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ x+ Q K% A7 ?% v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& Q5 w% }7 F8 r3 c* Y5 Y: xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' B* _3 i+ Z) ^3 _7 h
0x00, 0xFF);" n7 g8 K" `" I( n" a. `# K
4 E& ^8 q2 i! |- C
/* Enable synchronization of RX and TX sections */ , \. _. i B% r) d2 B$ L3 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 ]8 c' z& [7 H8 d, v! DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 V+ M7 b8 l- u9 M! E2 l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; z5 R6 v2 j% w8 T8 u! H: c/ J/ [** Set the serializers, Currently only one serializer is set as
, P& i$ {" l! L- G** transmitter and one serializer as receiver.
: ^4 U1 c2 b( r$ o n*/
. p' k- ^1 h3 AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& N3 ^0 ?9 e; h) XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( Y, {2 p `& \7 \3 |** Configure the McASP pins ' G3 O# h2 w4 P; D6 e
** Input - Frame Sync, Clock and Serializer Rx
9 }& z# w2 D0 f; X** Output - Serializer Tx is connected to the input of the codec & W+ {5 U* `" `
*/
% T- u% E; I$ Q. EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, y; b g" P# A) S+ i& i2 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# t$ x1 I8 y' l# G3 m1 h& b* O. P, m/ uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 u& D2 e- ~! w" i( \1 _2 K
| MCASP_PIN_ACLKX: Q" F+ {0 _7 d. z! R j2 x
| MCASP_PIN_AHCLKX
9 m: O2 f# Q5 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ R6 b7 u- T& C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " @! b) |2 ?% `
| MCASP_TX_CLKFAIL / Y+ z9 V2 }. y$ R% N
| MCASP_TX_SYNCERROR
- N% k" p0 p9 w1 S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : A/ d7 i$ H- N0 j; _; `; G9 _
| MCASP_RX_CLKFAIL
# l8 i; I/ W% X| MCASP_RX_SYNCERROR 1 p( o# B6 |3 A! z( u, S2 g
| MCASP_RX_OVERRUN);3 ]" W7 t6 J( k- w- B+ Y4 n
} static void I2SDataTxRxActivate(void)) C4 u/ E" ?, ~$ h, d d& Z
{
5 v$ s. C% ]$ G# F/* Start the clocks */
, x5 l" G C* j; p% A7 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) r- B A% w+ nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 L" @' x' ~% w- c- `1 t; ?8 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- C3 \! q6 n6 U! _& A9 C& j
EDMA3_TRIG_MODE_EVENT);
# e6 W- }0 Z, Y8 T9 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ c1 h! |6 o( h3 |- b$ R9 ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; ]/ k, | @5 n6 E; w) \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. ?! c' M* m/ \! }/ V2 iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 H2 U& m5 @9 y$ a J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* s+ V. k6 O1 |8 S5 t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 H0 _& _; ^$ Z/ m: C( S1 ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( f1 _: N' L* [! G: v( H. y, S6 F
} # P9 n- P* Q+ d \5 C# `6 B& L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + N2 @ w# q' ]% r
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