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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. ^0 [( V. a, |- M- k
input mcasp_ahclkx,2 `+ b5 s+ {/ d: `
input mcasp_aclkx,4 Z) W, ~+ h! x( \0 P7 v
input axr0,! C- R( x+ Y- ?9 |
# x$ `1 t4 w7 q& C
output mcasp_afsr,6 v4 T7 \" Q% i! E
output mcasp_ahclkr,
+ T4 y& C3 m7 [output mcasp_aclkr,
. ?8 m' X( n& _: J* M. \6 T1 b: S! u9 x7 A& Youtput axr1,, k2 ~* Q, W! R
assign mcasp_afsr = mcasp_afsx;' c# R) C. Y5 R) _. v- q
assign mcasp_aclkr = mcasp_aclkx;
7 ~6 s$ j1 W# Y% ]0 gassign mcasp_ahclkr = mcasp_ahclkx;
1 a: Q* j' G @+ iassign axr1 = axr0; ; J3 F$ ^% V I, r
+ e+ |$ p, Q$ {5 h( k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" T+ x0 K; O4 _! y* |: E" s0 Cstatic void McASPI2SConfigure(void)
. X9 n9 k7 c4 Z- ^7 u: C- l5 i+ V' {{5 @9 N9 E& h! c" E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 q- E" t6 W. x, ]9 i) n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ r' `, k/ n# ?% sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 z3 G/ F( _, K" M6 | yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! L3 s1 r7 z8 h( `+ S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% z8 i* ^$ u9 U6 X( Z6 i W1 BMCASP_RX_MODE_DMA);; Y" V C$ U+ Z3 C/ Y7 G- V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. d$ m; m/ \: D- h' f9 L; F$ s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& X7 f! j, E. d2 F; A; R7 `% O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / d. B/ h( z% d$ @0 a; Z9 b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 d% P& m* g5 p4 M2 l! t+ ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 e1 W8 V- S" c: c# L, T) A* O9 G' X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# P% u6 Z7 q5 N0 {% {5 O' B3 \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 |7 y+ v: q: U! c( SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 u5 _# i! `: qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 Q' r7 ?, X/ k& _
0x00, 0xFF); /* configure the clock for transmitter */7 R: A$ d6 @, e. E2 d' Y8 D/ ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' q% e q* s; P- RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; }) K" S6 ]/ E% b2 ?$ ]+ J4 b7 @$ a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) V, g; W* ^1 Y% i- e0 P* ~
0x00, 0xFF);1 R4 Z( N$ x5 r$ C$ x1 K% N- m
1 O- l' R& w: L' ]
/* Enable synchronization of RX and TX sections */
6 _. O' Z+ }7 z. ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ M" g/ k/ S& {2 {1 T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- U/ ?9 o5 ]( l9 t* s* a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 E/ r7 [# U9 w4 A& A
** Set the serializers, Currently only one serializer is set as- O( f% k3 [$ L6 y3 b
** transmitter and one serializer as receiver.
6 ?+ I6 g' Q. o) }*/3 ]8 H# w) d( l% o" i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ W5 ~, W# c" {+ f* |0 H& F! ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 ?5 }1 V3 O3 H7 Y
** Configure the McASP pins & n' M$ J* M0 ~' n/ s+ h
** Input - Frame Sync, Clock and Serializer Rx, t! v# _% `, [3 B$ ^. x
** Output - Serializer Tx is connected to the input of the codec
! i! m. [: Z9 z5 E*/
$ [9 @0 M( ]+ y7 q |2 J5 BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: v, X& h4 R! i* z) hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ Y1 y2 e* B# X9 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 i8 j) H' O5 c! |- V: O1 J| MCASP_PIN_ACLKX
& H+ w* G8 M) V. c| MCASP_PIN_AHCLKX
. p+ A, N9 {5 [6 O7 {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; D# D/ n9 S. Q8 f @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* w4 `0 p% M9 K9 v6 D| MCASP_TX_CLKFAIL
% [; H6 I" Y' t4 p0 G7 m$ h| MCASP_TX_SYNCERROR/ [/ C. N1 z6 R; y/ y" P% T, q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ [0 |0 i1 [4 L8 o0 \! z s| MCASP_RX_CLKFAIL
9 I3 n. D: @) I+ ^% D+ {! A, ]. N3 q| MCASP_RX_SYNCERROR & L4 N1 y# X# {0 J- G
| MCASP_RX_OVERRUN);
# y: z" a1 c% A# v} static void I2SDataTxRxActivate(void)
* w* ~3 o% g* b5 C: u{
, q, x r% ^5 I0 _2 v/* Start the clocks */2 A |/ {& ~# o t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& d* H" H x) T' H! S* T D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 r' z1 v1 A% L/ W' r9 U+ }1 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- u6 w j! E9 e4 s
EDMA3_TRIG_MODE_EVENT);
- E+ v4 T" m$ REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : n3 ]* V3 S2 X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# t. F( k, {; M9 ^+ K/ TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 w, A- k+ ]- m, Q5 p, c& J8 B @! @8 nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) G$ b$ N' Q7 F8 n1 k+ f* Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 ~) L5 O4 l7 g/ z" z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 Y3 Y/ A$ V* r# v9 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: e; s, O- a# ] @- S
} * z$ ^8 N- K0 q; i* o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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