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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 G& `* H$ h+ w7 T5 x! y4 [: ^
input mcasp_ahclkx,( F6 u6 V1 L4 p$ p: O! @% H( _# n
input mcasp_aclkx,
0 o3 r# w2 o9 p# ginput axr0,) p) L9 ~: V; w& B: j( B7 d L# B
+ S7 e0 O* z Uoutput mcasp_afsr,) Q0 N+ e8 z% V$ ^. N' b1 _5 o. j
output mcasp_ahclkr,
! ]( `6 Q, S, Y" voutput mcasp_aclkr,
/ _7 U: n5 y5 w; m, koutput axr1,* H4 t$ w7 v. i+ z
assign mcasp_afsr = mcasp_afsx;
Y1 b3 b0 D& Z( w/ x" Q7 C' h% `assign mcasp_aclkr = mcasp_aclkx;- h0 ]& `" g& T( Z% [* z9 x
assign mcasp_ahclkr = mcasp_ahclkx;2 H& K7 R* H5 [; k4 ]' U* c
assign axr1 = axr0;
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: f) b# u H8 O! f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * t d& _$ _1 l$ ]! \/ ^% W
static void McASPI2SConfigure(void)/ D t# E0 J! B8 R, d3 `/ R9 {1 m3 }
{) p- @ l# r8 x/ w
McASPRxReset(SOC_MCASP_0_CTRL_REGS); |$ S _( E) P( t! d! `3 [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" n5 O, ]5 u+ `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; X% _4 e9 q( D7 g& I& a; [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) f: i7 y5 N% w# ^: UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 R5 ]* D0 {7 t
MCASP_RX_MODE_DMA);: k& P$ g& K4 I; S3 K: j! k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 d' p4 P A; k$ Z6 s* O: eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 @3 U6 }# j+ r8 P' S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( X3 h, [/ { ^! u" o! ?0 gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 \: L2 H' C" K3 L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 r |1 i" y h1 W" C7 OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 u' J+ S% _% n' e' sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 T. M& `+ @& ]8 }4 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 Y4 O/ G2 M( x+ S yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 p% C2 N0 U& A, _ n/ g* z
0x00, 0xFF); /* configure the clock for transmitter */
4 f$ [* T6 _" M. j! n) PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ y, e7 K2 U. w8 H. r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 f+ F7 \( X: a. o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# ?* k9 g9 a; X8 I! k# Q
0x00, 0xFF);
7 `+ c, W, s. |# Q
( X! S( s9 S) c- v1 `' I* L/ i0 X O/* Enable synchronization of RX and TX sections */ : H- b9 u8 A" I* E' p- j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 c V, B) J$ F% a1 b2 KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# D5 b0 n" K5 ~% A) k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 j# P% x4 r5 z; }1 K
** Set the serializers, Currently only one serializer is set as
' ^) a1 X, G) a1 u! i6 t! }" y** transmitter and one serializer as receiver.
6 j1 i! U" Q- j0 ]% r*/4 z6 W( V8 c9 i# [( L8 Q, H* P6 e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* T0 g6 v! z9 Q, u7 ]- aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 M! @# W7 {9 Y' W: K( }** Configure the McASP pins
/ l' M$ l7 y1 W! K6 A** Input - Frame Sync, Clock and Serializer Rx1 R/ ~7 g$ N* |" `9 z( D
** Output - Serializer Tx is connected to the input of the codec
" l- D- h8 `9 X*// g* g/ \; @: D5 V; J# ^3 O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. Q7 _/ {: R' e1 x2 w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 ^5 H% m! W9 H0 e' [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( R" g9 ^) a: V9 v
| MCASP_PIN_ACLKX0 b3 A' X, L4 s3 Z2 y- s; n# i
| MCASP_PIN_AHCLKX
( r" p/ x' T1 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' S3 }7 r! q( X; B/ Y( g0 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ T8 D) ]% O4 S- D| MCASP_TX_CLKFAIL
, K- |3 k, m# R9 Q* d| MCASP_TX_SYNCERROR
0 j# p* j/ u; C* \0 H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % R$ B8 }; n- Z; ]: M- b9 P; G
| MCASP_RX_CLKFAIL
0 g9 v9 {3 P: T. c) s! T- j- x$ {/ B| MCASP_RX_SYNCERROR " K& C- A# O* p
| MCASP_RX_OVERRUN); N" ?) Q3 _/ o4 z
} static void I2SDataTxRxActivate(void)+ l( g0 m, d7 H, J( w- ?' J
{+ s3 {5 ]- R! C9 _$ |
/* Start the clocks */) I5 Y% s" Z3 ]2 ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 I. s/ M: i* w6 D1 M- V3 L7 F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 o1 o1 p9 w$ L* u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 f* V$ S) ?9 D
EDMA3_TRIG_MODE_EVENT);, S* |7 F# i$ K4 E D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + [+ [8 Z* O5 k. s$ |+ H% I3 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ _% C* n/ ` `8 [6 h& [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* a( K2 Q% e; N. vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( z/ |- C0 ?+ ?8 | B$ }' [3 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// _. J. {! o8 G6 `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ J ?9 _0 q, o! N0 ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: s }, G/ V4 c) O% h}
F3 Z3 S0 g7 i) B5 B0 R5 O; c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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