|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 ~* X$ |1 c5 p% A; O$ x
input mcasp_ahclkx,
4 [+ N4 K- Y. E; B7 Cinput mcasp_aclkx,
+ m8 V' C( s& E; `" f7 Xinput axr0," k' X. J( D9 I7 z: f6 Q
7 }1 y$ L- i; I# s4 ]! {$ x5 f
output mcasp_afsr,
7 \- t$ ]+ W& x. Uoutput mcasp_ahclkr,( I* W2 @% C" T- S
output mcasp_aclkr,) A. L0 M2 m2 M+ a1 p3 Y' x
output axr1,. d+ |& `" ]+ a: ^
assign mcasp_afsr = mcasp_afsx;% e8 B) K4 G _) o$ a" O7 X; M
assign mcasp_aclkr = mcasp_aclkx;. o1 J. z- _& l- K# T
assign mcasp_ahclkr = mcasp_ahclkx;9 I9 @( H; \& W$ S, {! y
assign axr1 = axr0; ; y- |0 H0 |9 }$ p$ x) u& A
( |; f$ |0 p- y( x, s. C2 d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . w' X$ \2 W/ ~" z5 [
static void McASPI2SConfigure(void)( r0 F- t1 Y, ~$ ~& u
{
; M& P7 [6 c# ^4 b VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" `' U5 H' u7 k5 V5 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) q4 R, h2 j7 U/ X/ B/ XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 L l( n. a) x; G) RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# \" j' ]2 z! B. u! m* g& _( wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 @* `) c9 M6 IMCASP_RX_MODE_DMA);
- N4 |0 e- { {( oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 J' b3 N( w2 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% j2 M' P3 q2 ` z% h3 ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 q- [$ g$ u: q- `+ r, f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 t' e% {) m" ]: w. v Z8 jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, N3 z6 K$ C5 v. m- J* i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 U5 A# I/ F _ a4 } G$ T# N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 e& Y9 F& O* ^+ P4 n/ SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & }" |% y/ \8 a, x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 f' K8 h+ K! u9 q0x00, 0xFF); /* configure the clock for transmitter */
8 p+ u$ ~7 W9 r9 w2 a/ t& B7 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( Y4 r, g1 _3 L j) e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , h! ^/ U" M1 l2 D6 v3 f C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 ?+ F7 k& A- e+ c+ z0x00, 0xFF);
9 g4 z' k( i( z1 S4 D/ `6 t# i7 X9 r& a7 ]- }
/* Enable synchronization of RX and TX sections */ ; d: J9 P* A; W/ |, U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 o1 y# h) w* X7 x" gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- A! K8 ^7 L2 h0 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, a! |+ D# y1 x( x0 c$ g% U8 c+ y" x** Set the serializers, Currently only one serializer is set as5 N$ ]" Y$ G2 } c& Z
** transmitter and one serializer as receiver.
0 y3 D. b7 U& _8 @# d*/
0 d3 q6 k, S; }+ a5 J: u! NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& a' K/ N" p$ s# q) R# `( z7 G/ V1 c# WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ ^# G* T- h8 n4 A! r1 J** Configure the McASP pins
4 T6 Z. N. A) B, y: {" D! n* h1 K** Input - Frame Sync, Clock and Serializer Rx
- S6 d/ ?0 j5 _1 @** Output - Serializer Tx is connected to the input of the codec
! [9 i8 [+ L0 p, h7 V*/
6 J$ z5 r) v% [. l8 NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. e# @# c. Y, T& }! a: l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* X+ q% o @' G# ~" k8 x- F6 u+ d/ OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 Y9 u2 ^1 `5 |3 O/ i: R
| MCASP_PIN_ACLKX
; e4 l1 I! @ c0 Z! P* s- m| MCASP_PIN_AHCLKX
; T6 |, B9 H' \0 G" R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! u$ d6 `4 P2 B2 g4 I3 kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) Q* w" k1 B% O/ y. J# s0 x| MCASP_TX_CLKFAIL . o$ y/ b9 M$ j- g4 s9 g7 d. `* ?7 @
| MCASP_TX_SYNCERROR
' R' ]- H8 p/ N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) x& w- P: _! p( Y| MCASP_RX_CLKFAIL
1 o7 V6 W/ v' @: P8 f: \, S. w| MCASP_RX_SYNCERROR
3 l: Y/ I# m! l4 F7 m. E| MCASP_RX_OVERRUN);3 H1 A) o6 M; p: I/ N" {; [
} static void I2SDataTxRxActivate(void)8 p0 [- X9 X, y6 B9 r8 B3 R
{4 f1 Z: Q/ h' T
/* Start the clocks */1 ~0 N- ]' y. W; Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& k7 P9 I% W8 z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 ~) U' |( n z- u: Q) m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, J/ v$ X+ [& ^) s) s' h) D4 O3 |' y
EDMA3_TRIG_MODE_EVENT);$ H5 Z% E' k- B0 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& y$ E& h1 B# f# r& t: O" @! _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# |4 M, G* J5 |: E0 f+ bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 B; p7 B' C2 H" D$ e: \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; P- r' F, w! T; twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, ?$ ?1 x5 ^1 n% C. T6 @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" T' j+ t7 @$ Y' K' O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* t7 I+ S$ w n, y}
& C* `/ Z/ t( G- ^/ t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
% b( Q2 L8 u f) N1 l& V& \ |