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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 v: j5 F3 d5 i! Q) _- J
input mcasp_ahclkx,
& [4 D# p; K3 binput mcasp_aclkx,0 S4 j6 g$ o: G0 A& o0 [$ e
input axr0,' v) ^6 [9 P# y N" w6 V/ v- Q
8 b- l# ~$ Y0 a$ l, ~. H. foutput mcasp_afsr,( T3 {- m5 I4 T) X5 v
output mcasp_ahclkr,) _' I& n, t# b+ L
output mcasp_aclkr,
0 G0 w. x) y7 `output axr1,
; i5 D3 J5 G9 w' f assign mcasp_afsr = mcasp_afsx;
& B1 `4 C5 G* zassign mcasp_aclkr = mcasp_aclkx;
: G' ^+ u; Q6 A: ^- [ D$ gassign mcasp_ahclkr = mcasp_ahclkx;
/ Q& X6 Y$ F' |4 h, c! aassign axr1 = axr0; 1 n' |6 ~% q" {( G9 F. r5 b
2 F8 q: L& Y8 R4 N6 Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 b; P' h% P- [( L. Z* }7 qstatic void McASPI2SConfigure(void)* B" Y0 t5 o: h) ?
{
7 O: L% _1 y0 @% ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 d2 i) `$ f C% V" R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, d [& F3 l* {; }% {6 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 c) x7 d& Q3 a5 k+ Y2 SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& u$ s. O7 |: F$ X- @6 |' kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ V" U) r2 R: B: x/ p
MCASP_RX_MODE_DMA);
k6 V. }1 U. H" zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ o+ e% S: P( V- _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* e& u; `! A M0 W; E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / N3 f! h3 t. N8 I( k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 U% V/ [; ^* d- B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 I* c: w2 e* c5 `8 n1 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. x2 P: R+ j. B5 T) DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ z/ U0 p7 S! E5 }! g. ` uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 N0 ?- U' L6 T5 V7 i+ b1 S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 I6 I$ u" k) t+ u0 B0x00, 0xFF); /* configure the clock for transmitter */0 K: l& a, @9 p* R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 p8 y/ V+ y/ X0 u* UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' n8 ]5 i8 Z* m9 v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ Q" @( X0 C2 }( M$ @0x00, 0xFF);/ k; n" y1 R) U/ ?# Z% u1 w
3 k$ f" b$ h J6 U0 _. F: t' N! Y6 y
/* Enable synchronization of RX and TX sections */
% E1 P4 s( W+ eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 A) E$ g( ^- g8 U: Q+ X+ E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- m6 g9 e( x1 d/ ?4 s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; [" P- ?6 j9 k3 s+ y4 o** Set the serializers, Currently only one serializer is set as
/ @# T: M1 M4 z** transmitter and one serializer as receiver.. N; U Q1 p, e# J' ~' S; e
*/
( f: T/ B/ d, r4 O( b4 fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 M7 z$ O$ p& d0 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( X6 F; m0 {) [+ L0 r N) I# y** Configure the McASP pins 4 r* N, X$ G$ S1 v% |2 D) y, }3 e6 {1 B- u
** Input - Frame Sync, Clock and Serializer Rx9 ^, o' ]# t1 q+ o
** Output - Serializer Tx is connected to the input of the codec
& g! X. s7 Y3 t# K) Z6 E2 W J( L*/( {3 h9 }$ F5 t( ]) h" H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! O0 F# P/ w- n0 M9 VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 P: U& P! r. U7 C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& A# B( E2 V1 E' u3 ]
| MCASP_PIN_ACLKX
3 x1 h' |8 d }+ P" J| MCASP_PIN_AHCLKX) z, a, I E' g# G O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; P& B6 | w+ [4 M$ l! e, Q/ R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 S% j* h/ I: m, R I| MCASP_TX_CLKFAIL
& X" S0 }5 n' ~: W+ u& G| MCASP_TX_SYNCERROR
7 a) U( l1 R# Z' X9 b P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 b; ~5 y; y/ t* L3 _| MCASP_RX_CLKFAIL$ B0 J* h0 ~: W
| MCASP_RX_SYNCERROR 6 K% L7 _* H' ]7 k
| MCASP_RX_OVERRUN);& q* f: h- ~/ f+ e- u; q1 |
} static void I2SDataTxRxActivate(void)
3 K# s+ J- x- k% S1 A5 E* z6 q{
( ]1 H, S: F, C4 W! I/* Start the clocks */
& p' [1 a( W1 k. Z8 a4 y! X1 n9 F' sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( H; L9 O% n% n3 B2 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 [& k! M$ @* J! d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 m. H! A# I) v% [EDMA3_TRIG_MODE_EVENT);' i* t9 u$ f; C% }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 H( o% `1 I; l8 ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
a9 Z3 W1 D0 G5 N2 }* l6 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 H3 h \4 G# W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* r: Y# J8 I5 r4 D& k3 q5 gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. R& b7 X/ ?+ o3 `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) B1 O( i; h& P( X" gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 K! o- n6 n' S. p; J& @. E} $ ^* q4 r" ^# X, k" G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % r2 P: a1 M9 U7 A
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