|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," l5 Z- V$ w4 H6 w- X6 ^
input mcasp_ahclkx,9 g1 l' k4 g/ D/ \
input mcasp_aclkx,& {5 I0 D; L5 @) |, G3 G" n
input axr0,
& x7 n- c0 J$ X G: |4 X
; W. s) F/ H" G$ _% M4 noutput mcasp_afsr,
o; X0 e0 M {3 o, f9 woutput mcasp_ahclkr,& |7 G3 w' W0 a! n: ]6 t" ]7 N
output mcasp_aclkr,
( R# u, w/ A( loutput axr1,
1 h9 X, ^4 l1 ]! K assign mcasp_afsr = mcasp_afsx;
1 p# s# n& I. a9 c3 Dassign mcasp_aclkr = mcasp_aclkx;
. Q( g1 o6 c# }8 w) w. Q/ t. {assign mcasp_ahclkr = mcasp_ahclkx;
+ i9 f( A3 c4 J( ^) qassign axr1 = axr0; 3 L) T% h8 w5 F
, z: g, ?" j. k, s; b# H9 l' _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ q0 m& i, j' r4 ^2 h4 b) D W
static void McASPI2SConfigure(void)
: p& J( L: d2 n! {) w- v{
' w# F% C: F, `' g( H7 {McASPRxReset(SOC_MCASP_0_CTRL_REGS);. M( U9 A; I1 z! ]; _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; H& g, e) z3 w* z, B, H0 OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 ^! Y/ B o- P4 o' O; y! V, c% xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 z3 x u' Q9 T0 ~, l5 S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. D& m9 P: Q, Q W
MCASP_RX_MODE_DMA);- ^1 x( |, u/ e, U8 {9 l0 P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, |7 z2 k2 j0 W2 g5 W9 K6 ]! ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' k$ o' ^( g/ J/ u! v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( c: u# W+ k$ A. \1 vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' K( ]/ v' I. r2 a9 t& D* ~ n8 b: F( q: |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 Z5 d/ X8 D( t& P6 [* {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 p- a2 T8 u- a! {% u8 d/ c6 i8 z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; R7 U8 V2 G% ~. b) n! U4 m- p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # }* q; c- k$ f7 |; q/ K. F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, a) ]7 m$ L+ `/ k0x00, 0xFF); /* configure the clock for transmitter */1 c) E2 [7 N) b8 l, l0 H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ k2 O2 w( \4 @. h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
Q( Z2 A, }4 v8 e6 W+ d" W/ OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 Q' B) Z& C5 _. n2 R8 s9 w; K& |: q0x00, 0xFF);/ h7 q2 a9 H$ \2 G, K5 n
$ B$ n7 y6 F/ G* V, e6 M) y1 `/* Enable synchronization of RX and TX sections */
! A9 a( z. x) ]1 W3 u- D) g4 K! a6 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 _9 i, c Q/ D6 K; ^; z8 u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 o# w+ R& i# S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 s% u* H! Y+ Q** Set the serializers, Currently only one serializer is set as# b1 Q) G- a! F6 W; Z- q5 S
** transmitter and one serializer as receiver.3 Z( o* u) K8 z1 X) |4 e
*/
. j% J: p7 ~9 d- n9 k; }- p) oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! w% Z0 a! P* o' s0 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! }3 L5 g- I3 i3 Z** Configure the McASP pins
1 [' x+ Q& ]) z- K; l9 o** Input - Frame Sync, Clock and Serializer Rx
7 Q r0 ~$ K" @, a) A. n** Output - Serializer Tx is connected to the input of the codec
: O+ B0 q W& c) V2 ]7 Y* k: S*/
$ I7 u1 X$ e; Z- K; GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ k8 H. H$ e2 A7 N& M5 b, A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) J# A- b5 n' Q1 D. JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* q! g- o( n# M; x) E
| MCASP_PIN_ACLKX/ e) E5 A2 y# ~: |) W
| MCASP_PIN_AHCLKX) [6 ^! ]& x+ z1 ]! F0 P( `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ N% c- z: [* J% ~) z$ MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* V, e2 i* _1 h$ E# K- U V| MCASP_TX_CLKFAIL % V. y ^( R$ q
| MCASP_TX_SYNCERROR
0 r7 D% s; W; P: H8 n# x4 X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: K1 L6 V2 M, ^: q: N- o8 q, I| MCASP_RX_CLKFAIL" ?- {. A0 P1 ]5 p
| MCASP_RX_SYNCERROR 2 U! X0 g+ N9 q7 F% T& {
| MCASP_RX_OVERRUN);
2 y0 q; f7 s; x+ i0 ?; K3 D$ k4 z} static void I2SDataTxRxActivate(void)
, u4 ?, T$ A, s) e) {( H{. u. @) {, C4 w4 `
/* Start the clocks */& a: d; c. P$ ?$ f! _1 U, c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* E9 m$ O! }( u9 I; p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* {% y" t. G: b9 A' ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ j1 c" j; V7 {2 SEDMA3_TRIG_MODE_EVENT);
1 p/ k- f- |$ b, wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + x5 u& z3 z9 K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 w( C7 M6 P3 A8 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ W$ x; i, p: ?3 i$ Z; EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- ~8 B) J, N$ w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 }& r; \: @2 ^: R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 N6 r* W' s. g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 a! p3 W7 l9 [5 D- }
}
3 A; G3 W& x3 i8 k5 S& L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; N' H6 S1 K' n+ ` |