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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 C8 c8 J2 a' \/ xinput mcasp_ahclkx,/ d# }3 P( h3 h( `6 v
input mcasp_aclkx,
: `4 F/ \4 [! s( A, u" Finput axr0,, s/ @+ D: ]" c I& F! g6 H
: z& e# P% w6 y* X8 E$ Loutput mcasp_afsr,) _) Z2 {! A) h4 @
output mcasp_ahclkr,
- _9 V; }$ M4 Xoutput mcasp_aclkr,3 h% o, {& D+ ?
output axr1,
9 ^, k' Y3 u4 k3 r3 U/ R8 [ assign mcasp_afsr = mcasp_afsx;$ c* q! u" }+ ^3 g/ C; t7 F
assign mcasp_aclkr = mcasp_aclkx;
, l, }9 z: t& n* W) r& N% S4 r! Aassign mcasp_ahclkr = mcasp_ahclkx;
. P `" _0 d1 eassign axr1 = axr0;
7 N! H, u& U7 N! T% A6 I) r3 W; D9 b6 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & ?! h# e' H: v5 g+ z; h7 @2 X
static void McASPI2SConfigure(void)( T9 A) V" E7 ^/ M0 H
{4 z; y# X# L7 s- y( O; D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. w: v, C9 i. C8 S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 N" j( B4 B6 s$ x3 Y$ FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 Q/ S# _$ w4 p. ~9 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& k* u* L: A$ o, @: iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 w$ M( e: ?( | D$ q
MCASP_RX_MODE_DMA);
& Q! v' ^% F! bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 J% {" w: x; I X) @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' H& ?3 @" w2 N( s. _: C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# g5 z7 X1 X3 I! j1 N- n% {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. ^4 Z) G/ ?: d5 u7 yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 T! U4 D! a) z+ `8 F2 e) `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ T' f. ^% H o' gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 i1 F6 z- |3 g$ [: TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # j3 ]7 o. b: [3 }8 o% |3 t9 u4 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# D9 H/ L) |( n1 @$ P2 O
0x00, 0xFF); /* configure the clock for transmitter */
+ Q6 Y, |) o8 f+ TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 O' Q% n0 z" ]7 q; b4 K) ]4 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . L, L/ ? O l2 u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 D+ }4 m/ ? z! ?0x00, 0xFF);4 H7 E) ^6 s! m' n: |8 ?6 x4 R
3 ?& H, V4 M: K- x4 S" a/* Enable synchronization of RX and TX sections */ / i6 K# P! `. l5 l5 z' w% l% S) m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: k! w- X6 n8 U' E/ b* @: XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 [1 J* A$ W' R* `8 D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 K$ E( O( l- i' {! x& x t** Set the serializers, Currently only one serializer is set as5 k9 S1 a6 H$ ]- c" M% K6 @+ i" E
** transmitter and one serializer as receiver.- l) E# ?, O) E. c! \" `
*/
& |5 b" O* t) I2 t. A, [5 FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, u0 m' @4 l. c3 }4 y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 N1 k( c* h' V( r
** Configure the McASP pins
& N7 u/ l+ U8 y# {2 [** Input - Frame Sync, Clock and Serializer Rx
& X& a9 R: n" p. C** Output - Serializer Tx is connected to the input of the codec O& T4 I3 x7 C# D# ^
*/
0 \0 |6 \3 G9 T& v9 L. Y& cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' s; T8 R$ ]9 I' b5 t, {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, c/ i9 H! @ m1 c" OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) V1 s8 n9 {% n' U: e; L9 @" C' Q/ J| MCASP_PIN_ACLKX$ u$ J9 P) N3 B
| MCASP_PIN_AHCLKX
0 K p7 h" E& H, l# @3 U( S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- |/ i4 Y$ T+ Q- G5 A2 n+ r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, q N2 H4 k' u: O% ~1 ~! r| MCASP_TX_CLKFAIL
! C5 _9 X% ^ Y1 A# a; p8 w| MCASP_TX_SYNCERROR% B' [$ t0 B. n* x6 ~, C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( p1 |8 e+ k8 s& h# F5 R
| MCASP_RX_CLKFAIL0 V3 p; O5 T5 a* z/ T
| MCASP_RX_SYNCERROR 6 ~. m) i: b. P+ d: Q
| MCASP_RX_OVERRUN);- ~: g. o( T- l7 Q
} static void I2SDataTxRxActivate(void): {& `3 n* C7 L6 F# D( o4 u
{) ]6 E0 T/ T/ W# W2 R8 R
/* Start the clocks */6 o/ K1 D- a! H2 a4 M/ E4 V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 q5 z. Y, O! E8 _% M5 \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ a; `0 Q8 B5 p+ L7 Y0 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," \# P, h% U4 w/ `( X
EDMA3_TRIG_MODE_EVENT);& T, A7 C6 u3 B! S0 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 v. Y0 P8 y& [7 J2 g8 ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" K5 i7 |2 [! i3 e5 g$ c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ p4 A b) p) }5 v% X# XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! L* r$ o1 B( g2 a/ R: {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( X: i* c- k8 R1 P. p1 O n% a# [; AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# j/ x' e, T/ C; _$ Q& X9 n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- ?: g1 _- R5 m3 R& K! W5 l; {9 a}
3 I0 o+ S9 r$ x1 S0 G$ x1 c7 A8 M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. q h8 p8 W4 N- p
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