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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 B% \2 R9 ?+ @) S
input mcasp_ahclkx,% ]) A. N. @7 G
input mcasp_aclkx,8 z! p0 D6 M% ?2 g5 ~ m2 ~
input axr0,
5 y& }7 Q5 \8 r3 C
1 N5 j, w$ V) toutput mcasp_afsr,
. B* D% |1 D' Z& @. _' aoutput mcasp_ahclkr,0 ~5 e& n0 {3 }- s D3 h6 r/ X: T1 K
output mcasp_aclkr,
) Q I% i, }+ x$ J' Koutput axr1,4 E' n; e& G. [8 y; O
assign mcasp_afsr = mcasp_afsx;
# B. u8 }% L; Nassign mcasp_aclkr = mcasp_aclkx;/ {) j* n, h5 E
assign mcasp_ahclkr = mcasp_ahclkx;' r0 |% ]" d0 h5 U
assign axr1 = axr0; 1 V; ]1 u2 u T, _- N
- J( @- U, o: V% s7 i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 E! c3 W5 x3 O! o3 Dstatic void McASPI2SConfigure(void), B* j+ F5 U( j; e
{ ~. r$ A) p* W- V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: q3 F! Y" w. n! M' F" D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' l7 Z- M9 W1 ~; s5 QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. C/ U, G [* ~' I' r: T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// T2 U, K, `; U& E% B/ t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 h9 G+ Z7 f. ~( r; l& L8 G
MCASP_RX_MODE_DMA);$ c1 T4 I! H9 P" [( s! y& _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 Z a/ _& M. ?' u6 nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 ]% `2 |% h$ \) C. oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" ~* s4 U/ j, @8 {9 R: Y$ SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ m2 c( {, U; Z, QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# R: F$ U% t& `) I6 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 Z D# d! o. X& G1 a# x K5 u- x1 D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 l0 l2 ?0 \ f5 U. s* y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( r3 {7 n9 ]3 BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' q1 q, B9 j* T5 C0x00, 0xFF); /* configure the clock for transmitter */
( n: j, Y/ T6 s/ I% {0 YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* P/ ]5 u2 e/ w0 _6 o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 O& w+ O# `- Q; ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," x. i) N/ }# x( w& s4 j0 @
0x00, 0xFF);: s% q; d9 m1 p, R
5 T" g1 F0 H) ]+ l7 |
/* Enable synchronization of RX and TX sections */ ( M% H, r" g; ?# t" Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ Q; i$ f. H; BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. p( n: |/ g8 a2 n% |0 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 [' Q7 M2 g& N0 G# J** Set the serializers, Currently only one serializer is set as8 [- }8 i: F Y" h$ G
** transmitter and one serializer as receiver.) ~' X, w: K3 {& d
*/1 k/ J @- o3 E+ {" P7 X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ R- }4 [# U) Q" YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 u6 Z! s" o) @+ i! b( B' ?8 c** Configure the McASP pins 9 ?, G& _# Y4 \
** Input - Frame Sync, Clock and Serializer Rx
1 X( E7 Y( V4 Z6 ` n, B** Output - Serializer Tx is connected to the input of the codec E ]& }4 A: t: q* q" R$ s
*/# q9 B0 w+ Y/ e, \" f6 ]& L1 K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ q( x2 T& `5 V. j# m7 vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# G1 ~7 m1 f# V3 H+ y7 s' _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. ?3 u: s& n5 w) X7 S) i
| MCASP_PIN_ACLKX
' h8 ~* |9 j7 y' b6 S8 K| MCASP_PIN_AHCLKX2 ~- s3 U# B* Q6 G8 v l, ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! o( J# B) @$ g! G3 UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' H8 ?6 Q) a- }3 u0 S/ n( e| MCASP_TX_CLKFAIL 4 G6 C- } F' L* t
| MCASP_TX_SYNCERROR) @: r/ i% d# K: e5 [- g2 q; P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; k- f* {4 h* l( o5 d. f! Q
| MCASP_RX_CLKFAIL
: x' z' a# B* U& z5 F' K7 K9 b| MCASP_RX_SYNCERROR
, N9 V5 M1 M t* n' M7 h| MCASP_RX_OVERRUN);/ M# f' {/ v5 i
} static void I2SDataTxRxActivate(void)8 H4 @$ s; k, m0 N" N$ ?. u
{ U9 y' P1 Y! L* V0 C
/* Start the clocks */% W4 C: H, X% P! C* a* j7 C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ O) _3 I8 R7 T* H u0 r6 ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' G E3 w; U4 B: U$ V5 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, f8 q! w+ w6 [ M& j" B# kEDMA3_TRIG_MODE_EVENT);5 `7 U& g+ C: a1 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * S) \9 p- }! F2 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! g: t9 s* T: ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. W: @' V: c) e& W$ O' x* yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
^. | w& i' U4 n0 H# v* C( Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 X5 \1 \8 r/ t" a& F0 a2 nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, V5 m- U1 h# R8 m# z5 b1 dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( g) d3 Q( I. {, i$ c1 w- P
}
- W2 J5 A# A9 h" s4 U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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