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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," Y% o2 U/ m: B! O+ e
input mcasp_ahclkx,( D/ h5 l/ v0 }8 y
input mcasp_aclkx,
% _6 w1 D5 W1 s+ m Binput axr0,
) P4 u! u% ?0 R7 z3 X2 f8 G( ~
B: j C% Y0 H8 b( N9 houtput mcasp_afsr,3 S4 \7 D+ x: Z! G
output mcasp_ahclkr,8 f/ ~! O) r! m7 N1 z' J; {
output mcasp_aclkr,2 q" D7 _7 J$ I8 [" a. P4 r8 I S
output axr1,
0 b7 }. N J/ X k1 Y assign mcasp_afsr = mcasp_afsx;) j1 b2 @7 q8 D
assign mcasp_aclkr = mcasp_aclkx;& z8 \* f6 n, r, O! e2 p
assign mcasp_ahclkr = mcasp_ahclkx;8 l* V% l# d- |5 w( Z& `
assign axr1 = axr0; X9 `( a( N4 K% h/ Q
$ q: Z' M' }* i T8 h! R4 d& U" s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , y: x/ ?$ w/ J w
static void McASPI2SConfigure(void)0 Y# b/ A' C1 I5 [1 D5 z# {- K
{) r, ]4 V* y1 `, e! w* L; E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 k5 i- {; n' [0 Q. i K2 G5 h, [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ J. V' N# W+ S; y$ l: E- G; C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. C) q! [( h& E1 Z* ^/ q, E g2 N2 [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) Z6 O3 B4 q9 t% K2 VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: a) w# s2 @ w7 E. C* o
MCASP_RX_MODE_DMA);
) ~ |+ }' k9 @! yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 B! M* \+ o6 V3 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% ~! L0 j- P" b6 s+ X! {7 T1 qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 d) n9 v( V, e$ h9 V6 x! ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 `4 `- U- @/ M: N5 e5 l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - k. A, {" o; z7 f* L) W+ `5 ]7 {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' J( |0 K# P9 f" K4 C6 g% S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
G2 @8 _* ^9 c& C; j, SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) l( {, M0 u' {) T6 T$ X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) S3 K! J9 {9 H! w8 i& Y/ m* y- _0x00, 0xFF); /* configure the clock for transmitter */
9 J: E) j- \9 _6 r3 Y& q! [; f! HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" V( j0 v3 d2 a4 B& @: r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 n; R( t' {# M2 n. e7 j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 w/ c+ b' {5 ]0x00, 0xFF);
5 Z6 X; Q9 ?. U: H6 Q% w! E" B' b% L
/ a' m+ o# B( w5 }& v/* Enable synchronization of RX and TX sections */
0 t0 C+ X0 x" qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! S3 x7 e3 B v: }1 q4 D( qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& b; g u! _5 `/ c5 C$ l; P7 xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) F5 d: @; u2 M: v0 p' d
** Set the serializers, Currently only one serializer is set as
6 j* G, q4 o+ y R; p/ n6 p" _** transmitter and one serializer as receiver.5 e+ P* \8 `- |) Q
*/
/ A B" A" B: ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 A% I) v/ k6 M2 b% s7 qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 `5 Q3 C. a4 S** Configure the McASP pins
) N* W, D& V6 k% f; p. X! f** Input - Frame Sync, Clock and Serializer Rx2 T$ q9 {0 U& f, |/ @7 [
** Output - Serializer Tx is connected to the input of the codec % o9 s# k5 o c; c) r- G( k* I
*/% O6 m( ^" `4 y7 l! y. @4 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* g5 _5 j6 m3 r3 GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: W" _# T# c, K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: A5 T, t4 y7 ?$ H% x| MCASP_PIN_ACLKX. A9 d5 A, G" | b* G
| MCASP_PIN_AHCLKX
1 w" J0 D& s2 b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
a4 _ o' S# `6 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ r, R+ m2 R8 _' y| MCASP_TX_CLKFAIL ~/ @8 ~0 z* v' N2 X9 {7 W( {
| MCASP_TX_SYNCERROR
! A0 n# r1 X: ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 N( ~+ a8 _$ U| MCASP_RX_CLKFAIL
% K& P) t9 L9 M3 j8 ]6 z6 @| MCASP_RX_SYNCERROR ; s) f g/ Z. s+ C
| MCASP_RX_OVERRUN);
* G0 R6 p. I! A" j: g} static void I2SDataTxRxActivate(void)5 i9 C" g* e5 w; x% d
{2 q p- K5 E# s9 B% Z5 a) H
/* Start the clocks */
# ~- Y, V4 q: z$ jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% X; ]5 D) W; X' p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' T* T6 }, ?4 U, f+ A& r: i' C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# L+ p5 i0 D8 M6 J, m1 J# Z0 [" [EDMA3_TRIG_MODE_EVENT);
8 q' ~8 i& B+ D% WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* M& V9 c7 C9 @: ]4 U0 C* |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! q8 F) p) i0 ]2 w# a# G8 i$ ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; b# W# T' n* P s! D* {! R: Y/ D/ _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 ]4 [3 z% _2 s2 F: v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 H6 A) Q- I( b+ U3 H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( |3 i! q# X$ Y" SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; s4 l$ C! |) y# N$ m/ N h" J+ o}
$ t {# Z) V- }( f7 n; k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * N: [: D- L! x+ j# e
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