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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& _. U7 V/ ]6 V6 X. D! _) B
input mcasp_ahclkx,
5 V4 I- _" n ]# l+ Cinput mcasp_aclkx,
# h, w$ ^# x. I* G6 ]input axr0,
5 X6 x" i9 a7 n
: S1 _+ h7 j( P6 s/ i N9 Q$ n, koutput mcasp_afsr,
. O0 [% A3 A/ \1 ]! y4 m! j1 doutput mcasp_ahclkr,
$ X" N) x( y% c. Eoutput mcasp_aclkr,
$ ~/ ^# i# l+ t0 voutput axr1,; _0 j7 {. F* F( {( n5 z/ r& I
assign mcasp_afsr = mcasp_afsx;9 L9 }! ^9 o4 T5 r; {3 q
assign mcasp_aclkr = mcasp_aclkx;
, h' r- T4 o3 b- S: Kassign mcasp_ahclkr = mcasp_ahclkx;
! v/ n3 V3 y* fassign axr1 = axr0;
9 w& V% V+ @% P. d7 u h* F% {$ C, q! P9 M3 E( d* l3 m/ l. {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; R& ^" I( e8 p1 ]5 i
static void McASPI2SConfigure(void)
2 Q. Y! N6 R* @/ A0 f+ \{
; Y A( @$ b: ?/ R, q( }McASPRxReset(SOC_MCASP_0_CTRL_REGS);- c- X4 P) C+ R' e9 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ d: Y& w. x6 o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: [' x- X8 O; i7 ?# {/ T# a) ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! s6 q0 S# |+ b/ L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; ]# W. W8 Z' o. x( `& D/ c
MCASP_RX_MODE_DMA);
: C/ A' C, H( |' ~( Y$ x$ hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) l0 |2 u t% J8 @ D* ^# B5 K$ }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. ^; A% B/ g. P& v; T) BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; `5 i, Z1 D O+ M. o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ M& V. A7 a" q$ {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 o' E6 A5 }9 l* A5 m% a5 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 c& W G( j5 r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 D* j3 F7 |! b. g0 C1 @- h& u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 ]( V, v# \ B4 P! r8 k: I4 z6 c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# I0 Q) F4 m3 ^% ^
0x00, 0xFF); /* configure the clock for transmitter */6 }7 Y% U. z2 ?0 [/ x c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( z6 _. J$ O2 A! g, f5 Z! I. g' I! ?, v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. i' Z0 ^$ t `9 n; [8 P$ uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 t/ ]* O, @0 W+ K& ?, _- ~; M0x00, 0xFF);
6 ~% q; z q0 ] N1 N2 J* x3 M( L$ k7 n- V, O( i& f: K
/* Enable synchronization of RX and TX sections */
. G, u! W# C6 Q3 t8 j2 sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* o4 O+ b! D1 y9 }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: P0 O& {* b) H+ i/ @# G" h' U) s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
K4 }* a/ ?8 s. u' `3 j** Set the serializers, Currently only one serializer is set as8 J1 X0 |# s* y. A
** transmitter and one serializer as receiver.
/ D9 C# [2 k6 S. j*/
; n; u. g! f3 j' t! a% JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( u: H, _9 ]! sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 `) @. T) [2 H: v
** Configure the McASP pins $ o' x ^' R2 Z& K2 z
** Input - Frame Sync, Clock and Serializer Rx5 e" S/ E7 X# L9 e. h; u8 @( f
** Output - Serializer Tx is connected to the input of the codec ' \$ b$ N& j+ r5 [- o
*/
7 L$ b5 @( l% UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& `- \4 Y& r$ A! F" D- n" @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* Z2 z3 O5 w5 {) ]" bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: y; G& `/ C" }* v+ ^| MCASP_PIN_ACLKX
) f2 Z6 U! f5 n6 A8 u' S| MCASP_PIN_AHCLKX
: m8 g$ h! I% f9 l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: C& Y7 L1 K$ B1 i* K6 g' c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & }5 E3 m+ x( p2 E6 e
| MCASP_TX_CLKFAIL
2 T# }9 f4 g% B* }$ ~| MCASP_TX_SYNCERROR
0 @/ u9 n0 [/ ~1 z$ J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : C# o8 T d( P# l+ N
| MCASP_RX_CLKFAIL; W8 m) _& }3 P; ~; m6 e
| MCASP_RX_SYNCERROR 0 y, P; p+ [% C; \9 R( q; p
| MCASP_RX_OVERRUN);
. |7 S6 m3 p p* c0 o} static void I2SDataTxRxActivate(void)0 _+ G& I: z& w* z! R% F9 e& U
{' m" o/ `) f7 o _' H
/* Start the clocks */0 g% k9 B- R+ d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ E9 K$ N0 i) |+ G2 v6 gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// {* ?4 l' ?" u# f4 x& K4 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( E/ j2 }' Y6 K& o! \3 o
EDMA3_TRIG_MODE_EVENT);1 m8 }3 Q/ {# F) w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, a1 o) M' X- p& F5 M3 J4 S; X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 f) ?, t% y. f! M/ UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; F7 _1 `4 t0 O6 U' e8 J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 `" {$ Z. o) l& m0 e5 W7 ]6 o5 z% k- I& {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 D0 ]& [" d; U6 u2 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 ]% ?+ f: m. @! n w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ k5 H; H4 R1 u& ^}
5 ~0 [* h, u: g9 x _1 A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : `, v3 ]' q7 @& K. m4 R& ]
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