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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( F7 B4 l" }0 m, M: U! g5 i$ s! Linput mcasp_ahclkx,9 \: y6 ]6 A7 B" }4 e
input mcasp_aclkx,2 P1 y4 g0 J1 R( p
input axr0,( {1 m" y3 w7 ^
3 H8 z1 _" w% g, [# h f0 Koutput mcasp_afsr,
& _* R* K& X0 _+ ~3 a& x: s3 S1 i6 Foutput mcasp_ahclkr,/ j, j5 x4 R% {, q
output mcasp_aclkr,- F7 o) m7 q/ z: S
output axr1,, C L, O. @. l& x$ o/ q* D! _8 m
assign mcasp_afsr = mcasp_afsx;! g$ p) U o, @* b: v$ |
assign mcasp_aclkr = mcasp_aclkx;
+ \! ~% I( ]/ v7 Zassign mcasp_ahclkr = mcasp_ahclkx;
% w( v [# h/ H8 Y; o" t7 sassign axr1 = axr0; 0 H6 L' }( ?% t+ n/ ~# f
/ B6 U- U. p# ]$ l' U* W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 t% S7 r3 Y Z! W
static void McASPI2SConfigure(void), q" u3 A3 }6 c! e" ^9 U
{( V3 x; Q; u2 i) I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' S2 o2 u6 d: w9 vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// T1 |+ N( {3 I! q5 E* ~5 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; ?3 E2 A( F& y0 \* j3 n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ l# }8 d2 X3 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# R- D5 K2 e) l) Z w
MCASP_RX_MODE_DMA);% t5 w. N$ U! U0 E% |) N4 q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 C- C8 q% Q3 t+ e0 J) aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 o S2 M, K( v& g( n7 CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % u# ^" ?* N/ t) q, |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. l. \ o1 b3 g# _) CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 ^ D' d4 I6 v. I; i, d* g2 |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 e: ]% O. L' r# z _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ ]+ I" r$ b; F( [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# D0 @) t9 w2 ?2 {: oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. P* {( z8 E" O# U- N* t0x00, 0xFF); /* configure the clock for transmitter */
# _, b8 r Y& k0 L& `- IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 y# O7 Y9 Q; }" W h8 P$ ~! L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; M P; ]6 Y( g t% |. Q. s) {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 g2 R0 ^: w. ^6 K2 @
0x00, 0xFF);" G$ g3 @5 C. Z7 M
8 j) E! \! i% D' r- L/* Enable synchronization of RX and TX sections */ $ S( Y; U. ^0 j7 I! s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 E* t' X C$ o; v" Z7 Y" M; ~% e; `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( |) p+ s1 {$ j% l# y& V! yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" s2 l. y v/ d** Set the serializers, Currently only one serializer is set as* V5 f V9 Y" S, t3 c
** transmitter and one serializer as receiver.
" X5 }; c' j' v: p" Z*/
1 {. I/ H- U& u: X/ DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 E. Y+ \% d1 [! `" h- t' k' O6 J( k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** P) U( d8 w* ], v2 K: X
** Configure the McASP pins
/ g5 s4 H1 m2 Y6 L/ V! B** Input - Frame Sync, Clock and Serializer Rx
: s. D/ [3 q8 ?; u" z/ I** Output - Serializer Tx is connected to the input of the codec ) O$ ~2 M9 V: |0 G0 \
*/& X! r6 H# y% T7 t# k% R* g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, _; o( l4 I+ e1 ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 r+ { c, N: [, h2 W( Y8 ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 H+ |3 v" h; ?' A2 G8 U9 Q| MCASP_PIN_ACLKX8 L' o' N, g" v+ F4 ?
| MCASP_PIN_AHCLKX+ x" x6 B+ R$ R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ {- u9 r0 |/ n: B4 t) t1 ^+ f" CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! {6 b$ g9 x z( \; Z! q' l
| MCASP_TX_CLKFAIL
4 y' l$ I- ~* W3 u" c) ]| MCASP_TX_SYNCERROR# t& p( S% @: j1 z/ X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
b" Y1 R) }' ~& X$ a| MCASP_RX_CLKFAIL: I$ ?& @9 _6 D
| MCASP_RX_SYNCERROR ; l5 e5 \! M/ A7 L W
| MCASP_RX_OVERRUN);9 K" k T, w6 q$ `1 B7 `' |
} static void I2SDataTxRxActivate(void)4 t- O. Y& q# }0 X, K9 d
{
; s5 b, ~% R7 o; G5 f/* Start the clocks */
/ |5 d5 J5 G! `; fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( t, ?5 c% G- `" j; {; n, P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 i& U) H3 R1 U' x: K+ ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! s8 V8 l( ^3 u* m' R4 UEDMA3_TRIG_MODE_EVENT);3 ^1 d1 v5 p5 R% A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) E* s( w) r' h( M7 T- u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 o) S9 W+ T( nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" q& H- m4 z7 B; w) f( N, CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: j7 L" L. E, _+ Z; E/ h4 }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 o2 c% L O: H+ D; Z W! Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 L g" r* |3 T ?5 a+ ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& m& ` ?. W4 F} . g, Z, F! [5 {7 S P7 O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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