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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 v7 D$ S& X8 g* Z! b- sinput mcasp_ahclkx,
. F0 }0 h! T% d) Dinput mcasp_aclkx," {0 ]6 K8 |- w
input axr0,3 N6 z: Y% P: t
5 ?6 x' g9 H; [output mcasp_afsr,7 g2 r2 P( D3 [9 j! }+ u0 G( h$ C
output mcasp_ahclkr,8 C) Y$ k( W3 q6 S2 A. H: H
output mcasp_aclkr,
, R, U* T8 j3 H, l c% soutput axr1,
! k L% N; r3 c, J6 ?, o) [! a7 h assign mcasp_afsr = mcasp_afsx;
9 P: Q ~* e( D2 gassign mcasp_aclkr = mcasp_aclkx;
$ ^9 V, H: s* z& y" G( a- L+ sassign mcasp_ahclkr = mcasp_ahclkx;: _/ z/ x" S' s& D7 T
assign axr1 = axr0;
- ` T( `' i: i
9 `* D% H8 f# c: F( @5 `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 }; g5 U% |5 T5 a
static void McASPI2SConfigure(void)
$ _9 M( s# b& x2 G; A. L7 q{" v; i6 I2 H* T: r& f) j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% @: V# Q. Y4 P. K5 ~* W7 s* x7 u6 t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 `+ h; \, {+ Z4 r* L# p: }9 _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# [8 c$ ]& @0 Z) c4 Y5 E8 O) _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( r1 W8 ~: E! {% ?1 k9 GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 e; [6 U8 W1 ?. z! F/ f- w& EMCASP_RX_MODE_DMA);+ J! u ~1 p% P; i$ @) S6 y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& ]" s1 j: D4 X. J9 AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- Q8 M- d! d* h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 z& Z8 \0 j$ tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& c1 \( {& E0 C& S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 J% d9 {7 l" E5 n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' G; a0 Z1 L. T7 v2 b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 T/ x: y- _3 z2 o/ ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' `; s* \: j% J3 x9 [* _- p* Z* f0 dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, V5 b" B2 W. [& w1 t/ e: E0 R: M$ E
0x00, 0xFF); /* configure the clock for transmitter */" ~7 j2 I" Y8 H$ g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& i. F2 w d M% P! X" UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, ` X m2 F! K0 yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ o- u5 V$ b. V% Z2 W
0x00, 0xFF);
5 [/ t, z- s/ Q* s3 Y- Q( K: q: j7 }6 R. @
/* Enable synchronization of RX and TX sections */
8 r; B0 U* T5 _! [4 Y; mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' N4 z6 v8 w" C( N' XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& L( c+ F' r8 L" u& i2 b) g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- w5 F- `, `! a
** Set the serializers, Currently only one serializer is set as. U3 T3 I" C( A. _
** transmitter and one serializer as receiver.; r( E! x+ p& C* i' e3 X
*/ n* M3 B) t% y* f1 M* G3 Z/ b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) j3 O) Z' j6 \4 yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- ?6 W" P( ^& i
** Configure the McASP pins # T D/ j+ y/ x5 S1 \/ k, a
** Input - Frame Sync, Clock and Serializer Rx
6 z% k$ D2 G/ S/ ?5 r** Output - Serializer Tx is connected to the input of the codec / {" }* F! X& G% A0 L$ m
*/
9 [; {4 P$ P) b0 H TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& k6 U* o* r0 yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
S8 A+ a4 ~/ C& t6 a" \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 q, J5 t7 ]6 Q+ c! |$ r- {$ {" }| MCASP_PIN_ACLKX# \( @" G. w! D
| MCASP_PIN_AHCLKX
( l e, D9 y' S M" Y7 A. M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) x. |8 q) b8 m. U# z$ O# QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ S; Y- p- x$ g( \/ S| MCASP_TX_CLKFAIL + E& R/ k2 o; @& H/ M+ r
| MCASP_TX_SYNCERROR! {( U$ m" ?+ o4 F, i+ ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ B& g' D7 S4 P/ h| MCASP_RX_CLKFAIL
. f$ t" J- r* _7 i* S0 h A| MCASP_RX_SYNCERROR / L+ L* n5 k6 [& p7 ^
| MCASP_RX_OVERRUN);% b/ _; J0 O4 w: Q
} static void I2SDataTxRxActivate(void)
1 n: \7 k9 U: O, R6 u{
. J, U. q& ]7 z/* Start the clocks */8 k/ ]/ J1 v9 R" x, u5 e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' k- p# _7 v0 d+ v# |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 w. q# F; n/ E; g4 K, {7 A: M8 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* \) S6 D$ s$ H; c/ [. jEDMA3_TRIG_MODE_EVENT);
/ t8 L( y/ H1 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) C! q1 K$ I1 u$ ^; U) ?( l2 i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! c% K* V: f# L7 m+ `0 lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 X" G9 ^2 A5 h4 T7 w; c0 YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 M; ~# |" L4 @+ m: k/ d$ wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& c3 \- v% `$ y8 C/ iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( P5 V4 S4 ]4 R' PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 H& m- s3 f# x& @ g' c) H}
$ N, F! k l0 O; v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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