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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: P2 J* a1 ~( I3 v' Dinput mcasp_ahclkx,- a9 ~0 k- C" V/ C, Y( F% q1 c
input mcasp_aclkx,
3 M' o1 ~5 O4 yinput axr0,
/ `' [8 [1 T$ F% y0 N) W, X$ R8 I- ~( w& ]1 L) l
output mcasp_afsr,
* P7 r) X% H, xoutput mcasp_ahclkr,; r5 A: Y( |8 x. p
output mcasp_aclkr,4 l" q6 z3 i; L; j" j
output axr1,
. u1 o. T4 ~/ l+ x assign mcasp_afsr = mcasp_afsx;
& d, v9 [( z4 xassign mcasp_aclkr = mcasp_aclkx;
# @1 U5 d& W) i. P3 yassign mcasp_ahclkr = mcasp_ahclkx; ^! D1 |& E7 H3 w" n: B o
assign axr1 = axr0;
+ p- A: i C! I Q- U3 }0 k
4 S; j; ~& w: ~! {+ k! l" G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) Z* r: S1 C( C4 mstatic void McASPI2SConfigure(void)
% t! }7 \7 N0 U3 ?{
/ a7 r+ s8 j4 v) p3 s3 u0 cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 c1 W p; D/ W k0 `+ xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" J0 `2 W1 t! J: t! ]! D& T6 MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 A! X9 Z- g$ p5 e7 n% |& pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 Y: M1 l8 N M4 @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* |. D$ k. J) @2 J! P
MCASP_RX_MODE_DMA);0 J+ N. y) q% I. l* K5 k7 \/ d2 M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 J! K( @" F6 d4 l2 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 ?3 r6 k! I, }2 p/ `, VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 b) S$ d6 K, @. b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) A5 ?% _4 j! d+ V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ s" {7 K1 K$ l a/ _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) y- N2 Y. r; r: ~7 t9 {6 e* W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 O* y7 v/ a8 |, h- x r I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 v( F* [2 p2 T) N& ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, y( M$ f) w* Y6 c
0x00, 0xFF); /* configure the clock for transmitter */
& ~; B8 W8 u) Q0 f8 U( j- NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# z4 @* m" \* e( ^& H S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ {& G: N+ s" O& Q D# nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 b2 T, ?# E. Q( p4 F4 a
0x00, 0xFF);" f" | }8 q9 w/ P5 `' _: O+ Y
; o& y3 Q1 r0 p) c' ?' _
/* Enable synchronization of RX and TX sections */ * A) _/ v1 A8 x, S9 q; J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% r" q! s, b5 v4 T! rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 l; n5 W" s8 E/ c( b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( s* |1 k# E2 Z; j4 p** Set the serializers, Currently only one serializer is set as4 B9 M6 s4 G% k2 @4 h, m; Z
** transmitter and one serializer as receiver.% a7 }. F. L+ Q+ L! S- I
*/
6 \+ i0 {7 W% W8 EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 V8 _. \/ C/ [+ O% W. I5 {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 J1 f. _3 q' m** Configure the McASP pins , Q9 @! d& @* N1 v& q4 N
** Input - Frame Sync, Clock and Serializer Rx
& J6 ]: y: m% g) m( s4 i# f; V6 j** Output - Serializer Tx is connected to the input of the codec , Y3 D6 Y8 @: k7 z; Z
*/& t; M+ n9 @5 l/ ~" z9 U. s* {7 h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 x0 b3 P1 t% M; B* D1 c- ^; ^+ sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! _; H1 _' G% X5 K5 a/ |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 v, _2 }+ X# ?# U: f
| MCASP_PIN_ACLKX
! J( w& {* I' Y: w( d$ X| MCASP_PIN_AHCLKX9 r0 w; T! Z! `! {& D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% I/ x5 K& H/ y. P# M% C' @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 O) N+ s( A& F: c4 C) {6 r1 v| MCASP_TX_CLKFAIL ( _* l3 ~8 k; v0 }5 X
| MCASP_TX_SYNCERROR) _ t: E; B) C* v! |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; I- I$ P& m$ P9 B4 {" k
| MCASP_RX_CLKFAIL
' q9 {+ U& v9 f6 w6 d( V( ]$ P| MCASP_RX_SYNCERROR
1 o, Y5 g6 X. ^, e| MCASP_RX_OVERRUN); K# `! y/ z( R! o2 T
} static void I2SDataTxRxActivate(void)
5 w8 a a1 o$ O+ F! R9 L4 W{
7 R0 Q n, L# _* y/* Start the clocks */
$ C6 a) e& |$ s, QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 G% U/ {" W) e4 G' l. u" @/ v3 e( _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% ?0 s( b, J' ~% C m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' t [8 \- O% {& {5 j" c# s
EDMA3_TRIG_MODE_EVENT);
- C" K& l' Y0 M) Z% h& p: WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 h2 @; ?8 D* r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& K/ O# \% i9 ~; }1 mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: z( [. v* C) E# r! |; I& X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( i- p( @* _; ?2 z) D3 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ q; W' }, |7 D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" y2 Y" ?5 j$ }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 V. z- u* H# u0 t
}
2 F m$ h% P6 x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' y; I/ z9 ]# ~& c9 g& w3 t) w
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