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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' [& {2 l; R `% w* ?" {input mcasp_ahclkx,
$ N& k: w: U( o7 e: U0 A5 cinput mcasp_aclkx,0 [/ r. N2 _* U( s% ?+ C
input axr0,0 N$ ^7 d; k/ S
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output mcasp_afsr,
! I, T+ z- V0 U6 h5 M! ioutput mcasp_ahclkr,$ G& `6 F) Z6 d2 p; X* x
output mcasp_aclkr,' x9 d' f, u1 ^5 f9 {, k5 j" Q
output axr1,
( Z7 B5 d) W6 t! Q; p/ B- }/ m( n assign mcasp_afsr = mcasp_afsx;
8 O( y% ~* a6 M$ ~8 kassign mcasp_aclkr = mcasp_aclkx;
. A8 @4 c4 w+ D. Cassign mcasp_ahclkr = mcasp_ahclkx;
9 P% g2 w( t! e. }' G; l& bassign axr1 = axr0;
0 X5 {9 f7 `' U |& X; W9 S' N/ T
* |- x! W+ H, H9 r% j* J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 M' H7 g/ P$ d4 V( Dstatic void McASPI2SConfigure(void)
1 X2 N/ ?0 t! V7 u8 N+ M+ U" i{1 a& E. X" K2 ]$ ]4 S W) `) ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( L% E( s$ p) b/ o6 x, T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. G( D$ X; b. PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 A+ f" n# S- H h$ dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% e w9 A7 u1 G6 k9 C$ J9 E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% e( c8 Z" l6 qMCASP_RX_MODE_DMA);$ Z6 H: S; v- H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( j: `5 \" n/ h4 l6 `2 E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 Y/ k6 y7 h" W9 i0 {% V* p( v5 C& N2 dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : O+ s" d" E$ v6 M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- f& ?6 l2 C2 [2 z0 oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ ?5 g% G* M. E1 fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( ?- n; {. O" A* S& N" LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. y# [/ X1 T- n" g3 b% b. m/ h- x M+ L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 O1 b# S' N9 m! \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, o8 }6 r. R# k2 o+ g4 s7 w% ]$ J; h0x00, 0xFF); /* configure the clock for transmitter */
# y. ~% F7 B4 @& q6 `% w; V, hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 D" q% c+ p8 B: d! \0 V/ B4 ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % h$ G: c5 i1 h; I2 [6 e5 e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 O# W, m0 Q+ v; B0 V' G% L& e
0x00, 0xFF);0 ^0 \$ N6 W$ M1 S0 h& w
" j3 c9 A% ]8 Q6 S' l7 `: K- l/* Enable synchronization of RX and TX sections */
* |& J1 O- K) F) H9 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( w; z) T* g" U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 D+ l: T* d! c" Z, SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; |1 `) r/ ]4 B# D0 ^! ?* f% R** Set the serializers, Currently only one serializer is set as
7 Y: X; J4 j% A4 ]1 f# _4 d** transmitter and one serializer as receiver." ~4 ?7 ^& B& o* c2 ?2 B
*/
8 f8 j& a# O) d$ t" I9 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; P$ h+ H `& c* y tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. \1 M- _0 v* U. E; o/ U
** Configure the McASP pins
) O0 w7 Y- A4 j* @, ]' j! A6 ~** Input - Frame Sync, Clock and Serializer Rx$ K* C# W; K- v' q% H
** Output - Serializer Tx is connected to the input of the codec
5 P) Y3 e0 p# |: B5 M3 W7 l*/
" U3 j l. h5 MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, C S7 e' ^- R! D# q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 y3 o7 x7 F/ h4 H# m; t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 N' r- w& V: F3 v" C) v, A5 L$ Q
| MCASP_PIN_ACLKX8 _. O. N9 y; C3 |! v' F
| MCASP_PIN_AHCLKX# u- F' {- K' n# ?( x) |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 v T F0 z3 r8 ^1 b5 bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 _& R$ G8 ^2 A3 z5 y, C
| MCASP_TX_CLKFAIL 7 o2 i' q/ m: B. [+ F
| MCASP_TX_SYNCERROR/ Q7 X1 A, S1 Y" z' s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' A, _1 Q, @! P- K, S9 A" d, W| MCASP_RX_CLKFAIL
0 l& e# ~$ s% w& p! D| MCASP_RX_SYNCERROR
* @% I! |. Y, Z, l0 U9 @| MCASP_RX_OVERRUN);3 _6 k! y6 h9 v$ M
} static void I2SDataTxRxActivate(void)
$ O0 a; g9 c( v{
, r* r- S7 A- D8 P8 a1 R0 M8 P/ n/* Start the clocks */6 a9 q+ L$ [1 I' `- @9 W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' t+ b1 j3 j& Q. l G4 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, a& F2 g, q$ A- @# wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 y& h6 l1 \: hEDMA3_TRIG_MODE_EVENT);
2 o$ b9 D4 H7 b) FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 n1 \+ N5 @( o2 X# X+ Y) UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 @6 h. G9 K- G' H M- u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ T, a1 L8 C$ B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: {* G9 a7 E% R9 Z+ @" u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& A6 A5 ^/ y( y. o8 t% P! v& d- WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- k& G4 I* q. I$ \4 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: ^' W# C5 L9 C7 y0 c% P/ M0 a
}
" H) ?# g7 O' M+ n$ a# m9 t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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