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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 P1 a5 g% Z! m5 g! \( z& X( w# Oinput mcasp_ahclkx,' W6 x! D. w$ a
input mcasp_aclkx,8 g @2 D% }* y4 J6 n
input axr0,
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output mcasp_afsr,5 C- L0 ^+ D Z: M: d& j6 _
output mcasp_ahclkr,# ^9 i( w7 } D/ l
output mcasp_aclkr,
+ z) o5 ~) Q4 @( ]' V2 [* uoutput axr1,5 j: N' }" Z6 j4 o6 C
assign mcasp_afsr = mcasp_afsx;
; u c# {" ^" |: m2 N& tassign mcasp_aclkr = mcasp_aclkx;2 t# @7 Z$ ?7 N
assign mcasp_ahclkr = mcasp_ahclkx;
! @2 z* Z' h" M0 Passign axr1 = axr0;
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$ G4 S0 n6 D) M. R3 y+ I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . v, A% b! p( N4 ?
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);" y$ `. t6 @5 P, E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 P. ]" f' q nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* _& X. `2 k' d9 ~& Q, K S( w: x P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, Y6 H5 G: g/ {+ n( S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( H" }: @) T7 Q6 a! c7 w5 O5 g) M, _
MCASP_RX_MODE_DMA);: Y0 o. M+ Q4 V- e* o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ U! ]3 G& Z o# B$ kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ _0 |2 v1 K, e6 G6 ]( eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: k2 H0 k) |1 H7 @$ g+ hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 u- }( N/ l0 q5 A( l0 \% Y. a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + N4 D* I3 Y! u# a( A( M5 D8 M" W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# t7 z/ L5 M7 P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 y0 C. l6 M7 N# Z I) r) O, A0 B" D! XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 r# L- b# X$ H5 y* w! g* y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ Q) D$ u/ k7 x/ f0x00, 0xFF); /* configure the clock for transmitter */
$ ?- B4 I# P7 ]& VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% ~, |0 G& V. P8 }9 k5 KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : b4 W% S( Y& x7 z" r5 K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- S7 M. A0 D+ w+ L3 f% }
0x00, 0xFF);7 ?7 x& ?* C' x1 p6 u* c6 f
5 ~$ I' ~% H ?7 m9 k5 }2 E0 D8 w/* Enable synchronization of RX and TX sections */ y; i9 u; R+ G. v+ q7 M6 S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 f2 q% ]9 M* _$ v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 y, Q: c' \: p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) S. _7 y+ I$ B' b4 ^4 a( Q4 x** Set the serializers, Currently only one serializer is set as
. N/ R( p, w( b+ U' S** transmitter and one serializer as receiver.1 n& W$ l* r9 e
*/9 c: u$ d0 i8 v; d4 X" Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" F8 y5 B$ h) l; |4 X3 Z6 }7 j$ sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: O4 p: f! g. X9 K* T5 e** Configure the McASP pins 4 T' h5 S8 x( X* Z1 T8 w
** Input - Frame Sync, Clock and Serializer Rx
5 d& v2 o) J: x/ g; }5 K; i( f7 R** Output - Serializer Tx is connected to the input of the codec
' A: @. k$ a" @6 z6 e3 b1 E*/0 {; z' Z$ i1 L( H7 Z# t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ J) O7 q) h; V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: m3 a9 w2 O, _0 u L7 \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 U; d* z9 q& N3 Q1 S| MCASP_PIN_ACLKX
$ E8 O2 L9 _. R| MCASP_PIN_AHCLKX
' n) R7 A% V2 W* N0 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ X; e, K" w4 l3 p9 M# J( cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - g+ i9 X5 h: e: G& @' b8 L% j! K
| MCASP_TX_CLKFAIL
- ]) G5 K3 W4 L; d/ O; e$ j6 u| MCASP_TX_SYNCERROR
3 w' E4 U2 j; ~0 g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; }6 o2 H5 l, r1 b2 @' |* ~
| MCASP_RX_CLKFAIL* c$ L) s6 E( z/ i; s
| MCASP_RX_SYNCERROR
! r+ k, J* N0 Z: d1 q3 h% U9 u| MCASP_RX_OVERRUN);
; b) B. v4 R6 D} static void I2SDataTxRxActivate(void)
5 m+ A2 m2 g( d" X9 r{
, X) A6 T; J* @/ Q/* Start the clocks */
! O8 r- q+ b! B; ~: A( k! K wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" a0 X+ X2 e! ?6 I% \6 z9 I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 i; s7 l$ L4 n/ P& y; f' DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ i t" h% c' p* p7 B' DEDMA3_TRIG_MODE_EVENT);
3 d1 O. Z# m: e+ o& d2 n1 m% V3 l6 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. K- L, W& ]7 x( ]/ `* m; d$ ~; \; FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# l! R3 X- q) m6 E2 O; z1 U. |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ I; H0 A( A5 q( @3 F! t- v% J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 N6 o7 \7 z0 `0 r9 ?6 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: s& J9 ]3 ]& _1 n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 S% o" ^3 @4 c5 q6 m1 P0 xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' Y) h, y j& C2 X
}
) h- e' O: o" G0 T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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