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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 g: `. O8 k( u+ `8 b+ {input mcasp_ahclkx,
: v5 N6 b# X/ Y# m5 `$ Jinput mcasp_aclkx,5 X$ w6 ~# y- `5 C2 b8 c
input axr0,. D+ S3 ~/ s7 l* A2 g3 i
9 {0 _5 ]+ ?) p# _ w- ?output mcasp_afsr,
" w0 W1 P2 `3 doutput mcasp_ahclkr,
" n0 Q7 }" j6 woutput mcasp_aclkr,
/ j' h7 |3 ~6 N6 \7 joutput axr1,
, [: d/ ^" F" l; m s assign mcasp_afsr = mcasp_afsx;) ^8 o l/ [1 F* V" \% \8 ]
assign mcasp_aclkr = mcasp_aclkx;6 o$ V- K* l, t7 Z5 T1 g2 i, c
assign mcasp_ahclkr = mcasp_ahclkx;
) ~% c+ G% H! O. u4 n# z$ G( Y! rassign axr1 = axr0;
: X0 r' f' ^% |& J! [. e. ]: V9 u* C9 }+ g! [9 T7 F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : B7 t: k. u( }% k2 q; ^4 _
static void McASPI2SConfigure(void)! u4 L+ G3 y0 W/ V+ P; K" A
{
; c* N8 f% B5 l) H5 uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 M. L: w ~0 }9 G# vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% U* g8 c; }* F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 ^$ ^6 f# W1 I: e$ m+ W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 x& S1 ^/ e- i% g) Y7 l3 i: ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 w4 V4 M' E$ iMCASP_RX_MODE_DMA);; V( H: m& @) Q4 e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; \! V& s1 q" t# N* S% u* nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; D; j7 b* p4 g9 A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 y; L) }% ]5 O2 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 e4 ~4 `( l$ r' I f$ F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( W( x/ I0 ?9 _6 N: ^& S7 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: ] Q) I* G# e- r, ?0 \: J9 U% c: WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- C0 g# `2 m" X( s, \# IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 d. W3 }: H: l0 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* }6 c4 P$ }' {
0x00, 0xFF); /* configure the clock for transmitter */1 Q5 k# |% [/ Z3 O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( L9 ]7 f: K" H1 y z$ O# e; WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' _+ Y5 a" v( A2 D! JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; `. @+ J1 w! e" r9 J, M0x00, 0xFF);
, r- v" c i( _2 j9 _# Z/ x8 \/ ^8 b/ T4 n* I9 P
/* Enable synchronization of RX and TX sections */ 5 Q- E0 N! b2 `" b1 u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ b3 \1 m$ t# k+ O% gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 ~# \$ P/ k* q! a0 w cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! B: I2 Q. h' o" s2 u" B
** Set the serializers, Currently only one serializer is set as
! ~/ Z. l- j; R% d! w0 K* O! \; r' g e** transmitter and one serializer as receiver.
5 a4 `4 K8 h5 v- \& S8 M i*/
6 O" ?- M+ H2 ?1 F4 hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! ~! Z$ h5 M% p3 ^: h+ wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ Y% L! ^) R. Y% g# D7 l! ^0 i** Configure the McASP pins
( Z- j7 I7 z. [** Input - Frame Sync, Clock and Serializer Rx
$ z; K6 m4 w; g2 i1 A% k** Output - Serializer Tx is connected to the input of the codec
0 ^4 ?, y* v2 y$ ]* M9 I*/) \) e: N. m4 S6 y. Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 j9 B: A0 F1 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 X+ ~, d; Z* t, u+ U% }, H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! A0 W& E% d2 @" f# w8 Q
| MCASP_PIN_ACLKX" x3 U( L% R o$ O
| MCASP_PIN_AHCLKX+ w: x: s( m+ t! @5 `$ q; W( l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ J( J2 y% q: pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' j4 J+ R( v \) x0 ?: q; K
| MCASP_TX_CLKFAIL 2 W" t$ h* {8 T- o6 N6 C/ t, {2 ~
| MCASP_TX_SYNCERROR5 m4 d F; D: E4 R2 U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 L3 r$ Y3 o8 H7 H
| MCASP_RX_CLKFAIL
& @; G" x7 a: H( l- || MCASP_RX_SYNCERROR 3 N" X" J" @$ w7 Z( S% R" n
| MCASP_RX_OVERRUN);
, M2 b! |8 _/ S4 O, z8 g7 c6 R} static void I2SDataTxRxActivate(void)( v8 Y# v4 o, o# s: `& i2 v1 M. W% L
{+ z$ ~7 |4 ~$ G5 Y6 O& u
/* Start the clocks */& d: [3 S/ Z& _% u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; l. |! @4 ~3 e& H+ s& LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. \) a- q5 G$ D1 l2 U. F7 _, ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 ?. P. S4 g4 I8 vEDMA3_TRIG_MODE_EVENT);
' a9 f0 } `5 U9 L# |2 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" P4 ^/ L9 c- w: z9 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 E/ C3 k2 L: _( g, T8 J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ }! b8 M/ V" ~! I" Y# |0 v5 LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 I1 ]7 f& ~, x2 H5 T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; G/ k2 y9 d) z) H R1 R. CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 {% J9 V1 O# C5 zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 \+ T, Q7 X1 M} ; o, m! n3 h& S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / \& q4 z. E& d, F1 R% k
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