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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! e' y9 E- P. ^6 I7 }* Y/ Rinput mcasp_ahclkx,' p3 ~2 G( @9 L! U7 @! B0 v
input mcasp_aclkx,
! c- G& I: H: E: K, p" }& Ainput axr0,
* ?5 E, ~ E, y% z) H" I
& P1 l9 a* y+ [5 E+ b: @0 N6 ]output mcasp_afsr,- K9 C% H& A! d/ e+ k( l
output mcasp_ahclkr,+ n; \, O- _7 f0 Z
output mcasp_aclkr,: _ E/ [0 B3 A. ` X& a
output axr1,# y% M" H {8 g; w* T6 Y
assign mcasp_afsr = mcasp_afsx;( |3 O5 \3 P: ?$ G9 D; ?! C( r0 ]
assign mcasp_aclkr = mcasp_aclkx;
7 ` v. \ `" L/ ?- W6 A! Eassign mcasp_ahclkr = mcasp_ahclkx;
6 | c6 z8 h/ R6 ?( l" \% massign axr1 = axr0; ! |2 \, i0 J) W7 E" P9 v
; ^2 ^/ W3 m5 D/ B, p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 S; r2 d, f3 u' m7 T
static void McASPI2SConfigure(void)5 B L7 u: Y+ k$ f
{ V; J5 g7 ^$ }* l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 u1 }& F, ]# i4 s& t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& x7 J2 b" k0 o6 U# Z/ ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 N5 Y" L6 ]- H' K+ }& Z% I z n* xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% s }0 o: o# b+ d$ G3 ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 [3 Z9 f, t- t1 O- m! q+ ~
MCASP_RX_MODE_DMA);
8 x! z9 E. |- y8 s" D" T4 ^( w3 SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 M- }; u! M7 C- y+ I: z) m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( \/ h, F6 t# \! s5 B5 g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 M: y% W, a6 K6 V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. p4 I# c* f4 b, G3 LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - ~2 {" ~& H0 T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 i( L' I" |- _+ L; L0 sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) F# E# s5 L/ z/ V8 I6 y3 c/ s+ UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 g8 H' a; ^' T# p6 f m8 r) L- g( U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 x- t; X6 Y. a! v/ p: S
0x00, 0xFF); /* configure the clock for transmitter */% W1 @& a& S- C$ O, t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, R' o, q2 Z: @( K3 SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) x. R* d4 h" R8 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( b7 v1 }& G" W) l" n( q T& z6 O& l
0x00, 0xFF);
0 E' z+ ?+ I% a3 t2 J* L6 K" t* d" ]' n" H- s' l3 t9 Q! x
/* Enable synchronization of RX and TX sections */ 8 x7 B) S, D) ?# }* C; _0 Q6 J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 I* A& P$ ]7 {/ e3 zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: I/ v/ M3 n) p$ A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, j Y& r1 p5 G) i$ e: w
** Set the serializers, Currently only one serializer is set as( c) J% y5 }6 x& ` q( o
** transmitter and one serializer as receiver.
+ l+ N6 v" B* z+ k% v2 C*/9 f6 r! Q- m, [* r: m* M: B) p; T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% T) n* D6 ?7 N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 |/ w# A8 c) Y2 x6 J# w
** Configure the McASP pins
" d7 _5 P+ C: y3 s** Input - Frame Sync, Clock and Serializer Rx5 b% M9 ]) s* I% E- x; E2 k$ M' [
** Output - Serializer Tx is connected to the input of the codec
) _5 N2 ~9 L" O) k9 O6 R" W: M3 F7 h*/
M9 |- O j! S$ E& q, ?3 SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 D( W' ]) E& u9 k2 k1 uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ \, R' M8 |: c5 fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- U! ]1 ]# v4 L1 }7 h2 P4 g| MCASP_PIN_ACLKX. P7 h I$ K, w. ?0 K! r
| MCASP_PIN_AHCLKX
- B8 S8 [/ L" D/ ~+ k% ?. _7 B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 | `+ W( K; W* y. K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 r0 @- R. S# A: p) U! r| MCASP_TX_CLKFAIL
5 n r2 ^. K2 Y: s4 Y| MCASP_TX_SYNCERROR
, K" L8 H9 A% L7 a3 F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# ]6 i3 e2 y' `; t) {3 ~, l; M! J% B4 c| MCASP_RX_CLKFAIL9 H$ |$ Q. V1 [; a" F
| MCASP_RX_SYNCERROR
' F) D+ B9 w/ i) [3 D: e| MCASP_RX_OVERRUN);
3 }8 y2 W! m: r} static void I2SDataTxRxActivate(void); b# d. U" `5 l3 \8 Y* A f
{
7 T& L: K" I" y/ O, @4 b/* Start the clocks */
- y% |& ~% X# o5 v- J) \& Q2 D& f) b. i7 YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, g+ ^4 `& j; G" ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 P5 f3 Y3 j/ EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ a, u* K3 _0 g
EDMA3_TRIG_MODE_EVENT);
/ I7 L5 \; A' u. @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : e8 ^, o5 S: C0 i; D2 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 m; E) Z- q9 I2 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 N6 G& A/ W1 O0 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ d0 A2 u, C7 swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ {$ X7 J" `- ]2 x4 [# d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, W6 m+ [7 h5 \2 K) d6 A) Y$ PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& {! V( D% ^9 H7 \} * a, W& }7 Z. _# c- E/ X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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