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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 x( p# n3 G" J1 Dinput mcasp_ahclkx,
) ]; Y' V T( @* q) Uinput mcasp_aclkx,. D1 W1 a* {3 u1 R
input axr0,# H" V, X7 C2 ^; [* e
5 x1 x+ _2 f3 x
output mcasp_afsr,
4 Q \6 T5 p+ Y& | V- E" loutput mcasp_ahclkr,. Y7 f9 ?' E; p! G
output mcasp_aclkr,
0 _& F4 @0 B. ]# L" {output axr1,7 h( D2 d" K2 i5 u2 {% d
assign mcasp_afsr = mcasp_afsx;
2 C0 ^3 E$ S1 ~8 e1 ?6 q" g1 B% Jassign mcasp_aclkr = mcasp_aclkx;2 h6 }( K* G* X- l
assign mcasp_ahclkr = mcasp_ahclkx;% h9 ^% P4 `+ B, K5 J0 s: N; e
assign axr1 = axr0;
( U/ M) y( H3 s% {+ t! H3 U" M! O% Q u3 ]( Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - I. G" C0 S9 w, ^! U, J% Q
static void McASPI2SConfigure(void)
: V! }& e/ M; L" }( Q; V( \{9 M! J' K7 C* J1 I) @5 h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ t5 _0 ]5 H% y5 a3 Z+ O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) K1 y7 U+ M: X6 r! z5 v8 OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 w5 ]* C$ j- D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 H$ B& ^& z# W# dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 {. A4 [: d% e, O$ w- QMCASP_RX_MODE_DMA);8 v* J9 i+ h, c- O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ [0 f T' g2 D8 ^# h$ G' b6 S# S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 S# ^$ X8 R4 x- w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 x' p( J7 D6 n% t( MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ W) I7 I0 ^ }* Y! G" c: F8 B$ Y+ o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " t3 U( g$ A' ^1 o' b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: p9 O# a, A+ Q9 `- @2 o6 MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ I" T. }0 }7 J- s" c5 G& D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 g$ {3 `' S2 o/ ^1 T: @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, l' d# ^( @! V# U5 w0x00, 0xFF); /* configure the clock for transmitter */
' x% V7 Z' R3 L% X* J* @. z UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 z, B" k7 A A% F C9 Y7 |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- s4 M$ ? q- k* l; ~0 [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 z6 H ]$ D' V# O0x00, 0xFF);
6 i. S! r3 X2 B$ C; s; e# g
+ E/ V( O. }7 D" z/* Enable synchronization of RX and TX sections */ " o' r# _$ F; I5 m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, ~, |0 o2 \! W. h0 q, b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' `) d2 ]# ^, u) g- c) _4 gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* r5 Z: I- b$ O" M! u
** Set the serializers, Currently only one serializer is set as0 T4 H0 U5 A$ j
** transmitter and one serializer as receiver.
: m2 D8 d$ M' ?*/$ r- z2 B( a; l" d$ Z4 t$ s7 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 n) s# u; ] {6 @2 @+ N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 n. V! ~, T- A2 [+ v8 t% P% P4 K
** Configure the McASP pins 6 z R( y0 V& ^9 b; u1 J
** Input - Frame Sync, Clock and Serializer Rx
6 f( b0 S+ q- e0 S* ]4 A** Output - Serializer Tx is connected to the input of the codec & H" w6 ]% }0 J. d
*/
3 Q: D# s3 |9 y7 f; T" A3 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" n- |7 I( b# ~# q) h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% Q" ~" ]( P) g" j! E7 kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( Z% |2 q6 w% [' d# } \
| MCASP_PIN_ACLKX
6 ^; h8 n4 N2 X0 A1 ~" g| MCASP_PIN_AHCLKX
$ ?% @. @/ s1 c' f9 t+ i* b$ \5 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// Z8 C x3 o# i Z6 b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . O" x3 ~, W9 Y) X
| MCASP_TX_CLKFAIL . A+ w: P: p( k V8 s4 }/ Z$ L- B/ v
| MCASP_TX_SYNCERROR- Z/ W% \4 I. ?( w- M. ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ D$ R. Y2 ?! F1 i8 V) q| MCASP_RX_CLKFAIL
5 h+ R3 z1 u0 V) W! ^| MCASP_RX_SYNCERROR . P# t! O5 c- g" N! H! U7 X
| MCASP_RX_OVERRUN);2 l8 l9 o: k- q! v
} static void I2SDataTxRxActivate(void) k2 p3 H4 X8 S: C' T- I& ]
{
" D3 ^! Z" @( C- d5 a/ i/* Start the clocks */
7 C. `4 B* @0 O: ~0 a& S$ P1 ~( QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; y1 U$ v6 s* `5 M4 P6 u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 W- I; z) V6 M8 e, e0 `) m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# Y8 ?& L* K! H; v: ZEDMA3_TRIG_MODE_EVENT);9 `& ]8 d! o( e" S9 `, F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & p- U9 u/ |$ T# u* M" V6 s9 |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, F2 J7 u2 }3 f0 Q q A3 \- MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, n& M; t3 c; F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: o9 D, U' L! p5 m- |4 o" I0 e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 Y8 o0 r# s4 S: I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( B! N5 }' Y% h5 F/ h0 D1 Q, VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 v2 h) F( f2 E1 N8 y+ I1 v( {; Z
}
3 N T* d; H+ P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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