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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 B4 G7 S! ?# O. A
input mcasp_ahclkx,
3 o: V9 f, y1 ginput mcasp_aclkx,
! ? P: @% C& C& w1 G: e6 uinput axr0,: b0 W* w# I1 u x
+ Z/ d6 z, u& a; @0 h2 K7 n
output mcasp_afsr,5 y* u. i; }+ R
output mcasp_ahclkr,, R% S( r$ P7 W* s- M5 ^
output mcasp_aclkr,
1 l' I7 D4 o, A: s. moutput axr1,8 _9 H- t8 Y( E' p; U- v4 h
assign mcasp_afsr = mcasp_afsx;+ C. H, ~$ {% p5 o3 ~
assign mcasp_aclkr = mcasp_aclkx;
$ h6 a$ \5 N1 T. q3 W# ` uassign mcasp_ahclkr = mcasp_ahclkx;
# s" H2 V' q ]& Nassign axr1 = axr0;
' w2 L. a* w, j3 q& F' z; `! E- k5 l3 v# }2 k4 d! w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % _2 ~/ h( `7 h" W# `3 q+ S+ |
static void McASPI2SConfigure(void)
) x6 H4 k6 m- k1 @) D7 z{
% P7 V8 y1 ^) O f0 Z9 S- ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);* m( F4 z& S; N. v9 L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 M# _2 a* y0 G h: Y: ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 v j! C& i3 h2 H/ T2 \! ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 ^8 N, j. X4 x W9 m3 F1 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 D% }! }" p/ ^MCASP_RX_MODE_DMA);
5 y) ]1 V8 P0 J$ [# P( n9 [3 bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- [1 R8 d" F w+ f. ]5 d8 b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 q3 c! W: Q# r& {6 m+ @0 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( @5 d! P5 P) V$ ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 T- |- W- {: O+ c2 [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; u: [% v$ p$ c5 `' t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 T, Y2 N) J9 N0 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! n* N6 z+ [% V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - I: T# M% M- Q$ _# w$ h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
J% N* h/ ?0 a. C* S0x00, 0xFF); /* configure the clock for transmitter */
% t6 N. n" N B8 r) RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& V: G1 J4 S \- G+ y7 }' XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: X, p, ]' ^. d# X p. j1 N5 I% b: p9 pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ E) X4 u. X+ Z
0x00, 0xFF);
9 { ]* g5 P8 _+ i( Z) j1 r$ v( r( l/ w3 d0 N
/* Enable synchronization of RX and TX sections */ ' T) p# _, }& P" G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 n9 c) t; _& Q0 P8 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" D& O- p4 ]3 _9 wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! h, E0 f5 D! q" V/ G( r
** Set the serializers, Currently only one serializer is set as+ |! }! n. y8 h6 k
** transmitter and one serializer as receiver.
& @( } y2 R1 T7 m! I*/4 h0 D# g& p7 D) I' t% D7 K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ J+ C+ C+ g& u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% S. s. g6 i) v( O+ X2 L** Configure the McASP pins
# m) E* i1 [ S6 b** Input - Frame Sync, Clock and Serializer Rx
8 m' v& }1 X+ ?6 U** Output - Serializer Tx is connected to the input of the codec
6 [1 H$ I- J/ M*/
1 M! _4 b/ t' {% L @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) }$ q* x4 L3 d9 g1 b8 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& o0 j8 j# `) P2 @: @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, h4 F0 G5 x. w- _) `
| MCASP_PIN_ACLKX( I2 ]& i; h1 K/ X, ?6 m/ p
| MCASP_PIN_AHCLKX
: ?5 Y' ~/ g- a$ y5 j; p+ G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& [" N" v- A( b! f' N) C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , d1 I* d) |0 W2 P. B
| MCASP_TX_CLKFAIL
9 ~; f8 b# n# I, G# u* E4 F$ G| MCASP_TX_SYNCERROR- ]6 H& n( t! [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( P% q- t/ ], I8 ?| MCASP_RX_CLKFAIL
' m" b3 J# l7 T/ j+ \% d# W| MCASP_RX_SYNCERROR 5 V. |. r0 H% h3 {
| MCASP_RX_OVERRUN);
$ X# u3 n5 ^( ~% J% L} static void I2SDataTxRxActivate(void)
4 F8 R+ m& i D. r2 m! K: M Z5 k U{! g/ S9 R9 w7 ]
/* Start the clocks */4 x4 a8 m0 V a+ s1 }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# c$ B3 Q J2 _+ HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 y$ e' d; E' g( [: S* |2 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- o6 y3 U4 s) S8 W6 o3 t" \; ~1 E
EDMA3_TRIG_MODE_EVENT);
% W; O% @% f& YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
z9 i$ P+ H/ t. g4 ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; r- I/ Y D0 {0 GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
a: [# E8 T+ H* r3 qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ l; K$ B0 Z6 d& G' O! M& d, c% Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" d$ {4 `" `. f5 iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! D5 o9 c. @! x- B/ Q: |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! k2 s4 Z+ K) X. X}
6 t' p3 Q3 F* \+ `: p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ i5 w' W0 F5 b' E6 R( B: C
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