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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 c1 e1 t+ c) Minput mcasp_ahclkx,
4 H2 Q/ v) ^! y' S3 Oinput mcasp_aclkx,
4 x+ P5 s5 A- R$ U( ^9 Finput axr0,
7 J! b# r* W. h: X+ x9 r9 u% F6 Y- x. Z- p, w
output mcasp_afsr,0 r9 o4 D/ o2 m- {, b- }
output mcasp_ahclkr,, _' ~3 ]' b& ]# t/ G
output mcasp_aclkr,
6 t; D9 A6 k2 `3 Foutput axr1,
" E, K- S% o# _0 b" I# | d' b assign mcasp_afsr = mcasp_afsx;' t7 N) j- p$ Z
assign mcasp_aclkr = mcasp_aclkx;3 A. H8 Z! w9 d* p
assign mcasp_ahclkr = mcasp_ahclkx; W; e' Y( `4 O- R. p& E& O
assign axr1 = axr0; $ ?4 F$ o& k0 w1 S! y* W; R
5 }: X4 Q/ ` A6 w% Z/ V/ E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% \- t/ p% A* Z. R" mstatic void McASPI2SConfigure(void)
" w$ Y( P) x2 P% n( M{
% I/ l( W& @% T! D ]4 N9 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 O2 w+ y3 z/ q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 Y' w! g- Q7 `5 f/ z7 B" xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ Z* o8 }9 a+ U! E4 |& E! `* _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 _$ c z$ c+ w0 O& h9 H: w# DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! e& K6 l) Z( l: w0 kMCASP_RX_MODE_DMA);! ^2 h1 a! ]: u0 R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ W( `- e5 k( [% \) ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 b/ H! v8 |3 z0 {/ a. nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + T7 x% w) e4 a$ k/ r2 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ R2 c$ c% a3 p: N/ I0 `7 pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + n4 {. z6 `* @4 e- K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 R! S; y' |4 O* z& G) r0 S& O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 p3 ?, V3 K' a. _9 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- K6 P( Y: _1 o0 |" }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 \2 _2 B. ]+ z$ Q
0x00, 0xFF); /* configure the clock for transmitter */: i9 Y# Q) Z b+ l* b' t* f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); ?' X5 F+ ]" B' e# C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); `8 W$ f: l5 a( R4 O' V1 O) ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! O S9 E$ ~/ S/ P
0x00, 0xFF);
: j% [% c' z/ v1 J, M i
# E% B X; \7 B" P( T& s) [/* Enable synchronization of RX and TX sections */
# N+ K4 v* l' tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* y1 c7 j# P" zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 {" p4 Y. r+ A, I* k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, Z4 a8 m U3 C$ R1 n D0 n) l+ h9 w** Set the serializers, Currently only one serializer is set as3 m) | y* G# ^7 i+ m# e% h
** transmitter and one serializer as receiver.4 @" e! r4 a8 ]& O7 i, B1 L
*/+ P9 Q$ T; q+ u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 r1 u. k0 r( J$ t& VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ y/ y4 n; w/ }# y! R( j7 g2 V
** Configure the McASP pins
7 K! M4 i& j, H+ u. n** Input - Frame Sync, Clock and Serializer Rx# i' n# \% I! c1 W+ g
** Output - Serializer Tx is connected to the input of the codec
W8 G* O7 g8 \! v8 p# E; O*/2 O4 m% T1 X9 B# [! D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 @) e! P3 z4 J7 E& P2 z% X7 H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% J& p- w4 L3 f7 v g. k) z% QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ T' P: B% O5 C: {7 N| MCASP_PIN_ACLKX. g: S+ K! i: Y# w( O3 s
| MCASP_PIN_AHCLKX, W! Q$ h, ~3 {1 X P3 C$ `# V% n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 T O2 u4 g" k: r5 p$ lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! A5 N0 Z+ a. I4 u5 S| MCASP_TX_CLKFAIL
2 ^8 `) ^7 V% J0 l( f/ u% }( K| MCASP_TX_SYNCERROR( E6 t' [; x9 p5 v7 R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . X( g; K/ y" ~; a
| MCASP_RX_CLKFAIL8 B2 I* N; G8 u* G% o
| MCASP_RX_SYNCERROR
9 K, g' R; _$ m8 d* D. t/ O| MCASP_RX_OVERRUN);
7 E2 U- ^5 y: A, k} static void I2SDataTxRxActivate(void)2 @* i2 M5 k: P5 q. X
{+ [- c& t6 `* J! i% b; B% V6 |
/* Start the clocks */, S5 X: i2 u1 I! W/ h1 t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. m' t& U: Y% R/ ]! k% O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% T: c" |4 d, |. H+ ^* }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 g, ^+ P* J! ?& P7 R t
EDMA3_TRIG_MODE_EVENT);
) k; H L+ K9 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) P2 l* z7 Z4 z% A/ {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 S6 g' c/ r1 U. t8 D# s, gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; j: M o$ k1 V# n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* A" @4 K3 {& V& d" E1 u9 r3 @2 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; }2 y4 T0 q9 T. V( \" t( x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); t4 i) \3 U0 b/ V7 _ i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ S- {* ^ Y! y' q: O( V6 v
}
; H, H S/ ~, r/ X% R& @$ Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 f9 ~8 [! r! p! z0 Z
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