|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( ?' U1 I/ i' ]3 }9 D! B' N6 a; K3 Sinput mcasp_ahclkx,
+ v9 y: {2 y9 p3 j j$ Sinput mcasp_aclkx,$ f; Q' H6 ]! q7 R6 e
input axr0,
9 G1 A- I0 r; K" O
, V5 Z. j8 P* C& d9 l/ ]5 C. W* K0 u7 coutput mcasp_afsr,
9 m- A$ n/ \" R% X( B4 ~output mcasp_ahclkr,4 Z& c) m H% e; ?$ U+ {# B
output mcasp_aclkr,1 y _. R* [% ?) Y5 M5 _; r# h
output axr1,
+ S' P/ j8 e+ f0 U assign mcasp_afsr = mcasp_afsx;* k. h) Y0 N) b8 N0 p
assign mcasp_aclkr = mcasp_aclkx;/ s( U2 e4 u0 v
assign mcasp_ahclkr = mcasp_ahclkx;. x5 \$ ~7 Q t) [ S" X( U
assign axr1 = axr0;
" {$ h2 Y+ l+ v; Z, s5 Z5 ?; |' n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % S v" t T1 P T. C) y$ ^0 \
static void McASPI2SConfigure(void)
: I0 F, z0 @- G* F, S{7 r2 P$ M8 ~& p2 v6 F3 f$ t' p+ D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- t; p5 W/ u: l$ p: l8 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ B! l1 Y- E( B3 N/ N4 q7 l4 s3 MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); @: N# V. s3 O; C9 Z- @9 X5 I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ {# R; }: m1 T/ H" c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 B' C' g& c: g( H9 L+ ^3 b7 Y/ f
MCASP_RX_MODE_DMA);
7 m5 B! ?0 f! g- H/ w# S7 C+ @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: b: i+ L/ s$ v& I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 s2 T; Q5 n! V+ a# tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 ?0 d& ~& i) Z$ k8 X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( {$ G5 R1 h# C& f, ]& O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 A7 c) b2 e9 q) i3 D! kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* J3 U1 K6 z4 d, u AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 K" ^. [% b% T4 J J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 B5 ^% \5 Z" a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ Y8 ~# W& }: w6 X0x00, 0xFF); /* configure the clock for transmitter */
2 o9 b1 I" k. @. c2 p! Z, sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" W8 `; k$ N, j9 r% NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( P2 W8 |, P h+ V( j- ~' q2 bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ l1 S. [2 v I! L& S# w6 T$ {0x00, 0xFF);3 S; X/ p* G; W. ]% B
+ l# R4 M1 `% E8 m0 g; F& ?
/* Enable synchronization of RX and TX sections */
; |3 F1 q+ @& e, D% T7 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' m g* O$ G! u! w$ kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ v4 A9 S ?( \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* {" |6 x3 O" M$ l7 H
** Set the serializers, Currently only one serializer is set as) c0 e! b' n5 |+ q% K+ {
** transmitter and one serializer as receiver.
8 `7 @9 e% A ?( q n; [*/
! Q( U- G% ~" [! ^4 h/ ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 t; i7 s6 [" J2 T5 n1 k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& D6 U0 T# W* S! M, L$ [; w** Configure the McASP pins
6 V. ^5 t9 w4 a5 M5 X* J* _** Input - Frame Sync, Clock and Serializer Rx( c7 Q6 R1 W0 D: J; p: O
** Output - Serializer Tx is connected to the input of the codec 6 p- I3 |2 z1 m) `5 v
*/8 Y# u2 Y2 h% o' S/ R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) U- \( \5 j2 y& mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* F/ _* d6 c& ~( _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 K+ x: R& ~. c3 `" v M| MCASP_PIN_ACLKX$ J7 m, Z! K& n
| MCASP_PIN_AHCLKX
0 t8 I) d u7 n0 A3 f; {0 P! D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' U) [$ z9 _/ u" Y4 G. R) nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) m r) ^: {6 k( r y6 ?| MCASP_TX_CLKFAIL
' h/ \9 B3 j* l! n: z| MCASP_TX_SYNCERROR# {8 Z" n2 u& W2 B9 n3 m# l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 s( y3 u% S9 z4 H, i| MCASP_RX_CLKFAIL( k, i0 V, w8 b/ I8 h& r _% x0 v) f
| MCASP_RX_SYNCERROR
7 x# Z4 {, V& O! Z3 X| MCASP_RX_OVERRUN);
, |+ U7 i/ B% n& z/ I5 B} static void I2SDataTxRxActivate(void)
9 }# Q+ r1 ?6 }{
, x# n% t* S' h7 m/* Start the clocks */6 ~/ ~: O- Y2 }. o/ i% T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 t, m7 q7 y/ G- D0 T( X9 K6 c" KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ m0 U) X/ B1 [1 q! |& [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 K( h" T$ Y3 x/ V3 [% G- uEDMA3_TRIG_MODE_EVENT);
9 M% h4 `9 |8 r8 J% g0 S9 T5 ?. w7 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& m% h0 {5 k- kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" ]+ z1 e* o3 n4 \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% [1 s# y. r; s" F2 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 g2 N. t+ @+ l* Y7 p' k& U, _2 g( J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 _/ O2 P C% o% IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- Q6 J2 s7 K ]5 G+ ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 F) _- C E! N0 ]1 ~}
' Z1 R% N3 x2 U% L# u: G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " P1 b! E( n; v) S
|