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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 Y* ?2 \ e: i+ Q' T1 z
input mcasp_ahclkx,
% @2 A# i. ^ n1 i. {/ Cinput mcasp_aclkx,. m% C" B) E) W
input axr0,
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* j. V/ {" e3 y7 z6 D9 k- e" woutput mcasp_afsr,
8 c6 ?( \ w' F1 D4 doutput mcasp_ahclkr,
, ]" a ~7 q* j( J* o3 U3 Q0 Z8 U# ^output mcasp_aclkr,
* n( x$ D# U8 [) ioutput axr1,/ D# [3 d: T! S$ }( {, N' u4 K0 P9 ^
assign mcasp_afsr = mcasp_afsx;
* z5 W; ]6 Y, Cassign mcasp_aclkr = mcasp_aclkx;
3 X1 F' d7 v& U: rassign mcasp_ahclkr = mcasp_ahclkx;3 t' |4 { [0 v$ V
assign axr1 = axr0; 3 I C$ |( W3 R* `; p' B( {
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % @( c: y6 ]* A( \* ?
static void McASPI2SConfigure(void)" |. E; Y! b# K
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);; T0 a7 e9 c& _, @" y- n+ P& d1 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& K# n# ]6 V W g2 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ ^& s# Z( ]8 o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 d1 M1 n4 X; G L5 @+ ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 `# Z$ J( y/ U, J1 c+ Y! s
MCASP_RX_MODE_DMA);; B# l' R! T, X6 i: J/ p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 m3 K6 g, ^$ a. xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' C4 L2 O r7 t! r& k/ v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , e2 E& I2 }! k& _ k4 B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( w& d, V3 \' s3 VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 f1 k$ Q8 v& H5 x5 g7 i# kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 E8 D; s4 H# P5 o/ M& S* k7 i: E8 J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 x# [& f" D/ U* D5 O8 h. K* U9 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! E! I* [' u( X+ }" QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 K: @! ^9 Z/ A' o5 S8 E! ]
0x00, 0xFF); /* configure the clock for transmitter */
: O- N" E& N: q7 x. [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! P* r6 a' a/ _4 K7 \$ ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( v1 w9 S2 _0 S/ R, F; S1 c- @( SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( h: M) |, y/ _: R
0x00, 0xFF);
* ]* {; Q* R7 v7 I) y
4 V9 Q& K$ E5 B8 Y* e* B/* Enable synchronization of RX and TX sections */ 3 Y7 B) Q( U" a6 f8 b3 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: d0 T% P& w7 X7 g" D( H) g# yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ y8 a6 e( s# j) U& U: ^$ {: ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 E* I ?5 r2 N, H, I1 w** Set the serializers, Currently only one serializer is set as
; c3 r+ @5 t' n# F i3 B) Z3 n1 x** transmitter and one serializer as receiver.4 w: ~0 P8 f! c9 Z9 k4 \# `# L2 m
*/
- i, r* H5 U3 R8 YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: @' A5 r R) b( K, KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( a5 F( y7 F5 q) \** Configure the McASP pins
) U( V0 K4 D5 K* o# x/ P" ^** Input - Frame Sync, Clock and Serializer Rx
: J) |4 P1 Q1 ]! D7 v* g) y** Output - Serializer Tx is connected to the input of the codec
: s9 _+ T- ?1 Y; S1 O*/
. x& O+ w) ~+ WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) I! F0 z- M; W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
@: a5 Z ^/ e4 ]. gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( B: X! `* k& b' p
| MCASP_PIN_ACLKX
A# D. F' U$ |% K" a| MCASP_PIN_AHCLKX
9 A/ l2 j3 r" ^" I I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 v1 W+ U3 o7 n5 n* Y4 X1 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & a2 K! d/ T8 o/ j' x2 Y( f& z' d
| MCASP_TX_CLKFAIL
+ @5 \9 K3 E8 S @0 k| MCASP_TX_SYNCERROR
: Z6 N4 \+ h6 Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + q. r) L7 b& L
| MCASP_RX_CLKFAIL
+ w; B/ O" b+ _ ^+ c. W1 j| MCASP_RX_SYNCERROR
7 v! I) q! }3 d, O- t/ n- B y| MCASP_RX_OVERRUN);4 s0 d. u4 d6 @" Z9 {
} static void I2SDataTxRxActivate(void), e7 f. b+ U# W* O
{
5 S/ B! m4 h3 q) z" B) d/* Start the clocks */
- {# c1 L2 S ~( P# X) ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. i2 j. @; [- ~, l8 f5 t; U) PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 N2 M# @, b0 L" S' B4 N( }9 l+ ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 y( X1 s1 ]) c* P6 N7 |' dEDMA3_TRIG_MODE_EVENT);
, h2 s: a% F$ X) K) ^+ GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 c7 {, F' Z, A( a @- ~5 N+ ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, b) B+ u$ V" Z% o3 f9 U4 x3 |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& m4 A& l4 K" R! X$ nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" H$ o6 c6 I" ^/ U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" S+ o( b' Z% G3 i$ Q' ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 a; m) h& G9 c! [ `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( a& P% T- P* }
} ' @# y% {( w6 P2 A ^% E* m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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