|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 a8 i* x3 Z& Binput mcasp_ahclkx,
( \. }9 c ^; l* z: y. yinput mcasp_aclkx,; v0 t% _' h3 W3 }6 [
input axr0,
* N: o; y# ]" U5 g* J( w! |! b+ C6 J9 @
output mcasp_afsr, y* \0 d3 f: M6 X! J+ V
output mcasp_ahclkr,
7 A Q1 N% s3 [# Aoutput mcasp_aclkr,& P: D: l- s6 k
output axr1,) }% h( ]$ K0 z5 O( _" F+ q
assign mcasp_afsr = mcasp_afsx;
8 f. ?. z3 o- h4 e0 ~assign mcasp_aclkr = mcasp_aclkx;# N: {/ m4 ~* E( X
assign mcasp_ahclkr = mcasp_ahclkx;0 O% }; V! G) n! U; | H- Q9 {1 e
assign axr1 = axr0;
: k+ C0 ]" z. U, }/ A z. a) g2 r) c! N0 _, s1 ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- y: y: Y6 a* ?! g' estatic void McASPI2SConfigure(void)
/ x% y, D& u! l J' H+ H( A{
# r4 V" I; q0 L/ N4 O- pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 X. C) N$ m+ r1 |. `( J3 M$ G7 uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" L" B X6 }8 ~) J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
W- u2 {4 V" o# C% _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% M( `8 Y1 O! U2 Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! j4 J# V5 y# k. P4 C. s# P7 bMCASP_RX_MODE_DMA);0 F# z/ Y) J2 W1 s7 J. Q/ h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 `+ N0 f4 e. g$ E: w$ EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 H! f O0 O" U! j; p: W( tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' E1 n& U; W/ D# A0 dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& q; E1 D8 @& u# x8 y w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ P! u; f# Q1 w, l- B! yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ D* m' G. S0 G& MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 R1 ~. S' @# d0 P p8 V& s4 uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% @! {2 \$ F! [1 j, [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 ^5 F+ k; z: q# ~% g7 A! d0x00, 0xFF); /* configure the clock for transmitter */
, o" T( ? e8 ]$ Q CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) ]0 S! [6 u8 L# |" @0 f1 o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) L1 e4 J" Z( {' v* `" M- Y- V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- z+ l1 O# j7 F0x00, 0xFF);! J; s ~) @* z3 u' o, T! ?3 Z
, a5 G2 B( g8 g- H! `2 ~/* Enable synchronization of RX and TX sections */ 9 W J& {. E' m$ b- M7 c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ Z$ n1 U7 j1 ?9 v/ g. O; dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 \: v- x. J9 O: U# P- x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** A1 Y/ ]7 H- G+ M
** Set the serializers, Currently only one serializer is set as( c% t% D1 f4 C/ ~3 ?1 Y0 b
** transmitter and one serializer as receiver.
0 b1 n/ J { c- ?3 L*/
1 N5 e7 u* T( n0 o/ S# ?" W4 hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! m2 J1 D7 Z% h( `0 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 ]. p2 A, V$ C** Configure the McASP pins
5 l9 X/ o; s9 Y. Z B0 N** Input - Frame Sync, Clock and Serializer Rx
1 p# s. c! ~! m. b* J: N** Output - Serializer Tx is connected to the input of the codec
& Z9 O& L$ K6 s+ H8 Q3 `% Q*/( C/ d. e: X; T8 j8 }9 V% c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 Z; s7 J) h2 m" C: pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 }' z2 ~7 n+ B/ j- v. U; j: mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% E; _* l0 c) I4 I: k5 w| MCASP_PIN_ACLKX
" _. X) Y/ T& J" C| MCASP_PIN_AHCLKX
6 F# G# U- G; D7 z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 j5 p8 M% o/ Y* i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 b1 J0 h9 S5 Z5 E, K, ^$ B| MCASP_TX_CLKFAIL
2 [& d3 z$ A) [9 u% l| MCASP_TX_SYNCERROR
4 a2 r5 I3 X; d/ b( K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 X+ u2 i2 ~8 R- `" Y| MCASP_RX_CLKFAIL
; |7 h: c/ e [( M2 Z| MCASP_RX_SYNCERROR
' Q& A* r9 ~/ A! A; v. x1 y4 A| MCASP_RX_OVERRUN);
+ W. n% d) Z4 X! I% c: D} static void I2SDataTxRxActivate(void)8 [5 c& J r! d# ~* o! ?( x
{
; _) E* `# ~$ o8 Q2 \/* Start the clocks */: V$ n2 z6 L7 f1 q, A. x% j# y4 O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 v% i J; ~& OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# \, z# X a9 d6 W- O* E3 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" F: f6 R b! X6 N3 r+ o( h7 e3 Z qEDMA3_TRIG_MODE_EVENT);9 m; R" C+ f+ n4 Z7 S6 a% Y: w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' ~9 r/ u" l' Q& S' h V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ s- \ n0 u; A3 [* N8 qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' Y4 }) d$ [8 R( s1 ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) x2 w" ?! z/ [- A; hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 f+ X. ~5 |; W8 g6 y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 V9 w' ?' f! C. B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ I% f6 a( N& C) E6 ^ q} , i2 R* @: n7 {: T. q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , |6 p3 N- o: I. E' i& }: V
|