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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 d) l* {) f- M$ E
input mcasp_ahclkx,
* L, E. Q+ e0 a/ g D) _/ w6 I7 tinput mcasp_aclkx,+ n6 b6 G1 n4 }9 v& }
input axr0,% `( C6 }5 p4 h# O/ y
4 K0 d! X: n+ Y$ w8 I) R- s) Voutput mcasp_afsr,# G+ t) u+ q% f
output mcasp_ahclkr,
9 K4 ], r4 F# c# L/ X5 t$ _output mcasp_aclkr,
( V. R" O* _5 }! J* Voutput axr1,: l% h4 Y3 u B0 l4 g
assign mcasp_afsr = mcasp_afsx;7 }! ?& p2 c- B
assign mcasp_aclkr = mcasp_aclkx;2 z1 U9 w+ l8 r( q: C+ M1 O
assign mcasp_ahclkr = mcasp_ahclkx;4 y2 j4 B5 T" `' [" Q
assign axr1 = axr0;
1 ~* D7 K7 O& N0 i8 u8 t" }% O7 ~
& ~0 C6 C7 S5 ]1 V8 w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( X& ~9 l3 L6 @: @static void McASPI2SConfigure(void)+ F5 p7 Q N6 m" ?" Z
{
9 r; L/ Y( {- c$ A+ e& s1 |+ x# sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 B1 U7 Y$ `: L' v3 A, m; w) eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. \& ~, y4 Z: q. w! BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( r: s1 A# Q1 _9 z* r1 zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; [& Q6 \9 X1 c& b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 ^ W* n1 ^2 ]2 }, M
MCASP_RX_MODE_DMA);1 y+ \# Z, K9 ^( F$ ^ f! o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: P2 I, |5 G5 Q1 m: ]8 u ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ j. ]) B3 p# M1 Y7 q s+ R8 U5 P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . v* A7 E0 O1 X' M! i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& K% O5 f; T% }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 ]: b- H/ f: DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 ]' b" y# v% eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. e) b1 Q8 U/ \+ W! E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : n. _+ I5 Z& g- K2 F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. L% `0 y' s7 D( G# P+ J/ J' g0x00, 0xFF); /* configure the clock for transmitter */; M1 U6 ~# E0 }9 w2 P9 H+ v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 C9 ?" p9 y! ?. i$ @, G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 y+ `& ~; S: K/ sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& c+ w `: u1 P! k6 w
0x00, 0xFF);0 U( U" S4 o0 l$ I. v/ t, Z
E0 e( C$ K Z* S0 X* ]/* Enable synchronization of RX and TX sections */
$ E9 p' a" j$ s1 `, ?2 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& [0 z- x% [8 ^9 I2 I" X' i; JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# X) N$ t" ?: t, O( Q7 Y _; V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 K; j" i+ L# n- q** Set the serializers, Currently only one serializer is set as
2 o' D' L! |# v8 x, ^** transmitter and one serializer as receiver.0 ]* ~' z$ T- j! X
*/: w) \- ]. c/ e" D/ P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 W. G( N& b% M* C: \+ O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' M3 u7 [ U" ?) t6 b! P4 C** Configure the McASP pins % i8 R5 E7 e: w: V3 w P7 S8 @
** Input - Frame Sync, Clock and Serializer Rx5 j; y3 C+ Z5 Y1 S3 r; m
** Output - Serializer Tx is connected to the input of the codec 9 _2 n }- K( ^# S" u4 o: g5 a
*/
. d5 z( H2 T3 ^* K+ E0 P. _# A. uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 P: K- h2 r# t! E9 {: SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& z: L/ a" V' N( u9 ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ B& N* v" r* I2 c0 u
| MCASP_PIN_ACLKX$ G% `. h; h# [$ S$ R" l) I9 Y* ` d
| MCASP_PIN_AHCLKX
B, y! A' B! s& `4 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 S t/ s# k# S5 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% p5 n+ V, [5 f& B8 M9 C8 i| MCASP_TX_CLKFAIL r2 z* s( |$ H) ^
| MCASP_TX_SYNCERROR
) j# h+ Z, A) ~) Q' K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) d' P5 S% z1 ?$ Q
| MCASP_RX_CLKFAIL, M$ S; T+ D2 j2 |
| MCASP_RX_SYNCERROR : ], E7 y. h* Y" [ Y
| MCASP_RX_OVERRUN);# J& `- z1 I$ L9 c z
} static void I2SDataTxRxActivate(void)
, v3 w8 @# o6 p) V4 M{8 g. U8 c2 |- C s
/* Start the clocks */6 T! j7 C8 z; @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ R+ o( E0 C+ a7 GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' Y& X5 ?: V# _! i1 @7 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 \% X$ n' x" C4 EEDMA3_TRIG_MODE_EVENT);9 x& T& C* M+ T5 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 v4 s9 @7 j4 x4 N& Q6 g$ D- `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 a/ B3 r: D: \" q7 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& n/ K: [3 e' n9 d; t" G# \ U& {5 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 }6 m5 D' B/ J+ Q6 J7 q1 M+ Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( c, K) g s0 p! z TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. A; b3 f* _/ t, _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 T. i! ^+ a" h
} " w9 J2 ~0 O. c1 D& c. }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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