|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 h$ n5 d* D+ |! m0 Xinput mcasp_ahclkx,# F3 a6 h4 R4 R8 d
input mcasp_aclkx,
9 }) @ y ^( l7 V, P4 ginput axr0,- |' D( z* C% N- x1 r- V
; p. j m5 Z5 h0 @0 C' ~4 {output mcasp_afsr," V5 b6 I! U- Q0 l+ U) g
output mcasp_ahclkr,+ L! N" p! I8 j4 o7 ^$ @& m
output mcasp_aclkr,
' U7 R9 ]! J# s1 B8 L, }' ioutput axr1, a, T* g4 K/ O( a
assign mcasp_afsr = mcasp_afsx;
" q5 ?8 c. x8 [ o+ N- P( r4 d9 dassign mcasp_aclkr = mcasp_aclkx;
2 i0 ~/ v6 p$ I9 Vassign mcasp_ahclkr = mcasp_ahclkx;
0 B# M) ]: z! `2 d, [0 sassign axr1 = axr0;
' w0 Y1 K: m0 c9 J
/ H: [- d0 H8 V/ h+ H0 D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) u/ c) A Y9 i" W7 V7 _) \static void McASPI2SConfigure(void)
9 t' w2 E; V- U/ j3 o{
9 C: Y# }1 e% m* |# hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 ~: D& f( Z4 H2 C! t% O6 BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- @1 q2 j8 _% O* N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& g5 S6 z3 Y* `' W. o! z& l- \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. a- g5 Q4 G& B" p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ e5 g% I; U; h3 {' r" U+ SMCASP_RX_MODE_DMA);+ [, t9 m, c2 l
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 a1 f8 e8 m, Q2 v# ^2 ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ E# R- N6 N2 B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' a8 L# U! J- Y7 L+ M/ Z p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 k* H; @: _7 `! h# \; C" cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 d# t8 c) Y9 B8 [# o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ Q ^; d b$ m5 l; h/ U6 g" C1 K/ l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 E* H4 ]& d0 I6 U7 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 D* V+ w! C$ q0 D; X, B1 e. P1 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 c: P6 V* y0 `( f7 Y, B
0x00, 0xFF); /* configure the clock for transmitter */
8 V% `0 `5 I* s3 L& v6 ~5 x& CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, `: f' w% r! ~! u1 L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ i6 A+ S4 d# e; t6 X: w+ H2 ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% ^1 b1 m! h7 Z9 ]4 U% \- G0x00, 0xFF);
, N" T q8 d: G% p% r0 C
& D8 |0 Q3 [0 y# X+ d: u! @. [7 T/* Enable synchronization of RX and TX sections */ & c; ?3 n7 s4 H9 U9 M- [/ g n- n$ ]+ X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 j# F/ y; g2 o c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ W7 ]) \/ f8 [# ]! z! o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 _, r3 ]5 W; ^: R8 t
** Set the serializers, Currently only one serializer is set as
5 g/ p4 Y& c- u9 R) e) E** transmitter and one serializer as receiver.
; Y' Y3 G w! S* v s*/6 W- p/ Z* \' g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 h- j7 v7 |* ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 x3 s: K+ g2 E3 p- c+ ]** Configure the McASP pins
) \( a2 W# k2 e6 y8 Q** Input - Frame Sync, Clock and Serializer Rx
& M( N" l/ B* h0 Z0 J2 F** Output - Serializer Tx is connected to the input of the codec
# T6 s& B! a1 a4 R) {- z$ Q8 C*/
% d' B9 q* b/ @( r2 \" p( PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 s% ^: T) T4 a- I$ o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 p4 h e0 g& w" u& E( r& ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! i2 \7 v+ b4 P
| MCASP_PIN_ACLKX
3 h- _4 u3 k! D/ b7 G, M| MCASP_PIN_AHCLKX7 Z1 e" k' Y9 ]1 l$ v! N9 O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. N' r6 y, R1 ~& Z7 L6 mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 G2 X5 H4 V! e2 @8 _8 a
| MCASP_TX_CLKFAIL
! D* @: r( s+ T| MCASP_TX_SYNCERROR& ]1 D0 C1 L2 H7 ?. H' N; [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - {$ p; D# h1 R# W: o
| MCASP_RX_CLKFAIL
6 u1 m5 m* Y5 h7 \: G* @| MCASP_RX_SYNCERROR
$ R- ?4 @3 y/ A| MCASP_RX_OVERRUN);
3 P" u* |: q% x: q# R, x4 c} static void I2SDataTxRxActivate(void)9 o8 g: I b. L% J
{+ |2 V+ k3 l5 x& c$ A# ^
/* Start the clocks */. z- r6 W& X* C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* u/ }0 j( E! P* N/ ?* v+ t! _& `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. @% W7 x5 s1 y8 W2 v' g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- l! W' X7 K. w3 K! a9 CEDMA3_TRIG_MODE_EVENT);
$ D1 s$ r1 o; e! S7 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 t& [( l2 a! N8 o, R6 X: ~5 aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 p" V% X5 v6 O, ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# F* F5 l+ D. h( E- k5 y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ Z- Z4 l4 `5 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 f g2 g: X: B3 d. w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
P# `% [2 n$ H1 W& g3 m( ^4 I7 XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 o0 K; z: v8 V" I2 Y$ k: `4 Y
}
, L g# n1 k0 L6 {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- M" r# g7 Z% E5 }, q0 [ |