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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 S! c' ?6 j8 G/ g+ L0 ?5 Ginput mcasp_ahclkx,
9 d2 u2 I/ Q. O5 E0 w$ s! S1 yinput mcasp_aclkx,$ R h. Y% d0 I* }7 [ z
input axr0,. z3 o$ t2 m* ?6 I8 n
# H1 S, D7 W1 Y# H) _output mcasp_afsr,# Y0 s4 m( R; J+ U6 e4 L e# ]$ j
output mcasp_ahclkr,( @# v* a6 V( ~' P& {% a% Y4 v0 c
output mcasp_aclkr,1 E' K( A: v+ M" I/ }8 H4 Y
output axr1,
$ K" h0 o0 p" S: Z3 d assign mcasp_afsr = mcasp_afsx;
& G9 W& M; W# Y- Gassign mcasp_aclkr = mcasp_aclkx;
1 e9 m2 T; o) Nassign mcasp_ahclkr = mcasp_ahclkx;- @! Y" S! B4 g* {' X3 S
assign axr1 = axr0; 6 T4 C E4 ]& g, R
6 H6 a; F D) `! C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 w" Z# d3 i O0 w8 d( I
static void McASPI2SConfigure(void)
7 Q! [* o6 Y+ T& u- `7 a0 }{
2 m5 ]- Q' W8 Z+ B. m& lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" d5 Z. @$ d, k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 {6 n) I2 A. A; K1 E! l& e, {% C+ C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); {% }5 A+ n0 K! i7 ?9 S6 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ f/ L( o5 X4 U0 M4 I! yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Z: @" @! `: fMCASP_RX_MODE_DMA);3 r* Z! ]' t; ]: |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& r! j5 b" ~. R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) H2 y: [; Y bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . g' t! u, c2 @6 Y- d( a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. p/ C& d; O8 k4 a9 m6 C% b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 u' ~+ o, V) kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) ^& U% p5 C. g2 { `% n% RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 j: n( Y$ K2 A' \( t% J$ UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" h+ S* ^: K: n+ OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 n9 J) M# o+ j# x0x00, 0xFF); /* configure the clock for transmitter */
5 D' [4 i, d, jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: I8 u0 c! c) f! ]' ~; |: O& p& p$ c4 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 r( N; i' N% @' j2 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* t( [8 [. P; W5 l' A# X F# a0x00, 0xFF);! m# e- A6 d% P e
/ Q( `0 ^$ J$ n- M5 E/* Enable synchronization of RX and TX sections */ - s& D5 Q( F! c) w9 Z% K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 C" @& R- }$ @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 y$ S6 {/ j: hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, }( m: c" @4 z) ~4 u$ N
** Set the serializers, Currently only one serializer is set as
( F% _1 x, Q4 m$ x** transmitter and one serializer as receiver.
7 o# \2 N @' R3 l T( n6 V*/
5 h8 }* P; U4 \. jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& g' O/ l* s# nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( X% x5 j2 k0 ~ t0 M. x, n
** Configure the McASP pins , v6 ^9 O- z9 M/ A5 L
** Input - Frame Sync, Clock and Serializer Rx9 m8 b8 e$ E" X' J
** Output - Serializer Tx is connected to the input of the codec 9 w* }- Z/ v, L# p+ @
*/
2 |) z* x. x' b# k5 V7 {9 O" F& JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% J4 t( g: ^7 ?* V9 m _0 t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 [. ^0 l/ O9 C' c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 \0 f7 z9 w. J6 C$ Z$ B( C2 t| MCASP_PIN_ACLKX2 u) b2 j# H; Z2 x [1 u
| MCASP_PIN_AHCLKX
/ H! p! x% ~% q3 D& `3 p0 a \5 g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. H4 ^0 _1 @. V* r5 M+ dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # E( l. u4 R- R# v( p
| MCASP_TX_CLKFAIL 0 ]8 b+ O! |* H) `# S
| MCASP_TX_SYNCERROR- h6 M, j2 v: R( ]; p- ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 }7 j7 ], q0 M' z/ z+ Z: R| MCASP_RX_CLKFAIL/ v' }5 Q1 {0 W/ A+ N; | y( x
| MCASP_RX_SYNCERROR J: d1 S0 t$ P) S
| MCASP_RX_OVERRUN);" i, A9 U6 f$ i) M7 Q D$ Y
} static void I2SDataTxRxActivate(void)% L3 S, J( T A( Y9 j' F7 d5 @; ~1 d
{
* x4 {. E* a; g: a* [. U/* Start the clocks */
9 W( ?! X7 V5 d! \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 F( ^& X# K; U7 F) b0 q$ m. }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( k' @5 i! z* u; q9 E* CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 {, }# q6 x8 G7 Y% I0 MEDMA3_TRIG_MODE_EVENT);6 Y/ Q' X9 o. @$ ?& e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % ]. P6 ~( J K$ K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
S: C# j B& `: CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) O! V1 s, y, g6 s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 w' k& B4 L r9 w- _* W" n+ iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 D [9 k% x) C1 ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 [4 x& j. `6 ^3 `. R2 JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 U' k4 D0 s' N} $ Q3 Z4 P) m* v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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