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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," i o) W' }: ~9 S8 O
input mcasp_ahclkx,$ |* v) t }# I: b. m
input mcasp_aclkx,
5 X" @3 r9 ] winput axr0,
0 P' ^* b' i' a0 x% Q
3 ]8 b2 v, y3 f5 F1 i7 j4 aoutput mcasp_afsr,
# v0 o4 Y G& {5 f' e# N1 n- `output mcasp_ahclkr,8 w1 ?; v( ?! @; W7 l
output mcasp_aclkr,
& ?4 r+ p; I, L: k# a' z( `% qoutput axr1,7 U* S' ~$ m3 t! v
assign mcasp_afsr = mcasp_afsx;
; D% f+ L, }! q2 dassign mcasp_aclkr = mcasp_aclkx;
/ j5 T9 w6 t9 A' b: a T; zassign mcasp_ahclkr = mcasp_ahclkx;
9 W) X0 u5 f( P0 g# s* _assign axr1 = axr0; " h6 t) _) q' G5 V& F: p
+ j2 W7 f! g: L+ f! [( w3 k: A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 I* }2 B2 G) }3 z
static void McASPI2SConfigure(void)
( e5 L9 ~" m3 x/ T7 I% L{2 c; b# E% \+ f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 F9 _; b; n* J4 R2 c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 j- q+ e* r" R* G/ PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 l6 T, i$ d* Y1 _- S# n8 @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, C8 e; F5 f; N5 s" \, ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# Z. @ S" {5 y, ~4 _) aMCASP_RX_MODE_DMA);
, ~8 q+ E* G3 J5 NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 N6 a, d z6 ?9 y; `2 W- Z' i4 l; w- ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 p8 S1 N f# G- B% y+ B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: {4 r9 } _" |7 S, X4 D4 w' OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. n# C& V: @! z/ D5 y, W1 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% {4 M- Y. m. P& U4 i& V2 tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- M/ t9 E, q6 \. e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 O2 C m8 E2 b( z5 ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ |" W; j8 O. N$ o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 g9 b8 l! ]# |# {0x00, 0xFF); /* configure the clock for transmitter */6 r% ?/ B' V0 m) S! p2 p7 @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 u: K# N( ?7 p0 WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 g: B5 E1 j1 }( \, y3 L: \- XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ t$ i3 n* \6 ~) H) S9 g. T& `0x00, 0xFF);+ T% i8 v) G1 C1 Y1 g
$ }1 @; Y6 }7 |/ |8 E
/* Enable synchronization of RX and TX sections */ ( L( @5 O& c C. Q E- H' y+ F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 Y I( I7 K2 h9 ^- C6 U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. K' m; q- K8 Q' t) g; f' {7 [: T i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 D" P! ~8 e* m
** Set the serializers, Currently only one serializer is set as
7 G, s& b. P4 h. U& _3 T1 [" {** transmitter and one serializer as receiver.
/ X' Q( f) X# M1 T5 C+ z+ x*/
# P H8 S2 r! W0 l0 W1 ~+ c# x* h! T0 |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ s+ O# c1 u- a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, [' f0 g, ^' C/ w, I f/ k/ a** Configure the McASP pins
/ J5 Q5 R' @3 |2 x** Input - Frame Sync, Clock and Serializer Rx
! e L' h/ ~- g) V$ Y; J** Output - Serializer Tx is connected to the input of the codec
# l% h+ a& f$ `7 T. H$ n ~% O*/5 m' y8 R: p V0 Q4 l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, Q" c( @3 E W$ S# V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ W, _# |" N8 Z1 RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! d1 v0 J/ t5 n; ]9 W0 ~- p| MCASP_PIN_ACLKX7 ^( O3 l; f7 X% h4 S
| MCASP_PIN_AHCLKX
$ K: d B$ c4 h7 k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, I% p# y& c- p4 r7 NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : ]1 N0 g/ y2 L K& ?# u3 H
| MCASP_TX_CLKFAIL 9 m. i0 d- ?4 x7 }. C6 ?
| MCASP_TX_SYNCERROR
- y4 V+ t$ Y5 B# ~0 B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 _9 M4 K' {0 ~1 v( W| MCASP_RX_CLKFAIL( `5 Z; g8 L7 j2 F) R
| MCASP_RX_SYNCERROR 2 n, n2 g0 C" s0 Z
| MCASP_RX_OVERRUN);
2 s1 I* s2 S+ W0 K) Q} static void I2SDataTxRxActivate(void)
" l/ R2 j0 l" Y0 ?2 V- r{
% W5 }& n' g( b: E& {% p4 q$ p/* Start the clocks */
( d; @7 k* ]7 s. O! V( LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* ~9 I2 N& k! w D5 |' t4 w! H( @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 g) t- p p7 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( U5 s4 g9 `" A/ E2 I/ cEDMA3_TRIG_MODE_EVENT);
4 f% j8 a; }1 j6 w- l ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & R- Z' j" P1 ]& v% J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ x8 c K' W7 g5 [ E$ KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 Y- P9 H0 C, l+ U$ TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 ~, N' V9 D3 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ y/ x1 @0 A' p; V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 q# W. h( c, \- F9 T/ H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: F$ W5 e+ |% {$ o} 4 m) c" ]; \3 z2 v# X' t7 M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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