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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& ]- o1 ]6 x b6 l! Xinput mcasp_ahclkx,# {! k, y& ?* ?1 F6 p
input mcasp_aclkx,
' e! K7 @/ \) V9 I) q$ |, w6 ?input axr0,
* n/ ~3 m& h. _+ u2 C- X2 G& G! f f0 ?
output mcasp_afsr,( i7 v& r `. k7 E$ V" R8 u
output mcasp_ahclkr,
! g! d4 b0 p- t$ Zoutput mcasp_aclkr,* p; Q5 R" D" s) ~1 f! y( r2 Z
output axr1,( k/ U, o# ?, @/ ^+ n. i
assign mcasp_afsr = mcasp_afsx;! M3 _" K6 E4 i2 `1 |0 v& l, e) h0 Q
assign mcasp_aclkr = mcasp_aclkx;8 d# r8 _/ I1 U5 m9 k2 u. _; j
assign mcasp_ahclkr = mcasp_ahclkx;
[1 x' c& U) x' Jassign axr1 = axr0;
9 j9 g! o1 _. O7 k# O; Q! e) y' I! p- Y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 \5 M9 T0 ~7 R9 J# [2 N0 T1 O
static void McASPI2SConfigure(void)3 b) g, Y' q. C; T$ J
{' P5 I6 W/ g2 l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% ~2 x+ u1 a# }: E. c, g0 b3 F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 c4 v! O* ~$ bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. a) i, ^6 R- k: I% y! ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 M1 A* W8 \- C( {3 QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," P0 V1 W% V6 d& x5 t6 [
MCASP_RX_MODE_DMA);& D& b i5 V. N0 `6 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 ?9 ^& u. j9 ]6 h: xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% ^9 R) m3 q; W/ m+ Q9 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' ~8 ?2 Y. S& p; ~3 x- b+ `8 hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 x. F& t0 F& z/ s# ~# VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & i+ ~ S: Q( u2 }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 ~3 A5 A' Y% v; c4 y% n: {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 C5 U6 U5 a" { BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- w: h8 X, b! K% oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 U; z3 H" x9 z3 ]5 A0x00, 0xFF); /* configure the clock for transmitter */6 {/ Q; m- z" l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 ?' }' j) \, hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # H: ?3 @9 P- W5 j' U. m! P( j/ P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 \" A1 ?$ c5 N. ^" s
0x00, 0xFF);: u5 f/ L3 @; T: ^/ C
' X7 z3 m: i& m! ~4 \+ p
/* Enable synchronization of RX and TX sections */ ! Z/ y0 T7 ?0 K; n( t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ U7 E3 y! D# ^, Q" w- W2 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); d. G7 k5 ?. L. @" a! o8 G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 D/ E1 ?. b. A3 x& a
** Set the serializers, Currently only one serializer is set as
% C# W* h. b1 N** transmitter and one serializer as receiver.
' n$ M( t8 [4 l4 T# }*/& N7 k _0 s; g. Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ m! o. U) ^& @- H& T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: }0 r4 k9 K4 G' ~/ R
** Configure the McASP pins 0 u; O6 {6 K5 h' N0 t: X
** Input - Frame Sync, Clock and Serializer Rx
' R! z( j" k" w. h* o** Output - Serializer Tx is connected to the input of the codec $ b; b; Z4 u7 L# P/ P
*/$ j- ~5 f3 i1 f* i0 a" R! j/ \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; ^# ^" n4 a8 |( g( CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. r2 c7 T% W" J& x" M. b# ?8 ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: l! Y6 p: J% A/ P- k
| MCASP_PIN_ACLKX
; \5 t0 w& k$ {( y| MCASP_PIN_AHCLKX
* E, h1 T0 W5 \5 _6 l: e6 @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& O, D( `5 S5 r; e4 k3 ~. k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . R% q1 Z2 z/ m7 o6 j
| MCASP_TX_CLKFAIL
' ~4 b" r! ?# U| MCASP_TX_SYNCERROR
6 n8 ], F& u) t, s& @$ n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: g3 D' e1 E3 \6 T& ~. b/ |0 F9 I| MCASP_RX_CLKFAIL
1 l" u V- `2 |$ `7 K( E| MCASP_RX_SYNCERROR 5 ]3 e6 @6 f( O
| MCASP_RX_OVERRUN);9 }% K2 ~" B! T& T( l
} static void I2SDataTxRxActivate(void)0 h% @$ }3 h% B' _
{
8 r$ J p2 }( r/ Y" A/* Start the clocks */
; {8 ~. A! Q1 K# p) u3 MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) U1 O/ U* j8 s/ x! f vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 a, U, X6 u$ W/ g5 L/ A+ oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( z& r9 G$ N7 ]( U
EDMA3_TRIG_MODE_EVENT);$ N) `1 E# R7 b+ G, E j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 @# f4 n# L2 w+ Q5 j/ d8 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 ?+ S. W' m5 B( ~0 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ i) O) g; x2 M- WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 ]) E6 W/ q' [& J1 K5 p/ S1 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' r; f: X9 H1 JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ B' @# ^6 I$ Z( I, C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. J4 ?* ?6 v3 u& [}
) v8 T/ A+ r# z9 P. e7 }6 }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) ^& x2 o4 s7 T7 l) h; D+ e
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