|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 _+ t3 f, ]- X. r9 b4 e. O' G# _; V5 W
input mcasp_ahclkx,+ r0 \% \- n: b% q( L8 N
input mcasp_aclkx,, W5 s+ y m. j* T. x3 A
input axr0,
! o# {: z' j" P3 t6 Y. x& n1 Q
8 P& Y% p# c6 i5 coutput mcasp_afsr,7 _; Z! d4 z2 ^& D7 I' Q
output mcasp_ahclkr,* W# L$ ^7 `4 a7 t
output mcasp_aclkr,* F: r8 N) c+ l" ^ b9 T2 y
output axr1,
& T. N( \1 }% r/ m assign mcasp_afsr = mcasp_afsx;+ a1 l) Y* Q" f) o4 z8 w; M
assign mcasp_aclkr = mcasp_aclkx;/ f) |$ `- y, d5 ~# E
assign mcasp_ahclkr = mcasp_ahclkx;' l4 x7 }3 ` F
assign axr1 = axr0;
" r& B L! D2 r' U- V: C
% P) w! y; y9 ~9 I. p. \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' D3 {5 P' Y3 [, B& B2 R, bstatic void McASPI2SConfigure(void)2 p0 t# ]) Q3 T5 A# v4 ?
{; ]% i. e- |2 Q, x2 r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 t+ D0 \6 ~0 Q9 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
w- C6 f* {$ C/ g KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); g- }8 }) P; p& W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# S: _+ P4 F1 `% B7 UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, F' P I; v5 u" R1 k' h
MCASP_RX_MODE_DMA);
2 }/ E2 f) d# {6 e6 s4 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 X; i# X% ? k( f$ A: \0 y8 l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, E/ b' P0 u5 C, b- WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' w5 u+ c& ?% |$ rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ |5 g# p$ K! c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" ^9 H @. {1 Q# B1 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 M' O m* B$ I v1 v) hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' y7 h$ v+ r6 P7 w; R+ j D- oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( f* D3 [( [- _1 R; I( {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
J8 F+ h5 D6 z9 s* ~0 |0x00, 0xFF); /* configure the clock for transmitter */
/ p% z: M5 j; S* CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- @/ C4 D# ~8 _7 }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 f. E2 s: @" m/ {! W7 n; R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 u* f2 n4 L) M0 j* I+ y
0x00, 0xFF);- ]4 {% Q8 S9 \; A* `! ^0 |( h
" S7 J9 ~ S% H" N7 ]/ V
/* Enable synchronization of RX and TX sections */
, P9 Q5 D2 D. `8 b6 b, j& ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ l) i" Z# W, pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 u& j" I/ \( a4 @0 K xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: }. I8 b1 X% Q6 g% m
** Set the serializers, Currently only one serializer is set as
u& p& V+ s& ?: I% c* h** transmitter and one serializer as receiver.
1 A, S! x' Y2 u7 c8 @# l4 o*/
2 Y+ F0 j* @; F' lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: ?/ L& j- w. A/ w* o$ W8 D5 u) W$ x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 N9 Z. ]; K" ?4 q& H4 X" {! l
** Configure the McASP pins
2 Y& Q$ f7 R: m% H( P2 P8 Q. \** Input - Frame Sync, Clock and Serializer Rx
6 F% [9 R9 {7 N, ~2 n, K# G- d1 `** Output - Serializer Tx is connected to the input of the codec & e- u' V' w# h3 @: C8 t$ Z
*/ h7 o: Q t; }) q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 y! `; F% _* E( h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" y- A( F. L; A/ l2 jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 l/ s6 B5 u# W/ F; I9 o5 p
| MCASP_PIN_ACLKX
) K& [8 L6 G- I4 y0 u2 z| MCASP_PIN_AHCLKX
, p8 ^* ]2 u$ L* N7 b: \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 V& x# l. F9 @/ O/ ]' v# Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* L, E. }5 v. ~, r1 |* k| MCASP_TX_CLKFAIL & E ]( T7 a% Y+ P2 S
| MCASP_TX_SYNCERROR+ G# c+ ^4 l& T1 e0 h( z- q. E. o! ^
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 o2 r2 g' V& {8 V) `* c# p
| MCASP_RX_CLKFAIL. D+ f0 {; @( b* p
| MCASP_RX_SYNCERROR
- U! V' u+ A, y+ W4 A: i% E| MCASP_RX_OVERRUN);% G6 _, {; q" E; Q7 F$ v
} static void I2SDataTxRxActivate(void)
# I6 M2 x! t; W, ]: H& {+ [% _# E{
6 _% Q4 t/ v8 l/* Start the clocks */
' y8 e+ i$ H0 n4 R% C/ VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% l9 K1 V: u4 ^& G6 w8 `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 T r. U( T6 y5 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* ?* F R0 ?, {" D( M
EDMA3_TRIG_MODE_EVENT);( b @/ i Y% R1 z4 O- ^" J. t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 Y9 u1 l( c3 E. MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 E, J* ~2 u' \5 B- g( Y$ H# dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" O. w1 T1 a1 s# y. @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 E5 Z3 D5 `4 n; L7 l2 a0 k# f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. p# {3 h; m% Y! zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& v! q# G8 s1 t, O% L: GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* V* n& z2 P5 U4 _% |2 a" j, a} ; b7 I# ?" Z# v& w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
9 R' y3 P5 R. m' n |