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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, r4 A) b" [" g
input mcasp_ahclkx,
1 m, U2 U# Y! O5 b' Ninput mcasp_aclkx,
$ }$ \4 F; n$ O% jinput axr0,
/ {5 k1 s/ [# ^3 g4 B9 U) [" a/ e2 G% Z5 m3 s
output mcasp_afsr,
7 N* j, W2 ~* u' D w+ F W- Woutput mcasp_ahclkr,* W- l, `9 a5 e% _6 g5 h
output mcasp_aclkr,2 n0 Q5 L1 E2 q1 K4 m8 A
output axr1,8 @0 s; T {% I2 i3 S
assign mcasp_afsr = mcasp_afsx;
7 M+ ^! R n% N7 t! Kassign mcasp_aclkr = mcasp_aclkx;
- u7 K. `, g; w0 uassign mcasp_ahclkr = mcasp_ahclkx;' W1 w3 y- n( i- f$ E" Y9 ?8 V
assign axr1 = axr0;
1 j( [, p. l* D) j2 R
. x0 Y- h; X6 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % J% ~% `) D3 y- Z; q" p
static void McASPI2SConfigure(void)
: t: Y* ~ \; [; G% I* V- X{
0 o* |( o! U+ MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 ]! k) }* |! c- ~& G! S: r: t; p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 s) S, J- c2 `. K6 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' K1 k! C# [: q$ D: }+ c \7 {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 m8 y& k k# \6 O, w; R/ @6 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ O; Z2 t' p# t& M: vMCASP_RX_MODE_DMA);
1 E& g9 _# k: _, |5 {5 JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 \! z& v7 q& C4 L" W/ X+ b3 d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ o/ I' h# d5 ]$ f5 V- fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 p! W4 {0 L0 Z$ K- n Q) JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( h& ]6 g y) S1 G4 J0 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! ]5 d0 T/ x2 p. m( I' G' vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! f$ c/ h, S0 l( J- R3 S( }0 R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 a" M" j! |. y, y9 L$ C/ N# UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# h; [/ X: }/ ^! p! u2 A0 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 g9 N, A; V1 ]* F' V
0x00, 0xFF); /* configure the clock for transmitter */6 u, j0 ?; Z, }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' @" T2 G* g: }& J% ?. X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 u5 ~, l; Y$ W2 R! ^; @% ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& g2 P3 e4 U$ \4 v/ b; w W1 Y8 P6 t m0x00, 0xFF);2 d/ z [7 U) n0 ~7 P, B: K
: J- K9 D& O# P% n7 g) H3 X8 U
/* Enable synchronization of RX and TX sections */ * T+ ~; [( A1 ] C6 Y4 h- u, g3 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
I# |+ F& i0 X9 T KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" t1 p) o9 s# I# L" m# z8 J0 V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' Y1 x! g2 U' o: R) ?' }7 s, @4 G
** Set the serializers, Currently only one serializer is set as( |2 ` B" y: V% [4 D: [5 W- j8 c
** transmitter and one serializer as receiver.
: |. |2 p1 b- X4 Q) C*/& ?- n5 G' c) S8 F, {+ v# P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 x0 U# q' D2 J: n& W4 H9 d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ ^* [5 x- S/ O+ x! C: ~** Configure the McASP pins 1 Y2 }* L$ k5 C
** Input - Frame Sync, Clock and Serializer Rx4 B9 X3 q2 |* ~ u6 V/ _
** Output - Serializer Tx is connected to the input of the codec
# n" x# `7 ^4 b }' u+ D Y3 N+ w*/% x& \# R2 X6 [" G: x/ D4 ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* [- K$ I/ _% g6 L6 [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& I6 u8 ]0 z+ s7 D& J" ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" U; Q& Z, H8 L% _| MCASP_PIN_ACLKX+ W' T8 x/ Y. s) b
| MCASP_PIN_AHCLKX- x+ ~ E2 {3 D* g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; G' p. [6 E3 P2 T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ v, O1 l& F* |6 K| MCASP_TX_CLKFAIL
0 r# h/ r4 h1 A$ Y0 G9 G% M0 r| MCASP_TX_SYNCERROR( r4 y* N) _" [- C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, g+ e7 Z/ e8 i| MCASP_RX_CLKFAIL
0 Z8 }; K3 o& x* }| MCASP_RX_SYNCERROR
d, K! c' D. V; p! ^| MCASP_RX_OVERRUN);& B" m! _" S F( g
} static void I2SDataTxRxActivate(void)) q: A0 t0 ?8 t. J1 V: N0 t
{
; p4 E* z4 e- o- Z1 S7 F" n# u/* Start the clocks */
5 z" s1 t N! t# e- y4 c+ B! KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 w$ S3 x, Y" }0 ~) DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, j+ j5 C1 X: B1 u3 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. v* x! v* |3 _( ?# W$ {8 v. xEDMA3_TRIG_MODE_EVENT);. y$ p2 I: O, N `! O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # ]% o8 c0 A- g/ o- \7 u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 Y' m; ^. F! \5 kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 `" I& r5 \) l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- ?% e. w% \$ Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' B1 Y0 Z9 s+ EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" Y4 Z7 Y$ U3 ^5 K. pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; c. Q' `8 B) z/ A! y
}
9 Y; K1 l9 s- N% c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. R/ |& J8 l U; u, y% Q
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