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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 ~! C( B. c$ F% a4 V% S8 N% Ninput mcasp_ahclkx,) F6 J# a, W9 }2 O% k) J; c
input mcasp_aclkx,
' P! g* s8 n! h3 g linput axr0,0 U! R" k; z9 p. r! f2 Z0 Z
9 `* O' a) f. a* B3 L
output mcasp_afsr,
2 P! U5 c( E% F; t+ doutput mcasp_ahclkr,) X0 l! z# F4 k6 S) H: [" B
output mcasp_aclkr,8 Z4 J7 m2 J5 H4 u) {
output axr1,# M9 ?. U2 L: C6 Z! G
assign mcasp_afsr = mcasp_afsx;6 h, u; T- ^) [+ r+ M
assign mcasp_aclkr = mcasp_aclkx;5 F4 X9 ^, A7 f! Y/ V. F9 B0 q
assign mcasp_ahclkr = mcasp_ahclkx;
. D3 q0 J9 p; x; j! s! m* Jassign axr1 = axr0;
6 e# l g0 y+ ~5 V
7 V' t6 g! d: y, x* G# R6 Q# N7 P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 U( ~' ]7 c. E5 s0 Dstatic void McASPI2SConfigure(void)
- t$ u4 D: X5 \. h1 x{
3 n! T G o0 w# J7 m; nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 o: ^3 o) F- X+ d5 m. c, x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 q- K$ N1 J/ i- _+ v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 |, O' Z0 ?% ?9 ?9 x% J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' M a% L1 n. \/ r# @, g7 h; E5 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ r) L4 [8 \0 Q7 R" {! ZMCASP_RX_MODE_DMA);
8 t' W m5 Q; M* I! G% zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. c, r& r* _# Q8 S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' ~( v- {! {1 p" v% t( [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- h: x6 ~0 k2 {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ l% B3 R' i; g0 B }& e/ y8 G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! H* a& A2 K! N4 w8 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. [4 w; ]5 `; N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. p% j$ C7 Q- L" b4 a8 P/ g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: b4 c/ C) A& L0 p1 w: y3 f ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# `; G8 r5 ^9 P! j& |8 h+ M% p
0x00, 0xFF); /* configure the clock for transmitter */
2 Y/ ]" Q; ?( JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& v( {/ L3 ~; t$ A. W: z- nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 K! g: q. R6 U a3 RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 o0 J& P( s+ L5 v0x00, 0xFF);% f6 Y; _* D! F& ^+ O/ c- p
7 V7 i9 u: s5 H! N+ C! P/* Enable synchronization of RX and TX sections */ E% l$ ?& S: C( _; [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ O4 o3 n+ E4 V) \+ ?, |- Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( m" p0 p6 S* d* P4 L: h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 [5 @# w; z! G( M
** Set the serializers, Currently only one serializer is set as
_* @( v6 {: P& u! n$ X# }** transmitter and one serializer as receiver.! D* h. O, Q" R' O; Y0 A
*/
8 ~% K+ y4 x5 t; Y! nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) `' s# H/ ^9 F5 i5 ]) DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 A: ]7 Q+ w" ^: c9 J
** Configure the McASP pins
% r1 E# h$ m1 o$ a** Input - Frame Sync, Clock and Serializer Rx" m' d, q# M1 J" R0 m
** Output - Serializer Tx is connected to the input of the codec # n' d' O1 _& O' E/ N# |$ U+ @/ C
*/ Q7 Q% o" t+ _. I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# D$ x4 u, A& H0 A# g9 w j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 R% k5 G& ^2 S9 J' `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ L/ a7 f( O( Z, @0 [+ w| MCASP_PIN_ACLKX
( Z' @, z$ f3 N' e: Q! D0 X| MCASP_PIN_AHCLKX% s; \$ h% [1 f4 C: u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ F I! H/ y) x* }0 N4 V# c0 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + q3 f& d* z1 ^0 M4 t- ?
| MCASP_TX_CLKFAIL
& z5 X, J4 ?- j; m" x/ i- C| MCASP_TX_SYNCERROR: U. z8 U& _/ C* @+ B$ D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 K7 r& l6 c& k6 m$ }| MCASP_RX_CLKFAIL
% }$ S. F- z7 P8 n4 v; v* ~| MCASP_RX_SYNCERROR 7 y. E- L1 m S
| MCASP_RX_OVERRUN);
5 _4 L* b: W1 Q4 T( M} static void I2SDataTxRxActivate(void)
+ A+ s# u5 W `, l- L{
( E% P a# [' c7 L. B N/* Start the clocks */
( Z* U9 V3 \7 T2 k- P3 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 B# n3 Y* P8 a [; P6 f5 L TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" ~3 {% w8 u7 m8 E4 l. u4 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( L t Z" t1 O4 ]7 WEDMA3_TRIG_MODE_EVENT);/ Z9 w' w, r$ s e( V" }. I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * w; L, j1 M; h# ~* k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 z/ `& b" b4 e8 I b4 `' ?# V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( z# o+ p5 q8 V X6 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 A! P! ~' f+ X' ] Z! ^0 Y+ W' G2 B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- o! h+ [/ j$ H5 FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
|, e3 v1 m8 P% H" j# x- s9 V1 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, U! U2 l$ z0 c7 J) {' u" n
}
; @ Z# W% W% W6 ^2 `+ F! w' [0 I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # t9 \# ~3 I4 B, H4 K6 M; z) k
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