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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 k' D* e5 i0 Z8 ^" _2 L. o& g- K
input mcasp_ahclkx,
6 C6 @; r" t* D8 p$ u! A- l; h0 Ainput mcasp_aclkx,
2 [3 a4 C0 o# a8 ainput axr0,' d8 q9 m; l# S& \
0 z0 {" t( j0 ioutput mcasp_afsr,
/ A0 b! v- p' y! O- aoutput mcasp_ahclkr,4 i. f A. V; b1 z( }, m7 |, ^
output mcasp_aclkr,; [7 k& c( R0 M4 ^& J% T j
output axr1,4 @0 C% v6 o/ T3 q) ]- K- d
assign mcasp_afsr = mcasp_afsx;
4 d9 |2 J' F. |! \assign mcasp_aclkr = mcasp_aclkx;
! `. `& }+ C1 b( F Passign mcasp_ahclkr = mcasp_ahclkx;
! ^9 z, q8 y+ X' Vassign axr1 = axr0;
/ X& t K8 s2 Z7 @: m. d7 A5 I% u; r1 T2 R% `! F% R$ \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 P7 w, B1 Y- e# rstatic void McASPI2SConfigure(void)1 O e% w! x& j' a' O" u
{0 ?* ]4 Z( L4 Q* j& x* I2 S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& x+ E% Q* L) i5 M3 ?" M7 bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* F* N: u1 C" a( d& q u( c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* a( ~6 Q2 g8 P" \8 g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% b# B9 c# a* u# k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 f* ^ e+ c0 z" f# o& d ~MCASP_RX_MODE_DMA);4 D" ?' C; w/ q/ ^! Q# W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( r6 p& u2 I8 s3 E, {. D: R+ b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# C4 |7 N N3 {, i- y. {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( m9 L8 x$ w4 Q/ l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 d: X8 N, B7 e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # h4 j, ^( J5 E# T. g2 g* R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 G N; r( A" H/ X" [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" F) i6 ]5 s" o; c5 q- V. D0 ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( m# I$ |! g$ i; n" H+ H1 u# G3 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' A! w/ j' y: M) q* j0x00, 0xFF); /* configure the clock for transmitter */
) X( j# z. \& n9 D7 h7 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! S- R6 l1 t% ~2 q* I- p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 ~6 g* ]6 u! v/ vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 Y- `# A- r* Q6 b3 w
0x00, 0xFF);) z2 k, U8 y0 [$ I
! R7 {. H1 Y, p/* Enable synchronization of RX and TX sections */ 7 [' x: W- f' \6 P+ M3 H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 T) i8 c+ P/ [7 }6 }" K* u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" u' _, Y1 [* x: X3 h- J. [. qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ g7 e Q/ ^& z+ |- m* F** Set the serializers, Currently only one serializer is set as
; l3 R$ Y% B. Z5 x: f( a! O" y** transmitter and one serializer as receiver.+ y' D# h: \* \: s9 G l4 ~2 C: Y
*/
* d. b* P- K: y0 ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
o4 O, `$ \" W. @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 r8 o1 P# Z$ _5 j** Configure the McASP pins
. p+ Q+ f% O5 Z' A8 w' U2 H/ R" V** Input - Frame Sync, Clock and Serializer Rx) z0 e" c* D% C
** Output - Serializer Tx is connected to the input of the codec ( T5 b2 G/ }! F2 q
*/9 e9 m7 `2 x! D+ q6 |! ]9 U' n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% l( K; W {; m3 w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
A+ _% \% d$ |! x( }' q* LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( Q+ v! B" Z1 W0 C| MCASP_PIN_ACLKX
8 b8 N5 q- m4 R6 [7 b \| MCASP_PIN_AHCLKX$ t5 n! }3 `- m/ K' @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- a" E$ Y$ v) T$ j6 g A' m' N, n: l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 I1 l" F% A; Q" P- j4 ^) R
| MCASP_TX_CLKFAIL $ i ^3 k2 B! X7 j
| MCASP_TX_SYNCERROR# o5 i- y5 g9 k: s0 J' D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( _$ u9 f1 I9 l0 {; i; ^* e% G| MCASP_RX_CLKFAIL
8 i! L" {/ ~ @| MCASP_RX_SYNCERROR
# n* O1 ?9 G$ @| MCASP_RX_OVERRUN);
B5 t# Z* { O4 a5 n2 \8 }} static void I2SDataTxRxActivate(void)5 N, j* E8 N0 C& y
{; X5 S$ Y! k1 Z/ m `
/* Start the clocks */% M6 F0 f ?1 q# A* U6 e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# p r0 t/ d' o* Q$ Z" T; g7 ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& ^& Q( x8 z; S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. v9 `; U8 g% lEDMA3_TRIG_MODE_EVENT);
: K6 j7 l: R8 S9 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 m' Y1 L# O7 D! P# y/ z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* O3 H4 o. w/ j6 R3 F: g" ^3 JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
s6 g q! ]3 \, O2 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" T0 e R) {6 Q# K; C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 q) u+ |# _' A3 w0 \) w- `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ Q1 W" p3 I3 {; ^& t0 ?+ ~/ qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( L3 k; t2 I5 h
}
9 x* C: p' A+ k/ }. @9 ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % k+ v: ~. p1 c8 y2 M+ [, v
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