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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' Q8 N- q. d7 R6 f0 xinput mcasp_ahclkx,
& O/ R4 ^( j# p+ Dinput mcasp_aclkx,
8 n. f5 r( v" b. w5 ]& Q* minput axr0,
# e- \. G5 ]1 f2 i; r0 J4 Q# M& @. ?5 S
output mcasp_afsr,
& G3 j+ c: D) G: s1 z I9 Z9 koutput mcasp_ahclkr,
) X, M" l* {( v9 j' |output mcasp_aclkr,9 k5 f/ {. _5 E# H* B1 G+ \& A
output axr1,- s9 [$ B% J5 q$ u0 F
assign mcasp_afsr = mcasp_afsx;
9 j9 S9 |+ [# g9 D% ~9 f0 @! cassign mcasp_aclkr = mcasp_aclkx;% D$ N$ u; Q$ h% i
assign mcasp_ahclkr = mcasp_ahclkx;' ~ Y4 U% }" C
assign axr1 = axr0; " Y9 Z. s& M+ T8 J, V5 F& J/ g# R2 m) n
- ^3 r0 m5 r, e7 k2 x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 R* V( L6 Y: Y( k& A; s! Gstatic void McASPI2SConfigure(void)
& C+ k0 b& O& U- u+ G* s{! A3 ?/ ]& o5 ]# w3 B/ Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* L, U& n. e' p6 n7 l) R: P. F. T# GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ Z, k% l$ n' wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: R/ W$ n' V: fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& i1 k* B9 `) [0 }+ }, lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" k: D1 N2 G. q5 T% t7 A/ Q' t* ]MCASP_RX_MODE_DMA);4 ]: R6 N m, h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. V8 i4 ~8 V$ {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% c5 J0 t0 t3 N4 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# W5 u* x, ~6 ]. N4 fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 H& I+ t. @& W) B6 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 J z0 d. E- W3 M3 @) | y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# m' b |) L6 x, I2 P& MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* ^. D w1 z1 _. h" [0 [: PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , g" j6 H' Z) J4 D, [+ o+ w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 Z; }. g3 O0 Q( Z' `( p# ~0x00, 0xFF); /* configure the clock for transmitter */5 S% }9 i0 K6 t2 {9 D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# A+ S7 @( y: L$ Q# b' l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : ?; R1 i( r. B" r G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 _4 w1 {# J0 }* O# `# Z/ d3 a7 z
0x00, 0xFF);$ y0 }1 H m; a' W3 \
! {3 m$ u9 e6 ~7 }7 ?; G/* Enable synchronization of RX and TX sections */ # q- m: @" j0 @3 B& \! t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. m6 K- q B6 E2 J/ l( |+ A4 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. j9 @. C9 Q& N0 n8 T6 UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 \! ?6 b0 W7 `
** Set the serializers, Currently only one serializer is set as. K# b f4 P$ R% p- F3 ?9 W
** transmitter and one serializer as receiver.
4 ?* T% `! W9 j8 ~, y: \4 k' D*/
0 U+ b& B; _, R, N' lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, k: k6 {1 Q5 lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 k+ e( t& p. h1 s
** Configure the McASP pins 1 w# W! p8 S, u5 [
** Input - Frame Sync, Clock and Serializer Rx$ x) f, C: D: ]6 g8 w: {
** Output - Serializer Tx is connected to the input of the codec ; Z2 |3 Q G' f3 _* U7 ^8 {
*/5 [% w( l2 V- c# e9 }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) C6 c/ Y2 g$ V# `" R2 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, Z/ m$ \# X. l# z- ?0 }' V# TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ P$ }, N% g+ _; j| MCASP_PIN_ACLKX' }0 X9 @: [6 D9 e5 }) }
| MCASP_PIN_AHCLKX* w+ t$ y; w# U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ?$ k& h% M2 f b$ i" U" f, D# IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % K6 \: D, ^1 m
| MCASP_TX_CLKFAIL
" E1 p: H; U1 k6 ^| MCASP_TX_SYNCERROR
) ?7 i% Z; V2 A) g3 ?, J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
~; @# g6 V. G: L| MCASP_RX_CLKFAIL
0 A" C0 h! K9 G( c4 K& W# A) U) ?7 A| MCASP_RX_SYNCERROR 5 `2 | \6 c* I7 x; K' e, N
| MCASP_RX_OVERRUN);' q" a: h' |2 _) d7 U1 ^2 |3 ]7 G: _
} static void I2SDataTxRxActivate(void)
+ X/ f- E6 g0 I6 q4 s{
0 w+ M \( j, [1 [; _/* Start the clocks */
4 a5 W: o4 S. H" [' x3 f. A1 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) u2 d5 y2 o, oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 r" y+ k+ g6 G( Z8 F8 w3 V) UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 }3 T2 T" ^+ S+ `' y1 cEDMA3_TRIG_MODE_EVENT);% \+ S( S( e1 d& i* S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 N: F. U2 `8 g; [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 K: O1 S/ g/ l) O/ `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! {1 r$ `# q/ c K1 S$ V0 c) @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 C% N. v9 f" t0 d, P2 J( Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; h1 @+ @9 t$ D. j2 n; w0 xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" ]# J, A+ m" o+ F3 p; H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 P4 Y' C" E6 ]
} * Z( o* a8 C% h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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