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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 v; ^+ `: Z4 x5 m1 X7 N: i9 O+ tinput mcasp_ahclkx,
9 E$ A# L( B6 G# t: Cinput mcasp_aclkx,
6 y2 q2 q# a) P2 K' {- J' \8 ^; N' Ginput axr0,- i- J9 q( e0 L% ?) `( E
5 m7 Y9 B/ [; G W% A" toutput mcasp_afsr,) S+ m% K, G) ]) _
output mcasp_ahclkr,0 v" c+ q8 M, s6 F5 W
output mcasp_aclkr,5 M( A; Q9 W+ P- E) f2 r, l: @
output axr1,4 m8 i* s" j+ [; k: k/ z a
assign mcasp_afsr = mcasp_afsx;
' F; V; ^- `7 {assign mcasp_aclkr = mcasp_aclkx;
$ C' b7 S3 E& x" L8 K* \7 ]assign mcasp_ahclkr = mcasp_ahclkx;
: @5 J; `0 X$ F, o; _+ H9 Iassign axr1 = axr0;
1 c4 U( Z9 E4 B& Q T
3 n% F% T" q$ O" s5 c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 l9 C, t( l: N8 m; l9 sstatic void McASPI2SConfigure(void)# _" m" D6 {5 l/ `7 j, t
{
9 f, y5 o3 C% ^5 t7 Q& W3 W, nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 C+ t! Q3 Y" G, p& U jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 [1 H, U) x: Z1 `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! u- S* X+ k0 P* F1 X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ u# T7 W. W$ X) P: C2 @( }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# T: Y1 c9 o! I2 bMCASP_RX_MODE_DMA);
! ?9 \; k: D! }; P* E, I$ dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 s M3 Q2 D9 b2 DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, p# |$ t+ F2 t3 O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' U% x, p4 ^3 Z$ m5 o- v/ r BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 i! O/ R x1 |5 L/ Y1 n& |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! a# h0 n) `" `$ y' V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- D p: ^& ~) |; t" M& Z' yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); K) B" {, r+ c& h$ i- P8 V7 A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); V) T1 n4 D) P' y7 L( [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 f U) N4 ?; y O0x00, 0xFF); /* configure the clock for transmitter */+ E/ ~) C6 y7 E8 g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) h3 T+ z8 E1 g1 ]' j" e cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) O5 i' f+ L4 l; BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 Q) K$ m% }8 }% U3 E: E0 W+ |0x00, 0xFF);* h" B- k* V$ h: D/ V' d
8 B: {9 r4 [: N
/* Enable synchronization of RX and TX sections */ 9 m3 p% @4 {) ^8 n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" l7 r+ Y' n9 J- |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& s5 Q9 ^- J" ^8 J' Q4 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! ?2 x, a& d/ M/ ^$ j* u( y
** Set the serializers, Currently only one serializer is set as D- A* M1 C K* u9 [: m
** transmitter and one serializer as receiver.* p3 x' Y) w0 t1 Y& j$ ]3 _; N/ p
*/
2 o) r$ F! u& r* O1 HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 w- }5 k- G" h) P# t0 S+ L$ f: YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" W7 A( u6 ?% L+ D
** Configure the McASP pins 2 |1 B+ u' P n" T% y
** Input - Frame Sync, Clock and Serializer Rx
0 I% U; d! a2 {7 [. K** Output - Serializer Tx is connected to the input of the codec 5 t0 W: H$ P: B# B7 o# J/ i
*/- s) I5 o' E/ g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 q4 y& Z: p4 ]8 dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 Q, H% E2 e0 j5 z5 G* x5 K% PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 D y# W, @: t$ q. J/ ~
| MCASP_PIN_ACLKX; X+ k# `7 b3 m- J( O2 E* W: m( Q
| MCASP_PIN_AHCLKX
0 e$ E0 N9 w# Z. H& A; P4 q! X) }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: g5 K; G! y- a/ r2 U# c, m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 o1 S! J" R6 g' |
| MCASP_TX_CLKFAIL 7 l, R) H% K. D& W* U4 A: Q
| MCASP_TX_SYNCERROR2 H0 b! @. \+ k- G' E; @+ p! p: G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * O- O6 D* G0 c$ F' B
| MCASP_RX_CLKFAIL
: K6 l2 O- [2 C# {' d1 m| MCASP_RX_SYNCERROR & ~7 T# g0 y5 \3 c3 u5 D
| MCASP_RX_OVERRUN);8 F, w; s. H3 b4 m
} static void I2SDataTxRxActivate(void)
) b6 g ^& v9 a- f{) @- w& s: U1 R' N7 G% c8 r
/* Start the clocks */
. Z) t& {8 u* o* G( zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 {: R: t6 T5 c: J0 ? w. u4 k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 p9 |. P0 { e' mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( ~6 m. X( P) R o7 p
EDMA3_TRIG_MODE_EVENT);
|" P: Q/ w6 t& b( j0 REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + \) ]8 o* a( m! Z! @! r, A: X% b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 X: b$ K/ n1 i1 ?" h8 e4 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' E; m' o) X! N$ F+ T8 S2 I" gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; m, Q+ F0 }9 R6 m6 V- W' q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 }( ?4 w# C# u% z% C& ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! @0 f7 @9 ^; L3 k* |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: q% F# r; O* a3 T1 y9 w}
3 Q: U) t8 e! q3 Y" R- q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( }" I+ [! b: y1 W& y- R
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