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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 h1 c; v$ p9 t6 h/ Z6 S7 C- Y, S/ Q0 J4 yinput mcasp_ahclkx, X0 J! A+ s `" \
input mcasp_aclkx,# I4 Z s) F4 \. W
input axr0,& o) o. K7 S7 M7 Q1 k- s
/ o& G B, ~4 L1 x: A8 xoutput mcasp_afsr,
& M' g4 ?3 ?( moutput mcasp_ahclkr,
& e h ]) ~. c toutput mcasp_aclkr,& P- ^' Y+ r6 S: e- e o5 H
output axr1,
$ q# k/ h- m# m8 e+ K- [3 ^ assign mcasp_afsr = mcasp_afsx;
@( J6 o9 S" E$ X2 b1 Wassign mcasp_aclkr = mcasp_aclkx;# _% u8 v/ [' q9 r6 M* a
assign mcasp_ahclkr = mcasp_ahclkx;- g! U; v" L7 H( j$ {# O: X7 z
assign axr1 = axr0;
) \% `9 s1 D) a% h6 }4 f
7 t# r' ^# B4 Y- e9 h9 Y' Y) Y* [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 [7 l2 V# j. j9 E9 d4 I- ~static void McASPI2SConfigure(void)$ p# m+ Z* {2 K. z# I" a$ S- G
{# {, L4 Y; \3 m4 o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. B* P; s: U: F/ p- E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 Q! ^" r3 x8 T: E! k2 \8 `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 T7 n! L+ i5 t) f# hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 n1 p. c9 r* ]9 J! YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- M. B7 D( F- `/ C
MCASP_RX_MODE_DMA);: h, k: u5 w9 C2 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 ~8 y/ y" o* YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) \" V1 D3 y' kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
I8 P% w9 K' m+ P- BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 d/ D. m: a1 K* E5 i# gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; n+ K+ i! L1 X4 S6 _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& Z/ Q% o0 u7 L& G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- J! T3 K/ S" B2 G$ yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + S9 z, h! A1 J: y4 Y- |7 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
z- E0 {; r$ V3 W% @' ?( n. t0x00, 0xFF); /* configure the clock for transmitter */7 x; R4 @7 W* g0 b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 }" r& M* q% J0 ~5 E% w& ^2 i5 S8 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 K6 g2 ?. `# j! ?/ |( oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ r4 q2 X7 ^; a6 U' D/ W& ]% T
0x00, 0xFF); ^$ j" Q k+ Y. Y9 L+ B
8 Z7 c2 n7 `. i; O6 g( O/ t6 ?. _+ g
/* Enable synchronization of RX and TX sections */
& ^9 {9 _' y2 g' W2 y6 K( YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 O% n8 `# @) V- J/ a: m5 U/ i xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( O0 @# L' N+ G4 X, y c% k3 n8 XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' Y% E* J6 d7 Y! @" d* D) ]9 x** Set the serializers, Currently only one serializer is set as
& i1 J/ z i/ f9 b** transmitter and one serializer as receiver.
2 S: z6 n* x9 R3 V: C& S$ s/ \7 r*/- S; x7 ^; [: ?8 V; b' t5 z6 A. J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, {% K3 U _ i: i! w3 U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- s6 R. a& t4 W* l6 Q** Configure the McASP pins
; p2 m. R. y4 i** Input - Frame Sync, Clock and Serializer Rx
/ O% T' S# o! }** Output - Serializer Tx is connected to the input of the codec 1 `( ]0 z6 b4 D! j w/ n
*/
, x$ S' k# L' k* i8 j6 Y8 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ Q5 A) b- H+ v, m& S. cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, l/ Z+ W2 _7 I# V5 F1 ]4 ]7 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' [3 T3 u n5 e3 ^# _
| MCASP_PIN_ACLKX# x! C) ?% N) N/ }6 y
| MCASP_PIN_AHCLKX
m, [* j8 t3 L# v" }6 v0 A3 d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 e5 C7 _, o% K5 P3 sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 |) E0 z! s' p% y8 d| MCASP_TX_CLKFAIL . D: f. O$ E; a4 n ?: b
| MCASP_TX_SYNCERROR
, n5 Z2 Q! B2 R6 v# n- z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. G7 b4 w" f" H3 v4 B| MCASP_RX_CLKFAIL
1 i% A ]0 N! v# E# a( v5 e| MCASP_RX_SYNCERROR
* E; h7 N M6 o' V0 G" J| MCASP_RX_OVERRUN);0 ~, [) k2 h3 I, m9 B
} static void I2SDataTxRxActivate(void); P+ i( R7 z. O
{
) b1 r9 T7 E. K1 a& x3 J, ?9 h& z/* Start the clocks */
" j1 D3 K) L: X! q; @, ]/ VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
V& _& T: i0 h$ `2 T+ wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- m( u: B/ g# iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 M( O' J2 A$ i. BEDMA3_TRIG_MODE_EVENT);
2 |4 t( F$ O; z) N* z3 Z) kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & m t' ~8 T+ ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 d' w7 m; A- lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 Q; b8 {; G) x5 t0 `" pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 Q2 H4 @" m" C4 Q& Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( P7 r, E( o2 r0 \( I+ S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ \$ d- a4 Z1 S) ^. R1 _, kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 {- C6 x4 J( @3 S# g8 g0 C
}
4 C! J, K( Z% F' ]) y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
c) m0 b$ ?. h/ Y* `1 q9 ^ |