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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 y! u2 v7 @) [8 a$ l' x) \
input mcasp_ahclkx,8 ?5 a2 i0 b* w) e) i L2 B
input mcasp_aclkx,$ [0 o9 J! L7 }
input axr0,
) I7 p! W2 B* _, C! ^" P+ Z8 W' h( J
output mcasp_afsr,
3 s% B6 F: j$ D: ?) |* A2 Ooutput mcasp_ahclkr,
, Z) N. p# W* b5 toutput mcasp_aclkr,! N# a+ w" Y) g9 j' z; m0 D
output axr1,' |" a0 V7 E E/ Q
assign mcasp_afsr = mcasp_afsx;- q9 j2 u6 ? t/ c |
assign mcasp_aclkr = mcasp_aclkx;0 t# d% W% l" `9 I+ l, G
assign mcasp_ahclkr = mcasp_ahclkx;# s2 ?. M* U) s+ C
assign axr1 = axr0; 1 j+ L( w6 R& s1 E q3 d9 h
1 d; B; {( C" c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" ]3 [; Q( k: D% X& _+ pstatic void McASPI2SConfigure(void)+ T7 j# B: i; o( Q2 G4 L. ^
{8 F" M7 R: }" T0 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( D8 Q; w: J3 [% s# TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 [# ` K# ?+ N- }) V& |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! Y: \; v! t ?6 LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- V2 ^8 r) m/ U( `2 O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) k. P2 V2 @0 c0 z: q. b
MCASP_RX_MODE_DMA);8 g# y/ l% N4 C$ \4 b x1 S1 \7 @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: Z( \1 E E n$ |2 `$ `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ f& k& x( k5 a' S+ t$ nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & q2 i5 J6 [' j. p# l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' R! ?, V% O6 FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) `7 r$ T6 h8 j5 q& x, FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 z9 q r" G: F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ \+ e. @* v) k+ Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 D. r5 O( H A+ [$ d$ BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) O/ \& H+ m6 ^% W% g2 X$ v1 L
0x00, 0xFF); /* configure the clock for transmitter */$ Y, ~" l0 n' l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# a) h$ ?% T1 L) JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 e" |- Z/ `0 aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. S" {1 Y) L$ J: a4 E" A
0x00, 0xFF);+ b7 z! e5 K- S% c/ r8 T9 H1 u
2 B2 g. S6 C. L1 g- ]9 P* \
/* Enable synchronization of RX and TX sections */
2 `- P2 |' V# X2 e/ n/ @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ {, \9 [5 V+ d6 K' D- oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 a) ]' s( o# U+ j% |2 UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" @- }, x; n% ]0 ?0 }** Set the serializers, Currently only one serializer is set as
% c$ q9 Q- N1 ~/ @** transmitter and one serializer as receiver.
( |. E' W9 A! a' q$ W3 a8 c*/
& K h/ O7 H% KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- X) D6 M. D$ O* p! A. O% @: C) W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ `- A5 K7 I2 q: l3 G' q* m
** Configure the McASP pins ' Y5 G- U, Y5 I( F9 Z6 s+ b$ k* o
** Input - Frame Sync, Clock and Serializer Rx
8 |7 U- {. J- ^. {& P' N% ]) U6 [** Output - Serializer Tx is connected to the input of the codec
4 H- ]# J+ e0 G3 O*/7 Z: r, u- f) T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 O9 m2 t7 o% `& Z# q' n8 @9 Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; I4 Y. Z4 A2 M- L1 T4 BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' m5 p9 p2 p2 u| MCASP_PIN_ACLKX7 u R, F/ j7 C2 }/ c% Y# Q- g
| MCASP_PIN_AHCLKX5 c# z8 ~ z2 R/ x7 l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 D B* t0 l& M4 F6 i: ?3 j; k7 N/ y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & c% t3 K4 |: Z% e. \* }1 e- m, X
| MCASP_TX_CLKFAIL
m1 p5 Z; Q- L8 c! j: M1 H| MCASP_TX_SYNCERROR
6 x8 P" n- ~4 m/ H2 f% u% ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 _ G, Y: a, z1 X| MCASP_RX_CLKFAIL
8 L2 _" {. G% J0 Q7 \; B. t1 U! b| MCASP_RX_SYNCERROR 0 Y6 _4 d+ h+ v( w9 S
| MCASP_RX_OVERRUN);
3 X6 B2 Q) W7 ?} static void I2SDataTxRxActivate(void)2 F& E! O2 z- S' \# K @2 D
{
7 _' m2 D8 y8 s/* Start the clocks */
9 {$ h! s, F: mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% J6 ~# z+ k' @6 m' L3 P/ _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// q. @1 b# \: @% g2 _' M, |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ N( @& K7 f4 V7 |6 [
EDMA3_TRIG_MODE_EVENT);% X" o7 [' E& R- g9 O0 K, |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 |. G* q$ |8 x/ S7 cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ J0 ?; @4 k( [" C4 I3 s: N i+ O$ FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. W2 W1 h% i+ ~/ _1 e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, ?0 Y8 I5 d! H; Z" }3 s; O5 F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: }8 h( d6 Y) S& E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 w- p0 U4 x# A1 c+ w; ]7 x* u* KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! N. g3 g9 D s; S) Y
} 6 b* t/ e3 |3 M* X- s2 d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 l4 ^5 K" T t' t" S' y& W+ r
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