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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: i. p; D+ J1 \. K4 D1 S0 ]0 Z& c
input mcasp_ahclkx,' s3 j, h* [! V" \
input mcasp_aclkx,
* K |0 E8 o' B$ G$ G' minput axr0,& }- t% ] O! j' s
1 B+ M3 e5 L6 h" l- Ooutput mcasp_afsr,
& R3 V! v0 w) h D: v7 ~" Noutput mcasp_ahclkr,
' f+ N: u! Q3 S! }output mcasp_aclkr,
% f: C- Y7 j% ooutput axr1,! j4 f0 f Z$ o- }
assign mcasp_afsr = mcasp_afsx;" O5 u- p& \5 e: t2 J
assign mcasp_aclkr = mcasp_aclkx;$ [# H/ O r5 `, o
assign mcasp_ahclkr = mcasp_ahclkx;
, f! D7 R! N5 k% d: l* Xassign axr1 = axr0;
( f5 Z3 B2 U# }$ t( r1 a' U' g+ i7 J3 ?7 @! P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . y8 Z5 y4 p. ?; A6 D: r
static void McASPI2SConfigure(void)2 a0 W3 f7 ]. k! ^' |8 W% r2 n( X
{5 u/ @* N+ i8 p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ S: P* V% p$ M( l( h' \* U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- ^% [* M' r# h) O( WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 f# E: X" J% @, {7 t+ \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; j& E& \% {/ E) X3 [9 cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# W' }- i( y v; l
MCASP_RX_MODE_DMA);5 x7 `- m! V& U, R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 A2 N; Z, L6 ]. Z; H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% H& w* `& ^' s+ @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 Y( Z2 a7 s/ B2 Z6 \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# B# u$ V* I8 {" h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 `: F2 O& e9 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ d/ | O5 k% v$ X4 U! R% H; c# F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 L- S6 W* I- P8 P& J2 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- h' H' q2 l$ r% X6 j9 e+ n& yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 |% a& d4 @' P. s
0x00, 0xFF); /* configure the clock for transmitter */" B; |7 Z- E( C/ a8 ] o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 v3 J( N$ K c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
p/ u) |3 x1 qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& v+ K5 l) d( ^( |6 P- e5 I+ a0x00, 0xFF);% S' _; o2 [& \7 s: X; P" N p
# d9 b U/ r. {& S7 p$ D1 a4 ]0 `/* Enable synchronization of RX and TX sections */ & `. T: E% O5 r; M# d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 J: M# u7 V% w9 P1 E! ^! W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! e* D/ f" M, ^; y! o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( A, } @3 f+ K w** Set the serializers, Currently only one serializer is set as% p' m/ u2 H7 a: y; b9 a m# q
** transmitter and one serializer as receiver.9 W. A0 \# p" Z! e0 O' m4 N, {
*/) z+ j* ]' t; e$ n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ P. ~# g* j W+ n/ {7 c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- v+ r. _7 d7 {# b7 u3 M** Configure the McASP pins ! _ G8 F4 U' G) t, q
** Input - Frame Sync, Clock and Serializer Rx
6 I6 h# d1 i; H) y& t** Output - Serializer Tx is connected to the input of the codec $ h, g! Z- _9 M P
*/
( b* f3 L8 N! v+ |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 M* ^3 `: l! `7 W. L" z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ @$ J3 f/ F1 r1 s {! D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ g1 o' O2 L9 l2 S' J| MCASP_PIN_ACLKX
0 y4 l4 H5 R" [) a6 _ f1 I" ]" J| MCASP_PIN_AHCLKX
, I& B& I( K& c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 x3 |4 g3 f) OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" [- P5 s5 c( g8 D4 W9 D| MCASP_TX_CLKFAIL
" s# y i- G/ v8 K8 m| MCASP_TX_SYNCERROR: b5 N* K" Y4 ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ \7 t; X* F; n: I5 M0 _# Z1 d9 J| MCASP_RX_CLKFAIL
& D0 [; m# C, t; a| MCASP_RX_SYNCERROR 0 V) `. g* I1 O$ ]+ X- I! q: ^
| MCASP_RX_OVERRUN);& o1 n- O) J* `* M. E* F" W
} static void I2SDataTxRxActivate(void)' F# L1 }" m% Y4 ?% h) B
{
1 J l! M9 }& E7 ?( O3 Q2 _/* Start the clocks */3 e( p( r# \& j8 m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: E* r4 D1 r. @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( U! o+ @' v% r6 c/ I9 [0 Y4 B9 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, Z+ f# ^8 L0 J& u2 F9 X, yEDMA3_TRIG_MODE_EVENT);
. j' F* z$ d, Q2 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 {, L! X+ P& K0 j7 XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 u, |3 p+ G+ Z' t8 t- P* E, u; AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 @, E2 ~7 [, x/ J- N; B6 C7 Q( d0 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 e2 N2 D' z+ g, ]( y( jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 e0 V; Z! e% {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# i: j. E0 v+ ]+ P( ~' Y( ]$ r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 B' H* S6 Q# \8 x: ?: O6 a& n}
2 s! h) s6 n. q9 g0 H. ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 G) h4 p4 z5 P7 w3 g
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