MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
" _3 y8 Z: l0 s9 Y$ S0 e6 H; ]input mcasp_ahclkx,
- u# F0 H0 R9 S  x7 G! ~input mcasp_aclkx,
input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
  S/ t' f# p4 aoutput mcasp_aclkr,
, {3 v% n+ T* G0 z+ K! X4 Zoutput axr1,

assign mcasp_afsr = mcasp_afsx;
" X9 k1 w) }! z7 B( I6 F6 Zassign mcasp_aclkr = mcasp_aclkx;
6 T1 }  r: e3 m" ?1 Wassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
: x' m7 b8 z7 U4 U+ h{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) A) O1 m2 D% e& x" ^McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# B+ j$ R! n% C/ M# hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
6 y4 P% M5 z- W5 }& iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
5 I! C8 U- d; VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ f: }* r3 K( JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ {$ u7 y1 l6 |. ]! s2 A! bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 r! X; J7 z: T, Y) k+ K7 EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 e( u; _, f: y$ zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; z0 E$ n6 C1 j2 Z1 F7 O+ j0x00, 0xFF);

/* configure the clock for transmitter */
" p3 [% F1 q2 W  K! L6 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, i& V: L1 T% n3 N- j7 ?" A5 UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. M# ~% u9 _0 u; P" kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! e! j' j4 k6 r  j. m! A0x00, 0xFF);
) R4 K2 z6 Z4 y! T
/* Enable synchronization of RX and TX sections */
# B/ V8 s2 H6 E( fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
# Y" n" }" v$ j: y  g* Q. O** Set the serializers, Currently only one serializer is set as
; B) b- O1 e$ D** transmitter and one serializer as receiver.
*/
& K# t3 u9 m8 XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
6 C9 j$ |4 k, G/ B4 B4 F** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
# L& G3 I+ |7 L7 K0 |1 h+ `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; V, p; G! Q) E! E1 L" {6 {% BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* i9 ?# G- x2 t7 T7 t0 \7 `. x9 |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 a2 W- }% R+ f9 D% h| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 L8 v# l: A2 M| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
( W; @7 M1 O6 G| MCASP_RX_SYNCERROR
4 X% n7 D( {; L| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
* J  ^) v8 v3 S' _1 p+ a{
1 h) S- ~+ n  L/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- z/ c, N9 F7 K6 t: z: q' a+ ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 N. x/ l# h; j0 r/ S, i1 nEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
2 r. d) d( i" ]; MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
% J3 q( r/ b9 Z9 Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( @6 N6 q+ E' U' a$ J# a0 }2 X1 k}

* u* m) N. K0 j" \

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

4 F5 J7 A. K  A# A