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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 C9 z Y1 a+ x( O% T9 Minput mcasp_ahclkx,4 c( y: O g2 Q9 `
input mcasp_aclkx,
0 [* M) o$ z% h6 g% sinput axr0,
+ L3 a( Y0 W9 M2 R, B! F% |% s; E; T* v4 B5 M
output mcasp_afsr,1 J) U* F& s2 A, t" j, ^
output mcasp_ahclkr,5 }2 p7 f2 W! T% _' l* z* v" v
output mcasp_aclkr,, K5 x7 q/ U& ^' t# H
output axr1,
. p+ X1 b2 Z9 {6 ~ assign mcasp_afsr = mcasp_afsx;
! u; t# g3 T* wassign mcasp_aclkr = mcasp_aclkx;
, Z8 d# ^8 m8 @/ k: hassign mcasp_ahclkr = mcasp_ahclkx;1 J* s; V7 I t. C. N0 {7 \! ^: t
assign axr1 = axr0; 7 q$ S& g, ~" @% [/ C- o
1 d1 d3 c. f7 Z& s4 g3 j! I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 r+ ? Z$ c# I$ ^static void McASPI2SConfigure(void)
' F2 b1 A9 g5 U{0 t0 d+ `% R8 x, |3 y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# i1 [! T( S0 {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, z4 w2 f% V; F5 |8 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ N( V9 c( C4 v' P! {0 H! s. U! gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 k1 M: D7 Z H' {$ z% t. [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ p1 V/ e& t* k, h; ?; H: f' e5 WMCASP_RX_MODE_DMA);
/ P* v: @6 B% m2 M) t4 d. e' _: Y& Y) uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% u. S. k) g% q4 t9 Q8 K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 b& m. {9 Q6 k5 l2 k! }' F: {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, t7 y$ V7 T# F8 r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 M8 F, _' w. p% {, h8 N* |) {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' A. [! _( |) f; g9 R/ x* V5 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& W) S, Y( R7 O4 t" T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" U$ p- A4 p$ E" h4 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 y, o) f2 [3 }/ {4 \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! S* Y5 w J8 ~6 x |
0x00, 0xFF); /* configure the clock for transmitter */: Y1 f0 B( E, N W1 H9 \6 w, z3 N$ m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 O6 E% ]* i; v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . U/ {; D; L v; Y4 E; `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- E; ]2 N8 x! A5 A8 l Y: R* Q
0x00, 0xFF);
. \- G6 B0 u% E" T }- C) ^" v1 L% Z9 i; }
/* Enable synchronization of RX and TX sections */
8 e( w8 ` E8 D) J- UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 {: I: E* w4 e* V3 kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' H7 _) y o0 Y5 S& o/ _* v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 w7 E4 k: o% R0 F5 s( p$ d+ Z& O** Set the serializers, Currently only one serializer is set as. x; p9 E# b, F ~5 y. I/ G C
** transmitter and one serializer as receiver.) h+ @1 v( u9 _9 B6 B
*/) u4 u+ P1 s0 g7 M' e; N; e9 H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& l# X. K+ t4 f% l0 G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 i1 E; d5 l' E* }- b9 @
** Configure the McASP pins $ h6 z+ \) V( i" j
** Input - Frame Sync, Clock and Serializer Rx
" j9 j) T# w! A; B** Output - Serializer Tx is connected to the input of the codec - @3 e$ L6 {# I1 j1 S! K& D
*/
1 \4 D7 u6 h3 ]7 r6 ^+ YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ I; S" j |" c8 OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: r1 ?$ x9 n' w$ Y& @. U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 e/ o' U4 c4 Y3 [) Q' W
| MCASP_PIN_ACLKX) f P$ w0 p. F8 T
| MCASP_PIN_AHCLKX, l+ }4 n* V5 u4 f6 P. v3 ^2 X* \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: c2 T1 m0 p1 v$ i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" g2 e" p" ?; x3 @4 p4 F| MCASP_TX_CLKFAIL
. v( T9 o! n( s8 K: W| MCASP_TX_SYNCERROR
0 V# H1 ]. e7 |/ }7 c1 ^, F2 ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! o! O+ d; Y8 h4 A. S* A| MCASP_RX_CLKFAIL
# ^2 o' \4 J2 z# D* Q8 e2 q. i- F| MCASP_RX_SYNCERROR $ D6 G2 I( H9 J0 }
| MCASP_RX_OVERRUN);! z2 F0 w: ~" g
} static void I2SDataTxRxActivate(void)
1 w. [$ T: z! L: i4 m{
9 g: y9 @, y1 P0 c n/* Start the clocks */
1 d& _: G8 o6 N% G; ]# }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 N% H" {0 l$ r" v4 z1 ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# }4 o7 R6 J. J* W6 ^; x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 I' g3 ?/ J; bEDMA3_TRIG_MODE_EVENT);2 f3 t" V: R x. h% e& f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 @* v, m3 } D. T4 nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* u+ s9 n' w8 I9 d! xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. F& n5 r7 j1 j- v" VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( F! T+ \/ @: mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 Q6 d; K% o" o! R0 x; ?9 kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 U5 o! V, g: c- ]9 ~+ eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 ]" S# B& H3 j# ^) ~; P}
; p0 L4 K9 P5 I& e* B; D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 ]" R& a8 Z1 \3 A+ J
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