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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 Y: B: w$ I, `5 ~$ ]input mcasp_ahclkx,
8 |5 N* U* D3 ~input mcasp_aclkx,
: [3 }4 M3 ]! Hinput axr0,, R6 }( _8 ~" u& U
9 f7 p/ \+ Z' E+ Xoutput mcasp_afsr,
4 B. x* B' Z3 m6 t$ \# a, v& N% |output mcasp_ahclkr,7 i& h& t+ k& r, J. T
output mcasp_aclkr,' n8 z5 T+ p0 }! M% f
output axr1,- ]4 Q- x8 I m2 O E3 s) M0 r# e6 f
assign mcasp_afsr = mcasp_afsx;
' U+ n$ s3 A v0 h; ?5 f" X) Jassign mcasp_aclkr = mcasp_aclkx;6 w$ v r* {: ^
assign mcasp_ahclkr = mcasp_ahclkx;
$ F- v L0 L Vassign axr1 = axr0; 8 k; p G- Z7 m5 q2 N! h9 Z
/ T9 M: K9 P7 _) Z* o A) @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 D5 \) ?4 ? d& N- q% Mstatic void McASPI2SConfigure(void)
( C- M: V0 k+ C- g4 p# Q{. Y; Z2 N8 t6 ]& w* }, L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 b% A2 p$ c& D/ `, p% b. `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* K! i& E2 A/ a( Z' S1 x8 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 i; R- [4 P: x9 [( X4 g1 ~/ z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% U9 f) `& y9 O: S7 sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, f, M+ U5 T+ i. b
MCASP_RX_MODE_DMA);
+ ~+ t# v7 b" J3 K- v' Z4 A1 bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 G) n+ L0 `6 h/ _ KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 }0 ]: P/ g% \7 A1 `# mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! u, i# j! [9 C3 x" J3 f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 {6 m1 n1 m5 O3 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* I- L+ Z9 o0 \) nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, g( [5 _6 w* G, rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 k% ?( b- M' t8 P3 D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 O4 U4 a. o j6 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 ~/ A/ U& X( r4 u
0x00, 0xFF); /* configure the clock for transmitter */5 _$ r+ f- A( E# W' l( Z, B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 \- [( ? c9 y5 [! D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 K% \. }' [- @7 u% {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. w! x* b' V* V. e: P# i0x00, 0xFF);. s6 w8 O! B9 B5 Z0 O( b: `
; I7 c" V: J% G( q/* Enable synchronization of RX and TX sections */ : b! x3 v. Y9 e# S8 E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ ]. C0 k9 t& j6 z/ w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: l! [ n- [+ b$ V! KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 ]# T8 n8 y0 W) f/ S
** Set the serializers, Currently only one serializer is set as
' {7 i' ^$ {* X: M- Q( H8 [( h3 I** transmitter and one serializer as receiver.7 |9 N# \% V" Q+ B& \
*/, \$ `* ]& w3 S3 U9 N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 f+ r; p' n0 F; e& D% Y9 l$ i: H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( Z) t8 e9 q2 d+ V4 h2 {** Configure the McASP pins
j: H! _& b5 O** Input - Frame Sync, Clock and Serializer Rx# O. \* G- g' [# ^/ V' T
** Output - Serializer Tx is connected to the input of the codec % p. ~$ e- x, ]
*/
/ Y' W! ^2 V2 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! ?, ^6 g/ D$ J: DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ ]$ x) _0 F/ b1 t" H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ \$ E, x f6 W2 M! x P" v| MCASP_PIN_ACLKX; M( d. z# D1 i7 Q3 S" S7 E. k+ S
| MCASP_PIN_AHCLKX
! c/ B% ?9 `* [# u( E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' b! L; u2 V$ Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( g! E6 X2 g3 g4 f8 d7 h
| MCASP_TX_CLKFAIL / Q- E- K6 P6 T7 T V
| MCASP_TX_SYNCERROR
?$ I+ Z3 J5 ?- q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ c2 [7 H3 Z" J3 h! k" e$ t; t| MCASP_RX_CLKFAIL" e+ k6 s( b1 \# B9 W
| MCASP_RX_SYNCERROR , Z& K7 N) v7 _4 Q
| MCASP_RX_OVERRUN);3 R4 \$ j6 `4 Y
} static void I2SDataTxRxActivate(void)5 h$ v& N! u, o2 c5 |9 S% K5 s
{
* ~1 p7 x& w% J. [' M6 N8 y9 E/* Start the clocks */% F% T' N U0 C( b1 P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. P% B% j6 X9 q1 o& ]* CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( C2 k4 v, i$ v$ w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 M/ _" I4 ^% ZEDMA3_TRIG_MODE_EVENT);! J1 G4 u8 m: m9 R( {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' t4 W2 Q8 e$ s+ K, F) P& BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* e3 O% Z: q4 uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. n3 F. s9 I7 P; [0 o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. V2 D1 V. Y2 ?+ H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: H5 T% Z6 C/ ^# J. i% u" kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 |% n* c' y: X U3 b ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! a4 U- U, P0 A; P- C* B
}
/ D" U, P9 u6 l; P7 v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , d8 Y% ? }8 | m5 A' O
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