我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ W5 @% d1 F, E! _9 p: C! sinput mcasp_ahclkx,% a; Q0 m9 L3 u8 S1 V
input mcasp_aclkx,
# v/ B$ y) M& A1 oinput axr0,
8 M3 _( A* `$ y/ T2 w, A3 X" H0 j
output mcasp_afsr,
6 o2 p2 u1 k4 ^" P ?2 O7 k0 Moutput mcasp_ahclkr,
# Z$ w! L% C7 d! ]7 Voutput mcasp_aclkr,
# G9 }6 `3 z/ x+ M+ |output axr1,* c' g/ J8 n. s! O$ A
assign mcasp_afsr = mcasp_afsx;
$ _0 r8 {7 M* `# l+ `9 M3 fassign mcasp_aclkr = mcasp_aclkx;& I: R7 G2 ]1 l
assign mcasp_ahclkr = mcasp_ahclkx;' S1 a! B3 {( t
assign axr1 = axr0;
; z, q6 n+ I! ]# A7 w9 K( p
) t2 @: O P, X; r N* X, O$ R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! m: C" c+ U5 H, k$ tstatic void McASPI2SConfigure(void)
. J4 @/ q! F' G3 u. w{
4 Q, B- ^& L! E8 tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- A0 z9 @5 D3 T8 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- {2 S( K7 V1 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); S% Q# q- t _; @7 t8 [& C0 q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# h' b' d8 w+ m3 ]9 P4 G: W/ p9 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: t2 V- s; n2 W
MCASP_RX_MODE_DMA);
6 O) ?7 S J- z; c. _3 ` ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" c: u7 X! ?9 N1 r" I9 nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% G8 l& {( _; L6 Q! |& v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 c* x9 z2 F9 r0 OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( \- A( G3 [/ s/ qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % m1 x, v7 f5 I6 r4 g
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 g2 t$ u8 j, \& V/ a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 W6 M) |. `4 a$ E& Y2 J) iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
Q7 w1 c) e' K) Q% P! R8 v" P- ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( c& s& o/ ` i6 T2 ]0x00, 0xFF); /* configure the clock for transmitter */
7 u q/ k7 O. }* f7 NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 O1 Z8 E8 r6 e/ h7 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ M$ @, t! H7 N# j+ G; BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# {4 r% }+ [1 Z* V1 P6 i
0x00, 0xFF); s6 V/ z1 A& t
/ t& a* O1 c7 N* i; E( b. ^- w0 Z4 V/* Enable synchronization of RX and TX sections */ % M! N! u J& g- A# V7 k" _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 a% ~6 x/ h6 D$ N& w1 q: l$ d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ a7 G( ]5 E+ I# F% ?) YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) f) i- U! k; i- J3 B' s
** Set the serializers, Currently only one serializer is set as$ d. `" e' _9 a# A7 a, i; f
** transmitter and one serializer as receiver.! }, o& z3 f ^& n B' y
*/
9 ]. F1 m/ W0 O& D1 J" cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 ^1 ~. K5 ]9 C/ r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) [' X0 ]2 y; C9 ~ P% w: H
** Configure the McASP pins
0 s i! K- Z) j8 Y+ d2 r; z** Input - Frame Sync, Clock and Serializer Rx$ U4 v/ L4 h0 j$ d
** Output - Serializer Tx is connected to the input of the codec
4 c2 c' _1 h9 {- ~8 _*/. s8 D% {" U& Y: M) a" c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ j) Z$ h4 C+ dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 [8 S. l7 n. C0 f8 o# ^* Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ d9 _; ^( Q. R8 g9 ^: M3 C5 [| MCASP_PIN_ACLKX9 u) X: ]. ^) M. }5 m' K5 B
| MCASP_PIN_AHCLKX$ r1 V, v8 p/ x. p7 @" S2 W9 _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 M+ f0 [! b# n: ?" F. }% C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 W/ g! l: `4 v6 b| MCASP_TX_CLKFAIL 9 H6 e( w3 s7 [' y* w
| MCASP_TX_SYNCERROR
) F; J z1 N7 B! w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " v" l! J& n0 e7 T' ?5 O
| MCASP_RX_CLKFAIL
$ [$ E1 V4 u3 t, {| MCASP_RX_SYNCERROR
% Z0 n4 j2 ^6 i. I* ]; `| MCASP_RX_OVERRUN);
; c/ _' H; E% \} static void I2SDataTxRxActivate(void)2 E& b Z7 q9 C2 J7 F
{
4 J- Q" U$ f5 O2 c3 F2 e m G/* Start the clocks */
2 s" F: o" q8 i2 z2 EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! L- X8 J0 ~" l6 n+ w. ]" fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ E* |6 M* K$ j) f# }) `, FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: {! ~7 W. M" w6 o
EDMA3_TRIG_MODE_EVENT);* ]! c2 L0 l6 ?7 Q, S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % j( V. s2 x, Y2 I J* s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, t# z4 [* a, _7 n% B( ?. tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ M$ t+ w4 {8 q9 k& f% ?* EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
R; E: h: v5 L/ Y! Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ ?4 K; x1 l$ M2 D# Q. wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 n+ l- u' X$ UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& m! o' G* _1 u5 \7 [7 |) G}
6 I; x3 L* C2 P- r+ {; X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 P5 T/ J9 r% a' z) q8 A8 d* d
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