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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, Y; z! S! M1 W9 u; h1 w+ S' C* l
input mcasp_ahclkx,
: @5 Y& V# q _# Qinput mcasp_aclkx,
# x- [5 e ?& I3 {% w' Iinput axr0,
6 \( Z/ z$ W7 y9 \/ _" ^
; N4 w" ]& P( H+ o! c* o1 H" Ioutput mcasp_afsr,4 ^" L. W% x' z* e/ G: c/ O
output mcasp_ahclkr,5 y: w" A. U5 i
output mcasp_aclkr,
: S4 [' A a3 g: x$ xoutput axr1,/ k% g+ z* X Z0 d% ?) k- s
assign mcasp_afsr = mcasp_afsx;# F* e2 c; ^+ f6 D, n$ P% Y2 x0 ~" A
assign mcasp_aclkr = mcasp_aclkx;
+ I, Z: U/ c' x0 {$ u7 qassign mcasp_ahclkr = mcasp_ahclkx;9 o+ Y" J+ z% U' N0 X
assign axr1 = axr0; S. s5 o! h6 d4 X
! W* N6 s1 v7 q/ ? q. J. `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. d$ `) A& ^( }1 k8 p6 O* O8 wstatic void McASPI2SConfigure(void)$ q m+ S1 d" }3 e/ ~
{0 }' t9 U3 Q# ]3 c0 x; [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% L4 @6 G" n! \5 C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 f) h$ t' [8 wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 Z4 R7 h) K( ]% ?" j" zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: L; V0 u K) D5 {5 M2 oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' l$ _. Q* I$ K/ D- ?
MCASP_RX_MODE_DMA);
9 |% r- E! H& ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
U- X& B# |) J L; gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* Y) O4 I) q( s9 v$ u, r2 M$ t4 S* T' RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 \6 T# s1 L( q; hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, \0 [ M+ z' e V, Z. v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " e% Z9 s0 P9 x! o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" }9 |" R' |. [9 o3 Q; F3 oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* W7 X/ v" F# n: B hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); D0 Z' B ]. F! B0 ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, I, D9 m1 r; z( e/ ?0 W+ z
0x00, 0xFF); /* configure the clock for transmitter */
+ q- G2 ?) {+ {1 o9 YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* [+ T r* U$ W& _9 ~6 @( fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 R- i# ~. K7 r4 e, `9 h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 A! H* `8 X8 f0x00, 0xFF);3 Q3 c1 [4 v& {: j
3 P: E+ l& i) z2 j1 K
/* Enable synchronization of RX and TX sections */ ) T+ p8 e! @2 g* N# ^1 ^) q. o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 D) J, w4 `& N3 Y1 wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 Z5 g8 z! H2 m/ D7 R! j; hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 W$ C* m4 a( L: o4 R
** Set the serializers, Currently only one serializer is set as7 h' C! T) Q0 P1 L0 q
** transmitter and one serializer as receiver.
& t7 k# e. K7 T6 }*/% `$ m1 v0 v, [$ B! G' V- z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); T) i) Q" n& c( Z6 Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 Z5 q1 M# p4 n& Z: q! y0 p( n; M** Configure the McASP pins : R3 x& a* p6 v
** Input - Frame Sync, Clock and Serializer Rx
* T. E1 m# M9 Z9 w" F** Output - Serializer Tx is connected to the input of the codec 8 p* N L- J2 o% ]& ~- N% t
*/, a* T: g: e& z& {: x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 n- u2 y. ]& Y, @/ }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- E; {5 e+ ~( @) S. CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ {$ z' W9 R' b, I9 w: `' v
| MCASP_PIN_ACLKX6 a9 M- L2 |- R8 ]; G9 n
| MCASP_PIN_AHCLKX) t" w) T T5 q( q1 _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( l+ f9 _ J+ h, D |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 L6 ]* R& a. {9 R1 ?: m$ a
| MCASP_TX_CLKFAIL
: }1 o. Y. }$ z! I! ^" O| MCASP_TX_SYNCERROR
! P/ H3 R6 A( O, A3 H, || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! E) _( ^# v' r9 }| MCASP_RX_CLKFAIL7 M4 K# {2 @, ~5 q
| MCASP_RX_SYNCERROR
6 `% v+ ?5 B" G* g$ X| MCASP_RX_OVERRUN);
1 n, f. E( ]: K$ _' x: c5 M} static void I2SDataTxRxActivate(void). Q/ e5 p3 b+ n W+ h' ~8 p
{6 k }% @: R. Z
/* Start the clocks */
9 F! d# _) y: y! jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 c6 {. j2 Y5 y$ b _5 E GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 Z! \5 H0 T4 \5 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" {/ A4 m' l+ z4 C1 J! kEDMA3_TRIG_MODE_EVENT);5 P, w$ a# a6 V! s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% h' P( X6 b( t9 _5 ^2 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 _* s7 J3 r# X$ A1 Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 G1 e" u/ i8 E7 a7 v* ~, L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' }. Y, g) l' q$ Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" h7 A3 [+ T( @- |. c; V" JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. W6 L, s8 n% Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 U2 x5 f: o7 b! s1 h0 |/ l1 \
} & c: N9 j: y' g4 r4 \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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