|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# Y9 \, D5 B$ v, y/ [
input mcasp_ahclkx,; ?" q" ?" m1 d. `1 E$ H; y# U
input mcasp_aclkx,5 W1 C& A. V) O U. `% H
input axr0, v+ L! B, p% v5 K- r( U& V
$ @7 }* m# c8 ~6 v- X, o2 N+ @9 woutput mcasp_afsr,5 x) i8 v# e& S7 b
output mcasp_ahclkr,9 {( T9 c! T1 e- e0 C
output mcasp_aclkr,
1 [6 E1 l6 h6 L6 }! r: q Uoutput axr1,
0 ]2 |) I! X# F assign mcasp_afsr = mcasp_afsx;
% X) z% P6 i" m5 aassign mcasp_aclkr = mcasp_aclkx;2 P2 h! x/ n1 ^ Z* L0 I8 g% Y
assign mcasp_ahclkr = mcasp_ahclkx;
' b! L7 h3 d. V, ~. Y j- d0 passign axr1 = axr0;
6 L z4 [; F8 A# L* t. s% x# K8 i6 ^; A0 N; r( \6 d3 l& Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * b1 T% ], k1 R
static void McASPI2SConfigure(void)) g, F( J6 _/ I0 e) H
{
/ _# V& R7 l: H5 D g+ kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 I0 ^$ e7 J/ h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 V% U4 L, z8 C! B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% `7 u& \! k" J4 ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 L3 d2 B8 c# }1 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," E- E8 p1 }5 A. |8 g
MCASP_RX_MODE_DMA);
, a3 y: B" H: Q3 Q7 j0 A- sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
f4 K$ Q: ?. I/ ~+ E: l& j9 jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 S% U- u3 a$ ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& `+ s- U9 d2 z& l% k- u0 @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) O; P" `3 \ l: H e) P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 G c! T; k% h* i; q1 V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- f/ N0 M1 y; c+ K! ?" ]+ p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* _' P, r6 w& F% A- E2 m( n3 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & E3 P1 G+ T: p3 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! t9 [. G5 \: {% |
0x00, 0xFF); /* configure the clock for transmitter */
9 z5 u& U* u0 sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 n% M" z Q' |: G4 T4 I) H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( g2 Z' k' |$ o' }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. |! k7 ~$ Q+ V7 y+ M* [, g B0x00, 0xFF);
; h5 ?; ~2 A: T/ G E* E! v' ?# `' u r# c
/* Enable synchronization of RX and TX sections */
9 ^7 T$ T) d% A# v* D& JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ q3 Q/ @; {, C: ^8 b8 A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! u+ H" y1 J* T, V( I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& F1 r/ S9 m% `. b7 X* k
** Set the serializers, Currently only one serializer is set as
$ ?6 o* v- {3 u1 z" E** transmitter and one serializer as receiver.# z8 @: @! G6 Q2 q0 s# t$ t& T
*/
4 I. Z; E' {) c7 c rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' ~1 O' w' e* DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& o# ^3 {' d: H** Configure the McASP pins
+ N- x" D& W+ s8 ^$ e0 y** Input - Frame Sync, Clock and Serializer Rx2 U g) A: g# r# B+ G
** Output - Serializer Tx is connected to the input of the codec ) m2 V+ H( @4 H9 U
*/* f7 H2 T4 W# L6 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 J6 ]+ t* O* c% K) D2 O% d0 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* I+ _# c7 z& s5 _: |) \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 ~' H$ A1 _! s u
| MCASP_PIN_ACLKX
- Q! Q* s+ w' j$ Z" R| MCASP_PIN_AHCLKX; A( @' c. L2 g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, Y- P7 B( j3 ~1 K8 hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 P+ O- u2 Q) q! Z" @% [/ Y4 B( q2 m; l+ A| MCASP_TX_CLKFAIL
5 [/ U5 q& o4 Q& T4 S- [4 ~1 N| MCASP_TX_SYNCERROR4 {" ?: a; D( r4 F! [$ D3 h/ S7 q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* A" l Z$ D7 b; q3 r| MCASP_RX_CLKFAIL E& \2 H- S7 c+ A
| MCASP_RX_SYNCERROR / g9 k( C7 Q+ }) O2 a) c
| MCASP_RX_OVERRUN);
9 [$ m6 g6 a4 i: E} static void I2SDataTxRxActivate(void)3 I& N) S; C5 d; p% x
{
( |( o" u) K8 v Y: k( B6 g; b8 l% |/* Start the clocks */" g8 _% D# C' `6 R# x/ P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 V' h: y- G1 D% M$ o0 @7 a$ }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ P8 g. f ^1 B! V' `1 \, q4 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 C) t3 m! Y6 x9 x* ~EDMA3_TRIG_MODE_EVENT);
; W& C2 m/ g% S; @ h2 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + {' d, o( I9 q& }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& Y1 N7 @) @6 C) K. Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% K. V8 x( h$ [* M4 N! jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# c- a8 ?: H7 \1 L9 K) R5 r0 Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 _5 ]4 L- n) ]9 P* jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 _8 V% z6 u7 F& S* g8 \' E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 U+ W* l4 L: e
}
# j/ s! d1 F6 D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 G6 j/ ^; C0 P1 P# E; C
|