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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 i4 b) a. V+ @: _0 R. K3 ~
input mcasp_ahclkx,
: X, I( Z' g m0 j' l$ a' Xinput mcasp_aclkx,. c- L1 E$ W: B' J) [
input axr0,) ^+ n* K' M$ \+ ]. b: \( E7 e3 [6 W/ i
& y. W% I% h! p( Z3 A
output mcasp_afsr,/ d8 G) B2 b0 O. W! _; F+ i
output mcasp_ahclkr, Q$ v, k; y$ i3 @
output mcasp_aclkr,! \0 ^9 \4 _% ^: D3 a
output axr1,
' x: [6 t( l C assign mcasp_afsr = mcasp_afsx;
8 Z* c7 ^7 @, t( R: n, \assign mcasp_aclkr = mcasp_aclkx;4 L N. a; ?$ b7 O! L5 C
assign mcasp_ahclkr = mcasp_ahclkx;- O' c0 z d4 _/ q0 Y" \, |
assign axr1 = axr0;
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* v; t. |+ e* V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % i% t; a1 L0 _5 a2 r
static void McASPI2SConfigure(void)! R6 P+ p7 x; i* p
{
: [3 ?9 E; V+ Q: zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 L, E7 o4 d) n4 w( ~$ w" ~' L& wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, h5 O4 h, X& z1 E [! v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' _7 ]' A0 o; _5 ?. `) R! h& I1 K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) V7 H( b( T4 K" uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 v* H7 I1 A; g- p0 c
MCASP_RX_MODE_DMA);
% G7 F$ s# ~/ E0 Q, c* tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ s" H! T/ b, B: T$ q {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 h# h7 S% i/ N' t2 ? }) d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 T1 i8 O, H( Q$ A! nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 n' N. W5 k) ^2 g7 i% z2 `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: Q. p& T; C7 E8 i9 Z0 c& {4 [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) ~4 J( q( t0 x5 h/ x, p2 G" L& OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& r9 ~9 _& H% m+ K; Y9 x" }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 H6 m4 d7 ]6 S$ @+ FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. u+ A* h' ~6 k
0x00, 0xFF); /* configure the clock for transmitter */
$ H# c9 N( G( VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. D' U' `/ x; AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! w! r0 h# k8 `+ N! NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," ?! n9 l6 b) A8 k* I! X
0x00, 0xFF);# I* f0 W# ^ O* j; J7 Z; K
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/* Enable synchronization of RX and TX sections */
/ F: F9 D. q2 c; qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& Y6 S+ Z' Y _, Z# g. ^% D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 ^1 u J$ p& @* QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 L$ Q2 f) L0 I; T5 h** Set the serializers, Currently only one serializer is set as, [: l/ C8 z. j3 J) `6 ^" |% w
** transmitter and one serializer as receiver.1 c7 F" o% b2 Z; V" c) {
*/
' |# G! q. R5 D& H+ l( j+ IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 @; ^, j) f' @9 X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 T" @' R0 d p$ p5 u* U** Configure the McASP pins
& t% ^* E' X7 y) u** Input - Frame Sync, Clock and Serializer Rx
& v8 h/ U( R4 c" I** Output - Serializer Tx is connected to the input of the codec
9 j! r+ q0 @: y( y4 I) Q' j*/+ R3 A' F8 Y; G$ j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& U5 L0 t& d: [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- y, o0 m3 F" [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 [5 ~& a" o0 k; F. K) o+ P- o
| MCASP_PIN_ACLKX0 o9 O+ U& k( C5 A: t
| MCASP_PIN_AHCLKX
3 r, x1 K b3 } r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 o8 |3 G% P% H! r8 }! F; m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; z9 g% K0 F6 Q
| MCASP_TX_CLKFAIL ! Z" P! F1 X0 B: B% X
| MCASP_TX_SYNCERROR
) |4 T' {; I, h2 s; X& R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 U$ X4 J9 O# L. U" W) [& Q- J
| MCASP_RX_CLKFAIL2 @; U) d9 y. q( E& |
| MCASP_RX_SYNCERROR ! N, X9 P7 x, C
| MCASP_RX_OVERRUN);
5 Y. [) o* }: ~! p* l} static void I2SDataTxRxActivate(void)
2 D6 O- d# [: F$ Y2 z9 f5 S{% T- I. ^) s3 U C9 x' k/ R3 ^7 p
/* Start the clocks */
. Y3 f+ O0 a* g5 C" QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: g5 T4 \4 I8 C$ E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ _" |2 x' O& }- |* s" k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# Q$ t3 X3 C* I$ g) F/ K
EDMA3_TRIG_MODE_EVENT);( A A4 X" h: w0 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " K# q6 R# |2 H# n4 y3 G) e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
E( e: O% Y% nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- B X& q/ }$ D9 e q W4 ?! _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: n5 i/ z" j- u+ c1 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 a& b6 d3 }- v5 g! p, R9 g' A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 f6 ~ u9 L E* h& w t+ Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ R1 c1 a. l* ~/ l8 m} " P, F) g0 O5 ` `: f9 X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 l* c) u; w* r6 ]# A* N# ^+ j1 Y. j8 Z
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