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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% A5 W4 \5 m5 c: iinput mcasp_ahclkx,' M0 z( R1 u$ v- \+ d
input mcasp_aclkx,
8 H- x0 F- H5 einput axr0,1 a* \& `2 |1 u* z- d3 o
/ t- o4 M5 P" T/ G3 V/ Youtput mcasp_afsr,
! _" v& |4 q7 r! H. houtput mcasp_ahclkr,& A& e5 C& l$ d
output mcasp_aclkr,
9 L( |: J3 o- O! k3 H& k, [8 |output axr1,
4 I C7 d; A" K" n assign mcasp_afsr = mcasp_afsx;4 |1 a; r) V% G* p, g/ N
assign mcasp_aclkr = mcasp_aclkx;
V; b P( ~6 G! Eassign mcasp_ahclkr = mcasp_ahclkx;
- I9 ~+ S% _" f, l+ E7 |! Z ?/ Rassign axr1 = axr0; 4 m7 F1 A6 |5 ]% [+ t' R
- D4 e0 ~: q; N5 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& T8 B G0 M2 i0 @$ `0 `static void McASPI2SConfigure(void)
! ?, Y4 O) I* l3 i) H! V8 @, |; U' \{" j; @, h: `+ \+ j3 P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 u" w. R3 r5 a9 Q2 c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 V: Z. i+ w `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 j1 p- i" i, T/ ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' A8 w8 f; N0 l1 A# tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' @4 H( c( j% B5 B' FMCASP_RX_MODE_DMA);
$ ~9 @: c9 v% q, P3 VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 I! ]8 g1 H. m# O$ n3 ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& r% Y$ z" R5 } w* LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( H, n5 q4 @" v, SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 V# Q7 |; R F+ \* P8 T! s1 r3 `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, W7 U8 a' O/ z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! B9 Z2 M8 P, P; x9 I$ Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, a$ o$ U. P; I u3 C+ e5 \# [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 ]0 J( J, X, L+ Y# L. q& I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! o7 p2 G* ^4 Q
0x00, 0xFF); /* configure the clock for transmitter */3 `3 G' k( h7 Z' y" P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, } v: F2 E3 B0 z3 p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. O2 ^! l5 a j: `- }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* `6 e6 U& Y. O6 R. p
0x00, 0xFF);1 E) v, L' s0 ?; _- B9 s. k' s
9 f9 b6 z4 o, J: \) x: Q5 h
/* Enable synchronization of RX and TX sections */ 9 o) Y0 j( X7 v8 c @, d/ @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 y4 X K, X# u! k. kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& U% R c4 d! x7 XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- f8 Y4 s' b) _2 n: B** Set the serializers, Currently only one serializer is set as
' i# P4 i' g! X; G/ {( f* ^5 Y- p** transmitter and one serializer as receiver.; m- b7 H! }" d
*/
" |# E" q0 m2 G+ W LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 _5 W& g# n: k# S" x2 oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: ~" A$ u4 i" L1 C. K8 I I** Configure the McASP pins $ s/ @, [+ w& q: H( ~; h
** Input - Frame Sync, Clock and Serializer Rx9 j3 v+ d+ y( |0 b4 D5 i
** Output - Serializer Tx is connected to the input of the codec
) M, b) x! C: y0 ~2 C& V. q. ]4 J9 r*/
! @; |4 k- E2 R' R1 n5 N4 d5 I5 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% H3 t2 }8 N* E( E1 `% P+ g0 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" N6 i$ L# B# ?% f+ s8 k* q: y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( k; ^" p& S4 d$ o; |( ?
| MCASP_PIN_ACLKX& V: ^: A& ]0 a, @: B: Z- [
| MCASP_PIN_AHCLKX2 E: g( k3 e- x+ U+ ]1 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 b1 H4 E, P9 v3 v n+ y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. u( j* g4 G7 V8 x( O7 A' Q| MCASP_TX_CLKFAIL
8 a# t1 V) S; `! u% y# g! n' ~| MCASP_TX_SYNCERROR- l7 ~' b% W; k9 t8 ? n1 u, C2 x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 O7 T% t) J% q$ S b, p/ ~8 ~| MCASP_RX_CLKFAIL
* t- G9 m6 O! d0 G" D1 h| MCASP_RX_SYNCERROR ( Y2 h0 H) m6 d( `0 X+ a4 W
| MCASP_RX_OVERRUN);- i: d! O+ N& a: C1 O% z
} static void I2SDataTxRxActivate(void)
+ h0 d. ]. f4 O: ]9 D" w& O{, T t( W; z! U" b2 L
/* Start the clocks */2 @0 M# U: f' t8 u0 J8 J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 b; x" F* O5 P& P8 R% kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, m0 ]& b5 `( i) q0 Q! FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
k: f! }9 f# {6 [ REDMA3_TRIG_MODE_EVENT);$ f; s) l( v3 N- S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % z" n+ m2 E5 I2 [1 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# j% [8 B& p1 z8 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: ]4 {/ o+ \6 }: Y: H/ }- B) l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( {0 m; Y' f$ v# P" N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! \1 K: B" \# J+ _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) j0 M9 ^! O- ^, n( D5 f! Z( ]5 \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( R. m6 G& w* a6 a. _} . j2 C6 @7 u: i1 R: p9 B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 @9 Z. b, o% x B
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