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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," `3 F, x, D! ?. }/ {- e$ }
input mcasp_ahclkx,( t9 }6 o0 [; i2 b
input mcasp_aclkx,. t& {" n: [) ?& q. f" d4 I, S
input axr0,6 r; q" h! O- U3 N
( [1 j6 q; N* Ooutput mcasp_afsr,5 p, E0 k1 P+ m6 G! ~9 f# r$ O( `
output mcasp_ahclkr,
8 I! r4 G4 V" g; ]output mcasp_aclkr,
( C1 Y, d$ n3 B6 a. ^output axr1,6 F# O0 p; A7 W) K t6 p. v8 K( s& }
assign mcasp_afsr = mcasp_afsx;
% y" ?7 N+ D; ^' H# T0 ?6 x' Gassign mcasp_aclkr = mcasp_aclkx;) ^9 f8 G. e5 ~; n! p& J: f1 K
assign mcasp_ahclkr = mcasp_ahclkx;
* ~9 z% l1 O/ Z% Lassign axr1 = axr0;
" I" H4 r8 a% G$ e+ V4 T4 K1 ^: F. ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 T7 ?+ ~% u7 o8 N0 hstatic void McASPI2SConfigure(void)9 T2 ]' U& @& ]/ u4 o }6 I. l: Z2 ?
{
9 P. P! k2 ?0 G" N( k9 S& T ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. h0 ^" z! d5 {" lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 f' X0 G1 l7 JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. H/ @3 j' x$ L( {0 q" T* @" ~8 {6 _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ t& R2 Q3 r; w/ Y8 E9 Y5 G/ QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- S { P' d4 D. k
MCASP_RX_MODE_DMA);- L' A3 y! ~0 R3 ?5 z j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, i6 @9 r9 }$ z6 L3 g; B8 E5 A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ }6 |- l! J* x5 w' }: r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 s2 g! J ~# |6 f& n7 ~7 hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% w5 _8 g2 x4 L. R& {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, I, y: P5 m) \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' f; m4 V9 X0 Q5 gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# y& {# l/ k4 u' W3 {8 ^% ]2 T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 ~; B' J) g2 r1 Z \8 ~( S$ v1 l8 WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ ^+ ^6 }9 P- C3 R. N
0x00, 0xFF); /* configure the clock for transmitter */: c, r% x5 N$ f2 X8 ^ Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- Q: K3 }! Q- Q7 T5 d, _: Z4 L1 s$ hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: p3 y6 r9 @" S: S3 }/ t7 `) k4 u/ XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, Q$ V) W* n5 c H6 Y: _0x00, 0xFF);; P1 s: O; k' S# I4 A8 b
' {+ q& \+ U" m ?; X2 g/* Enable synchronization of RX and TX sections */
6 P. Z1 C- U0 s$ WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 F, a" O$ }# tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ h, Q4 x. M& d, y& K; i( c% R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** @' |# |8 _0 n9 D- P" S- q/ d
** Set the serializers, Currently only one serializer is set as/ J% @! C; x+ A8 J
** transmitter and one serializer as receiver./ n9 J8 j: u" g/ s- l/ I
*/
0 P: x9 T+ H! I' y/ nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ J4 T7 q/ Q& F `6 `0 U: LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 b7 K. r. _" O8 w0 i5 K- e** Configure the McASP pins 9 Q8 w. e% e3 B" O
** Input - Frame Sync, Clock and Serializer Rx
( g1 a7 ^. |9 m: \; h** Output - Serializer Tx is connected to the input of the codec
1 M; I- |; o6 `9 S3 _*/
$ F( {, o; E" p" O% M4 |: ?% `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! e$ R2 f" _5 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; z: |6 [& {+ ~9 a; o: J& YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 c, }5 o; H5 `5 M| MCASP_PIN_ACLKX; n$ y8 s/ v4 } n }2 n! W$ ?
| MCASP_PIN_AHCLKX' P. W9 ?+ G, V6 |- u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& }6 m& p+ b# z7 d+ \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 D& A7 n; P1 T
| MCASP_TX_CLKFAIL + \' h" V( X2 T! ]. N: [
| MCASP_TX_SYNCERROR
7 |9 T& u0 R. G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " a0 R/ a1 `) }/ P9 L3 e; U
| MCASP_RX_CLKFAIL
* A$ N& J, P% a+ A, y9 z" `: U' e| MCASP_RX_SYNCERROR
' m- c9 I& N% O0 \" [' f/ u- W! C| MCASP_RX_OVERRUN);8 W( E. V! Y- t% p
} static void I2SDataTxRxActivate(void)
3 L2 j2 U L' f0 j; J3 ~; }3 D) g{
2 v7 O4 L; d) h- O4 } f/* Start the clocks */6 S- @! h* ]1 _8 d' h1 a$ z" {. o) v9 n" P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 d8 ?! J: a4 i8 ?( g! N1 W$ d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& ~0 Y3 m7 P! M8 C; G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* Z8 R( M' I$ X5 X# @
EDMA3_TRIG_MODE_EVENT);
. y. A6 T* B8 B3 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: W$ Z$ L' }) V& w& b0 z4 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// {4 ^2 C& @: N, n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( X7 x7 M) }, B8 g% [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) x/ }( e4 ~ o! s7 K% Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, x* k+ v5 S6 v' N9 [% G; OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. i* S3 O, N$ Y- B% S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: o5 t2 [0 e' J} 6 E8 W# c& @- ~+ n; J. y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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