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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. |. _, h. Z; {input mcasp_ahclkx,8 m& |! o0 p; e6 g9 P# d) s
input mcasp_aclkx,1 T) Z. ]" J% K6 W
input axr0,
H4 B5 |% d* [* J
$ J! ]+ A: J" f* T& }* `output mcasp_afsr,
8 a. Z; l4 {) x( B Xoutput mcasp_ahclkr,$ F" n% z6 v, o3 W* d
output mcasp_aclkr,
5 h' \$ y0 s! J# K- L5 Uoutput axr1,
, ]6 H+ m8 D3 T2 Y, n- x assign mcasp_afsr = mcasp_afsx;
1 R5 b/ b, C& |" \ n6 I( Rassign mcasp_aclkr = mcasp_aclkx;# @4 _& W4 {2 g
assign mcasp_ahclkr = mcasp_ahclkx;
1 n& u' d8 v/ |; Dassign axr1 = axr0; 6 j1 [, d9 I/ l$ M7 z5 w' j/ U
& f6 Z( h* |! b( I# ^# |/ X% `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 c$ Y8 p, b$ Y X: Z2 ]* G
static void McASPI2SConfigure(void)6 l0 y. R0 U, E: M. I5 f' E5 S& F
{+ X& w% F/ X4 t; U& g8 ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 O( V- N, F- c! |7 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
J( }* _, O$ ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ I1 G# {, T" L! _) U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: z2 E, q1 _$ yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: W) \) O/ n5 F% L {
MCASP_RX_MODE_DMA);2 q# ~; e: f1 Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 F5 l4 t: {# {! @4 [6 p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 [) W; N/ e3 v9 P0 K2 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" Z: F% t$ ?' C: T8 J% S) cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% ^) [; u; a8 M, H. g3 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' t6 ?2 o3 B. }! ^2 S$ \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 i& K1 ~6 m; }1 i/ q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 J" w+ M5 c# p* p. iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , n$ X2 H3 q& S# D! |/ A; M2 y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. C/ I% y, U# v x
0x00, 0xFF); /* configure the clock for transmitter *// C0 W# [+ C' c9 f7 R- _3 c! U6 N. M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' C' R% L. u7 DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ b) r& W9 O6 z. WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' N5 E* x2 ?, \9 M( J0x00, 0xFF);
/ x( T9 F' |0 i/ p7 e5 J/ {
) q/ r+ D# z- y9 Z: m9 _; F/* Enable synchronization of RX and TX sections */ 0 m( s5 x0 l0 v+ ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 S0 I5 M4 o( W% H& c5 P4 ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 q! p6 z, h J6 F6 G! y( [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 O8 s, r T6 L5 W3 A( T5 m# N
** Set the serializers, Currently only one serializer is set as
( O; ^1 i& C5 p: K E3 } t: x7 @( ~** transmitter and one serializer as receiver.0 V- h/ P: d2 |! F" C
*/
- p5 k2 H) q, ]" Q/ G3 O+ r v! fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 }: U% V. S4 w# ^+ ~0 X( P9 x. BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( p3 o4 Z9 r7 o$ H. V** Configure the McASP pins
; |. A& X8 |0 W: Q** Input - Frame Sync, Clock and Serializer Rx9 t7 S' r% g7 G; k6 \
** Output - Serializer Tx is connected to the input of the codec + d: W# N: H% L' t9 ?, [0 m' Q
*/* c: t9 t. |4 {+ C! L/ k9 f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. r, u' e( n* g* ~' \9 n+ T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" l) O. V3 c2 o7 S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) R; n" ]6 l4 f0 B1 a* v% I4 B+ w& f( H| MCASP_PIN_ACLKX
( n, ]" l! @1 c| MCASP_PIN_AHCLKX2 h% n, G# f0 I2 j/ h& m2 {- ~$ @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) ^2 T4 R1 R1 \" RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 u- ^- k0 x9 T% y' E
| MCASP_TX_CLKFAIL 3 C6 |' e3 Y0 t# y) p. r, S
| MCASP_TX_SYNCERROR
$ H2 ~& A$ n v+ W ~. w7 m( j3 u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , G7 `* b' A: O
| MCASP_RX_CLKFAIL
( z. _& C1 ]9 U5 Z| MCASP_RX_SYNCERROR 7 ?0 m0 S9 b7 F% \/ ~# W& \) A3 ^
| MCASP_RX_OVERRUN);
3 n1 d/ ?8 {4 }0 ~- u) v! s} static void I2SDataTxRxActivate(void)
. K, U Z; i; S4 N{
+ @7 @$ [: j* d+ \3 P. `6 V3 R L( F/* Start the clocks */
9 U+ v9 Q" |3 @6 E8 J) C, N: H; t0 [% HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) Q0 r- T# J6 O5 l1 v2 o' y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 K U$ [4 {2 n0 h. G( s {4 gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 y- x1 V5 P K9 E( N7 o
EDMA3_TRIG_MODE_EVENT);
( j3 ]) M) v5 Q/ r' V- k7 A5 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( ?, g1 G5 N0 f- {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* e& v" Z' |, _ hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ y; {* Q6 K- f6 Y) U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* ~2 T! W }" S7 v1 a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' i* i& W1 u0 F# |# b) J4 w7 }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 C( P' u4 @0 s1 B3 `! s+ y- fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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