|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 }$ m! e$ Z7 z* zinput mcasp_ahclkx,1 ^) Q8 ~4 N0 r& r5 M, v
input mcasp_aclkx,
3 ]6 Z5 ]/ n, \* g g* vinput axr0,' \" a0 k3 I8 ]5 g4 ?3 d" v
- ^4 j( ~: P, K) \ K, l: p' P2 Qoutput mcasp_afsr,
% U) W$ L' X# \8 ~3 r3 poutput mcasp_ahclkr,$ Y9 `. r% o! A. }5 f# a% P* Y
output mcasp_aclkr,
' ?; M6 Z! \$ `; `( Zoutput axr1,- h1 V, D# Y P3 r& W1 b. |$ N' s
assign mcasp_afsr = mcasp_afsx;- P( D8 w6 y9 z0 n! Q; _) W
assign mcasp_aclkr = mcasp_aclkx;' K- q8 u0 h2 T
assign mcasp_ahclkr = mcasp_ahclkx;) L8 ^' T6 e' S. j ~* j9 T: C6 Y
assign axr1 = axr0; / _/ P& t d, A7 p
6 G8 P% j; t2 i- s) g% Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) _8 X" u+ [: p+ p) H8 T Z, g E
static void McASPI2SConfigure(void)
$ [* s% W! ^2 |% V) R2 I{5 B; O4 P+ P; _3 {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 |+ W& Z% |* z& K9 s( V$ A2 D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! d5 H9 U L; B" u# n& E. }8 Z; z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, I4 s3 ^. x+ ~) b2 u: l' UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: p' }! p1 h8 G& a1 V- ] Y' R! M& I$ UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 j+ [. ~0 B( P# e( U2 t$ U. FMCASP_RX_MODE_DMA);
( [6 L9 E$ H7 Y% L1 e& l3 R6 E& Z4 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ u2 D' f" q# f+ } oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. P' F4 s4 D" W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' m; u7 O5 Q+ V4 A& ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ l* y. Z. p$ v; Q( n# PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % P: d& F4 U) b' F/ A! P# c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! @0 y; N9 Q1 L% fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 v0 b$ o2 ^, Y0 @8 |3 s5 B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 o9 m6 l" ~) m. f9 [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
r( Q9 w/ H* t' l+ Y# ~0x00, 0xFF); /* configure the clock for transmitter */
6 K! l+ h+ b! O# J0 Y% JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 f5 B- ]: U9 a0 h8 \" L& m3 [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ Z8 _8 z; Z2 h1 g! D" r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 c% {% X2 [+ A* M9 L
0x00, 0xFF);
" m0 P8 ^) _' P; C6 `6 Y( ^
8 j0 q, L9 a# T! I/* Enable synchronization of RX and TX sections */ v0 m- L" y5 f) z: @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 E6 M% P: ^( ~' x8 UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( |- Q7 L4 `% NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( b$ P' W. v& V# @4 g( D% g$ j
** Set the serializers, Currently only one serializer is set as- A6 X" J" Q; p
** transmitter and one serializer as receiver.
1 q9 a! r( Z- b- j, \3 P' {*/
9 J7 X% H6 h) Y9 g3 l) CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 Y- c& |+ o, y' Y4 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 i# m' f0 K+ p+ V3 P. L** Configure the McASP pins
# l W3 m# L& b** Input - Frame Sync, Clock and Serializer Rx; {$ Z# G2 a' O7 k' F" d
** Output - Serializer Tx is connected to the input of the codec " E7 D ~% @" f( g* P' S, Z! g$ j
*/0 q3 L9 L v( \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# E7 K. n: g, ?; b& JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; ^1 J: C, u- p1 V2 i6 J3 y% BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! o# \/ J A4 ~$ C5 [/ R" J
| MCASP_PIN_ACLKX
( B* A) U( f7 N% G| MCASP_PIN_AHCLKX
0 }2 l" ?# I0 ^: d" l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& ^4 U$ {+ Q% ^6 mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. w! a- R6 M6 e| MCASP_TX_CLKFAIL 6 w8 E4 X8 B, H) Z4 g
| MCASP_TX_SYNCERROR# u7 H2 Z6 k6 t9 L$ Y4 y* ^1 Q0 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 R" x1 U; e) W3 M& A
| MCASP_RX_CLKFAIL
! b2 P' A# N+ y| MCASP_RX_SYNCERROR
" U; g+ |& {9 E" Y" d# ^" |- K1 I4 }/ t| MCASP_RX_OVERRUN);
6 O/ D. n& O/ p3 i U8 i} static void I2SDataTxRxActivate(void)
' C D. k' }3 \. _; p{
* Z' Z- n: w2 P3 H! e7 B/* Start the clocks */6 h$ x6 I/ _" J+ [ f: z7 P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 Z4 ^: Q: g" p% \* y2 F6 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# j; o3 j, `: L- f% e. i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 S9 E) q) t4 J8 m1 Y- g: m# K6 vEDMA3_TRIG_MODE_EVENT);8 C; S/ J# s0 a3 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. _6 k- }; ^9 _7 X* Y4 R5 i: b; EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' O3 M1 X5 g& uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' Y: C$ l0 C. w" d$ ^; g' JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 f2 p- m' @) m4 o; ^# Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// N1 C( b& A3 f) w$ H }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! r( i% \( {$ v/ o- w+ W; ]" t7 e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. ~% `% T3 ~4 L$ F! o7 g
}
5 _. ?5 j) U: h, ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
U9 H* d1 }% d' u& i |