|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; W& g5 ^, ?) ~7 k7 h
input mcasp_ahclkx,4 m! [4 ~* z1 w8 l9 a3 a: o
input mcasp_aclkx,
+ U1 N3 F8 g1 Z$ a$ F$ q) uinput axr0,
+ H" A- P- p3 @7 g' @7 S# }! Y) h+ ~& d1 O6 | H
output mcasp_afsr,. v1 l6 R4 R- l! L1 G7 }
output mcasp_ahclkr,
' n5 j% U" H# a( xoutput mcasp_aclkr,. v9 E1 E9 l$ ~ t6 P
output axr1,
s, J& s) E% I% Y assign mcasp_afsr = mcasp_afsx;
9 Y) l* |; y0 }( N; @assign mcasp_aclkr = mcasp_aclkx;! s- @% I3 u) ]* N, s+ v
assign mcasp_ahclkr = mcasp_ahclkx;
# O) U; m, P; ^! N' Massign axr1 = axr0;
; S' f+ [, [4 o; c4 z+ w3 D8 s0 L) c/ J( \2 H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 X1 O* Z- v3 }9 v% t9 s
static void McASPI2SConfigure(void)) g! m2 q" d2 G' o) g
{
. S/ V2 {$ Y/ MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, E& ~* I7 k6 n/ M# d" {6 {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' K+ n$ Y8 b0 t1 n7 e5 S, q6 O4 dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ R' k9 [, U0 F6 g+ p; lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# @5 P+ _6 G8 V3 ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) }% [3 k) L5 X7 g4 Z% S4 [
MCASP_RX_MODE_DMA);1 ~' @6 x: _7 K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! d p9 V. V! ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% [" n5 c w5 g( P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 C$ G# C; J2 F' p5 @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ S8 K' X" O4 X: f6 z' f3 s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : {* w- O3 Y2 ]1 I; S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 _( B, y& Y7 U8 l" kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% V G& ]5 l9 F! O9 C2 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 b9 A$ N* A1 I; _7 N5 YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( i& {: I8 S/ [# ]; e8 }
0x00, 0xFF); /* configure the clock for transmitter */
P" A' h8 b5 H; C/ sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, o: e: E- [9 L: C; \' B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , }& Q) i7 [& I" A1 C: \$ @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( k8 s$ _" f$ O0x00, 0xFF);: t0 {) o s1 Y$ q5 M
$ ^& e/ U7 l" t. j+ q2 _1 _1 ^ ?$ B/ J/* Enable synchronization of RX and TX sections */ , r6 [/ {- C: |( m5 t. c1 B a4 e( v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 a# f3 j8 S4 d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! Z1 g% ?7 d" a8 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, R/ `$ b$ T0 C3 U. a4 b
** Set the serializers, Currently only one serializer is set as
! A: v+ R" [$ a3 G! g- ~** transmitter and one serializer as receiver.% O5 L7 J9 C5 T' S$ I# E0 H" O8 j1 l/ i
*/+ V! l# w3 ^9 I6 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; Q7 |! z8 `" ]" B; R6 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- m1 y0 d y) S3 c6 U** Configure the McASP pins + h/ B, C( B% `9 A0 f
** Input - Frame Sync, Clock and Serializer Rx
( N- `' a' s) @7 r- y1 ^** Output - Serializer Tx is connected to the input of the codec 0 I! a3 r8 B' c/ _1 N5 A
*/0 I" [! B! a1 v$ J7 k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' C2 m+ C/ l/ R' D, x6 M' A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 x$ C. E" f2 z+ M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; I4 s: E: ~; g% Z7 `' a. k
| MCASP_PIN_ACLKX) M: s/ ^$ O: n. ?# o
| MCASP_PIN_AHCLKX
' V2 {! E) V& ?& P* F$ B* u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 q# @) u# p* n9 a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : X" Q R7 Z* Y; X" b
| MCASP_TX_CLKFAIL 3 q8 r; n' d6 `' B' B" @
| MCASP_TX_SYNCERROR: i3 j* T, _+ r2 d F* l" f4 ^
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ R2 Y; _+ T' s' L* q
| MCASP_RX_CLKFAIL
( f* C0 _ s. j. p- C5 o5 [: ]7 Z| MCASP_RX_SYNCERROR 9 [+ O, W+ R7 ?
| MCASP_RX_OVERRUN);" W' w: i- x, y0 y0 x
} static void I2SDataTxRxActivate(void)) f( _! t, ~; _' |3 x1 Y. J: L5 Y
{
: m( m R3 P6 \; N/* Start the clocks */
) l K" U( h4 |7 H" w% ] ^7 R8 lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- }, u; H) v1 `/ R9 ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, g& c4 o% b( J: [9 }5 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& K, X. c5 H, {; U( K; rEDMA3_TRIG_MODE_EVENT);5 V2 k7 C0 r0 h/ R% n$ w. F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 D5 l& J- K8 Z- U9 ]/ l* `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ E$ {" a& b+ l8 t: _! Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 |" i: [& O7 {& G$ D. D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* L7 J- r& T$ m" s! ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 d0 K" n8 |: \. U1 d/ m* \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 D% Y- p7 M$ f/ J! k/ ^. {: I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 F& |3 o9 A0 p p/ t
}
; F' f5 v0 Y |& g( F& K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
% I3 Q0 r5 M- y' ]' w |