|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, K. {5 |6 Z2 ^' _+ V
input mcasp_ahclkx,+ k/ O! o* j: p% G) ]0 y
input mcasp_aclkx,# J2 S" c6 R' ]0 t+ J
input axr0,
6 S6 b! e- A9 }; w" q3 p" m7 C4 L& Q# b8 B2 w# k3 N: A
output mcasp_afsr,
& B$ K5 C8 _& G" U, F* xoutput mcasp_ahclkr,) g# @/ i# D2 \7 k- m# n$ c
output mcasp_aclkr,
1 _. v' F: ?% v0 X% uoutput axr1,( k# |8 j3 n& c& P" `7 ~
assign mcasp_afsr = mcasp_afsx;
6 M% T8 F5 `- u( ~' Rassign mcasp_aclkr = mcasp_aclkx;; l* e% V, `/ a- a. I$ y r
assign mcasp_ahclkr = mcasp_ahclkx;
3 T* C4 V. F, D3 ^assign axr1 = axr0; $ b( D: M: r! N* @. p8 |: ^: ^
/ t( \" b' u' V3 e, D+ ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : @: W! P# S. E3 _ T" B
static void McASPI2SConfigure(void)
% W; _; x8 Z- {+ X{
$ s: o& v- U" E+ [8 qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 V/ u/ z$ ^! Q$ ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; ^3 D7 e7 g8 d2 w1 ]7 g, h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 l8 B+ t/ g7 ?. S$ s6 c; n/ d" R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! z1 l2 w5 Q8 f5 `8 }9 y$ k; y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ \& b0 W, d; f( U7 i
MCASP_RX_MODE_DMA);$ [' t! ?6 z& ^" |0 b8 n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 u6 w6 I( _; ]) V, l0 ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// ?; K$ e. L# {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 r" M- } _1 mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* F5 z8 @& L4 f# a; CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- v( |. U) B3 n# [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% Q0 @; p* ]) A- p6 f! A5 m6 C2 S1 I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ N) h8 V0 a% }! _7 W( e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * b- j7 d5 i/ x$ S: G
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 A% l! {1 N5 ` D3 L5 S# d- E, J0x00, 0xFF); /* configure the clock for transmitter */. |/ H3 J% W) o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) K9 ?8 q- ~9 W5 k2 t, s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 y3 A, n; n. a1 s( @7 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" L; R6 N- K6 m$ V0x00, 0xFF);, s& q% ^3 W( \& m% v
a8 Z$ C, w' b0 M6 q/* Enable synchronization of RX and TX sections */
5 |0 K! o0 m7 o8 g/ @+ j3 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 J& W1 D$ Q A- I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 Z: G. a- k: U! Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 z; n- k1 g8 Q* Z/ t** Set the serializers, Currently only one serializer is set as
. I1 U+ n9 _, ~4 X" e** transmitter and one serializer as receiver.
) k+ p, e! u2 i1 Z) l*/
; _& M& Y* D. H4 n( dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 b" s7 b# @% A8 K! E6 ~& p# O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** b- L+ I4 x* J/ d0 K" z) A6 L
** Configure the McASP pins * L1 z" ^0 J) g1 m0 a
** Input - Frame Sync, Clock and Serializer Rx7 V3 D5 i* M$ G3 N& ?0 A
** Output - Serializer Tx is connected to the input of the codec # Y7 j3 w. y6 ]8 C
*/
- \& {* I; J$ U& u/ S# [& R* Q; nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ P: ]- N* P4 K2 M% N9 R k' tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 p* I% l- a2 J7 C: Z: qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 C2 F! `0 c% Y3 i. v+ `| MCASP_PIN_ACLKX
$ ^ Q) l) }: |3 |. }| MCASP_PIN_AHCLKX
+ M2 r# b- D) {/ Q0 M9 h; ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 d3 K2 Y4 y4 H2 ^' B6 a; mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, A4 \2 i( Z' W9 E2 ~, ], t| MCASP_TX_CLKFAIL
% h# v; b2 D) [; `| MCASP_TX_SYNCERROR. {* p, G/ A9 N" J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR s8 m( N) ^2 a# `/ g
| MCASP_RX_CLKFAIL
. f& P" V" e- p7 ^, x1 k4 ~, g| MCASP_RX_SYNCERROR
( Z |7 g! K& b, {4 d& ^) ^8 a| MCASP_RX_OVERRUN);9 q: f% z! f* P8 A/ y* I+ I) O! @
} static void I2SDataTxRxActivate(void)) v3 R/ g2 c2 u t0 l, B$ M
{+ P$ e! Q+ k8 G+ _
/* Start the clocks */8 f( V$ j/ K! b: R# ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) y* L- G5 B( S( b! H7 {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 u9 n1 s3 v/ ~0 `1 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( R4 P4 |( I ]) Z. I# q& {' Q
EDMA3_TRIG_MODE_EVENT);2 M. |' ?/ H0 C9 f, `( k. U- W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% K* {5 r. U6 e: yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( _' U+ p6 d& h! x. \$ _' P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 q, x) }! }, X1 n: x/ I m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" Q/ o6 d# M: z5 P2 {$ b$ j9 B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 |, g, n4 o. }2 S5 k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
{8 f4 E4 ?; t, Z6 WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. \/ Y" p ] R2 s$ u- K, e, B: I
} * D( z6 B+ D# u+ g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 |! K8 B: {* ^2 @* z) @' A3 D! M T
|