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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- ]8 {' j" V" I3 Binput mcasp_ahclkx,( @- t4 q& Z; ?* l6 u% B
input mcasp_aclkx,
& A; ?) k" m9 y4 P" Qinput axr0,
* r/ a. u1 S9 n# _ d z. |' w3 z) c% L6 L2 R E; h
output mcasp_afsr,
3 y* l, n7 l( K5 v4 Ioutput mcasp_ahclkr,
' j. m l2 K2 i3 l8 w @output mcasp_aclkr,! A" i+ T1 E7 y2 t( }6 D8 ?
output axr1,
7 h: C" C* I4 ]* m4 m. P4 Z assign mcasp_afsr = mcasp_afsx;" u) C z0 U" i! }$ I
assign mcasp_aclkr = mcasp_aclkx;1 X* l; N6 y! a+ q
assign mcasp_ahclkr = mcasp_ahclkx;* Q- U" `& ?: Y" {; m
assign axr1 = axr0; ( W" ]* _2 e; I1 R& Z8 \
5 w6 {' b1 T& y$ M4 ?0 q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! g1 ]8 u0 U6 i R- |static void McASPI2SConfigure(void)
_5 p& b1 N5 d{
9 b. x! |, f7 e9 n6 z& DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ R# [- J2 f$ [0 q" ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ W) F9 v: i4 MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 B9 Q6 B2 u( D2 t" v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! [, Y6 ^" @( E$ T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 W6 [2 {; {( e6 g" L; oMCASP_RX_MODE_DMA);+ q6 O. {. s4 [& E5 A- b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 t$ S* v5 q7 @% bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 D1 A" A1 |5 a$ h4 EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 b3 M! s2 J6 R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" d- b+ P; r( h8 }" z$ P& S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 {( z, z7 u( f% F9 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 b$ j# C" L8 O2 h! z5 W- W7 V% X0 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& E! w; G% t$ V9 y, m3 ]0 q9 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( ?3 v! T& W! p; u1 C NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 w/ R- s9 H H6 X: t* o% N0x00, 0xFF); /* configure the clock for transmitter */
) \: f7 z8 |! R0 y1 R, v9 aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* o. C- O' _& Z/ H; j) n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 o! S1 S/ _" u) T' lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 U& z* Q4 k$ o8 P& D0x00, 0xFF);! D* H3 }/ {, U# b ~) D
6 c7 S3 J. Y }/* Enable synchronization of RX and TX sections */ & D1 W8 q! [4 Y3 }1 T2 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" r' e) U) ^' eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. w. W3 x. o; f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 k; Y) q/ ~0 ^8 J" \( T9 H
** Set the serializers, Currently only one serializer is set as. X- G$ o1 h2 k: _: j
** transmitter and one serializer as receiver. v+ V, f( p3 w n
*/ {( c3 {; e( d( t; w* J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 c% z5 W M8 Y# Z* P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, X$ d8 f. Q6 e
** Configure the McASP pins
, z6 c4 c# J+ g0 x** Input - Frame Sync, Clock and Serializer Rx
1 k8 t1 q2 L) n; i9 q** Output - Serializer Tx is connected to the input of the codec
3 i/ t& Q7 u, R! v- d, x1 c0 x*/
* a; ]- W( p/ [. y4 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 B5 K0 f7 O1 P* x; G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 a0 }& `* ~5 } D$ a) v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 f. |/ s; A- u1 o5 L* S
| MCASP_PIN_ACLKX
4 a: R! `: |0 z) H/ n| MCASP_PIN_AHCLKX
6 U1 p2 T6 }0 v2 w/ ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 L( Z j. G" l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 i( L: B6 a6 p( h: W
| MCASP_TX_CLKFAIL
) ~3 L$ r4 D% O& A+ `0 h. [+ L| MCASP_TX_SYNCERROR
6 s# y( C8 F( x5 k7 Q7 v: L& r" S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 g- r% I; U1 g/ X$ c| MCASP_RX_CLKFAIL
( v3 A* D6 {. ?* o| MCASP_RX_SYNCERROR
$ |% _/ E# R' C3 H* b7 C| MCASP_RX_OVERRUN);- {5 L6 f. ?5 a/ V3 ~" D$ Z7 m
} static void I2SDataTxRxActivate(void)
5 \: t: c2 n9 Y3 V# E{
( W. ~* g+ J7 R& L# U. L6 W/* Start the clocks */5 g; y) I' V; j6 Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 S6 v, |' E, a) i+ D- ^$ b0 L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& P% ] F$ n, I+ }) fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& _+ t1 r2 g8 j# S7 sEDMA3_TRIG_MODE_EVENT);
+ A$ S5 j) ?9 u( J( H' `$ E3 N xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. C6 F) h. n+ {$ }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 E. h4 s/ c' ^8 E- X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( }/ S& L7 y6 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 d9 d0 e: }. ?; E: c* \* T8 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. l# ~& U8 C9 r+ l: ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 O, @! Z% {) N2 c0 _2 T! C! GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ }; k0 g- o) T3 z8 t$ D" v
} $ d5 i( O: X+ L0 Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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