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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 I! A3 K2 R) W4 N/ g0 I2 U2 ?1 y
input mcasp_ahclkx,; H7 j( s5 y/ c
input mcasp_aclkx,4 }" S' V! A# P
input axr0,
3 r d5 I* i% T. b& I. L. `/ D- a* n3 v2 Y3 T. l
output mcasp_afsr,
+ A2 |% ]- k0 s! `! `/ Loutput mcasp_ahclkr,
! n. u+ L& `6 B% ooutput mcasp_aclkr,) z& ?; ~1 y# m' D
output axr1,
8 M! ]( w# q/ k. `( R% @" s assign mcasp_afsr = mcasp_afsx;4 d" H. X8 x5 u( A+ M* h$ J( L
assign mcasp_aclkr = mcasp_aclkx;6 s. O2 O1 G# n, A( r
assign mcasp_ahclkr = mcasp_ahclkx;8 S- O) [" e' o" q- l
assign axr1 = axr0; 4 _( ] O: E3 E8 X- F( S( U' D. O
* f1 \: w M1 q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* P& g2 S+ v/ ~: Estatic void McASPI2SConfigure(void)
! c% Z2 f( G; X; n- T8 f* c, _{0 U* }; j+ P/ ~2 N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 ~. s; H, a- y1 p G7 a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 n) }) k7 P: `3 J6 G$ [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ { M" ~" Y. j0 s4 a5 jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) l) P9 @" g; U# E% H3 u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ Z4 Q6 ]! s/ FMCASP_RX_MODE_DMA);" b% l; a* Z/ Z, j6 U3 ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% f' |$ w& ^, u8 s6 a- `4 R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 ?7 [: Q' n2 }- R1 N G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) E* h. B0 a+ m V: w# IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 }" } u* a3 A# H& gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( N2 [% S' @6 X- a* N6 [+ \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" L4 ^% j5 f( I5 z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" N ~1 l6 d7 |. D+ {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 G7 o: i2 ^: Q2 \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, M. w; }; h/ E% f# U0x00, 0xFF); /* configure the clock for transmitter */
- a7 Q+ w T( E! R! V/ `( oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ ~) J% H5 \$ L; |8 |! K7 X/ H# t% L7 `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ ?. J: V% S g E' w% TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( B% K( g: I+ F7 B3 V* o0x00, 0xFF);
8 p1 B& U" `- g/ c {7 Y4 Q
: d, F% Z6 W0 p) o/* Enable synchronization of RX and TX sections */ ! J# @% T" z. N+ j" }3 X& m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( ?+ r( e: r6 B" P' aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* |5 s. T( ~9 S6 Z' G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
H1 @1 h) E; r: X** Set the serializers, Currently only one serializer is set as
$ \: W4 p+ z: m# n* m" b# u: r** transmitter and one serializer as receiver.
! Q& u3 Z0 u7 r) r; @2 A* R7 X*/
6 ^* S& {" E& g6 E E+ i# SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* v: v0 Y4 V2 L5 e( MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& C' [/ o4 Y# o5 \0 A** Configure the McASP pins
" m+ K% j9 F5 ~** Input - Frame Sync, Clock and Serializer Rx# L8 d0 m4 E* \! P' p- R. D4 W
** Output - Serializer Tx is connected to the input of the codec * b& ?4 a8 n; y: S
*/
% l+ [+ X! Q, x0 G J5 O: SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. a$ G* {8 B2 K4 @* m. N+ T- M* mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- Z1 p* L% d0 T8 J" `# i+ mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 f$ P) V- M, t3 s| MCASP_PIN_ACLKX
1 ]3 |: g2 d! d& O- ~9 K3 k- @3 E| MCASP_PIN_AHCLKX) I3 O/ O! X" Z2 s# |* G" m0 H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ e E2 {4 f' \3 e3 p, NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " q8 p5 |7 H' y* Y5 \2 ` O
| MCASP_TX_CLKFAIL ( R2 f- P! [9 N. x$ o
| MCASP_TX_SYNCERROR E5 C0 W0 G+ i. X- A+ \7 G5 M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; {5 |# F% q8 w5 ?; U3 W1 T$ F
| MCASP_RX_CLKFAIL
* |4 I$ T' l( |* h| MCASP_RX_SYNCERROR
R, x. M8 @& P( v* M1 w9 R| MCASP_RX_OVERRUN);
4 D8 d% k+ }! `) F& }( H, T( y: j1 R} static void I2SDataTxRxActivate(void)
/ L1 W( y9 S% {. k2 k{
: H, s+ d: a" d: ^7 Q' I: M1 C/* Start the clocks */
; s1 a& ?. E& [1 `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& J3 A5 @6 j1 M2 p0 p2 o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 c) U4 f6 E5 c1 n. K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 K. J. g/ r7 o
EDMA3_TRIG_MODE_EVENT);+ j: Y) r y4 b9 O% F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 z9 S6 _8 J+ k$ @& \; P& c4 N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, ~, s- ?' `1 J% [' cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 l0 B ]# G' t) O4 \2 C1 _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ c1 @' P2 P( @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ ~4 H% t! r# G$ _+ R: {# }) R* n" |. `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 z8 p1 {+ ^5 UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- _( S8 G. \& t- O$ _; C5 i6 f
}
# r9 b$ \" |- a3 d9 \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- z% _& q9 d) k5 n b |