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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ a/ ^4 o) @" `3 u2 V
input mcasp_ahclkx,
T$ n# y. Y, f9 J0 v6 W* Rinput mcasp_aclkx,
' _- C' T1 ]& q: j" Vinput axr0,
/ _8 e( V8 D( {; W B+ q! N, e% K) i* F$ b( G; }6 w' H2 ] `4 s
output mcasp_afsr,
' { X# N. t# ~ U; ioutput mcasp_ahclkr,
g$ S- g6 L- _7 i9 ]8 P9 t5 u. ]output mcasp_aclkr,
0 U2 @2 N# Z) S) v" e8 P1 v9 M/ t/ houtput axr1,
1 @$ w& }* x# H4 | assign mcasp_afsr = mcasp_afsx; A* T3 Q' u' n+ T) G" Q
assign mcasp_aclkr = mcasp_aclkx;
; f7 i: S' t5 ]+ y; @* y3 P0 P& Vassign mcasp_ahclkr = mcasp_ahclkx;/ Y2 [! S1 _8 D& w0 C
assign axr1 = axr0; ! ?) C! G% l7 ]
, s3 E9 z7 U- }' v) L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ W. D( q* Y& W/ |# `static void McASPI2SConfigure(void)$ `$ ]. k: T5 P: w
{6 \/ @4 j9 r( u2 N. y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' m, F7 W. j$ L/ [5 T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; s3 @4 K- z" b# pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 l& n7 {8 V* y& w' c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# l; B* |% q, v6 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 H3 d. L: P3 l/ O- i# S
MCASP_RX_MODE_DMA);- i6 P8 B7 s# V7 J6 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! E( z8 T0 j _ D) t/ Y; P) UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) U* M; k# a/ \0 r* _4 p) }& RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' ]: L+ q- ^+ v- V2 }- yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& l2 T* r+ R+ W1 o& ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 F+ f- d9 t7 E7 P+ R+ B+ c E% g* TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: L. Z3 k/ W4 h8 C% EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. q& K4 |4 ?, m' L t0 w& BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 L& B0 _; }6 C2 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, e' x3 g, v8 ?0 U% X8 k
0x00, 0xFF); /* configure the clock for transmitter */
6 C: ]- u" t7 t! V+ h5 wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& L* a, O' f$ p1 I/ b9 D8 H8 c; F1 UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" E! L0 `8 S+ k3 O1 tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 f* G: N7 q& o1 W8 n; W" V" y
0x00, 0xFF);
" g O+ Q( q% n+ |2 d/ [5 V: f4 w7 g; h$ Q& \$ }. ^4 K
/* Enable synchronization of RX and TX sections */ * p1 F( {7 a" Z2 u! X' q1 r7 T0 ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 T& x. W4 M h wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 K4 @1 \8 p8 G/ ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ M" ]+ G3 e7 J8 A' \
** Set the serializers, Currently only one serializer is set as3 K. e7 s* N! O- }
** transmitter and one serializer as receiver.
2 C0 H/ h4 X* M*/
4 k, z# y! [# T! u) a# Q* a. k: s4 RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ g% ~* u, c c$ x! i: Z) b D6 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 r; T- l' [* L3 G1 j( {4 c** Configure the McASP pins
( Y5 [) N; n( S X** Input - Frame Sync, Clock and Serializer Rx
% s1 U2 y" D1 z0 v. a** Output - Serializer Tx is connected to the input of the codec
A( s* `/ @. h' @4 g) U1 C*/& a5 b4 s9 i3 ?% o r* A6 r5 `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; S2 j3 R( G) j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 O! ]0 B* m# \5 j+ x* |2 h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* m+ M3 Z; y; K6 C0 V
| MCASP_PIN_ACLKX1 `" K6 o" }, o2 k( ~5 \- y
| MCASP_PIN_AHCLKX+ r5 w# R" X0 x- ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% Z/ S( y8 b7 y$ R/ JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % \3 J' Y7 k4 {! H7 E0 y) X
| MCASP_TX_CLKFAIL 3 X2 e- U# V" G% V3 w
| MCASP_TX_SYNCERROR+ L; q# z4 s; b0 U% \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
v2 b6 G. U& f8 d. K6 E+ s; M1 r: F| MCASP_RX_CLKFAIL
* ~2 w* e: k) G, r5 C; X| MCASP_RX_SYNCERROR
5 w. b" x# \# |% e/ E| MCASP_RX_OVERRUN);
! u9 ~. d0 p" W% k) K} static void I2SDataTxRxActivate(void)
) \- H3 _: Y. t& R* ?{
5 | R4 P: d+ {: t( w/* Start the clocks */4 Z) A+ Y- a5 S o6 u7 j# Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 S% b& r. w! I% Z) U' i* y5 {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* I' a; N4 _% }% n2 X- xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 ~+ C3 z' Y* `5 Z9 P0 n) BEDMA3_TRIG_MODE_EVENT);* l. v& s- z7 v+ { F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 ]* }% g* S( ~4 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 K' v+ ~/ B, n( R; A/ \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 n0 i1 @: }: {) V/ x% r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ s8 B" \$ g$ [3 p" ^# x/ N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 N: q" D- I2 U+ A" Q: m( o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% O; K& s6 y3 s& i" `2 f$ C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& L& H0 e% l3 b2 U4 f% `}
- Y$ y: C; L8 i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & V7 w8 V$ [# ^6 n# U+ G
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