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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, J; W) Z6 Z" @( ?$ R
input mcasp_ahclkx,0 N" ?' N" F- L
input mcasp_aclkx,& C7 \ l* R( O" A2 {
input axr0,
; R+ |: G* A; { E+ Q
' T w g8 j, \9 W6 h5 s4 koutput mcasp_afsr,
# q3 |0 B) E0 A* Loutput mcasp_ahclkr,
- l; w* w* t1 ^6 {. foutput mcasp_aclkr,
+ H" F0 A9 Z1 N3 R6 S- w( [output axr1,/ A6 a. W% x; {8 Z r' u0 {$ z0 |
assign mcasp_afsr = mcasp_afsx;% k% ^4 {+ y6 m- ]2 e
assign mcasp_aclkr = mcasp_aclkx;) _0 r4 \8 \0 R
assign mcasp_ahclkr = mcasp_ahclkx;( a4 r: W6 `: n" I5 V
assign axr1 = axr0; % q7 @% [1 Y4 p" `" e* t3 U+ ?
' w' \+ m; W% `* s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . q) C: m& `! Y. Z% F
static void McASPI2SConfigure(void): l: c6 T2 ^; f+ q- j+ @( ^4 J
{0 w! }* _! Y' K Z0 k7 @4 X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 X6 p3 E# Q i; NMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; X/ j+ }7 w# x8 ?9 d) c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- o1 V' t, `8 _" \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& d# ]' |2 E9 @5 t3 L# ^6 e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& r# X r+ L% x- |' E4 e8 T+ k+ E! s
MCASP_RX_MODE_DMA);6 C$ P+ h1 n4 F- {+ E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& h; R# [: O, t+ t" u' _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& K2 c7 N1 @ L& K6 LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 l& J3 ?2 R+ `* GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! ?4 b" d: n- W9 y8 R- i. X8 pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& b& G, E) I) u0 v/ NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% P4 N' P; E+ o0 G/ I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" ~) ]% U0 ~5 U2 W( k/ Q+ ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, Z3 [- l) Q5 A8 h/ rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- c X2 ~5 N) U) D, T1 L3 M, H0x00, 0xFF); /* configure the clock for transmitter */
! A. O. g3 Y" gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, S3 F) j' l7 C7 s; ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 ]# E# F8 W1 `5 Y+ j7 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 E$ `! A y* ~; z0 G& T7 ?6 E0x00, 0xFF);, D1 e8 _0 O Q2 S0 g* U) M
" I6 }5 Q: @: D6 f0 r/ | t/* Enable synchronization of RX and TX sections */
" c ~( g! ]0 d+ v7 r! ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( P' R1 T2 |+ n+ N% @9 a r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 B# O9 ~$ `1 n, C! sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; A3 z* y7 ^ o/ _ E6 E** Set the serializers, Currently only one serializer is set as/ L% N2 N( F) F( [, V$ ]! x
** transmitter and one serializer as receiver.9 B0 C* K6 I( t) [! F5 T& i" B( @
*/8 X. \3 z X! I# ? r1 S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 J* x( C* }3 d. _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% J5 Q" z+ i, K3 Z4 t1 p( O! g
** Configure the McASP pins
' f0 Q3 e6 q0 ^- E5 f** Input - Frame Sync, Clock and Serializer Rx
$ N% S$ W8 N+ m }- C- ^1 F' {** Output - Serializer Tx is connected to the input of the codec 6 c" L7 g! v% O# n6 P* P
*/2 O$ z& i$ c! C" y6 R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* X z5 t& Y- l/ O) L S, u, k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; E3 a9 @ ?+ z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! _" y/ @5 }5 Z: `& @| MCASP_PIN_ACLKX5 N5 L, s) x8 B1 [. l
| MCASP_PIN_AHCLKX
# r6 o, ~3 j Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% V/ e0 p, c3 c/ z- i4 zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 R9 ]) b6 F+ } _ `" f| MCASP_TX_CLKFAIL
$ s9 b! k2 ]; U) p" _; Q3 o- `! y& y| MCASP_TX_SYNCERROR
, d, T5 o6 O7 R: Y/ c' D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( Z% l) ?5 X. f. e
| MCASP_RX_CLKFAIL6 A' Q; A8 n5 ] l
| MCASP_RX_SYNCERROR
3 p1 z5 k, z& M0 L3 e$ h| MCASP_RX_OVERRUN);- t4 Y( E6 ?7 S1 @. t7 N1 j3 o
} static void I2SDataTxRxActivate(void)
+ w9 N6 Z# y8 j9 W/ J6 J0 d# b7 @{7 C- k% w$ {' [4 a3 D
/* Start the clocks */9 F: E/ k6 c0 L8 m1 I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 G+ ^, t v* x8 m- GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 p+ [/ ~: s; H: l( F; j TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# L3 C! n& |* \4 J0 }0 M/ J( dEDMA3_TRIG_MODE_EVENT);
: g: H) v, J8 H) l- tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! ?( v3 @! Z X# w' J) ^' _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: Q' P* ^* H" D' ~$ G2 v, o+ ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 O& q. p' m* X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ N+ u% d' U1 X. z. |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 G4 D- \6 w7 T$ W5 x2 t, P2 `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 r* W/ [+ m8 C* t: v% B6 M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' b# v( Y9 V- |7 U' c+ B
}
5 l& U/ S+ W/ z* e, o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - j6 |( f2 }$ U5 i" H
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