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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; m& z, p6 y; ?! g+ A5 k& j( n
input mcasp_ahclkx,6 q6 j) l* a o) G5 N
input mcasp_aclkx,
4 L1 l( \9 O! G8 _1 `$ \input axr0,
! P6 i6 f" c/ _7 U4 H
7 l' u0 M2 Q( h5 I/ |4 coutput mcasp_afsr,' T5 i7 Q! s# ]& ~1 x% b: n
output mcasp_ahclkr,* I# j( Z5 ?0 @3 E, v# g: F
output mcasp_aclkr,
: j) V7 l( D0 g$ t _4 o4 q5 Qoutput axr1,* |5 W" ^; W& _) h" K' T
assign mcasp_afsr = mcasp_afsx;
; T+ }' r# s& \* [6 nassign mcasp_aclkr = mcasp_aclkx;# i# b {# t$ h( k& Z7 q- |
assign mcasp_ahclkr = mcasp_ahclkx;
2 i( P: V# _% g6 J: v& fassign axr1 = axr0; 4 ^ D& S# ~9 J5 s7 q& K9 j& e
4 r$ y2 I( Z0 ~: _- W. i) U0 b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 X( j# I, e/ D4 `- C3 s6 H1 u! B
static void McASPI2SConfigure(void)
8 w. m' A, L0 H. n) X{
, s4 ~0 T! b8 F# F0 i; a) TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% H6 ~# j5 E) tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 G" F0 X# ^ _! s* N7 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) i0 O% G5 u/ i, U, `/ I0 R/ pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 F' J- f) T; N3 `" Y3 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ U5 }% W. M, j; _% m* cMCASP_RX_MODE_DMA);
* f0 i2 k! B) \! jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" S5 _- F5 L) k4 h- d& rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& h/ g) J& L" xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& x5 G- ~' X3 t/ T4 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 v) q! i: |: AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 A$ D1 B' z4 T. r/ A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) M7 e+ t- ]% ~. q2 w1 s# V0 XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ ?$ j# _0 b- n; W9 P& r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / M5 d* _; j5 m! Z- G$ U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) V# Z+ A( V0 w5 [7 a7 y
0x00, 0xFF); /* configure the clock for transmitter */
8 C5 C4 ~; V& j8 H2 H2 N# b- TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 `. R, a1 d& k( N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * J/ y1 n8 q+ ^" N8 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ s- E+ s" m! Z- g' B$ y6 {2 }0x00, 0xFF);9 h" O$ M1 o, O' |6 x9 @1 `2 x4 A- Z
. T% [5 |" ^9 h0 K- `2 J, J- O/* Enable synchronization of RX and TX sections */
* ]# z+ o7 E9 \0 h; k; |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* Q1 _# R$ r& F6 V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ V8 j# }/ ?+ \1 K, AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( M- X8 h) H* L, I& D5 o** Set the serializers, Currently only one serializer is set as
& O+ W; a/ g8 i! p, O+ C** transmitter and one serializer as receiver., H' v0 Y$ u' `6 a' F
*/9 z3 j/ _+ P% C0 |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 ]' o7 ?$ |+ |4 l9 k9 U i. ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" b9 c. j# g# s$ C6 @** Configure the McASP pins
9 e& W0 [# D5 R7 m _7 N" n** Input - Frame Sync, Clock and Serializer Rx
5 V# N# v. m6 P8 t** Output - Serializer Tx is connected to the input of the codec
/ e( i) A# ^ [. O# P4 w*/7 s/ _3 V/ `; a5 ]9 n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% d4 ^* ?# Q5 f: l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 }) @- Y5 V+ t9 n- V7 D- P, ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" n9 @* {3 \; `7 h# c
| MCASP_PIN_ACLKX- i! N$ x u) P" t) C4 G
| MCASP_PIN_AHCLKX
2 }& e& ^" \6 m! [5 s7 v5 x# p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ n! h6 P! H# y2 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % {( `: d- s( x
| MCASP_TX_CLKFAIL ! B; n5 @2 j: Y+ E2 l4 J G. V
| MCASP_TX_SYNCERROR% b# l8 B( ?) A: J8 w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! n% r9 T ~* I. d6 k| MCASP_RX_CLKFAIL
- ^9 a( y5 v; K- }+ u: c5 J| MCASP_RX_SYNCERROR
5 ?0 w! R$ K8 I4 _; L' T| MCASP_RX_OVERRUN);
' j) L. Y& l( `9 F; L} static void I2SDataTxRxActivate(void)
( r6 g, l& S0 {. B$ {3 {. l* f8 A{# `+ }8 {( ^) S/ f$ |
/* Start the clocks */
/ @7 R5 k, [% NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) K+ M8 Z8 X6 r: ]# J; H$ U/ I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 G2 {' Y" N8 l! i) sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 e* L% o7 O" q, B
EDMA3_TRIG_MODE_EVENT);
7 \9 E4 Y' `1 d3 v* BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 {; g) Q! x0 b" h; r+ r% JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ N6 V- e) _: z1 m3 \6 x' MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& m$ E/ w X! s4 y5 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% P# W( p8 P. J c5 X# c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 X/ O8 C- H8 `/ c* c& {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 x: \. A, \5 {3 i. W @$ A0 KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" m8 {$ P3 q8 {5 m/ v% ~, ]
} 9 L7 K) P6 ?! J+ X; A7 t3 Z# r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & [, W9 |/ k) Y4 z$ L) ]/ `. h' r
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