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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" ^2 D4 u) {' k) y6 H: \/ V+ Hinput mcasp_ahclkx," n- A& P3 |5 [4 v0 @, D
input mcasp_aclkx,
# ], ]: S- [# {' l6 N dinput axr0,
- ]( D, J6 v. p+ R9 T4 n6 Z5 w7 o0 Y! u
output mcasp_afsr,' q& C& a+ ]- ]
output mcasp_ahclkr,1 r1 V m$ X2 h
output mcasp_aclkr,' V& B% P* h. O9 M6 ?& ~; Z: h0 |
output axr1,% _" X6 e1 o Z' C3 Y3 ?: r
assign mcasp_afsr = mcasp_afsx;- M" k5 F/ o8 X+ Y% g' I1 Z
assign mcasp_aclkr = mcasp_aclkx;
3 s& x1 N- T( S) `3 B8 Qassign mcasp_ahclkr = mcasp_ahclkx;0 e8 C. |- R& X r5 h" `( J+ L3 t
assign axr1 = axr0;
9 X$ V, a7 r. |: j0 L9 Z: l9 z5 a# n, Z8 }0 b, y6 Y1 S" u8 d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ ]* p* v( L, B* V$ w( y, I" Rstatic void McASPI2SConfigure(void)) q; u: O& w4 e5 W* k1 v/ r. F9 f$ w7 l
{
7 m3 ~( b( Q2 t( o. b& i1 c' N+ TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. Q+ l2 D2 t- K5 c' f7 `# ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 `. \9 o. v& }- u% H0 P* Q1 V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 B+ [/ k. _' F: \* e% e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 r: D8 `2 f# z5 B# c# d8 QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# n1 b9 B/ h0 R- K7 rMCASP_RX_MODE_DMA);/ z2 n1 k% e: T9 x/ ^+ P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: d) z$ D. b5 w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; J# D5 O4 c" s- V. ^# R- o w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 m1 Z" [( u! M( [" h! T& YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 u% ]2 ^+ U6 C( pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; G. K9 i7 {, V+ \* v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. l+ Z7 J$ ~0 d$ W z( o; D) p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); K& c5 h( }3 }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + [, m1 M1 ?- g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. O ~, W0 \( m8 B7 w# h( v; [
0x00, 0xFF); /* configure the clock for transmitter */- S+ z! j4 T8 J" [/ s# c8 j$ c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 }4 v3 ?; p1 l9 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) O2 [0 K0 {, o$ HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, ~8 u3 j- B2 \+ h0x00, 0xFF);
4 X) A0 d$ S- m8 W. u( n. D" g9 \4 ]; u& w- R8 _! T# g
/* Enable synchronization of RX and TX sections */ 4 m; b- o- G5 I, X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 ?+ B. ], [! \# H, F( F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% \ n" Q4 X% C& w' K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 I3 K$ D7 {* q* K' K5 N$ S** Set the serializers, Currently only one serializer is set as
: B1 Q5 c+ g! [$ _, t* w** transmitter and one serializer as receiver.: o: h: o6 t4 V2 T
*/
* K8 a/ d4 o) A9 f- o5 v: R RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 ~$ |( E) j* y% {/ ?7 A9 B1 R) ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* e. Y% B" T7 W: H** Configure the McASP pins % O: b# j2 \+ a: S* b. d$ G
** Input - Frame Sync, Clock and Serializer Rx
6 g( b( b& I/ ^; g7 E& D/ g' h** Output - Serializer Tx is connected to the input of the codec 5 ]9 K" u# F: f: y8 A
*/! p( V) b u; M) i& E" Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, x5 f# w$ {6 Q9 ?- o8 SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); E, j3 D5 H( O- c+ U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. ]. o4 ]9 d# ^* h) {
| MCASP_PIN_ACLKX% ?( p1 J) F& |5 c
| MCASP_PIN_AHCLKX( m; b4 Y+ V" m$ L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" f3 j$ i2 X }$ L7 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 I R5 B, [6 l, j% K& m2 L
| MCASP_TX_CLKFAIL
3 B' y& l/ \1 Y| MCASP_TX_SYNCERROR! H; q$ h4 U0 l0 Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " @. M+ j/ m9 o7 p
| MCASP_RX_CLKFAIL
R( D. J6 N, c. E9 R| MCASP_RX_SYNCERROR
[$ J: Q( G) Y" N4 A) V| MCASP_RX_OVERRUN);
7 T! S5 R) [2 L6 J* R} static void I2SDataTxRxActivate(void)
) l/ A0 Z0 U' y0 ]% m) {* G{
1 {( d* R3 x0 x5 E2 {' v/* Start the clocks */" S, z+ d" D$ Z* S7 B, Y8 f0 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' u8 ]5 H- p# v6 {5 |/ s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! Q0 q" A! Y. c! YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" L9 o7 l" n! Z: {EDMA3_TRIG_MODE_EVENT);
- u1 u$ ^( B2 ~2 s' b' N* LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 u- v4 u( Q! m3 y1 b' V4 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 W$ P) E2 D1 e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. t. q* K3 E; o/ l- h R; a# o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 i$ r+ J& j; {. E, J3 p$ X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' J; H S; H; O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); N. O% E+ W9 T% b: U" i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); [$ L, y2 n6 j, |8 {) f
}
[/ f* W/ R& m3 k; _- i; Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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