|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% m/ ~ s5 }: x8 }' P: D2 Hinput mcasp_ahclkx,$ ~) ?& o5 K) {9 Q) p" }
input mcasp_aclkx,
! S: R; h2 Y9 s4 G& g9 t. `input axr0,9 @2 q$ V0 N e3 h+ V) w
2 R& Q- D% f7 `% ~output mcasp_afsr,/ [ o5 S1 n" `4 i) |# c$ y
output mcasp_ahclkr,
3 c0 v. H- i- goutput mcasp_aclkr,- v* }4 l) o5 Y0 y: F R1 N
output axr1,
' j6 U$ O, T) M& K' l assign mcasp_afsr = mcasp_afsx;
9 r7 q9 [) A2 u7 Q. A# O" Eassign mcasp_aclkr = mcasp_aclkx;9 |9 s$ i4 C: o
assign mcasp_ahclkr = mcasp_ahclkx;: {9 K' d, M0 l
assign axr1 = axr0; 4 u. y) Z; T) _3 \, S
. S5 h3 y& Q- d Q6 W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + F( n3 x# V) D( \8 r0 k9 B7 q. |- v9 H
static void McASPI2SConfigure(void)9 ^% S- A! [" a
{
2 O) D/ d& H( M8 r2 P1 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ J8 B# h/ M0 K* J" i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& {, V: i4 B2 m% a7 Y' A, dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ U3 t5 @' a% S# }! VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 Z$ b S; D# j9 P, |; LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. t8 Q8 K" F/ k
MCASP_RX_MODE_DMA);
" j% \ f$ E" Y I, p( y3 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ \; j) A: ?6 d$ g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 K" N6 S7 ~9 KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . b/ h2 }2 O; C0 {1 n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; ~. z. f+ [7 X3 n) iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' G- ~0 o, ]* r3 A8 n' I9 O) @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% A2 ?3 G p, N9 c9 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% m i9 n2 s* {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 q- V0 k! C( _5 v7 O+ D7 h3 f" _% n9 ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, {2 [9 F# T: {
0x00, 0xFF); /* configure the clock for transmitter */
}' v' s. u m4 gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" m0 q' T" y% [& V- M+ K6 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / t# }3 @# u6 ]* b o5 }5 i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# n; t* b1 {- j2 Z
0x00, 0xFF);+ F- P7 ` a- i; w: n( n. k
: h" k$ v( O7 `/* Enable synchronization of RX and TX sections */ & l! ^: e1 [2 c9 ^/ f# B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 [6 t; q1 p. m8 OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 x/ Q3 V" V6 k! w4 O% B sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* ^5 @" r, Z- c# C+ g5 D** Set the serializers, Currently only one serializer is set as
' y7 o4 z7 m# n( i& E** transmitter and one serializer as receiver.
; E7 H; P# P W9 g0 s*/- h+ {9 m. s7 F2 @, Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% ^, M6 E0 r' n% V( m" j, V* dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% n. R5 b8 }& H1 O; Q7 {
** Configure the McASP pins
- f/ l, p! r# ?% o. N/ v8 s** Input - Frame Sync, Clock and Serializer Rx' W; D+ I# R/ g2 `; B ]
** Output - Serializer Tx is connected to the input of the codec
0 I$ g" E& O9 l" c# D$ ]/ |/ q*/! q) b! `9 |0 m0 H! j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 u8 y H; F; n% F3 W9 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' b0 l% f- J$ \+ N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; ]' {- B2 ^ ~9 z1 C' Q; q5 ?| MCASP_PIN_ACLKX: D& }& n( S1 v1 z
| MCASP_PIN_AHCLKX
% i( ~+ H/ C+ X6 i$ ]3 ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 a v- ?1 A9 P! s3 PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / x. t1 J' j$ T F8 B: m# |
| MCASP_TX_CLKFAIL q* Z" x4 T* v8 ?4 R/ J
| MCASP_TX_SYNCERROR$ W' x3 H5 Q# \: T+ e5 E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / ~" U7 u8 }* e3 U9 o
| MCASP_RX_CLKFAIL9 f% N( ]+ {9 A# j( G3 {* n# k) J& \
| MCASP_RX_SYNCERROR ; U* Q- Z8 r( W: X, R7 |/ R5 D
| MCASP_RX_OVERRUN);. `! @, B \% a" b' G
} static void I2SDataTxRxActivate(void)
/ n. C# h6 e4 t( {+ Q; l{2 `8 B3 v# m! K
/* Start the clocks */
, M, h, l2 b7 w2 JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 b$ U0 `% g2 o9 R3 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 U" `4 g" m& o/ ^# ^3 m5 c9 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; d+ P4 K1 K% o+ M" ^, U
EDMA3_TRIG_MODE_EVENT);+ {7 N, M' W6 \+ e* U4 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 p* {* n* d( |6 g9 \$ o( r1 v0 C2 cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ J2 e* m. A7 S4 ?' W/ V, iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ _; V6 ]; W6 i7 v0 f( Z5 b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( q* g( S/ ], {4 h. l% T4 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 |" f3 D8 b) O+ v* \- _% r7 w9 n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 `" ]8 z( V, {! F$ J. T. PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 l3 p3 ~( Z' R! ?% B1 q8 S} ( M( W& V8 o4 l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 x5 p' K( o% b
|