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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* F+ i( @1 J; Q2 uinput mcasp_ahclkx,0 B+ S% o" o) Z% s9 Y
input mcasp_aclkx,( o, O5 c+ D/ p
input axr0,. L n* I& i: t [! Q
' Q8 G7 A8 j1 Q/ y8 Y b7 o0 K0 c
output mcasp_afsr,
2 L$ G8 T" e5 T" ~5 b. w( y! L/ L$ [! voutput mcasp_ahclkr,
& Z1 _% E( n0 T* ^. \9 T C0 Aoutput mcasp_aclkr,5 {* c5 Q3 S. Z- I- W1 j
output axr1,, p5 P' B6 D; H8 ]( l$ B: r2 c
assign mcasp_afsr = mcasp_afsx;' t# W2 \) a8 _- U# G1 L
assign mcasp_aclkr = mcasp_aclkx;
3 N3 ]8 t3 E( Massign mcasp_ahclkr = mcasp_ahclkx;
a* Y; I0 u \4 \' J' Massign axr1 = axr0;
: H1 g8 m# Q/ q7 Q5 L
1 p) r. t1 u- `3 J7 ^* g, ]( R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - Z. h. q1 j- O( v4 r
static void McASPI2SConfigure(void)
3 J1 |# n0 j. i, C{
! X0 C! o* g: x$ `McASPRxReset(SOC_MCASP_0_CTRL_REGS);( u2 c: ]3 S( O G, {2 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 p# `, G* N( ]1 T3 ~# z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 E' E3 @1 g) uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 V: \1 P- ]* n9 x0 k5 k. n4 ^1 HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. K& ]# T% X! \* n) e
MCASP_RX_MODE_DMA);0 Q, S! b: [; K7 K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& M# C, ~9 L& c$ O7 N' s; i; Q+ E5 iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" e# U3 \ k, gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " X2 Y8 o; R3 X+ P0 |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 a! A; n, m, h8 E% x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * p( P$ O3 M1 u" A$ y7 S5 ~8 I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- |2 ~0 N# Z8 EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" C& ~) G s6 W; X, v# r9 m& `: |) B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: j2 e. `" u4 ]( EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; v) E1 Y# i2 ]' l0x00, 0xFF); /* configure the clock for transmitter */
y4 K7 g, z2 kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
d' b9 x) f$ n8 h5 ]- iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, Z) Z) ?7 \ U3 F' ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 F& i. C4 k, t( H a2 T0x00, 0xFF);, n* O( q1 l" e; T3 Q
6 { R( G3 e+ w0 u6 ?/ v$ e. y5 H/* Enable synchronization of RX and TX sections */
! i7 v) j0 z* i' I9 v2 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# ~! [1 u C& X q% Q/ `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 s$ n1 h4 _) {% M0 W3 l" QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** ]; X( m3 P* M' ? \5 {
** Set the serializers, Currently only one serializer is set as
% Y7 w" S: M, Q: o/ J$ q" F** transmitter and one serializer as receiver.
+ b! H; S1 u) d. T. s# G*/
, j$ y% z- K N* L/ m, wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 n' ]! Y5 u6 a b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; j0 e. ?# Y; k0 p. l3 E5 q** Configure the McASP pins
1 A8 ]- r, ]/ o8 s$ c** Input - Frame Sync, Clock and Serializer Rx
0 M2 I. \! Z6 l5 P' [' Q1 v; f** Output - Serializer Tx is connected to the input of the codec
W0 k3 u( B- j8 {$ N*/5 d; n, v4 K" A3 _& b* r. e1 y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! o. _0 l2 d VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ e. B% G1 o8 I- _5 {# r* I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- O/ R+ [0 w- o1 d8 y| MCASP_PIN_ACLKX
3 d- d L! X9 a) \$ S| MCASP_PIN_AHCLKX7 P2 p: v- {! u9 h0 n# ] x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' u8 a2 E$ }7 K3 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! e& [% n. X0 {$ l$ _0 t
| MCASP_TX_CLKFAIL
/ Y) D J; N1 L, l# w- e& K8 D| MCASP_TX_SYNCERROR: w8 o. x" @. O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, E a o$ {, B0 r| MCASP_RX_CLKFAIL
0 y: v/ g& \3 g& K/ t| MCASP_RX_SYNCERROR ! ?1 n k9 m W5 y
| MCASP_RX_OVERRUN);
) r' {2 j( j, m9 k- }} static void I2SDataTxRxActivate(void)3 |' p6 c w( m! ^% H5 X
{, _+ J+ \9 n8 F, S" b1 W3 N
/* Start the clocks */
/ R1 N7 p# ^5 s/ ^# G2 v, sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; w/ l/ Q8 |$ j9 [" AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: _% Y5 v1 Y4 A/ C8 q" Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& F! n( `5 U- c. N, m* U2 J4 HEDMA3_TRIG_MODE_EVENT);
% m# |" M$ d: B. y. u6 H0 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 Z% @- ?1 @2 F( s5 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 e1 M. u5 d& n' o- j% Y+ \ aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: X& I Q$ |, a0 ?# H! X6 ~' \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 [2 [7 g& L2 d+ `% h$ P; T. Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 u3 X0 R V( ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ m1 ~* Q! A3 N* d$ |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) }6 a1 P! G1 ?* R5 E5 O3 `} : K4 B" D! D" k. |; \8 v' {' U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 P4 E6 P N. @
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