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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! Q& ]+ q8 B; U! X binput mcasp_ahclkx,
' ]; d, Z4 q W9 sinput mcasp_aclkx,
* J" P9 F1 N. h- T4 Dinput axr0,
! ?2 E6 g' e `# ^# I7 L0 q- L/ w/ _6 Z4 \/ D) R9 r
output mcasp_afsr,$ i0 Z/ n8 _9 U4 ]
output mcasp_ahclkr,9 }3 Q2 X1 |8 ~' e
output mcasp_aclkr,
2 Y" w6 Y) `; ^ k2 j" U1 [output axr1,, W9 D+ B. V5 `; G/ r
assign mcasp_afsr = mcasp_afsx;
6 R& p! z5 j- S/ Sassign mcasp_aclkr = mcasp_aclkx;1 [" t( b( R' p% i
assign mcasp_ahclkr = mcasp_ahclkx;
- M. Q% `& j+ {8 k) e0 Jassign axr1 = axr0;
) d7 R0 }+ m2 m& _9 O W+ w, R' c$ y j4 J5 ] z) M# N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 k3 U8 A# D- i3 n& k e9 Ystatic void McASPI2SConfigure(void)* _" E' [ a# C# E& _
{; ?3 C( |$ c7 Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- u8 v/ `7 g/ n) M: L* q0 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( G( x% w$ h7 M- t% g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& k5 Z; L8 {4 a$ h$ a- X0 YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, r0 H2 j' U c9 Y9 k" u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 S1 W8 _" t9 r. @" |MCASP_RX_MODE_DMA);
# k& K+ h. e& GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; r8 b: g) |0 \- L$ z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 O, J" C. L4 V, j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 }/ k+ Z6 E; J; \( G. u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ @6 ~' ?3 P! z+ IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - q, e. d+ h1 A8 t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 y4 Z1 E' _3 H" c* E$ dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 X1 g* A) `* }2 k5 P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! e0 U H* a& Z+ uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 O. m; J. x* \, n" A
0x00, 0xFF); /* configure the clock for transmitter */
5 D8 G- v' D Q5 ~# FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 x, m3 M, R" w6 m: QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; E. k" t b% [: t" y2 t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* s4 W% b/ z, N% \8 O3 \9 B
0x00, 0xFF);; ^7 Y+ j- {" f& r( x- \* H
* g. Y% P- N% i" |
/* Enable synchronization of RX and TX sections */
, m# W5 r# ^& t8 ] i/ zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 \. }$ r( J- r& M2 z" j b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& C4 X7 u G; b& |' t* _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* g; d5 w ` t S9 w8 V0 n' ^( l** Set the serializers, Currently only one serializer is set as. v+ U$ f- H9 u) P) u1 J' Y
** transmitter and one serializer as receiver.5 I& E' u; o6 ?, z) o8 ~
*/
. E" c4 m9 Q: AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' f R/ ^& `( D/ `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 ^! Y6 k: Z. c7 K& g1 g
** Configure the McASP pins
' s- S( P! h- r' s. a9 `2 D** Input - Frame Sync, Clock and Serializer Rx
* x7 K& g1 ^6 g9 w3 ?0 }** Output - Serializer Tx is connected to the input of the codec 6 s* y/ G. u# _; |7 r9 H( C/ }
*/# Q3 f2 }1 A& M# @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 g3 Z- m; l; L' m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 z6 x9 u' m5 D) n5 e5 o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 u) O/ M* L- ~" T1 X| MCASP_PIN_ACLKX% T' |! D2 C/ Y% E/ a
| MCASP_PIN_AHCLKX
& r- p: D8 z2 @" Y5 b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 s5 Y' g$ E* `( G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' {" G2 w" ]8 Y' F+ @* W3 y| MCASP_TX_CLKFAIL
- h6 h4 Z- }8 t3 _$ d+ \ U| MCASP_TX_SYNCERROR2 C! F: g% ?* Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 V. y+ n' I) L/ p% o9 X/ y| MCASP_RX_CLKFAIL6 ]4 J5 O: a* B5 ]; Z% H
| MCASP_RX_SYNCERROR 4 j8 H L$ ~4 \. W2 n) l
| MCASP_RX_OVERRUN);
) M( N A7 B2 J# X. R$ E2 s} static void I2SDataTxRxActivate(void)/ ~8 Y$ w+ G2 y% U# B0 J9 V9 ^
{( j* d$ ?1 N* T, N
/* Start the clocks */
# D1 h1 i r. _: T! PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( b1 G2 f# h& gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 |; ~# u0 F# Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 j& U) X8 i' E/ c9 n
EDMA3_TRIG_MODE_EVENT);
+ m" i7 o0 T( X- |( W KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: P. g5 p/ d$ }6 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" u7 Z7 M1 a+ E' B4 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 y, T! F3 X( c4 t0 e# S! K6 {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: o" \- }+ e2 w b n2 i+ Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ }% N, [& h) H$ o7 `8 YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 t$ ~! k' a" x: d4 p: G- K( HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 P( S9 P. e( ?& p* H! Z} . c* a5 q' X( h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - i y% l q5 G0 [* \
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