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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 q( U, I6 L- d+ Linput mcasp_ahclkx,- Y P' F$ H. s
input mcasp_aclkx,! w' o0 Q; R( s4 L- A7 o
input axr0,
# W2 T' J/ o: K- C% {9 r: O: d' j T& F# a2 q
output mcasp_afsr,5 v9 g# k9 A0 n: K
output mcasp_ahclkr,
' `& e( Y3 T2 uoutput mcasp_aclkr,
4 P3 m: t% S* F3 I( Y- n2 Qoutput axr1,
. ?8 @# @0 y1 N! o/ L# M; B* E assign mcasp_afsr = mcasp_afsx;# i! J8 N' b1 m- ]1 s9 d! ~
assign mcasp_aclkr = mcasp_aclkx;3 K5 c3 C% n1 e7 e
assign mcasp_ahclkr = mcasp_ahclkx;
0 M- Q3 p) G2 Z0 eassign axr1 = axr0; - u9 B4 R7 p1 u+ z. C' R% g
7 O3 S/ @ s4 u% z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 p) x. P# J4 H$ u0 v- M: R, @' g
static void McASPI2SConfigure(void)( H0 N1 h y9 l7 d, o
{
/ F7 ?$ H: L; \# OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
_, x/ S% W% X( y, c9 @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" h: _, z8 X7 L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 \2 V( H" c& V% K; ^! D9 n: ^# FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% h$ A3 W6 Q+ @0 S& h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 i. O# H8 `' u, a$ I5 tMCASP_RX_MODE_DMA);
% A7 X# N9 q3 b# YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- _7 Y: {! x6 z. `1 X+ q' ^! _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; f1 K/ w* \1 rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% }0 |' @" t! k" Z3 SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: @# u: O4 T2 Y) t2 \" A# L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" C' M% m. f! r& G! nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 w7 B* V# e4 V, LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 u6 Q+ N6 q0 H( O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 {3 }( }& F8 D2 n1 L6 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, W- D _- }) M3 a: U2 d
0x00, 0xFF); /* configure the clock for transmitter */4 t# K. w8 i6 X1 X" O4 L* {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* d; y$ l; M' L z+ HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- n5 v+ [, W5 L0 o3 O3 R( qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. l. V0 z# z! ^: ]
0x00, 0xFF);% o8 i g8 i) { D
/ A& g+ j* ?) F5 i! u# n/* Enable synchronization of RX and TX sections */ ! R1 O6 H4 E7 r1 t L; [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# z0 Y1 \ T. X ]! D# IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 c+ h( w+ H) c QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; q ~" ^1 u/ G( ?, [" S6 X3 }& _** Set the serializers, Currently only one serializer is set as
) F; k0 \; L& a6 ?** transmitter and one serializer as receiver.& [! l3 S1 S3 S3 g9 o; P
*/
! r/ t3 f+ f3 `7 P! `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 I$ {$ X1 G5 m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) v5 f' o7 l3 C5 C4 _0 F** Configure the McASP pins
( F, V& o) O6 e( D5 _** Input - Frame Sync, Clock and Serializer Rx; ~& C" ]" n$ E2 `
** Output - Serializer Tx is connected to the input of the codec
( N# n: j$ P3 o8 y*/: R1 G2 ~" P: O* d' ?2 e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 z6 S* E7 [3 d/ ~4 C" s+ _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 o+ @" {9 z( B7 `/ z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; `6 i4 D$ Q+ s/ R2 A3 F+ U
| MCASP_PIN_ACLKX1 j$ g' e8 B& r( J
| MCASP_PIN_AHCLKX
4 @0 k# n" x/ t6 }0 h8 a% {8 m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 u0 h9 c$ m8 s+ p& z Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) r9 ^1 m, ~- z6 y9 g4 b| MCASP_TX_CLKFAIL . T. {& l7 Z5 h; X Y& U( B
| MCASP_TX_SYNCERROR
; `( g8 k# [7 m: Q4 h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' e4 N( Y$ }6 `5 |+ j: a/ v" N| MCASP_RX_CLKFAIL9 T6 k4 \+ j. O# P& w# ^: W
| MCASP_RX_SYNCERROR
3 e& y1 O7 _) d| MCASP_RX_OVERRUN);4 H8 i) I9 c9 z
} static void I2SDataTxRxActivate(void)8 t" w {0 e8 Z% f0 B
{
4 s4 a8 D! E+ u4 L; ^$ l; P& m/* Start the clocks */6 Z4 @! l1 l0 Q: l5 ?3 W; t m T5 p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ d5 L0 Z5 ]7 o- N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 V7 p3 X& x: c! {0 }( wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- M( l* F, D% O i: rEDMA3_TRIG_MODE_EVENT);
8 U& `6 T B' `2 Q: hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- ?9 W# S5 X7 z; m* w/ y2 d% }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 A- A+ y3 H. S$ M0 r( Q$ S$ R1 wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 K8 e2 F# ?$ X0 z, i) k3 @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 M6 c1 \& |+ K5 M7 j0 N* ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 f- [4 s& Q1 {8 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) P) U3 k1 F. f! |* lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ t( Z: f# N5 B+ j0 k}
" |4 N# Y4 z+ X" {# ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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