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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ k/ ^+ H- F( K
input mcasp_ahclkx,5 E9 Y, z( y& K
input mcasp_aclkx,0 C( \6 T3 |" c4 z8 r
input axr0,0 o. S, X8 m4 J, v! p# O
. d$ D2 y9 }1 x9 s1 M! _! E7 h7 uoutput mcasp_afsr,7 \# ^+ W! ]$ ~* T& K9 G
output mcasp_ahclkr,1 F- K( I1 a! [
output mcasp_aclkr,; U" X% }% O" e: W" [# F) K1 {
output axr1,9 D8 y1 c+ w& ^3 `1 o
assign mcasp_afsr = mcasp_afsx;
) l* e& m. c$ O6 @' S* Yassign mcasp_aclkr = mcasp_aclkx;
/ ]0 K" c7 G! N. A/ sassign mcasp_ahclkr = mcasp_ahclkx;: q) [. g" o0 D/ Z6 j6 V
assign axr1 = axr0;
8 l- u3 u- t2 U7 r) T) d# G, W/ ?# V. I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 v4 x6 C; d! b# Y2 z
static void McASPI2SConfigure(void)
* ]; x* H+ y3 D/ ]* C, e# V{3 n' A9 j2 Z- l$ F0 L0 `+ s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! v: L' ^/ m& x0 W( j. P6 u" M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 X" x& A' J9 K% V: w2 S1 m! Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 g0 D/ ~7 Q {; t: Z: A! N8 J2 v- WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 N0 h6 t- i, ~5 f; L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& R! w$ S; `# a& V' D% J5 S1 L
MCASP_RX_MODE_DMA);
0 Q7 j, T$ g( V; y4 H0 e# U7 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 p0 G [7 v, P. i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 X2 k( i- d: j( D9 x {6 I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) A5 }- U7 n+ W# rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 ?% ~/ }0 P. w+ ~5 K$ z8 m" y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : s5 H4 ?% \$ b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, Q5 c3 x6 T' g- E K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 L$ ~$ u3 M1 T! OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 s/ w2 z9 Y' p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& A! [' F1 w- X8 w/ m
0x00, 0xFF); /* configure the clock for transmitter */
6 D! ?/ L$ \. ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, h) @ R3 D9 G1 w; V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 ^. {* A8 D5 c$ f: w4 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& B; }( q5 {8 k1 _( L4 [3 y$ e
0x00, 0xFF);
7 }9 e, o* r" I- h1 I$ g
) E) D1 D8 K5 W- \! a* J/* Enable synchronization of RX and TX sections */ % M9 T V3 i: l8 A# f3 ^+ v# G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 n# V" @5 d1 A& L; F0 s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ J( T( M7 Q% G: V$ rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 C1 n# _0 n2 j** Set the serializers, Currently only one serializer is set as0 K+ _. t$ H; x; j" N$ P
** transmitter and one serializer as receiver.
; |( g% a" V; K*/
6 j$ S7 F+ A3 T: y. W9 fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 | f) K7 f9 L: [. N3 m3 }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ ^$ Y' [/ z- J% O7 x/ ~# H& c
** Configure the McASP pins
: h1 F" }% F r3 B4 X** Input - Frame Sync, Clock and Serializer Rx
5 P& M9 A9 T% k4 B** Output - Serializer Tx is connected to the input of the codec
4 G* N* f4 l1 {9 V*/
4 Y: o/ W. I7 UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 v) _* T$ m$ F. Q$ |! y6 M1 L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ a& m1 X# o5 j6 o ]- J1 u/ i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 H! O% J0 `; Q; F X0 `" U| MCASP_PIN_ACLKX7 A2 E, q, J$ e
| MCASP_PIN_AHCLKX
, R3 M% B+ P& Q8 D$ G7 `5 {% y/ K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! Y7 [% n- F' @3 R5 eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 Z$ i% C* y5 K' p# w, l
| MCASP_TX_CLKFAIL . Z w) d/ Q9 a0 B1 j, u+ M0 ~* T
| MCASP_TX_SYNCERROR$ r+ e5 J, d, f# x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 P' G: |. z+ S2 j2 Q| MCASP_RX_CLKFAIL
; A' J5 w- @' l# m7 r. } J4 z( C| MCASP_RX_SYNCERROR 5 W& ?2 c+ }, S, a' P9 X
| MCASP_RX_OVERRUN);
8 L/ b- b- l% d/ n, j} static void I2SDataTxRxActivate(void)
# M& O J0 i$ t9 L{
! ]2 m3 [3 E. l/ n# N. s: H/* Start the clocks */
2 Y8 ?% R0 z+ x$ A# p9 a0 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 ]8 z7 ?) d6 M& A! ^1 }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ d4 v L( D: U8 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
n7 v7 \* @9 X* e" U8 ]EDMA3_TRIG_MODE_EVENT);
' K9 b" f% ?4 y9 Q# P8 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- J, ?0 E5 b! z( vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 f1 c7 B, _& u! SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); U% P/ w$ C& i; u! F+ v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- F8 c+ m* r- o3 A+ z$ O7 \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' \( u# S A Z. C2 h& c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 K+ X' x' |* M4 E) tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% a+ \' \% e" ^4 S* c} , f3 V+ R, r) B+ A. E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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