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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ _ L; P2 n, d: L
input mcasp_ahclkx,
3 U6 j6 |3 i4 l. h2 }7 g8 L+ }0 ginput mcasp_aclkx,
" C! ^9 `8 i! M' oinput axr0,8 n2 ^. p v; Y. E1 [2 f
3 q o4 V# X( ]output mcasp_afsr,
9 Q: _1 E$ l6 q. _4 Joutput mcasp_ahclkr,1 E7 ~3 x; b1 g: N5 x
output mcasp_aclkr,
$ M# l+ v8 ^$ k; E& koutput axr1,) h, h6 D3 f4 q# `
assign mcasp_afsr = mcasp_afsx;
& z; K) @, y5 H/ _assign mcasp_aclkr = mcasp_aclkx;
) B( Z4 F- I" _$ v0 f- Uassign mcasp_ahclkr = mcasp_ahclkx;2 H' ~* ?5 \% e: F8 O8 f
assign axr1 = axr0;
3 w- m* g$ p$ F0 Q# C* x) ]' R
, w# X+ n8 h- `& X. D4 _7 P0 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 }0 J. l; ]# e& f2 Y8 R, S% V1 e
static void McASPI2SConfigure(void)
, y2 ^* n+ | h6 {{
$ X y& c% Y& L3 \' W& A2 r* oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' j4 M0 [- D" ^6 U1 V! U3 OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% `$ ^! T, i9 J$ B( g! b, t
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ v$ T4 g; Y g1 a2 WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 o" W* s+ M+ e/ H0 `3 g" w% qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: N; ^4 z# x; f& F# r: f+ A! OMCASP_RX_MODE_DMA);0 P2 E& r7 M N8 Y0 `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," R. H6 e. M8 D4 X: v4 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ A/ D- }- M9 r8 V6 jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 _5 E. M T/ ~ V8 F) UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, c3 W3 s! M# y8 k4 U, b$ g3 ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: P G4 |2 ]3 K9 c! V; sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& }) ?+ }+ X. |/ E6 n, e5 c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% _. Y" E/ E$ N) P" x5 V' [- lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! X" B* u+ ~' X( R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# N) {# z! r: \1 s( B2 ?. G' V0 H1 |8 T
0x00, 0xFF); /* configure the clock for transmitter */$ r1 w) b+ a( h% S- U. C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# r* V6 S9 f0 f0 H' f& F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - q ^+ G, s' k+ Q6 R6 Y3 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. X I! d% f$ X- [$ q
0x00, 0xFF);4 P& O; W% E, L9 |& p0 J1 }
4 F. m+ P, o W ~+ k) h
/* Enable synchronization of RX and TX sections */ 1 t3 U8 d2 U, {, K& B; h" \! i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" t ` K. z4 Z5 J! LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# z$ `& U- p& p% fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** h( J4 |# [9 q
** Set the serializers, Currently only one serializer is set as
, D0 y7 J# S7 T$ N, b( l6 U** transmitter and one serializer as receiver.
H, Z" t8 h b5 f& ^9 D$ p; M0 }8 `*/
+ R' b i, n5 ~3 TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 U" a3 n5 ~% j( T6 H0 D$ b6 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; r9 j e, v* \3 ]0 R* {' t; N** Configure the McASP pins 5 }/ G. v7 Y0 h8 }$ y
** Input - Frame Sync, Clock and Serializer Rx
7 t8 ?+ F8 C }$ h! e" d) S** Output - Serializer Tx is connected to the input of the codec
7 r9 M* L. i: S* K*/( D# X) f* U& k& ?5 Y! k' ?8 d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 {- ? b. y0 Y8 ?. l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, w% F1 r, A+ K; F% r$ JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& ~$ y) D2 @7 J+ ~( r3 N| MCASP_PIN_ACLKX, B2 `& u( _* H& \. I5 @- [
| MCASP_PIN_AHCLKX
( o$ z3 l, t9 N% P: h; ?8 C: t8 R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( Y( P; w7 P# ~9 E) m+ HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 ]( |5 Y4 e7 a1 | Y
| MCASP_TX_CLKFAIL
% w; k g) e9 ?9 J7 h5 Y. d" y| MCASP_TX_SYNCERROR' K: i) G( D, ^0 ^) `* \. S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 o" U( K, [1 _* {7 G7 l( \
| MCASP_RX_CLKFAIL* J4 p2 }3 \0 h
| MCASP_RX_SYNCERROR
* x/ x" A+ \: U. S& b5 i& e| MCASP_RX_OVERRUN);7 x( ?2 ~7 ]3 e) k0 G; k. J7 t
} static void I2SDataTxRxActivate(void)
( G+ z! O; U$ q6 t7 b; G{
6 p, A: z# u4 w: |1 P6 V/* Start the clocks */
# Z H2 O& a2 D/ y& `4 A% x) ?' yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# w( n% g# f# \6 k+ [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 ?9 f+ C# |) p+ j wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; ?6 j+ }( ~, j
EDMA3_TRIG_MODE_EVENT);
/ T! } ^* o8 R7 H! S' zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- ~ m1 e( J0 Z- |) k- |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 K$ B) n' W3 d& D7 g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 n' |& N# I6 n& L. ^( eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& B! Q7 l/ J: X$ a; `, o( v( m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 N6 q$ _0 s5 T1 ?. ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; S& r0 D/ h# d @: Z6 G' ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 F# a x( z0 I" ^+ b}
. g4 o6 v3 J- q; N$ ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ ?' Z% X. a& q3 l8 Y; M0 F- n
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