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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," D0 H1 Q% i" \4 h
input mcasp_ahclkx,3 H8 Q' ~+ Y1 f2 N+ R
input mcasp_aclkx,
2 a8 S: o' h6 K, Z9 ^7 Zinput axr0,. J, P) u! N: b8 _: G2 K6 l
; N( ^" Z4 \$ u l' Houtput mcasp_afsr,
; F- B" y \( Q+ m0 V0 P0 ^output mcasp_ahclkr,! U [. G9 Z0 T
output mcasp_aclkr,/ m) h& c r: }* m
output axr1,, m/ |# {8 D- }/ A- |6 n8 Y% f
assign mcasp_afsr = mcasp_afsx;' U& k; s( k+ u) M `
assign mcasp_aclkr = mcasp_aclkx;
( J) a( s _6 F* ?% U; Zassign mcasp_ahclkr = mcasp_ahclkx;9 C6 `. P7 t) t0 V
assign axr1 = axr0;
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# J% ^" l3 \. s! ]: m; Z3 N) o# t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . u5 s. o& e- q0 e; G
static void McASPI2SConfigure(void)- f& O; p. k2 Y% `7 [1 d; r
{$ s; B& F4 r- m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, b; @# G* T3 J9 A& b* u1 E3 NMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 s, m3 P7 X, q, f1 X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% j3 S* b4 J6 o* Q# J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' r+ q: O+ C8 q) U; y$ Q+ nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 D0 o q6 ~% O2 R
MCASP_RX_MODE_DMA);- n( Z; b6 x7 _# E2 @" {7 P$ g) o; C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# L- y5 E0 V0 D. A1 J+ r: |: ]. eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 W7 d/ T5 [. I' }) K. _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & i% h* [% |% T6 Y. t/ T( x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' o5 L9 w+ A8 A5 G; V& C3 K* W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ T- E, w1 W% O9 h- K% qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
K6 H) o- r6 X. HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 T: S9 l5 h; P8 V4 V; O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* v* e3 P( a5 _8 t' \! R3 iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, s6 G1 {6 P8 S8 I+ p' A# B& z0 G0x00, 0xFF); /* configure the clock for transmitter */
5 A: H v+ U& g7 Z* f$ x1 \2 T* UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" Z* \& q. i# r/ H2 i5 ^0 a' V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( X: m: i7 ~: B0 x1 C) e4 K1 cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% O ]5 m) k( G5 B7 F/ r* J
0x00, 0xFF);( \/ A9 M" q% E3 p! {
- c. c$ Y: _) o# n$ a- [/* Enable synchronization of RX and TX sections */ 9 }: u, r8 U, R7 b. N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 [( k. ~/ {- H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% L) m4 z. b* m. V) _0 L4 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: J- W8 \. z7 {& ^: z$ g
** Set the serializers, Currently only one serializer is set as% o" L A+ a6 p* E$ z! ~
** transmitter and one serializer as receiver.8 l9 D+ {2 p* K+ J( q2 b3 S' v$ f, m
*/4 O6 I9 @3 u+ J& S3 A o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" C# t7 g6 B0 j vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# {5 v0 A+ q6 S) q( b5 s** Configure the McASP pins
, N c1 D/ q I T** Input - Frame Sync, Clock and Serializer Rx
9 U; F! s) z& n** Output - Serializer Tx is connected to the input of the codec & [' w# w" A& W; h* b. q, ~
*/
5 N. b y _7 V% l% f: bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); ]" O8 i$ h b2 J; D3 S5 a+ E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& V* D( V, m, ~/ P% o; ~2 |. l& E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; r6 P) X- }3 j5 z o# h& E| MCASP_PIN_ACLKX
0 k, ]0 D1 ^ T A b* x: K6 c| MCASP_PIN_AHCLKX
' F3 {9 {8 i2 B- ?$ k/ x) U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& p. U8 x1 D& x( ^3 o) k# V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR u4 P& o1 [0 R0 t1 o2 ]# f+ L
| MCASP_TX_CLKFAIL . H9 \) D4 D" s& y: g. G1 |& m8 `1 b
| MCASP_TX_SYNCERROR
9 ~. r: S( w3 i ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 {( D% y1 y9 M; V# m| MCASP_RX_CLKFAIL
: ~5 R+ m* l$ @; S& ?+ e| MCASP_RX_SYNCERROR
- w# Q- t' ]) k' S6 | h" ?# ^| MCASP_RX_OVERRUN);3 [- N6 N9 ?/ l: ?/ U
} static void I2SDataTxRxActivate(void)
3 O/ h% [) n$ X) b) R6 w{
! M3 d" B4 v5 L7 F/* Start the clocks */4 G) x/ m. t& P+ R6 Q5 y1 N2 }* B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' x$ t/ R: G% e8 l/ K. R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" C' n0 d, t2 b/ _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 f3 {; H- ?6 N5 n1 i# i2 k
EDMA3_TRIG_MODE_EVENT);& x2 G6 U N7 V6 [ r+ m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 R. [' m4 ^( R4 W/ K C2 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- t, e) q7 M5 v$ h9 P" X, P: x- B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- U# s( U2 H7 {' k1 l4 m5 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ ?7 K1 J* j# g4 {8 Y3 Y( g8 zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; A* j$ u& M7 J a3 B, y) _9 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 i) c' Y0 E5 _3 d. r# z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 h5 s7 v6 p0 F
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