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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 C) K! f6 {" ~ {- p1 [input mcasp_ahclkx,
- D3 ~, F4 ~5 R; r3 h' x+ T7 B# f" sinput mcasp_aclkx,
; {- P- J1 T5 C8 tinput axr0,' R {5 z4 u; i7 b/ D# D0 f
/ L& n5 N( P# z' a
output mcasp_afsr,
: \; ?- a, ~8 h/ Ioutput mcasp_ahclkr,8 N9 m9 V4 |6 Y! Q& H1 q/ f& F
output mcasp_aclkr,
! [8 J/ }7 `9 b Noutput axr1,
/ o' x% j0 `, `7 U) E; S6 m assign mcasp_afsr = mcasp_afsx;4 P' Q- c+ Y, \* Q( r; r Y3 v
assign mcasp_aclkr = mcasp_aclkx;- ?4 f; S! R" D8 E
assign mcasp_ahclkr = mcasp_ahclkx;1 Z% T' B# C& r
assign axr1 = axr0; ) O) o, o* q* p& \+ x- b; y+ B
) _4 q& d9 ]7 S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 N) ]5 G3 [: ?5 Q6 A/ |' kstatic void McASPI2SConfigure(void)
w* i; \% a! j6 F7 a, h8 p{
# J+ G. }' C! N) \! R; f& }. MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: d% k: K8 d/ w I2 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 a2 N! R: A3 U4 f" t/ OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! \0 Q5 _! e3 g" D W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ v7 D1 i4 {; Y+ ~) _2 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 M3 B9 C) l6 a9 ?( U3 p+ C) xMCASP_RX_MODE_DMA);
) p7 u6 ?* c2 W0 hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 @) f9 A0 ]" _! J, e7 @" @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& l/ s% J& l! j1 n- p' q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : Q5 q# u V u P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' }* ]1 A3 | `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 [& k% g' C7 Q% b, bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 O+ m( ?& @ W2 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- v9 m+ F' v3 Z. M" g0 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 j+ l, I5 i, \' L" V. jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 I0 f- G8 J2 F, y- F9 a4 l0x00, 0xFF); /* configure the clock for transmitter */
6 x/ O2 O5 J# {2 e) E2 z' RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 x% V8 V& k2 oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 k9 O. T! ?0 ]7 MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 ~. i1 A4 V; k4 ] L( ~1 o f* J
0x00, 0xFF);7 k7 }/ {% k% }* `( [1 u) }
7 N$ w$ ?. w2 X+ r1 g; o$ D! A/* Enable synchronization of RX and TX sections */ 6 f( b" l, ~# s& ?& S% y% v+ T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- F* j% \/ C+ ~) i/ _5 [ FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 v9 k @+ r7 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! k" Y- e; m0 |$ d6 \6 ~
** Set the serializers, Currently only one serializer is set as. h+ e; F0 u3 e. E. {
** transmitter and one serializer as receiver.) _( H" X' ?8 X" X2 }5 G
*/0 t: w, a% Y% ~$ y* A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 P `, r a- @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 F* h" J. w+ U. Y8 X. u
** Configure the McASP pins
. t# A' O: k' b+ h** Input - Frame Sync, Clock and Serializer Rx
0 ^, o9 X$ i# z: @' }5 T7 z3 W** Output - Serializer Tx is connected to the input of the codec
; x$ q& e2 s6 L( _, B*/" u9 l W1 o% Y! ^7 ^/ p0 H# c% k5 _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, H% q6 `0 @1 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 Z% Q6 t) ?2 o: B+ ~8 M; rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; @# L2 G( N" v9 \& n6 Q| MCASP_PIN_ACLKX8 T3 X) j3 ^/ `/ V h Y4 U$ ?
| MCASP_PIN_AHCLKX
5 B2 Y J$ B" d% H6 `9 Z( g( J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 O h- K! t1 \$ @# O- p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 o( r7 x3 p+ ?7 m) C8 S
| MCASP_TX_CLKFAIL ) H# y1 C% r- u/ u
| MCASP_TX_SYNCERROR; V& Z, e+ i& S F* _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 }3 _* m# \* e# q9 c+ n| MCASP_RX_CLKFAIL
+ \$ V4 R4 f) y- n| MCASP_RX_SYNCERROR
: m: I0 n: g# T8 g7 o) s| MCASP_RX_OVERRUN);) z9 d* F3 E! D
} static void I2SDataTxRxActivate(void)' E U" T- r0 y, o8 V! `& \
{
9 \( ~% H8 k, W/* Start the clocks */6 P0 T6 P! j. m$ Z8 z& b5 @0 V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ Z; |, o/ q- ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# {! |0 \6 X6 `& o8 s- z: p$ P7 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 a7 z$ B+ T% w* P3 H" r
EDMA3_TRIG_MODE_EVENT);1 ]7 T9 ?# Y4 D* N2 t7 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 Z6 `" R3 ~/ F- l, A+ d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 L* |6 }) @9 p# e& p; JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; l) m/ @( s! I) }+ h- S/ \; z: Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( B2 d! O4 f/ c; I8 A) I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# z- G: O) [1 c1 ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 y( A& n" Y lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ b: u- y+ q9 I- `7 C8 v+ i6 j
}
+ {7 ?" k: u- ?( y/ Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 _" U6 o3 j+ Q Y: [* M5 y0 i" `
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