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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," X2 b- w8 w9 f% z
input mcasp_ahclkx,
/ L/ |: \2 X/ { |input mcasp_aclkx,
. m9 B+ a: Z2 m) t1 _6 ^; dinput axr0,
! g, O3 L& f6 Z# d, F
- O) Q- ^4 X: C* ioutput mcasp_afsr,8 W/ u$ a: T0 D) P1 O; z2 t
output mcasp_ahclkr,5 A& M% K @1 f+ o( \6 u
output mcasp_aclkr,
! O6 ? a. m. d1 ooutput axr1,' ~0 Q" `" G: D: X% F9 ?
assign mcasp_afsr = mcasp_afsx;4 C }# @* ^" [, J9 g
assign mcasp_aclkr = mcasp_aclkx;6 z5 S" O" K+ i* b
assign mcasp_ahclkr = mcasp_ahclkx;) Z: R8 f4 E4 V8 ^& j- C# t
assign axr1 = axr0;
6 a; C+ E$ t. G- Q8 Y' z/ s: N# I) y3 ^/ L+ m& ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 I0 V b$ C% O% s+ `0 d! ^; g2 x
static void McASPI2SConfigure(void)
8 S ] |" E y{, [3 w- i/ V/ `; v7 ~' T1 X* T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# L( m9 v$ m" oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 Y d N6 F( H( v' t
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% k& b0 R0 ?% Q6 ?- @0 {* F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ {) r5 c: u5 r2 ]2 e5 r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% Y3 _, p" {1 i( |( y+ N) KMCASP_RX_MODE_DMA);
! S1 ]3 |' f0 g7 k- K; ~ }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, P+ F3 ?8 ]0 b( x) p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! ?1 ~/ w& Q! ?; g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 u3 w. j1 i+ ?/ T8 b$ h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 @" k. b1 H6 A% V7 ?, ?9 IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " M n' P& v: m5 }: R e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# U' T6 }- O7 A9 N% dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 E4 T2 e+ m% T/ a& x: F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! f# l; f! W/ x5 a6 I( W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, f7 {* }+ J+ o/ H, H0x00, 0xFF); /* configure the clock for transmitter */) V* I4 q/ R L5 H6 `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
q' f: v- T6 [6 [3 J _% DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% F c0 @/ V3 x3 b8 \) E4 i6 aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% \, j6 Z e% O% ?$ \0x00, 0xFF);( F4 Q& C( `- y
" V/ S6 _1 \* ?6 ~/* Enable synchronization of RX and TX sections */
7 u, m* ~2 ]2 [! K/ D* F3 }0 t5 ]9 [/ SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 }/ l! S+ T! B# Q! g) M. o3 P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 L& n; N4 s: A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ X- x+ N6 S1 b% x; j$ c( Y5 L** Set the serializers, Currently only one serializer is set as4 F8 D% t% N4 |0 Z* `
** transmitter and one serializer as receiver.
4 c- s! B; s( b0 o. W, S*/
" N- `) N' Y+ _! ~# q$ G: ?* B5 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 Y/ f+ {- {3 b5 \! Z. P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: F1 L, {4 F) ^* z) t* ^ S7 m2 I5 D
** Configure the McASP pins
: a2 f$ S9 P6 {7 ?; N! I: x* r** Input - Frame Sync, Clock and Serializer Rx
& q7 V/ q$ @9 t: g- e7 Z' k** Output - Serializer Tx is connected to the input of the codec * `% ^# @( ~1 H# w7 s
*/
( f- r7 D( Y3 q+ I w2 U# g8 ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
n$ B( ?9 o8 p( AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 z! W2 P' X! i5 Z4 N4 F5 U1 o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% K- ~: s! | S8 x' q| MCASP_PIN_ACLKX
5 ], w. ?2 X& Z0 n| MCASP_PIN_AHCLKX9 O( {, C8 D% D1 ]7 t5 a: G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 A& G8 n. J. F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 J u2 G5 I& ]: @! f; ^: U| MCASP_TX_CLKFAIL
+ {' N4 e9 v* ]3 L8 N| MCASP_TX_SYNCERROR j: `2 D$ n: O; G: R8 {1 t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- o1 o$ n w+ ~| MCASP_RX_CLKFAIL
% N- r2 }4 _2 r5 }| MCASP_RX_SYNCERROR 7 q3 F5 _5 Q; A6 E! c: x
| MCASP_RX_OVERRUN);1 ]* C. l4 U: g
} static void I2SDataTxRxActivate(void)
! \& l5 A" H+ j7 w4 A$ k{
2 l" r* j; U7 M4 S8 z4 q$ O7 F/* Start the clocks */
" J9 f" `; w4 x% u3 z5 v# BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& B. S/ W5 M M/ w; P8 Y0 [5 |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 G# z+ W: S5 L& ~$ lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 J0 c& T% M5 u
EDMA3_TRIG_MODE_EVENT);
1 J0 [7 A0 \# N5 R g- Y4 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, ^' s$ x% P+ M6 \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# y2 N C/ J: ]1 p: Q- R0 {3 f- z6 n+ rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 ?; y5 K5 c1 R2 _6 b" X2 j1 j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 v% @) N* v' T0 T* o& q' g( F5 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# s$ b" L) N' q+ K" `1 ~6 i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' f& z0 v$ f& R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 g% C$ y5 S; ~: w} 4 L9 w$ _, e* `- Q6 w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 n# @$ _7 @' d/ [9 t8 ?
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