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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! p4 c2 {# e8 r. {. Xinput mcasp_ahclkx,5 b5 p/ U7 `8 z, i, Z0 H
input mcasp_aclkx,
3 M% j! |6 }2 V$ N4 J# c6 ^& K$ \input axr0,, i( m; N5 B, A# h4 I% z( T
- K; z* E' J3 V2 ^* N5 ~output mcasp_afsr,- G- ]1 A3 o$ G) ?( W
output mcasp_ahclkr,
/ G) X) Z2 w' p/ [* @. R; {- doutput mcasp_aclkr,8 X @0 l' j: d3 r3 L) o$ S' T6 d
output axr1,
4 D+ I8 x" N* {& ~9 }' W& b assign mcasp_afsr = mcasp_afsx;
7 F% X: [: i* E2 @2 |# L' Eassign mcasp_aclkr = mcasp_aclkx;
: }0 Z! e0 W" Tassign mcasp_ahclkr = mcasp_ahclkx;
0 E3 G' x- N% D0 Z3 bassign axr1 = axr0;
8 B3 x* F* @3 U* B1 Y9 D" ?6 f, |) g2 I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : L4 m |5 I. l3 t J5 p
static void McASPI2SConfigure(void)
: y. g1 f: ]" r{
9 r/ P$ ]& B+ ?3 SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( n8 p$ m# r6 S! z3 W* i1 p! |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 I* q f/ m! J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 C" e. T# k9 o6 Z( V2 LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ F" p& j8 g& d* L& P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- @" z. c5 q% \' u$ y
MCASP_RX_MODE_DMA);
3 v- V8 l4 m; h( GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 G% _) L, {: g/ q9 X: E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
T; _+ M. A- m. ?+ ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( B) |. ^- L: ]3 C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 F: X5 V/ q5 t0 L" b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 K$ A% E$ C( P' }) }5 b% [3 i% `, F' [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! v. Y1 g1 @7 j# [/ o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 k9 p) J! q3 e6 w( n$ hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 B$ [% F7 v/ A# g3 m' G# P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( ]; q* p" D: D4 d M9 L
0x00, 0xFF); /* configure the clock for transmitter */" a, |0 W8 c# x& T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 }7 s, t/ e/ l+ ~3 n t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 F8 j' |* y' J! L. P7 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: N. {/ y/ T: [7 {1 ~6 g" i* T0x00, 0xFF);% }: ^2 t" M9 ~
) g4 V/ g+ J Z7 h; O9 p0 t# F
/* Enable synchronization of RX and TX sections */ 8 @% f7 @2 {! Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" N9 m* p) a7 x9 Q4 R4 X1 L5 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 R3 N! t+ G5 P8 p* k( h2 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' G2 t, T4 H. a9 u" Z9 ~, W& v
** Set the serializers, Currently only one serializer is set as
; y/ x+ @& o+ I- v2 b! X ]0 p0 q** transmitter and one serializer as receiver.
1 y/ b3 v0 h! F*/
, F, f4 N/ r. ?3 R$ `2 e2 X8 aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 k Z% n: H& G3 W" [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- N' S6 w7 `; S9 v
** Configure the McASP pins
8 m; `7 X' v& _4 l. S& W+ R** Input - Frame Sync, Clock and Serializer Rx
% S4 x* w" s2 ~1 X' G1 E* ?1 J: U9 \** Output - Serializer Tx is connected to the input of the codec 6 `: K/ t f- {+ ?
*/5 E0 r5 `0 ]0 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ v; d# a0 ?2 GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
\) o8 U5 N) _. u& F: \9 ~. t0 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 F7 v9 K5 s3 \8 X% || MCASP_PIN_ACLKX
5 z& o+ q2 F1 L6 J7 r. C# g( k| MCASP_PIN_AHCLKX! L# ]5 v( o: o# M0 {6 s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, m" r5 F( x5 F9 H$ M( G: j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( a8 j4 j; y; B) ? y, o9 k% l, T: f| MCASP_TX_CLKFAIL " E1 [' s$ U" @' b
| MCASP_TX_SYNCERROR
5 I; ]5 i% }6 [2 g: _! I- h& || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ @ O- e8 q1 T+ o# v3 N1 F| MCASP_RX_CLKFAIL
1 g, n8 X8 x0 ]| MCASP_RX_SYNCERROR
$ D9 _/ H; {3 z| MCASP_RX_OVERRUN);
+ N/ [9 T0 b! X1 n9 `# u! F} static void I2SDataTxRxActivate(void)
9 A% C6 D. o7 Q0 B# u4 c; x8 X" [+ k{
& ~6 I8 h$ _6 ], s A, P% s2 _( n( n/* Start the clocks */& s. y2 Q! M' T0 ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! x# p+ y9 n% R Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ W- R& w1 d+ ~5 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% W7 `* ~9 a v+ p5 N ^' jEDMA3_TRIG_MODE_EVENT); w# h2 O& U! J, `/ ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ E+ m9 a9 m0 nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 I- B. u* d \% ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 V: {6 Y% R( O( m0 I1 Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: w+ I8 d& v1 c, y7 L. X+ e* }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) y3 o# j# x W7 n7 `5 jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 q7 }, c8 q3 e( ?$ H- [3 z O' gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 y9 y4 X j" f) K: Q}
* E) L: \" V0 a* u! i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; @& x3 H/ I; I7 M5 H. K
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