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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% w7 [) |1 `; }7 Q5 W$ Ginput mcasp_ahclkx,. d" O! J& t& q7 j3 P. }$ Y
input mcasp_aclkx,
( z6 s2 ^' @1 `3 I8 g4 vinput axr0,
* E8 b8 i! r2 E) ]2 t! z
4 q W" v0 r2 `1 j1 Q" loutput mcasp_afsr,$ k) W" T8 v% j" l* s
output mcasp_ahclkr,! k8 t6 v1 {, w- V. n0 g, {
output mcasp_aclkr,
" ?$ ]- A7 | |4 i. H3 Z5 loutput axr1,' r. a ~5 ^3 ?& Q+ J$ O% A2 g
assign mcasp_afsr = mcasp_afsx;
! L0 m3 R* j) N4 R) g! |% kassign mcasp_aclkr = mcasp_aclkx;
2 M3 x. ?# ]; m- p$ Z# rassign mcasp_ahclkr = mcasp_ahclkx;
8 X. b8 _ ^0 Q' G, U4 Vassign axr1 = axr0; ; K# p, ^3 u5 y0 F+ J# p; Z
$ h# d) g* T* i/ d w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 f( e; \0 y1 s
static void McASPI2SConfigure(void)
5 J) w) E9 E8 U/ ?' j, R) ~{; y6 d$ D& _ A9 v- y0 n, {; @# I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 o; l* d3 a$ E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% X$ F/ _2 w1 ~3 j4 ~" t
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 I B% x' f, K$ Z/ XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 |" Y5 j3 J, U& M' nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* ~0 q, g4 A* m! ^2 _8 U/ c1 }
MCASP_RX_MODE_DMA);
+ x, Q& W& }4 p/ E* m MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: y6 |$ w4 \/ |+ _8 y1 d4 {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ u; Y8 @- `) A6 p- p, N/ }8 q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 F6 |) P+ _% a/ A2 W! ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 H" _2 j: O* N. T. m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 Q, \$ q3 d ?9 i( h3 M0 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. c# ?8 r8 _0 A# @) ^! T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 N M- A; c* }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 b8 c4 ?! I" B- P) y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. H' w5 H( O S& K8 N0x00, 0xFF); /* configure the clock for transmitter */
& m$ Z2 K) C+ S" pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. l: D3 [. I+ L% w4 X, s/ UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( X L, [% f" v, V7 B: [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" J1 o$ B) r" s. c' l0x00, 0xFF);
5 G% n' `# T' K4 Y
" K. L8 A# X- A( z/* Enable synchronization of RX and TX sections */
- I2 W" @ m# J( ?8 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! \% e, j! h( t4 k2 e1 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 z$ H U: v+ a& p) uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ d' ]) G8 ]! c+ z
** Set the serializers, Currently only one serializer is set as
9 l9 `) L0 v7 k; x M5 g1 |** transmitter and one serializer as receiver.5 Q- @) ?/ r& O3 B
*/
9 }( ?& @1 f" r4 `" WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); T( [$ V2 y" q5 m3 J: [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 m6 r# n7 _0 P6 i
** Configure the McASP pins 1 x( T& d5 L3 {) S
** Input - Frame Sync, Clock and Serializer Rx
5 }7 [! ^3 G/ ]. B** Output - Serializer Tx is connected to the input of the codec / b9 f. X0 m5 q) }7 P/ @
*/
# d; g6 @( C; g( `5 X6 wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ y) v3 \. K7 o6 s% H5 rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ d5 M, g- Z v4 z3 U- Z8 I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 x) E3 M- s! l/ [( R
| MCASP_PIN_ACLKX9 V0 Q2 E4 ^: J" }2 X7 u
| MCASP_PIN_AHCLKX4 R% n7 t w7 H2 I7 }. ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ m* h" f, t9 X/ [5 h! TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' |& {5 {: t/ e/ ^. Q: Q( V- P" E
| MCASP_TX_CLKFAIL 2 h' f9 |8 n$ F n) m2 [+ Q: w4 Z
| MCASP_TX_SYNCERROR! ^$ T# T* A6 G) Y9 Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; |# b2 z8 y: P! t| MCASP_RX_CLKFAIL& e( S7 k2 S1 z" |+ [& Q( }. H
| MCASP_RX_SYNCERROR
8 S1 B- o. d' k/ d| MCASP_RX_OVERRUN);* q U& O+ Y$ i: I6 Y
} static void I2SDataTxRxActivate(void)' l' ^6 _* Z( Q6 L8 L, T) @# [
{
; T6 @# }) G; {6 v( y( r/* Start the clocks */) I9 o: z F" {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ x. d( V( C: k A$ F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& N. q9 R6 ?$ f2 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 i# [4 N! P, Z6 F# \' _' J5 ~
EDMA3_TRIG_MODE_EVENT);
1 C |: `. @4 |8 ? V/ gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / I5 T d/ ]% M+ \& M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( a9 ]! ]: |: m9 U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 }6 w! r) w2 N' c+ u* b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 H- q; l, K( A/ ?( _1 ^- T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& Q. t& o' c- r* LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. J. }& _# C9 e( E5 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 A0 `8 q5 S! P+ R" g
}
4 S C* C$ \! z: R( q# S3 P6 e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & @, Z6 K0 S( s; n- \
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