MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
4 t  u# i' N# Y" j0 B4 ^5 qinput mcasp_ahclkx,
, n. O6 F) v  y, Oinput mcasp_aclkx,
. e/ J- K& c. a+ |- W/ C, o( l8 a% finput axr0,
! B! a/ ^8 q) s# I2 G6 Z
" P0 B2 w2 f* u2 d" y+ Youtput mcasp_afsr,
output mcasp_ahclkr,
' L5 b& d: ~5 woutput mcasp_aclkr,
# X8 {7 P# e) ^. G+ koutput axr1,

assign mcasp_afsr = mcasp_afsx;
: m  q: V5 ^2 o- ~assign mcasp_aclkr = mcasp_aclkx;
5 E  f" o/ n, |& @assign mcasp_ahclkr = mcasp_ahclkx;
) ]2 R; \+ c! }4 j; F* n; passign axr1 = axr0;

" L) P8 ]5 @8 s% {

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
$ M- K( x0 V0 rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' t- z0 X  Q4 d+ |* yMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
! v3 A/ Q) L9 UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' N" [' @4 Y- L- J5 JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 |" G2 W( f; y& I$ `MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( H4 h) p/ |, N& J/ Y! n# OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: H9 S" v( C1 ~4 u5 `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 y6 ]: g. x6 H: D, ^9 T1 Z0x00, 0xFF);

/* configure the clock for transmitter */
6 `  W8 E$ q, ]' A9 j. l% y  ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 z% F8 }% s* i4 y- J; j, q0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
" v; I/ h  n+ i% m& ~  cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
6 ^3 A5 a5 H! N  R' p- ?8 T  E*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
/ k( R$ x! M% Z6 z/ y( P2 z** Configure the McASP pins
' b- ~9 w1 s1 f( T, o  W% ]** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
9 Q) t! j  p+ e& _- AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- o' F; B% l+ U  I8 ~' r9 u% Y  x: dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
9 I% X) u% ]" P# O% Z+ m# s0 e: x| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
  Z. L; u- j5 w3 f6 G5 ]! {# T| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
; o2 @/ \+ W, v5 I  {, H1 W| MCASP_RX_SYNCERROR
' c% I' f0 F0 b| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
' Q6 t: j" z$ Z1 ]; T3 k, n5 U{
) L/ L6 w: h; W2 D* J/* Start the clocks */
. Y# U3 T6 Q4 P5 {/ ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
# ?8 R5 Y6 M. F" D5 e& m" S+ v: Q$ B# A1 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) H# Z6 s) z/ y/ q! PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 k4 P5 b! Z9 t. HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

; {' H3 `6 k& j- x1 o

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

# B% ~, U( a( K" @