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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; @4 d z' v, y; ninput mcasp_ahclkx,- x2 O! G& p2 Z. z: s0 A
input mcasp_aclkx,: |# T* D' p, U4 M$ |0 W
input axr0,
; j6 L* h8 q% Y6 b' ]- r8 b* l" H) y; T2 H% m1 M
output mcasp_afsr,
7 u6 u3 |4 r" `# s: r' S/ `. ]2 D7 Moutput mcasp_ahclkr,
/ p- [7 u& R& p: M6 {& routput mcasp_aclkr,) [# i3 U' U8 x5 ^$ `
output axr1,
- t; j7 g0 L6 }" T assign mcasp_afsr = mcasp_afsx;( M2 K! w. c& Y6 W# K' N) u
assign mcasp_aclkr = mcasp_aclkx;; ^2 f: G1 r) R2 C: X8 a: l
assign mcasp_ahclkr = mcasp_ahclkx;
; b/ s+ e) H- ?1 K$ J0 _# U- @: Fassign axr1 = axr0;
/ x6 W/ P, S; z& {* M }" u7 `) E7 z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # ^- I# q3 W3 m& l
static void McASPI2SConfigure(void)
5 V5 }% p: m4 F4 o+ R" {) o" i$ M! t{
9 u) j f; G# {: yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( m0 n) g P* h, Q8 S |6 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 Y- I1 W6 D) X' e6 ^ H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 i* x2 R- K% D3 Q- [$ E% k; ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ s* w( e( r2 F1 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 t$ E1 X$ U1 S- a( D" e
MCASP_RX_MODE_DMA);
! X3 q1 F) C4 [- HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 W1 K4 {) `$ M8 t# o1 O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ v% q2 A! n- ]2 n7 M' |9 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; \, c) g3 R( g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! B+ A) T+ u; S- \% B( CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 E2 u0 c) u* n0 @, ]" ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' @5 M% ~2 @# a8 m* L- FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 V8 O3 z. j: H, \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * V+ N# v; o( Y' h9 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% a" u, h4 i; C0 h: y( Q0x00, 0xFF); /* configure the clock for transmitter */
, i& M* o2 h% a2 `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: p! W9 }8 i0 d$ i8 l* y* IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - ^! ?! P5 h5 l8 s' n1 v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 `# l/ ?3 N* E$ B5 e0 e3 S+ F0x00, 0xFF); c; E4 p* Q* N' E/ i# k
/ J: N% K/ q, C3 k `
/* Enable synchronization of RX and TX sections */
0 y$ `0 R: A6 h& a- w0 s$ \( VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! d8 I* H; q2 g& k1 sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ U' i3 c$ r' | |6 _. E: lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ e2 A6 L9 @2 q2 }
** Set the serializers, Currently only one serializer is set as
; X7 K/ q! B) U4 b0 @** transmitter and one serializer as receiver. v! g( G, R. H4 P/ {
*/
. O* w* U' x# m8 z# W! v9 D. F3 `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: k! e' |; V2 c( d, `2 {( x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. V7 G( v% @% L" S
** Configure the McASP pins
# k; o" o/ q2 [+ K, Q, r** Input - Frame Sync, Clock and Serializer Rx
% x) W$ K2 w3 O" h4 l t** Output - Serializer Tx is connected to the input of the codec & J U: a/ T2 N6 U
*/
; X5 j8 P+ Z+ I+ L( y' g2 uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* r3 w9 _# b, G# x! R. I ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# x; @$ h1 ~( r1 {3 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
H# [2 M+ W% x| MCASP_PIN_ACLKX
; F* e0 Y6 b. v5 N! L$ u' Z; ?| MCASP_PIN_AHCLKX! |) P7 [) j& V1 C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: q' Y1 D9 t9 @: S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % g) O2 ]/ _* ^! r
| MCASP_TX_CLKFAIL # S) R" g: F& r
| MCASP_TX_SYNCERROR
0 @# t4 x# w* K4 A) D/ K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' w8 v; j0 h5 f* }
| MCASP_RX_CLKFAIL
u! [; d- z0 F C| MCASP_RX_SYNCERROR + n, |# f/ h# P# r. w5 Q5 E) G' \5 X
| MCASP_RX_OVERRUN);
4 p. C' q: [2 f) a7 a. [} static void I2SDataTxRxActivate(void)
+ S; o* J; k8 ~; h* {{
: Y6 P% F3 a4 F( Q$ W9 a, o/* Start the clocks */
; K, s! a) d0 ^' k1 ]! b2 q, VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# O1 u+ _3 Y4 W) @; FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ @' w6 V/ w6 f) h5 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- I7 J% k0 Y5 D+ L9 n/ j K
EDMA3_TRIG_MODE_EVENT);' i. Z8 N" K( H; _2 x) E9 U4 z4 G+ X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# t3 M7 {* ~% y' w+ U$ l+ PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) k! S5 Z P. i. R2 P, dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. L p' W* a5 M+ _- R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ o6 w& t! X/ X* R- @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 G( K( ]* r0 ?) \4 J, o1 sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; M$ ~( g7 s0 [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 I) h$ G8 c1 z0 x} . I2 S, |9 i$ s' I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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