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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 l5 r, \& \1 R1 I1 t' Qinput mcasp_ahclkx,( B% C T! x3 Q; I, x2 ^
input mcasp_aclkx,4 e2 `8 R8 i' s. w% u
input axr0,
5 e! E9 @3 e. B) K+ O) i9 U0 Y% x1 r) h( x4 E" X* ]" z8 `
output mcasp_afsr,
: y) {4 s6 d0 O6 i! Q3 C1 Y% r, S1 foutput mcasp_ahclkr,/ Y1 f0 l6 j& c: X% D" E
output mcasp_aclkr,
9 k' \& Y- q% z* f$ D' houtput axr1,- H2 g! D S& X% k
assign mcasp_afsr = mcasp_afsx;
/ E9 E8 D$ V, G$ S. y8 w% tassign mcasp_aclkr = mcasp_aclkx;' I( u8 D$ Z, p5 u2 r6 s. v% T
assign mcasp_ahclkr = mcasp_ahclkx;
- P Q( q/ p: r# W4 @assign axr1 = axr0;
8 P$ t0 ^3 w& w) h
3 @( W* T5 K& E, Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( j5 f2 ~" a' P, ~' [% O. I
static void McASPI2SConfigure(void)9 A: D0 r$ ]) ]2 c2 y2 v1 ^
{4 X, E# M: I1 w/ ]9 i& o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- E. L% r- A! h" C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; @' i# \3 ^/ \6 UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" k9 [6 w, ]! X8 I0 U \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ |% S2 d. T I) Z8 m: _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ z# b& G3 q" }/ C; N8 bMCASP_RX_MODE_DMA);; k5 y7 E( @! V# \* K7 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' _2 S6 B' C3 o9 l6 ]* T0 t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 Y& h( \3 `$ ^, AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 O* Y* w$ N. r/ S+ m0 S+ YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 x1 W* _8 v( a+ |: C% {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 J# n: l5 A7 c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! S* R, f8 Y: ]- @. VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 A) V4 j2 X! K8 fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. w8 J! m T. x8 \9 p) eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ {+ f; U. n) Q# { M; z0x00, 0xFF); /* configure the clock for transmitter */
/ u- n; L) N! Y$ ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 A% J$ O- s) e2 G3 y! x; j" pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 L0 {1 y& G& c# TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. `/ G2 J8 _% w9 P* W9 l0x00, 0xFF);
3 b1 C' a9 E" K( O
7 T' }$ R. ?% F) t5 f0 q/* Enable synchronization of RX and TX sections */ $ H# }6 y" {" N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) X1 d7 I$ _ [, ?$ A. Q- W# e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( s) t* J3 n: i! c' Y- _$ z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% R* X* s5 K. F3 p9 \( n** Set the serializers, Currently only one serializer is set as! Y l% n; Z e( d: Y' a' l
** transmitter and one serializer as receiver.
6 X- |$ e S# s5 C# b2 J' k*/' V" B- A$ G4 w) l. \6 @+ s% @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 q6 y3 B# ?" CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 G" N) X! T7 m" k/ }
** Configure the McASP pins
1 A0 F; D3 Q8 ^4 K& C( h) q** Input - Frame Sync, Clock and Serializer Rx- p/ s0 E* \# u" @9 @
** Output - Serializer Tx is connected to the input of the codec
: C( y' B( j5 ^# i0 l*/
) j3 F8 O2 S' B4 M1 f* z, QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 @, S3 `) q+ |1 Z2 L( J9 m) BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 J6 x* U2 x3 s, T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. M! y; M: J& b1 \
| MCASP_PIN_ACLKX
2 n2 o% R. S- P. D| MCASP_PIN_AHCLKX
% Y4 o& f( k3 w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& j# U- o7 _' z( G9 v* c9 p1 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 U2 Y& [! h; u& B
| MCASP_TX_CLKFAIL $ F' y/ j- Q, O1 v+ C, F- m) L O
| MCASP_TX_SYNCERROR
! |$ ]9 s' Z5 r L" Y* b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# Z- c V- h" W# \4 F) F| MCASP_RX_CLKFAIL
# W4 }, N, V' y0 V2 g. h& f5 m| MCASP_RX_SYNCERROR ; X% u/ M( ^% k6 u
| MCASP_RX_OVERRUN);8 X9 j. K8 X. I8 U) C5 Q
} static void I2SDataTxRxActivate(void)" g! R' e5 N3 k3 P$ @% ]
{# l0 R$ I, p0 Q1 U2 r
/* Start the clocks */' m5 ?% }% G. N2 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 W* z' V2 C6 r0 GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* T( E8 _% f9 }3 @+ u/ R* r+ BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, l: Z- i- ?+ v& m
EDMA3_TRIG_MODE_EVENT);
4 }) D/ c/ J+ a. n X# A \! hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + Y# P7 M- B- J+ m: a, F. p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- A/ U- b7 S& a1 @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 W. N" {% N, F& DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, [1 i& P: w2 L# g; q3 V1 D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 a" }9 O$ x& `1 @8 {1 `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( P Z" |: Z& w- @) JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. w$ [* p9 Z7 C h; m& F
}
4 B5 s8 ~* @6 Z! R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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