|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. R# g! W5 D4 w7 Z9 m
input mcasp_ahclkx,
1 y7 f2 l* z$ a6 p3 r9 G: _4 uinput mcasp_aclkx,& Q7 e% W+ h$ }8 T0 U# d; _
input axr0,
7 ] `+ L" ~& i _$ v: f& E& }! I5 X) N/ p2 Y1 N
output mcasp_afsr,
M i0 v6 S9 ~. ooutput mcasp_ahclkr,% [3 o( U: ~7 N2 d, V' c
output mcasp_aclkr,
4 c8 ^' s y6 `( }output axr1,. @; z: A% s: Y3 L
assign mcasp_afsr = mcasp_afsx;7 y5 @& J) \0 m) ?) m2 w
assign mcasp_aclkr = mcasp_aclkx;
E7 Z8 l4 v# ?% Nassign mcasp_ahclkr = mcasp_ahclkx;" p/ r6 v: Z5 [5 ]4 g( Q/ n+ d
assign axr1 = axr0;
, J4 m& E; Z9 I$ v( l' s& k* e6 H' J1 o) C# b& K1 R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" `6 e' g$ x/ k, B, N( l0 Pstatic void McASPI2SConfigure(void)' Z F3 I/ u$ h* k, q7 T: e) M
{5 _, \/ J' m& E- U) S/ @ N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ W+ w: b& Z2 N/ K7 _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" t* @/ O% _: U* M$ K* YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 S4 `& q/ F, c: b& |: g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
M% W/ t8 j! q. G1 d1 P8 }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 U0 h& i8 l* fMCASP_RX_MODE_DMA);
9 ?7 e. ^( B Z2 V$ v/ M/ `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; z1 k6 o5 C/ y I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! ?7 G" [2 r/ Q- s; ]( FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 I, d4 ~# U w1 L0 W5 {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ `# f$ @9 A* q3 O& }3 g* m8 U9 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ ]. T4 k6 E( o3 dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! {/ {: L: Z, H3 gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 i" Q! l8 l/ H, y/ VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 C9 {# a- I: ~) @: X; M; X5 R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ B9 e) O- v9 Q! f [8 F+ s( b
0x00, 0xFF); /* configure the clock for transmitter */
1 X4 Y% D# O4 X8 f% EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# [0 J! [5 e# f( B7 I" t1 i- y( RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 ^5 G1 W' ?0 Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- j' j8 o( h4 `* _4 w0 E; S
0x00, 0xFF);
7 [* P/ R- i# |& f7 _4 p; r8 u2 A
. p' o& N5 @3 H" N$ r: r/* Enable synchronization of RX and TX sections */
) d9 o% F9 T- ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 p* |5 w; p+ b u; j6 c7 QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, d o( d6 W: c9 }! m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: n1 s" j* @3 u9 }0 z6 T** Set the serializers, Currently only one serializer is set as+ y+ E& [9 L# l3 E) i$ U
** transmitter and one serializer as receiver.
% A; w+ j& }. r+ Y: [7 X*/) X4 z$ l! M) s- t C5 R1 S3 I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: L8 N# c$ C' o0 n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 b: X! ]0 X1 F, K* o- A: L
** Configure the McASP pins
& p/ |, ?# X! V6 i0 v9 W0 j** Input - Frame Sync, Clock and Serializer Rx2 e; J5 A4 S7 d
** Output - Serializer Tx is connected to the input of the codec 7 K1 o# d5 H' Q6 h. R/ Z1 U+ m
*/6 R6 b! Z* m% V6 X. N( |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! y/ g( ^% a. N p8 N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 Z- J3 X. b% \$ g- pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ w i6 {" {7 _( a- [) B. [! ]: p
| MCASP_PIN_ACLKX
+ P6 m$ |$ N$ S; n7 Z S$ k, ~| MCASP_PIN_AHCLKX
2 K, m( g: F9 N b, i& Q w1 U7 g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& u2 r0 l9 H3 L7 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 i7 b$ n0 T u9 G| MCASP_TX_CLKFAIL % }' G4 q! Q4 ^
| MCASP_TX_SYNCERROR- K3 I2 a/ J2 Q- r' Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( B' ]6 g. ^8 }7 k# R| MCASP_RX_CLKFAIL
9 S% v( {2 o( R, b2 ~| MCASP_RX_SYNCERROR
1 _3 V2 P0 V, @0 h% h' }| MCASP_RX_OVERRUN);- V7 J$ S' i- G0 n
} static void I2SDataTxRxActivate(void)
- k; R& k3 l1 h{
8 L/ n+ Q- F5 w2 T" o/* Start the clocks */8 k6 k2 Z) c }+ M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- ?& L0 V' \( G! Y& v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& S' ^; A$ M4 t/ l$ yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ y1 t8 H! ]0 ^3 v, p/ o
EDMA3_TRIG_MODE_EVENT);
4 ^6 S) g# e& Q4 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, v z3 q3 q3 W5 T3 J h, p! o$ WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ i" [* W' L" Z/ }0 q( u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ R; A, J% z G' s( O5 v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 U7 V" h* ]# D$ m+ k; h3 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 B# x0 j, {+ ^- c& c7 p# @6 y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& ]- e1 l: X# M4 c' s8 ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) n% t3 i- z X' m0 ^+ A5 V: I% B
} 0 ?) m! n4 d. x8 c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / g! G" A7 o; Y: s* Y! c2 F
|