|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) R2 C2 P6 W; _$ F0 E
input mcasp_ahclkx,
9 D- H% {* W- P* k- @input mcasp_aclkx,
$ C9 ?) A8 j% [$ {! }% h, {input axr0,0 K& t3 m4 C4 f8 F( t# @$ M& [' L
: l( y% H5 O. a! ]9 T4 V( C
output mcasp_afsr,
2 a9 x- F+ b5 D5 q' F( V' M" b8 Voutput mcasp_ahclkr,* z. l3 S$ c, E- I. l; k1 o( p: w" a: y
output mcasp_aclkr,
8 p+ s+ o" F1 G/ v! G, eoutput axr1,/ [" z6 e/ R$ ~5 h, z# `9 u
assign mcasp_afsr = mcasp_afsx;
& k% n# r2 y& V! X$ |assign mcasp_aclkr = mcasp_aclkx;
& |: j9 Z& T$ v, Jassign mcasp_ahclkr = mcasp_ahclkx;
{' P/ _6 m4 Dassign axr1 = axr0;
; ~# i, |9 O$ |/ z. L4 O# | \( X; M
5 R6 \& u# y( P/ v( O5 m8 q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 T S1 a) y, Z2 fstatic void McASPI2SConfigure(void)
5 S/ G0 ?( z; u1 N+ P& L3 `{" E0 `) l. k/ R7 h0 L" V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( c g% g }$ @2 k% U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 z4 g& d2 u. T kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 B8 G. {9 {! a! R% K: F, C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ V9 D) h; K% L& L WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: A' q: v: b* @2 N" I' wMCASP_RX_MODE_DMA);1 C. ]( y, H+ I) P0 }/ \3 s4 X- e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 \+ w) M8 w* }$ H- v; R8 u* y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ \( S% r3 @( V% q; _% H( k' sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - u" V, O E, m l; g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 d. _8 W! S$ Q0 `- i$ r) s0 cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 u, Z& _# t. r ~) Y L( P' ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, G7 Y6 ^( R3 {, N* a; LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. \1 A5 e6 T+ _ iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & z, m8 G$ Y# I2 H( o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 W: q; i- W) d! F$ J# y0x00, 0xFF); /* configure the clock for transmitter */
! h U7 v) V$ d+ v5 W' ]# ?6 NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" k. G+ u+ P5 O; }+ h( l0 Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' T0 Q+ u, T9 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 ]* x9 t6 T" @. N
0x00, 0xFF);6 Q3 N+ j3 f6 F8 o' S$ U
: V. {2 k/ P, U+ @2 `# k7 E! ]
/* Enable synchronization of RX and TX sections */ 0 ?: `" m0 M# R! X( m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- a. q, e: Z% `2 O& P/ X- rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 ~; p" w' h) v3 v5 i/ e3 }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 F4 u* J2 M8 @# W/ [) n9 ^
** Set the serializers, Currently only one serializer is set as! [/ G) j) O% ^' J
** transmitter and one serializer as receiver.
, [( {( S8 ]- t j5 o3 c) e*/3 ?5 I0 M0 x, ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( g0 N: b6 P% @% k5 n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** e# l- k0 Q" g0 O/ h% w& g
** Configure the McASP pins
' \0 Q) O7 b( m** Input - Frame Sync, Clock and Serializer Rx/ _" B; @0 g8 @! N1 k" J* w& F0 v
** Output - Serializer Tx is connected to the input of the codec
. h. Y' C$ ~' d# r5 z5 B3 K*/! R* o2 `' j4 Z$ |' S$ n- ?% v: \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ m t5 ]9 K7 q# ?; d9 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ R1 }6 O% E; w9 A$ I; c% B8 Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 c; p; u: _, a4 V9 a2 m% z| MCASP_PIN_ACLKX
% }) P! K! X6 _ d| MCASP_PIN_AHCLKX
2 D0 T6 \8 u6 C. `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 Y0 u5 {: K0 k9 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 x1 K% ~6 V$ n0 y! B4 y8 S- `, h| MCASP_TX_CLKFAIL * C$ m; v6 [7 Z3 d3 }/ I' o/ _7 I
| MCASP_TX_SYNCERROR. d0 @( L1 M7 h8 `0 ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ X( B- c6 w7 z
| MCASP_RX_CLKFAIL8 D7 \9 F2 H; d
| MCASP_RX_SYNCERROR " v( U4 F8 h" O" z
| MCASP_RX_OVERRUN);9 F* H' G+ F/ l2 [1 i$ q- ]
} static void I2SDataTxRxActivate(void)
2 Y" w1 k4 y/ e2 B5 n2 H+ x0 l{ l" p* o( B, m7 d3 ~& L/ v
/* Start the clocks */
6 m/ J! h6 j8 ?; O8 [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 w$ j5 M) M2 D* m3 ~ Y3 J( \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 z& \: Z1 ]/ B2 J* o6 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 u- `. W% I8 {: c$ T) |: D6 P. W0 [EDMA3_TRIG_MODE_EVENT);
9 p/ W( h( w- N+ a! O& UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . Y# |. m% q* M4 N; y) `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 D# _1 `8 y/ [( \$ Z0 q+ a0 v! LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 v" w) ?, W% p2 P; s, TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ S* v9 |7 S0 O# a4 f& E- M/ Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ o: `" j5 g, ]# g. w' g# A1 K+ z: jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 q" Z3 n, z( q9 r0 F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ E0 p! h( u' D, D- f; w5 G- ?5 D
} ) E7 }7 B5 ~' ~! Q* P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 |5 l8 A9 w) E1 A$ J- M6 X |