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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ m4 i4 [8 a; P% i% o+ ?input mcasp_ahclkx,
2 L6 r# ^2 c# h. E3 e$ {0 `input mcasp_aclkx,& F/ r: } B# F' m1 Y- \
input axr0,( W" X* d) y( Z5 R' G$ ^
5 B u- b2 j9 z) M+ @4 w
output mcasp_afsr,
9 R9 m0 x7 r; u* c$ q6 R- Soutput mcasp_ahclkr,
8 B1 I3 c" |) o1 ?9 Ooutput mcasp_aclkr,
- ]* L$ D/ d; | eoutput axr1,
& V' w* M$ V$ J. Q; C8 V% {$ H' E assign mcasp_afsr = mcasp_afsx;8 I1 U3 y! b( p3 F6 |9 U
assign mcasp_aclkr = mcasp_aclkx;3 _1 I; _1 @8 S. N
assign mcasp_ahclkr = mcasp_ahclkx;
" m. j' c$ g1 Q* n0 Kassign axr1 = axr0;
7 E2 Z1 ` u/ |2 n
* m- n/ _4 X/ B! l5 ?6 c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 E7 H* z* I& Q3 ]8 W7 R3 H8 a
static void McASPI2SConfigure(void)
* q! d% u4 Z4 C; [+ ~5 ?8 l, D{
* ^! I+ N6 C4 G; k. S* DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 ~3 b4 T) ]+ l7 U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. a8 ~! F* Y; gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 K: j3 Z9 B w3 r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 |' p) {2 v$ {1 H2 w- ]9 ~& K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 @: X2 n# x# T9 [ I5 O
MCASP_RX_MODE_DMA);: x( }3 E4 x& \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& s4 p6 B- M, z' B3 s4 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
~+ x; x, I5 @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 A9 N8 i6 m# ^. Y$ f4 gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 U/ o7 ] [8 \- A; TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' e) ~! `. r" `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 ]0 Q$ ^% h' T% w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 U4 x a! Y, qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ v- U) w6 p1 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
R( @7 I- h" y3 g5 n, d9 F4 h0x00, 0xFF); /* configure the clock for transmitter */
! X6 J1 k$ b! J( C, [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, d% s& C/ p+ r5 v7 o( RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ B* Q! L8 N* Q0 @1 X7 YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 x* _: \& W* ~ |6 J0x00, 0xFF);6 i# r* O( V! |/ s$ e
$ I' t5 H8 X5 r+ n! l1 p
/* Enable synchronization of RX and TX sections */ ! F8 d" l, N+ q9 S4 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. F, f7 y+ Y/ Y; B' U0 `. K- c/ h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 J# T! J5 K8 ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) r2 ]0 Q+ i% h2 w3 z9 [! y) ~
** Set the serializers, Currently only one serializer is set as
5 e* f' W4 `$ s/ T6 ], h7 b: n** transmitter and one serializer as receiver.: y8 p9 X/ W; z! i' z
*/
H3 B+ s) x- c4 \' U' eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. `/ f' O% U5 r- z6 l+ QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ o i" M( R5 _$ F8 c, E% i** Configure the McASP pins
3 V+ i) `" ~' i6 r** Input - Frame Sync, Clock and Serializer Rx9 S: y) _- Q! J1 Y$ e+ W3 Y
** Output - Serializer Tx is connected to the input of the codec $ n% L6 t! K: l6 O
*/0 A) U" W# q% e* T$ p: Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 n( u$ d9 y! ~4 E. ?4 U/ CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
_6 T4 t# W2 @0 }1 A/ UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! i5 ?8 e. {; h, W% {1 G9 U8 z1 U, [
| MCASP_PIN_ACLKX5 j0 N! S+ r, Q0 m% X
| MCASP_PIN_AHCLKX
4 M- r- f2 h8 ~* N4 g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! `! ?: X! O: `; f2 Y5 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 x# r1 V [/ N% U: R| MCASP_TX_CLKFAIL
% h2 B& X4 J7 K9 u| MCASP_TX_SYNCERROR% o$ B- C, C1 H& X* m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 C# j, R3 i5 k: k) R& ^
| MCASP_RX_CLKFAIL' Z: w, y9 \8 X w
| MCASP_RX_SYNCERROR
2 R% C/ \* v. |! H| MCASP_RX_OVERRUN);5 ], W5 d5 N# P
} static void I2SDataTxRxActivate(void)( S, v* @/ I" Q/ i D7 ~$ b
{
4 @4 Y9 P0 B) [% q/* Start the clocks */
6 G! w2 g5 s2 L+ \4 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 W0 m) S- M/ b& V8 D9 sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 E3 F: M' E8 T. r, A, `/ J: XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 b# R% e' B0 x) X4 l6 v/ TEDMA3_TRIG_MODE_EVENT);
- _& r- x$ J" O! ?" u3 A- wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - b8 g& ?& m7 S' P; f Q+ Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ r+ }8 T# R P+ W% a% AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( @) y1 I, ]0 c0 U7 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# D- ~( U" i) M3 L/ C0 m6 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 [1 l$ T% c, d2 Q) o* DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ Y, G5 c& ~' w9 J* I+ x9 b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& T' A5 _- ]; L} 7 F% p6 W% E0 s1 R d c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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