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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. \5 l. W, e x, U
input mcasp_ahclkx,
5 |4 n: d7 X$ c$ }5 `4 V* K% Pinput mcasp_aclkx,
5 T8 S3 j/ o' B4 |input axr0,
1 T2 K n+ ]/ B- _
4 s9 q( O- C C$ i6 L; Uoutput mcasp_afsr,
# ?" C Y, F4 {2 L' P/ \+ Poutput mcasp_ahclkr,: b" P; Y9 F G% |$ L- d
output mcasp_aclkr,
& I* {5 Y2 m" soutput axr1,
9 p8 v2 F$ P# G2 z4 a- p) C+ \& L$ u assign mcasp_afsr = mcasp_afsx;
' u3 u% b% s7 Y( massign mcasp_aclkr = mcasp_aclkx;2 W3 Z0 {9 W3 O) r
assign mcasp_ahclkr = mcasp_ahclkx;( H" f; z( }. q
assign axr1 = axr0;
0 }% i: \( Q3 r1 X$ u4 [6 a1 `) F+ l1 H- a* {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % e. |+ a/ C) c: o
static void McASPI2SConfigure(void)) o8 ?) S+ {4 n! I8 l2 K
{" R G' h* @# U# _, \5 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 d5 E2 f/ {8 Z# a- SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% j$ j9 d. j: q' l: b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ |7 C: K- k( \; a. lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* p- h6 \% ]% EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 m, g& O; a2 B
MCASP_RX_MODE_DMA);
2 ~2 M, o' V: V9 |: R! wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 W* Z. V( _. s& Z9 I7 mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 e6 F' L! T6 e T" q( c% V5 O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" A, D/ _, L1 h: w/ ^" G5 _, hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ r/ B: ?! q% | ^0 tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, q1 ~$ ?1 q. b. n7 J6 u/ h f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# `' n! o& {- e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; d7 c n" h7 C7 i8 z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! C- J+ `" Y' Y! P) x' a+ {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 |7 k% {/ S7 x* d; x4 Q! w
0x00, 0xFF); /* configure the clock for transmitter */6 I2 w. _, S% y6 x& }2 O1 g6 V Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# b0 J3 E0 K1 c$ `" @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 T# _0 b s0 u% K! J3 hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' [6 B5 W' L& m
0x00, 0xFF);
* @: c- k4 o/ B1 g8 J ?5 x @! _% [% u, u2 m
/* Enable synchronization of RX and TX sections */ + f4 W8 r2 ^5 \ Z! {7 r( S/ ^/ M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 X2 _1 F( k7 G( ~0 h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 @5 B5 K/ J' C% z( O$ l% p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 C; I, t* E0 V0 G% S9 I
** Set the serializers, Currently only one serializer is set as
' Q2 p/ F3 o8 t** transmitter and one serializer as receiver.
2 r# ?. R, I# o/ l*/# t. v: H6 W1 f" g! y3 C- L* H7 F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 x8 l/ }# I. K7 n$ _* e q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ D/ `) w6 B- l& }** Configure the McASP pins
" I7 H/ T" [4 ^** Input - Frame Sync, Clock and Serializer Rx
& ?* `9 X: _8 L- z. y** Output - Serializer Tx is connected to the input of the codec
% {3 `& z8 u: y0 M* N' i% L0 S*/; e, t9 x" v( C% U, @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
E( J% f: d; _8 P# tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ O, F) I) `6 j+ S2 O. H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ a. I2 ]- a4 ]" G) } S6 U+ || MCASP_PIN_ACLKX
- J8 W) U4 q# W' a6 @6 C| MCASP_PIN_AHCLKX+ a5 g" F% T) l; W' Y2 D% i L/ W) r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 \. d; t; E0 O9 z4 G' s+ eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 B0 g1 f. N0 O# I. W$ E# X| MCASP_TX_CLKFAIL / ?% x2 ]9 t0 }0 W0 @$ H
| MCASP_TX_SYNCERROR
) q6 A! g* {; D, N7 p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; A& S) C" n% K4 c5 g1 O) [
| MCASP_RX_CLKFAIL
, x; P* m' Z# c| MCASP_RX_SYNCERROR % S- J. N' G: w8 O8 S
| MCASP_RX_OVERRUN);8 o4 | F( i' K. Q! Z* g
} static void I2SDataTxRxActivate(void)* A4 O6 m! y1 [0 u A7 |$ X
{
7 c0 d P- C9 C1 H& s/* Start the clocks */ ?/ X' g4 d# t/ E6 H1 }. g3 ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 a, l0 A- E( S! u# O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 w3 y7 n% v( m9 x4 A! gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! D0 U Z( B) e4 ^& M! H& Z7 nEDMA3_TRIG_MODE_EVENT);6 F$ t) P8 U0 V5 l2 v6 x$ x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : X* p! k8 ? {: V! x1 P6 ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* m! |% a2 G3 B2 }" H3 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 Y# R5 z% j g6 ?* HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 M( w* a$ p3 V! Y1 wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' f7 o) k. ^7 F n, r, JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 w5 |+ Q3 ?. ~! A6 I; lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, z3 i+ g7 w" k6 g} ! V' A' w; h; ?& h; U B) O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; V7 X+ C# [$ y8 k* Z
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