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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 ?) a. B$ C, F
input mcasp_ahclkx,
4 r+ ~# ~0 E! e: @+ v+ ~% {* ]input mcasp_aclkx,8 V: `, ]7 Z# @$ b( w3 O
input axr0,
* L6 M9 q9 {8 S. f# W e' c$ S0 b5 M, k
output mcasp_afsr,, I" b1 u* [5 |; P6 u, @
output mcasp_ahclkr,
6 ?8 y8 y/ M; x* Goutput mcasp_aclkr,, T5 K8 _, ?; w& E0 n8 V
output axr1,0 T" ?0 v/ b) k" z! r
assign mcasp_afsr = mcasp_afsx;
' n& d( J, ]8 k4 I ?1 k; Iassign mcasp_aclkr = mcasp_aclkx;. R% { ~8 m# s
assign mcasp_ahclkr = mcasp_ahclkx;; D" `8 A) E! z3 c! ?+ P, i8 m
assign axr1 = axr0; 8 v0 z, x7 t4 o
0 T: ?/ U% v4 Y ? y- i" R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 `4 i3 M0 N& U5 V% k- Cstatic void McASPI2SConfigure(void); s3 K1 L5 s$ b" Y5 o
{
7 U6 d; ]7 y/ s/ E2 A9 s: h5 f/ I6 Q7 K% TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ b4 r5 T9 z( F# u( e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: Q0 V. }7 B6 @0 ^3 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 C) Y6 X" r; Q' S6 SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ |2 P1 y/ G E2 T/ C$ N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 D4 f8 Y, W3 cMCASP_RX_MODE_DMA);
, w1 W @7 H9 y& q. k- K" xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 G n0 O8 H' S$ o& J! A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 h; L$ n; U: mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' w9 ]6 I, t% S1 m7 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# s, Z* ?8 u6 H5 B$ B* y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
I2 J7 V Q$ K3 N, V- I$ IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- {$ j1 Y1 E; c3 z1 d0 l, `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* ^, o/ c2 W. p9 d1 h2 U2 `& KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & D: S- G- F4 K: K1 V8 j- O7 t! Y, t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ N: M- _4 }$ L1 D# G) u6 {9 {0x00, 0xFF); /* configure the clock for transmitter */
, M0 x: r! I9 o; P$ wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, N/ K/ ]! ^4 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 j' W1 D# K2 `; u2 e- G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& \5 v/ N$ J4 [" `0x00, 0xFF);
) z2 i- |9 q* K: q* Z' ^6 E5 T# }2 F( u$ t+ ` b+ E
/* Enable synchronization of RX and TX sections */
; l1 A8 \/ \6 D% `2 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: F; ]: K) y* H8 f% J3 T! ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- k7 @0 W' G) |3 ? ]/ }8 tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 `. X4 e& N6 \9 w" V- \** Set the serializers, Currently only one serializer is set as" P. u) S. u F2 K& Y. P8 `
** transmitter and one serializer as receiver.# a; y% V) m+ u; e2 e: p
*/
C5 [. U5 _1 z6 V& O% e: ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: D7 `+ `+ h% p8 g% p, l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 C: ]4 E, N6 n9 x; i$ [2 n** Configure the McASP pins / W7 b. l& F6 L4 w8 L2 f
** Input - Frame Sync, Clock and Serializer Rx4 v, M0 z3 }; ?8 l/ M, f% R
** Output - Serializer Tx is connected to the input of the codec ; }! Z- ?6 R) y5 N
*/( C) V; e( k" u8 `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 V B0 n9 I2 C F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& ?* x' x7 T% C# O" i( [' E$ h8 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ c# G! M5 M* a- \9 g
| MCASP_PIN_ACLKX+ z3 I. W" `0 P6 H/ J
| MCASP_PIN_AHCLKX" o. \" `4 f! R4 C- F+ E+ H# ?3 C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
@3 D q+ P3 z$ o0 |$ vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 G; M& z0 i0 i- }0 C| MCASP_TX_CLKFAIL 4 @2 d' s$ H! }( ?' u; p* K2 d/ j. ~
| MCASP_TX_SYNCERROR
w# N" n2 _+ N- X6 w( U* b: s) e- |* A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( {4 w/ D- g; Z5 W0 ?7 Q$ P
| MCASP_RX_CLKFAIL
2 `( j1 p" f% G' A' W1 b1 P. n| MCASP_RX_SYNCERROR
& ~! w0 `2 U, `( a3 |, ]5 y5 b| MCASP_RX_OVERRUN);
$ {/ Z4 j- W- G4 O5 F} static void I2SDataTxRxActivate(void)
, K/ i/ v) g) t5 S; K{2 O/ c$ Y* Y1 O; O/ A1 T% ` w
/* Start the clocks */
! Z2 k; w0 `* w, E1 M* ~2 w1 \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, ^6 C2 C+ [; ?9 O7 c# M: O; sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 U" W6 s( Q$ [% H+ \; M2 [+ k( w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- L* E7 d# O3 \
EDMA3_TRIG_MODE_EVENT);
8 Q+ n* Y. Y0 o& Z7 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 F" L1 D2 z; S, N0 \+ FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ q% A7 M3 A* _& cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" I6 I# Y* D2 I2 `' t7 G9 ~( e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. h$ X/ b, X) S0 a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 v8 r& Z0 W0 t6 }+ q; K1 V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 z6 K l3 u# f9 s+ h- L/ Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* Y& x! M6 d6 Z7 c$ J} 0 N) E, J* v4 n4 @7 A- A
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 d0 l4 _! K0 i
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