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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ U8 b5 F" c {' _input mcasp_ahclkx,4 p3 J) k7 P1 G# [
input mcasp_aclkx, }5 I3 q* D- c( u# N; O: A/ i. | d4 V3 U
input axr0,; ~9 A" }# S g9 V
4 L& ]; H/ O7 x# i% `
output mcasp_afsr,, L& c2 J/ c3 }
output mcasp_ahclkr,
2 |3 E% x+ W; A5 zoutput mcasp_aclkr,: _. }: s5 x) j) }$ W
output axr1,* P6 F0 k, j! F J% h9 |$ c5 C( C; M
assign mcasp_afsr = mcasp_afsx;0 J5 B" b& S/ ?4 G" {+ L" c
assign mcasp_aclkr = mcasp_aclkx;
' L {9 v' n3 J8 P% w3 h0 D7 `1 P% p; hassign mcasp_ahclkr = mcasp_ahclkx;8 i0 X( Y2 j* Y$ y. o& B4 g/ I
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! N' T" r- i- b( D, \
static void McASPI2SConfigure(void)
+ J% Z" B$ N" u4 p2 Z2 M1 ]{
; T# ~; X* i, H: c8 jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- M$ t! r! j2 _- h: x; h I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) c+ @6 q5 p5 p& d: l8 WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) Q/ R% ]3 |) E1 w3 |" ]2 M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ `3 q, D3 L# S9 S+ h! w: l7 K! ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 R0 t U* `2 F" YMCASP_RX_MODE_DMA);
" o1 k* y# E' \8 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ T9 o4 p+ i3 C r$ ~7 J1 O5 E& }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& V4 q, Y& j9 o2 y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 ?* z, v/ m8 F7 N6 R3 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ O1 u% _( r: MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 f2 T. `% O, M* c% R( WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 ~2 o+ I3 \' r1 L2 u/ |6 |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; c1 L& v9 U8 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# b' C& }" A8 s9 fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( P" R! H! Z. N7 N V% X& F
0x00, 0xFF); /* configure the clock for transmitter */
* J/ L; T5 p2 C* b* qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 ^. k% l: U* Q. {, L( h# NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! I& Y7 B3 H1 c) @" a- h5 B+ y( dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* C. l! `, z2 K- |1 s l0x00, 0xFF);
3 I- F1 l/ {% L7 K8 O5 W; g+ Z* ~
6 i& B; Q8 t9 G, d/* Enable synchronization of RX and TX sections */
7 Q( f" l- T; @2 BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 o' N |, y" KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: X3 x- z" w7 z! o$ a. nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, z' z" K( n+ L! v+ w** Set the serializers, Currently only one serializer is set as
* }% \* R1 c8 @! t8 ]* r** transmitter and one serializer as receiver.
* I% F; A: L0 Q3 Q*/
$ |9 d' p3 u1 ?5 \! x# ?) ` \* YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) s7 u: \! C& m* D; ]+ U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. z5 i4 U" }$ e9 y) ?0 M: Y
** Configure the McASP pins + U: j. f: m. @/ w
** Input - Frame Sync, Clock and Serializer Rx
- [% i. A3 v& M5 y3 p3 D3 X** Output - Serializer Tx is connected to the input of the codec 2 f4 L( v# y A; ^
*/
' {; K$ `( h: G& A6 D- y EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" o+ K2 D9 K8 h: V- E6 w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 x7 @/ @( ~0 ?! Q1 V5 G1 G3 }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- x& o2 w1 `: @# H| MCASP_PIN_ACLKX9 E- M' [5 H, \: Y3 r% M0 |
| MCASP_PIN_AHCLKX4 u f2 J0 \* X1 v" l2 N7 ~' w8 R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 F1 F' _. ]* [ a9 r- EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 T$ S# o( v T4 H- J- y
| MCASP_TX_CLKFAIL ! w+ V J) N5 X- h8 \$ j
| MCASP_TX_SYNCERROR
8 S2 r$ x" M; c/ R, Q! f& s, ]8 t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! @/ C! Z9 \7 n& j$ E& U| MCASP_RX_CLKFAIL
* X/ l6 \5 t w8 \2 p| MCASP_RX_SYNCERROR 1 Q: W5 P3 O+ h+ I- A( M
| MCASP_RX_OVERRUN);4 T1 g P0 b% z$ b
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
7 `9 ]* C. I/ {+ D$ n' b# Q+ QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 p9 p& ?% M; B% iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 e- L' S6 j2 c' V4 q) J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ J: L H U+ z
EDMA3_TRIG_MODE_EVENT);
7 i# `3 h8 W2 x5 X4 N( P% OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 l' h+ |7 _5 U8 o; ^3 V6 K; `6 k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 c4 Y5 g. `6 ^/ ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 ]& ?5 I# M- F7 W) H! j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 l+ n& o% C( k( \9 F# @4 {, V; U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 y( q3 T5 L' ~+ D) v0 s) e! iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; c K. p/ s# |, lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( W- ~! ^& A9 M- j7 `}
& Q) \: N3 q* f' N6 ^" l3 S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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