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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 y" g+ I+ u. i% Yinput mcasp_ahclkx,
# K9 W8 M5 d) M/ A: u( finput mcasp_aclkx,% n7 I0 e" u- p) X z% u+ k
input axr0,
6 E+ e: V+ n; g7 y- c w
5 z Q2 H6 n/ u# {2 m" ?! ioutput mcasp_afsr,
$ H8 I, j! i- \& F% V" z) G8 Zoutput mcasp_ahclkr,
% b+ `3 j' a% h! L* Soutput mcasp_aclkr,
/ t4 A) ~9 W% Uoutput axr1,( u; T1 T1 x2 q. U
assign mcasp_afsr = mcasp_afsx;
* K! e- B- u* |' K# U* oassign mcasp_aclkr = mcasp_aclkx;
/ n t& i4 r9 E# x$ N( e& M, w4 `assign mcasp_ahclkr = mcasp_ahclkx;
4 F# {, x8 K- o+ F5 Y$ a3 Cassign axr1 = axr0; 0 I+ g; r1 {& T% y
4 e( y: e' g: h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 W* g2 E V8 l8 B1 o
static void McASPI2SConfigure(void)7 f h) Q: n) r. e$ f4 A6 B8 T
{
; P. D$ J7 J" v/ [+ EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, a8 j3 e+ w4 G6 b4 t1 EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. m0 T) x; g( L* L! d, A2 H+ W( _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 d7 ~1 O: l8 l! h5 n5 AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 M! H5 R6 o; }: }; pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 }% z2 \+ _# D% VMCASP_RX_MODE_DMA);' G- Y8 f- N% m: r8 D5 j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' x4 W: W9 \. n: C& d6 n- v+ @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- W& F5 Y. b+ `% j" ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! q7 {6 V6 _! C, {) O; i+ xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 R, K3 K0 o: g O- ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, z: Q/ \' Q3 u. O( a% t! y3 k) uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 U- l* l; k% z3 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 U# p& A+ H; g' r: L$ r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 [5 V: l. ~. \) x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 j- a! \5 M4 X3 c0x00, 0xFF); /* configure the clock for transmitter */1 q. ]- q7 m, j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% q' P* V3 k0 J! k6 b* BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / a! J! b H% U6 j5 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 _3 Y+ S4 L% L. S0 q0x00, 0xFF);+ r( C- ^0 i- q: a, S" O
/ n5 M; }4 k6 [4 P/* Enable synchronization of RX and TX sections */
4 n1 } F+ ?& P/ W h- VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 P& J7 _: |& W+ S% ?8 _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 X9 D5 ~& @# q5 i) v( `) C* I0 OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 ^: |9 R8 k+ P6 R8 Y# Z0 D; n0 M: V** Set the serializers, Currently only one serializer is set as
& E9 a3 b+ S2 d" @/ W, S5 }; `** transmitter and one serializer as receiver.
( ?1 E5 u5 r0 z) F0 V*/ u E& P& s" b# L, k- U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ D L$ V' B! Y \2 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) S. b" y& U; ~6 n+ o, x+ C
** Configure the McASP pins + k$ C) j1 ]# `$ w
** Input - Frame Sync, Clock and Serializer Rx# P, D1 p, C% a6 a$ ^* o# O
** Output - Serializer Tx is connected to the input of the codec
) E! ^9 x. U" q5 d0 H4 g*/
& ^4 Y* L+ v5 L/ bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: L* A, {+ Z7 ~& |8 W& A, @) z9 x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" p& h/ N5 y" a' O. n0 R* i( X3 u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* J; ?9 w- o# c: l# a& c
| MCASP_PIN_ACLKX! a8 I1 v* \$ [2 E3 D8 n5 H) n. o
| MCASP_PIN_AHCLKX
6 P1 K1 d; [0 s3 s- W1 o L% Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 A! b! Y2 F+ t1 x% f/ eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " d$ K8 n5 {+ \/ Z
| MCASP_TX_CLKFAIL
9 r5 Y- s& F8 X| MCASP_TX_SYNCERROR
5 F; y$ Y6 ?/ f( \1 W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 u) U3 z/ L+ G& z& X1 ]; q| MCASP_RX_CLKFAIL8 l4 T% [+ G7 _" \1 O
| MCASP_RX_SYNCERROR
" [6 x! p& _/ ]: M9 u" V| MCASP_RX_OVERRUN);) h% K8 A: A' t$ ]0 y8 ~
} static void I2SDataTxRxActivate(void)
4 b5 v% D- @: K{, n5 m/ x$ o7 j. _ o
/* Start the clocks */) a* X" c( T+ P, B* ^, {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
S/ h" x) l5 L$ t% S2 M$ o+ E8 AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" O! p6 P% j/ n& q9 G, J5 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 F6 `! `2 u% k/ @4 Z
EDMA3_TRIG_MODE_EVENT);
3 x" e7 b3 k% o1 T5 v# B- g) lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % w: z! q8 k* R% E% w1 _& g# o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 V+ D7 A n( o8 E+ i) A2 _1 s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 b% a( P7 M0 O- uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# e/ F/ }* j- f/ Q ]( O* ?) l* `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 s( H$ f( P7 H3 y" F1 @0 I- g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 _8 Y1 b" e# b+ E; ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* B! Y5 a+ M& Q. M} 8 y$ M* c5 u3 l" {0 ?3 j6 y4 j: y/ x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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