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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 \3 J) @* J) v
input mcasp_ahclkx, F2 ^4 b8 Q" h; Y; V# r8 x/ T
input mcasp_aclkx,
4 s! h" f4 @1 Q, ]8 W( linput axr0,
: f* g. ]4 q% p: A- J& ^# o0 K* Z" z. a, ]
output mcasp_afsr,
4 l q; q* o D8 Zoutput mcasp_ahclkr,0 t. T1 M5 S7 w/ G: ]1 F
output mcasp_aclkr,
9 J. G, C7 i/ {+ n+ @/ c; O; goutput axr1,
/ \% z C8 B2 e' D1 f assign mcasp_afsr = mcasp_afsx;9 A' c$ b( h/ e: E* t
assign mcasp_aclkr = mcasp_aclkx;
6 a$ [/ b" q! p. passign mcasp_ahclkr = mcasp_ahclkx;. v+ L5 ^3 ~# L
assign axr1 = axr0;
# H4 y0 t# r4 }
+ J. e" S: h, M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( e L7 h* E k
static void McASPI2SConfigure(void)
1 e, q- X6 k2 G$ h{; O- l3 t6 K2 c$ O6 C. @8 N% w, d
McASPRxReset(SOC_MCASP_0_CTRL_REGS); @, K( O- V) D' K. ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. A+ {' E1 U& ], {! JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 _* x1 z9 j* ^, ]( ]( t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 U" T7 Z; k/ }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! c; S2 {. @! X: X9 I. V( {% Z
MCASP_RX_MODE_DMA);8 U( z- M' ^& i5 X. s( a! j2 N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& C8 c+ D w) ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 P2 m0 h+ ?- [( Q2 jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, }; Y; I/ s& W& |9 S4 c: j3 bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
t. u5 a+ V6 C/ L, [8 WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & Y8 ?5 g: _1 o9 T4 r9 v4 d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 L4 k' W' Q5 ` g* Z% B8 r/ wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 {) {6 s' V7 V$ S6 h$ w: C, S. V6 ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 Q: }3 R8 l" ^- D; `, D- A# H e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! U+ _3 ^1 @) c' B E
0x00, 0xFF); /* configure the clock for transmitter */8 h6 t+ }+ Q9 D5 T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 _' ` a; s$ U1 [( G* ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 w) }( g% l5 Y! H- XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 O% s* P! l$ r7 _) c! s! \4 J
0x00, 0xFF);4 V; R8 S+ x5 Q+ q f; U$ u
* R" |; A1 v0 d0 u; j# B* ~: Q+ I/* Enable synchronization of RX and TX sections */ 0 E2 Z: V4 t* s! o" n$ ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, z- Y. V" _1 a2 Y9 \9 w" B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* q V5 b! ]9 x% [2 k: Z1 e! e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 b4 h& J2 `6 [8 j( n( i** Set the serializers, Currently only one serializer is set as
. q5 M5 K8 J+ M** transmitter and one serializer as receiver.' r$ u% R' G7 C | R
*/
; N5 U8 S2 k6 j3 g, _! qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: @9 c: S# u5 ~) a+ {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 ^1 e, T3 u3 N0 A. G. N2 K% e** Configure the McASP pins
( ]0 w- P& l$ R/ O0 a** Input - Frame Sync, Clock and Serializer Rx5 M D$ q) E" P: W' L* |8 g
** Output - Serializer Tx is connected to the input of the codec
! }' F7 J1 G4 h; P; k, V+ s- M) [+ j/ I1 F*/
6 H$ g: J* z/ r2 G3 S! P- |+ QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% W9 D, i3 F% J' h" f$ B8 Y- o/ |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; s2 K. ^! Z8 ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# V- j1 K) }* f J3 F x$ F
| MCASP_PIN_ACLKX
; a* D" o6 z7 c* [2 V| MCASP_PIN_AHCLKX
3 I! a' u9 Z1 `' x& N2 ]% [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" q$ B9 y+ _/ L" ?( r# t4 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 K9 x. f/ `/ B$ d| MCASP_TX_CLKFAIL
4 k, h2 ^4 D7 ^2 |5 v, M" z% A) m| MCASP_TX_SYNCERROR
1 X! T9 ?1 P' Y* Y1 t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . A5 K {3 p) u+ U% T" _5 T
| MCASP_RX_CLKFAIL0 t+ G- \/ D3 {% _
| MCASP_RX_SYNCERROR 8 Q9 z; x; B9 \
| MCASP_RX_OVERRUN);9 p# q8 t( Z* {" z8 Q T
} static void I2SDataTxRxActivate(void) x! q' {) n& m7 e. T; q$ y \
{7 k: \4 n2 R t# }% y& q: z
/* Start the clocks */
1 N% t& _/ E4 [6 {6 qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& f8 p9 u# @3 e, P E& GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 c% L$ l6 Q# \9 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ z" F: V# A9 J, \' W* k- d9 L$ VEDMA3_TRIG_MODE_EVENT);
" ^2 k5 ^8 o. d/ w% gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 a# G% }6 I* iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& Q5 S; {: L7 Q0 ? ` y. ^& W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" u' p2 Q5 l8 p, g2 ^& dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 w- i& w, b* P5 V' I4 Q2 r' Q* Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& v* [. V4 D ^& p' i1 r7 T" t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( i: }: a' c! J2 u& fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, P2 i7 @7 f& L5 l8 n8 [
}
6 a! z, U" Y" T/ X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ F8 i, g/ K% e1 J. n4 L
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