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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 w% o& h+ x* E5 Y* e& {8 x
input mcasp_ahclkx,! m1 v: L; M% l0 l6 B
input mcasp_aclkx,
2 p- m9 w) \7 s' I7 c1 oinput axr0,- d6 Y& h7 g# s) v# V6 v9 z
2 M" f' P; p# |+ }3 ?output mcasp_afsr,- f! D3 ^0 C8 G" Q
output mcasp_ahclkr,
" k: T" V$ m Y) g1 r- eoutput mcasp_aclkr,
$ v* _6 T) d7 S+ y* x! Goutput axr1," z, F5 k* M$ U& \
assign mcasp_afsr = mcasp_afsx;
. r! L0 [! |3 v1 Rassign mcasp_aclkr = mcasp_aclkx;
8 r: B, x* o4 M% Lassign mcasp_ahclkr = mcasp_ahclkx;3 [8 L; d; l9 p4 A/ H. v) l1 e
assign axr1 = axr0;
* R# h; V- P: H7 b2 f% K" X& ?9 H: a: q- S! V! X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # J; N! Q! l z# Q
static void McASPI2SConfigure(void) t i7 [- g, Y1 [, c K' l
{
Z, K1 G7 u5 m1 {+ MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ ?6 n2 r' [- C; FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 C- Q) v0 `% o& g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 k9 Q% q( B+ w: I8 K; s4 R" R, aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" s/ \* i9 p+ V( v+ @5 g- L. C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 _! q9 B2 G7 B' Z, ^4 lMCASP_RX_MODE_DMA);
s* @& k; D0 J. TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," P1 o6 a* p2 Z# R6 m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! X5 {) {% ~& N+ y5 t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! W5 K! g8 J; j/ v! ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* D5 f& U7 `# c% f* v( W/ c' g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* E2 r9 |2 E4 f& X: @$ t0 l, IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# l5 N( n2 F, S- z8 y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 G6 D8 r. i: ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % k6 d0 j) R* k, c* Y! ~0 s- t* c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# {# |0 Y0 c, z8 Z0 C3 g9 m4 A- ], `
0x00, 0xFF); /* configure the clock for transmitter */
! o: S' U) O( J: |# b/ _ F1 ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 D: ]: Y7 }" n5 K1 BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 k' o1 L! x+ v' P" x5 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. a. s- S' G8 K" K6 T6 h/ G/ |0x00, 0xFF);
9 T( x# @3 ~, V1 u: H/ h0 F6 [# |$ B; S7 ^0 A. b e3 `
/* Enable synchronization of RX and TX sections */ * \: G5 l9 V" n9 v y( d+ z5 F; q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ e, {' x/ w5 a+ C* g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, }+ ?5 {0 h. H) C7 ^5 }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( E4 R' j6 P- ^" G
** Set the serializers, Currently only one serializer is set as
) W( }! U2 N2 s( d2 N$ {2 P1 }** transmitter and one serializer as receiver.
( [3 H0 _$ P) g' N*/
; d* p/ V2 l3 Z+ C1 bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 u, C7 H& m" A D/ q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! t' e: j+ m) }0 Z5 s ?' n) ?% I9 `
** Configure the McASP pins
4 C# L/ v1 s# T" O5 F** Input - Frame Sync, Clock and Serializer Rx
B Q$ g" p/ C$ z3 R" h** Output - Serializer Tx is connected to the input of the codec ' q, V$ ~3 H, F' }
*/
0 w+ X# z4 O" s N9 _+ dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: l$ X2 q2 H4 p1 j) R- `) [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! `2 W% [' F2 c& G& Z7 a' c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& i0 O) L# b" H H9 k4 w2 ^* B| MCASP_PIN_ACLKX( g8 S8 s2 ^: S5 f) y2 F* q, F
| MCASP_PIN_AHCLKX4 m% Q6 Y' z5 T; ?" e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 v4 V- |: c g5 a8 T' xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' }8 P7 T/ z Y* y; G| MCASP_TX_CLKFAIL ) l' }# ]4 _6 A* ~- j6 S- w
| MCASP_TX_SYNCERROR
6 n; N0 y5 S9 @5 M, V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# L h0 B5 C* o4 H/ X& Y# }| MCASP_RX_CLKFAIL
+ Q9 _; q: r& s6 p| MCASP_RX_SYNCERROR . t7 A! t* {# X7 S% }
| MCASP_RX_OVERRUN);, X E' w' s' |6 ?( d
} static void I2SDataTxRxActivate(void)1 L5 x _$ }, r: ?. M5 y3 ^
{7 a- e7 r$ [, d: J% K* _
/* Start the clocks */
5 F |) d F* P. j3 ^7 D2 lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 \. M& M8 L" q( n7 G+ tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# S: J! P) S4 Q6 a2 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: e' i2 L9 L3 ^, y* T/ {
EDMA3_TRIG_MODE_EVENT);
4 O1 l6 q% C6 X$ J1 ?* OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 [# _4 s: S3 l- O5 X2 W. f& h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# V! R0 ], ?4 UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ {4 C: j3 ]9 d- x, y& \( W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 j& {0 Y! j7 X) G M3 g% ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. i, W5 X/ K2 e- v3 HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! B! c4 M% Z1 B2 b# S$ v: a1 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 _) m$ d& O' q/ Q5 y} + W; h3 b! u5 K' C+ ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) z3 D1 [% k, [ J0 t) b
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