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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, G+ k: L" s6 ]
input mcasp_ahclkx,
! @8 ~$ [. E2 I5 j: winput mcasp_aclkx,
) B" G( j$ l' L6 E) p, d+ ]input axr0,
: e# m: q" j- s% e% Z& B: J% ?" f3 m" t# ~; r5 k
output mcasp_afsr,9 q5 Z M7 J7 u: t! j
output mcasp_ahclkr,, b$ Y7 u1 Y, L. K
output mcasp_aclkr,- s0 e" Z* i4 W* p
output axr1,
* W0 N' y- A/ q+ s, Q& G assign mcasp_afsr = mcasp_afsx;1 f$ j" e' O) N5 x4 e3 B
assign mcasp_aclkr = mcasp_aclkx;" L2 @6 u" D* f9 ]9 b
assign mcasp_ahclkr = mcasp_ahclkx;) m2 O5 n9 I: I) C7 t3 \
assign axr1 = axr0; ! v2 e# N1 P% ~0 f3 E( T2 L9 F4 X
. b" G, [) v, i! s# D2 Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 i+ q2 V+ t I4 z( N6 L
static void McASPI2SConfigure(void)
# y* Z! e2 ^6 z. L3 u/ p' z& t- e s{+ B0 m8 u5 }! L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; r4 h5 S" W' D' o$ `7 ]& {0 U4 PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- s1 j( E* ?. H5 B: ^7 E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 o, K( q* k* E6 b* z: PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) Q9 V% w/ f t0 LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' O/ a# W2 z$ {- n' c8 ?: \5 |' _
MCASP_RX_MODE_DMA);; E3 {+ Y1 z' Y3 b. }) K" l/ k$ @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( K. g* X2 R$ S' O4 z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# C6 p( M( n$ l, f5 V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! s/ v3 g" d1 w' @9 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
y( W* J, s& kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
?; B$ v( j8 b9 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ G" [7 p m# k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- C6 a; g! |' j" e5 U3 b. `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- }$ ?% t5 V0 s( H) @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 F+ m: X; e2 T" n0x00, 0xFF); /* configure the clock for transmitter */6 d# Q9 Q! s- ]- v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 c3 d" ? u1 i5 X$ I" m# Y4 R( mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : k2 J# f2 K) G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ b, ?7 {+ Z$ P+ q7 A; N$ }( r; ~
0x00, 0xFF);- h) ~- x' Z: M6 s3 K1 e
7 W( e6 m8 U1 H* [/* Enable synchronization of RX and TX sections */
, Z; W& K/ ]2 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ S0 b+ M% u8 n9 }( ?4 KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* j T% H V" o" N1 `3 k2 J9 bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ O) J2 E" t/ G$ V: |, o** Set the serializers, Currently only one serializer is set as. R1 a5 n: x" O9 z" u# R
** transmitter and one serializer as receiver. T0 o6 K8 Q' G" u1 G
*/
$ B" S4 {+ q" C6 ?) GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 A3 ~/ I% X1 R2 Z) D: kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ Y* b# L- P- R) r$ Y
** Configure the McASP pins
1 Z( d& J+ d8 D) f# ^' U** Input - Frame Sync, Clock and Serializer Rx
& F P. V+ V x5 _** Output - Serializer Tx is connected to the input of the codec 7 j1 \3 X- L2 \% I
*/
1 W& |) q# M, x" M/ ], hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: X q, U) ?% i5 K" `+ l0 U4 V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; s6 k' M/ ^! Y' v9 u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 B# Q; r- e+ C' ^+ ^% u: \4 I| MCASP_PIN_ACLKX0 {4 o# u* I$ ?( M$ y4 h: q6 r) v
| MCASP_PIN_AHCLKX
) e J' d% \" E+ i4 \' _# X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& }" s/ u5 ?8 M0 d( M' j8 x( z* ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * N+ V/ W! G4 c$ u
| MCASP_TX_CLKFAIL
' B6 ~' p' X: O( P; V% B| MCASP_TX_SYNCERROR8 H9 x: B7 H- P5 k, {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 S8 Q; _0 r" k: ^7 s* P J Q| MCASP_RX_CLKFAIL+ O# W7 ?2 H! ]4 e
| MCASP_RX_SYNCERROR & ], [. W1 w: }% @5 c
| MCASP_RX_OVERRUN);7 [7 `3 B' k; V# o+ I( H4 u
} static void I2SDataTxRxActivate(void)0 i- r7 K. G3 U+ n9 L
{% m, K! t8 K9 S$ H4 }6 H7 d! g' z. n
/* Start the clocks */) X( c) s+ }" [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 D3 \1 `: W% [6 V' QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ G' m5 T1 U- }) h' I8 e! nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& B) R/ m6 }0 b2 Z: ]4 f% o
EDMA3_TRIG_MODE_EVENT);# t: e$ Z, L& X2 V7 I# u* [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 d8 P' E/ Y. r5 u; _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 c9 i3 W0 g# P$ w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) V/ O! ~0 p, ?5 B B, A, z. ]0 IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# g9 ]* s) i! M, s- ]& W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 y$ i0 G+ M$ xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 x% p7 D7 I* N7 Q0 {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- p6 j+ R3 }8 G* {} 2 X1 t5 ~5 E9 b1 V" o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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