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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- m0 ^4 |$ `( h. s' linput mcasp_ahclkx,5 U, Y8 u. ^- ~. s- R, p( q
input mcasp_aclkx,' a+ d/ Q( {' |
input axr0,
- D$ T: _: T6 b2 Q' p8 E) ~/ b8 j
' w2 l- m) L) ooutput mcasp_afsr,; t6 x1 S+ e/ P. I6 |/ l; y
output mcasp_ahclkr,
; \0 y- i. P& b K- _output mcasp_aclkr,3 p. G7 }, b+ S' C; a
output axr1,9 ]" W+ z. j" W9 {; A4 E3 L E
assign mcasp_afsr = mcasp_afsx;
* g2 r+ o1 ]' R$ dassign mcasp_aclkr = mcasp_aclkx;
! i8 V0 b, `8 @3 q# I aassign mcasp_ahclkr = mcasp_ahclkx;- r# A( l& U! H; ~
assign axr1 = axr0; ! {% i8 P& b6 t: `1 h" Q1 ~# I' R
5 t8 g' ]) a1 d# ~2 ]( Z4 n+ Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 m6 {6 w8 r* y! W
static void McASPI2SConfigure(void): {' }( {( Z0 \ J7 D+ W0 \9 R' G. t
{
" Y$ e1 Q9 r4 \( ]' V4 A; PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ b" M/ Q. {. O- j' A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 S& s; J! v/ Z+ m0 F" vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; i7 N6 O2 l. y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 i: V, U- }, L6 j, Z7 k) v0 KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ C3 X/ U* R! l# w8 P/ E' _; CMCASP_RX_MODE_DMA);
# q, o" L, n9 i: o- D0 k$ ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) s& r4 f7 z' O$ F! \3 `0 S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, m, l; p$ }3 O- t, IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 R* {7 J% R4 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 V7 O* ]" \- O1 Y, _. SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + @* P( o; l4 R0 _( T# S& B+ W M# \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 Q( J/ c) G5 y( H. p6 S, {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; i' _# z! c! [6 {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : A, f4 W3 V& @$ ^* N8 J4 j) V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ J5 _$ w: }( Y E2 }
0x00, 0xFF); /* configure the clock for transmitter */6 g2 p* ]+ I* W6 r, o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' D* l5 E& Z# L5 Q) n2 l W) l2 k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 U, {$ D, F' c% |0 VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 N( Z& _) m9 D- b* U* p0x00, 0xFF);% M O8 p- y! _ o
: w5 `5 K- H& P7 N
/* Enable synchronization of RX and TX sections */
! z/ R0 C) k8 Y# z5 l( pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& j$ X" {) i. I. S) u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% B6 ^7 {3 ?( ^! Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 e" I6 E* M' k' |* k** Set the serializers, Currently only one serializer is set as& I( z* c, C1 A# U1 Y, x
** transmitter and one serializer as receiver.1 r m" e5 o" }6 t* g
*/
5 G! {5 t6 [$ CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); V. l" N7 |7 o& @7 V& e( ^8 q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 N6 x% j* |3 G9 W4 r! |** Configure the McASP pins
$ l: @* S" F; M3 b% T3 o** Input - Frame Sync, Clock and Serializer Rx3 I, |: d; ?# W4 `0 }. d
** Output - Serializer Tx is connected to the input of the codec ) t H$ x/ z- ?& _ ] \
*/3 E3 ~% T8 |) n" e( \* G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) I# {0 h/ z+ K! ]2 w) P: ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. |4 e- `1 ~1 g0 [3 M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! F& }* j1 g% [; p4 | _: t {| MCASP_PIN_ACLKX
, M1 j+ H' Z1 |) y7 o$ w| MCASP_PIN_AHCLKX5 o( y; L+ M. b0 _3 z0 w1 e) ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ c5 N. N, T+ j( S# c5 DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 c- Q2 m( Y+ G! }9 w: D: M
| MCASP_TX_CLKFAIL ! @/ d, [/ A" q9 h2 k5 o
| MCASP_TX_SYNCERROR+ ?$ p- n0 s* _9 r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
G" g$ O( G2 {" t1 _3 _) Z| MCASP_RX_CLKFAIL
* `8 N9 m- D. B3 G' I- ~5 ^4 ?6 o, A5 z| MCASP_RX_SYNCERROR ' l# a- W9 l$ B: d
| MCASP_RX_OVERRUN);' j. D6 K" W% y
} static void I2SDataTxRxActivate(void)
, `& X9 p9 c4 U) T2 g6 K$ l/ {( d{; Y# }0 R4 n. q8 I- b# D; L2 H) L
/* Start the clocks */' W/ Q6 u" r' A4 J* `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# G7 O7 M" { \# V8 J& [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ i7 z5 |; O4 w* y7 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' t0 O) L9 Y6 s* M
EDMA3_TRIG_MODE_EVENT);& F/ k- @0 n- U6 {$ Y" d9 a( L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
c7 _* U) y9 u6 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% R5 x- r- X8 M, M6 e6 b( l1 |) z+ F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" H1 z- _; ~4 N. R! l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 x$ V8 o7 y( H+ }# |% z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ t; \! q; J( I* z v# i! Z. mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 o [( p2 v' p3 V1 r5 P$ |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ h' j0 f4 V* A$ ^ U6 p' F}
" O9 S3 U) N3 l. j0 ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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