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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. i' r# x) m) Q U* ]" E: |
input mcasp_ahclkx,
8 I4 H# p! D, x* B) C: rinput mcasp_aclkx,
i1 \7 x1 p" q; Uinput axr0,/ N) K2 q) M2 ^0 b
5 L$ [) I4 k! i5 woutput mcasp_afsr,; e4 D ^ a5 A9 u' s
output mcasp_ahclkr,
7 L- L5 z, W+ houtput mcasp_aclkr,
/ [9 z5 C6 K& [! h& Eoutput axr1,8 m& a4 {1 g" c& D6 G# y- e
assign mcasp_afsr = mcasp_afsx;
: T/ i; `6 e' U) A) C) S! Aassign mcasp_aclkr = mcasp_aclkx;: q, X6 |$ R9 F- A% o0 K; }) v
assign mcasp_ahclkr = mcasp_ahclkx;
) _) N8 P b: a# T* gassign axr1 = axr0; 1 h. K# y+ y- J
- L% \2 l; w. _7 M7 \. H B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% y) `! A8 H# M0 Z3 S! Lstatic void McASPI2SConfigure(void)
' ~4 M& [/ v+ z4 N+ B! `( l" ]{0 c6 D g6 F: O& A. K! I' c% o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; n" g& {/ `9 g; s" v* v8 M; U7 W7 |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- _/ z) L& a1 W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- g; p7 a4 F8 m7 C: t. sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ v/ y/ d2 q/ J" s) u$ M9 vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* u) G4 ~, P0 V0 r0 Y, |7 NMCASP_RX_MODE_DMA);% Z6 k8 A9 n1 |- _0 L6 u) r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* Y7 w( f( m* E" i& t- AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- v+ d4 \: J& l7 Q" v1 c. \7 BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 Y: D y: S; S6 n1 t( k4 A0 }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ e9 d1 P6 n/ s! W8 v. C: V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 ^* i s% M0 I3 j3 ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 u0 d6 } g- E1 p7 B3 @' UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ t# @+ y) ~% _6 U7 a, K0 A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 g1 ~8 j: I$ Q+ W7 H* F& w- [' X' VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 B# r- b$ ?6 J+ K e6 r/ c
0x00, 0xFF); /* configure the clock for transmitter */
. Q/ y' a2 h2 D8 L* ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; ^: {. g0 M4 h4 t, k4 [# AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! s( r" s! F3 Z; M, K4 LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, Z8 [ W K+ _$ m4 O( N" v% c. Y; R' o4 R
0x00, 0xFF);
0 M) G9 Q; j* X- Y( L/ [
2 x- }+ S. b! h/* Enable synchronization of RX and TX sections */
- b7 n) z; _: H7 R! }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ [7 H1 W$ ^& l1 f6 Y0 LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 c: G3 C. ~9 j' T+ V9 k6 CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** w( z0 m M3 Y' `% Y4 j7 ]
** Set the serializers, Currently only one serializer is set as
9 T; \8 H: ]: ~; |% A% [1 J** transmitter and one serializer as receiver.
4 T6 o4 k( V& Z' Q# |: W6 d*/
; k9 F- R) d8 ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 `/ ]% ~6 k4 p3 s W, HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 w, M5 D4 Y0 d! q) t" _** Configure the McASP pins
# k* a K' u3 c6 a( y** Input - Frame Sync, Clock and Serializer Rx, L1 |" V( r7 Q- b
** Output - Serializer Tx is connected to the input of the codec " U" g" p0 I8 r2 l- j) m6 q* z
*/
; l j1 M# p- L- w l# KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# R" q0 {/ i% `0 t I- ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 f; U. e) [7 s$ A+ F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 U5 O9 i# C5 ~9 ?# x
| MCASP_PIN_ACLKX8 R5 H0 @, V' L
| MCASP_PIN_AHCLKX2 M1 r: S1 Q0 X# M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 Z% K0 ?( a6 v2 F" [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# m+ I# P( j7 x0 C% g| MCASP_TX_CLKFAIL 7 w* t/ F' n; @" A
| MCASP_TX_SYNCERROR8 v, d6 h! d# F( K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ `+ a6 ~; |% A| MCASP_RX_CLKFAIL
4 z' w# v3 G0 O' X| MCASP_RX_SYNCERROR ( D3 \1 O! r, m3 D9 g0 {
| MCASP_RX_OVERRUN);
/ B9 N! \- r6 Z- |$ e- _} static void I2SDataTxRxActivate(void)
6 r3 a* t( b/ _) j3 E{
% w& F/ r/ y6 y) |! V# O. ^/* Start the clocks */' o) J9 c& ]6 W$ H' h2 s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 p! M s1 k8 g/ e/ S% N9 D/ oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 j' s, \" e* g6 g) z3 a! sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; d; B) X8 Y7 X c0 f: i8 NEDMA3_TRIG_MODE_EVENT);, b$ a& m( |4 t0 D$ Z7 g6 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ A+ V6 |8 x3 _$ T0 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- Q/ a! r) M9 e' M0 TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, Z' h4 [: O) N& Q2 vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 D+ A; d, G( Q$ rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; ^+ h) m' S) o# P6 w7 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, Z) r( q1 i1 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! F: r- h* t* T( e6 s}
% G9 X, A o/ S' }* D* h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 @! M5 h. k4 u( @
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