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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! n' s J/ p% K# t4 V8 V6 L
input mcasp_ahclkx,
U( U! J. u4 c; rinput mcasp_aclkx,
# k+ N' y3 [3 ^# zinput axr0,+ r) w! S4 D, u* @7 @6 e1 g* x% }8 d9 N
" g) V5 y' q: j! z Y+ }" `6 z
output mcasp_afsr,
! y- D* b( i; D; R# J3 [5 v3 coutput mcasp_ahclkr,; U" h5 q/ t c5 M1 N7 g6 i l
output mcasp_aclkr,' p' j( ~$ S- [0 X, n; }' k
output axr1,7 N3 I4 q, e+ z, k1 w8 j* V; p
assign mcasp_afsr = mcasp_afsx;7 d' A- J& N1 x& q+ B
assign mcasp_aclkr = mcasp_aclkx;' y7 ^$ D9 _6 F
assign mcasp_ahclkr = mcasp_ahclkx;8 E0 a6 J2 N+ K6 B) p w+ W
assign axr1 = axr0; 7 V( ~' q& h& n! i
9 l$ g* l" L/ [5 m! x6 i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* _# p4 W- A& p0 D7 i0 l+ }* \+ ?% nstatic void McASPI2SConfigure(void) g; I/ A: s: W6 i' u& e
{
! C; X2 U7 S. `6 c5 _, VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 ~8 ^* t/ H) I; I0 @# j/ H8 Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: p+ k8 X: H( z% r5 o T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! n: t* U3 o8 Y- M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& u. \' N: l- i# \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 _' Q" L( M8 g; U# H+ QMCASP_RX_MODE_DMA);# F1 N. X, ?5 W: T# K9 I2 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
X- b' H- C( q5 {6 o: @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) S4 T2 K- g1 t% U: ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- t! X7 r! ~$ A+ rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 e" X V ?/ P- @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. }* C$ z% X7 l9 V! uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 n/ E# L: F3 P/ W7 uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; U; r% C. w6 z: m* T& b3 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; s2 e6 I7 v2 {/ S) y$ ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- E( m# E w& I# z8 K) f0x00, 0xFF); /* configure the clock for transmitter */
- T- k) |3 n* ]& N$ e* m; uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 Y& E* C8 j2 l) E X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( N) J) I, k* c: H" c3 d0 b! _, a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," q1 r* T4 B: J, @) L* c
0x00, 0xFF);4 U0 o3 R1 @ p- s( a
, x# P" _- ` z$ r0 R9 H. g: u/* Enable synchronization of RX and TX sections */
. b) M! U0 {$ B1 y: W" t* y) TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. ]; S# h0 ]) p; }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; K# n) E$ T8 Z# M' x0 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% k& t5 K; T* D; p2 B. F$ q" k** Set the serializers, Currently only one serializer is set as, P& ~( r' `9 G; J+ ~, ~* c- y# a
** transmitter and one serializer as receiver.5 l+ Y6 K3 a, k( K' m( b
*/
( |' ~. i) A+ iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! n( h8 h0 E2 ^0 Y* D% |" K' t1 o LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 b' i( \; J) t2 c& {+ b0 l** Configure the McASP pins ! L) Y! h0 n q# S
** Input - Frame Sync, Clock and Serializer Rx
1 i+ E1 [: h: L& V3 K) c5 z# z& C( w4 h** Output - Serializer Tx is connected to the input of the codec
/ y( k* y# p5 z0 O C# {1 v( D*/
8 D3 d9 [8 q$ D, p* IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 ^" y+ S' Z4 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. b. t( v* _. ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- Z4 v1 Y) B6 K3 ?8 h2 ]" E0 S| MCASP_PIN_ACLKX
& z( [4 l/ ?, v| MCASP_PIN_AHCLKX
7 A2 I' E4 v8 l# @- V4 r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& d1 y4 }# y! y$ W. l, hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, {- f, i6 y' d' c$ E- Z" q8 i3 a| MCASP_TX_CLKFAIL
W- n5 }; [& q# Q| MCASP_TX_SYNCERROR9 C, i) h: i4 S# h# B4 O$ S R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : o; [. Z x% O {
| MCASP_RX_CLKFAIL
. O% q2 B' I0 \8 C' }| MCASP_RX_SYNCERROR ! E' ~7 f e3 s9 L+ P( ~: k
| MCASP_RX_OVERRUN);. H6 z b) l1 X1 ]2 |' D5 }! k
} static void I2SDataTxRxActivate(void); ^! `1 p. g0 Q6 ^
{ D3 W9 S+ ^0 j! X0 Q3 N& x! o
/* Start the clocks */5 E' C8 G- y) J/ U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ ^% k9 K' G) n% _+ ]1 `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ ^# ?3 N: u5 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 [' g! Y3 R# O* n0 d! V: B# q1 g- i
EDMA3_TRIG_MODE_EVENT);
6 j5 O) o$ K8 u3 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( H9 N8 h$ t, t7 }, x: O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ m+ v# x! ~$ A0 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 t- A+ u8 S. p8 a( X4 B" `( |1 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& n; F+ t; K* F: L7 o$ D4 \! g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% u" H9 u8 I; z% e. `& m AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( U; w& v" ^7 w1 r* A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( @: H, f) E" Q$ @) _: K} }9 s' a# v% @1 k& r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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