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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ E+ x5 w- v2 M, l$ ^8 h5 Qinput mcasp_ahclkx,
* b/ }6 @( s e6 _7 w% Vinput mcasp_aclkx,
7 u( _, m l9 \+ s% ^; r+ pinput axr0,7 A$ B7 r% Q4 ~2 F& J$ |5 R n1 r
* W0 i6 c, I3 ]" V) h& M5 A# } ^7 s4 }
output mcasp_afsr,' y! ^1 _; G! t
output mcasp_ahclkr," B) o- o- r+ t" t( u, f4 k0 D: A
output mcasp_aclkr,
4 k2 V2 w6 Q( Z7 N4 s' K: ooutput axr1,# m$ n, O, _/ C- E1 U
assign mcasp_afsr = mcasp_afsx;
; a* l- Q( S9 ~assign mcasp_aclkr = mcasp_aclkx;
, F+ G( a6 k) Wassign mcasp_ahclkr = mcasp_ahclkx; Y. l8 i1 n1 p; M! K. G D/ K6 d
assign axr1 = axr0;
' G, d) S7 I# `9 y6 Z7 V$ _) D" R# R8 r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. s3 m0 a: a4 t& ]# Vstatic void McASPI2SConfigure(void)2 o R |6 N9 ?* v& R( `" }
{
1 [2 ?- n5 l c6 W. L" p j( o5 aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# F/ G8 D1 g- x! F1 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 y( P3 k+ V1 P2 d) f6 v8 {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 \1 w- e9 M. [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; K% W9 [) n# N3 Y* f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 H+ e, X' n# sMCASP_RX_MODE_DMA);
" z5 {8 Q* J9 t( r2 b6 Q9 hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," [7 W2 J" P t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ z' f' V- N, D: z/ f' V/ f4 g( zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , G: L6 D) I; c+ t Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* R) r" \, t, S8 D) P: P, C4 Y, I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 @7 M$ [, z2 T6 d& m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. [( Z; x& Q& ^: W" ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 u' H* b% s1 Q8 nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, g b9 x* P( c$ t, W2 ^: oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, H$ o/ ~9 g/ k; U
0x00, 0xFF); /* configure the clock for transmitter */# \$ T4 F' B8 O1 h5 B+ @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 b: K$ s- z, u. ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 p7 ]: `5 k& u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 x4 a! e z9 `2 j- N8 i6 N
0x00, 0xFF);2 {2 a( U3 M* U c( e3 L* G$ z
6 \) v: s' V; W' R3 X/* Enable synchronization of RX and TX sections */
/ p% Q5 r5 x2 }" Y* [- Q( m* qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) d+ h! p. x% Z8 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 B& M3 e" X$ e% t0 P8 UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 D7 F: s, J) ?; I! z5 A
** Set the serializers, Currently only one serializer is set as5 m' b3 t" E# P1 t4 z
** transmitter and one serializer as receiver.6 m- d$ u; ?9 |3 r+ ]- h
*/, O8 d1 B- g6 w0 d* r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& t% z; J' ]# w: l6 s7 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ U3 E0 U: n% X** Configure the McASP pins 0 U9 a* R- J N0 F+ Z
** Input - Frame Sync, Clock and Serializer Rx
9 ^* l( d! b. F8 b** Output - Serializer Tx is connected to the input of the codec
7 Z' _. y! Z$ P& ?* Q# W1 b9 j*/
" E( O. S- ]( NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% I! u6 ]) t7 \: A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ _+ |- U+ l; @9 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- @, _6 h& w B9 n
| MCASP_PIN_ACLKX1 H* J4 ]1 p5 E9 U! R4 F3 W% i. @
| MCASP_PIN_AHCLKX
, |: k* K! D: w F+ n+ d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 M+ C' l# K9 j+ `8 Q! y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 }! n h! K7 x5 z! g3 H
| MCASP_TX_CLKFAIL 6 }- B. x. m3 K% D4 g a/ e h
| MCASP_TX_SYNCERROR0 o; s9 H. |* y, z4 n) x5 h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / F% o. F* A3 I. c* c, h+ M9 E
| MCASP_RX_CLKFAIL
8 n$ D/ M5 d3 d+ f| MCASP_RX_SYNCERROR
: M0 p9 J6 ^. |+ y" L| MCASP_RX_OVERRUN);/ [: E |6 G8 {0 s- W$ o0 }/ C
} static void I2SDataTxRxActivate(void)
8 I l2 t8 S9 k7 \. v{
8 n5 `, S( L9 [% ~# x' `/* Start the clocks */
( f% u* T$ z0 C! HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ p$ Y, ~5 F% v! L& `! r: D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' ?" S: s# ^* U4 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& G; p1 Q% V2 X; J2 }# F- m% B
EDMA3_TRIG_MODE_EVENT);8 A! \: q5 e- t1 ^; {) k' s7 R% p8 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * ^5 L: V. i- c0 p, O& Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 m8 k1 S3 P' Y( W7 N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 p/ i) h A+ W7 c7 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 t. c" c; C5 {' k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" h+ e8 Z1 r9 R7 {- M3 f. q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 R7 R1 ]& a* g& }7 ~$ h; [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) v$ t# w& `& |4 T2 K
} " D' C4 i! B1 ^, Z. g; o1 N- F8 N; `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * t, a# x3 k ]( A
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