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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. j/ M9 K% _1 U2 J# _3 u9 U: z1 @, hinput mcasp_ahclkx,
7 |, E1 S1 g8 w& W1 y% ]# Oinput mcasp_aclkx,
6 S3 o. e) M- d0 l2 J- e7 Vinput axr0,$ X' O" C9 }# P
. F8 d; L: Q1 ?output mcasp_afsr,
% ^+ K; b' T% y% uoutput mcasp_ahclkr,
- x3 U Z9 |% {: ?# }* koutput mcasp_aclkr,6 n! g0 b; {: j
output axr1,
9 e) L+ {$ _8 R assign mcasp_afsr = mcasp_afsx;3 M7 s# ]5 M: U/ i
assign mcasp_aclkr = mcasp_aclkx;& @# n; {. H" U* O2 m; y
assign mcasp_ahclkr = mcasp_ahclkx;
1 L8 E( ]3 ?3 N& p+ Y% o) ^9 F& xassign axr1 = axr0; 8 z4 H( E8 y' R. q
2 g' Y. O$ X( C% O3 d, `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 o* X0 H' [) vstatic void McASPI2SConfigure(void): r/ g. Z- [% u! I; y
{, M w9 a0 X4 y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 `' E3 S/ A+ G4 C0 {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 o( `4 A3 E- r. ^( ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, m: F9 F" s6 o. R9 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! q" n3 N4 [2 v' W$ {0 |5 y8 E* t, UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& M' y i2 e; z$ N( g1 G
MCASP_RX_MODE_DMA);
2 i3 e* ]/ {: @9 F) ]4 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 {$ e) i/ _. s5 a: Y6 ~1 E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 u6 T, k5 d) qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 ^2 i# j' `" R, m5 @6 lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 f6 H+ q" p' w7 j0 Y$ T5 h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 b e Z4 _5 g" S5 c& b& @4 ~, hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, t0 o( I) H) H5 t! V3 U! X5 o% aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! Z, L1 j. R" B3 B3 [) X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ d2 K; X7 ~8 H2 |! Q1 rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! _1 G4 w* P9 w8 w; A* P: ?0x00, 0xFF); /* configure the clock for transmitter */
& A: T+ u* ?9 MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& h3 k9 A0 R9 c. U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% R. k% o0 ], W! O' J' H2 k" NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% p# z3 j+ o9 g: e/ Z; ?
0x00, 0xFF);( c/ m9 R9 G1 V8 z- l- R5 X8 r8 D
7 f* V6 ~ M" y2 {% }
/* Enable synchronization of RX and TX sections */ . Y2 C! w3 r+ g4 ~8 _) S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& f' @$ D' h/ u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 A' T7 J* b6 T5 I5 l, b" z! [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; e, v! U9 N9 O$ f
** Set the serializers, Currently only one serializer is set as* f1 d8 W8 Q2 A H" f
** transmitter and one serializer as receiver.) M0 h, J W+ L8 ^; i
*/! g1 }, ~8 z' _8 p D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; B t" i: \ D( c5 T* }1 V3 d$ _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- x, C3 g! E( V** Configure the McASP pins d3 X1 u7 a( w2 ?
** Input - Frame Sync, Clock and Serializer Rx0 [5 w& e) ]6 T2 j$ X
** Output - Serializer Tx is connected to the input of the codec , m' r4 O4 \8 V u0 A
*/- Y/ S W$ H C, u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 \. l; c& E$ T% Z) c8 K* @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 ~6 X8 j; l$ s) A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# m" X! e5 a) a% ]9 z; ?' i| MCASP_PIN_ACLKX
# [' U \( C- W% N- L5 W| MCASP_PIN_AHCLKX7 i" ]/ S! d# L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' a" E g# c9 z6 N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. f8 J. k+ M0 d& w! M| MCASP_TX_CLKFAIL 8 i! B, ]# F; L2 N
| MCASP_TX_SYNCERROR+ i' a/ x* ~5 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# U2 u0 N' t; w| MCASP_RX_CLKFAIL
( J2 o8 B; x5 _9 I9 Z| MCASP_RX_SYNCERROR 6 D$ m2 Y3 @6 u2 K0 j- t
| MCASP_RX_OVERRUN);- ?' B7 Q& a1 _) P2 f- x; T
} static void I2SDataTxRxActivate(void)
% Z6 A/ q1 ]4 G{* ^ `5 D u) I: P/ l2 C" S8 m: C, H
/* Start the clocks */: \" Q8 N% @, e+ B- d2 L8 s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# Z! x( H% i: `8 b7 `: o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ m( B; @+ ]" Q7 K c! S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( F. N3 C/ l1 _4 r! Z* @0 b NEDMA3_TRIG_MODE_EVENT);% a# P* U: _, X, }- J. E: n. e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# L8 j' S0 p; {( `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 Y- p9 N$ B; q9 s- nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ B8 x7 ~4 ~% `/ q1 ]* L# A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 I# v6 a! j1 h7 e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' q: D9 q- n& u% a; c+ L7 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" P7 `1 ]7 {0 Z0 r+ y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 B5 G5 j/ e& S) L8 L
} ) V( s1 o1 f# s/ O9 e8 U; c6 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 l: p$ ~- g/ _# w( [8 V* F |