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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' {1 g8 ~% [( ~$ s% Y
input mcasp_ahclkx,
- t3 x5 F6 j3 d- z- minput mcasp_aclkx,
Q, J) \( L2 s# [! L+ i8 d: ]input axr0,0 f- g a7 G# i1 ~
+ |5 s; U1 |1 u4 e7 _# O5 N3 Woutput mcasp_afsr,! w& t: o! y. O9 h6 T$ @
output mcasp_ahclkr,* b% Y D3 I! h+ l7 W g
output mcasp_aclkr,
7 L; w* Y( @2 Z, i, {output axr1,
9 s4 R$ F2 ~" g' z0 U! W' h9 }; k4 I assign mcasp_afsr = mcasp_afsx;
/ [/ h1 x. w- r# y: zassign mcasp_aclkr = mcasp_aclkx;
) ?) m2 b* s# N2 H% B3 n3 uassign mcasp_ahclkr = mcasp_ahclkx;4 X, W, d( A0 O
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 Z/ f& S% J' ]+ T$ l0 m
static void McASPI2SConfigure(void)
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; ? A! Q, K; K, d7 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 Q( G" t+ `' N8 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 d1 v- g# Y; Z/ P5 ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); L; ~3 Y K v6 ^7 B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" I3 T: }/ [. [1 K7 z7 f( m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, ]- X9 L0 [0 W$ h& s" ]9 r
MCASP_RX_MODE_DMA);
; p; E0 b) Y$ y0 b$ b) u H& k0 hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% e& C0 }% O \, V! nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 I* v) K8 q9 G) u% I0 O" DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) k3 B @( J M, J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, C3 D- c3 c% `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 M X0 e o1 V0 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 E" v, I. e4 N, C S+ A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 _! u$ T' H; k7 d7 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# x' _4 D$ i7 {$ i4 E6 c; AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( T. j8 }/ u8 u& A$ T0x00, 0xFF); /* configure the clock for transmitter */; c/ L- q. e! X0 H3 s0 Y+ y* R7 O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
o9 ~: q& T, tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 ]/ }0 ^0 y0 y. R* QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 \2 p4 y9 s3 `2 m" P% [0x00, 0xFF);( S# {8 J8 P& s0 w5 O0 ?( {
. q8 v) ]" w `/ j2 x0 i
/* Enable synchronization of RX and TX sections */
Y& d7 {: m t: mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% f. J( O- T4 F7 c& AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 G: ]7 k% k c$ n& [; R8 {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 |% |* X" S, d4 \% t
** Set the serializers, Currently only one serializer is set as
& P% }9 ~( y3 ^: r0 B9 `- ^** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); h) f7 J9 ?3 o( K8 R+ q3 m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 @, m* N/ r: a7 w8 J& c& L** Configure the McASP pins . Y$ Y9 D- |1 P1 X
** Input - Frame Sync, Clock and Serializer Rx
1 ~3 P' _) \, B) q** Output - Serializer Tx is connected to the input of the codec & w' S8 r% g' X9 u2 ~
*/
8 ]% h: `' F2 p/ m* p$ D' IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 b6 U& v8 M6 W0 o3 m8 W! _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# u4 C& l2 R1 c1 m$ `) YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 R: k5 t% s8 _' \9 q' I| MCASP_PIN_ACLKX+ p$ M9 `% V x# \8 R/ I" z: A3 q
| MCASP_PIN_AHCLKX {8 [8 h9 a9 T# I6 M% J2 V* [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" Z7 n* N( _1 Z% u4 |7 ~ S% ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 W3 ]9 r2 L5 L% e- I' K
| MCASP_TX_CLKFAIL 8 S! e, A, B: W$ B" s3 O
| MCASP_TX_SYNCERROR
: E p E: \; S/ d% P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ I8 v" w- | |+ B% P E/ U: w4 M
| MCASP_RX_CLKFAIL# A. H6 W" i1 n
| MCASP_RX_SYNCERROR
8 ^$ m( W1 p6 F+ A) L5 R- g3 Q* x| MCASP_RX_OVERRUN);) V" `- F+ U# \( S! O. r( c
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */- f, ]0 q. P6 w' K! w6 }2 A6 o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 B3 u( ?3 W7 p/ E& Z! F" d& b. FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& D6 _! _8 C. w: ?, pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. j7 H7 u+ r' {3 V* ?$ h# K, D
EDMA3_TRIG_MODE_EVENT);
' N$ B2 V- F' {7 {3 r. h4 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; [! [) ?* B" p8 ?+ H# n3 O qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# d* }5 {5 D( m# P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ d2 ~6 J+ H! I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* t$ L4 E. n- R- _; T- u+ Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' A- U0 u9 h- k6 T1 V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 B$ C& L# c; t3 E5 OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: o6 l+ c0 a2 m
} 3 F1 S3 H3 N& S2 y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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