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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* P8 Z5 _/ j7 V, ^* _1 Y5 x0 p8 h% jinput mcasp_ahclkx,4 L- t+ H$ l( u) m. v2 v: W& I% N
input mcasp_aclkx,
R9 k5 e6 O( S* {input axr0,
( Z2 h1 C2 p. N: O& |
# [8 b9 X" Q' A0 c/ `4 U' E7 [output mcasp_afsr,# e: G* v0 W+ L1 o9 }
output mcasp_ahclkr,
, c. `$ ^( I% }; r* ]! Houtput mcasp_aclkr,
# ^4 B) L9 w; D! woutput axr1,1 }( g4 S6 I$ @- w( H
assign mcasp_afsr = mcasp_afsx;$ K/ t2 Y! N$ O1 d, p$ e
assign mcasp_aclkr = mcasp_aclkx;
% K4 q" E/ x% j2 h4 W- ?assign mcasp_ahclkr = mcasp_ahclkx;0 S/ C: t+ ^+ H- h. S
assign axr1 = axr0; ) V7 v7 b- w' O9 N& x
, n# e+ T* J W/ q3 \7 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 I9 s& I1 R" @/ |, Cstatic void McASPI2SConfigure(void)5 c% J {9 D" {, f/ ?3 u
{* T. k' O: E) T7 K3 |5 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; c/ c. n- w x8 V% AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 c) q0 i' f+ ^9 I. ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 d/ Q2 p. e, y- p a8 LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 u: ^. G9 K5 N- P& p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ o4 `: m. Z4 S) T) [MCASP_RX_MODE_DMA);1 i! F! z$ z. u q1 r: b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ v i; L: M; `- L3 ^8 |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' S, N* M I3 ^! @- g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) Y+ E" M7 x; Y. DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# D8 W9 @, b3 D# M1 Q( v0 WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 z1 e# ~8 X4 U. QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ Y y; t# l& S6 w3 o$ qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 N1 Z3 T. A! iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 H( x5 W. W! F2 u' i5 m2 h: @1 }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# T8 C; M) Y Z; H- n
0x00, 0xFF); /* configure the clock for transmitter */
2 P$ r6 @4 P& \6 `: aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 E3 ?. a! }& t/ F% @# O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - L Z& l. o9 w, q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 T' V9 ^+ i" a& w
0x00, 0xFF);" Z- S+ B" V# ~
* X/ l" L1 T& i8 G( Y
/* Enable synchronization of RX and TX sections */ / m$ i$ F6 e: Q7 O: c0 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: @: c: f8 Q8 c6 }5 l( k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 _( g J9 i& dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- u9 Q5 U f: X; i$ Q- w4 u
** Set the serializers, Currently only one serializer is set as
/ K4 t+ W2 A! p) T9 O$ s3 F** transmitter and one serializer as receiver.& X9 K* P+ a% L5 W
*/
' o: A( K6 C4 O/ L/ \5 h1 m) Y; sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: P; D9 t0 M3 v% HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 O* ?5 Z& _( d s) k** Configure the McASP pins
5 i1 I3 q/ S8 P7 Y$ \ G9 `** Input - Frame Sync, Clock and Serializer Rx
1 @( E) @/ C3 }/ D. [** Output - Serializer Tx is connected to the input of the codec
, ~! P- C5 r) J, x! A0 Z3 x*/
& l- {, |# F, d3 b. YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 Y, a( R; r/ F- d1 L& p2 t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- u: F. _' B- i" G5 ?3 L+ JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. T8 o0 Q+ q7 u/ Y4 F5 p| MCASP_PIN_ACLKX
; x( L* L+ ~6 J1 P ^# m| MCASP_PIN_AHCLKX
q6 L) T: @! r# M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 k& }( _6 K! A6 m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : f% w p- R( i' @: [9 f
| MCASP_TX_CLKFAIL / q8 f {7 ^% N
| MCASP_TX_SYNCERROR
$ c7 S" y2 k2 F. Y A H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! w( a" S0 [3 ?% I' G+ \$ @0 I| MCASP_RX_CLKFAIL+ M- Y k& l/ s7 S5 z
| MCASP_RX_SYNCERROR
3 V1 r T3 s( @" V# Z# o| MCASP_RX_OVERRUN);& n7 V1 s* t& z: K9 u
} static void I2SDataTxRxActivate(void)
: ?9 C) W" n" B6 h0 |4 f4 W( N{
! U+ }( }& K+ M( U/* Start the clocks */
8 C r9 k5 Q% @5 C$ tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) @1 K" h% h. q# U7 h6 v4 _, PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 N! v( T( [4 B1 w Q' s0 M' t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* K7 @! U0 U0 p+ n) |$ tEDMA3_TRIG_MODE_EVENT);" x$ f# \! N. H8 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; P. U" n) a( W2 Q7 Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 m8 m$ E" h! `( G+ wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 Q e6 X$ H. L% P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 |4 ~9 M. i) g I+ bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 ^5 ]8 h0 V- X9 I" R& L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 T1 b9 h3 T7 n4 a5 ]) b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. E, Y! `4 t' t2 ]! Y} $ _: j o8 k. p+ p! n2 {) D. S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . b; ?6 F F' ~' ~
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