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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 f' x4 w# D, V& F- T! |1 e
input mcasp_ahclkx, @- K4 r3 ?; X H
input mcasp_aclkx,/ t, B- l- B& c0 m& @
input axr0,
! p5 Y: ~, V# H
' K4 w. N' C; u+ m; O) zoutput mcasp_afsr,
, z3 W4 C9 Z& n1 ~output mcasp_ahclkr,
( R: N9 L4 ~8 R$ n0 Voutput mcasp_aclkr,/ K, T1 ]8 o$ K0 v+ `* v. M
output axr1,% M( e( G1 \; s' e/ c8 A
assign mcasp_afsr = mcasp_afsx;
: Z! l1 s. |! p, h. k# Massign mcasp_aclkr = mcasp_aclkx;. U# ?/ S* a% O h* ~$ _9 D: \2 f
assign mcasp_ahclkr = mcasp_ahclkx;- h3 g8 l& U/ i
assign axr1 = axr0; 0 U* V" F( w; a* K& `9 O
! D" l: C. w2 X, S$ h9 b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, a" F1 z+ a2 y( e% J. ustatic void McASPI2SConfigure(void)
) p9 o0 Y' _, E2 M4 O: m{
' L- x3 b" {, E6 j1 f4 t( FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% B, {+ w% W; `+ G+ o6 R0 X/ \3 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# Y1 G, r! `9 _, d! ]4 w; b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 D4 P" X! G; s7 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) @5 l; A4 c4 r4 O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: @, C* \3 r3 V! l9 x
MCASP_RX_MODE_DMA);: }( q1 }; W1 X9 P5 u1 w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 ~& k" Q! K8 H$ {/ y- l d; Z+ [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, e7 R5 s4 O9 F9 u! r+ m. [1 A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + C9 C7 q8 e& p7 G8 E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( L; A# l O( ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ W: g1 g$ F9 p# i) \+ s5 h5 q" ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" V" V7 T3 r# W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% ?8 B% y k3 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 a: V2 V& X/ R$ [1 R" B( bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( x7 X0 Q: ^+ W1 V, F/ x a4 u' c0x00, 0xFF); /* configure the clock for transmitter *// r1 F% P6 N6 D7 @0 e& W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: D8 C* Q, ^6 P; m- y; k4 T; [; Y4 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: b% U, D0 g8 P D. R) ~0 zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 o. Z# [: q; r0x00, 0xFF);
- P9 k/ X1 e# I1 U& ?. e" n% c- K7 r
/* Enable synchronization of RX and TX sections */
7 x; n+ J1 V5 F# W( }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 K( U/ G" I! Q0 H! y3 y5 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); j. b; F# _( ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, p" u n* N) D7 T# Y8 P
** Set the serializers, Currently only one serializer is set as! {" a0 {9 J/ }
** transmitter and one serializer as receiver. A& t9 a1 ?* q. p0 j. S8 j
*/
z4 y! q) x/ J* ^$ U8 YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! k* [0 x. a& ^2 E! C/ [: }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ c2 M6 o4 G8 C
** Configure the McASP pins
+ R5 T! V+ p% ^& F** Input - Frame Sync, Clock and Serializer Rx
0 F0 E4 H" Q. _% J3 D& g** Output - Serializer Tx is connected to the input of the codec
- I6 T3 ]6 H' l2 b/ h- A6 Z*/: k4 a( a) P- h* |, e h3 W2 E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% q- y# G& S9 D6 b8 b- M! T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: h( {' @2 z" C& u0 uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 Z0 P9 _# q4 U5 B& r$ X; G& C4 Y. \
| MCASP_PIN_ACLKX
0 l! E* o7 M5 {0 D| MCASP_PIN_AHCLKX0 J8 }7 K# {7 v7 R k3 G6 D1 @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 [3 f& {! f9 [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 F6 @. Q2 L5 p! c0 h0 W
| MCASP_TX_CLKFAIL + w( Y: y W n$ ~( O, I b( O& @
| MCASP_TX_SYNCERROR2 @0 Q( _, [7 x) E: ~9 Y. |( \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - }9 d0 @& Y8 e, j1 p; A
| MCASP_RX_CLKFAIL! i9 G( e! K H3 t/ T7 q: H
| MCASP_RX_SYNCERROR
& z u7 ~5 m7 ]5 [' U& u3 [% N| MCASP_RX_OVERRUN);- b; h, a: [' l6 B4 {
} static void I2SDataTxRxActivate(void)9 a0 H* `7 D" a8 { M9 P
{
. F8 L( \- S( }/* Start the clocks */1 x. w k! b& _4 C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 Z( f9 g& ?- z" @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 Y9 p' ]- n2 U; }! M: B; i4 w3 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* s6 T, j# W; X- u
EDMA3_TRIG_MODE_EVENT);
% |0 `. ?. W5 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, B. u$ L* k5 K, E' q$ h: [/ A* R0 O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- j2 ?, B; X7 t: ?4 C6 B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 B7 |- H3 v D9 oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" j, k0 `/ q8 I8 M# p- [" g7 W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* }4 _/ M0 l. f5 }$ J2 Q/ ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 d( E p7 j0 ?% V/ m% H8 D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" W/ y& W& n" W( C$ p: q/ s7 U
}
# V* g, c3 r% _$ t9 f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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