|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: @6 x9 T/ F2 p* v$ q" Kinput mcasp_ahclkx,
0 y% O M% B/ S4 Winput mcasp_aclkx,+ o* [2 ?; \3 F* z; U( j1 l
input axr0,
5 O$ G4 m7 f0 C/ d" ?1 H Y, M7 u. }* ^
output mcasp_afsr, P F1 v2 }0 d. C6 S% s& i
output mcasp_ahclkr,
3 C8 E( h: q' E2 houtput mcasp_aclkr,
* N" V# Z+ }- `, K5 Q# qoutput axr1,6 g4 D% t7 ~7 L) U2 c$ `5 w8 _
assign mcasp_afsr = mcasp_afsx;
, X! [5 x. y5 Y: massign mcasp_aclkr = mcasp_aclkx;1 p S6 _, i6 c- K
assign mcasp_ahclkr = mcasp_ahclkx;
# I# `, u- ]8 {/ ~$ M+ Uassign axr1 = axr0; 9 q- Q. M5 e; n
" o6 ]2 s9 \) O( d! \* d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( T6 a% r. _* r5 n, \- t
static void McASPI2SConfigure(void)+ a7 W- s- s2 z+ Q7 l
{# j3 [! N2 p {- X C) ]. {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; `, T9 X( h; V& x# a# OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 b. H" O6 O- p1 [+ pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; L6 U7 u" g& U+ N% RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 q! T) e, q- P4 a3 h2 m0 O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ P0 j0 A8 a( ?9 w4 r6 A' YMCASP_RX_MODE_DMA);
/ q3 [" @# b1 N; o/ eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ W& {/ X4 J3 d$ X. E; g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" o! Q5 O- ]; N5 Y! l; _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * d7 d+ j6 ^: c$ H# |: T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 |6 D7 W) s* j+ JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . x1 E9 c4 Y% Z2 ~+ O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% x+ @2 N* Z6 o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' u% d9 p$ r4 b/ I6 z4 N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) u% a% d# u3 ^7 F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
}9 I2 Z3 \$ Q0x00, 0xFF); /* configure the clock for transmitter */4 \- Z" B5 n" x4 _7 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) B3 }1 X" A) ^6 x7 z2 E% R: @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
N1 n- V V8 P; j) p* _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- K5 H7 s4 [7 |) f2 K0x00, 0xFF);
2 B5 Z5 l! p$ ]9 u
% Y6 c# f( B g/ P# n. }4 C/* Enable synchronization of RX and TX sections */
* |' H) P1 A8 y, g i+ SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 e" `) E0 a7 ]( ?$ d/ a8 vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 }& p6 ?8 [1 T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* n) E! d2 |; E/ d! w
** Set the serializers, Currently only one serializer is set as# [; a3 v7 a# B, O
** transmitter and one serializer as receiver.
7 V% k4 H" m$ G*/- c4 i j) j: j9 L. f; b) I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
O& [( y& ?: x* ^. Y2 rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. b" D8 f+ P7 Q/ M. s+ z
** Configure the McASP pins ' Z7 |5 j, l; O1 V, v( b" g# _( ^
** Input - Frame Sync, Clock and Serializer Rx
9 Z5 W4 ], Y5 s& L& S" z' T/ |** Output - Serializer Tx is connected to the input of the codec
- H) h. n% L6 h* V# `; O5 p*/* R! ]$ V$ z- i9 p( H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 w, T& O' D" d, tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 o) ?9 F# v p6 [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 a- ?- F$ }; m1 ~9 m| MCASP_PIN_ACLKX
/ w7 m5 l7 K) N" p; C| MCASP_PIN_AHCLKX- X. M+ U( r# l) g; n) b$ `* d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 G4 R- |- W9 | R. {0 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 M# `7 d" t* U& U: m| MCASP_TX_CLKFAIL ! R. R( Q" ~5 E' K
| MCASP_TX_SYNCERROR8 q2 v) e6 \! R# |* ^+ T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + C% ~6 |9 E! Z* a) H) W- {" S1 j
| MCASP_RX_CLKFAIL
5 {" |/ s* {/ w* _! W* x5 O| MCASP_RX_SYNCERROR ; A$ b& s' O* _! i- j4 i1 P! E
| MCASP_RX_OVERRUN);
. R& T7 c0 T) G! M, j- [' O3 c, A2 e} static void I2SDataTxRxActivate(void); U* W1 b) W! Y7 e1 m1 Z! A9 D
{
: q7 i/ Q3 `" Y* K0 z& K/* Start the clocks */7 P3 h( c% T, @: z9 z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 f$ ^" j, o' }9 ]" Q6 LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' ?1 u" P& i2 p+ {9 G9 x7 c2 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ N. D$ x/ E& M% j9 z4 F* @
EDMA3_TRIG_MODE_EVENT);( G4 B6 u7 c2 p9 f ]% t4 o' B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - Q; [# B9 A! q/ ?& I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 Q, R" |+ p: J1 }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 j, e9 [9 K+ s" D! j; c6 N9 K2 a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! z& R* h3 B! p9 |$ Z0 G# D' J8 l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: v, y3 E: y6 R* G; O/ O G; J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; J$ ]" t! L0 `9 p, V! H" QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; ?) F) i) ^5 P6 ~1 q4 i& y
} 2 g* F. F. P& i- E' ?0 w4 f$ T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
5 y+ ~" W# {9 D" e/ v9 l4 J |