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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 ^! I7 l7 S. b1 ^
input mcasp_ahclkx,/ h7 m% X$ ^3 v* ?
input mcasp_aclkx,/ d+ z: ^; J+ w+ {/ d4 l
input axr0,
3 M" o+ y1 X5 o+ L1 ~9 O$ d
! v* y/ B! v% g5 youtput mcasp_afsr,
8 ^$ ~5 {3 Z3 U: E8 c. voutput mcasp_ahclkr,
& K) G: o. H3 x6 {( Moutput mcasp_aclkr,
) `1 H% {5 L/ `7 D- y: a, _output axr1,3 W/ O0 v/ e% M9 b
assign mcasp_afsr = mcasp_afsx;
- j- u. e L% Z/ wassign mcasp_aclkr = mcasp_aclkx;
4 ?) a) I% k z+ Y1 i+ g" `. bassign mcasp_ahclkr = mcasp_ahclkx;
( {, A7 L) v9 S( F- J& o% yassign axr1 = axr0; 6 U4 L6 p1 V) d. L2 M4 D: L) m
# [" Z0 J* W3 O/ l* d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 |! K6 y$ r0 q. W. `# O* _+ Pstatic void McASPI2SConfigure(void)
. m6 @6 V! H! n0 Q. d# M{+ d0 \, q8 V3 I; i$ m: L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 O ]9 p. J0 _4 g' o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' q4 S. ~, m6 ? ]3 p1 d3 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* [( X6 x& S6 z @0 WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) A0 f1 c! T2 p5 _& B2 h+ b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, U- x7 K. I Z$ P4 i
MCASP_RX_MODE_DMA);
4 S; z" F. L/ C4 a3 e! g7 ~: iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& W1 g5 z+ Z8 S, _3 p( cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ c0 M! i5 h* {9 w+ ~& q) j! X1 O7 m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 s) O& L% n) G5 q) ?; m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. p7 \& w1 e- M8 e K% y- XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 I! o, Q& s1 u0 E; |* \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. c0 t; h, i4 `% i2 EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" |& x/ e3 Y* _' LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * x4 Z B8 n: B$ v3 u. p9 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," S1 n3 m+ j, ~) b8 a* }
0x00, 0xFF); /* configure the clock for transmitter */- R2 v( S3 K3 C" H5 d; X" Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 O6 |. a, P0 t* |: n- x( {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 e2 j' \, G7 [, gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: w; u* c8 T. c9 @. N( N4 ~, E) W: g0x00, 0xFF);
& a; C+ c/ ]6 u0 p f# ?& u9 X$ a
" f4 f( f* C0 S/* Enable synchronization of RX and TX sections */ ) A3 X- B* A D7 D6 |5 D) L/ F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 u1 \2 u& x. K: E' C( u7 S* X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ t" F0 f4 v) CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ Q: X; `/ W0 J7 `. O** Set the serializers, Currently only one serializer is set as
M6 X6 J0 M2 b# P/ Z** transmitter and one serializer as receiver.
$ h# c0 t) @3 W4 H. `# s*/9 d6 l/ T/ J+ y H. K4 |: Y% r7 p9 R+ l2 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 g: q8 y* B$ w+ N6 ?, AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! c( A/ v% p w+ h% e2 `** Configure the McASP pins
" f) K1 d' V# f, B5 }1 e** Input - Frame Sync, Clock and Serializer Rx
6 r9 n: U. h+ z- `3 K. s" w** Output - Serializer Tx is connected to the input of the codec
( C% r9 ~6 d# n7 `* g9 y3 ]4 ^*/ ~3 i7 ~; O. m- d! _# i+ p4 q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' E" Y: X5 a+ d) V5 L' p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ A$ B2 l4 j3 w6 j2 c) l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, }: C$ |3 ?- h$ x! C; Y/ r
| MCASP_PIN_ACLKX" M/ m5 w# z2 s6 ]' l+ Q2 n# o
| MCASP_PIN_AHCLKX
0 h: X2 m3 x+ A; L. E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 F7 ]1 i: i- r8 ~0 C% U( M1 r/ ^5 {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR C" o$ |5 v6 _& a! q2 c" W% s3 y
| MCASP_TX_CLKFAIL ! G# ^3 `# Q2 W: l
| MCASP_TX_SYNCERROR
$ D. n! Y6 N1 c- x$ k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 {# g9 t5 t* Y3 u ?| MCASP_RX_CLKFAIL* t+ b. @+ N$ ?" B# e
| MCASP_RX_SYNCERROR + [# z6 ~3 i D% D3 ?5 e
| MCASP_RX_OVERRUN);% |; c+ w# _ S6 M0 m& x
} static void I2SDataTxRxActivate(void)5 V% f. U& ]; R( T0 _
{
" H9 p/ d3 ?7 t+ d; x# N4 c/* Start the clocks */9 }: d. R+ q* z' I: r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) C0 Z( q; d9 X3 }. J; f+ h3 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 B% l" C) f. d5 N- I- Q2 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 p7 R$ \& S, _7 w8 f: q& tEDMA3_TRIG_MODE_EVENT);' M: T. ?( U. i( D. L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. x }/ g! t( u( u6 TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 S. |! q+ Z9 V k, {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 b$ T; j8 }- r& ~0 a9 Y# @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" y+ r+ Y8 b+ m% ^5 ]! M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. l$ L6 ~: \+ E4 e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ @/ c7 U& K! g! J, \+ uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ I5 K6 p) r- @5 d
}
$ ]& U( C8 j4 z( Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 W3 N" j' z5 w; P
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