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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! C2 T$ Y! i' d7 j0 Kinput mcasp_ahclkx,$ s- M! T. o5 a5 W) e$ u+ H
input mcasp_aclkx,
; ~+ f' r' e( v; ~) [$ `input axr0,( k* d( P1 l& W5 t1 ?- l8 q
" U" ]" o" i; x: W- @* {9 E
output mcasp_afsr,& K, V# ]3 X9 Z* E
output mcasp_ahclkr,7 B. }6 n* E/ l
output mcasp_aclkr,, A- p6 N0 q# O, \
output axr1,, i# D: t$ {+ t
assign mcasp_afsr = mcasp_afsx;% l2 f! ?0 m: O7 n I" `
assign mcasp_aclkr = mcasp_aclkx;
$ P7 [7 ?# ~/ J. g3 T- Gassign mcasp_ahclkr = mcasp_ahclkx;8 p& P; c& `! h# A* P6 s
assign axr1 = axr0; ! j/ P+ i! v5 t, |4 ?% f' x
+ X5 S1 K3 I8 V2 N1 t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( ]" Z) ^. x# D5 y: N
static void McASPI2SConfigure(void); z7 R1 F, p6 X8 T% t% ~: d# I$ Q
{
$ d# o+ I: c2 W7 X; pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( F0 y' [) M7 E" z& r; l* Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 n1 P5 ^, x4 TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 k1 A8 W" C$ R9 rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 I: Z4 u& [3 n4 ?3 }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! V0 \1 T6 t) F2 |8 r' G
MCASP_RX_MODE_DMA);% @: r/ q- m; A+ J, a5 w. V8 s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 ~! }/ G- ^: h8 P, TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& t+ D* C7 ^' R# L7 F ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 D5 X J& }& H8 E& h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 ^! Z) ~8 C) i5 [6 D8 w! N5 O1 B! w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , N3 u0 y% |) N$ W) v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 \* |% K0 [! w# r. aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# H: |+ G$ `7 [- T4 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . f/ l; H7 P/ `& D/ P1 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 s/ Y( G* {' b0x00, 0xFF); /* configure the clock for transmitter */
" w5 a1 p- D% g! E5 w( LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 B- b1 n, ?8 A, [1 [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ X+ S$ A7 [! |) m/ E; v- T: fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* Q2 Y; S. Q: e9 ^# M
0x00, 0xFF);7 g. A2 R8 _ j: ^( s% ? W8 `$ [
* J g8 I" g8 k+ ?) B0 S4 i. o, C/* Enable synchronization of RX and TX sections */
: S# _% b5 h- M! s3 I9 SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ [: Y% U$ D: q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; k5 ?7 W3 y: T5 d* KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 h9 y: _4 Q& ?3 i. X! y** Set the serializers, Currently only one serializer is set as
' r$ h% K1 j+ o$ v** transmitter and one serializer as receiver.# Y/ S4 m0 C+ l0 u9 ~
*/7 y G2 D: J; S* D) ?# T) q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ e" I1 t2 O8 y* v* E8 v- v# g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; N' \0 q% v: ^
** Configure the McASP pins
$ L$ L0 G1 T5 `* R4 F** Input - Frame Sync, Clock and Serializer Rx+ V& L% G Y! B) \7 D
** Output - Serializer Tx is connected to the input of the codec . X' v) M7 l0 M% ?/ v9 q
*/# }5 W0 G. R* ~# u% O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 }9 K w; d4 {* M' z* y) t. X4 l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! P* b: s$ S0 W- k* O$ rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
r$ K8 l6 W+ A) T- b( T| MCASP_PIN_ACLKX6 `* k7 `5 O6 N: G1 B$ X0 L
| MCASP_PIN_AHCLKX# B7 [3 v$ V* L& v; O+ _3 L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ v- W" o0 o0 Q$ h+ IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* e# V* k/ H$ \2 N: Z# O6 Z| MCASP_TX_CLKFAIL ( c: c1 F6 d1 M, j! A
| MCASP_TX_SYNCERROR) |8 u6 ?% _! E/ Q9 B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + K. [7 }- m c7 ~, z, N+ F: H* F
| MCASP_RX_CLKFAIL
8 D/ Y0 J! F! v: g# [| MCASP_RX_SYNCERROR & {; H; I4 @4 Z9 ^9 j8 G
| MCASP_RX_OVERRUN);
( U) h5 w0 j9 \/ f$ V* m5 R0 j6 \} static void I2SDataTxRxActivate(void)
! Z& { ~4 ^8 i3 B* N) i{5 l2 J! e' ?8 O
/* Start the clocks */
$ v% A7 i' A, f- ~7 T: PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 H P" z+ b @4 k" j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ F" a5 k1 Y- S7 N; `5 I1 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) i, A& M# B, n2 m! Z
EDMA3_TRIG_MODE_EVENT);& {; J5 q3 h2 C8 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 G& _* {; n8 e6 L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// ^8 c) i5 `2 W# b( s8 q- C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. i2 O7 v3 K( M5 y& K3 T8 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 X$ T. g! }, q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% ^5 I1 X" Q% s) G5 s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 ? ^" w+ ]* k+ t% ]8 u) t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ f7 G4 a2 e2 h% O7 S9 i# N2 r( i}
V/ N$ r( ~8 e3 j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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