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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
j* |% U6 q3 Vinput mcasp_ahclkx,
- O! _8 ^; K5 n8 a$ u8 y) S+ D% [* dinput mcasp_aclkx,! B% \# L1 ?, ^+ t$ \
input axr0,
, w# x0 o6 i) z6 m2 ^9 [3 m, l4 w+ |5 Q( u8 h
output mcasp_afsr,
4 S& v# u% I- y6 qoutput mcasp_ahclkr,
) Y" X% V. P/ i! C3 b. v4 Q9 Woutput mcasp_aclkr,
% R3 y k, C5 l" [7 s7 Xoutput axr1,
4 J( G/ Q: f5 V. p& c% E0 A assign mcasp_afsr = mcasp_afsx;
: ?0 K5 Y# G/ Y5 U7 A( p A( Hassign mcasp_aclkr = mcasp_aclkx;
4 {! t2 M V7 y: K, Vassign mcasp_ahclkr = mcasp_ahclkx;
! a4 G/ W9 [! M6 s$ yassign axr1 = axr0;
+ l: J# C- Q5 G1 O, O7 B! e2 ` U7 }; b+ Y; n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ G9 ? S5 }" h2 [8 F9 @: C8 ?
static void McASPI2SConfigure(void)7 p% R6 ~7 r1 K0 ?
{4 X9 i) ?- I i9 Z( B# @: R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( {8 Z4 @0 _/ O5 P# e7 e, hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* ? j3 {0 C( a* @, ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ @9 u% u: x+ r3 R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& u/ x; k! k4 Y, m0 GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& v) B1 ^4 p7 a* IMCASP_RX_MODE_DMA);4 D6 C! L% L( {% X" S9 y- m) T% _& C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- ?* F5 z. \/ u' r- RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" C4 M( o9 P/ i' B- h rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- T+ _9 s3 O$ m% ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( s8 R! x! j2 C, c9 ]: X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ L; L' h( n) D! m3 P7 PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; E# V4 Y5 r1 r9 S) D2 q9 g$ L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' j: n1 |8 w6 \' i7 g* a# j2 ^. n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - t0 T; ~1 m a; B1 o) e$ r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 V5 O4 o& V7 Y# c4 @& y
0x00, 0xFF); /* configure the clock for transmitter */( T! c, P0 m% O0 x( J! o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 |8 `/ N/ S: C% u( IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 y+ O8 r% Q# \4 k% C. Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( w# v1 [! C3 \) t0x00, 0xFF);
& s( F4 C' v3 \, G- P9 }0 S: |& G7 D6 R% f: i# o, C: T% a
/* Enable synchronization of RX and TX sections */ : N' Y5 X2 J% e& E; u; d" E3 d! v" j; U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; D; h; X+ a5 S% ^1 oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 \2 X* q- X, u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& p- i7 h( ?5 A- d8 L
** Set the serializers, Currently only one serializer is set as
/ S. f% X5 R. q% t" o W# ?** transmitter and one serializer as receiver.1 e: I8 Z& O1 U b# Q
*/
! j- K1 z6 z' i9 B* h( @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 M4 V; v/ q. u& c, i6 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! ~/ q+ p3 N3 r
** Configure the McASP pins
* U2 G4 D- k3 c; t9 G7 _3 X( f** Input - Frame Sync, Clock and Serializer Rx
2 ?6 \ ~# u2 N0 }** Output - Serializer Tx is connected to the input of the codec
$ b8 [) |5 |# ]" I1 H*/
+ J- q1 P$ j4 C; p# pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 \3 h1 C) h3 ]1 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( U1 z' F J- d2 r4 q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ ^4 I+ C' ]2 Y, ]' M
| MCASP_PIN_ACLKX
8 P, F/ L; Q5 o/ D9 ^; T, X9 y" o| MCASP_PIN_AHCLKX( y6 E( M. z+ d- O( b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* P' R! b4 M/ ]8 W5 a1 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* @, S3 t, _- S' L; {, \$ [* O) _. m# ?| MCASP_TX_CLKFAIL 8 J/ j! Y7 P, g# w( z3 T
| MCASP_TX_SYNCERROR
8 m/ m5 \& c; z5 h i/ [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , U2 X0 j! F* z8 B9 V
| MCASP_RX_CLKFAIL
( {' F- w% B7 I2 y, b" H f K. @9 Q| MCASP_RX_SYNCERROR ' ~! p+ n {8 y9 j
| MCASP_RX_OVERRUN);; i7 f$ }5 p: f1 u" R+ l. p0 |- @9 X
} static void I2SDataTxRxActivate(void)
+ [% I: E0 F/ S, C3 i+ z- p- K{
- J" j, W$ p$ i( U E) O/* Start the clocks */
* b8 x2 M/ y& V9 a) WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 W: d9 Q8 Z' `1 U: ?8 [% i0 L3 sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 e3 C3 g# r9 t1 [; [, Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* l, o- ]- ^# ~8 u+ a
EDMA3_TRIG_MODE_EVENT);
, U1 A' V! @: m) d, tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 ^8 ^9 b/ x4 c9 t1 ?) ^0 }5 J+ ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: Q) A' ~& x' Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- F9 {+ d* F8 ^" V7 T$ ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% d' n( p& Y. E. u5 n1 {; Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# A {7 K- ^. y1 j) q0 N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ y" ~" d" J1 p# }) v) x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; Y. F3 O5 { p/ x7 y* w}
& o' F W# E+ k* S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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