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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& y8 E: h# d% R2 K2 e1 R9 v+ k; _
input mcasp_ahclkx,
- I" r2 T& W) B) l' finput mcasp_aclkx,. O& D2 @. s5 z
input axr0,5 O5 u4 \6 g- k- Q. B0 h; ]$ g8 E, z
& C7 C o0 a1 S Youtput mcasp_afsr,! ^- N* X- N5 A
output mcasp_ahclkr,
$ H: q. I8 n. ] ?# M1 youtput mcasp_aclkr,
5 d9 C0 }6 {. F' k3 K( I5 S% xoutput axr1,
$ U% b! [! T1 l' u. [5 B assign mcasp_afsr = mcasp_afsx;, L' z. h* T. W' M+ y" R; `, c
assign mcasp_aclkr = mcasp_aclkx;* C t4 A9 w, ]) _* _) S! D
assign mcasp_ahclkr = mcasp_ahclkx;6 }7 |% S" t; z# p, U+ }2 u8 n
assign axr1 = axr0;
8 ?- J" q. o9 A& T" ^
/ Z* [/ G) V, N0 Q+ f( }2 ]+ n" [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! S4 x$ y3 d7 P& N2 {; |- {9 Mstatic void McASPI2SConfigure(void)
h: u) Q) Z$ v{: r/ ]5 z- J* ^ U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* \$ b) |" b; n( @9 j9 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 V$ u& |8 f/ k- b: @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 J8 o& W3 w/ Q$ eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! g7 \7 p4 z1 ^9 J( V$ K: O3 R: q: xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 _/ h3 @6 [3 P' W2 ?) I7 \- kMCASP_RX_MODE_DMA);
: U$ A. ?; u0 g# P6 Y! e. wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 t4 @1 D+ A1 U2 S; x v% h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 q8 H; ~) h/ W |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 s2 o, S' w* T' b3 A1 i8 _4 EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* w/ K" H4 j7 g; l8 Z3 o/ g! M& o7 s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 ]* D$ H+ u9 |3 ?/ X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, A, Y' C, P! j- gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& o) Y. R" Y( ~6 c3 p, r; ^7 x# P, O+ z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * v7 @. `: [8 S& Z1 c; G" L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 G" k/ K2 Y! \5 e+ J; p% ]" I$ E0x00, 0xFF); /* configure the clock for transmitter */" j9 V1 w( A a" {4 w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' U' h) ^& ]" p2 m' l5 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' R) f$ K ]5 ?0 U; M7 m/ tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 K8 d& y; x9 I8 H
0x00, 0xFF);& r- A+ {6 V, Z: s- u! M
9 Z1 ?3 O: ]9 m9 n# \
/* Enable synchronization of RX and TX sections */ , ?0 b. C* C6 i6 F+ C- @: l- V% s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- u6 e5 B3 Z% Q- [2 P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ z+ Y' B( X4 e, @& o0 e( G, OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 }: E. o+ c" G: @
** Set the serializers, Currently only one serializer is set as
7 W& s; t+ E7 w3 D. c) u" s** transmitter and one serializer as receiver.
) J8 L/ }" |- V5 E*/8 O$ b) V6 {* e! N" o9 ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ l8 B- ]+ z) c* k! z# U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ @: I0 P# `( R/ h# v' i+ A& i** Configure the McASP pins
) S4 f6 N0 L) Y! l+ F** Input - Frame Sync, Clock and Serializer Rx# e- F5 b0 ~: R7 |8 r
** Output - Serializer Tx is connected to the input of the codec
; r) |% q6 l; `, ^( V7 m*/0 H$ `2 a5 S w) n- g# t! h& T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 A$ ~9 H' Z$ ~) H1 o7 E1 U. ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! X) x/ F6 l& m. y8 ]' c# Q' a6 tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 _" x: }. ]0 \3 l# C1 B| MCASP_PIN_ACLKX
1 d+ q( a. d# I0 z2 B4 O. D+ A- P| MCASP_PIN_AHCLKX
# y9 F9 k: R) e6 t. W1 D0 O. Y2 P% e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 j7 W% ^7 ?. [4 _3 {1 ]0 Y' T" q) o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & b6 `2 s% e7 ]8 D; v5 P R: C" l
| MCASP_TX_CLKFAIL , `; Q4 \. n E$ D; |
| MCASP_TX_SYNCERROR! d2 C, I% p, F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 `5 q9 _3 l1 I) u8 {2 S
| MCASP_RX_CLKFAIL
3 M/ P. Q/ p/ _) ~| MCASP_RX_SYNCERROR
6 X% u, k' y& t| MCASP_RX_OVERRUN);
, `- n% K% m% `$ r, l& k' s9 a} static void I2SDataTxRxActivate(void)
/ J2 `3 m" o& T& M4 E4 l v{! A6 d8 r( |: u4 W0 P8 C
/* Start the clocks */. G& c" h. G4 i! j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& F( T x3 k8 B7 I8 v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 ^2 h3 E* d% T! g5 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& G) P3 Q+ U1 C' \) \) f
EDMA3_TRIG_MODE_EVENT);4 Z# i1 f% e, A' W/ Z, J6 V7 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ A& a# g% f* kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 w* d% j/ I( ~' Q+ D1 w- a5 E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; s* Z/ t+ L' l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' G+ Y1 t( {% A* T9 k- C4 o; ?" h. W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- O' u, c- h4 ~9 {8 X& h0 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 o' e' i2 J- n: `$ A1 t6 @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ M( ?) B. }) A: p
} 0 Z, X0 Q) X7 o0 {/ h" I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 G0 ~; x8 D, R$ X" R
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