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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 y; q9 K% c$ f$ G- M' u
input mcasp_ahclkx,3 Y! |2 U3 ]" b: N8 O
input mcasp_aclkx,
I3 o' O6 r; i9 J1 Z) c* Yinput axr0,# d0 _) x L: L9 I/ r: K4 G# g
& F+ g1 y4 A/ c; q& }" a+ p9 G
output mcasp_afsr,! s+ @ s3 v) |9 y
output mcasp_ahclkr,6 w2 k4 w1 t7 k6 M
output mcasp_aclkr,7 O, V9 { t' c4 N4 O' z
output axr1,( X( S$ N; w' k j! A9 |) n
assign mcasp_afsr = mcasp_afsx;+ _ e6 N) E$ Y$ r! Z$ E
assign mcasp_aclkr = mcasp_aclkx;
7 S# C6 Z4 \6 ?assign mcasp_ahclkr = mcasp_ahclkx;0 @8 e1 L; o' h5 S u2 _
assign axr1 = axr0;
$ S4 J0 g5 ]2 a
/ a: L3 { H3 |6 @' R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , W3 n# N; M3 @! B2 E9 s
static void McASPI2SConfigure(void)3 X( o6 w" G& p9 |
{
9 P7 x ~" W+ N9 iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; ?+ |& [ |& @7 H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' q# ~- T% {& b6 ^& c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! J) P8 w2 @" [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, ~ Z( b: c* j" P9 {& W4 x# J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 l' e( R6 j: \' g# O" Y
MCASP_RX_MODE_DMA);
$ K# X |3 X1 ]; f; z, NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 a! i6 ~, l/ ?3 C& H% f; v% PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 Y/ H1 d2 I u* X- S3 OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" c' H" s6 { }; pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ u& u7 H" w% @& ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + U+ B! L+ d7 L' H4 P$ D) M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( M: Z3 @/ x, ]1 MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& Z- ]3 k; d7 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + N& K/ |! U8 S" J) W# F* {- y' V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( v4 B6 O: F5 x! k% v
0x00, 0xFF); /* configure the clock for transmitter */2 g% [( v# C6 F5 V U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); Q$ L4 V+ b, G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' `- L4 h. V1 \& S6 P7 X# eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 N' O# P/ R1 U5 s8 m7 n% w3 [: }0x00, 0xFF);. ~9 S. B- v5 z1 ^$ }( ^: P
' G0 g+ Z1 C( p d' i/* Enable synchronization of RX and TX sections */
5 @* m5 Z+ x! I1 O' cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 I( b5 H5 D2 e$ X3 k0 f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 J- M% t w* ~! a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. {% U* z' B4 n
** Set the serializers, Currently only one serializer is set as
/ G: F' A' L( W/ Y9 k** transmitter and one serializer as receiver.# r" T# } W, f
*/
- }& J/ {# L& Y4 o" ~3 s, nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 o' |0 N$ l8 L! g9 ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ x! Z: @6 r5 @0 u: n/ B# A6 S
** Configure the McASP pins ' e, X2 y f0 d8 _
** Input - Frame Sync, Clock and Serializer Rx
( k2 a6 U3 w; `, W6 U5 |/ R/ u! R** Output - Serializer Tx is connected to the input of the codec
* o0 ]6 w$ O& s2 r$ d) n*/
! J, l, F4 ]7 B( V1 \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 |: q7 I) ?9 v' O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 c5 s1 J9 i! [/ y( ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: x4 U5 @% T# N* p g" L. H: G2 W0 b| MCASP_PIN_ACLKX
! I" m( g/ ?8 o9 u7 P| MCASP_PIN_AHCLKX2 T! B B# J% T% @+ J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ K2 G# k1 ?" e+ F5 U+ G% K& }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 W: b( S7 g5 |+ [8 n3 E$ C% v3 R8 P* @| MCASP_TX_CLKFAIL
( z* q# |" a. G. s) ~, p9 E| MCASP_TX_SYNCERROR8 y+ h: e7 F9 }, O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR F/ W: _) n3 Y- y7 k1 Y
| MCASP_RX_CLKFAIL
# i" V" w' ^2 c| MCASP_RX_SYNCERROR
7 ^* B: \, I2 m5 y5 A% h3 O, c6 q( n% C| MCASP_RX_OVERRUN);5 }5 g2 ~( _/ c
} static void I2SDataTxRxActivate(void)4 K9 b1 M' T3 R! [
{3 u3 l; U% e) D- d$ q
/* Start the clocks */
8 _2 O. V- c* B8 O0 [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ q$ ?4 ]) n# o0 Y$ C2 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 _6 R3 K' U! u2 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 y- u/ F% `7 h: D/ I' S
EDMA3_TRIG_MODE_EVENT); o* ?) g0 J3 X# T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 m; F6 \( o# M% k& T k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* U; j/ V9 ?0 S2 rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. ~' B8 U7 @# X; @7 p4 _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 A9 T# ^) k! g& n0 M9 Z, c# v% R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ R- G, L6 n% |* ~" Y3 }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- ? k$ f: M& u$ WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 O, ? F' N4 L6 b o
}
9 g% H6 t( \4 y, S% A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 D# v/ n% c3 c" W' i7 f
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