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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( ~% ^6 _* L0 X- @+ f; c3 C& y( qinput mcasp_ahclkx,
% e G. e; w/ S$ {, `6 ~input mcasp_aclkx,2 p. s1 G+ D7 P7 L# r# v/ a! ^4 S
input axr0,
. q- V* Z9 j7 Q4 t6 i
/ e5 e, C3 q2 q. aoutput mcasp_afsr,4 K1 L# A; s& i0 s# [% r
output mcasp_ahclkr,3 _: Y' S8 q) z/ `7 n1 i0 q5 h
output mcasp_aclkr,
, O! a; r' ^: I2 X+ Eoutput axr1,
9 I& ]/ _3 l$ Z# Z9 A+ s assign mcasp_afsr = mcasp_afsx;$ t- y4 C; L* |& {. v
assign mcasp_aclkr = mcasp_aclkx;, b8 F& Z, k) l. P& w; V0 ?4 l
assign mcasp_ahclkr = mcasp_ahclkx;
$ h" h8 W5 p4 n/ T [9 t% b1 f$ }assign axr1 = axr0; ) G+ r5 N+ {1 I u
1 @1 N2 O; q5 I( I9 f% }4 `) h% `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ f3 K$ H. r* \9 E( K* C; m2 i3 [; zstatic void McASPI2SConfigure(void)
: Y" @3 `2 x6 B{
! r' @' P& W# `9 W- [2 _/ ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ v! _8 p" M: Y8 q3 y, E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 b; i* A+ c6 N9 @ r* K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 p, o* s2 V( u% W; A9 jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& } K2 M( b* W; B$ d% G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& _- k. i: R- F" n5 ^. i3 RMCASP_RX_MODE_DMA);
* `; J; A, s9 S1 v# r0 R) KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 [, [' t f8 J( b) ?' @! `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 R& L4 j8 |4 q7 F7 k+ p' [/ vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 H# m- `' ?8 q/ x4 xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* u5 n" N. ~- a3 z( w1 t6 |: v) G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% Z% @) ^, V& z4 N$ uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( P I8 }+ p2 a2 P* F7 l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 P: x/ B9 A1 @6 [2 _! @; F% `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
L) m; @6 I- yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) a h$ ^: z* `0 h3 w0x00, 0xFF); /* configure the clock for transmitter */
( j, @) b2 b* KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 I1 B6 i% i4 F, }/ v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 }4 X1 s! R6 b9 y( AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, h# P$ m( U$ u1 d$ s0x00, 0xFF);
% s3 t3 k8 a ]' C2 G* _3 N! v. A2 o2 N6 m+ i& A. X$ k7 Y) ?) {
/* Enable synchronization of RX and TX sections */ # ^( \. S5 O6 [2 N7 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* o+ x* ?; Y V7 Y" z+ i2 QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 ^8 I' G; [4 S6 u! Z! ^0 O1 M# }" HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
d1 @$ p3 R2 E% {2 K7 U0 h L& y** Set the serializers, Currently only one serializer is set as
d M) o1 @) ^1 s** transmitter and one serializer as receiver.) K4 [5 i. h' n1 q2 \; D
*/6 x* }( b& |+ V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; \6 \" V( ?# s$ KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- P8 t+ v4 r; m7 X
** Configure the McASP pins
I. d5 V/ }* V& K** Input - Frame Sync, Clock and Serializer Rx1 f5 u8 B# j( S
** Output - Serializer Tx is connected to the input of the codec
. q/ w, \1 w' G5 S2 W$ m*/
2 G# s. F: t; w# t/ F! eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% P! o4 ]5 T! hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! P" S' c1 M" Z! E9 c. R Z1 c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: j; X0 M* s8 K W8 w| MCASP_PIN_ACLKX- V( ]5 o& D6 m0 J" r" R
| MCASP_PIN_AHCLKX
: Z! Q6 W& U, b) T! v! z0 g( ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( \- Y& x" e" U* r' cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 M) P- t/ |+ a- J- f| MCASP_TX_CLKFAIL # v2 d, V \3 n
| MCASP_TX_SYNCERROR* \; Q8 p& e: \( Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# f) w: M/ a: N. d1 p) b| MCASP_RX_CLKFAIL
; I) _% B9 R T* ~* {$ U| MCASP_RX_SYNCERROR ! B' A& d# `4 v+ M7 n/ [9 D2 S
| MCASP_RX_OVERRUN);
) o5 a% t6 O) q} static void I2SDataTxRxActivate(void)
: U: h( v W5 W G3 b D{* T( v, G& `( J5 A1 M3 s" l6 O
/* Start the clocks */
* D/ {! i8 ~- tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); i! ?+ ~4 W% p+ B K% d: e4 g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
p) T8 x$ ?" N% V7 P. a3 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 y! n, V' W, Y: U
EDMA3_TRIG_MODE_EVENT);- W" l M0 G- A& Z; C6 i J" u( k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + _0 H1 s0 P6 @! t: D& J1 W3 k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, G% N" ] i. x6 ^9 n$ @; |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 h- A" \6 V# I5 M$ D# m1 G6 s9 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 s/ G8 k" ?( ~3 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 l0 I2 n' B. b+ \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 o) q3 u2 W. d- XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 H. C) K; d7 d% e& e
} 3 f/ ~8 A/ o3 J* f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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