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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: O9 f* r: D8 r- M& k8 S7 s
input mcasp_ahclkx,
' B; s1 X C+ U& linput mcasp_aclkx,
) m- o( F' L# [& Z6 y3 tinput axr0,8 S# y/ F0 ~- N( h
5 K: V5 i$ i7 e& t+ n, e
output mcasp_afsr,$ H4 ]/ L) |8 I$ g4 E
output mcasp_ahclkr,
' E( T6 f; O0 _- A8 ^& Qoutput mcasp_aclkr,
$ |8 P% `: N- Y$ r& g# ?* _8 Q1 Woutput axr1,- A+ ?& {1 }8 I% g2 @5 O9 Q
assign mcasp_afsr = mcasp_afsx;! z$ m2 O0 N% S
assign mcasp_aclkr = mcasp_aclkx;
2 R0 O' \. P6 {) Eassign mcasp_ahclkr = mcasp_ahclkx;; M1 [8 d( }6 W$ ^5 U1 X
assign axr1 = axr0; 2 b ^1 P; v. B( k0 ~7 `
9 s: l; a. P( ?5 a% ]) ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; ?" l3 E" k2 d" n/ Y8 b( }( Jstatic void McASPI2SConfigure(void)
% h& n* g5 B6 \; ~" G% l{
9 ?, {: O0 P2 w; hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% X1 X# M' F# l2 u- e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 ]/ V; q( V1 n; L+ d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ E7 q7 K Y: W$ Z/ Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 f# t5 w: s/ U3 [4 }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" h5 ~. |& m- R' ~MCASP_RX_MODE_DMA);
' x6 B1 X& o# f8 MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 \' Y; c1 @% o% y4 `3 e# T' Y2 nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ L, [- t. l5 t' G( j, k% L5 F' A; }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " U2 k& l* M) X( k0 {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 J& Q' g( p8 [5 i" Z" K" m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 B5 T$ V% D7 s1 v' N. m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. |' P! [$ C2 n4 B* z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 `1 `- d' Z) c5 s' mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & X" o" }/ `' j8 I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' r0 d$ \5 U( c; Y' a5 p& W$ {' `
0x00, 0xFF); /* configure the clock for transmitter */
! r/ |) F; ]0 q- a* p2 J. q+ I( lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 u, K& p% ?5 \/ s S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) I0 q1 H8 ]5 |* w: lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ D' u! t+ j8 s. J; Q
0x00, 0xFF);
- v& n& b. m! ?. J
% q2 n5 o. b( h' m; }- K. n$ {+ @/* Enable synchronization of RX and TX sections */
, |; B+ S6 g$ X: r7 pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, [$ I7 z F7 X$ ^) ^3 _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, r% K, w5 P a0 o8 W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' x! u& p2 L0 a$ g** Set the serializers, Currently only one serializer is set as6 T1 J$ Y% b. O0 S* w
** transmitter and one serializer as receiver.
* N) N8 m& i K; O*/- _* `0 t, n( b1 s4 _! _) z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 N4 F2 i* o: K( X0 `% R- ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) B6 X% r1 }4 z( W# x" {$ X/ f7 \** Configure the McASP pins 5 c1 S- M, q1 F( X
** Input - Frame Sync, Clock and Serializer Rx V0 G, V* G/ e+ z: `
** Output - Serializer Tx is connected to the input of the codec
7 J7 W6 J- [; d9 J& q3 l( f*/
) {; w, {3 {' j; Y9 F Y4 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 H. C8 r9 b8 h9 `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' q1 r; N# W0 u* J2 ?# {2 w! @* JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" r# ^1 P/ h! R. r| MCASP_PIN_ACLKX8 ?+ p5 L9 R6 F( z r2 b" u
| MCASP_PIN_AHCLKX
2 S( l( [3 _: Y. r- @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ k$ |8 R' Q( A9 {/ ?; k6 ^0 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) Y N: X; o& Z G1 A| MCASP_TX_CLKFAIL
4 X+ t; N# r Q7 c2 X. P1 `| MCASP_TX_SYNCERROR/ _* J" Z4 `* N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, E* F5 F2 g+ u) q, \( F! h' p# `| MCASP_RX_CLKFAIL
; D8 R$ L, K6 J, v1 n| MCASP_RX_SYNCERROR 1 C/ o+ D" t: Y# X% a
| MCASP_RX_OVERRUN);
3 b1 l+ I* Q8 n! U: l" @6 a} static void I2SDataTxRxActivate(void)
, a, r2 a# O' ]( E; r8 K{& p o5 a( Y% g/ w' i0 Z
/* Start the clocks */
3 f+ N4 U$ c$ c b; rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; i1 @7 [3 C" K4 U/ t/ ]6 B1 L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 ~) J# Q8 b, dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; U3 } ^& Q5 ]
EDMA3_TRIG_MODE_EVENT);
4 T; O3 \' w+ v+ u! _) [4 {+ hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 h3 \1 k, n$ J) X8 R% R. C7 h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 l. Z% `6 K1 B5 ~- ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ n1 A. b) Q% ?! T1 P XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, P" ?2 I% z3 W$ {4 h& u) N$ C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 B" C5 u% z, i# W( s. ]. q7 P Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) X6 {" f% O% ]- \5 u! f/ XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, J7 r- n7 e/ B2 I
}
0 a- F6 ?( m+ ~: i! ?: l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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