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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* Q o. D q; a9 w
input mcasp_ahclkx,
$ x' S1 S% }1 P, U' einput mcasp_aclkx,! D, i6 e P0 W, @! A+ E( s. n
input axr0,+ r- N) Y9 O/ b9 o# j; ?, C
1 q8 t# A. n g/ Goutput mcasp_afsr,
& o# f& k( H' woutput mcasp_ahclkr,* m! ^, y6 L, d8 y. h/ J( T% n
output mcasp_aclkr,7 T5 Y9 u5 [3 m* |
output axr1,9 _% ^% ]; o9 E0 K8 p: j. S
assign mcasp_afsr = mcasp_afsx;& p4 `# p3 A; E$ y0 }5 u! \
assign mcasp_aclkr = mcasp_aclkx;/ B z% c# H0 C' ?* L. d7 U. {
assign mcasp_ahclkr = mcasp_ahclkx;/ `( {) W( `1 X$ z, N
assign axr1 = axr0; " d( ~1 g- P. v3 w
6 P1 U9 ]$ s- K0 A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / Y, s Z3 o( J. l
static void McASPI2SConfigure(void)+ Z( x# V, z; P' B$ U' s
{
& f9 l0 o2 J& A Y" kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: H- s' t4 U& i. W U W' SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. E9 `7 E7 _* ?2 g1 D1 c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, Q' s7 s. o# d1 Z2 _- L( i' U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 R$ A& p& e1 g0 Z4 J2 k8 z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# y' d" `1 _- \MCASP_RX_MODE_DMA);1 {/ g' w) ~! b7 O# h* M- K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ `% ?" R8 j7 a: F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" V @; J3 k' z. K, n8 m E8 `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ S1 k! n# ?4 y4 k$ m' w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) \5 W9 v& O/ [0 c% O- p8 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
t; w5 J- p' Z6 _8 B1 KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 p6 \$ y7 z3 o9 d, L1 LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 e( s: c; l/ Z9 I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 c2 p& ~0 t2 W9 z- i$ A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ G% h: o+ w2 _; G
0x00, 0xFF); /* configure the clock for transmitter */
/ @& k9 A- T {7 G) O5 xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* ?, `$ D2 l' r' c" ?; hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " R5 ?* r5 E+ J# B& E$ @. s' x# S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( e2 N: k [1 r0x00, 0xFF);9 y4 }7 ?# M1 g6 X$ l. w
3 E5 n1 L- v8 q5 x( {& z% \1 L( L+ p
/* Enable synchronization of RX and TX sections */ * L& s' S6 G& |, \. D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 e7 x2 b7 w* c2 ?+ K( e6 Q# a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" K. j* N/ L5 @5 Y6 |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; @8 ^* t4 Z2 i1 f4 U% _
** Set the serializers, Currently only one serializer is set as
6 n2 U0 P0 T' D" W" V3 |) h+ x** transmitter and one serializer as receiver.
. @8 q! N% W# U/ w$ a; ?7 K, \*/
2 V! ]$ A% ?+ e- I, r9 ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% G1 v e2 P; t) E% e4 G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; Y5 s& X1 i! @4 \# F5 \** Configure the McASP pins
! ]/ a+ P/ o5 c0 I* R2 R6 ]( h2 |** Input - Frame Sync, Clock and Serializer Rx) N2 i" D3 h; u
** Output - Serializer Tx is connected to the input of the codec
9 R2 Y2 [" B: {- G( e*/
9 y% o& T7 Y' `; uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! ^2 B, |& _- G: r* E |3 z( d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 p) ^+ L& a1 F; c. r3 I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 M+ P& W1 \+ U1 W$ f3 C( v
| MCASP_PIN_ACLKX
7 Y; h$ y7 p. u$ H, l2 R| MCASP_PIN_AHCLKX
7 I8 \5 z ]! ~! X" w% w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. f; ]3 y$ Y5 i. ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ [. j) m# }# \8 a# ]| MCASP_TX_CLKFAIL
5 Z* s5 c* W2 B| MCASP_TX_SYNCERROR
' |% r+ ?1 x. i' v: a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) S4 G* Q. V- b8 K/ T8 U& ?) S: U7 r
| MCASP_RX_CLKFAIL
' o* y% i/ z1 ^$ U( K. f8 F| MCASP_RX_SYNCERROR " R- l$ J/ P0 W6 O7 M8 ?- t5 d; X
| MCASP_RX_OVERRUN);
" z3 g _9 |& S$ P# j} static void I2SDataTxRxActivate(void)* W8 n/ |! B5 Q4 P
{
( j/ n/ d& {) n2 h1 q$ r/* Start the clocks */* P' a5 U( P4 v5 m0 r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ i1 V1 d& ?& F; m6 k5 S ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 q, [0 c; F$ T1 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' [6 F$ B6 d3 j8 p A+ ~' q9 hEDMA3_TRIG_MODE_EVENT);) B( S8 @: }7 H! _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, i5 o9 i9 f8 x; n- h% |" c3 d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ c$ j% Z3 ]4 y7 X5 \1 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# Q: R/ {, \1 KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 r2 Z( z( ~# h9 P) o4 `" K. owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: m0 m! G$ L3 q7 h; w; \ U* mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. ]- A+ m! x! |* L, _' kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 Z8 M( N; b5 T+ s) y3 R4 l} 3 {9 a6 Y; `7 U+ m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 U c1 k3 A- y! X6 n+ e8 x' H0 p* \5 L
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