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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 W0 P# ]( Q8 E3 O8 ^* P8 y/ I) t# Yinput mcasp_ahclkx,
5 ~, A0 H3 o' C5 T2 F! Hinput mcasp_aclkx,
8 i: e8 ~2 T) L! i- Sinput axr0,, w1 ?! N# h, f3 S( l* i
$ N* y) p8 r4 l( L
output mcasp_afsr,
# ~5 H- x7 K+ g/ m* Y; y7 soutput mcasp_ahclkr," \4 E0 x! [4 {7 M( I! j9 |3 ^9 P
output mcasp_aclkr,
. J" l/ g0 ^; V. |* Qoutput axr1,, s j" l5 m4 K" V
assign mcasp_afsr = mcasp_afsx;
1 H3 u; j/ h. k7 @9 k7 i& I. `assign mcasp_aclkr = mcasp_aclkx;' \4 F" r8 U. J: G
assign mcasp_ahclkr = mcasp_ahclkx;; x$ m/ N! @$ b$ p
assign axr1 = axr0; ; u9 L1 |: n6 g9 E6 b( n
3 h( J* L' {. D. E$ ]+ q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 ~4 Y9 n4 U$ Q" u* U) ^
static void McASPI2SConfigure(void)
3 j9 ~; q) v; m- E6 X/ {/ `. g: y{
; a( L( K5 K1 p( f3 _" dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' j/ G% S$ b5 b5 m& p; I* b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- y1 u6 H. |4 |& k) r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 w9 [! w4 e' P' R( K. U8 p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; I) ]8 d0 r eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 K4 Z. h' P4 }9 v# j" n0 {MCASP_RX_MODE_DMA);
0 C/ q6 ]! O. C( SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) `% t; {8 ?8 [4 a0 B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; s8 H$ n4 I! y$ ^, X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # ~* m* g m8 V+ A! O! \; }6 U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ W4 K' o* [* ]* E7 a+ F0 }) wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; l) B' ?9 D6 B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 p2 `' Q, `6 |5 ~; V- p, uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& q7 m/ J% v4 h$ r2 Q4 oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - ^# p7 m5 ^% @5 ` N. A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 P7 r* L$ C2 @8 S5 n; w' \
0x00, 0xFF); /* configure the clock for transmitter */$ I. z$ |+ k' K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 O! W& L _" S. R' O9 D2 I8 N! fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " w9 r. ?1 [" j) F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 |+ W( J" P. y4 O& r% N, Q3 C
0x00, 0xFF);
2 z* b% C- B: H! m+ \" s3 S6 o+ P/ b) K! n' n
/* Enable synchronization of RX and TX sections */ . H4 Y" K" a9 W2 i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 G! u7 r7 t( K3 T# M3 o9 xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% F2 H4 \# j+ Y+ a4 F3 V% OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 r% x; G E" `3 {' Y3 }% [" N** Set the serializers, Currently only one serializer is set as+ {8 F; @' @% \6 ]8 Z$ ]- k
** transmitter and one serializer as receiver.
$ a% E( h1 C$ Q% e/ U*/9 m k8 `1 _! D7 |0 Z% I2 `+ E" l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; D, z% t3 u" J# C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- ~6 k* ~) B: x5 V( x. R& H** Configure the McASP pins
, f2 \( X4 a6 U1 G** Input - Frame Sync, Clock and Serializer Rx
! A( I3 R, h" f3 T5 I** Output - Serializer Tx is connected to the input of the codec
/ E% |& f, ~) ?7 c6 ~6 X*/+ c$ X7 g+ X7 D; ~% ~! B% o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ T7 x& t; y% G7 Q9 Q1 J+ xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% u* |) V" b* q8 ]1 @5 d, R7 I4 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 b6 y( N j, z& f _9 D& I+ m0 E" V
| MCASP_PIN_ACLKX
: z9 @3 p) W4 j& W# E. R| MCASP_PIN_AHCLKX
8 j& h+ ~5 l& q2 e3 P' ^' J0 M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 y; K6 J* T, c6 }2 k0 eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ w. p9 {* M0 o| MCASP_TX_CLKFAIL : j* Q P- S6 L8 r; f) t
| MCASP_TX_SYNCERROR9 _9 H& v# ^) t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : Y7 l# T: L& }# _4 Q0 H4 V
| MCASP_RX_CLKFAIL
7 M, H5 [: f* k| MCASP_RX_SYNCERROR
1 V! ?, M- g2 v5 ]8 y* C! L0 t| MCASP_RX_OVERRUN);! g, J' {% O8 b- U
} static void I2SDataTxRxActivate(void)! u! y0 C& A" X$ }% u! V, ^
{9 D6 H8 ~* z2 t [
/* Start the clocks */
9 g& M6 S7 P8 m- _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( ~7 `/ i t6 [2 x) E& q" _# rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 P# }+ n9 p) z2 N+ d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 b- F# J9 Q; l; w& u1 @1 `& F% sEDMA3_TRIG_MODE_EVENT);9 t) \$ r7 ^7 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 b0 A- L1 x) m+ i3 ^% z) m, C' p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, G7 }2 Z; v' w& n; g! c+ rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ R/ G2 R: }1 N* H- d9 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* b, h8 Q a! C4 P' ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* u, u# h$ k* o; oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- J( v7 C, G' f" D: v' ~- O4 bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 X; O; i$ v# j- j' q* Q
} $ }, `$ {; G# v& S; z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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