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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 M3 d1 a5 Z3 \" E2 p
input mcasp_ahclkx,2 `1 m l& O7 R/ a2 s
input mcasp_aclkx,# [7 x0 u8 S: i' K, ]+ ^* k
input axr0,
, @* C2 i0 S6 s' W# p6 h4 k, D! }8 l) c2 _! ]# Q! J% Z5 k+ F
output mcasp_afsr,
1 f% H0 D% b4 o* s+ W5 ?9 Y) T( q2 loutput mcasp_ahclkr,0 P' q+ G8 F; \' ]! n, O
output mcasp_aclkr,) d( E& F5 t1 o# E
output axr1,
0 o4 h' D2 ^0 T4 B- J3 T assign mcasp_afsr = mcasp_afsx;- Z$ z3 Y7 q4 Z7 L ^, o/ _
assign mcasp_aclkr = mcasp_aclkx; Y) I+ A) F7 I9 `$ P# Q: g
assign mcasp_ahclkr = mcasp_ahclkx;4 J C6 ^: |9 c: [" G0 t
assign axr1 = axr0;
+ U" }. j0 B" N4 }: |( H2 x3 P
( c7 \9 }" u: _: h+ R9 W$ t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ e7 `$ k) g Y" f' Mstatic void McASPI2SConfigure(void)
; W8 v5 D8 N; c0 R9 m5 J{
: n) r- T* S) KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- z$ q$ w% P3 t2 OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% u6 M( G5 I& V( e8 q" K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 Z2 p0 m* c2 mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. y( z* D: e- w9 k y3 qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. A) U9 f4 q) T! c' rMCASP_RX_MODE_DMA);
5 a! }# o4 v* s8 ~ SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
V0 ~) D+ `6 lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# ?0 h& c+ Y4 Y! e$ K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& _3 k: r H$ oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" x7 `! r, z2 u! G! y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% o9 J N& J. M0 W- g- s2 w/ jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 E& F, N3 u4 Q9 {: i# J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 a7 S- f$ ?0 b" b/ S7 f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - ]) v: W) }7 O, [ ~' U2 @' X. N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" e3 v7 G2 o( Q" u8 i0x00, 0xFF); /* configure the clock for transmitter */) N2 t1 P+ r7 {6 d* b3 S2 g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ x5 \ J& K/ f# c) N# \' A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& P' q6 v' n0 X1 ] pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. v% u; B: H/ C
0x00, 0xFF);: ^& O; d8 w& ?4 C
, Z: u# n' n& R" ~* k/* Enable synchronization of RX and TX sections */ 9 ?; j4 {) K9 D* s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 i- K; _5 l% W2 K" z. Z R$ `- jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ {; k: |) @, f% F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 Y5 e" V9 N- ?, K
** Set the serializers, Currently only one serializer is set as
* W& K" _' U9 }& R8 o8 m6 k" g* l** transmitter and one serializer as receiver.
4 Q. t# i( N! Y! Z2 \0 ]9 Y*/
7 v# a. ~. {( C1 Y) yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 B: W* v. y4 F6 CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, r* Y; \* \& e3 x** Configure the McASP pins
, Y; D/ }! s4 y% J4 ]( l** Input - Frame Sync, Clock and Serializer Rx
, z( j$ [. D. t) @/ D** Output - Serializer Tx is connected to the input of the codec 8 u& V0 a K6 `5 Z3 F! s4 F
*/
# m9 \: d* S+ _% f# R) H4 {# jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 j8 m9 O" |& R3 z9 `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 x4 M/ i; X% y( i! k0 q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' @- Y/ n R3 P F# q0 Q$ e| MCASP_PIN_ACLKX
9 f) T, y- r+ q* Z4 \ z% v| MCASP_PIN_AHCLKX- D2 C. \, z" M5 E2 v+ @4 Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' k5 v" v2 f S- }* KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. v' g# k- z. D; v| MCASP_TX_CLKFAIL ! |$ C% @- H8 f' e* F
| MCASP_TX_SYNCERROR
1 G+ n! c2 l- A! a% }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ r7 d- k' f! I% x| MCASP_RX_CLKFAIL4 v5 J2 d( g, L$ T* ]
| MCASP_RX_SYNCERROR 6 i+ B3 E6 @; `" f; y" O% e1 [: c
| MCASP_RX_OVERRUN);: S$ I9 E% A( l- w7 s$ p
} static void I2SDataTxRxActivate(void)
" [3 h: c8 n/ @. g8 T, j+ ?& k7 {{4 z, n" q6 ]' @
/* Start the clocks */- i% t5 f2 @/ u" f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 r) X& r# ~; P9 m% V y, D7 X6 B( iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 f/ X0 V* ` q/ `+ Z1 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
\+ m6 m. R' P+ BEDMA3_TRIG_MODE_EVENT);3 I) A7 V# M# o# Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
T( {$ W3 X1 z1 @8 XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! w* e- H6 N$ k7 w- }3 A# LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; k7 |6 c; l: @! m' ?7 r% _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& e& ?) F/ ~ M- @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: `( q5 a8 f, x7 A, \; L; E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 [0 F: |' ^, s5 ]* y: _& B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 m& U, l4 h B+ ~/ W
}
: @/ {$ z9 {8 }8 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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