MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
. V7 [/ n1 ^7 u9 {0 b4 r& [7 Hinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

" g7 @5 r" A5 Houtput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
% g3 |1 Y/ {  ]9 j

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
/ @1 z6 q4 C5 h) d+ d8 kassign mcasp_ahclkr = mcasp_ahclkx;
* j0 Y6 L/ w$ q5 h' Vassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
+ K- }3 C0 w; I! j" }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
9 I) r! G/ h/ n5 h  Z; fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ V, f, I8 g3 S% P( ^" d6 q& [9 nMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# t% i6 f' M" c% i4 LMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" W. [+ M. x, V0 n1 H% @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: }8 y& m3 ^% dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* {! h- W$ d" t- D0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 M$ c! R: k+ o2 O: YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# @8 @. Q8 w/ R2 }2 Q0 k3 IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
# ]8 T  X! }) I0 |5 MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
; |" f/ M1 \% }5 b5 i** Set the serializers, Currently only one serializer is set as
, k" E# ]& e3 o. I  a& B9 P** transmitter and one serializer as receiver.
( w6 L! \" u, E*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 F8 |6 g2 t/ _& ]9 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
* s* i, O( X" W** Configure the McASP pins
* Q' w1 l2 J8 u** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
* e9 c3 H6 j2 H& qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" v2 F: N6 f/ E+ K: k# G* r/ J$ f) `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
  M, O) D2 a0 i/ l6 }  W| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
' C4 b  l$ Q7 q: `" d| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
- B% p1 E( B$ x/ i0 rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
5 |9 u$ s2 m+ q' b6 E| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
9 b. j4 u6 h( I5 a0 c; }6 a+ B| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
  M: d4 X: H) v, u4 ^. |}

static void I2SDataTxRxActivate(void)
- A2 @7 V" |& E, f6 k; c& K{
+ I+ [% Y7 h) y# {1 R: E3 E/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 I3 Q8 b+ \4 |$ _$ KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 t* D% U0 |! Q2 IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
& m1 V4 H' l3 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; K$ d$ G, H9 `* [+ @$ }- s  }% EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
( ?  p3 n4 A# J8 S2 {) j! hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! A$ X% \) T% D0 q+ P7 h+ D  AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.