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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 j# ]$ W4 g, x) a0 o' t9 N3 y, q) Xinput mcasp_ahclkx,! K4 m( }4 c% M" W4 @
input mcasp_aclkx,! r8 ^4 a |- P: G6 r
input axr0,5 g9 u; o/ h! W
8 Y/ W0 ?% ]9 @output mcasp_afsr,7 \2 B* e' }# ^& A0 D! H6 [) w
output mcasp_ahclkr,
Z3 e# ^/ y% K: Soutput mcasp_aclkr,
7 n' _6 p; y8 N' ^5 T5 a8 Toutput axr1,: v9 z4 c1 C2 ^( t
assign mcasp_afsr = mcasp_afsx;
1 I) r" M" L+ Q+ K& F. y# Wassign mcasp_aclkr = mcasp_aclkx;
, e: x5 {5 h& F# K9 M& Dassign mcasp_ahclkr = mcasp_ahclkx;3 X5 ?) Z/ g% K$ |
assign axr1 = axr0;
" p; v e! E4 c% }# Q+ G" }* b8 s" k0 M! d$ j: d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 @* q, h9 @6 s1 M; Z
static void McASPI2SConfigure(void)7 v/ u6 K8 l4 u0 i
{/ L3 k3 j- X) u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 `8 h: y# T7 y3 Q$ ^% e5 K6 AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 u* [3 v/ j# ^/ q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 @" D; V# P3 D& B& B8 R! ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) A5 K% F" m; @. H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 j! j2 V) S7 F) X2 D
MCASP_RX_MODE_DMA);* b! G# x: M" ~ H$ b% ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. ^' P. S( @+ W. I1 I1 V1 EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# y( D; _7 F! Q2 Y0 Y& AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' s1 y) ?9 `* E: jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& `# w" b R+ V% X1 kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 ~ o# N3 w& D8 T$ ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; H# Z N( r& _7 v8 E+ fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 E3 o2 q5 x5 q- \& PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* z1 V7 ]8 s( ^6 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ R9 a0 K7 D5 o% U
0x00, 0xFF); /* configure the clock for transmitter */" R" l* g) ~! l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( y3 a1 F5 d3 ]. MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 p- H$ u% x/ e) _, v& w9 w* r' pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& R& ~, T' n8 v( t' G, g. A0x00, 0xFF);' L, u2 w+ _1 c7 B
2 p# k) t8 v; \! P% ?/* Enable synchronization of RX and TX sections */
* V& v1 q& X6 ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* M- R$ T6 z* K# ^# f1 e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ n8 y) l! b' k0 \' Y) M2 L \) ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, P0 j- j/ ~( d/ d
** Set the serializers, Currently only one serializer is set as
+ k; T6 Q3 g9 r5 O** transmitter and one serializer as receiver.
& K/ }" A6 F5 y% B% O* J*/
- } F, v0 S+ Q$ ^6 t6 m) y" p& WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( L$ ^- x8 ]# B4 s* O3 nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 }& }. L9 ^. y: N; \) Q
** Configure the McASP pins
( K- }" _# b: T8 t** Input - Frame Sync, Clock and Serializer Rx. _1 g1 m0 }: z& A8 _
** Output - Serializer Tx is connected to the input of the codec % ?$ i% d% H! ]1 J
*/
5 \+ w( B. x$ O& ]3 O KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" i% `$ ?% j3 H: H( D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* n% K% ^- i* z; c; C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 I8 s+ b- A% C| MCASP_PIN_ACLKX1 G) H$ Z& b/ f" |5 F8 l8 ~% _
| MCASP_PIN_AHCLKX
5 p' Y5 o# G8 ^+ v! v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* X# `7 l7 l; {' n6 kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 E+ z4 Q x, |3 W* x* @
| MCASP_TX_CLKFAIL
5 e6 P8 S1 P; Q& j+ b/ t| MCASP_TX_SYNCERROR: z6 ~4 `; Y. q- z- M5 B4 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 t; [" P* S+ T9 N0 N* F
| MCASP_RX_CLKFAIL
& p; p7 ?6 s: G) K( Z2 B9 x| MCASP_RX_SYNCERROR 2 J* ^/ L, R! Z c
| MCASP_RX_OVERRUN);
+ L& B6 ~: U4 h8 C1 H} static void I2SDataTxRxActivate(void)
3 M9 ]% J+ C$ m- ^- r* D{6 E# r0 O/ }9 m5 Q. |
/* Start the clocks */' e4 ?* B' S; Y- Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( r% h- t/ u# H- D( M$ O3 M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ M. S c3 U) P! u/ j$ Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 F; C c+ Z& ~2 X* i9 J# u# BEDMA3_TRIG_MODE_EVENT);
% q* R/ r5 \: }* j! e9 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
X0 `" E2 `: U# g7 X9 ?4 t; cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! p& K3 A$ Y6 u2 K4 ?7 ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 p- A& t7 A3 X1 Z% J7 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 s4 g0 r5 N+ D, A& i( zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 R; B; [* k0 g3 L9 v0 S' Z3 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' p' V6 W0 Y8 P- g' I) d5 t/ vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 p' H5 a0 A$ c1 T9 r; }} " Y4 m2 z! D) Z- h) @2 W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; x: N' x5 y' \! i& F0 a
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