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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" a6 Z4 U6 s0 f" u! P R. U1 ginput mcasp_ahclkx,( W4 ?8 r/ R0 i+ R
input mcasp_aclkx,: Z1 L4 A$ T M# V
input axr0,* Z% }& Z1 i% n! h2 u, c2 \- C. d
6 O5 t4 |6 V6 r9 [6 @2 W7 _
output mcasp_afsr,
: K- h) `4 ]+ G g- I/ n. Ooutput mcasp_ahclkr,
R+ t( J5 {8 S0 t. g5 voutput mcasp_aclkr,
1 u% \- D' M: z r- A# L5 S0 aoutput axr1,
7 b% q. e1 U. e% z6 D* B assign mcasp_afsr = mcasp_afsx;
6 U; K; h' @5 \8 R; {. q' a$ ?- [assign mcasp_aclkr = mcasp_aclkx;) S& m! t5 b! F# v! \ s4 K
assign mcasp_ahclkr = mcasp_ahclkx;; L4 n6 }4 W% G6 d8 r+ F
assign axr1 = axr0; $ K' m l1 m$ T, I1 ]/ y3 \9 E
/ L1 D$ I7 {. N) x6 J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# x2 ?' E& |% cstatic void McASPI2SConfigure(void)
9 o% I% f/ t4 @; J' L3 k" a$ O2 G1 s{
0 N4 y, h: ]6 C/ i% sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! Y4 C l6 i, U- M, i' r0 @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ I9 b4 G7 C3 N- p8 H' K8 EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% p6 d" {7 [( e$ `( B- o8 d4 sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ l# ]# y w8 H; M6 {% nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( N* ~$ j; M* y# ?: c+ D9 cMCASP_RX_MODE_DMA);
* j1 n/ ]8 \" t4 z+ _" m+ J. _ UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 R; l& p. F9 s( V) [# w" }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" ~" ?0 ^# B! ]/ u, Z( v' ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # F4 K2 q% {, ^: p+ g# y. m: C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 x% t) G7 H& e+ dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' g1 `! D% d1 O5 W: _$ t6 d3 WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- B( E* v/ e9 `' d, I0 R: S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 c7 q" _7 [8 a5 i4 ]( W) D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; s" I `: n @* u- JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- O1 f7 h( ]3 Z0x00, 0xFF); /* configure the clock for transmitter */, z% y" j4 ]# l _0 |& s9 K4 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) X+ q6 q8 l1 s1 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . M; `2 x9 f' o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 ]( I/ F, t2 R! o; R0x00, 0xFF);
- H) V; i0 J5 Q: T/ ?' z w
3 Q: e& P6 ]4 e6 @. K1 ?+ J; `/* Enable synchronization of RX and TX sections */
6 \0 E- X2 A: lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 B8 R9 i) W" T# Q2 \3 s5 gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 M7 j; V2 ]9 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. d g# Y3 n8 B& B
** Set the serializers, Currently only one serializer is set as9 V) V8 W: z5 {
** transmitter and one serializer as receiver.# b0 G4 T1 Z. j/ ]
*/
0 D' v9 @8 ?) r4 K( N% N6 n! eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 }7 ?) g8 Q( s4 _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ x* y" H; t+ z8 E7 V3 D/ J6 B** Configure the McASP pins 6 _" L8 g# l) P
** Input - Frame Sync, Clock and Serializer Rx
8 Z( I6 ^! o+ h/ E; }% ?** Output - Serializer Tx is connected to the input of the codec " [1 t. _5 K) X* K A; ~+ e r
*/" A% ^- J& v& f; b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 A% p# L' K1 \5 [( u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 o7 Q6 h) W& b$ G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 Q6 F& J8 W6 w: I8 f! ^) W
| MCASP_PIN_ACLKX# I8 N c4 E: D+ n3 O) z1 w z
| MCASP_PIN_AHCLKX* r7 S* [' w5 p) t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 k! e9 i F+ Q3 c3 V2 q* k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # [" p1 l5 ~! Y+ o' @. n
| MCASP_TX_CLKFAIL 2 s, J- L& Y `8 M3 @3 S; J) \
| MCASP_TX_SYNCERROR @" S1 ~% V1 I0 A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; O: @" @/ y! N2 ?
| MCASP_RX_CLKFAIL
: s. U q0 z. W y| MCASP_RX_SYNCERROR 4 \* B! k2 l3 d5 W
| MCASP_RX_OVERRUN);
9 m! c9 Y1 Q7 a M: i} static void I2SDataTxRxActivate(void)& K6 B n5 b/ e2 | G# O
{! t0 L& \! U3 y5 W6 g; R
/* Start the clocks */
( Y1 N; [+ j+ w5 AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 ~& N9 j4 ^0 X7 e7 z% N+ s. i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& G8 c4 A) D& Y ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 z2 {1 J5 |8 o
EDMA3_TRIG_MODE_EVENT);- m1 @. }& H9 X1 r4 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
{- \& s5 p1 o1 A& y uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 l! z& f, Q* {; ~; \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 d3 v% U5 P! h5 u7 U' {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 ~4 u- K+ r+ S5 Q7 N _7 X4 G+ r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ _- p/ v1 a: N1 W6 | z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% v0 c3 H) u& w4 } iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& g0 w0 K& d5 ^% s
}
; s/ N h: c W. h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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