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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- s* |2 S% G7 l# W: a
input mcasp_ahclkx,; H7 Z2 ?. G% d' n
input mcasp_aclkx,
( {) Z1 |% d# E9 A( K5 o/ `input axr0,
; j' l0 K2 L$ k' S
9 ~3 w* L6 ]/ E! C: ?( r! b# coutput mcasp_afsr,6 e& g1 }/ G, A& F& a5 j
output mcasp_ahclkr,
( n, }. @- Y, @% xoutput mcasp_aclkr,
- U% G, C: J$ W& U' o woutput axr1,
- S' Y6 @3 d* r+ ?5 f8 | assign mcasp_afsr = mcasp_afsx;
/ ^/ Y. R' j+ y9 Y! A+ nassign mcasp_aclkr = mcasp_aclkx;5 a1 U$ }, I1 r) r
assign mcasp_ahclkr = mcasp_ahclkx;- h/ C7 d/ E7 z
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / u- B9 n: j% V5 S3 M8 H. a( E
static void McASPI2SConfigure(void)/ G# L K2 w3 Q' c
{$ \( g5 i6 ^5 L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, C+ M9 L" I& m! {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' q2 _7 T8 ^) Y7 QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 g! Y* }9 W6 M1 w: Y6 M3 X9 H) p+ oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ c. ]9 B* J* R* B, AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. I( t$ M' @4 }2 ^: t/ x* u& J% K
MCASP_RX_MODE_DMA);& i6 O* V& b- v3 L& q, b6 C7 ~0 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ t2 a" @- I; `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" h3 C/ w& o# |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 v, Y0 {" p; M5 E* X0 {$ b- m+ IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* [& e# a& f+ f! D1 a" o1 F6 ~' q; e$ qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ `1 h) x% Y8 A! nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 r$ c" H5 b5 j$ w& D/ _7 r$ F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 Z/ c( n; p, S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / t" ^' Z- X$ q ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 A# j2 u" O% ]- b' r" [' ]
0x00, 0xFF); /* configure the clock for transmitter */
% N }- c0 w, J- u Q9 V2 ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" l s; A% a3 ~0 H1 i- i& L* p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " X. u8 O$ p9 X' d& i' x* _8 C; c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! C& J0 ^( x2 F' |) p* W
0x00, 0xFF);0 F7 h0 |5 f( O* ?& g& e" W [
) e- ]* I5 `) Z! ~/* Enable synchronization of RX and TX sections */
2 E& @, n, F% qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 n+ z& F% X, ^ U7 m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( R: x+ L1 D3 \; ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" V' J i4 K/ V# H** Set the serializers, Currently only one serializer is set as' A+ l4 @2 l/ k' m$ ?/ n
** transmitter and one serializer as receiver.
8 F, h7 d& S- F*/
0 E2 C; x x2 y! s1 u; q! D. zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) @$ U9 n, v# ~* Z) Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 h: ^ X# N1 @7 e( U
** Configure the McASP pins
4 l0 w+ }( I+ v) ?) \3 N** Input - Frame Sync, Clock and Serializer Rx
7 @* j+ X) X4 Q; w& n** Output - Serializer Tx is connected to the input of the codec : N+ z$ Q# E4 n, C
*/
0 H- Q: z! X, c2 e( ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! r) n3 l0 S1 e" \& ?( Z, cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 ~ J6 L( Y( z' | [- D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ v8 u7 C# l) ^ @( s6 ? ^
| MCASP_PIN_ACLKX
K* x$ B5 ~0 \% g. V' y| MCASP_PIN_AHCLKX0 @4 |/ a, [- o# x) U$ J4 m+ g+ s$ U9 i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 T$ m: u! I3 S; o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; {8 F7 {9 q h* Y| MCASP_TX_CLKFAIL 4 S/ u; A$ Z$ f: \
| MCASP_TX_SYNCERROR7 p7 `, p5 |( |. V' s/ R3 F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & c/ N, H3 D& L. \! V
| MCASP_RX_CLKFAIL- b, u* t4 A, h! a$ C, J
| MCASP_RX_SYNCERROR ' T2 I0 x1 @! p- C; G
| MCASP_RX_OVERRUN);# i& q' i( `/ z* X
} static void I2SDataTxRxActivate(void)
9 R% B" R6 B; ~- A# K: h) f. |& D{
- K2 `0 m0 O R/* Start the clocks */
, b5 x& t( @ m$ G1 t- R4 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 e/ Z! G5 w. G( O; f# v( E9 u! B1 b! ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: p5 U% X" @' h: r! OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 _; a2 m. r* K: [
EDMA3_TRIG_MODE_EVENT);
. E" f7 e, Q6 Z7 G* U+ vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" M4 s* y4 V: i( \' p- GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 ^' ?9 Y$ W) l }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ r# V% k% C3 |( o- s2 E! dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 ]) \, l! m% Z5 R. ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- |1 M9 B2 \$ _5 o5 A% Y" V& v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' r, r4 u- W: L: V3 r5 t6 d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ [4 j+ X. E$ j+ }- r$ g" J I} 5 b0 L3 l! \8 M' ^' D R, B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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