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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) t. L# b: T( }: z
input mcasp_ahclkx,6 p8 r( K6 k3 m w* W( ~
input mcasp_aclkx,) g" z/ P P/ V3 I. s
input axr0,
, q. V7 A0 F! ` C( P9 h$ |
2 |/ | v/ n; Routput mcasp_afsr,
0 y s9 d- f! b( o Y0 soutput mcasp_ahclkr,
: s0 L6 a0 H& d* e, T2 L) ioutput mcasp_aclkr,
* @8 n: o0 x8 r% Y* Loutput axr1,
' w$ P" `% L* T9 v7 u* i. c- [ assign mcasp_afsr = mcasp_afsx;6 Y# a o" m. t! u. X" d
assign mcasp_aclkr = mcasp_aclkx;) y( r6 m t! X) `6 R( S& b
assign mcasp_ahclkr = mcasp_ahclkx;
0 X( C+ E/ g0 `" w( n bassign axr1 = axr0; / n" i- q7 _( i, N9 j# v/ }
1 @" j( i6 A; V' O: x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# s5 {0 n5 j d- {static void McASPI2SConfigure(void)
5 V7 X: z6 T* [5 ?0 [{: V' w2 E8 U' Y$ j' l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 V. Q. B3 \8 I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" U# c# V. m/ Y, H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" j7 w: i m- R0 U# @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 x$ Z7 y" L1 p2 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& S0 y3 g. e" g) X% bMCASP_RX_MODE_DMA);
8 e) i6 Z) Y9 n: S pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 K1 K1 b# F% k, ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! q8 ?7 f# Y0 ^7 X* }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) u4 ^: l S0 G. \: }) x( B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; |( |+ h) [6 q8 b( B4 SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ ^$ R- c# y4 Z9 u3 P- E) yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 X7 j# t1 J- g! r' H7 y1 y2 t7 wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ }+ B* c" G! z g9 [4 B( S6 |8 ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . w4 F, K C% ?& P# X. h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 B# \& v5 E! d3 E( k3 B" G% |6 q. Q
0x00, 0xFF); /* configure the clock for transmitter */
9 @8 }* |3 h4 y" k; x: `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' z# H1 v) O7 f% t7 ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: V% w( S9 E' T" ?9 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ M" G& X: G z& ?3 L% F0x00, 0xFF); F+ i$ T8 l# i4 I9 r
+ ^. m& y$ u' Y( E; K1 {
/* Enable synchronization of RX and TX sections */
1 I9 i5 S3 @5 L7 r& KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 F+ s5 b1 ~" T6 a$ {; b* s1 N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( L( v9 q! T: m3 h4 FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( t0 Q: J3 A" L2 W; ]2 ~** Set the serializers, Currently only one serializer is set as+ y, e+ \5 ]( n4 K `" \
** transmitter and one serializer as receiver.
9 Y _- ~) O4 n2 F*/" Z' m* w/ J+ x2 y. E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 k# F) S5 F& Q: nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; D7 K U* b" v$ d" ]- G
** Configure the McASP pins
5 @5 }/ b) E: x1 S+ Z/ l** Input - Frame Sync, Clock and Serializer Rx
1 \; m4 V" W9 }6 U** Output - Serializer Tx is connected to the input of the codec
7 V# s9 a6 `1 e% C- q*/( I% d# D0 \( E D7 H5 t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ n4 `7 b' w: d3 y4 j/ I& BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 @( b& q" J4 l B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 F8 |+ p( ^. q/ D7 {0 F| MCASP_PIN_ACLKX8 {+ [. H1 {. O% J' K
| MCASP_PIN_AHCLKX
% j3 D4 w1 ~% P# h0 y+ X3 g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% T" r) s2 e, ~/ X, q2 V3 ~* DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ w: t* @# e# G6 D# m" B& W| MCASP_TX_CLKFAIL
3 i! ^5 c' f1 c+ A+ G8 D0 N7 n| MCASP_TX_SYNCERROR, b% R/ P. ]' a7 c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , ]( z2 ?* Q9 \0 T, ?
| MCASP_RX_CLKFAIL' ?% F2 J6 m5 ^
| MCASP_RX_SYNCERROR
6 i4 p3 r {+ Y* f| MCASP_RX_OVERRUN);
5 \4 Z* N/ D5 X/ t1 ?5 J} static void I2SDataTxRxActivate(void)8 U7 U( {% F5 ^# x& \
{
, Z9 t) J, c3 W3 e0 s/* Start the clocks */
9 _1 F$ H: n4 m0 U8 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 j6 I* K; L1 P" H: Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// ?! `$ J7 t: p2 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& u' M3 \ u9 p% OEDMA3_TRIG_MODE_EVENT);
& {7 J5 F/ @/ v- lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 Y8 ?( R$ S# J+ O) g( V1 OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( ]) o0 ]- C7 I. c. U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ d2 e8 K' ]: u8 T9 j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' s. h. r" M* l8 g8 L8 h7 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ f5 q: T9 P0 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ L: A9 S3 ]0 Y! ^0 L) GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: w& ^$ n' a7 V" l
} # F! T7 }! i& Z% g" c8 b- T6 s8 H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - H! p9 N& O g1 b5 L t
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