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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- @, n# }; o/ C: Y# r
input mcasp_ahclkx,; b) f) z s' V5 v* n$ W
input mcasp_aclkx,( b0 b3 i( a2 i, U1 t/ \8 F
input axr0,9 c8 Z7 e3 x$ k9 o3 X, M# j9 n
) g/ T! H) X" X5 Zoutput mcasp_afsr,
7 w3 i# B$ b2 @- Goutput mcasp_ahclkr,
, b X; k/ ^4 J; |3 k- j$ Youtput mcasp_aclkr,; w' d/ S2 e& M* F# i# Q
output axr1,* v; g/ o& T- j# x0 k" k t K
assign mcasp_afsr = mcasp_afsx;" t/ p1 Y U( c
assign mcasp_aclkr = mcasp_aclkx;, |! Z! m+ S. M# d8 {
assign mcasp_ahclkr = mcasp_ahclkx;
9 [; L" S2 d! V) ~4 P, e8 t: zassign axr1 = axr0;
: T! _6 ]$ @/ z4 `5 T. V
1 I; _% s* C+ U, t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 I+ ]" e- G" @ f" n1 z, b0 X9 estatic void McASPI2SConfigure(void)
$ {0 G) p% s% b. l& G, }{
) x- q3 A; d+ t# w8 g- fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ p7 Q3 ?8 X$ K+ W# S. C+ G+ _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
h6 c& N7 t9 L6 _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ U2 z( q# K% ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ D1 j7 D1 P% U. O& }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ k3 T+ C4 j! ~ [5 n. h8 e/ b* _# BMCASP_RX_MODE_DMA);1 g, X, a; v$ n" e) N+ \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 {2 [! u1 k, TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: |1 Q% o5 P1 Z: W4 i6 s* U, ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 q9 a& e# e3 u( T% B! i! C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) r! M. D7 Y: L& B# o' JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! ^7 \/ V5 |; ]* A7 k: |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- E# }# u$ U4 v; u# }+ ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 I# S2 O8 `1 K: y! T: uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 \* |: e' v8 g# |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 u4 K6 Z& `4 i' V3 E
0x00, 0xFF); /* configure the clock for transmitter */$ B- J" h1 P7 {/ X+ ^2 c+ S9 e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 V+ m5 ?) |1 O0 h- C( G, bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( _1 {' W! z0 ~4 l N9 eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 r' N: [, _: ~! ]5 Q! t; Y0x00, 0xFF);+ b& w0 L$ ^0 F ]# @$ h
B; @8 c6 w: ~8 D9 m, @4 t/* Enable synchronization of RX and TX sections */
+ f3 v( E2 q3 a$ `3 S# wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; Q7 Z/ p' X% p' i* TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" V) m2 a$ j. uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: B0 o& z7 K" D& J0 S** Set the serializers, Currently only one serializer is set as
( a3 F9 J$ d- v7 x3 k7 \ b** transmitter and one serializer as receiver.
3 \/ ~3 h! Z5 H8 `5 V& t*/6 T) x) R2 T9 X7 x/ N# _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 A$ I3 j Y) J% c( F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. D8 d N2 J6 [, Z7 e** Configure the McASP pins
* J y; g$ ?1 B# Z# H** Input - Frame Sync, Clock and Serializer Rx' d! A; l- K- S+ T
** Output - Serializer Tx is connected to the input of the codec
; p' b) p) _3 F# ^, M! }( T4 A*/
% @3 x& w2 I: KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 H5 D: o/ i! ~, {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 L: w" e7 I) X+ g* J$ Q# {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 j* ] B, p2 ?& A) w% ]& E B
| MCASP_PIN_ACLKX
1 O" d, o. x7 J- V% @| MCASP_PIN_AHCLKX4 d1 D7 ^! t) _' D: q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! h# Q* D2 X! {: u( L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % c' G6 w2 Q# y
| MCASP_TX_CLKFAIL * V$ s9 X2 Z' x8 q- i1 A
| MCASP_TX_SYNCERROR
K* w/ \8 P: h1 t+ `, y/ K( k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 U3 b5 T) U t| MCASP_RX_CLKFAIL$ d* N9 E- _5 y# I% d, o+ ]
| MCASP_RX_SYNCERROR ( j( q0 A" k1 j0 _) g+ ]
| MCASP_RX_OVERRUN);
# j% [2 R9 V4 C2 e. _} static void I2SDataTxRxActivate(void)
0 D2 }) ^# @0 l+ v7 [- ^9 i{" R, L' _9 l7 v6 R+ Z: V' r
/* Start the clocks */8 y( @' H2 F2 [% d7 t0 p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, `9 l( F8 ]' Q7 @' V" u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 R: G6 m0 I( h- A# z' l# }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 D$ N5 y& _5 G: X
EDMA3_TRIG_MODE_EVENT);
" ?, B' l: v4 V4 ^2 REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# ] l& n" X4 `. l& zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
E1 g8 a% g5 T) wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 P% v! s" V/ F) DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 w: c0 `* x4 J8 O' r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" n8 f) a# V+ F# N- {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) @7 E, z( x r$ ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ `3 w; `9 _: c9 G+ i' p
}
6 M) u" w) W+ ?! y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + K; e8 H( _/ ^
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