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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, `% I; h( [( I9 c+ binput mcasp_ahclkx,% H% l# {5 |0 d1 v
input mcasp_aclkx,3 N, F0 O# o: S- m5 w: V3 H
input axr0,
9 D2 M! b8 D4 x3 [. A
& I2 @- @: R5 I3 W/ W6 moutput mcasp_afsr,
; H6 w E' W) N- c/ @output mcasp_ahclkr,0 [, a' A6 J! b
output mcasp_aclkr,
* B) y9 C% {3 \4 J" Z; V5 T1 foutput axr1,
. w# ^4 D3 }; V6 R' R, G assign mcasp_afsr = mcasp_afsx;
' l6 p4 u- E4 f2 Massign mcasp_aclkr = mcasp_aclkx;9 H& `4 i& {4 w% l. M! I
assign mcasp_ahclkr = mcasp_ahclkx;5 m* Y* Q/ g& h4 L. y
assign axr1 = axr0;
+ G. F& k* u9 Q2 [7 x; K4 [9 T$ p( b7 B2 A/ k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 Q$ |7 ~" V- x0 c% }- \static void McASPI2SConfigure(void)) u) Z8 D( T& ?# L
{. {/ r' E# \2 W% E. ^ y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 K- }% O6 [0 i+ [2 FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; @, X5 u# ]1 \0 KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, Y5 y X4 O" v4 g( dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# {) q+ p0 A" l5 T9 s1 L I. pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! U+ t: N7 E1 G. BMCASP_RX_MODE_DMA);& t4 v: w D) W; o- E$ q9 v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; r9 U" Z) O- Y, N: F. A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 I. Y) e+ b; }+ f- `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 a/ F Z2 I6 N M4 y$ n* _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! @/ P/ l- f0 j1 O0 O$ h) _8 AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* F7 P9 Q1 u$ [. SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: U2 g8 s0 v3 Q. K8 O- j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. F3 m* B: e9 J- M3 k7 U7 G+ eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + E: {: S+ l, C+ X H& W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" ~0 M' ~3 ^6 x$ k h% t0x00, 0xFF); /* configure the clock for transmitter */
! l3 `+ r3 D, g8 |" Y) JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 d: B* j7 U% n8 k d8 nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / r# J; I. m0 C# Y+ U+ l; S O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 H- S" T" m+ K, p
0x00, 0xFF);
9 o( s2 R9 @# ^+ w0 D+ `
" Y6 }$ G0 O+ j' D* R3 q/* Enable synchronization of RX and TX sections */
3 a: U1 ]: l% d; j- ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 S8 ?2 M$ a$ t; \$ ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, L1 p+ c" R9 `) {# U$ kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 p5 H% V' q8 g; d
** Set the serializers, Currently only one serializer is set as
# }' t/ \0 B4 w |. f- C) h** transmitter and one serializer as receiver.
# ~3 y2 }+ Q0 ~. j+ }, i- Q: c*/& A3 @- ?# I3 W( `7 h' U# c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) x1 T! h: L4 F% R3 b: WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 P( {' f! w! ^7 [0 O; L- Z8 L5 z6 u** Configure the McASP pins
+ `0 g3 v( z, G- W7 V** Input - Frame Sync, Clock and Serializer Rx1 L# C4 p0 b, G' Y
** Output - Serializer Tx is connected to the input of the codec ( j0 l7 |) e! w
*/
0 N: r; R: i. X, T2 hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) I7 o) U* F/ w" u U R, K2 k! X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( n7 q+ ~& P C8 }* x( X# `) OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' M$ R/ p( r* N$ N7 V0 R1 H| MCASP_PIN_ACLKX( m, q, J9 Z2 k$ w# L6 P
| MCASP_PIN_AHCLKX
. P5 m9 P# T) t- ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' D; p) e0 I* o4 {1 oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* c' E& Y M7 g+ V% \2 z0 e; Y: B| MCASP_TX_CLKFAIL
3 y5 Z5 |% D6 M8 B, k0 {0 W| MCASP_TX_SYNCERROR- ?+ N4 o" v2 U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! J, I8 T. ^% F
| MCASP_RX_CLKFAIL
" i h1 A4 F! ~$ M( g X. a| MCASP_RX_SYNCERROR
, r! W& g% n Z7 L| MCASP_RX_OVERRUN);
& E: n: w( ~/ E} static void I2SDataTxRxActivate(void)
6 d$ e! a+ d2 E* b{
( j) w/ m$ D, |/* Start the clocks */3 g" \3 u6 L' \6 } W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% V4 ^9 L1 d0 [* U) x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 V: F9 e8 }" r( h( aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 D- c$ a- }! V1 P$ A4 [- V+ k* M3 }- n
EDMA3_TRIG_MODE_EVENT);, [3 h d6 } Y- k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" i, o8 F; l$ mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ g5 ]) E5 a9 y0 I( H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 J9 J% M, `" k. {: l/ N: ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ k) Q% Z r! P7 Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. a, \! @6 N! `( X& ]" yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( t; P6 {( r# d9 c+ q( f. h+ D1 j1 g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& s/ ^! G; q0 K) W} 5 b" U9 q; I& m) }! ?4 H) d+ h8 N, [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # u& X Z% j0 F
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