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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 `" R$ W( ^7 d# d" b0 |( R
input mcasp_ahclkx,
/ ?) G; Y9 s( @" J9 }, Uinput mcasp_aclkx,+ A$ L% q6 h4 N \& k
input axr0,3 c v5 ]6 n, y: D$ \
# e; D' \" h1 o. ^, e: y- Xoutput mcasp_afsr,$ R" M4 B- u- o1 z6 g
output mcasp_ahclkr,) Y) b n) O3 o( L
output mcasp_aclkr,
4 G+ a- h. N8 S# a: i5 Q) K. n Koutput axr1,
I5 ^2 B% O0 p assign mcasp_afsr = mcasp_afsx;
0 r1 B1 p! @5 D1 c: r. p& g9 qassign mcasp_aclkr = mcasp_aclkx;
/ v! _7 J2 L: J" Q( y6 Nassign mcasp_ahclkr = mcasp_ahclkx;
4 l6 j0 W% u1 G" s; N4 Z S4 Z$ ~assign axr1 = axr0; A7 M# U Q" Y1 L; m( P
/ X, N" X& B/ M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* B: W1 A- G' ?; Zstatic void McASPI2SConfigure(void)
& |& b, y9 q' `8 P0 ^! {7 ^+ c, \{( Q, |+ l4 I" g: v1 O2 v8 c, J7 ?' c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 i0 X9 n8 E# L9 p5 } [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 K4 H' B( O3 O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! L' ^' F4 e: D2 G! wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- t0 M! m2 h6 G# f+ qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ i3 {$ C* ]( e. P
MCASP_RX_MODE_DMA);
9 C" e! @# P& o. f, v1 n* C2 LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 v w; D. [/ x. P0 t7 u6 I! ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& D/ `5 e8 }, a" R2 c6 [: eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 i8 ^0 z1 v- O( LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 g/ x& O3 {$ C/ T mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ H% [% {5 C& {, {4 Z; M$ u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 L" ]+ m8 K% I \" f$ c* b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 O. |0 O$ d$ f; Q! \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( \7 G. p" [7 n/ j- J9 S9 Y4 y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 n- H+ r0 V& x% @; t) \
0x00, 0xFF); /* configure the clock for transmitter */' t( H: r4 H6 P$ d/ V3 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 u6 N2 M1 {/ m# p! i' F- n; d# Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - ?3 N3 V8 h/ L5 n+ i! W4 s8 N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, h B0 g! |, @' e, p6 J8 W4 b" x0x00, 0xFF);
9 \! n5 c7 `5 z' [5 [" n) U3 D9 B- J" [6 ~6 Y v
/* Enable synchronization of RX and TX sections */
/ H& i9 z2 l3 @3 K2 tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# J% ]/ `' L. SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 C' P+ J7 D9 g) V: y3 [1 b0 q. F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% f# |( ]$ m$ \. I' W
** Set the serializers, Currently only one serializer is set as' z' {+ f4 ?; r1 U o. D! F
** transmitter and one serializer as receiver., c e9 T" P/ T! @7 a7 R g5 O
*/
2 w& X9 p0 B8 Q# VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ H, _8 b0 D) q" @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 o* U6 m2 Y* m$ ?
** Configure the McASP pins , W4 v$ ]& x" S& W% v. a0 i
** Input - Frame Sync, Clock and Serializer Rx# \) a. G9 p1 X* A% ?
** Output - Serializer Tx is connected to the input of the codec ! ~6 y2 H- h5 r( m: \1 d5 W0 q# v- L3 i/ _
*/8 R4 [- k3 B/ b( y4 L# O8 K) ^+ |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* O8 a4 W' l9 z8 q- zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. A' o8 z5 Z" U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) [0 r* U4 |+ {0 Q9 I& j
| MCASP_PIN_ACLKX, c) M0 E, x: m' X" P8 d
| MCASP_PIN_AHCLKX
2 k6 K. i, Y$ c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 ?$ a. S# J7 X" Q# j* h+ `& H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; Q F) e f& F; b
| MCASP_TX_CLKFAIL - e: A/ \+ X6 h( f- Q- J0 t- N
| MCASP_TX_SYNCERROR1 I% s7 j; ]4 j: W+ T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' i# d C: h" s9 U| MCASP_RX_CLKFAIL
_( G: A$ d4 _| MCASP_RX_SYNCERROR
# ~' T$ {9 s5 \3 c| MCASP_RX_OVERRUN);
0 z" t0 [2 S6 \( D1 L} static void I2SDataTxRxActivate(void)7 y: W6 Q& j/ ~0 g0 t: V
{* l' u, ^% I5 E$ b
/* Start the clocks */
1 P/ H9 m$ e* mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ N7 [; `8 Q, F6 i# w# vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 X# l2 w$ }( j# p9 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) i# O# G0 N( B7 s) |
EDMA3_TRIG_MODE_EVENT);% m" J7 j4 n( k6 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! K8 l$ v7 x4 l* g+ `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% ?* X3 R$ u' _7 ?+ @3 i* K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 b2 K4 x, \2 ^3 x. E1 j" L+ {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! t1 u$ l( l/ G! n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, K: B0 y. P n# \" ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) V$ t. W' ~4 ]( W$ P; c) K# ~1 ]4 ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 ?6 E( n" u. F- ?7 g4 o5 _
} $ W) r9 R! ]4 e( `! L, \! B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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