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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 G/ W* ~; J, A! U( i
input mcasp_ahclkx,
) P# Q" D1 U0 e: T5 Linput mcasp_aclkx,6 ?$ `4 U$ ^& l% w2 r
input axr0,
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3 P7 u. Z5 ]. B$ D- y' routput mcasp_afsr,2 o6 B8 ^) ]- C
output mcasp_ahclkr,- I+ s3 L8 w1 J- I+ s/ _1 ~! V
output mcasp_aclkr,: b! `. D1 l# w, J! l) x
output axr1,
5 Y3 Q ^5 ~$ f, e. z' |) j assign mcasp_afsr = mcasp_afsx;
9 U1 ~: }$ l* O) H# Dassign mcasp_aclkr = mcasp_aclkx;4 g& M: I$ o7 H+ c' t- B
assign mcasp_ahclkr = mcasp_ahclkx;- U, W2 ~& b& B9 P) T" G; j
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( c7 j# y8 r2 i. Kstatic void McASPI2SConfigure(void)
- Y9 `4 ?$ H3 {* O. M9 A{
" j* L/ S ?) P! N. [' d& ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);; d* R( ]8 C. o% i! P2 z# v& P" l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 i# c/ P# f& I. u& D$ X' D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 l C+ v- x; F2 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ F7 e* z" T6 V6 R1 N; kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' w: ^- Y- f+ F6 ?3 _6 jMCASP_RX_MODE_DMA);
7 |( x" c" d" [# w! dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 R. r$ Y1 X" Q X6 G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ t9 F" z+ U6 z. K, l& ]9 F( f o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 E- m! o3 f& y+ FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! n4 I! a2 X% w4 W1 YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . u" C$ m2 v* F: p% M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 H1 o, h/ A9 K4 H2 @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- I( E- k8 E; ^+ U) y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . {- s( X/ e; v. o8 [3 m2 f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, }1 c0 b) T( K8 S, T6 ~) u
0x00, 0xFF); /* configure the clock for transmitter */
$ t o, ^0 G5 q7 k% [9 _" LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ Y9 q- Y! L4 [( A: UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
v' l* I$ ]$ G0 Q: T% Q; Q9 u7 MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. F: `. a9 k1 J* b8 a
0x00, 0xFF);) ]2 H3 t! E8 M
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/* Enable synchronization of RX and TX sections */
& {6 p( b' A$ j! UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, b& |% o# y8 f& h0 `) v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 ^/ {: v5 n! Y& v6 p+ Z* T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ [5 M \ e' u) X; u$ \
** Set the serializers, Currently only one serializer is set as) Q& ]+ l5 D- v2 A4 u% E! u, i
** transmitter and one serializer as receiver.5 {" y/ e6 U, H4 I j% R
*/5 y; D, I8 }* |3 F- A! E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 B R3 S. \3 b0 s/ @2 Q' K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 Z: U# y g& c8 G7 R( h+ c6 R
** Configure the McASP pins
5 Q& }3 I% D L* Y** Input - Frame Sync, Clock and Serializer Rx, @. q* U% H* \1 e W# z
** Output - Serializer Tx is connected to the input of the codec
8 v) I, b( ?, ^# {& y4 J- S*/0 Y% k7 b7 w4 s9 F: U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' ?- c. P- |0 a: r* qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- f9 A& B+ S5 ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# o* `. y' Y X" v. W+ g0 ?
| MCASP_PIN_ACLKX
0 w' U5 z# c5 |2 y( F4 `& T9 a| MCASP_PIN_AHCLKX
( _% |. D1 M( S/ w( o) k* r" s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* z. ~% }+ c- E+ i) W9 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) Z" O/ Y/ N- ^! |$ n| MCASP_TX_CLKFAIL
6 R& j. R: G7 _$ z) o| MCASP_TX_SYNCERROR
0 `* m3 j( J4 A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % d. ^. U5 j, e8 n2 ^: J
| MCASP_RX_CLKFAIL
+ a# e2 l" F% D* q# v- E' l5 n! W' G| MCASP_RX_SYNCERROR
: \' C2 b7 A) q8 n| MCASP_RX_OVERRUN);
! n4 L/ a% R0 Y- i8 u0 j/ t} static void I2SDataTxRxActivate(void)
! ]5 o7 I: \* Y/ A, h0 T{9 y( U$ c& T3 w# V T. U
/* Start the clocks */
, F# ~! e( x0 s. y8 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 @; }9 z# F' c' g) EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ o0 U5 x) p3 N* D1 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 D; ~, J! Z+ Z) @
EDMA3_TRIG_MODE_EVENT);
; M, ?) D3 L2 q5 v- X8 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. L9 e$ j& c, yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! }2 p( x6 B9 d) R6 s7 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; U% G+ Z3 |' Q$ @9 F2 ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! ]" @- J5 p5 E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ V) O7 N6 l" F( O5 A* `% D* ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
x$ u6 T; x. a4 ^! e8 A, RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 q: ]9 m3 D* K1 Y7 X0 s
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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