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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! w) W J4 `, j. S" e1 B" ainput mcasp_ahclkx,
! e: Y) U3 D2 w8 K% G5 Rinput mcasp_aclkx,$ w O( X. p: _( W$ }5 `0 W3 C
input axr0,5 m u! Z8 V) H9 d8 E0 j5 A9 ~
# ^( d( P; U R8 W* N) ?) i, v) foutput mcasp_afsr,+ @8 }7 V! T3 |0 \
output mcasp_ahclkr,
7 r5 E' }2 q/ q6 Voutput mcasp_aclkr,+ }4 S c& N: E! v
output axr1,# t- {" A* F! u9 G- ?# W0 \* V% K
assign mcasp_afsr = mcasp_afsx;- Y- y. ~1 B' G- ]$ X) z, a
assign mcasp_aclkr = mcasp_aclkx;0 T8 E) D0 b& |
assign mcasp_ahclkr = mcasp_ahclkx;
9 W; j+ x- x( s+ h) Uassign axr1 = axr0; , C% k+ [6 I5 h- `0 Z+ l* F
; C; I3 M( V% M! M+ G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. ~7 Q5 e6 e" ?+ l$ Y, v- nstatic void McASPI2SConfigure(void)! X: H" y h- r& Z1 g& v) s7 r4 a* u
{
- Z' \) j% q l, i, ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, ^% E4 e; }7 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& v# ?9 S7 }9 E3 O% [( z& z" s# G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: S7 x% C! u7 X+ }3 Z3 a6 E# c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 L$ W5 V! D! e! N/ j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 t( h3 q% e% ^. G4 K; K C* Y. z
MCASP_RX_MODE_DMA);1 @# ^% D1 \( S: z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' D* x2 W" k6 c, ^" f" a8 E* |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% r# `# e8 F( }: P& {! {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: I- l! a$ z0 m4 |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: ^& _1 s" e0 r$ x5 u4 k2 W# x$ W. D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' d2 ] L. v% z# T7 e" {# Y/ C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ T0 P/ ?3 ?5 P* ^4 V' y7 K# lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 Z9 N8 O2 v# X; [# d- _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ k8 a( b9 C" I1 u2 |7 m/ }2 lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ i$ B5 [2 M1 L$ U1 B$ n
0x00, 0xFF); /* configure the clock for transmitter */& r4 h5 i9 T W, s F4 _! t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ c6 Z# Z- X5 A f BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 Z4 y ^" W6 X D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% n7 p ^* b" k2 N0x00, 0xFF);
. C0 y) o' d; u8 J% ^
5 E; V6 V% i5 v* h) Z/* Enable synchronization of RX and TX sections */ 3 C8 D8 @; Y- H4 D( W7 P! a% f8 o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# L; w, G: T8 F( `9 t; ?% k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 A7 d& g6 C, ]" x1 [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& C5 h: b* G$ b/ z2 j! H+ S
** Set the serializers, Currently only one serializer is set as
/ x( L$ u k5 C, f** transmitter and one serializer as receiver.7 v- j) d$ T% M l! V
*/2 h' X1 T" K, q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); ^ }3 R; n2 v% }$ w' p/ s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 V ?2 ^8 M& Z2 a
** Configure the McASP pins 6 ?8 m5 f2 q, r. l1 o7 \ N
** Input - Frame Sync, Clock and Serializer Rx
; g5 K! y& F: x2 K4 \8 B** Output - Serializer Tx is connected to the input of the codec # t- ^% x' g/ ]- i, x
*/! i; i" s+ O. |6 h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- m1 m. ]6 {; I+ CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: p7 q- v! g" q) D6 a3 eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; B0 [2 a, L4 f1 |) ]: _
| MCASP_PIN_ACLKX
9 V1 D7 l l, F1 T# V( n; w0 @, c| MCASP_PIN_AHCLKX
2 k( O8 G$ g6 o9 ~" m, `7 b: r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% u3 N) }% i; p+ L" f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 [+ Y; _" D, k0 Q z2 C6 ]
| MCASP_TX_CLKFAIL % a6 ?8 p L2 b7 u
| MCASP_TX_SYNCERROR
$ P: R" }2 i3 i6 p4 k5 Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# N5 d) o8 L G$ e$ g| MCASP_RX_CLKFAIL7 Z/ c0 c- Z/ E# r* ?
| MCASP_RX_SYNCERROR 6 E% h2 P- `# p
| MCASP_RX_OVERRUN);
0 \* t# f& D6 j5 Q} static void I2SDataTxRxActivate(void)
( ~8 a' S9 t% q7 @2 c6 m5 W{. {+ F% p1 d1 _3 I2 s% P
/* Start the clocks */
1 b1 s- l7 Z' {# m! e+ qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! G0 m- v$ r" H7 F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// Z4 g. O4 b. k" R. F1 R) M8 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 I9 S4 R5 u" O' wEDMA3_TRIG_MODE_EVENT);2 s8 p- n, H2 d1 E9 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " A/ u' p* L$ @, O' l+ T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: {7 q8 \" W; T# t/ u1 M6 gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, ]1 j! ~7 d2 u" L4 j2 c/ R- MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- J0 w/ a4 H% X( {1 `* c$ pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; A: ]6 R/ \* k5 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# p# n7 O& ?1 Z( y6 zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* ^: ]% W9 i7 v6 y1 c6 ]" I}
$ x4 {; H' x2 x4 s& e4 A* I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' f9 |. ] x, s& r' r! p% h
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