MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
& q/ m5 w, P( p% @$ ~input mcasp_aclkx,
input axr0,

; M) d! l" H5 J: r( c! Q3 q* k" _9 }3 ^output mcasp_afsr,
output mcasp_ahclkr,
5 @6 H3 X1 ~- m: M/ p% Boutput mcasp_aclkr,
output axr1,
- _% j4 n4 ^/ @  D7 u: Q

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
8 V9 s, ~7 q  {( @) Y1 {8 Hassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

7 m2 I" D# }7 \/ y& H* C- d

static void McASPI2SConfigure(void)
{
9 ?  C1 D  {2 ]3 kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' a) E# ?3 p0 U0 `9 H% D" UMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. f, M- x: z3 Y1 w: w( FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
0 e, N( @* g- E7 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
3 v0 @' n1 S1 U+ H5 c9 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ u6 o, y( y" T: C% R* vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# ~: w; H9 Y( K( X4 U  \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& s) v4 \/ ^- j) ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
7 n! {8 W/ T$ O; wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& B" `: l4 l( E1 f. ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 Y1 t2 W, r; ]! ?, H# }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

$ ~  \. i( |5 o6 A" G8 v$ `$ o: V/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ O, ^) Z1 C  W$ Y. f9 }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# N- F, C1 e: r- H3 SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
8 |; U9 d- ~5 L) F** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
+ @  `% G; a  T$ R# \) P7 D3 V*/
7 ^. ~" N# f2 @& ]( p# Q; wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
4 M' ^, z) e3 ~" W" ]5 X* g** Output - Serializer Tx is connected to the input of the codec
*/
) z) ~% }0 k% \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! z6 H3 @3 \. }8 U  C2 G/ H9 q; }; MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 u6 C" P* h( RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 K9 M2 C5 N- k' ]/ |: r  j* m0 u" c' f| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
: L5 z3 |# g  U) [$ K| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
) n, {" X) g& J3 B% G. L& s% w| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 j2 D! q$ c( V( h| MCASP_RX_CLKFAIL
! O3 B" Z% x0 u$ R2 l7 }| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
1 I7 h* _- k: K' }0 \: |}

static void I2SDataTxRxActivate(void)
{
7 x5 U& L+ `9 c' w% }/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
; B- r8 g# o4 R) i, a# zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% z) Z. r6 S( KEDMA3_TRIG_MODE_EVENT);
6 N3 D, }$ g- T/ ]- O+ pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
* |! |! y- ?. }+ c) [+ QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
8 t) l( A! N: W- `1 q+ D, `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ U# E1 Q$ @, c; Q$ R$ uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 h$ j  e, c$ B/ Z; l7 Q  E}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

9 }9 w2 N6 q9 R7 w: c% k