我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 d" X3 [4 Y7 |) \, ~4 @! |
input mcasp_ahclkx,
& q/ m5 w, P( p% @$ ~input mcasp_aclkx,7 `, M/ q3 l8 x) ^
input axr0,. z! ?; R* J6 Z. l( m
; M) d! l" H5 J: r( c! Q3 q* k" _9 }3 ^output mcasp_afsr,) P+ k& n, q4 l" p8 C
output mcasp_ahclkr,
5 @6 H3 X1 ~- m: M/ p% Boutput mcasp_aclkr,% `& ]6 k$ @/ Z
output axr1,
- _% j4 n4 ^/ @ D7 u: Q assign mcasp_afsr = mcasp_afsx;5 ]* b T% d% K- f- k. J2 o
assign mcasp_aclkr = mcasp_aclkx;
8 V9 s, ~7 q {( @) Y1 {8 Hassign mcasp_ahclkr = mcasp_ahclkx;7 c* A& h4 \, z4 T
assign axr1 = axr0; - v. _3 Z( q [9 \9 g
9 V& Z# |* V$ D( Z% @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 m2 I" D# }7 \/ y& H* C- dstatic void McASPI2SConfigure(void)9 q* E/ t7 P/ R5 X0 V
{
9 ? C1 D {2 ]3 kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' a) E# ?3 p0 U0 `9 H% D" UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* x* a( g+ T7 J2 g O5 c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. f, M- x: z3 Y1 w: w( FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 e, N( @* g- E7 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 M# i/ {/ e# W' l U9 ]: I3 {
MCASP_RX_MODE_DMA);
3 v0 @' n1 S1 U+ H5 c9 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 C; M) Z+ Y" [0 Y) v1 D, j$ v: m* ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ u6 o, y( y" T: C% R* vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # ~7 r. Z# F$ F: ~& \$ f" V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# ~: w; H9 Y( K( X4 U \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& s) v4 \/ ^- j) ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 n! {8 W/ T$ O; wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& B" `: l4 l( E1 f. ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / J1 Z: H2 p) E% ^* P. M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 {. z. N4 |( m b. `
0x00, 0xFF); /* configure the clock for transmitter */6 s( J1 m8 k4 c% L" q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% r% c) r. H! P X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 Y1 t2 W, r; ]! ?, H# }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& Y: F2 ]4 p+ e8 [8 O' B: b$ [4 g' r
0x00, 0xFF);, A6 z& f: \* Z7 N/ u. }1 q
$ ~ \. i( |5 o6 A" G8 v$ `$ o: V/* Enable synchronization of RX and TX sections */ . P5 A. e z% V }$ m; _; |& w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ O, ^) Z1 C W$ Y. f9 }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# N- F, C1 e: r- H3 SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 |; U9 d- ~5 L) F** Set the serializers, Currently only one serializer is set as+ H1 b! I, j5 R# p8 p
** transmitter and one serializer as receiver.
+ @ `% G; a T$ R# \) P7 D3 V*/
7 ^. ~" N# f2 @& ]( p# Q; wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 g3 i6 ]+ e0 j6 d& Z3 B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) k6 B9 l. j5 G" B" y
** Configure the McASP pins ' i9 _8 p' F) j3 a% s: n+ S
** Input - Frame Sync, Clock and Serializer Rx
4 M' ^, z) e3 ~" W" ]5 X* g** Output - Serializer Tx is connected to the input of the codec ' `8 i8 V0 P' r, D6 ^) `5 S
*/
) z) ~% }0 k% \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! z6 H3 @3 \. }8 U C2 G/ H9 q; }; MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 u6 C" P* h( RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 K9 M2 C5 N- k' ]/ |: r j* m0 u" c' f| MCASP_PIN_ACLKX+ ^' U X% q# y: i
| MCASP_PIN_AHCLKX
: L5 z3 |# g U) [$ K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ B( _+ j2 w9 U$ l! m' @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 z3 Y* Y( V; o N* r" T
| MCASP_TX_CLKFAIL
) n, {" X) g& J3 B% G. L& s% w| MCASP_TX_SYNCERROR( v; k/ M' B0 h% c7 @* @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 j2 D! q$ c( V( h| MCASP_RX_CLKFAIL
! O3 B" Z% x0 u$ R2 l7 }| MCASP_RX_SYNCERROR - m+ s0 a6 O) ^6 P$ s
| MCASP_RX_OVERRUN);
1 I7 h* _- k: K' }0 \: |} static void I2SDataTxRxActivate(void)- N2 v$ {: ?+ r$ `" u6 }( k
{
7 x5 U& L+ `9 c' w% }/* Start the clocks */! D" f" O$ d! e) Q" D4 b- c! [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 D+ {2 c- x! t' V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; B- r8 g# o4 R) i, a# zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% z) Z. r6 S( KEDMA3_TRIG_MODE_EVENT);
6 N3 D, }$ g- T/ ]- O+ pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' z# ?' |1 u5 a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* |! |! y- ?. }+ c) [+ QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- N0 P: R1 J- c6 d) G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. B4 X: X8 b4 k- ]! [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 t) l( A! N: W- `1 q+ D, `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ U# E1 Q$ @, c; Q$ R$ uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 h$ j e, c$ B/ Z; l7 Q E} * G' b! j/ M9 ^9 w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
9 }9 w2 N6 q9 R7 w: c% k |