我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% N, Y8 V9 w @( w# Sinput mcasp_ahclkx,* O( n! b% I: e7 y' k
input mcasp_aclkx,, R: O2 @$ I- `: ~8 k% G4 G, q
input axr0,
* ]) p ~! K+ S& E
- f) k; y1 L: Z9 }& {output mcasp_afsr,# M8 m# z: C% {6 @
output mcasp_ahclkr,# M2 d c; d8 Z" d1 g* s
output mcasp_aclkr,
) V* `! K3 r C! }' Goutput axr1,! T& X6 W' C( o; P2 L
assign mcasp_afsr = mcasp_afsx;7 S! n& Z4 q0 y
assign mcasp_aclkr = mcasp_aclkx;; q! M' ` ]4 P6 Y$ X
assign mcasp_ahclkr = mcasp_ahclkx;
4 G6 n4 a( ?4 C' h8 R7 J- oassign axr1 = axr0;
3 y& p2 s: L1 e- l5 ^4 W
. B$ h9 n8 u/ R# e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( G7 ^6 ~4 b) g& d
static void McASPI2SConfigure(void)
4 G- w" c, ], y) a! c: h0 T{' A3 e5 c [* ~7 z g) |8 Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* H8 P* N( K; ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* A' E& u4 M0 {9 GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( f% W1 F3 }0 g: ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ R' J6 B( D* W/ y3 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 T$ ^% s5 L' I _2 z9 U9 X& H" v- zMCASP_RX_MODE_DMA);
& b& f# F/ p3 X: f( B5 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- N$ ?" B$ i0 e: i. DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 a* h# P# D+ U BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) [' a9 j% r9 p( V$ ^0 B" TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
D+ _: j2 J) ?( a. _2 l qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * e! ?5 O' I/ _$ c5 ~/ H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 |# V+ d9 w$ b+ tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 T. R8 n% D7 ^' q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , \( H! y, f% M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 R6 h* `* ?7 y7 Y0x00, 0xFF); /* configure the clock for transmitter */ P, }3 m8 E" ~! `1 ~* Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* Z2 k Z0 ?. X, F0 P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; [/ ~+ g0 x; \ V1 ^; J3 m+ H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ T1 b0 q0 C4 `, ^1 n
0x00, 0xFF);' w3 W2 S6 [8 v9 ^/ }1 I& G' J! H4 \
/ p3 G# K. e- V' f
/* Enable synchronization of RX and TX sections */
1 V4 x- @$ s7 [6 l/ S, PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, S) B$ U9 S# }8 r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 f# V# a4 V* h, {6 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( m, ] C9 X+ p6 y7 Z
** Set the serializers, Currently only one serializer is set as
: e6 V; c" Z' h3 o0 b- S6 e6 T1 t6 t** transmitter and one serializer as receiver.% x$ W# k& ~; r7 h
*/8 f1 V: u. i8 v" [, \: u4 J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; Q8 a- ~8 N! X% e! H6 X) J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ E8 u% k: K( A& e5 _1 M# w- _ g! y6 V+ ?6 ^** Configure the McASP pins " Z2 R/ O4 _$ T# Y' z
** Input - Frame Sync, Clock and Serializer Rx" [& U% S7 U! b& ?! Z* A
** Output - Serializer Tx is connected to the input of the codec
6 I( c" H/ g. Q6 ~. T*/% f+ a5 ]+ c; j8 b" k u* r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); n) I( ^0 [; _; v) `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 U) m+ s+ _4 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ H) t% I4 B1 c$ q- O| MCASP_PIN_ACLKX# s& ^. _/ L% n8 y8 X
| MCASP_PIN_AHCLKX0 Z1 `3 Y( F2 G ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 A6 t" P$ K. o- @# }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' D% I U q; e1 E1 l: i7 [' W
| MCASP_TX_CLKFAIL
1 v2 I! N; t% U| MCASP_TX_SYNCERROR6 [+ u0 |7 A+ I: b- y+ N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 U6 {4 c! `8 g+ U| MCASP_RX_CLKFAIL1 ^; f9 M. x! C; Z' g1 P
| MCASP_RX_SYNCERROR 7 j( ^+ u; H7 A% l3 L+ c
| MCASP_RX_OVERRUN);. X9 N( a) U2 m' Z3 I
} static void I2SDataTxRxActivate(void)8 @4 e) m$ Y8 p6 t! Y0 f+ }
{
! ~( V0 A3 V N/* Start the clocks */
- s$ \' \7 j8 h3 V2 w$ fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, [6 ^7 E1 s) b: k5 C4 JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 j7 Y5 C7 q- \: y S: H: OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 R. J/ W- M w9 p
EDMA3_TRIG_MODE_EVENT);1 j* t+ v: @* F: A6 X2 P+ H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 i/ k+ I6 z$ O5 D+ m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 T- N/ T. w s/ L9 H, _0 I2 v1 {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ F1 J% I' c: x- l& v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; ?1 |) }. @2 i6 |: F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 ~1 W. g3 b- I" ^0 {1 lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, s4 Z: X+ s* d$ TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% k/ ]3 t. s. B, s' B}
: G W% n* k" m7 D, z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # \4 f" P$ O$ Q' i( Z
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