MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
* _+ g) r3 y5 Yinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
" m+ H( ~2 F6 R5 j
output mcasp_afsr,
. F& Y) j# q2 E9 T5 r- S  n; V' U  Noutput mcasp_ahclkr,
output mcasp_aclkr,
, N8 u- h- p. Poutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

" C; z/ M) ]6 P2 Q9 q) x7 }: B6 y

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
9 R1 L$ h1 U0 r0 o( ?5 ^( O  ~6 [{
/ Z  K1 K0 U3 O% v! f! rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% ]0 `2 Q* v" C' gMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
8 a9 Y: \( J. u2 m/ ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
- w1 E! c: `3 A  n" q  ?5 j# O- EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
2 H! Y  ~  A) W& v3 MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: m6 C/ @. H' B; OMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) h. ?- d6 Y8 c9 V% {1 LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# x6 ]  D; ], P6 f8 H+ BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ a' C7 ~, _$ e2 ^+ ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, |- ~) `3 W* Y1 t" B  |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
0 \# L- Z! h0 f2 q+ K$ B1 Q& ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 U4 c. T; J/ H, A$ ^! \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& y! m" w% {2 ]2 h9 @( Z) @+ B5 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
( R2 U  _* a2 {0 |$ Z: _! @) JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ N) O8 R: o: I5 L4 XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) e$ k& y; P5 b1 D1 @0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
6 F( y1 C- T& A% B: o# S% ^/ `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: z! ?. A/ H/ @1 `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
( S/ _: I5 P. x! `& k+ h** Set the serializers, Currently only one serializer is set as
$ g, q9 S5 v: P1 }** transmitter and one serializer as receiver.
0 D" h# W  [, Z/ P# {1 `*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 ]) ]( }1 j( t9 ?5 l  LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
, x' y" G* Z4 Z; P" R$ R, r** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
9 X. E# T( O# E1 l5 ]! z; }2 i** Output - Serializer Tx is connected to the input of the codec
*/
) E) f) L- a. ]4 \: k4 wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; x, y. f# L) q9 O" @| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
- G- d% L" z: C1 A| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
" |& v$ L7 U; B0 A5 I. a6 q| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 o* i! ~' Q& C8 Q| MCASP_RX_CLKFAIL
; Z2 y& j; |( n3 u% z| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
  r( A& z7 B2 Z5 A  P& m5 p{
/* Start the clocks */
) Y7 F( S1 V7 k( rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 A6 K( E1 C1 Y2 P5 ~EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
4 g, u( r! e: n% NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- f3 s/ t/ k8 X, wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
2 T2 J* C, R/ g" {5 uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

4 z/ X' O, z! q; S( V1 j: @# P

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

5 \5 l8 W4 w' B$ m8 v