我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 e3 k" b% ?6 S; Z. n, o7 X! \& Xinput mcasp_ahclkx,
6 b5 A/ M# ] ]* I- uinput mcasp_aclkx,
6 U) c! y7 Y3 O; l/ a% L" Xinput axr0,& c7 e+ [8 N% N7 M2 r7 y
4 Y( l+ R5 t0 F0 Qoutput mcasp_afsr,1 _; z7 f# V- [
output mcasp_ahclkr,
5 E* ^& R& k1 woutput mcasp_aclkr,9 H2 h8 A6 N; V; T7 T) e5 r0 f
output axr1,
( l3 U. E- Y) p1 |% O% G3 q assign mcasp_afsr = mcasp_afsx;7 k( v2 f8 I9 L7 f) Y
assign mcasp_aclkr = mcasp_aclkx;5 I: H" Y4 p7 O9 l: B
assign mcasp_ahclkr = mcasp_ahclkx;7 E3 [! h. K" b& [ H2 }. \; a- M
assign axr1 = axr0;
% n: k8 L" j! J, u- x" B7 X) u; E8 c9 @9 y& _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % g2 e7 T& a; _4 y! l
static void McASPI2SConfigure(void)* w) h: ]& B( C) T2 y8 E1 S! `
{
! C! ~6 s2 C2 A- y# xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 B; c1 Y1 @9 c9 a" ^1 |3 \+ a) `6 rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: j7 _) N7 O0 q, rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 Q! r' Z L0 C, e" @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! G$ X" H, w o k! m4 a' a" TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* ]9 {1 K7 `- X- C; kMCASP_RX_MODE_DMA);" {4 K3 B' `, d, G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" h) r8 x% [. r1 m; [9 B+ H# ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# d1 }7 p( i6 s: Z) JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 v: i0 Z2 O. m4 J9 g7 _9 t: O U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" A/ x5 N& A. g! oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! j5 |% ~+ O. x) |7 z P, L/ vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 K% A; ~# O. I/ B) MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ i% d& z6 u, Y0 q6 j( hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! |; I5 `/ P- J3 U7 N8 C( A, ], h+ AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: {' L$ I3 Q1 n+ q j& J
0x00, 0xFF); /* configure the clock for transmitter */: j% Z: a) C' k$ P+ l# }9 ?5 \) @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 C+ X+ D0 P9 j0 P1 k* m; S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - j5 M" m/ W2 U: S0 ~& f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% c/ t; k3 ]1 @ x1 c0x00, 0xFF);! |; \6 l$ o7 X
$ l/ d! g1 g) E! v
/* Enable synchronization of RX and TX sections */ ' J/ g+ H3 ^, c+ k6 D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 S0 b. w1 z4 Z- GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" H, `8 i% E. S& X4 l" d/ H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, z" O! d4 B3 u6 _8 Q
** Set the serializers, Currently only one serializer is set as
; B: r; Q. C+ X6 G+ s7 X** transmitter and one serializer as receiver.+ }1 Q& o: U# G) z( k0 z8 B+ d2 O
*/ F' |% K3 W7 w y1 P4 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 C8 {2 n" W- W! ]9 \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ d I/ C }4 A* u
** Configure the McASP pins " `0 U) p) Q% d& d* \7 O) _
** Input - Frame Sync, Clock and Serializer Rx
/ U6 Y& `9 }! K* W** Output - Serializer Tx is connected to the input of the codec
' y; h, a4 y) I4 C*/% ?$ k8 J: ^6 H& c+ T# J, X* ^5 g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, ]# f) L0 A/ U! w0 i% [( {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! m- P% G, o+ ?/ D) u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ `! X1 T. y0 W$ ]5 U
| MCASP_PIN_ACLKX: b5 y' d% L# d$ i1 ^
| MCASP_PIN_AHCLKX A3 ]% a; A( ^3 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ~) L! x, _, N* X/ K- xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR X- V: q+ s# D/ D9 F; U
| MCASP_TX_CLKFAIL 0 X8 ]6 _: Q5 z( k( W8 [1 L1 @
| MCASP_TX_SYNCERROR
' S* y2 h1 |7 m6 ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& ~3 n4 I9 r8 z4 Y2 Y| MCASP_RX_CLKFAIL/ a4 p9 ^* f0 r
| MCASP_RX_SYNCERROR * }; S4 t$ D% ^7 \8 ^) g
| MCASP_RX_OVERRUN);
% n& o2 F& o0 |0 I8 o} static void I2SDataTxRxActivate(void)$ f) X+ e& i5 k$ S0 s. U
{7 L, {! V* {4 b5 D
/* Start the clocks */ l5 j* Q1 {3 ~) I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 F# g, Q+ ? `. t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, R2 X: s; j4 O2 q8 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ p& ^8 U+ a. c
EDMA3_TRIG_MODE_EVENT);0 i1 K+ T' B& n* q: g m( P+ d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% ]. p3 ?0 c/ }0 t8 H2 YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 [! I7 ?7 s: Z" f" o$ O3 H, N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) |* f* Z( B: K9 A! b- A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& T! ~. q2 W7 b+ K M) N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 k. L2 w5 X7 y2 z' E$ X9 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: x) Q- k/ i; x r% u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- f, E( A$ c' y @: [6 y}
# L) r0 o! v2 u* J9 N: L& O0 V. k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; w V% W: b) Q/ ~+ ?4 `
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