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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' a6 n/ p/ y) c. e) q+ n$ _3 p
input mcasp_ahclkx,
, A ?+ Y3 L: winput mcasp_aclkx,
9 t; @) Z: l% e& y7 I" Yinput axr0,
% |8 a- F! K& `( ~% |8 c; H
- l3 T* V: `- H8 f$ V9 `output mcasp_afsr,1 ], s. | ]1 V2 c+ U
output mcasp_ahclkr,
6 J: R( \3 q/ V3 P# aoutput mcasp_aclkr,1 J. G' G+ ]7 s; W$ D) S/ G
output axr1,- U: x) q; p) q+ T) k
assign mcasp_afsr = mcasp_afsx;
4 L# z b) m. f) Q* ?9 Cassign mcasp_aclkr = mcasp_aclkx;6 m0 c0 x; N) ^! F0 j+ i/ p
assign mcasp_ahclkr = mcasp_ahclkx;* [/ O1 O) j4 J7 N( ]/ c+ ~* m+ Z
assign axr1 = axr0;
/ C' l% Y3 \% q& C. y! K2 g; A5 x6 |0 y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 x* r% z# W4 F+ S; {5 nstatic void McASPI2SConfigure(void)6 N; J( h6 u; ?+ v
{
& n4 `/ {" [( B7 S( R: KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 h) C' J; b2 x9 q* l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ g) {: z; @) I" x, u& A( F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' B" T0 c7 s8 q0 E: WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' X4 g' H% A, e, q+ d+ d5 bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) i1 l" E h, M6 W
MCASP_RX_MODE_DMA);( ]2 p. o* J; R! h5 b( E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( V" u& t7 B: F- ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 Z5 z2 v/ P9 s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 t3 X# l/ v0 n3 u9 C" I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; t( c/ u7 F8 I" FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : `$ q! M' D" I B0 w$ f [ O! I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; ~: X* o6 Q* b7 F: V7 O0 I" y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. q" n* q7 [4 ~' F8 P2 H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # g/ }( k$ E2 S$ U7 L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 g8 o r# M" Z0 U- @6 p( j
0x00, 0xFF); /* configure the clock for transmitter */
. ^6 `/ U. N- U/ S9 f! GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 q4 s* x5 f3 C7 R/ b: |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 |' ~2 P) S) N% u) S& z- ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, \% J9 e% y- H8 u+ m$ t% z" {' G( s
0x00, 0xFF);
2 i7 M- `: k6 a6 k4 I* Z; y: \5 |& P5 t. B" y A) l
/* Enable synchronization of RX and TX sections */
6 s- `: y, Q* DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ K5 @* s- e5 @8 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, X, f& k2 D U% X# H& T5 I7 r6 j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* I2 F# k- S& E% O, `8 _
** Set the serializers, Currently only one serializer is set as( H/ f, B- W0 b n) k( U/ @ x
** transmitter and one serializer as receiver.+ L# `: g4 j3 V7 n% Y* b) p
*/# q( E0 Y6 _. Q) d0 B7 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 N$ l# _1 M+ M3 N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# h" {3 O6 @" z** Configure the McASP pins
7 t* d5 P% S4 F% B# W* A** Input - Frame Sync, Clock and Serializer Rx) k2 |- `, f6 E* n$ O+ Y
** Output - Serializer Tx is connected to the input of the codec
4 q9 s5 a& Y; o' f" g*/6 l; C8 H1 m; `7 k+ @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* l" P* Z" s/ r2 z& L) tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; ]. w: [) P" W% e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- L6 z+ X* Q. C$ l# t
| MCASP_PIN_ACLKX
) Y3 u; k4 b$ D. w( i| MCASP_PIN_AHCLKX
# z8 B& ]' q8 W4 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- _ ^6 ~" t1 h$ OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * e+ [, x' l; I7 f7 ]; F9 W4 F: M- a
| MCASP_TX_CLKFAIL 4 M1 y: C3 }! d g
| MCASP_TX_SYNCERROR3 \9 }2 W+ A/ w9 X0 [8 z4 \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* T3 q3 ?$ A" K| MCASP_RX_CLKFAIL; j; P w% ], B, r; g# u
| MCASP_RX_SYNCERROR
" s1 d/ Y) j/ w7 j1 Y; g; [% W| MCASP_RX_OVERRUN);
4 o) `& P( j" ^, z# s; N; ?5 s* U} static void I2SDataTxRxActivate(void)
4 W$ @# [" \: [0 y4 o{4 w5 p4 I( d: R7 X
/* Start the clocks */
7 t5 g& z9 ~0 \, cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 b1 s0 y7 E' C" f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' d1 d2 G* }. J7 S! K }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 ^0 W+ T# R' R0 k7 FEDMA3_TRIG_MODE_EVENT);
5 h' I; E) c3 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 c7 ^0 k& f1 z$ | X/ |% x' c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
X7 z! J9 K0 a. B& p3 Z! W4 L2 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# Z4 \7 p& b9 t. b4 a* X& s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& u; V q+ R/ s! m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# ~7 m' C# g0 I: D+ M/ C# k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 j, F( g5 L8 y: }- k' D9 RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ j* N$ u, F" W) [
} * l4 S4 X. v k8 J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ F% T% u' w6 f. X2 C2 x0 S. Y+ n
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