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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
s, s$ G- q7 ]5 W* Finput mcasp_ahclkx,
8 x. v( a! w# ]! G: ^4 Pinput mcasp_aclkx,2 r) O% r. Z: I; e9 I$ G5 L
input axr0,
( j+ G" O! p u D7 O: |. R; P
" N% w; Q- U& f' y' U! K# ?* Q/ Ooutput mcasp_afsr,) I+ H2 V7 e8 c I9 h2 W
output mcasp_ahclkr,
; z3 ^" z% c% R k& K4 Z2 Voutput mcasp_aclkr,6 a9 @, {9 c9 m/ K- c
output axr1,
. C7 \ z# _1 @2 e& P8 } assign mcasp_afsr = mcasp_afsx;
! V6 L( {0 H, J& R% Passign mcasp_aclkr = mcasp_aclkx;( h% T1 V8 K* p
assign mcasp_ahclkr = mcasp_ahclkx;! E6 S+ |5 M8 K# ]$ M
assign axr1 = axr0; 6 c3 m! u# f0 m. y5 l
+ U& m8 U5 K6 e( l% f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 F8 M2 i4 |1 k, ~3 Astatic void McASPI2SConfigure(void)# b, `; m2 T. X
{
0 i7 y/ @5 Q/ r/ ~# `" sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ A1 I5 q; d, w T, VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 M6 ]4 E& [* M+ v, _! \( n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% r3 X5 R& {5 D4 T, g# L9 X1 AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 s; r. G# P9 g/ i* E1 H2 K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: R ^3 h7 e: h) dMCASP_RX_MODE_DMA);+ y3 w" C% @! k5 ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) _ C& L* n, P. ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 M5 }* e4 \1 t |6 J. L0 u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * j1 ~) m, t( p* ]" Q6 ]# w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 U; J( ?4 P6 V+ B# n3 ^5 t$ `& r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: E, ]0 q# D6 V2 N. z1 r3 gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, ^6 F0 `) I8 m8 \- \# g; CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 D( k& W5 t& {6 Z! T3 O$ H6 ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , p9 L' T* t' @$ ?/ k5 k# T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. R/ M! g3 V7 D- X l0x00, 0xFF); /* configure the clock for transmitter */
( D ~! O `2 {8 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" Q' Y; {$ q( p/ B% w& U' `- W" `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 S. U. L5 H3 PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 ]4 g8 ^* H1 I0 V' I8 u. [
0x00, 0xFF);
) w3 G2 R4 I! Q" P* x( o8 k% M2 f0 V" ^* E b6 n
/* Enable synchronization of RX and TX sections */ - g" \: M4 S; b9 Q! [' P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( ^1 C" W& V* z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ w! y& A2 k4 W8 P x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' D% ]6 ^* `4 s
** Set the serializers, Currently only one serializer is set as3 W9 V0 x. ?0 Y/ m( u" m/ F3 m
** transmitter and one serializer as receiver.) f+ | Q9 c$ i, D
*/
+ d( G9 _' [4 t) t3 U K5 x0 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. S- ^, _: Z! p* ]& M, O! ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 K3 w2 n3 I" m8 F, J" M/ Y5 J** Configure the McASP pins / c6 {* z; g: b# M/ j
** Input - Frame Sync, Clock and Serializer Rx
8 m# w' o3 C6 Q$ S; K" K9 L @+ u' v** Output - Serializer Tx is connected to the input of the codec
& q) p% D9 ]2 E0 N*/* V( Z3 h& {) p1 P- E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. |0 E, |9 ?: w8 v3 HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 {/ b4 f" q0 r Y( `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' t+ q7 O1 T! V' v$ r5 Y
| MCASP_PIN_ACLKX( b& u7 v, a/ A) A* S' A7 e3 W
| MCASP_PIN_AHCLKX
" G |4 K2 g% }' A2 T' \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 `( n8 `' F9 R+ VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& H4 |$ w5 y4 t/ I$ p' i' l| MCASP_TX_CLKFAIL
$ g4 x3 e9 N; R" x| MCASP_TX_SYNCERROR" x8 j4 d. A d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' m8 I, L* V! f# T+ I0 G( v5 h| MCASP_RX_CLKFAIL
0 S( V( X( A" A4 L! \, L| MCASP_RX_SYNCERROR + @6 e- }/ i K& l
| MCASP_RX_OVERRUN);* q& Q5 T, @9 G: T$ t- f; p' |
} static void I2SDataTxRxActivate(void)1 S8 E* L" p, o# {. L6 @
{* k* ~8 O0 n& D: y7 O# i1 x
/* Start the clocks */
8 x7 T7 e* z4 L% GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 r: j/ {/ Z6 Y8 xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ B/ G3 ^2 q% ~: U! Z {0 {8 b% m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: i7 X. K7 t$ }7 {EDMA3_TRIG_MODE_EVENT);
# A% r/ U# c/ L" H, XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 E, I @- F( q$ f$ [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: ^6 D) d: K, w8 g1 O( B* C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& B6 q( l" Z O" D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, a/ u: ^* r& U; [3 p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ u/ r* }+ E9 A! L5 l4 R. }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! Q% U0 E- k0 ^4 m _+ S9 |+ w6 o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 S- D+ a2 z; u& h
} 3 K6 s: q# n, t# _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 s* T3 u* f# ^6 _* l# y
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