MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
- f, C1 R1 _1 X+ S7 R& x* Y0 Sinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
+ d9 T9 P5 _& i
) Y$ b$ ^4 ]% Z' l* j4 g& Routput mcasp_afsr,
+ b% e' b0 ?- p, [5 Zoutput mcasp_ahclkr,
7 b( @* i. l* a- |3 M( doutput mcasp_aclkr,
- O$ b: r, b  k5 m7 X8 @output axr1,
7 P( H( I8 E1 G' v) ~+ \& B

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
. D3 G; ?& \! ?assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

2 f* k. I6 W( V; D

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

4 j; n) K" h' [2 y

static void McASPI2SConfigure(void)
. S; Y8 S& s) t$ |0 _- d& O{
. m: [1 ^! L- h: T9 ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
7 Q: g. w% h# a: H  sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
* g: g: h( a& T) d& c& k/ AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 o8 d: z: h% g/ q1 fMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 \, h  `- G9 O  @1 TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
, A# {/ V9 {6 F. C( a4 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- E2 \& }/ W8 p0 H& ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 G5 }, A" `+ p/ U- K  B5 Q+ {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
6 H  v5 D* ~3 J# w. hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
+ F! q0 x9 L1 ^  d4 e
/* Enable synchronization of RX and TX sections */
# G& A2 d7 R  A& t5 j; oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- }# Q, |! d6 P, M8 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
1 t7 m  ~% y" A& |. V/ d) D** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
1 g9 w2 r6 z; f0 k*/
. \( J( R* E8 w+ bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
! a6 L9 x6 _8 i8 @- D$ m** Configure the McASP pins
- i5 `/ S; X- b9 }& a6 Z** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
" F* v/ n  A" y( P+ z$ Z*/
! P/ W! v- |0 M( Z* @: l! gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% I# R; h4 z1 K4 s! SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" `- o- ~: E3 }" B* X| MCASP_PIN_ACLKX
* ]  O& a: }$ Z4 T- a/ N) p+ Y| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% a5 c+ ~5 P$ M# M& h2 s7 U  ^| MCASP_TX_CLKFAIL
  e; \: r& m) C) S/ {) ]7 Y+ m| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 g( k/ i3 H. Z; E' T5 j| MCASP_RX_CLKFAIL
/ _7 y  ^& N4 b0 H/ M| MCASP_RX_SYNCERROR
4 h% C/ o" a& Q$ `; Y( `. j: t" Z| MCASP_RX_OVERRUN);
6 }, `; O) {- Y" ~. g}

static void I2SDataTxRxActivate(void)
& V% q: [5 n, g* i{
, F5 {( r- a; B4 R$ a0 R, Q/ Y/* Start the clocks */
' p- u% _5 w' o( e& JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- u% I* Q4 t# B, i6 v1 ~: dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
( ?0 ~8 U5 |8 Z: \! }/ i  wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 R; t6 b0 {. [6 K3 dEDMA3_TRIG_MODE_EVENT);
4 t- u& l- k. T6 W$ \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
% `- w5 i0 r! e# WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 y# l4 h6 T2 e1 U2 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: h. g8 J$ \! ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 g- d( d3 m# x; S- |) m7 S}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.