|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 ?+ p* H9 [' v
input mcasp_ahclkx,$ L" @* t' n- O7 i" M: ^
input mcasp_aclkx,
. F4 v7 C% I" f8 u+ Tinput axr0,
2 [) C T$ J5 G8 b$ a$ \/ J( {+ A( s2 A8 q; u8 g1 I. U
output mcasp_afsr,
" W) E7 l! t L y4 B& ~output mcasp_ahclkr,
8 f, P5 T- w8 o6 U C& Voutput mcasp_aclkr,7 B( H" n3 r5 n& V! v0 h1 x
output axr1,. x0 x- Q0 \1 |+ }5 O
assign mcasp_afsr = mcasp_afsx;1 z, ?" L, F$ m4 i" P
assign mcasp_aclkr = mcasp_aclkx;" N' v+ G+ g5 u" P0 k/ o! [) g
assign mcasp_ahclkr = mcasp_ahclkx;
+ O3 y) L- `- n0 Rassign axr1 = axr0; 7 S+ H9 ^3 U( R# D
) e/ s; H! D, g/ Z e! x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 ^% F+ r" J# y1 G/ X4 M% j @" gstatic void McASPI2SConfigure(void)# B3 c, {; M$ O5 t Z! V( [
{
C# F( e( p7 b7 T; vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 t$ D" q5 a5 j' B( A2 P1 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( D; ^+ I+ p- G; I0 A; H9 c: g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; f1 N* b! E w3 _. A" f: wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 y& p) H' q2 \2 T. z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 b( ~* [, [& fMCASP_RX_MODE_DMA);( G3 J T) w& l6 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; w" m$ `) p C9 R% }& y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ L: Q p9 [6 _5 x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- M1 K* n/ Q, t+ ^$ j2 vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' v5 g1 O- Q6 _+ L. ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 }$ N) P' g& \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" Q# t% t+ U$ Q; ^: E6 {- a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& D, m1 N j/ W4 H: N" o/ |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # c. L# e+ H2 M9 c9 t/ `( M2 k& e. f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' C L6 q0 l4 G0 e/ o0x00, 0xFF); /* configure the clock for transmitter */
0 }6 t- c7 R0 c8 m- v6 U: tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- P, M, Y( O( G- o( q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) N! H9 d& r- a! z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, ^; v/ b- t2 h! q/ f6 F
0x00, 0xFF);
* T9 g; R; H: t; g( R: S4 X
6 A9 i( [5 R' P& y ~- b/* Enable synchronization of RX and TX sections */ # B6 `8 P7 j+ T, i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% x4 F4 l3 X& g5 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* ?1 h2 r/ `( A- d# O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 V) {. H! L0 i6 n! B% o3 G3 F
** Set the serializers, Currently only one serializer is set as% C2 J- d+ h& U& N4 y5 N
** transmitter and one serializer as receiver.
5 S2 a6 J' S1 w. f# `9 C*/
4 e5 f/ d. c( s+ d9 A1 pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' t6 Q! ^0 R7 g6 @! `3 RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 J1 ~& ?4 k2 X! A9 x% ]- l. {* F
** Configure the McASP pins
9 s" @3 ^- T2 A4 ~5 `* D; x* e3 ?& d** Input - Frame Sync, Clock and Serializer Rx9 {" c! x& H. W! m0 G
** Output - Serializer Tx is connected to the input of the codec ! j/ N& H* ?/ N0 v8 ?; b. O: p2 }! l" |
*/2 j2 o7 m9 g; m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 k" j3 u+ Y' H5 y3 }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 x4 t$ b. V/ L, |1 @- a& {# D+ a6 j C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 }; H* M4 v+ ?" ~( w
| MCASP_PIN_ACLKX
% n+ |( Y4 p6 E. j8 c! U3 l| MCASP_PIN_AHCLKX7 ]( h, @! X, O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ Y, z( X6 _8 g9 q8 ?+ LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ y6 L; M: I' A( j* D| MCASP_TX_CLKFAIL
+ |0 I( V7 \, q M7 }+ g- e' B9 c| MCASP_TX_SYNCERROR
( f- _0 l- |- s5 f* U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) W: p& J2 x3 G* d+ Q5 B& K
| MCASP_RX_CLKFAIL* p) F' z0 Q0 e$ B
| MCASP_RX_SYNCERROR
H! o% y* d7 y! t5 g! D| MCASP_RX_OVERRUN);
2 @! v4 B9 i: p} static void I2SDataTxRxActivate(void)
9 ?( I# c; `+ {3 o- M{
2 G& O' R. d( C* D3 C/* Start the clocks */
4 }/ Y; v( F7 [' bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# ^; t* L" Y4 N4 p/ c& {5 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" f% g( q+ y+ Z: w) u5 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' M3 O# a/ d) Q+ EEDMA3_TRIG_MODE_EVENT);
. K- D% @8 L9 ^8 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 V4 r/ m: Q2 d+ r w; EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% {% i# ]. U4 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# H) `. W, w$ }" ]* E6 P% B' RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" w+ @' ]; R1 a6 s- o& hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 }' U1 k7 V' x3 ?0 fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; K5 D* B' [7 m" h% p- T4 p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 t: y+ `) W( A2 [}
/ P9 c5 G! D6 ]( P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
4 N! r- v, ]9 ]/ Y/ _8 z: l |