MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
/ H2 w3 n* M; w) p: Rinput mcasp_aclkx,
- h$ U; t2 q3 E" ?. y! |6 yinput axr0,
/ t2 e5 u; G3 n8 v- {
1 @- s# D# G8 k5 w& Boutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
9 N2 Z  W5 ]9 Z  x; r9 p) voutput axr1,
' t9 e, m' M9 [' ~; `

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
9 Q' a, Y* y# t/ H/ z; lassign mcasp_ahclkr = mcasp_ahclkx;
0 k( n  u$ q. c7 hassign axr1 = axr0;

& \0 X9 m) @  z# ?/ N& Z0 S4 j1 s

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

( o, W% N0 M" p7 D7 ?  N

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 W1 a  z6 ]) x% xMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) k/ A5 j7 V  s; N; Q8 G# l2 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
6 N" T$ x. O" D& p. q5 EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* Q: @/ [1 T7 Z  c0 g5 o. aMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, x4 L( I+ \  a$ ]# uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
1 w  A) n! \! Z4 D: U2 B; QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 u, O. ]3 _, v9 r, c: ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, W1 g. J/ n+ h4 N+ vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, q( N, T1 ], GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ \- z& r6 d2 I5 G2 r- n! ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

  V6 `% }2 E1 Y' P! S) H/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& _% x: x* Z# |/ }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
  E( G6 `! t! {4 P  ^0 f** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
# e7 |; \( I4 H# |6 a( b) l4 L* QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) J( U2 Y4 ~, y3 r8 zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
9 W5 \$ @  s8 A5 L& k8 k- U** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
8 I$ O) v& k1 X0 y6 _3 y* k/ |** Output - Serializer Tx is connected to the input of the codec
- M9 }9 ]' J$ Y8 [*/
& K3 K! {6 C8 ~/ w  fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ o% R5 v2 w8 d/ `; {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ V( u8 ^/ z( f1 SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 P" r5 o! M0 _. n7 Q) M| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
+ {  s2 y% u  p; f( V) jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 ?7 K" A$ |. r1 ]  X! k6 o/ S- r| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
3 s9 Y0 X! C2 W3 T4 W| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
& M( x# O! U. g2 [# ^/ _| MCASP_RX_OVERRUN);
) E# v- a) C' p5 I& ]8 O9 x  |}

static void I2SDataTxRxActivate(void)
{
7 a& X8 N7 ?. C/ |1 U/* Start the clocks */
' s3 Q* W) t% |- UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
6 e. v$ u. e' M& x1 t" Q2 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* ^# h% ?$ F% W4 a) _) [2 ]* lEDMA3_TRIG_MODE_EVENT);
$ m, |6 c) o- s$ f7 @- ]& {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! k8 G0 d+ \8 r5 B: D6 sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

9 U, w! j% E# G0 ^( _7 [" m