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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. F9 S2 B8 Q/ `4 B
input mcasp_ahclkx,) v3 ^1 S% ]" G v5 {3 d( G2 p1 K
input mcasp_aclkx,, p; O! n+ B/ D2 d4 C9 Y- {3 L: l1 Z
input axr0,
7 f" x6 q1 v) F1 O; Z U. X8 ]! u; h5 z8 ~3 K* Q# c
output mcasp_afsr,6 Q- r9 a* N' N w( Z$ M- a
output mcasp_ahclkr,1 w d7 \! x5 `
output mcasp_aclkr,
0 H i( k2 f$ C) toutput axr1,) o) v" _! d/ F2 P, w
assign mcasp_afsr = mcasp_afsx;
2 {5 p) B$ F1 E! o9 r- t' Qassign mcasp_aclkr = mcasp_aclkx;
3 |* \* j+ H4 Z) G6 {) P/ oassign mcasp_ahclkr = mcasp_ahclkx;) ]4 b a' I2 R9 I1 w1 y) }, I
assign axr1 = axr0;
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5 [* T. h l. p7 E* q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. s, B$ X ]2 y$ L5 _6 Mstatic void McASPI2SConfigure(void)# E8 K9 {" y [% x& K
{
0 ?6 j' J; ~1 k. o$ GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ [$ T8 D+ @$ L- `( c0 O" O' }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; |3 v1 K7 P/ y% q/ {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 f$ r S5 _' L7 Z+ i- i [* W6 N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 [' v9 I/ @ j; X2 o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' S" Q; g; C* BMCASP_RX_MODE_DMA);4 a* w- p) ?+ S) n3 ?3 }, T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# D2 Y1 F+ C: X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# X- Y- [1 H+ d& p# _6 p1 p A* h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 R" |/ ?/ W1 T( A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 x; S, l3 f8 J( q/ Y/ W/ s: |" Q6 q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! `6 U, |% F* ?- k& mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 H* p6 ^. ]" s# B# mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( @+ o* Q8 d* f" {1 iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: Q9 ]# |! O6 z1 U; A, v ~1 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 e. W" l9 B$ f: n+ t( Y0x00, 0xFF); /* configure the clock for transmitter */7 g$ ?3 \4 h- m% _6 M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ ^8 R) M% L4 H- I& [5 q# N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , h5 L7 ^9 h3 `0 N. n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 M* J9 b1 `* h6 d& l' J% Z( r+ s$ i
0x00, 0xFF);
9 a& l# Z' u7 Y3 G: o
8 ^% @- \% W% X- O% w/* Enable synchronization of RX and TX sections */ + |( F: H2 s; _& x [7 C. ]5 Q3 Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' V3 n# n% }0 S, S; g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ \8 I* O! z' k7 u. z5 e" n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ k; o) y; H; R* d
** Set the serializers, Currently only one serializer is set as# T8 R$ K0 Z( }0 {; |* M1 b! c" q
** transmitter and one serializer as receiver.
* e2 q( `, j% ~% @& E/ j*/: b1 O! h( c' T4 n" o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 j$ P( U: Y d' r+ v- r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 S. L V q7 y8 L9 G
** Configure the McASP pins " E( b/ R; R/ S3 V2 p9 g2 X9 c
** Input - Frame Sync, Clock and Serializer Rx
6 t& ^$ M/ G! r* H+ H/ e$ N" j7 o3 `9 V% y** Output - Serializer Tx is connected to the input of the codec 0 ?' ?4 m# @0 D) I& s
*/
" g2 y, \) p+ E+ zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, x& e# Q( l9 j, v/ m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 H9 N% k4 C8 i5 l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 C: G! n8 X5 j( F6 H
| MCASP_PIN_ACLKX5 b2 W' i$ x1 @
| MCASP_PIN_AHCLKX6 v$ }2 F B( H' U9 ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 k- }5 U% G/ N2 ?3 u+ ?$ JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 K' g+ K3 d$ x) A
| MCASP_TX_CLKFAIL
. O4 P, z4 ?6 ?) L( L# a3 s: n| MCASP_TX_SYNCERROR; E& F/ U# v n9 S$ j- G5 j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 M4 N. E) I1 `/ f% b- N
| MCASP_RX_CLKFAIL
8 f" }6 U1 p1 F' c| MCASP_RX_SYNCERROR 7 n; H3 p; a9 ?- n
| MCASP_RX_OVERRUN);
, G' P3 `! I2 y} static void I2SDataTxRxActivate(void)& w% Q3 w$ O- w" n O( Y* g2 Y
{0 M# y5 A2 G0 C& j+ I6 ?& l2 N
/* Start the clocks */
" O( b( ~/ e: h7 L4 nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 @' w* E% v3 ^) M% m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ P2 e! ?3 @ \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" g" E) a( s) \7 l) N$ a, WEDMA3_TRIG_MODE_EVENT);
H% z: l% n8 I9 m1 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * _9 P& C* t6 S3 `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& X- W, I' g2 P! t; bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 l _1 y5 Q7 K4 n1 m; EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! D, O" z, I/ D6 z" K1 k/ W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 I+ A& C' v" e9 a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ i3 h4 s, @7 U* c. H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* o0 T, K/ `' l1 t" M& k' {- `0 {4 j, ?}
0 Z4 Y/ x% m. M; {4 \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ @5 b* u0 u6 D
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