|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ g. p5 B+ w; N! E- M7 B7 o, w; Jinput mcasp_ahclkx,
; c5 Q- d8 ~6 ?3 jinput mcasp_aclkx,
! l+ `. H. n7 _( B3 Yinput axr0,/ I6 @7 f, @6 [1 q2 q
, U) Q3 i6 ^* m/ h. G# g
output mcasp_afsr,
( \8 }( s9 N' X. G! Z! m. j5 Ioutput mcasp_ahclkr,
- t( a; O3 a9 N. z; C# H' ?output mcasp_aclkr,7 k8 F3 _2 F! s5 n- \
output axr1,
: O+ c) ~3 `( z assign mcasp_afsr = mcasp_afsx;
- F0 r7 N! ~( B1 e5 jassign mcasp_aclkr = mcasp_aclkx;
7 b6 G0 m: p0 E* L4 U8 zassign mcasp_ahclkr = mcasp_ahclkx;
' u! m7 ?/ S- f7 g+ jassign axr1 = axr0;
$ B5 a. G$ i0 c0 ^) e) _
0 i7 s' T% R# k0 Q' h# U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 o! ?+ m+ @. G2 X6 ]" x' L! Fstatic void McASPI2SConfigure(void)
" i' s% y2 i4 q{
0 p0 `, n, G. [$ h* m( d( AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- {. t# }& H$ h; ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 \4 b1 ?4 A& C2 n9 D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 ?# T8 J3 [5 d' _1 n* t$ @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 f( s% v4 `; ?( l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ f; P1 Q' ^6 }' B5 k
MCASP_RX_MODE_DMA);
8 ^% f; Q# V8 o6 oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 Z, o' u+ U. e" t+ g$ q( |6 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ f0 y r2 \# l% C. _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. i/ c. P W1 ^# g5 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# x0 e; t7 ]6 T/ y1 O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ n* j1 F. _- e. s4 T# U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# l& M0 v- j7 i8 u5 }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 A/ v9 J" J/ m7 oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& {( z7 e+ G# `! a( `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# V1 |9 y4 R/ n1 b6 j J; R
0x00, 0xFF); /* configure the clock for transmitter */
% X* J3 T, T, \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ F, n) U) [$ s fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- g2 z$ R/ P b2 ^3 v# DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 Q4 |: t+ P1 z; v9 a( g& g0 f0x00, 0xFF);/ E; ?9 |1 Z/ J1 F! `8 F; @
, _9 N& S: z1 L2 Q, s' e/* Enable synchronization of RX and TX sections */ 7 Q( S, L- ]& I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 m @/ i6 T3 M, W; i& w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 \$ |" N* h% k. e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% q+ B2 I7 k' c7 j8 ]** Set the serializers, Currently only one serializer is set as8 _$ O [+ T6 q" a- I9 d
** transmitter and one serializer as receiver.
* R4 D; u# G; C*/
) l: ]$ W3 m5 R; h3 ^1 DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, Q; z, ]3 E( L3 U& D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 D/ I( @, V$ U: ^$ Q
** Configure the McASP pins
' g( n! q1 i6 k+ _7 G2 U9 V0 C# L** Input - Frame Sync, Clock and Serializer Rx, a! ?7 X3 E0 C, [4 A3 I/ g
** Output - Serializer Tx is connected to the input of the codec
* {9 O2 W7 X1 w- V+ _/ |# X*/
" s* M# T, {; a/ y3 q$ tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& b# B( n; c4 h+ ~ l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* n7 r9 V; y9 M9 h& {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 m# C8 A8 [' m' ]0 n5 |; ?/ o| MCASP_PIN_ACLKX) G7 `. u+ u" `7 x5 x
| MCASP_PIN_AHCLKX3 ^) N- u; ]" o& S+ k( |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 \2 I! p7 C. I1 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - @6 t4 z2 d, x" N5 j7 W$ e
| MCASP_TX_CLKFAIL
- f) ?/ H# v T4 @* V0 ^, z( ~| MCASP_TX_SYNCERROR
) v$ T- V& D+ ~$ O7 F* i1 Q" s8 O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; N( M6 Q0 C- p. h
| MCASP_RX_CLKFAIL
) b3 t; R7 a+ y+ D' P| MCASP_RX_SYNCERROR , d# d8 u0 r/ {
| MCASP_RX_OVERRUN);
9 G: K* R% r- A} static void I2SDataTxRxActivate(void); y. w+ ^0 s& [: Y* }
{' O$ J$ W2 a7 a* j* {& N# Z: z1 z
/* Start the clocks */6 J# H' H0 e3 v1 C4 z. `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# e4 S9 p7 H& z# [7 rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# S) o2 v3 c7 P( t7 f# n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: |' x0 M5 s e r' X
EDMA3_TRIG_MODE_EVENT);8 N+ x7 j ~+ j- E+ X" _" R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ P i' g# m+ rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 o# ?- o2 M, ] n. O0 wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% A# _+ o: a7 d% r- ~3 B0 t- _" [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; [8 z, r, ~8 y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 ] [) R) D# v2 h( f; B1 wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: g$ ^# v8 L0 v) e$ i s5 [; J1 Q! y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
h. U. w6 _* l' l3 y} & I! v3 k0 \/ V1 C- r8 E1 B$ `- \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
+ U, R- d+ p3 l) f" m- V |