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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ z( G4 n6 {/ D! Y5 Rinput mcasp_ahclkx,! c7 F+ O: W1 X; @5 v1 i# B
input mcasp_aclkx,2 y; ?# O7 N [& W* M8 X
input axr0,
+ |1 G3 D5 y9 O# D! i/ q" L7 ~4 G; D0 [! i0 U* I, ]
output mcasp_afsr,
5 K y9 H& s* ?& p# F6 A) aoutput mcasp_ahclkr,
9 w" S* j! t+ T' Z8 n+ I r5 koutput mcasp_aclkr,
& ]/ D" F: G- I. @. Coutput axr1,* H0 M! {6 U) d' d2 M
assign mcasp_afsr = mcasp_afsx;% c7 t2 a1 w5 P: B* w
assign mcasp_aclkr = mcasp_aclkx;
2 V. k2 E7 w& H7 c; f7 Sassign mcasp_ahclkr = mcasp_ahclkx;
3 Z, A1 }+ A* @assign axr1 = axr0; - H8 a! y- w8 Q# }# l: O% {
3 @4 u) i# f w! F& U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 q+ D+ |) V9 V8 F3 Ystatic void McASPI2SConfigure(void)( p1 Y9 R$ z3 }; s: {2 d- _& _+ b2 c
{
% m# `1 q! \$ l) n! GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 \( M4 Z) K1 D1 u, bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: V$ N" a' l; ^% rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( C% X: q! o% p( I" I/ n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; S% Z4 G0 u6 G g1 j3 L' ^* s+ ?) k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. i& o [" }$ G& Q/ v, n2 i* a
MCASP_RX_MODE_DMA);
6 x. ~; R, [" Z' ^- P5 p9 ]) HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; a v7 a3 \' C0 j$ M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& S# U7 z; }; i2 Q' nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& b* x: p4 }7 O: N% [* m2 y. iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& k, k- B( j) i, R! w1 h% [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / a* _5 B( p: Y5 G `' r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' ^2 Z' u9 h, W4 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 {# q/ y5 k* a1 q& yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( ? r) c3 r3 u! U* i* P0 O: LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- e1 W3 A' V6 _; u7 D# U. S! L0x00, 0xFF); /* configure the clock for transmitter */
8 P4 m; g1 G& t/ xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 j5 A8 M @7 {% O( n! E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. A& Y6 p( L" C3 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# {: ?& v1 n6 R! ?# D2 f5 z0x00, 0xFF);0 W+ i& [5 d# {4 I% i7 u! N* `
( C! b. e4 ]4 Q8 o* ^9 j$ I+ U
/* Enable synchronization of RX and TX sections */
" c7 `8 R$ H# ] g1 e, [7 v. yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 ]8 f' B2 s* v" q: I3 BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) l6 {* f! B, F+ v4 `! MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: P7 g$ E ` U( J4 y& b% E/ E. z** Set the serializers, Currently only one serializer is set as
! i5 ~5 p/ K( `& Y6 \% {) x** transmitter and one serializer as receiver.3 R7 }7 R! P2 _8 ?+ s+ ^
*/" T3 ~ ]% y/ P, q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 o/ |. ~6 ]% x. k; xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 e- l* g0 P8 z% e
** Configure the McASP pins
: E% N1 F9 x- y** Input - Frame Sync, Clock and Serializer Rx7 S: j6 `1 e" A3 o3 y- T
** Output - Serializer Tx is connected to the input of the codec 7 _, m- }5 I: P e. o2 J" R- F* v
*/% _$ |; W0 a+ S) ?4 g1 l# ^9 q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 A' _2 c/ }5 HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 a# L5 E5 [# Z7 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 i6 Z3 ^7 h) i| MCASP_PIN_ACLKX
/ X2 C! W. t7 x5 C1 [6 C- f| MCASP_PIN_AHCLKX* |, M) g' I( B/ g2 I: d/ }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 v7 |, q: L' ~3 X1 TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) ?; e$ g. n* E
| MCASP_TX_CLKFAIL
. G/ b2 h# K& D7 q- r, D| MCASP_TX_SYNCERROR4 Q$ b, @; P* j9 K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " ?2 S; Z. H K( ]( J0 i1 d w3 [
| MCASP_RX_CLKFAIL
: L* B) L9 E1 a. k1 J: M# M| MCASP_RX_SYNCERROR 2 u- \. B4 s8 F9 _: a
| MCASP_RX_OVERRUN);
d( _& }& g) [% E$ x} static void I2SDataTxRxActivate(void)3 Z5 y1 D# g% ^! h7 m# ~5 G
{
& a4 E1 D1 w8 l- S3 f; H/ g/* Start the clocks */
, x* ]* x0 R4 O7 @/ tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* ]2 U% O1 I# N# L% q$ XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" ~6 M! `, c5 ?: o8 C8 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! t+ x) k9 s2 k- e2 w% ~EDMA3_TRIG_MODE_EVENT);
& [8 c5 M+ _* u/ BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . u' L4 O9 W4 t; a" z: Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( F- F& j4 ~5 A7 \2 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 `! t- l" l8 u: w7 M0 O: mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ _8 W3 a6 p) ^2 ~& f$ N* t8 _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( A" Z7 `+ M) E( O ~! h' qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); s4 u6 n4 V, K4 a1 M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) H6 S0 D: _& F, M# n( G4 u}
6 T4 `9 B: e8 E5 u# l& H$ r$ k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . ]1 t: v6 W& Q) g, ]! I) e4 F
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