MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
" D1 B4 Y; A6 D  `input mcasp_aclkx,
: Y9 M/ s; y2 D; @8 J+ O1 einput axr0,

' H/ {* S; u/ h" v9 R1 W. Doutput mcasp_afsr,
1 z( f; E" t5 e) p! J; Woutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
& ~3 I3 e/ \+ W. d; {* |2 R- L! Q5 Qassign mcasp_ahclkr = mcasp_ahclkx;
, w. b9 ]: q0 massign axr1 = axr0;

% _" ~" U  I; w0 M2 r" I. i0 f7 i

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
% U, n% }6 H* e* s" `{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. M; f% q* B' aMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
7 r5 k$ ~6 c7 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
  S$ d" t9 k- dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
! {) L8 X& ?- ]! Q8 }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* a$ G6 E2 N; j4 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 ~" L5 {1 g2 ~! t! _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
0 n+ ]( ^6 a) C8 D8 }3 UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) r( A- r1 \) ~9 k5 n' DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) a/ W* n/ h% X2 K0 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
7 v4 C" d* [$ g0 wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! W0 j& N; B7 _% s0 |0x00, 0xFF);

. m9 S1 d# o; g1 G/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
; w6 K; K% h& G- v( F, f5 IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 ]* Y0 k, U* V/ N3 T; }- gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
0 F) r2 u! f$ D* a% b$ G7 u9 Y0 F, s** Set the serializers, Currently only one serializer is set as
: j5 D. R, K4 C. z0 ~4 @/ w** transmitter and one serializer as receiver.
*/
, D  p- d% m7 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. s% i+ C* t/ n8 ^, m& ~0 kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
. f! |$ P/ U1 t( p  b** Configure the McASP pins
) g: Y+ D3 l& Y+ q** Input - Frame Sync, Clock and Serializer Rx
0 F5 H) d5 y3 c4 P9 L& M" R3 p** Output - Serializer Tx is connected to the input of the codec
3 j, ~' m7 g/ B, N- z+ P6 f*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) ^7 D2 N" W  @$ M/ O( E! @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, p0 T& k% l- a| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
) k1 e! F2 t9 r0 p! V) ^2 o| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
* v& ?" f0 ^! h1 |8 w  G, Q| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
, x' u! m; S. M& J" x{
0 ]5 r! O' K* O/* Start the clocks */
) Y$ R8 O  I! g+ j5 BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
! a3 V8 j2 O8 k6 w; w: cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 U  v& V! `8 [8 Z8 s6 X' @$ hEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 j& m' Z$ d4 ^. |4 |3 ?1 _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
% l% }1 o) ^* x0 D, B, g( w- K9 }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ \# r- J6 s+ z5 x% BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 d  h8 K# R5 H8 r3 H6 v$ ^0 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

( A6 Q7 U  E. }1 D6 L