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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 s5 i8 u( k1 X- m. `
input mcasp_ahclkx,( [" H' x5 |$ S+ G1 V6 `' A3 h, f
input mcasp_aclkx,
: o+ c+ y. P! ainput axr0,# g l2 r* T7 \9 L( M) ]" w5 ~/ \
0 a; r& B# A _( o. r
output mcasp_afsr,* j! r+ B" r. i. `; `
output mcasp_ahclkr,+ m1 B& T& `9 C3 g; r
output mcasp_aclkr,' A7 L7 W' t( T7 r
output axr1,+ \8 ]! Q( i2 F$ V
assign mcasp_afsr = mcasp_afsx;3 v2 f- S: R; ~3 v
assign mcasp_aclkr = mcasp_aclkx;5 t* F- x! A# \9 v7 M
assign mcasp_ahclkr = mcasp_ahclkx;. P/ O" V8 @. ?. M2 \
assign axr1 = axr0;
# Y' @# n+ k2 C. f y
# j9 H9 B Q6 e5 P& R9 F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * E& V8 s2 H s" _2 t
static void McASPI2SConfigure(void)+ U. g1 Q8 X/ C, O, x
{
& j" A- P r& T5 R9 ^2 b' eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: j+ l& t9 q9 r( c6 o! UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 S& e) A2 g; b" `/ XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 s6 T4 b5 Q/ y7 O- mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 a: w' x# i( t" Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 j/ J( Y: S8 K+ j; @4 W' QMCASP_RX_MODE_DMA);
& h0 M( V6 H# ^2 ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* z2 N7 U% `! y/ k! W2 [6 MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' F( @. u4 a5 y4 }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' Z+ Q) F% F* I( x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* @5 x+ C6 Q4 N$ ?% C7 VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 Z5 ~3 k4 c) R7 u5 ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( _" ~' P5 w# x9 X! nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 {: P% X( O# _% Q; {' p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % P$ c" F% M$ t# B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. ?, H* Q3 p$ r! A0x00, 0xFF); /* configure the clock for transmitter */
) o, D+ n; ?& O U0 \7 N dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, Z4 f( b2 g: g7 L z0 r; KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# _$ h# s; H# ?# v( |$ |5 MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 a' y$ p; \; r. G/ q- X/ f0x00, 0xFF);
5 Z/ {0 t% S4 G4 I3 X9 W# q3 O4 `" f$ p+ h {6 M
/* Enable synchronization of RX and TX sections */
' ?6 N/ Y; y [: z+ E. f; wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; g* [5 f6 D/ y/ y. V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, }8 F, p; f: CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 m* }+ Q* e0 `1 n% J" h** Set the serializers, Currently only one serializer is set as
( } A5 }! Q; x! b; o" k** transmitter and one serializer as receiver.- s/ R; N; s/ R. B ]
*/+ @ W" h! t* ^! R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 I/ A9 h9 E- ?" K9 _1 G- }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; P" v6 B5 t$ Z [4 P. H
** Configure the McASP pins % s5 ?, g: Z& g) ?
** Input - Frame Sync, Clock and Serializer Rx
6 J8 s3 E$ p3 @8 f. ~** Output - Serializer Tx is connected to the input of the codec % h7 k) S1 N8 ` k; h* C: [
*/$ u# J8 ?1 ^; h& \$ G6 X) v- W+ H" l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, R$ \' `2 E% N4 ]: }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 {8 Y7 A7 C% oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# @8 [5 |# l, Y9 [& ~4 U5 g& ?; O
| MCASP_PIN_ACLKX' k( i5 [* v- \, J
| MCASP_PIN_AHCLKX
+ F/ o) H, F5 Y/ y: W5 X' n5 W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. r$ h* L. u# n4 J. UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( ?7 b9 F9 `- G5 J1 y! A, P2 y0 E8 j| MCASP_TX_CLKFAIL
8 S; [; @+ T# t| MCASP_TX_SYNCERROR
$ Y) n4 `9 E2 u" w! I4 |' i4 W* O1 z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; T; v. _6 x" w5 U/ E; R; s| MCASP_RX_CLKFAIL
3 e$ m' b3 H4 d8 X$ T6 T| MCASP_RX_SYNCERROR
* ^3 t2 _; a, t) |; ^+ k! U| MCASP_RX_OVERRUN);
2 B7 i, v# H) W; z# I x} static void I2SDataTxRxActivate(void)+ s* ?6 f! c7 j; J" c" T
{
9 x. x, j; G9 Z" @4 t+ S/* Start the clocks */
' o% r; K5 p( B w, sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 q" t! Y" E$ r. @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! o& _2 K, r1 e6 f6 k3 T bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 n4 _/ B+ Q# G+ c# m
EDMA3_TRIG_MODE_EVENT);
; O ]4 N7 b4 I. ?" n) ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, g# b5 O9 @4 N- tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ G& g+ ~) a% C% o" W$ B q8 \) b3 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 @9 ]6 m, Y+ s6 g! P# c, Y. g5 v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, q& M: C" D! P2 K4 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 o2 n" |- ?0 C5 j' C' b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. D2 i; |- j# h: y iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& B3 M Z+ Y6 ]# ?4 C} $ n4 Y2 w8 {$ j% V2 `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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