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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, D/ E3 C w$ X# m$ Z/ V/ U
input mcasp_ahclkx,
6 e' ^4 k9 ~9 x1 D0 Vinput mcasp_aclkx,
0 e$ X8 N$ N- ~+ E9 L Sinput axr0,
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% n. {5 q4 h: Aoutput mcasp_afsr,
( O" j9 ] Y- K1 {' w; d; M- s( goutput mcasp_ahclkr,
7 b$ s0 p, x" o/ J! ~' i; Doutput mcasp_aclkr,
$ g4 w1 F% ^- Woutput axr1,5 r G/ l: C' q& {# b+ R
assign mcasp_afsr = mcasp_afsx;
0 ?( T6 P( c: aassign mcasp_aclkr = mcasp_aclkx;
: f2 G( l: I) |* o5 m" jassign mcasp_ahclkr = mcasp_ahclkx;$ O1 \; g* d% F4 B) `" G
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) B/ X1 j3 T8 j$ C9 c, Gstatic void McASPI2SConfigure(void)
- W' E" A( u" O{& P% b# C0 h: C2 ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 l. J+ k/ e; \3 d6 a$ FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- {( F. s& g/ \. b* l' b0 VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 w5 Q3 }$ |4 Z$ h9 @; {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ k; H2 F4 t3 A6 V2 D. mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 V, u7 D0 ~5 y; g* _) [% G: e
MCASP_RX_MODE_DMA);) u! u7 c+ w% ^' ?+ Y4 f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; _- X6 }2 ]& Q2 y! i& d4 P- hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 Q6 c: f7 f5 @: uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ [8 f3 G& T' }1 uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) N" E3 h1 }$ G( zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 o R* V$ U5 R2 U" M0 f4 CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" \' Q! K7 M; _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- A2 m2 ~. A2 b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. D' U+ c4 C+ M5 K2 C! u4 w( eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: n/ m) P. ~( M @5 x
0x00, 0xFF); /* configure the clock for transmitter */$ l3 j5 N# f! T; T: i3 z9 \& g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' t, _# k* D& C& j3 u" vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* F% K) e0 ~6 E1 eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& A9 w; z! |8 o& ~& C0x00, 0xFF);
% N5 r, I$ a7 G; T" V9 F) I1 s8 Q; F
& ?$ k6 |* [$ F) `: v* I/* Enable synchronization of RX and TX sections */
5 o S( S% v+ j8 F; |$ v* y/ aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 v4 |4 H& R- W) \8 ?! W- S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 f/ } u( k% B3 LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; B& J( \ l$ e3 [/ q** Set the serializers, Currently only one serializer is set as
" T' @0 B: b+ U' X- Z; S+ S** transmitter and one serializer as receiver.# ^! y. J6 u& L# G$ z5 c& a# P( q
*/) D1 h- m( |# v2 ~1 P. ` s# O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 r3 A1 _1 g; F) e: ?/ kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 l. E' u, g7 L2 a** Configure the McASP pins # v& p) S: r/ e5 O' H- G! g
** Input - Frame Sync, Clock and Serializer Rx+ m. ~# O% ~( g
** Output - Serializer Tx is connected to the input of the codec 2 |& P, u3 k! ]) l' R e- f
*/3 ]8 z6 F$ q9 U; L8 R7 h# Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ H7 M% [) K) T1 O2 @0 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); E" \5 w2 u9 v, o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 k& ]+ l/ H+ J+ ~ w/ R( Y' \; F| MCASP_PIN_ACLKX
' I5 r1 _' }$ k| MCASP_PIN_AHCLKX& y/ n, l: \) z% A7 N4 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// n6 S9 p1 w P V3 D8 T* X. ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# A- Y# Z: R: Z; n) H| MCASP_TX_CLKFAIL & W% d6 I7 J" S9 P! C: \5 u
| MCASP_TX_SYNCERROR
4 [7 r! d6 Y$ x) p3 G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; _2 j) d1 h+ M- {8 |: s/ R
| MCASP_RX_CLKFAIL) w# O# s3 U' e3 L8 F5 E& E
| MCASP_RX_SYNCERROR
o9 x* f$ w' m$ R% l| MCASP_RX_OVERRUN); w% w' W& e5 i! p4 p
} static void I2SDataTxRxActivate(void)
% b/ f$ r* _) k2 n$ e. l' f{% ~$ n3 I7 [+ N0 B6 V5 n
/* Start the clocks */# ?: c( u! i, E' s! r, N9 M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! H, [! T0 X2 f/ @8 k, e* [4 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, @. F: G" l; e, Q1 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 s. G4 C' N8 Z. m* M2 i1 \+ l5 I
EDMA3_TRIG_MODE_EVENT);
* ~8 Z {2 L7 [4 k. t3 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' j8 Y; W- f# O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 O2 x! h7 n \/ X. k. bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 c( x: n. O+ {7 s7 \9 J% r* WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' @1 p; }) X) J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
z* b8 L8 |+ C" JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: A" L) D' ~9 ^. c7 D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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