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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& ~6 G6 ?2 N$ v& t9 {
input mcasp_ahclkx,8 `1 G4 ^' w. v% t9 h
input mcasp_aclkx,
( ?3 {0 v2 w5 ^+ Linput axr0,$ R8 Z% S+ n/ G
7 S5 ~1 i" O- @5 r" B$ B2 V7 o2 x
output mcasp_afsr,# k2 x' q5 x& y5 t& h9 G9 _& M
output mcasp_ahclkr,' @# u- l9 U* Y7 e" {# `. y4 U
output mcasp_aclkr,* u J9 L& B% U% A
output axr1,
2 J; i7 w! s" u( K4 ]. g assign mcasp_afsr = mcasp_afsx;' Z1 I! n& r3 H- S0 W
assign mcasp_aclkr = mcasp_aclkx;; D [" T# a! Q' X$ W5 x4 _8 A% C$ M
assign mcasp_ahclkr = mcasp_ahclkx;
2 w0 A* X) m8 x, H; N4 Bassign axr1 = axr0;
% l1 n0 E0 a8 a/ l( h
) ]. U; f1 L# {9 o3 S6 r2 e9 T0 h+ g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 ^: U# C1 C( m. G( p
static void McASPI2SConfigure(void)
7 n9 i# F8 ^- ]- I4 {" u/ E{( r/ d) p/ K6 b- E8 D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( b0 S8 }/ E* ~* f$ J/ y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 z( r! k* ~" o2 w2 y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ k" C- v! z- c# y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: y( x+ A- [4 U5 J1 }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% H, i% O1 S& C, t) V1 ]& cMCASP_RX_MODE_DMA);& ], P, V" t* a( h: x; f4 B$ P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# b5 Z. v$ S8 Y. ?' ?) N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" H3 H g! _) x, \' L- ] y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' G% [0 a2 C! g+ O7 ]% D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 s4 X5 j1 G( J8 `7 m! G7 k& ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ A$ ^# L# W) mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* o6 x: b: P2 v) f7 b9 Q) X5 q# CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. @( `, t0 E# B ^7 b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ l1 [' J6 A. c6 Y$ ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ \/ u4 ^5 ^9 L5 c' D0 s0 {% N0x00, 0xFF); /* configure the clock for transmitter */
6 t! Z) c* S# C; DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ |- j: e# y) J3 I7 _$ }/ [! n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 [" I1 v. V8 Q) _) u% ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 R+ b: g- _" U! L* b4 M0x00, 0xFF);% s# ^9 _ n) e. }! n
- Y4 O1 W8 ?" d. ~2 V/* Enable synchronization of RX and TX sections */
( x7 G: w: O9 \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" a/ m# _7 K# Q+ a. X7 MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 i8 q2 C: A6 a8 \9 G0 W0 e+ w/ b2 XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 L5 v/ P& ^% i* q# i7 I** Set the serializers, Currently only one serializer is set as
: n ?, A2 [% S** transmitter and one serializer as receiver.6 I# h% B* D. d% }5 P- D
*/
4 i3 a% \" V* f. |0 n) ^( eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' B/ D" n3 D% g* ]2 ~& A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 T5 B U2 q: f& b# b1 C/ G
** Configure the McASP pins
3 g9 h8 X! _& f' J, ?4 ]** Input - Frame Sync, Clock and Serializer Rx
; L9 M+ r* R% Y6 z' \* V/ r+ l7 X** Output - Serializer Tx is connected to the input of the codec 0 g) f o, m, C7 z
*/: P2 \; @$ Z7 I$ g/ q& j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( t& I* K( `' Q; v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 Y% w, f$ u- ^% P( w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! l0 b: \6 m0 i
| MCASP_PIN_ACLKX* e- Q% \( u7 e4 F
| MCASP_PIN_AHCLKX
, L- D( h2 c% U5 O. u0 E8 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// w, d- u, o% G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- z/ W/ U9 B% S8 R5 Y| MCASP_TX_CLKFAIL , y# |& S1 m) ~4 K$ ]& i9 I3 c
| MCASP_TX_SYNCERROR
7 U& i4 v* J* f' J6 F: m, B* @) k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' j) l/ Z* x7 e5 D( O! ]( w! Q9 \
| MCASP_RX_CLKFAIL6 |( M3 i6 a2 ?* \
| MCASP_RX_SYNCERROR 4 v7 ]& |6 i5 \; P$ d# G
| MCASP_RX_OVERRUN); j2 U* a0 R+ W
} static void I2SDataTxRxActivate(void)3 G. X* V4 c- H8 i8 u
{- a6 |* M, j' J
/* Start the clocks */
5 u0 G$ N/ n1 T+ ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: V3 W0 p# v& m* j$ R6 \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 Z0 [' ?8 e3 {" PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' G6 Z- e8 M( W) N! j9 nEDMA3_TRIG_MODE_EVENT);
c* h( {! B+ ^0 f D( S7 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
`1 \8 A1 U" IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 H; h- Q% e$ B2 WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" F8 O% |( O3 v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 `7 y* e+ X2 T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 O8 a. e# [* u! Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 W3 P, ~+ f8 s: UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 {# k% a8 @3 R+ A3 A' o# j}
9 n& G/ \; x% \9 v9 D6 h: e" u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + K5 h& a: v" r5 N
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