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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: d6 X" f7 o9 f' H
input mcasp_ahclkx,# @2 F' r0 f2 ~5 s* `7 U9 ?- }% c8 p
input mcasp_aclkx,! I& C5 I" |0 F7 d+ I# W
input axr0,, B `. C+ _5 k' A4 W
* j1 m G$ a. u2 i/ Woutput mcasp_afsr,/ Z% ~/ Z) |- m. Y
output mcasp_ahclkr,
: F$ ~& a3 ~& m* h2 |8 p* youtput mcasp_aclkr,
1 P4 @* P3 R4 ?, A' C7 Ooutput axr1,
1 L! Q% v( |% o% Q- f+ j9 j! g0 j! a6 A assign mcasp_afsr = mcasp_afsx;: |' ?# g5 B( d1 N+ B/ ?
assign mcasp_aclkr = mcasp_aclkx;
6 u- W/ r$ M8 C+ T" B/ Q9 V( d6 z8 Xassign mcasp_ahclkr = mcasp_ahclkx;( N$ a8 G1 H$ l$ ?! n
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 ]( a& S( h5 Y) h% h
static void McASPI2SConfigure(void)+ }/ c4 Y0 Q* ]% p4 u9 N) d+ R
{
) f) m s5 v% U: Z5 O$ a* ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" \) s) d$ I2 U z. iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" n1 m% v; t; AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 m' o" ~# ? B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 S0 [; b2 o' E! w2 f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 ?5 ^ V, e0 ~3 S
MCASP_RX_MODE_DMA);' z' q5 R% I/ Q9 [8 }' U& l Q/ D6 b$ C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ o; V7 N" q- t7 {3 V' I9 L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 g& ?/ M2 J- H$ W5 P5 o7 J6 ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # _' `- H; D- q+ Z+ y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. C4 r9 u3 a6 P8 U/ JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 B( w/ c) v; CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% b1 _4 z3 h" y7 S) C0 }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ }. D' _9 M/ }$ v1 j, _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; o; c3 K8 n t% dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 A2 [2 c6 @3 B4 X+ }
0x00, 0xFF); /* configure the clock for transmitter */5 n( S; B" t/ e( B5 K% T( d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* Q; I. k( T. R8 }# T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; u. \4 T' e' `- L% o- x6 { QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% O7 I& s1 N" U5 N" O2 t
0x00, 0xFF);
, J6 O+ g n8 j" o7 L* G# D
; \- O; {5 z j: F9 M0 W/* Enable synchronization of RX and TX sections */
& x' `6 ]; m+ S8 ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 B1 [6 ]& v: s! ]# r" `3 w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) |& w: H7 |' S5 ~. Q6 B0 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 G1 @* A9 P# {** Set the serializers, Currently only one serializer is set as
0 j$ a3 I/ e7 F5 A8 P1 O** transmitter and one serializer as receiver.! s0 C; W, o G9 O& ~ X- Z+ o
*/
2 A, x% M' p/ J1 E# G D/ P: SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* Q" D9 W: m& W9 N* eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 O. _5 v) L6 w6 N" o6 m5 u% ~
** Configure the McASP pins . H2 v% U/ W/ Z8 P% [! u6 W: _4 S
** Input - Frame Sync, Clock and Serializer Rx
' X7 }# e+ \/ `& i0 o. u2 V** Output - Serializer Tx is connected to the input of the codec 4 O! {8 }! a0 |7 f/ ]
*/5 X4 w2 o( w9 v0 W* @9 G6 ?# o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ y4 g0 R+ Y" C6 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& Z0 |# N9 h- e8 k. z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- X# T* q2 ]7 A" s
| MCASP_PIN_ACLKX1 R5 w! e. b4 i/ E' v4 R
| MCASP_PIN_AHCLKX
( |( I- D0 s+ ^; b, R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: G: p5 ?" D2 R: t+ OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 l. P) \( `2 E; r/ ]/ S| MCASP_TX_CLKFAIL
* O k/ L+ r! o/ {+ S| MCASP_TX_SYNCERROR
- A/ F8 e& j7 J3 I+ h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) k6 y6 x+ M. J6 K/ E3 J
| MCASP_RX_CLKFAIL6 m* C4 T' Z3 U! ` [3 C( P
| MCASP_RX_SYNCERROR : n& l0 L) L8 T
| MCASP_RX_OVERRUN);
) b3 T- N' \$ I: I} static void I2SDataTxRxActivate(void)* b" l5 a- X/ E) `: _
{3 h$ R4 }! }; X; A" ?, x
/* Start the clocks */: d. O: S# j9 F- w1 T* R( S/ ?! X* ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); l$ Y6 l; o6 d0 C, a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 i+ ~( @* A/ D0 u* y# e dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# Y- A" D, Z/ s' D) lEDMA3_TRIG_MODE_EVENT);2 d2 ~" ?- d8 G9 L% f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& \% s& j4 e9 K2 `+ `- NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ @6 }2 H. r3 W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 _8 C1 E! I6 N: v6 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. z% e4 N$ W: Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 o: O4 P& u9 E# d4 D- mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
y$ N L2 H# O+ b5 A+ H5 wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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