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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 G+ P" v6 }# N# O
input mcasp_ahclkx,
; F9 P1 ]% E% Z& pinput mcasp_aclkx,( |, o! r) U1 Y3 {
input axr0,
8 Q, p8 {7 H6 E$ {$ U% M! ?/ z. L+ {/ t$ @
output mcasp_afsr,- K4 ^9 H& t& q4 A- x" \
output mcasp_ahclkr,
& q9 ~3 q. G( \1 F2 l9 U, v* koutput mcasp_aclkr,* j) Q5 ?0 P& U' A% u4 i
output axr1,/ d9 g3 f3 C" J1 l
assign mcasp_afsr = mcasp_afsx;
p/ z' f* O$ Q; uassign mcasp_aclkr = mcasp_aclkx;
1 W0 d, d- k6 p9 z5 C5 {1 Fassign mcasp_ahclkr = mcasp_ahclkx;" A' j' E( t* ~1 I/ A! t
assign axr1 = axr0;
, v8 F3 E. `# g# i# g c7 P0 R, w9 A! H! b5 K& H9 P9 f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- s( y3 h2 a" R% r9 i2 xstatic void McASPI2SConfigure(void)' H; ~8 |+ m- p ?7 x+ E& k3 y
{- x& Z. E4 G7 y1 R% }0 E& M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 Z) f2 [6 f( s! JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% M3 w- w% v$ K! j& }6 `) F" m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 Z* B" ?: A# g. R) d! xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ _% _% d8 `" S; w% K) A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, N6 Y* }2 |2 |1 pMCASP_RX_MODE_DMA);
1 | ?* L+ O( I7 z8 O; \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, c& n$ s9 D( f) rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% l) Q$ J' i N5 c. tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* G4 [8 z& J$ f! R xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( W0 R! w1 W' U0 l0 \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) S2 V4 O% e2 }% g- ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& `! Y) ]- x V1 D# Y* xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 g, g, w0 l. v6 iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& g0 ~* \# {3 b6 H" g6 WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 M, G7 c7 t3 g# D- K0x00, 0xFF); /* configure the clock for transmitter */5 ^& U& D3 }4 I) E/ D A4 {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! h/ g( r4 k2 i. k0 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & X3 p3 f$ G; @- h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ m8 e2 Y9 n$ i* S0x00, 0xFF);) B7 a" M2 G% E8 z+ O
) @/ D4 i! |- J% c! a
/* Enable synchronization of RX and TX sections */
3 j( |% a- j$ V2 o9 iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 m% _! E0 r/ K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ d1 _' r J! G5 {. r5 D% |6 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; }2 P! F0 [/ P3 z1 P4 X, |# \: X
** Set the serializers, Currently only one serializer is set as
h$ Z% ~7 g9 z8 K& y8 L8 }** transmitter and one serializer as receiver.* G% O/ x2 L8 M2 h
*/
9 G+ ^- ~4 {9 \3 ^. |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! h$ l J2 f$ R! a: h* `% K) I; AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- o2 z# ?: F" u7 Q- D** Configure the McASP pins
: v$ `. P8 N3 V) X** Input - Frame Sync, Clock and Serializer Rx3 U; V+ M% ?5 x# A& S4 }( I A$ P& F1 P
** Output - Serializer Tx is connected to the input of the codec * }- u# N; ~+ a) L/ y
*/
( `4 D7 O. T. A- `( e' x( _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. c( f9 U- l p3 _- q8 l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 z- e$ ~- `. ?7 X' \7 ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" i' I6 g( I* T9 d9 q$ y| MCASP_PIN_ACLKX n/ ]1 e- z3 \0 R- V" p$ |3 B
| MCASP_PIN_AHCLKX0 H# Y4 Q( @: q* `: C% _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# a( G3 r& u4 D8 u+ R& q! RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " a# M9 s+ x6 ~" ]! J5 U) e
| MCASP_TX_CLKFAIL
V: l" E% Z- R0 D- f9 ~* l( k| MCASP_TX_SYNCERROR
5 a6 x2 x/ N6 P! B$ E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% b |( _4 Z" S: r7 P1 `4 J| MCASP_RX_CLKFAIL
" t2 }8 \( J1 T T8 A8 M/ \| MCASP_RX_SYNCERROR , W- W; k5 z' o$ V! C
| MCASP_RX_OVERRUN);8 w- Q$ A9 Y' g$ n. L
} static void I2SDataTxRxActivate(void)! A& [3 |8 Z' @4 {" R
{
: N" x N. h* [+ G/ \4 x- e9 Q/* Start the clocks */) q8 z2 o; Q: N3 C! T0 y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( P: ^. S* i9 j/ E: r8 F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" r9 q. t1 P/ r qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 w% L2 I6 @, }+ I% b! O2 H# VEDMA3_TRIG_MODE_EVENT);% [2 N. c) ]" f; o: S% P* \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 a1 _5 b0 ]$ h) Q/ X( v( AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 l( d; |1 H+ T4 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! }6 O+ Z b/ M* T& B+ N, q( S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 H" ~3 M W1 Q4 p1 |+ h5 H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ f( j0 }2 |- `# l8 G- E- }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% d; e! q: R! S p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( h {% b2 f6 p9 d+ L- }} : |+ w" B$ y0 g+ T. W9 g; `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * i9 k% n+ _0 V9 t
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