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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# d- Z+ v/ _( c5 l2 }* I# Cinput mcasp_ahclkx,
$ ?' S0 J. r% X+ D8 S# oinput mcasp_aclkx,* E- Z" {8 ~7 O, k6 |( U
input axr0,* S) V: ~& t4 V/ |" Z1 N
7 ?; _: x2 G1 w
output mcasp_afsr,
$ A2 V, a* t' G0 H) W4 ? |9 l+ `! Poutput mcasp_ahclkr,
- n, x9 Y5 J: v3 soutput mcasp_aclkr,
6 w( s) Q( N, c; routput axr1,
! s/ K2 y z* Z' D* Y/ Z assign mcasp_afsr = mcasp_afsx;" N& E+ ]: V, F- _& c! n6 A8 F
assign mcasp_aclkr = mcasp_aclkx;
# L' z+ P& X+ K9 p& N* d8 D3 f' k8 nassign mcasp_ahclkr = mcasp_ahclkx;1 Q0 ?' J w+ M! O$ t. ~
assign axr1 = axr0;
- w0 c& m8 {6 o: ]5 \3 Y ]
3 q) O/ [8 ~$ M: S* L/ y3 x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * j1 R. h* \3 [; B. r& n% I
static void McASPI2SConfigure(void)' p- C: B# k( U+ `) X$ N
{
5 y2 a5 g4 [4 L* w" k2 F# UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; R; w$ D; |( i& p5 j+ J% |1 ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" a' q+ R3 P6 g( x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ L9 y W: y4 qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% N j: y4 h. ]- a/ U3 MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 a! O9 k8 b1 j. O3 a o( _
MCASP_RX_MODE_DMA);1 F+ v; l7 h5 V$ C* i1 }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; {" u/ l* N/ e3 `2 N, T, r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; h* X" l4 O# ^% c( I, h- R" v& cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 V( q3 F8 n6 Z$ W- x8 LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 y* ^ p& R6 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 |' Y3 D: L2 o8 ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 U9 U# ?, ?# f' }8 p! ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& L1 j; R" k$ }" E: n6 a8 E7 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ \. j5 p, Y) ]) C7 j, T7 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 p0 A+ w$ \- J' r9 K* N; ~- c) h
0x00, 0xFF); /* configure the clock for transmitter */+ n, Y/ L% T% S t" K3 O; ]$ _% W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' o6 t" ~* g p, F2 {, `) sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 Y- k& H/ `5 s4 M6 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 r% b+ N# |( e9 ~2 D) E# Z1 s
0x00, 0xFF);
4 U; s c# P3 f" E' x* ], d( P4 k3 W( H. B: m2 Y
/* Enable synchronization of RX and TX sections */
* W, n/ x) {& e+ x/ DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ q8 h2 A$ h" k6 N; }) T5 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 N- _" f" ?- L- k, xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ o _$ `" p- h! R5 p** Set the serializers, Currently only one serializer is set as
/ l: ]/ c, D! c, c( {$ H** transmitter and one serializer as receiver.4 O# K4 b9 ~: ?/ i& w
*/5 Z0 G0 o! k" m: `) `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( d. ^' ~" q0 l7 I5 _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. U* S$ C5 h; I! _$ @** Configure the McASP pins
1 p6 C5 A1 y: N2 u5 Q** Input - Frame Sync, Clock and Serializer Rx
2 C/ [# \: G( }** Output - Serializer Tx is connected to the input of the codec
: g0 p- u! a% |- g4 W*/5 Q2 J( D! Z% C$ X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 n1 X1 P$ N; k$ l' } jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
U+ [, |; i( b# f2 X' m# t( P) \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 T* K! n; Y$ B4 e3 |3 U| MCASP_PIN_ACLKX
4 o0 m, ?5 y% M/ z# G$ s, h3 v| MCASP_PIN_AHCLKX- H3 q$ R: J+ S0 O, t9 B7 K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" D/ Q; N! k+ \# u" f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + o+ Z! a; a* C, f5 o
| MCASP_TX_CLKFAIL 7 r' \& Y3 h# R, A
| MCASP_TX_SYNCERROR( X$ @) o, s9 ?* U9 a% I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* c0 g4 q# ~+ i+ v7 d: K| MCASP_RX_CLKFAIL
# y5 b: b1 f3 J# U| MCASP_RX_SYNCERROR , w: M5 X/ d/ n V8 p8 v1 J
| MCASP_RX_OVERRUN);2 h" b) t! o M& N' z4 w! F* x
} static void I2SDataTxRxActivate(void)
; l, Q( n. S( n4 `' V; J. L{
/ |. A4 V( r( l9 r! B3 p: R5 Z& S# R/* Start the clocks */" C$ l; J2 Z( @+ H: ~. `9 {4 Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, [) ?! O! |4 M7 O k, j% mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; L4 a1 h6 |5 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, e& [% M! S/ G/ A
EDMA3_TRIG_MODE_EVENT);- f2 P3 o- O/ A( G9 P/ b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; l _& ?+ ]$ v8 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
t* s7 c) j h" A6 x0 kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* v8 ^2 D0 _2 Z/ u- g# s. JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" O& @7 K3 d3 E; D% u8 {1 iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" d. P! c) Z. C% `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ |% A8 k+ Z3 v. ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 d) b6 i" K$ k, v6 k' N' ^8 u}
8 r( B6 ^) P& g3 c0 ^6 z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( ?" p- v7 E) I/ }4 A+ D; u+ d6 G
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