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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# ^: y# }! p8 u: _, A6 n" x/ vinput mcasp_ahclkx,# ~ ]. w/ h n/ m- q5 ^
input mcasp_aclkx,, Z& e9 g T. O: p8 H
input axr0,' _* k% V7 }* I; m. G
1 R" m' ]& b/ N5 A! F
output mcasp_afsr,$ [3 ^1 n' F; H/ r1 }, K T
output mcasp_ahclkr,
4 G3 Z. F0 z% Q, q9 foutput mcasp_aclkr,6 ^# c) j3 h# F4 V0 E3 Y$ {
output axr1,
/ ^5 P6 q: [. S p assign mcasp_afsr = mcasp_afsx;" ~# `- j: v& }2 x! y4 g* W
assign mcasp_aclkr = mcasp_aclkx;" |& D/ {2 U" u1 u( f5 }
assign mcasp_ahclkr = mcasp_ahclkx;* a3 u. C; e$ N! @
assign axr1 = axr0; ! j7 Y8 H9 h5 k, D$ \
; v i+ g! n2 Q9 ~! u5 n' b+ R0 ?+ |; i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 x1 ^9 h# p8 astatic void McASPI2SConfigure(void)$ E2 ~% u8 A; a' Y3 Y
{
& ~ s. L4 k1 K, NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 t9 i4 C/ `7 z# S9 ^1 ~% ]: v- m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: [7 ]- q! \3 F% CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# M' p! F2 b3 J2 G1 `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 y: V" ]- g ^ ]8 i2 `% [0 h& m) \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; ]& w7 H( ]% u6 e- g- O# j
MCASP_RX_MODE_DMA);
& {9 H7 z" _& u% {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; O2 R' B& t3 Q% p' c2 s, J' j! |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 Y1 y, R, y+ D$ k" h/ k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" K$ U8 e. k8 a6 y; yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 T, t- C5 n8 d9 t3 K' h$ t7 U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ ~/ [" f+ a9 \! D) f5 v! WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: }; ]1 y6 V# p" MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 {- d( I/ a5 W. O$ {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / x- g7 c# v4 J i8 y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ ]* }+ a5 H; c' Y5 V0 m' P1 e
0x00, 0xFF); /* configure the clock for transmitter */6 R4 u( V, d4 e3 C- P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- n3 X) y; t A! \0 gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; I7 z4 z& X! P& m. k3 v3 RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! E" A2 q5 R$ O0x00, 0xFF);2 d3 q# @* O' u3 A( r
/ f+ ]7 N5 L( Q: z& o! e$ J/* Enable synchronization of RX and TX sections */ 0 S5 h4 _$ n$ W8 [' V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* z% b$ j7 g6 F) a% Q. gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; d$ I; _6 ^4 z* b" bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& j$ e2 ?6 T1 _. n" ]' v, y$ ~% p
** Set the serializers, Currently only one serializer is set as
7 _5 } |% F% v** transmitter and one serializer as receiver.
5 n$ F: f# b0 @3 O w*/: e0 [) f4 v/ b" V: o+ ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 C8 p. G9 P$ e" RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ E5 n. J9 R4 d6 E3 t** Configure the McASP pins 0 \& v6 j; u2 U4 g' s Z
** Input - Frame Sync, Clock and Serializer Rx
+ J3 k( S; j* @/ K G4 \. R0 H** Output - Serializer Tx is connected to the input of the codec
9 B6 E7 e! @/ n3 q*/
# E! |8 U S( m. l9 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% T6 E+ R1 E9 B' e, J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! k+ y( ^* C0 _! ~( r$ m( s9 yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! N5 @; L0 |. ?. J| MCASP_PIN_ACLKX
! P! ]: S9 P: R9 T| MCASP_PIN_AHCLKX7 M8 l2 G. d/ @( t+ T2 x. ^3 ^. L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ [2 b: U! u1 v: z" x6 h% `: F+ W, FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % o2 g. L; M2 |
| MCASP_TX_CLKFAIL ! B9 T- y; K' q) n. B& v
| MCASP_TX_SYNCERROR
6 S6 V1 ?9 C; Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 ]+ v2 Y% w9 |8 w4 R; M& w5 D4 t| MCASP_RX_CLKFAIL t6 y( h8 G# Y' w
| MCASP_RX_SYNCERROR
4 X' r' K) y4 j! [! x f| MCASP_RX_OVERRUN);) H1 p) z* k- |9 |( i2 b
} static void I2SDataTxRxActivate(void)
8 J: e, ~$ \& a) H$ u{$ o& I" M2 Y* U% c; P/ w- m% Y
/* Start the clocks */, w$ S% `; m) o2 ^& k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) V0 b7 {1 f: N6 ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" N ]7 e7 I7 M6 z& m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# ^* ^# U) j* y/ Z$ ?2 T% e2 j1 {EDMA3_TRIG_MODE_EVENT);
9 ]2 g3 l+ w3 N" d" ^4 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- J' i' I7 D) D3 ~) y# w5 N% d4 b. IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! f( m. F7 U$ e3 F) f( g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! t( l: k) y* H* f2 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, F' H0 l( v0 w5 ?+ n+ J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 @6 G: |2 ^1 i# {8 U- n" }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 q0 C8 `' k( z1 TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- c; j/ n m% Z- f& K: ?' R
}
7 O* T$ V' Q" J% f" i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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