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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# d+ B0 i, o- |( Winput mcasp_ahclkx,- q/ V- m' d9 i0 z, I1 G
input mcasp_aclkx,+ K7 K; D6 N+ N4 Q3 ^7 K
input axr0,8 A7 a: v0 E1 U1 ^
9 Y; P7 a4 m" E
output mcasp_afsr,2 X2 @' k# Q; ~( y: J
output mcasp_ahclkr,6 w! {. i5 e: w) b$ j/ v& v
output mcasp_aclkr,
' w$ d3 L+ T( f: L, C$ T( g/ Poutput axr1, B5 @5 B7 h# s
assign mcasp_afsr = mcasp_afsx;
; i) a, N0 J$ c- \assign mcasp_aclkr = mcasp_aclkx;
0 Z7 B) P5 F; M5 r. j* ~3 Dassign mcasp_ahclkr = mcasp_ahclkx;
A. c( X) F' j4 Y. X) ]1 Fassign axr1 = axr0;
8 \3 a7 a" N# `
+ e n& s0 v& a Y0 l% ~ W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; o8 ?2 O5 v3 [# S( d& xstatic void McASPI2SConfigure(void)( [ P! A) G# D7 y- v2 l/ H
{
3 D# Y% K" t6 |3 K3 S2 G6 xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 p& w' x7 f+ i0 Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 f& B) j1 e2 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 M6 T8 p1 ]% B. A) S; vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) n* S( Y( k8 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 Z! M( G! J3 D5 a- w. YMCASP_RX_MODE_DMA);- E ^' K: W. E' J y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 ~: i1 z6 q2 QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, L! w* Z- u, L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : y. d& j3 ~) U; V, j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 \2 d: z; m& H! F3 A2 k6 lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, g- k8 v" e6 ]6 F4 X5 N+ c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 q% S9 ~' x* V) n' p; j9 x# Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* m" z9 P8 Q6 S) F, \% l! \, _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( H' q! K6 V4 ?- S1 M4 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! _4 L) ?9 g" U6 K% T! d0x00, 0xFF); /* configure the clock for transmitter */
& Z. G' y: K$ ]3 eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ ^. O5 Y! b, u5 LMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! E% h! J; r& J/ zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ l& O( u+ W# i1 p
0x00, 0xFF);, C C) @( C' m( f1 n" @
; D0 r/ {$ Z, y$ [/ k7 I/* Enable synchronization of RX and TX sections */ ) k) S. x* U$ v4 h/ D* J' m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- S2 T7 D2 w( P/ \# w$ b* Q1 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 t2 n% @6 C7 P) I1 rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: l1 y( n$ C4 Z9 M: A& t
** Set the serializers, Currently only one serializer is set as8 w8 c+ F4 m8 p4 P* Z: V8 @- Y# D% F
** transmitter and one serializer as receiver.
. ]4 `6 K, R5 \*/
2 _ v n5 [3 u* m2 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ r5 n) h, A+ q. ~$ [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ |- ]4 S# i6 B" b& A
** Configure the McASP pins ! w% e5 g n) u! d
** Input - Frame Sync, Clock and Serializer Rx
9 J& K( R; V% u4 W9 Z8 x% ]** Output - Serializer Tx is connected to the input of the codec
P$ Q: N* f u! J+ V6 v3 J*/
4 }8 I& ?( l4 b# ?; \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 \; c; `0 f5 J! k( Z* n# X0 KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 f6 y# r/ V7 k- ~. c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ Q0 F1 A2 m) K0 R+ y( J| MCASP_PIN_ACLKX- H2 H$ P) g% E# n- r8 r" E* x2 {8 e
| MCASP_PIN_AHCLKX4 s# n( o; f1 |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 s; _. B3 H+ v5 z, _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 t& p, o& u3 A" c# v8 X| MCASP_TX_CLKFAIL
5 s6 H1 `: K$ U$ P# Y( @| MCASP_TX_SYNCERROR& [! \6 I5 l9 k7 Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & s% ^, R j1 I
| MCASP_RX_CLKFAIL
0 } L2 S- N1 t. @+ f( ?| MCASP_RX_SYNCERROR 5 n* `! }' {, B2 X
| MCASP_RX_OVERRUN);: k( R) P4 J$ ~
} static void I2SDataTxRxActivate(void)* D4 X: ?& I2 f- A3 w
{ U+ r, l2 D4 W. S! o7 p
/* Start the clocks */
9 b; G( g7 x7 |& o! \ f8 KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ I# G& k% U3 D- KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ q; {7 i2 |* |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 z" t( C# s1 o5 P* }EDMA3_TRIG_MODE_EVENT);/ T: l4 h9 ~% p8 q( j: a1 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 ^4 x3 Z2 K- q. ?7 C: V* U5 q) z4 x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
]7 \5 s5 n; l: x9 @2 }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) b3 f/ d# Y2 ]- @& g% v9 j6 yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 V; E9 g# U/ Y$ K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" e& d5 \. i0 w: X9 K- q1 x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! |4 Q$ ?6 m3 X' r* u! [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 N7 W5 @3 M/ F
}
& o4 b+ ]# R9 A8 V' ?9 H5 {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 o& v, |4 Y9 g; y1 a
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