MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
$ r) V+ _# @) i" e+ z5 v+ |& Uinput mcasp_ahclkx,
" f# c, Y5 S, ]4 `1 einput mcasp_aclkx,
input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

5 }$ D. Z  \& g0 |- H4 |

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
8 Q# j' z$ S: n( A3 E* sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
$ I: p6 y+ ~8 g+ k6 W( DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 L! D8 o. V/ ?% z3 @6 z5 KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
  S7 y; ~" X/ ~/ q4 H) x, ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
0 z9 _% j+ i' g3 Y. a$ [5 _  cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) y: `# }. d1 ^9 W" K0 cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ Y! g$ h* z7 S5 M* IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) ?& @  a$ |# d" w7 Z' bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- f& F) Y7 v: X2 U% x4 M. s' mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, b/ C/ O2 X! ^& J# }) S/ \( p: `  cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' r$ x$ x/ F7 Y6 @  ?) K' L: _0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
7 b; ]8 w# v- ]" {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
# |) |" C: |, P2 _. [  JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
4 x! e+ T. K6 @! q8 @0 [** Set the serializers, Currently only one serializer is set as
8 J. k2 {# ]. F/ }2 A** transmitter and one serializer as receiver.
*/
* A0 s3 w# R. P; A- \5 ]" q, MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
, Q: C5 Q% d8 o8 i) \4 l** Configure the McASP pins
- Y7 Y' h+ o3 b5 E: k2 L4 }** Input - Frame Sync, Clock and Serializer Rx
* J: S3 a* o/ c/ N1 @$ Z' q  S** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% J& c3 P' q) [; s2 x0 cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# |# `' H7 G3 q- s. V7 U| MCASP_PIN_ACLKX
9 V0 m: T0 V, ?- A: p. \| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
$ v) ^4 W* C4 @& i2 tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
7 ^: K$ H5 n! j3 b/ F$ I, d" l7 a| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
, o6 {* K+ U" w+ K6 z8 Z| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
0 e/ Z5 e" a: q' j}

static void I2SDataTxRxActivate(void)
. U  u2 m" [8 A$ h" u; H{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
$ A/ A3 X( N1 A0 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 F3 s8 G4 J; z6 J/ P" v: |$ I, EEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
3 Y9 r( p; \0 g5 l6 t5 ^& uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ N  J7 v6 y6 c( y/ _: jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
+ c' S  ]* P5 Z5 C" ?/ a, n% Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 T5 g. o- B" JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% V1 l7 _4 Q$ {$ f! N}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.