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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' e7 S& B, T! x) H& N4 T3 E1 `) |input mcasp_ahclkx,
: u' d% P6 k6 p' ^% x) minput mcasp_aclkx,, H# x9 b& {+ T" d: z9 f3 E; W
input axr0,
" {0 B3 T. n( s% g# `; b! r! Z
4 j# [. C9 G+ y) f: P# @: Y/ Foutput mcasp_afsr,
o) _$ ]3 P& V T- {output mcasp_ahclkr,
9 `' ^9 O' o1 e8 E2 ~5 ?output mcasp_aclkr," H! q8 W$ }3 q' F) d1 |+ v
output axr1,
3 o) f2 ~) \* B2 t( B' r assign mcasp_afsr = mcasp_afsx; q) q; Z2 ? _+ `6 F V2 j! x6 B
assign mcasp_aclkr = mcasp_aclkx;
) t! |8 R) q* `2 e" h3 U2 kassign mcasp_ahclkr = mcasp_ahclkx;
, L w4 t' j/ Eassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 j# Z, M2 T4 w/ P: u2 c
static void McASPI2SConfigure(void)" H" i2 u* K- V, d- B! v
{
: v* e( L$ z& R4 oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" ^# R: C) g4 E5 O1 v5 {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( _( l7 v2 {& D9 |8 F, v( A) u/ dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 p+ I2 k: r- p* N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- b |$ A s2 }+ N* b3 XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ _4 l: R& ^7 o+ ~
MCASP_RX_MODE_DMA);
! ?1 T# D/ u: b9 {1 n- E' \7 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 S1 n. F9 |* d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 s% v) ?: a. X" hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # K) z. |9 c* d; Q/ T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 \ H: O2 Z8 fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 M, _1 }6 t+ @3 `. K& V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 W' W! G+ y3 L7 AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 p, K" p/ L8 C" p( z+ H9 T/ k6 eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; D7 q" g% G+ |0 G# p$ ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* u- B! S9 O7 X" _+ m
0x00, 0xFF); /* configure the clock for transmitter */, x$ Q( g5 l2 j& l# n( t0 j! E( K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. n* \6 c9 W: |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 S' x2 ^8 }( u m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- p( t8 A8 c3 ~2 {' n O5 J
0x00, 0xFF);; c' E/ O' [+ ~* N+ P y, e+ H0 x
: `4 v% p, C5 B! C4 }/ ]/* Enable synchronization of RX and TX sections */
) x6 S5 m) `) |- W$ A( W1 C- m/ d. Q+ m$ wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" t3 T- @! N' eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* b8 ~+ e! _% n( w* j( i: r+ O1 jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* C' k& E/ j/ {4 u- I
** Set the serializers, Currently only one serializer is set as3 l% C2 c/ `' Q* g/ I
** transmitter and one serializer as receiver.- I, h3 k# L5 Z5 U: U$ ] Y" {; o
*/! z& M P9 j1 C6 p: v* C. O3 A( H- K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 a8 L8 ]* n$ ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
f0 P3 _( [; E) x- C5 g** Configure the McASP pins
* A% {$ b: p4 i! z' E/ r' I** Input - Frame Sync, Clock and Serializer Rx! \. H) w. D0 ^7 ^3 l; ]0 K
** Output - Serializer Tx is connected to the input of the codec
2 T2 I: Z$ ~8 B) m& X( [) B*/
/ u* f6 U/ k: C& n3 sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; e3 K4 y0 k. x. F2 z x8 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' y7 {; V! V) _9 k$ [0 gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
S' d! n6 u X2 M| MCASP_PIN_ACLKX
+ c& @- T2 O' Y5 ?| MCASP_PIN_AHCLKX
/ I9 |. g- C3 ]4 {5 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% z% Q/ @+ e1 @5 n& zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # W3 W8 c% G+ i0 u" {5 ?
| MCASP_TX_CLKFAIL
7 f* _3 u3 F/ e: J| MCASP_TX_SYNCERROR4 H2 }. ~9 y; N7 K3 R/ ~1 c7 j' y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . ]2 a6 X2 u1 Q9 X. ~3 q) n
| MCASP_RX_CLKFAIL2 p* D3 g& D/ X1 A+ H R
| MCASP_RX_SYNCERROR
# Y7 e# K' n" n. x| MCASP_RX_OVERRUN);6 z% M- h, _+ r# \
} static void I2SDataTxRxActivate(void)6 Y; ?9 k3 @1 L; R* F
{( J D3 V$ g7 F+ I ~8 r8 g
/* Start the clocks */
# ]" Q3 b! G) _8 S% H' i9 _1 _! |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 T7 u- O$ F' V. E% [8 [# T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
{4 e2 g9 }/ ]# P* b$ ~; ]$ _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 s1 x2 q/ ~" v% U* Y( K. o- D
EDMA3_TRIG_MODE_EVENT);. K9 ^/ M. t% C1 X- {( f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! B S" Q2 N$ s! nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% H5 x' ]1 t' ^, D- Q/ f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); |/ |0 Z2 P0 k! j, [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 X' J+ y$ V3 I" X ~' k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( U( p) g- v/ ]6 C4 c1 b' x+ fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ j" F8 G$ y; A7 D1 V9 eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" z4 F3 [* k6 P! V) H2 ~}
w" e# J% u4 `% ?* _7 L. C- N4 G3 V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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