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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 V3 b$ l$ d5 S/ _4 @9 vinput mcasp_ahclkx,
' g$ q) ?/ x" A( v' O* V6 c, Dinput mcasp_aclkx,
/ n5 W4 y5 s' m4 u. o9 X0 iinput axr0,
" q. c( O( a9 Y& M$ r& W' z: c3 Y$ K
output mcasp_afsr,
& `. c, U5 h5 soutput mcasp_ahclkr,
+ ]; j$ e1 V7 N* |, V) Foutput mcasp_aclkr,
& X- e5 v: b- k: M2 Loutput axr1,
e: K, B5 O0 r2 y+ e7 Q assign mcasp_afsr = mcasp_afsx;
1 U* C& ^+ B& D' W$ {assign mcasp_aclkr = mcasp_aclkx;
0 ~- X) h( m! I% q: ? I/ [assign mcasp_ahclkr = mcasp_ahclkx;
o# ]' c' \' |. ^* a$ w) Lassign axr1 = axr0; $ H+ K2 k2 }, {; H, ]- F$ G
% E7 g7 D% b* _' `5 c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
{: q1 y4 ]% _static void McASPI2SConfigure(void)- B1 [: ]/ j5 {
{
# D! z% W, I& K6 s- t, cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ y& w0 z, G& K+ v6 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 C9 q: C2 S+ G: I2 D& c' |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- }3 ^7 B, d9 t9 N/ e5 ~1 bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, {! D' y% ^5 e$ CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( X6 S7 g' Y, c9 b
MCASP_RX_MODE_DMA);
* W" d1 J" l# j: Z$ nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% t9 B9 z& {8 @/ U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" H0 Y. t+ s# c+ H( L" v/ u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ M+ F% o# K/ h* N; t% EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 m Y7 W$ b; _& T% O2 bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % o: [6 p9 U/ i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" D! G2 \0 C( }$ r) r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 M/ n2 G" R8 {* U8 a5 e* r- gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 i, ^9 k/ ?, p, C& D" M x% z6 iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 m5 d8 c! @5 n! m, l& q! R: K# M
0x00, 0xFF); /* configure the clock for transmitter */
+ z1 [% v- C3 G5 e. [" N# [8 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& |5 T7 u" j* ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) t3 P; R# j/ ?8 |( Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 }) [" y" A6 ^/ [4 N( y: i
0x00, 0xFF);
3 E: i; ^# H* q7 T/ o6 Y# X3 A! W' w
5 V7 w: w" v' n: L; N/ s9 ]4 X/* Enable synchronization of RX and TX sections */ \+ w9 @: N& U! h) x$ U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 ^9 p) [7 \3 d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& Q% q p$ o' }# H6 b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) y4 i, ~! ?/ x# b. X$ O& I** Set the serializers, Currently only one serializer is set as
7 G$ \) ~) |7 g3 r4 P3 X% ^) w** transmitter and one serializer as receiver.+ H; b. V1 o: L) t# {
*/7 `3 D0 W6 }% f7 G$ y# g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) J$ f9 @3 Y$ {2 ]6 D" z/ J8 G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( @( B7 E7 J8 ]- n* S4 Q
** Configure the McASP pins
' W% B. @- \8 u( c% v1 ^6 {! A** Input - Frame Sync, Clock and Serializer Rx: s& a5 J6 u; ~2 A/ m
** Output - Serializer Tx is connected to the input of the codec 7 d2 q5 G: i6 d& ?
*/
6 t9 k! Q6 @) [, I$ [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 J7 }, L! E" U5 P; r! H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" e/ c c2 w9 A3 M0 p2 K8 a8 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 i3 m& T: t0 m
| MCASP_PIN_ACLKX
& a8 W1 A4 K$ v1 ?' L: |% N| MCASP_PIN_AHCLKX2 O: L$ J5 d9 M/ C0 `1 c& I, K( Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! }& G! ]; _% o, V* I9 i0 b; KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ ?3 [# _( I% B0 ~( A; |
| MCASP_TX_CLKFAIL
5 ~& S- H2 j# y% z. m| MCASP_TX_SYNCERROR5 @" H$ X/ `9 I$ p w# t6 H% a: K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 O& w7 k1 b! q6 n| MCASP_RX_CLKFAIL
, `: @/ X4 |% @- I9 y| MCASP_RX_SYNCERROR 5 @4 H0 K3 r' X7 i& }( m' k) e2 ?/ }
| MCASP_RX_OVERRUN);6 P/ c* U5 E) f5 x/ W8 ]
} static void I2SDataTxRxActivate(void)' P% `2 L6 Y1 U6 q; M
{; y# F1 K5 q2 X$ @/ t' }
/* Start the clocks */5 c! H0 s+ G: H- f4 h2 J+ B* X0 n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. I+ O' J$ g( wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ d* _& G8 I/ k- D9 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, g/ e; t% g. f9 zEDMA3_TRIG_MODE_EVENT);3 g: s( q5 s/ _, m! c. }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
Q0 F: s2 A0 W' F* W9 ^6 s. `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// N" t+ u& I8 I% X- }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& X) A { w& I1 F* Y6 G3 ^8 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 Y: Q: Z) g2 ~0 T; P; rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 A4 Y: G M+ a1 G# k1 V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& H, b( h$ X; O6 ~- i0 n+ kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 y# f5 q) P3 g4 i* r$ C}
! f9 F8 L& X2 A) q- [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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