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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& o: N: d: X; p. v. J
input mcasp_ahclkx,
5 ^! n; T8 U( T2 D/ \input mcasp_aclkx,! Z P* Q3 g) h7 T7 K3 z
input axr0,& M r0 I( C' V. E3 K! x) @
5 U0 {8 v) f+ ?3 r; o0 e, z4 koutput mcasp_afsr,
7 {* r! i: i M2 @$ k2 ^. ~output mcasp_ahclkr, @4 Z( J6 B& K5 \
output mcasp_aclkr,
/ V- c5 W T7 coutput axr1,* T" v W a9 D9 L! K0 Q; ]# z; D# y
assign mcasp_afsr = mcasp_afsx;3 T7 j9 _; N$ f: u. V/ H
assign mcasp_aclkr = mcasp_aclkx;
$ @0 K* C/ f0 | {assign mcasp_ahclkr = mcasp_ahclkx;* N# p* N( E' D7 ]) ]8 u
assign axr1 = axr0;
D( H3 r+ ]) f/ q7 o0 U/ \+ W% k- y# Y3 |; p% a/ s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) G4 \$ `' `. P1 [8 f- `" bstatic void McASPI2SConfigure(void)
0 N( D# M, I$ @) }# i$ @2 ^+ W, f{5 ~3 v; J$ Z/ i# E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
x0 W1 ^9 q/ m BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# H% ]3 C0 e7 x" L+ N: d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' {3 N" Q0 v n8 rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 p2 P% W* j3 Q$ p8 k) PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" \) [ ?% D% T6 Q+ @0 T$ C# Z1 `MCASP_RX_MODE_DMA);% b! l" G3 ~& d4 P% O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 g. B3 r7 |6 d/ {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 @; p7 k" ]$ v, ~) D% _( b4 iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. Q$ j$ T$ J" x: N5 u* ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) [, h3 G7 p& F- F0 J, V* `5 tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 z) B0 r- C7 U1 n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 \2 ?$ n9 z: v g# ?/ n, v) hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' b! `* D+ a* u( f9 D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! k$ T; x' h7 t: B- z# U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ @* N2 |; j) l/ _3 ~
0x00, 0xFF); /* configure the clock for transmitter */1 o2 s; M9 B' ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 P \( G% l& E" {$ o' A ^/ ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - \' k$ s, D% A9 K+ x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( h5 _& F0 {+ Q8 f
0x00, 0xFF);
! [' i1 P6 n+ f. d5 @9 g t
+ S7 p0 W" L2 b! c# Y% L7 o/* Enable synchronization of RX and TX sections */
& y- Q2 P8 v( d4 kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 j+ Z3 g! |( o* A$ L& T$ h* J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ ^8 V G! _8 N) U1 J& d) M; M9 YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 g( w k; y9 O4 u9 ]
** Set the serializers, Currently only one serializer is set as& J! N! `6 |9 K# |0 S: s
** transmitter and one serializer as receiver.6 e- @) y P) p6 M
*/
! V& F2 W3 Y! F' |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 _2 K( Q; ]2 h0 h. m1 j$ S+ x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** |0 W' @3 R* a( ^9 L' _
** Configure the McASP pins
. E& R5 K' Q( i4 R' x9 d# U( O** Input - Frame Sync, Clock and Serializer Rx/ r3 d- C4 v) l% B: d, v
** Output - Serializer Tx is connected to the input of the codec
# r% d) d t( L. P/ x*/
+ Q* `% w" V+ h9 n) SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. }) W2 h3 _4 ^- R: h# \9 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 z: V: V4 A e. M8 A5 e! KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; b$ \2 [- n; s4 p! i| MCASP_PIN_ACLKX
) ?( d* E ~+ g8 @| MCASP_PIN_AHCLKX
1 O' S9 g1 t {" P* i4 t& M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 L V }# Q% K3 Z7 g; I! ~- e9 W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ s& ~9 c b3 @2 B( U| MCASP_TX_CLKFAIL 8 d! n8 S1 ?( K4 a3 ~
| MCASP_TX_SYNCERROR6 T8 j$ ?/ e" X+ l3 c; \5 _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 \" {. {( K5 N" b| MCASP_RX_CLKFAIL
5 `' B1 r1 C; {5 x; H/ s8 r2 Z| MCASP_RX_SYNCERROR
* ~, K6 d3 S5 k8 b! A. \| MCASP_RX_OVERRUN);
- f( ]: [9 _" q$ R* Q6 ^} static void I2SDataTxRxActivate(void): U' ~) m6 ^8 c" q; {
{
j4 W: I# T0 @7 F/* Start the clocks */
- f+ T, I+ @- S l! C( LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 F$ i! x, [* y1 lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# X4 o' Z3 S% G) I# s! m& g& G- Z9 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 b. b F+ l4 m2 t9 f
EDMA3_TRIG_MODE_EVENT);
, D" f' i0 X/ n4 X- q5 H2 i4 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * C: y3 D9 @- J/ O. ~* P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& F# g# l) f- m% p8 S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: F& r) }( F( d: A& S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 L& r1 Z* v9 J+ H' q7 o* X" kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 F- M. N# G* E3 |+ ?: U3 c2 Z% Q2 j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- @0 ]2 g# E: S- [$ k1 `; n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, w; E. _. J) B& Q}
9 q* A/ u" ~4 K9 ]/ `) @3 E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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