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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 K1 R% ~* m( B
input mcasp_ahclkx,7 |" D5 _+ G9 f0 G' D
input mcasp_aclkx,4 ]1 I4 \* B. ?/ ~8 Z
input axr0,
$ x7 ^1 L* H$ }4 E% l8 ~) C+ w
$ z+ O# Z' I: Y% i9 |; routput mcasp_afsr,
3 j5 Z* h% u- Y! n: Doutput mcasp_ahclkr,! \% e1 a4 G# N; i
output mcasp_aclkr,8 A1 C) g1 Q& U
output axr1,( u* \4 I: }9 m2 R. o! d
assign mcasp_afsr = mcasp_afsx;5 b1 ^# n! q. L! w. @
assign mcasp_aclkr = mcasp_aclkx;, F! A9 B7 d- M
assign mcasp_ahclkr = mcasp_ahclkx;4 j( l& y; t/ E2 i/ U" J
assign axr1 = axr0;
( W7 Z" U9 G! }/ ~
R9 L. H j+ ~$ @( C. ^( e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 N) V- m2 `2 K0 \
static void McASPI2SConfigure(void)9 z% e( @5 W. `: x. O
{- w! R' M% s. E' {2 h" B o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ |8 o1 J+ t6 x4 }, l5 [- b# K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; Y8 m2 `+ S& m! M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ t# k$ x1 f: N: e* U, OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 N4 k1 `6 @7 g) y% g- dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' |; ]; w. U9 I# \1 v p4 G
MCASP_RX_MODE_DMA);
9 |8 z! C; T7 _; O' u) _" w, pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, R' ?4 W+ m( H3 \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// p9 i3 w( ~7 j7 C4 j( I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 U; U; @. _: w2 R* k! @$ u! i6 yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: j1 w8 Y: l2 ^. _1 [8 g0 P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ o5 u& \9 i+ Q# RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 u0 {5 W5 y8 p% TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ b: ?5 t& t# ^! p x1 F8 G" S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' U+ O2 q# L TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; ?( A4 i' P- Y0 i' B% j
0x00, 0xFF); /* configure the clock for transmitter */) E' {) i- |7 X* l9 i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* f! M( z/ e: E5 M# x" a/ \2 _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) U3 P, f# v9 \/ s3 U: oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- ]' C1 ?$ C+ P/ q0x00, 0xFF);
% o7 ~. |* W) \3 R+ \9 K8 [0 ^
6 U8 I3 d; @) B6 E/ O/* Enable synchronization of RX and TX sections */ 7 |1 `: z% e- X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ ]( R4 _! A/ }# r5 p9 L2 MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% F, u+ x0 Q4 e2 R% A4 \! I% eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 ?8 _! N* h( _& P9 e
** Set the serializers, Currently only one serializer is set as( v( ]9 u" b' @
** transmitter and one serializer as receiver.
0 _5 |& _; x; P1 P3 ~' U( A*/: g8 B6 J0 [: Y' ]9 k- ^$ ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& f: ^& U& x1 i6 ?# w# ]5 G0 B, YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* t3 u) f! [- y% A# |: y** Configure the McASP pins
- R' _! Q) |9 p* J. i** Input - Frame Sync, Clock and Serializer Rx
( ?0 ]9 F" v" U** Output - Serializer Tx is connected to the input of the codec ) T! O! w$ m3 r3 N" E" K
*/
! a6 N; q V$ [9 E# r* w4 p4 |- h' YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# c. k' }# O- J8 [+ n/ \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 h( g- z1 t& i. I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) z* Z; s/ W7 v( Y0 p
| MCASP_PIN_ACLKX4 L. V5 I/ X- R2 f/ S
| MCASP_PIN_AHCLKX
& K2 N9 I6 T& t3 d; @9 m0 V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, X2 Q3 K& D+ x- h Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 B1 A$ }% g# k0 j Q| MCASP_TX_CLKFAIL
2 L9 w2 t/ c( ^, c6 @6 b! G| MCASP_TX_SYNCERROR
: x' ?! I1 |1 `, N6 T+ j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 @: P# r* z* s T" R. z
| MCASP_RX_CLKFAIL& p. h+ P0 @1 R& ?5 C( C- a2 o2 u5 y3 c
| MCASP_RX_SYNCERROR
% D, n' S* X+ p6 w% ~5 D| MCASP_RX_OVERRUN);7 K- |1 I1 I# d7 C5 U
} static void I2SDataTxRxActivate(void)) N" J7 u0 T+ I' ?9 y; V: O
{1 @, _5 o5 S& H
/* Start the clocks */. C! T% j- {9 Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* W* }: N/ D- o/ {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" b( E! b- s! @; W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 c9 [* Y& J7 M
EDMA3_TRIG_MODE_EVENT);* {5 W3 S, g$ z/ v$ U, I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 S4 b' Y [# K. t1 N% j8 U+ D
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 q) v% n1 i6 ^9 K" H% O* C% BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( l2 I% F* Q4 C( F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 ?! p) o' ~' V( }$ iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// q; _. \. p* q2 _. L% m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, e& c% `: J" a8 F, U4 q( Q8 LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 n5 A. z: V. h2 [, K( k0 d: o- i
} 5 D4 r/ Q* ~$ G5 c2 M6 j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / u2 U, Q/ H* M% P; v6 P* N' C% Y
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