MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
) v5 x  o9 x3 k$ U- Y! z0 H% pinput axr0,
4 ?2 O' H( @  E( }
+ y# }) t2 c. x8 U8 F  Xoutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
  g. a+ x9 D3 W; y, _4 H

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
5 R4 F6 I6 v& u3 b" tassign axr1 = axr0;

/ M. M; l8 |; F+ w; W% G# R" m) E

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

  i' P& y# y+ \* ]

static void McASPI2SConfigure(void)
{
0 ^0 r' L( b2 E# N4 I. [6 HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# b; c; m+ ?8 D$ xMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
. m; ?# I  D  H% l7 B/ Y  \" W( C$ dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
7 B9 I9 O3 [1 L5 h- n5 a) UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
7 @' L# w; e) x/ `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
  e% o% @. c, H# dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 R) R/ T9 x% \5 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; x7 j  g& J  c5 b5 h0 o2 z0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 X' s, B: b$ z% m1 u& T6 c% Q- _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
$ V  ^/ Y; M3 Q
  ]$ e0 E% o) w4 d, m/* Enable synchronization of RX and TX sections */
3 v  D7 ?9 _' C/ q) V$ |' ~  }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
! o, @' M4 X3 n! nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
  P% b+ [# k0 r2 zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
# x6 n: {6 [( T; J** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
# B( J  J  F2 }5 h6 R& `* A  zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
$ o& h4 B3 ^/ \7 T** Output - Serializer Tx is connected to the input of the codec
' `6 Y$ g4 |* |7 X8 \4 R*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( |6 u: t0 G  |+ T- a| MCASP_PIN_ACLKX
' s6 ~$ U. F8 @* p| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
& f' o1 R2 y( B/ G: h| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( [/ C. s" c: }% y9 v1 w* j( S| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
: q0 L" |( j' o& f' k2 f" |3 W| MCASP_RX_OVERRUN);
* G: n0 P. u. z6 r3 A}

static void I2SDataTxRxActivate(void)
& e6 V+ ]$ p9 H3 D) [1 p9 h{
, `1 ]+ ?1 Q  Z& n+ g3 ?3 S/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
  a6 G- x8 E9 JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) Z8 ^6 e+ C2 I* B, a# xEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
0 y( S; }0 y9 P6 p1 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: O( \; R5 N# f" v4 r$ AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
/ c* P3 }+ b8 w# G8 O! jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
0 @$ T3 H; D3 k$ Q" jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.