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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 _3 ]% {) p$ s% v2 g/ L Hinput mcasp_ahclkx,
; J5 X A4 f! \& f0 O$ finput mcasp_aclkx,. B6 D/ n" u% S5 G1 n! U6 U
input axr0,
( d% X5 a9 C; y$ H. s* ?9 z# |' x$ m2 N0 e& M9 _6 o: D
output mcasp_afsr,5 V- H3 S. z3 f
output mcasp_ahclkr,
2 |2 W2 u* g+ [- z+ aoutput mcasp_aclkr,! ?6 y" w" Z- [7 v0 l3 W
output axr1,
: m0 P! J! N9 i. K assign mcasp_afsr = mcasp_afsx;
v+ b- t' `) A, _- \# ?assign mcasp_aclkr = mcasp_aclkx;
+ y$ h" T, c+ x7 |* |assign mcasp_ahclkr = mcasp_ahclkx;" k( \, i5 M& m3 a
assign axr1 = axr0; 7 S/ z5 z% j6 [- p/ P2 |
# n! W3 O1 t. w% \/ A; \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; Y. K( x) n. M: U. @0 [2 r
static void McASPI2SConfigure(void)
: {1 ]6 e# M9 A2 ~{
# F1 D* @1 f; NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( {5 t% J9 g8 o' j( o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 B& s* c% W6 c: G7 Q5 i& V5 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 N: ] a) j I7 a' D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. @# d$ t2 W" F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- g# [1 j6 o1 ~# R" U/ lMCASP_RX_MODE_DMA);! u# H" L- g- @0 B8 R1 r. b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, [+ U6 J+ J5 Q4 u' U# X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' Z$ u! J. J X4 ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( S# R0 S8 m: f0 w/ U4 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 i) P: R) k; r; s6 B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 {; [( ~4 M0 y' Z; n Y+ q! zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 l- c: T$ {4 ]2 M3 P" Q eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ F/ v% [) e: j8 m U4 T! T, j% SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) O @) B, T6 g* V. K5 E4 aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 @/ a. d. @7 R. g0x00, 0xFF); /* configure the clock for transmitter */9 w9 J" Q2 d/ C; k6 b* z7 `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 u4 w% n7 ~6 Y+ O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 u+ b4 K% m( X' h! k4 C" [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
M, v5 m$ h+ j5 l0x00, 0xFF);
3 g1 C s% ?; v) t: V8 @0 d& l9 y) M9 Q% N r+ B9 ~
/* Enable synchronization of RX and TX sections */
& }- }& F7 D& ^+ d9 m. h+ FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. [0 ^+ z! z9 }; qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 ^: N: n2 |$ h3 }+ c: U D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ p% w( j! J G0 q7 C9 h
** Set the serializers, Currently only one serializer is set as; [/ v1 u# b4 p ^; s+ p0 O0 T
** transmitter and one serializer as receiver.4 U4 M' ~& Q" E" ]4 C
*/
% l6 f. x7 {- _( x, T% cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- \+ R( d) w. e' xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 b& x5 v ?6 B: M: Y K' ?
** Configure the McASP pins 2 [6 ~4 r* e, O9 A
** Input - Frame Sync, Clock and Serializer Rx
7 f- J: r Z4 ~2 p' Q1 U2 t; i- V** Output - Serializer Tx is connected to the input of the codec
2 t9 q% h1 \( {$ n- w p*/
5 N9 u9 u2 j: V" z- iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 V6 `( f, C: u" dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ E( o8 A) D" _) E0 ?: D# iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX D6 `8 d1 {7 ^. n, k: z2 V+ U) e+ x
| MCASP_PIN_ACLKX
" b! u1 y2 x# || MCASP_PIN_AHCLKX6 V7 U1 u/ \# j9 W$ K+ j6 z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! d' e4 W. g$ D* l+ t/ m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 ?, [& K+ W/ ?( z7 B* h/ I| MCASP_TX_CLKFAIL ) M$ H0 f- S( J, j# ^2 n6 u, S
| MCASP_TX_SYNCERROR
% O( R2 I, M+ w. Z L, v+ x3 x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# y! ]* K! U% G$ P5 ?1 Z| MCASP_RX_CLKFAIL
, _* K+ {" `) s6 F% G| MCASP_RX_SYNCERROR
) `+ K) [3 A! p* V| MCASP_RX_OVERRUN);
7 Z2 Y3 J! V% ]3 H: V" s5 m} static void I2SDataTxRxActivate(void)
; w$ T2 t" _8 X& M) t{
1 q8 x0 A7 ] U. H/* Start the clocks */
7 Q" ^+ j6 v/ ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 d) U- ~7 A: i0 ]* f PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ L- T: ?7 ` A4 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( A' z6 S" x MEDMA3_TRIG_MODE_EVENT);0 y2 C, x* ~# ]$ B% g7 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 g; ~( Y8 K) b$ m. U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, ~) o/ P6 z9 T6 ~5 ~% _3 TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# }+ k& S9 e: c! \) z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ u/ v/ \6 P' a$ |: _( J7 S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 \* E8 Z) J( y) F) e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. ~4 A2 w; b' l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! J! k+ q/ {4 k- k}
Q+ B! G) X. F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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