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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ x% c; ]9 I- Y* C% \
input mcasp_ahclkx,# r5 J( y5 h! G) X
input mcasp_aclkx,! O. c5 n7 }5 V5 K! S
input axr0,
* j: h" ?, _, n3 t/ S8 D4 X
2 g% @- H) W& Koutput mcasp_afsr,: K6 Q1 h. q7 t0 H: X% F& \
output mcasp_ahclkr,& S% `" R# @" f% h
output mcasp_aclkr,
( I# p. P& t3 A0 Q' Youtput axr1," z/ r% k S m- ~& C
assign mcasp_afsr = mcasp_afsx;6 i' V" b0 i3 d, Z; o( E
assign mcasp_aclkr = mcasp_aclkx;$ f d* f3 ~! q
assign mcasp_ahclkr = mcasp_ahclkx;7 X |& d3 B* u+ N* X; D
assign axr1 = axr0; 3 d( }" S% d2 _1 f
( `& C7 N# [ G+ s4 T7 N, ?6 A/ ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ p8 R. D+ @' X y! y& F% Ustatic void McASPI2SConfigure(void)1 X& z, M: z- f7 T; \& l
{" ^) ^/ ?/ U7 K9 P- h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 {2 ~9 g) \) h `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) `1 n: P0 J) Z2 dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# I7 Y' G0 j5 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; h; ~" |) W. q. f8 F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! w: J0 u9 Z, n- N& \, q% jMCASP_RX_MODE_DMA);3 D, I, u& e& H: ~1 \# J0 L& [$ B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' z4 ?$ Z4 e) J7 b2 S% ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# s# y. H$ ]7 I3 U( B p2 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # R. q! o! V- ^ j) r+ ^; c+ H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ q5 a2 p4 \, Q) k9 L; D, GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( g- F+ ^$ D9 d& H5 U. R2 W4 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 ~! k# g1 b) C* u$ e8 M3 y" y3 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; ~( k; \4 w' J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 {0 s7 Z8 O( b3 {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ v( X, W5 {* F8 I* y0x00, 0xFF); /* configure the clock for transmitter */
4 g7 ?$ L8 ?! tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& N7 n. R* q X9 ^. r; F6 eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 O2 L3 H0 \8 |) e3 t8 bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- ^# q+ y% ~3 d1 {# B8 J5 y4 }7 f
0x00, 0xFF);# @: |8 ~- E' ~/ Y* Q
$ u. }/ ~* _3 L+ D4 h0 i4 w) V) V
/* Enable synchronization of RX and TX sections */ : W# k$ `7 i) \, W: ^* R: W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' R$ k: \$ @$ n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 `9 t/ w5 f4 ]* S) q; @3 x/ \2 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- P1 ^% F9 i# Y# ]( k$ K
** Set the serializers, Currently only one serializer is set as1 M: M/ G4 s' ]3 A5 K
** transmitter and one serializer as receiver.% O* M4 V! |5 `# [9 F5 _
*/
) {* s8 H- J* ^3 bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, K2 k% [& f4 ~% `: d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ x# p+ L/ c) \5 @6 w7 q** Configure the McASP pins 1 x w1 ~- b$ j }. W& j* Q
** Input - Frame Sync, Clock and Serializer Rx6 k" k# p% q6 D. u
** Output - Serializer Tx is connected to the input of the codec ; I" d( J$ D- `, j3 R# ^
*/
/ o+ t# R/ P! A9 b5 t3 X) u5 }6 vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 T( c. A9 _4 U7 u$ G0 ^8 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! I# V2 f7 `1 D2 bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- \! M6 t! s! y$ J9 B| MCASP_PIN_ACLKX
: Z: e$ v+ k! l) W( s. ]6 ?| MCASP_PIN_AHCLKX
' H* O: g$ S* j7 Y& y5 R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 l2 f( f. Q+ v5 O: D4 \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 y- q( y; r% z* o| MCASP_TX_CLKFAIL
0 M1 z6 l' @$ [| MCASP_TX_SYNCERROR8 r1 D: N) g2 I5 `$ w/ J k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. m9 X1 R6 J' X7 [. Q9 G. x| MCASP_RX_CLKFAIL' K" h6 K/ V1 Y- `
| MCASP_RX_SYNCERROR
2 _+ |, q% s+ `$ y6 s| MCASP_RX_OVERRUN);& j" M2 B/ y! A$ h
} static void I2SDataTxRxActivate(void)
. n$ Z8 [$ h7 ]2 C% N1 O{
- m8 q5 y1 Z7 \ N/* Start the clocks */
8 S# R7 Y7 q" T; y. ~! A, cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 S2 ^$ b! c. c& }" j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& T2 }1 N- J4 m4 L0 L* pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) _* L* j* g- H u% ?0 r$ ^EDMA3_TRIG_MODE_EVENT);: r% z! k) K: ~. g$ g3 l( b& z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ _8 H3 t" G' l8 D: H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* h- G8 G% q% r$ Y; E6 h1 lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* ^* U0 P" Z/ O5 EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* k* F8 @0 ?' x9 q1 Q( X. P7 k3 qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& D- z# G& a+ W9 |4 t8 ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: d1 H) O4 r% T+ p2 _: j5 O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 ]7 u1 M! M0 K2 ` s7 K8 G}
1 C+ y; |: W6 V: v4 u7 m( R7 ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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