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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 E& N' K, W5 o E- y
input mcasp_ahclkx,
( D1 Z; J/ j3 s, h' ^. Y* rinput mcasp_aclkx,
6 I( t5 E0 Y0 O" b8 g/ Sinput axr0,
& `- J7 m5 U# r7 t+ b3 Q4 }6 a+ W& P# a$ \( w } G& R3 W% U) P
output mcasp_afsr,
$ D) M7 F P' a6 ?& r Boutput mcasp_ahclkr,' D6 B* w7 X' N1 z
output mcasp_aclkr,
1 `4 B" c. D- Q' @5 X7 o, B0 s. Joutput axr1,9 u: `) `- e, F l' t
assign mcasp_afsr = mcasp_afsx;
9 p9 S6 I" t6 w& m/ v% jassign mcasp_aclkr = mcasp_aclkx;
7 t9 l/ T" f* G) L# ^assign mcasp_ahclkr = mcasp_ahclkx;8 ~ f" T, A9 @0 E& f
assign axr1 = axr0; . y1 Y! T; w/ ^/ g, Y
4 U( q9 n y. i1 j: Q* [6 @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# e; G4 E* h0 v5 q7 ~static void McASPI2SConfigure(void)* J E. _* t1 [9 C
{2 T7 o' y' A/ g" g+ k/ f3 h6 r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. z+ \( p6 M& M$ DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) _& Z$ {) } F- h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 l, ]* c* o) Y' u( f4 d5 e) C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( e& r0 Z& E% zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 X# u3 {0 H+ V; P; `
MCASP_RX_MODE_DMA);1 z3 F5 y9 r. O" j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 Q" H( @& i3 W6 Y) ~! q5 w! FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 l. z) ^7 f/ I0 B4 iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 g p& A% t0 T& ~) H4 D2 ?6 o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
c$ C- U$ H) P" t! N4 OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 @0 A7 G$ _/ ?" q4 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 z/ o* n+ k! H; n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 ~1 m! ?3 v% E) O# `# O0 W) W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 E0 s F+ A1 X5 u1 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, O1 Z2 |- c( d8 C% z
0x00, 0xFF); /* configure the clock for transmitter */9 i6 A6 }* \2 d0 S& F3 ~- J7 ^) h' d* @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; j% Y8 s* \7 K; Q) Y0 g. v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - e$ ?/ a+ o' V- R% U1 p. r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! ]$ P' S2 P; ?3 g8 U1 p
0x00, 0xFF);
* } \( d( g3 l6 {+ A/ U4 @2 q
$ G# b' a3 E" i: s9 H/* Enable synchronization of RX and TX sections */ ( D# v: r0 v: j4 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 k8 \5 V: |& y- L1 J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' z) I- Q; `0 F; b0 B4 }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" Q' h* u: a) D** Set the serializers, Currently only one serializer is set as
$ F7 J n9 X* g: `4 W3 q. L** transmitter and one serializer as receiver.
7 }/ m6 ~/ ]4 y*/
" w ]6 R7 X" F* dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 S1 r( ?) J5 ]; |8 u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. u5 l5 P0 x8 r) M( ?+ F1 {! Z7 I( ]
** Configure the McASP pins , }9 w: O, }# O; B
** Input - Frame Sync, Clock and Serializer Rx
' C2 c4 I& B6 F' i9 i T** Output - Serializer Tx is connected to the input of the codec
3 b. z: |4 |+ V; Z# f*/
9 a! Q+ s( [2 U$ xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; i: L5 j/ s" z9 GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 t/ u2 E( a# |8 b3 o$ H5 ?& o# X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ [6 I* E+ W0 x7 K$ x
| MCASP_PIN_ACLKX/ k7 T$ Y$ O7 V/ a
| MCASP_PIN_AHCLKX
- L" v5 J- v! I5 Y+ b: i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- y/ w( F6 K; C1 }4 j kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , r1 _; Z0 ^" k* ]8 F/ _4 U9 A
| MCASP_TX_CLKFAIL
* G- O$ n2 M4 @9 {| MCASP_TX_SYNCERROR$ u3 q4 F3 X4 f T8 x2 O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
f- W/ \/ O; y) n% o| MCASP_RX_CLKFAIL
$ W/ a* v3 O7 Y6 C| MCASP_RX_SYNCERROR . _. h$ g3 u2 p
| MCASP_RX_OVERRUN);
8 }; K& `2 V3 N: z- x} static void I2SDataTxRxActivate(void)" q9 P% N- Y1 w9 G2 F$ ^+ E, X
{
5 K0 r' J- l7 M' Z/* Start the clocks */
. B4 Y7 X: h4 l" HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. T) e- S- U# J( DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) p1 D( @: A' k8 ^; nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! s* Z/ D7 _$ m1 ]: {2 `4 H( Q+ R( c
EDMA3_TRIG_MODE_EVENT);9 B* |. \: p3 L3 f+ ~% W" ^$ E0 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ G1 }+ s2 N& a: \% ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 i8 e1 ~9 O+ D k& g( q; SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 {0 M @( P) v/ ^+ [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 H- X: V' j# d% @' K$ J/ O: c% a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 e9 f& f2 g. f, K* m( ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ e4 G: X# d+ p; WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ {1 s8 f5 |" L& y+ H& c- c
}
" q1 s$ R0 p6 B1 G2 h: k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * V2 }/ P2 r: O% Y' X6 D
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