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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 [" h1 P& g4 \. U5 t
input mcasp_ahclkx,' {, G9 {0 E& l6 a
input mcasp_aclkx,
0 L. `+ Z9 U; w1 B. Y% ~. Linput axr0,/ U6 d$ ?8 y$ P5 @2 I
( s" a7 v% x _" _% r& r. j7 uoutput mcasp_afsr,
$ d0 z& _0 I' t* }output mcasp_ahclkr,
6 h; G$ {, T4 e2 coutput mcasp_aclkr,
. f' h. n: W* s) [output axr1,
: `, y* z9 p$ {' j assign mcasp_afsr = mcasp_afsx;
/ c- ? s2 ]7 S* r$ N5 r- Xassign mcasp_aclkr = mcasp_aclkx;
7 D+ ?, R% O; O! L1 eassign mcasp_ahclkr = mcasp_ahclkx;
8 \6 a- q+ x/ q+ \assign axr1 = axr0;
! x6 I4 f" c1 t; D* {- l9 n7 h3 P; P# [/ ?& W+ N2 |+ y4 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, b1 }6 b" L( b* H. r, Ustatic void McASPI2SConfigure(void). G" H" E* ]) ~4 _* \. u0 h
{/ E$ {+ u! ?& K I D; q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) `& {7 |5 A, C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# s& K j/ i! pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ `2 ?) w* X6 `' M$ D6 ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* g6 P1 q2 }+ @4 H d: l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, O1 h/ w" e8 g1 F' a5 @ u. `MCASP_RX_MODE_DMA);
9 |3 l5 T) x6 t) z7 d2 R: BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; {6 y( I4 b- F2 m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ K/ g; U& m* i; D2 z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - s: v8 O9 @) a+ n; w) F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 ?" ~( j: T: E% G5 p% ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& ?, n# y- u- P' g, |$ hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ R; F9 S2 L9 b5 \9 l- o) k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: Y- t+ G) y- A2 c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * ^: I" D7 R7 L8 X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 Y- J' t# f4 Q1 p+ H# b
0x00, 0xFF); /* configure the clock for transmitter */
, e( K9 }. @1 b# [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 z- s: b5 k' l; ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 o6 `6 L! `; g/ A& c( }; r9 vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 u* X" K j) w/ [. `4 G0x00, 0xFF);
& Q' C1 q% d7 j# b
2 k( n% o: N0 ^+ z/* Enable synchronization of RX and TX sections */ ! X1 G6 N7 A7 e/ j8 M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) o1 e4 v, m, W% T0 Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 `* \4 X* T& A, \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' K2 S0 l) r# _3 g/ G( X
** Set the serializers, Currently only one serializer is set as4 o2 o( {+ o* S& c( [- L, a
** transmitter and one serializer as receiver.
6 `. ], Y% Z2 U! o: Q9 B6 M: y& U*/
$ [+ q- y3 O6 U( sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( i; r3 W+ v- A6 _4 SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* x. T6 V/ v" {' Y9 o; k3 c: n" v** Configure the McASP pins
2 X0 G6 s! `2 X$ Q' Q: G3 t3 L** Input - Frame Sync, Clock and Serializer Rx4 c% K. A/ p, C' ]
** Output - Serializer Tx is connected to the input of the codec
; c! ~# B) u" o/ ^*/! c' {. N- H/ y" [8 S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 f0 z8 o0 q/ @: t6 g( P! a* k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! g3 z, ?, `6 j* z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 F" d. V) E7 L| MCASP_PIN_ACLKX1 D% Q) y' N1 g7 Q
| MCASP_PIN_AHCLKX' v3 C: G1 ]7 T7 D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 i+ D6 e. A3 E7 c, ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( ~. @* O% s9 p" z9 E7 N| MCASP_TX_CLKFAIL & S/ n: ?3 O7 Q+ M; w9 b( c
| MCASP_TX_SYNCERROR! o9 |& [# e2 U, M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : l) E3 _* t# q6 f0 _" e0 E! ?& c
| MCASP_RX_CLKFAIL6 W: U& r! L! i {' z) m
| MCASP_RX_SYNCERROR
0 B9 [+ I, T+ F3 F3 P5 w4 b% w| MCASP_RX_OVERRUN);3 f# w) u2 a B" R* N
} static void I2SDataTxRxActivate(void)
3 E- `! [: a/ |2 y, ]# |{1 U1 o- e Z" E, d7 c3 {
/* Start the clocks */ g6 s* m0 {( h5 t( ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ l b+ u# s8 e$ @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& s& }- v; `/ z* i+ kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" I/ `$ s; ^' e- r3 V3 AEDMA3_TRIG_MODE_EVENT);
/ C# o0 o( i W" l/ [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, N3 m+ z5 i$ j/ FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ t: V% f+ P: OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 A. Z! k A7 b5 B1 [( w$ x% MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; A) h% C, ]4 D X; a% A- e3 Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ ^0 f/ I+ l2 T P; i( P" B4 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 V0 Z. ^2 f; ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( l4 l8 q$ w `9 l: p1 u} " x( o& c' X: d$ F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + @' I* E' b5 H* W! h X
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