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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; }" `9 F' _1 j; |8 ^/ X6 Binput mcasp_ahclkx,
. g# }% a' C5 b& V3 G/ ~! Sinput mcasp_aclkx,
! V" T% T# T) T: K! \- P3 iinput axr0,' C' H( l% ~+ r8 c2 Q4 s" ], }& j
# H/ M, ^. U5 boutput mcasp_afsr,
6 x" u6 M. k4 t' C+ `output mcasp_ahclkr,
8 X/ n2 F$ T3 u" h Y, houtput mcasp_aclkr,* m5 X" |2 o5 T, w6 y
output axr1,
3 C6 s, o% S4 u) k% `6 g Y; V assign mcasp_afsr = mcasp_afsx;% w( d3 n& @6 _; a1 E" X9 r9 l
assign mcasp_aclkr = mcasp_aclkx;
- I- Z( M8 t, jassign mcasp_ahclkr = mcasp_ahclkx;
. d+ F R* i. f0 Vassign axr1 = axr0;
2 h9 C5 V! a. |5 C
% ^. ?1 k$ b0 T! ^8 X: z% R% V% _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, T; J t- A' v0 Tstatic void McASPI2SConfigure(void)4 Q) q5 a: ?* H% s3 ~+ J
{8 O( P2 a2 C' ] P9 g: O1 u- L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# {0 m# R* j. K" E2 xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% T" `: L) }* S D) y( W" m, R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ H" \; A L+ r1 ?" [3 {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 P/ M6 k, }& t) e* uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 j5 Q0 W3 O1 Z+ n+ \MCASP_RX_MODE_DMA);7 m- E5 B( b! M0 w8 I) p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 D6 X% j7 ]$ e) r- R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( M4 C# O" d. h z( CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 J, X% k M" E# n7 U1 y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& i& J; D, W0 h& qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * S1 P$ U8 }" n0 E0 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% r& ?1 p: v4 O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 c1 j- N" Z. }3 ^# r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' g7 K9 v$ {1 Q- CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. X1 N- N/ O) Y9 Y* ]5 c3 N1 N0x00, 0xFF); /* configure the clock for transmitter */. a( s% G3 E, n- o" l2 _1 k" ^" E6 B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, Q) s# D- @% B5 {) o/ \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* p& u& `. b8 Q( b7 V( jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) J5 A j) Y$ T+ p" ^/ g& v
0x00, 0xFF);- |# a3 W4 H6 P/ s7 B* e* o
* l# a, m" h) n5 h5 ^9 e u5 \/* Enable synchronization of RX and TX sections */ ' R) {; P9 u7 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- n2 n" u- x9 r3 e0 \9 Y. I1 a4 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, {) R0 |" C; x8 a0 c5 b( x7 y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( D+ A7 { I0 T: R
** Set the serializers, Currently only one serializer is set as
% X2 I5 |' b( S( S& ?** transmitter and one serializer as receiver.
, {9 X' I2 O. Y( K/ j( S3 i N*/
! M" T9 V) x' e, r& HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: M& l4 i: ~2 h9 _/ G* `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! ]: I5 q3 g* J9 b0 s- g** Configure the McASP pins
$ M6 a; A( n: ] k& R0 t** Input - Frame Sync, Clock and Serializer Rx
) y: I" i2 }( \% a* V0 j) \** Output - Serializer Tx is connected to the input of the codec
3 s' F5 T# u% B6 E*/
+ P' Q; r. M AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 ^$ J) u1 g9 D( s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% w7 a5 d% E1 N4 d/ [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( G% Z7 g, X8 w9 J
| MCASP_PIN_ACLKX( }! c6 M5 W3 ?+ H! `
| MCASP_PIN_AHCLKX. X0 r! p' o% L- I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! C" O7 [1 m# W; F% J5 z3 p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 S, X/ \! h6 s0 [9 O
| MCASP_TX_CLKFAIL
& i* S: r/ d5 _| MCASP_TX_SYNCERROR( _% P* f: S# J, S" S S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; i% I9 ?3 b d9 s$ B& b. m| MCASP_RX_CLKFAIL
$ n; e; r* h, W7 S7 o| MCASP_RX_SYNCERROR & a ]( Z# u* k
| MCASP_RX_OVERRUN); v* e1 d" K/ l1 V! f: G
} static void I2SDataTxRxActivate(void)
: @. l8 M5 \, }1 I{
. }0 x8 U9 R) m/ [! H/* Start the clocks */, e# q$ t d) F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) |7 H ]4 J# H7 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# M; D$ ]5 t2 w$ _% ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( C" ^3 i( l: |, k
EDMA3_TRIG_MODE_EVENT);
6 U" U. o( v. H2 b0 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 H+ B# C; G2 t: c7 ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; J. [# |9 m# ?2 _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
I# l3 g+ @( D. aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% {% N8 y9 o' l" H5 W4 P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% _4 _0 e* J( S9 w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# R/ a8 \6 n: Z2 \" HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 m! Z! g! [) r- l}
# z' m! `% F+ w7 E3 N# o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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