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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 o+ K) b4 A, C# j! ]input mcasp_ahclkx,
# j; Z/ L* s5 x1 P4 k7 einput mcasp_aclkx,+ i% f) `2 I% M0 Q
input axr0,) {/ G) A2 h$ Z, j
5 r9 _5 R* K# y, {. Y* g
output mcasp_afsr,
; [# }" P: `) V. W/ Loutput mcasp_ahclkr,
4 a) c0 @+ u- w7 b& p$ b( q6 Youtput mcasp_aclkr,
& I8 _8 L% I# Q% `! k9 xoutput axr1,
: k5 U: t" L% f* F6 ~* N8 { assign mcasp_afsr = mcasp_afsx; M% u5 x$ p! a4 J: \; l, P) w
assign mcasp_aclkr = mcasp_aclkx;
0 C5 l$ N3 X ^" G; Y5 L; P' Dassign mcasp_ahclkr = mcasp_ahclkx;; K4 j' }2 ?0 \6 _1 O* m: P
assign axr1 = axr0; - _8 `6 Z7 z1 Z* n$ A
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 q/ J: t! y7 P+ l6 T8 Ostatic void McASPI2SConfigure(void)
6 }" b: f9 H2 Z) W# ]{
) N. L4 V+ C" }. I3 v% [. Y- K+ _McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ z: h# R+ H, f6 a" g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 @0 T; Q" A5 {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 E! f- B( Y, Y% S4 ^* C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
z4 Y8 @# k0 N& K1 \% T5 BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 G. s- [9 ^" B$ B' c
MCASP_RX_MODE_DMA);
5 Q @6 t- o, _' U+ EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& r/ x+ P) q- N0 n& q6 ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 q) _; c& U; j' {4 M% E4 xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, o6 B, M; M4 o% y2 M4 JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 t0 p& J( G. ~' Q2 w$ F* _( G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 e! T* h+ K! x2 Q0 ^4 c: `: b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ ^' }6 B! D7 V! ~' k. j" L7 }( h6 h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* e+ z6 q* t( ]- @* u' d$ V+ R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ m+ E1 Q7 ?8 m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 V- m8 m0 z9 `0 {
0x00, 0xFF); /* configure the clock for transmitter */* w; q; s( k+ | g7 J, E) K+ G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: S. H% W3 w, B6 d! s0 u, r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 r9 s6 i3 m# ]3 N9 C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& I! T5 }. ^! D% A0 t+ t9 f; e6 r: o
0x00, 0xFF);
0 j. T, q- u* a
4 n6 X2 L1 Q5 `+ S6 d6 s+ {1 n/* Enable synchronization of RX and TX sections */
6 U! H" ]+ I* ?6 t( BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, g: A5 |9 n0 c( O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 P5 Z/ r# V, w4 JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** ^/ u4 u2 p9 t+ R+ F
** Set the serializers, Currently only one serializer is set as
1 Z' ^5 k( O+ ~' v3 D2 A** transmitter and one serializer as receiver./ u3 U5 v/ I2 l1 Z& X
*/
- r$ P+ S# n" X% s% m" qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# ]8 m# h/ h/ bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, Y: q4 w$ F: y( W0 h** Configure the McASP pins ) J v& A9 y5 i! @. _3 ^
** Input - Frame Sync, Clock and Serializer Rx
/ } g% N8 e0 c+ y) M** Output - Serializer Tx is connected to the input of the codec
6 D r" J" Y% s% Y*/
% q6 z% ?* U- \ nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% \! c! J* s# y2 |, z Y2 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' N5 P& Q$ s6 [: Q$ A8 S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 e* m8 a" q. i/ K" t$ i3 F2 z| MCASP_PIN_ACLKX( V0 f6 @% _* {6 Q, l Y) K* X
| MCASP_PIN_AHCLKX* p* j) b* t% [: ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. c# I1 ?( b# h7 qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 V2 [: e, j {( N; c, {: V% K% U| MCASP_TX_CLKFAIL
+ q3 D0 F2 j# ]. i2 Q| MCASP_TX_SYNCERROR
' T9 ~0 M; s6 p ?3 L; {/ u7 L. E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; f- b& N. Y' W$ P; f
| MCASP_RX_CLKFAIL. g8 z P! f7 t( f7 ~1 v
| MCASP_RX_SYNCERROR
: U! s4 t6 O& g, \* R u| MCASP_RX_OVERRUN);9 J. p# m, e$ |
} static void I2SDataTxRxActivate(void)
. H* v9 v, {5 P$ Q7 F3 b{) n7 e9 f; R; J( W' |$ O
/* Start the clocks */
0 Z p3 J v: Q& e1 V7 IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 a8 h( G9 O3 F, j( xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- }. ~9 w) A a* L$ K7 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 E. z/ \0 B( L7 W. @/ K/ X3 K* R
EDMA3_TRIG_MODE_EVENT);
! I* ^3 \; z% ^" [: MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 g3 B, V6 s7 y5 l3 i% _" e+ V; E8 \, NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 d$ {% L5 l1 R/ t( H' j* p+ EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ H. a& d$ h* z9 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% |& X5 P( @/ i, r' K1 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 Y" [9 x* i0 x( R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! b. v6 @0 u/ S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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