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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' W6 @. i. F" W1 q& ]! c& q3 _2 g1 \input mcasp_ahclkx,
, @! o0 b, g7 A! iinput mcasp_aclkx,
' j! o! ?. y' L/ ?* @: Ainput axr0,$ Z7 m; F& b: a+ y: Q$ f
$ s1 P* K+ ~) V* V, y
output mcasp_afsr,
0 C2 |, g/ J1 ~' I; T' qoutput mcasp_ahclkr," z6 R. I7 w$ f% m4 ~. O
output mcasp_aclkr,; J7 \9 }3 \1 D& W1 \
output axr1,
; \+ ?8 F2 u9 e. m assign mcasp_afsr = mcasp_afsx;! I8 a+ N7 O8 w1 J) K
assign mcasp_aclkr = mcasp_aclkx;/ q' l; L& \) p& D/ ~. K
assign mcasp_ahclkr = mcasp_ahclkx;* {8 i6 V6 p1 [4 G
assign axr1 = axr0; % k; ^5 p$ f+ w8 ] e
; y6 ^2 ^- F$ N: ^' p% w+ S( ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & V; L+ o' s* U- D! I `) l
static void McASPI2SConfigure(void)
7 h7 p8 Q5 v% N: I1 k" A{
! l5 t/ h1 ^1 l% |1 f, `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& r1 `1 B# W5 e9 JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 f7 |* n; z9 ^: {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# U) Z6 p2 N i. _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% c, o7 e' o: w0 `% ^, ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: S/ H3 p, V: q$ n' i( J9 UMCASP_RX_MODE_DMA);; T( M+ M5 S8 O. d8 _+ E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% J7 `& T7 m( P* l, k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ x2 j# B# y2 z4 @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# C8 ]- O" h5 M1 {( @+ e( CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 k, P2 N1 S# X0 P' |& v4 Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 \- a/ M: ?) {& j6 t+ {/ O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ r$ ~ r: X, ^0 K0 u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ Z! X1 @- {) f D2 \ V( x- {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; M% ^ Q! M/ W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& O* }- S3 L( u1 P: F' Y. N" G
0x00, 0xFF); /* configure the clock for transmitter */
5 n6 o& d6 K( |4 S: l* ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, u8 |! W/ d; \' w1 rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. w$ e/ p# t. S8 SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 _0 T& v3 p2 Z, ^( X& r; T2 {- J0x00, 0xFF);
& K+ |: C4 p. ~' O1 H0 Z" W9 G% {$ V9 @8 d1 ?
/* Enable synchronization of RX and TX sections */ * ?2 }: d" m+ P) X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 q# n% j: y: t* R6 K3 Y0 rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 V$ Y4 Z) j4 o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
S* p0 y4 J* {# `! c! W: P** Set the serializers, Currently only one serializer is set as
7 ~" N& L; m: _/ d9 _/ H** transmitter and one serializer as receiver.' d" A1 }: S* w% z4 v4 d5 k
*/
8 X! f9 u1 G" MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 t0 o# z* ^" |1 Z0 AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" ^- k( O& m( k# P$ U: j) a** Configure the McASP pins 6 T6 J% q( D2 }- d4 g% w
** Input - Frame Sync, Clock and Serializer Rx
3 K( C) Y2 E0 \( T** Output - Serializer Tx is connected to the input of the codec
- E$ i0 u7 B' T*/: x2 N# G1 y$ h0 X1 u9 n1 d( E0 D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 u" M. K" d* n, ?4 ?- y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 Y. g! j4 v# B9 J [/ S/ n; BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 f; L' ?/ V/ V Y
| MCASP_PIN_ACLKX! Q: p% {- R# n' ?
| MCASP_PIN_AHCLKX; K) [5 y" Q, B' G B+ @0 Y" m- @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 c) D& s/ S1 h% j1 |+ @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. R6 M* O2 F0 B| MCASP_TX_CLKFAIL
3 `; a/ o5 x4 u- n| MCASP_TX_SYNCERROR
2 E/ q' P+ {9 O- Q3 N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : b5 f9 R- F- _2 r, K
| MCASP_RX_CLKFAIL
5 [: B$ x4 c# G$ J0 V$ s" ?" L- A| MCASP_RX_SYNCERROR
8 a8 m# U1 Z6 j4 D. w| MCASP_RX_OVERRUN);0 \# o @# q5 P
} static void I2SDataTxRxActivate(void)6 N) N P* f; x5 X2 R( P$ M7 {
{
# {! p0 G5 z% f& w/* Start the clocks */
2 c9 e7 l7 O. M1 o# h2 ]; zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) F1 m* z5 w5 H/ ?* h+ v! O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 x' V' M: c6 t! U; }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 O9 y6 _& q& B# t
EDMA3_TRIG_MODE_EVENT);
9 W2 `- E8 `7 `( F/ \* VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ l$ ^5 Y6 q% vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 o9 T9 V* P" W' ~$ `8 i; F# zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' a1 E( h: }# H6 U% _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 c9 H X# E1 w* g; L) P8 z' j0 jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 B! k, J! t) v- nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 h% V. ]+ b4 M* s$ Z& sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ V. y3 e& Y3 m4 b
}
i* O9 d6 a6 Z T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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