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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* Y0 w3 `3 n' L% zinput mcasp_ahclkx,: p7 E/ f5 [5 n) a
input mcasp_aclkx,
) m/ G% {4 ]0 ]9 Minput axr0,
5 N, h9 J7 u, d" ?* P
u3 H: l7 F7 `% Doutput mcasp_afsr,
8 s; P3 `: X# c6 |: z# K: xoutput mcasp_ahclkr,1 M2 O2 [2 Q4 d# H8 n4 {0 ~6 g+ Y
output mcasp_aclkr,3 G3 `' Y2 f: A. N
output axr1,
" i6 w" e2 E% F assign mcasp_afsr = mcasp_afsx;! a8 |5 |9 L( C
assign mcasp_aclkr = mcasp_aclkx;+ D$ G* h S3 _' E3 U$ I
assign mcasp_ahclkr = mcasp_ahclkx;
1 _+ C6 a& n" B1 `/ A. G& F5 m: Bassign axr1 = axr0;
) g7 }4 R0 f' W4 A
7 t3 k* N9 G/ B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* c, c1 d/ k" J4 L% |' Q& z! r" zstatic void McASPI2SConfigure(void)- u( @; m- a2 G4 }. @& u
{/ S# D! L5 @; P) S; h' |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ z: @* n/ |8 E' K$ u* a5 l. BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 S8 ?! v9 u5 l: TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 d+ @3 j' i" ~4 @; B% i$ ^& [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" m2 y! k% J9 M0 K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 i! T/ C& ]6 t
MCASP_RX_MODE_DMA);( N. W* x# D% V1 z e$ N( x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; G9 x* K$ H. r+ x# C! p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, L; z8 H. o$ B& F+ u7 o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' s& m$ w& L4 ^8 ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 u, x" S6 K5 f- Q/ ~2 C; @) XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' h' J2 _: A. P, CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 I+ C W/ |3 M4 ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 l1 V$ R0 c6 h# M9 uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 e/ X1 w5 h; ?" e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. P( M# L# g. C% _0x00, 0xFF); /* configure the clock for transmitter */3 _) p3 Q2 N2 [/ e) ?* ~3 T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 A- N0 b$ R! U( `. k: ]) S5 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- M8 T" D ?, e0 {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 y) E" R1 i& d' Q* f: p( w0x00, 0xFF);
8 S& O# U. l. v- A8 w
$ i' U/ C! q* B! x, q/* Enable synchronization of RX and TX sections */ 6 H5 B+ Y& ~' s. p; ?8 ~5 i* x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* {8 u, k9 |" @- J2 I: e0 T% L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 p3 d1 }7 y$ s; w2 m5 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 y9 a/ q/ h0 X7 z) p1 A1 l** Set the serializers, Currently only one serializer is set as
1 W0 K$ F& I& U& g1 g** transmitter and one serializer as receiver.
- {7 K9 S3 W7 C5 ]*/# ` [7 ^, y5 k; j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& j, d$ ~2 Y e0 R, c* f% @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! ], k: z( Q+ q$ f: V
** Configure the McASP pins
( c4 K$ j/ @* ? a5 @** Input - Frame Sync, Clock and Serializer Rx
( G# t1 G% v$ C** Output - Serializer Tx is connected to the input of the codec
; j* H. x9 _* X6 J( b5 K*/3 }$ t0 R8 c0 _# W. h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' f7 e: [( P! I7 o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. _/ R) M: o p2 K7 W* e/ lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 F( P1 x" U( v& D8 t% F+ J8 c| MCASP_PIN_ACLKX' }0 f6 B6 u$ i8 |
| MCASP_PIN_AHCLKX8 M S# z' K+ C" _) F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 v3 I4 a) l) |& ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% b# R' h4 r! ]- o/ ]6 ?| MCASP_TX_CLKFAIL
9 X: s8 O3 v( L# n$ K; ]1 a| MCASP_TX_SYNCERROR
/ |, d* o7 K: B4 g# M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 _3 r F+ ]5 H+ z9 ?| MCASP_RX_CLKFAIL3 f( }2 f; I! F2 e
| MCASP_RX_SYNCERROR $ Z: c1 n U5 H. ]
| MCASP_RX_OVERRUN);& h# Y+ s7 d. G7 { z+ |$ G$ b
} static void I2SDataTxRxActivate(void)$ c O; }3 L2 h& l5 G$ m, X
{, ~* F- q/ Z. z/ e# A/ T" K
/* Start the clocks */
. t# n/ W# N8 r `% ^8 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ K. z8 D, v, y* u9 uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 n. |( W/ M# g7 \2 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 z6 M- N$ O0 a( p0 o$ y
EDMA3_TRIG_MODE_EVENT);
4 Q$ _" e, h' Y/ C4 e6 `# j1 c4 u tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) L3 \: @) @" mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ j$ l# t! N$ f- t5 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 \3 @' w5 W! j/ v3 M: i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 X( l' _$ \/ n5 g9 c! d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: x" E: U ^$ i* ~- g+ F: d+ X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# e0 C: B0 G) H6 Y2 e7 p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& d i' }: N' W3 f, N7 W& ~}
2 X# X3 A$ I# D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 P9 {% N0 G( y, K) S. x: o
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