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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 d3 b( d, ~4 F" m0 Cinput mcasp_ahclkx,
" i$ @# J c' `8 a5 L1 L! ~input mcasp_aclkx,
9 ~- S# k' v, E, F* [! H6 N: L) `8 Dinput axr0,8 Z4 p; Q) N: [- e8 m% N# Q
$ L3 ?( ~) i# T
output mcasp_afsr,( R' [3 S7 S" E6 l4 ]
output mcasp_ahclkr,
. P/ G$ i$ ^0 ~( _output mcasp_aclkr,4 N- V. x3 Y2 Z0 |9 I
output axr1,' l6 [' P# y+ h. o
assign mcasp_afsr = mcasp_afsx;8 I7 P2 J0 Z# z; \0 m
assign mcasp_aclkr = mcasp_aclkx;
. `1 F C0 @$ e3 j. `assign mcasp_ahclkr = mcasp_ahclkx;7 t8 e0 X" f: i/ n1 R- L
assign axr1 = axr0; * J8 t% Z& ]5 w' E
: D" g& n4 }4 h; m" J) L" O: ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 I$ [6 m; p5 }8 R: v# `. l
static void McASPI2SConfigure(void)
- t7 L! T7 V1 V ]{
% V( a# {/ p& t$ aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 |, M6 D9 Q v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. x1 ~) f( X" g3 @7 y5 rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ l# f Q) V m- _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. `( D1 J* o# q7 O2 u& N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," u/ B% M7 |- e( T* H1 \
MCASP_RX_MODE_DMA);& X. b" J9 z- E7 d5 h5 X* Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; L) D4 p# S) u8 R f6 @% p: e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ G5 G% g# u* J3 {/ A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 A$ E# t1 B: a; G5 ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# n+ m5 \1 o5 z! o2 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" r7 {3 p1 y2 z$ hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 @" L+ L3 N$ R, L$ \5 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; M d) ~5 A2 w- h/ VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. I' v; q' O5 I z) [+ G7 f2 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: g4 P. m3 w2 i' P/ o, p W
0x00, 0xFF); /* configure the clock for transmitter */
; b4 o+ M q' K+ hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. c Q4 V0 M+ u+ rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 N' a$ V! j# x+ TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; V# E6 U. K& B
0x00, 0xFF);
+ P1 z1 I3 P+ B+ f- W1 l9 N" h" O" Z; b7 a7 T- I. n8 c
/* Enable synchronization of RX and TX sections */
8 W, `1 R% E4 r8 _- DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& c' L/ M, e0 _/ W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); ^9 o; U4 F5 Y* Z" ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 g- ?; b0 x+ {9 F+ p0 o1 ?
** Set the serializers, Currently only one serializer is set as
4 C8 B- f( V2 J/ B. R** transmitter and one serializer as receiver. c' |3 }3 e9 G8 h2 i6 u
*/
$ z% y; k8 }' {/ PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, z) J6 P! o; e* L- ^: q& ]' ^/ vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! r5 e/ w. W( H5 G0 h
** Configure the McASP pins
- o z6 N+ c+ ?- m** Input - Frame Sync, Clock and Serializer Rx9 O9 U* j& }& V" r$ z" v5 D
** Output - Serializer Tx is connected to the input of the codec
9 \' N: f, N- D+ v*/* p" Z. h/ s! A; H4 z& z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% |9 y( F' W: u0 t! l* Z( KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 r: w, y+ q9 u: V) LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; ^) R( `; f! y# @
| MCASP_PIN_ACLKX
1 ]* h% g& p, k" R" D9 `| MCASP_PIN_AHCLKX
0 u) k+ w+ @/ Q2 l; O3 E3 W; P0 x5 k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ M) c; G& W" H+ o6 l5 GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 d; I2 l" C; O% E; E| MCASP_TX_CLKFAIL
' ]. B% @ s# Z| MCASP_TX_SYNCERROR
, w1 I2 W& ~; f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 R& c& n% Z4 W/ N5 x `4 Q| MCASP_RX_CLKFAIL( Q5 l" V6 J6 }0 E L5 d9 m! f( c
| MCASP_RX_SYNCERROR ' ^$ F% o" x7 P7 C
| MCASP_RX_OVERRUN);
+ [- }: T! y# N% ~: C4 L ^3 A$ ?) B} static void I2SDataTxRxActivate(void) J$ a5 b) P: W/ J0 k6 j: S
{) m" \8 ?" N4 B9 f4 @
/* Start the clocks */6 ]% d! h- J# [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( T4 e( }3 ~0 d" jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 {! N2 S& R0 m5 T0 W, D5 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," |3 M3 r9 Z$ Q
EDMA3_TRIG_MODE_EVENT);" }; {/ ~& S6 K/ U7 S! B9 D% `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 q9 E$ [5 c1 I j. j5 g( x0 A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 M; C+ P+ ]) L, g7 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) w2 O/ _0 U9 p2 F4 `! C9 [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ f/ k d" U2 w% t) r0 ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 Y% P. | w# T! X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 w& {" L; f8 V$ k0 W Y: K1 o6 i# qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 B1 }9 Y M$ y
}
6 M) V" W. f: x6 K! S8 y( ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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