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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- ]* W/ v+ l/ g, x0 y
input mcasp_ahclkx,: W3 g* r2 ?9 ?6 {, q
input mcasp_aclkx,9 c ~& D1 ^1 _( J5 }# F, J, H
input axr0,& {0 ~8 c, w5 H8 o
6 h5 A! l' W7 u5 Coutput mcasp_afsr,
9 S& v7 J" q3 X; \output mcasp_ahclkr,
: O% q6 |* [9 N0 @0 moutput mcasp_aclkr,
, c+ s; J9 V1 r7 ]% f0 Soutput axr1,5 v6 r: g9 {8 W$ B
assign mcasp_afsr = mcasp_afsx;) L. M2 Y, [' v
assign mcasp_aclkr = mcasp_aclkx;# a5 W2 V5 s9 f% B5 @3 T8 T& j4 k) p
assign mcasp_ahclkr = mcasp_ahclkx;: [. e, g0 w* U8 @
assign axr1 = axr0; 9 b9 t' C, r. g" ?- s8 Q( Y
' u. ^' E4 l) f/ d+ {4 A8 h6 h1 Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 K) U' Y3 U, Q7 N: qstatic void McASPI2SConfigure(void)
+ ?& Q G/ T m+ Y7 m% v5 m8 `7 Z{
. |' {2 o0 \" TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, W. P% L2 O' v$ `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* ] c. P2 P5 f! j/ d7 i% OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 @( W: W. l9 {3 r+ L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 F" l1 p9 U1 W* d5 N, K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: d/ _) ?( R( H' T# n, {
MCASP_RX_MODE_DMA); a7 I& c" R* {4 k- i6 y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ k. M0 i# }) M; p, J8 i$ B! k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 M7 J0 ?# w% b% P5 z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' |* b6 y/ Y$ {3 Z+ x( b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 v; F2 Y' B+ c, g+ w0 LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# t; g: N4 v; v+ w' b+ wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 ]" F* m/ d6 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 O: Y' e* P2 q# JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 k0 r) { R9 Z' v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 Y. a$ {! y! V5 ~' O7 B
0x00, 0xFF); /* configure the clock for transmitter */
E1 |* g- u: RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: a7 q& W3 e q9 L1 J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) k! B( P) X0 M1 K, R) WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& S3 c# y7 n- r i0 ^/ s
0x00, 0xFF);& [- c3 F- Z# K
1 W! _% O$ B Z& ?
/* Enable synchronization of RX and TX sections */
W d* t+ `8 ~ U; h: ~/ Y2 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# `3 J% H# P! i; e# FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 O9 k7 ^3 S g+ q, E4 J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' d: T! L' g0 @ Q. B# _, u
** Set the serializers, Currently only one serializer is set as8 C6 {3 h) `0 k2 l+ _! j8 Q& a
** transmitter and one serializer as receiver.3 U+ E+ S" x$ S
*/
" j8 g5 ^3 J. _' r/ gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 Y+ R& _ s O+ R1 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 S1 Q7 O1 M; \$ [** Configure the McASP pins 4 l2 \9 f1 i3 t& C; r$ U7 b
** Input - Frame Sync, Clock and Serializer Rx) R( ^. L6 T9 }
** Output - Serializer Tx is connected to the input of the codec % K5 }; r8 I" O: ] |1 y
*/2 o$ Q% Y. o# a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" }9 L2 E4 \" B7 _% t# j; u% v; o, oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ Q+ k% c! |+ a0 C5 i& O! u! o$ cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 ~$ X6 q3 W+ l" ^/ t. m| MCASP_PIN_ACLKX
8 T1 L3 C* N; D3 o4 A2 U| MCASP_PIN_AHCLKX: g" M. h8 u! x3 \4 |, v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* t' c, r4 w: y' O- j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- W2 e- [' Z+ Z+ n$ V9 H| MCASP_TX_CLKFAIL ( a3 d) k/ g C9 A: A
| MCASP_TX_SYNCERROR" W2 q4 y( r& {( h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / F k0 n" V/ f4 `8 y9 H) o6 m: Q
| MCASP_RX_CLKFAIL
: Q/ E+ s; P' V/ X6 C% j" y% ~ A| MCASP_RX_SYNCERROR
$ t/ b6 R, K2 M6 F5 ]* ?7 I4 W| MCASP_RX_OVERRUN);# `( E3 L- e. V2 Y. s! X3 m- L
} static void I2SDataTxRxActivate(void)8 E8 G/ u: K: a3 y, F. w @8 O
{
3 j% H, P5 B% X" g4 k* [/* Start the clocks */
, c4 P7 h' H3 J2 b6 T/ {0 Q+ |/ yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( z! \) O7 N) ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 f* C% e# m4 O% e( @3 T3 S' h! dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 j: Y d6 |# ?. zEDMA3_TRIG_MODE_EVENT);
7 h, q2 T& Q% X4 T5 {8 c4 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( Y& b1 R3 P2 T ]! cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 `; s- u6 [8 ^! }3 Z8 `* eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
f2 x" G: ~8 H' H! GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* B6 G7 e& D4 owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 Z) Z( E- _, z7 o- l0 C4 wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! a( ]: v" R& x0 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 a/ y" a3 B. ^7 o- i7 [ R} ) c$ e. C7 h& }' B& `4 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & Z3 ~& ~! C2 N2 z
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