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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 h- `/ `2 W, s% J3 |input mcasp_ahclkx,
! V4 r# A( c# l; n% s4 o( g! c0 k; cinput mcasp_aclkx,4 V5 I8 {3 a9 p- u) \
input axr0,; m3 W' d2 L$ n, S
& {0 ~1 o( z) _2 p
output mcasp_afsr,% I0 t, h; A. s' k' v) s
output mcasp_ahclkr,: @3 { b% P" e: C
output mcasp_aclkr,
" Z1 M$ s5 _) ^: O$ Toutput axr1,4 N( [2 T- t5 L b
assign mcasp_afsr = mcasp_afsx;' F! l l2 H% a
assign mcasp_aclkr = mcasp_aclkx;3 K; r+ F3 p% Y* {
assign mcasp_ahclkr = mcasp_ahclkx; f/ g" K1 w: Y
assign axr1 = axr0;
' o! Q% s- X5 `2 T3 l( x6 l! q
1 D4 |- W) l4 W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: b& a. T- }; @- Qstatic void McASPI2SConfigure(void)8 l; a# e8 k3 _. a4 Y
{
; |- H' ^8 k5 B0 jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ S1 R$ L! S. XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 L. k8 G1 n% L* k" K4 M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 o% Y* A- C3 ^1 v. Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& R0 Y$ e, ?6 V/ ~, l: A L. OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, r. P e" g; j( x$ V/ o1 Z0 L
MCASP_RX_MODE_DMA);
8 U' C: e& o' ~0 LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 [- m3 i( P/ JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( }* B6 u0 U B! ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( A6 U9 p# R% v% K; o7 Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ x0 a& K) w: M, `5 f" N( VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ C0 p4 h2 u8 M* v: H0 `) A, Y0 fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 U1 u- y+ K/ t4 Z1 D7 L" L; yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& |# B) T) N7 P; X( f- fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, w2 `5 z# t3 I5 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% K$ b; l2 x9 i* b
0x00, 0xFF); /* configure the clock for transmitter */$ I7 i1 A% _- C2 S; R7 w' Q1 K% R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 o4 u; D$ t) B; JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 Q9 j5 ^' g1 v3 W. v2 J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ }0 U* g" P/ \/ [4 Z0x00, 0xFF);/ v4 k9 `3 _; u: T) N- Z+ W$ j
: _- N4 c- |6 y) j' d5 X
/* Enable synchronization of RX and TX sections */
" Y; Q9 {) K# E7 OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. d0 Z" m; r" _& n2 T; A( pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 h8 r: m0 |$ H5 U& f/ i5 ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& r7 X+ C4 W" @4 t" V4 {2 g4 A** Set the serializers, Currently only one serializer is set as
7 {0 e8 w5 p, Z% \ D: c1 i** transmitter and one serializer as receiver.
+ @+ Z& c2 a/ }5 C*/% d, ?$ `2 h, c2 R) w. h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
z. E. m. i) }5 I- z& M! k% E8 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' z9 p2 n/ l3 v( k: `
** Configure the McASP pins & t* Y% k# g, l* q3 E$ }
** Input - Frame Sync, Clock and Serializer Rx9 ^1 S2 F% K0 R
** Output - Serializer Tx is connected to the input of the codec " G$ E9 b" ~. b' O7 W# A+ A
*/
4 B" _) P N9 v2 s1 E# k# QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ F" G. q! h: P Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, _7 h6 S' Y8 M6 sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- _/ N$ `! Y. d$ M/ K- J| MCASP_PIN_ACLKX
: m4 b9 ]3 ^2 T7 || MCASP_PIN_AHCLKX: W, z$ d: l+ F# |& c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! R; ?& t( p7 I1 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 [5 l3 N' v; H9 E* F+ W
| MCASP_TX_CLKFAIL ( t) P& D# t: h/ K
| MCASP_TX_SYNCERROR
8 k5 p0 @3 T7 g2 Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, v% l* I9 ]/ M, G+ r1 w| MCASP_RX_CLKFAIL
% ^" t+ O/ s* U. R# W| MCASP_RX_SYNCERROR
% x2 ~8 V5 ~$ c+ `1 T; V| MCASP_RX_OVERRUN);
- `9 f% Q# h& f' M# x# O} static void I2SDataTxRxActivate(void)
' b: e* w0 g2 F% u% M( D{( g! z6 l/ F# e b9 W
/* Start the clocks */
" H4 B1 u" T/ F( J* s3 nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 g5 S7 ?5 T- F9 ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 ^5 J: K- c$ i5 A; T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 W. _& u# Z ~
EDMA3_TRIG_MODE_EVENT);
/ r, k4 j) k& o) s- Z% }4 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% x$ \& ]* e/ ~/ @! C* _8 ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" ^ m$ E9 V7 f( ]% pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! ^6 L" i/ g9 X+ v$ d& m0 [+ gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ A( T3 n' B) N. c4 p' Q; {- \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: P7 @( F. b' w, V& l& Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& c: Z0 N, V9 }( y! O) o0 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' V1 F; l5 j6 x8 ?, }! H$ @- Q} - _; A7 k* u" ]. G$ Q+ F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; Q0 }/ H) r0 r. `$ A* w- z1 w3 E/ Z# r* A
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