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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 e- r$ }, z9 e5 ^+ A3 X" _# B2 r) R
input mcasp_ahclkx,
. V8 L7 ]( f4 S' {input mcasp_aclkx,
9 ]8 c2 Z9 R+ o( Oinput axr0,
6 ?5 ^" a) K& ~8 S* Z/ a9 T* X2 ^ j% J0 |- |' E. D6 j* y; D
output mcasp_afsr,
+ y0 _+ R. h* `( j' ? `output mcasp_ahclkr,, P. S. \: Z' l% w
output mcasp_aclkr,! u2 ]2 {' J' w
output axr1,
1 v5 B+ ]+ v+ t* a2 t0 M& c: Y assign mcasp_afsr = mcasp_afsx;1 m' A6 h7 z) E: r. u0 c1 m6 C, j
assign mcasp_aclkr = mcasp_aclkx;
, X& y1 p# K: w1 G3 y0 U( Gassign mcasp_ahclkr = mcasp_ahclkx;6 U- d: @! l+ P( U8 q. \) ~
assign axr1 = axr0;
- }9 e& u6 o$ C) O! p* h+ G3 O1 t7 q* C/ H! o. O) E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 R, G( ~ H8 h8 ]1 @- J
static void McASPI2SConfigure(void)/ _* J0 x* A, z3 ~
{$ T/ H: Y7 P: u4 }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 n F! u+ l7 Q. i; _8 R" N2 A( V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ ]5 o! j! F3 N( s0 j# X. o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ j" {% H& r( d3 Z# V7 o. wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" I+ c: y- K+ ?4 k2 NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. l/ |& G# y K1 L: e! x# \ YMCASP_RX_MODE_DMA);
: ^9 Y. F1 N$ R; }1 x! qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, `7 ?) r) d+ f# ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: n+ g8 Q7 O, l& CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 `6 s4 Z4 ?* b% R0 P% N9 I9 iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ y8 x) v4 ~, q' S3 g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 a6 {8 `' O* w+ w6 M! c# `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 U) X6 q* n2 R5 [4 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) N( O9 y2 f) r5 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
E1 S7 t: Y8 p% z, C" m' yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: ?! u! V2 }, W
0x00, 0xFF); /* configure the clock for transmitter */, G( u+ T. P7 c+ z" x5 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 V* m/ d) X n9 S# |8 ?" c2 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- L' u# ?7 {$ `: o+ EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 E- x: y! N8 n: ?# r5 T% j0x00, 0xFF);# H3 S, W% ^% Y4 k1 r# H
) l( `2 r" M! e4 Z% {9 \/* Enable synchronization of RX and TX sections */
! Z4 t! r7 V G+ w- s9 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% f0 ?5 O& w" [* m; R, V) k- G' t: ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" K! z# x6 {/ X1 c4 H) r TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* X8 r4 l" E4 C
** Set the serializers, Currently only one serializer is set as7 Q3 b# i2 B) C! I' I* |
** transmitter and one serializer as receiver.
3 g8 d# h! w% `9 L% _0 D! E*/# n) V! r. c# S+ V& c# P. Y* P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 m9 h* Y6 x8 f5 y- y9 ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 r! K6 [* {% T9 n" g; }& X, N** Configure the McASP pins ) T2 _7 e0 z% Z5 b+ {% J
** Input - Frame Sync, Clock and Serializer Rx+ o5 J* U# D4 `0 e( y6 `
** Output - Serializer Tx is connected to the input of the codec
O N4 q9 |$ z) h' a4 i* v/ d/ d*/
5 d) \" n D6 R) c: \- ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 b' }1 |, T# A5 ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" k& f( W: p1 [- ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* F+ f& S9 g- K) j% Y+ w
| MCASP_PIN_ACLKX G4 k# S8 K+ N5 } L/ e
| MCASP_PIN_AHCLKX R2 y: Q' c. N6 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 Q- `2 x5 ~; c- e2 g) J) E/ ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - t9 Q: O( v4 l9 J* O2 T5 r
| MCASP_TX_CLKFAIL
& C. f3 H- ~: f. y' B/ D" X| MCASP_TX_SYNCERROR
3 _! R' \) a- C1 j" `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . E, X7 ^% p9 D7 c$ z1 m
| MCASP_RX_CLKFAIL4 U6 e2 ^1 e7 v/ Q" T
| MCASP_RX_SYNCERROR - h! B* m6 g5 V2 ~* Y$ n( ]
| MCASP_RX_OVERRUN);, S D* f P$ ]; A, Q# t
} static void I2SDataTxRxActivate(void)
* I, ?; H! h: j8 C& [$ F{6 G$ `7 z D) {1 k$ L7 p Q
/* Start the clocks */- @' i7 p8 ^: [! ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 R; n: w. d# B, X( X& R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 d+ G; Q9 z) L' G3 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ ~. ], x4 f5 r g2 X" i
EDMA3_TRIG_MODE_EVENT);
( ^8 J" w: p% u. f) d' I1 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' o1 k1 {. P6 y9 R1 n2 @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
|" |8 N' f N1 Y) `0 s* a+ BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 |$ ?; @0 p1 k* t7 G$ O1 [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ U) g9 K0 d5 V2 F6 _! d0 A! J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 l. |' _' `1 X1 pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 _5 t$ X: Q; M; Q' e# ]* wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 B8 |2 M6 B( {4 O# `+ u}
( S- u" l/ G8 O' m' C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 m" n1 y) Y, d% t- D2 D
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