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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 E7 l) ~ j" L; _! E1 |4 R; e/ oinput mcasp_ahclkx,* ]$ M2 f4 {9 P7 Y R& p
input mcasp_aclkx,7 M# N+ G1 S# R, U6 G }
input axr0,* V# \/ a; z& I P3 l5 l
3 e) _- `3 \/ a6 D. a) B: {; youtput mcasp_afsr,
* H! O1 }: j- m0 \" ~output mcasp_ahclkr,
& r! R* M5 z6 T6 I$ [$ \! zoutput mcasp_aclkr,
% p( V/ O$ y; |' Ooutput axr1,
0 V) m0 L# c6 ]0 W assign mcasp_afsr = mcasp_afsx;) [" I) R( z* p% z/ J C: T' `4 N2 A/ r
assign mcasp_aclkr = mcasp_aclkx;
5 m9 Q! \. r' Y i+ u0 @: massign mcasp_ahclkr = mcasp_ahclkx;; o$ w1 V$ q2 ~; n! z5 c* Y8 d/ R3 t
assign axr1 = axr0; 1 G' G+ P7 V& v2 V; v6 ]0 q3 K2 A
% n7 m; C9 k/ @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 ?( b6 p' e' ^, Hstatic void McASPI2SConfigure(void)
' K2 Y: K1 I6 }+ j{6 T1 O4 u; j. {2 _( G* s- k& O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 d0 {# `; [) c, k3 }$ H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 Y1 O( S7 s. ^0 @ h$ V) k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% X' E! X& S7 J8 f3 k' _* HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" {/ D+ O1 v( \3 z0 k5 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% r# M) U: n! IMCASP_RX_MODE_DMA);
; \. [# t8 j' t6 y @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, ^4 z0 i: u0 ~ ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ g/ ?9 c1 E) t1 @* pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , F1 U5 s! T% e3 D# G+ c# O* [9 a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; d* J) w0 g+ a6 b0 w5 Y" ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% |: @7 ^! G' H* OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: `5 x3 I+ Q0 x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: |$ ~9 f( l% X3 T) L7 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& y8 _, j/ A& k6 uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- Y" G A8 q. g" y: k0 }( S3 K0x00, 0xFF); /* configure the clock for transmitter */% w1 E( Q/ W# M" @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, W; Y: |7 R4 M2 a1 r/ }4 E. l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ \; @5 t6 s) DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 z7 ?. T: }% u: Z. F
0x00, 0xFF);
* H: I7 N/ f$ \3 M/ H9 I( ]9 \0 q
, b+ h$ O2 r0 }/ N% k% z$ M/* Enable synchronization of RX and TX sections */ , ~* K$ A0 z% }2 z* b/ [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) Z4 v) _1 z- z Z4 t [( CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; E/ I6 n: a; [2 WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& V+ U. D, |, i8 c
** Set the serializers, Currently only one serializer is set as
7 ^+ h* Y+ z% p) a( j$ E: F** transmitter and one serializer as receiver.0 _, u. O! `* a% N9 W1 G
*/
" p% a: h0 R1 A5 |0 YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 h. A4 Q* b$ O4 ?; S' v: W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. I5 N/ M3 R+ G# a** Configure the McASP pins : ^" `: d& C2 v* Q0 `
** Input - Frame Sync, Clock and Serializer Rx$ d" y5 o# u$ R" m/ }/ b- ]( R
** Output - Serializer Tx is connected to the input of the codec ( k% z' x( Y3 s- {3 G; e
*/5 w j/ w4 \3 P# E4 \1 K' R0 Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" G, R5 c; j' i% q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. \: b) z, }. ?( g! z8 W( jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) Y, ?1 I9 T( |$ ]8 N4 q& C
| MCASP_PIN_ACLKX
) m% d2 f1 Y; d# g| MCASP_PIN_AHCLKX
* G$ [5 {/ I7 Z( G3 [6 v/ }0 M* f7 H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! r, n: n4 |% m; m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 v! b8 K7 X9 A9 K; U$ l9 b| MCASP_TX_CLKFAIL + G, Z* L$ c; [1 g4 r6 n+ |6 i
| MCASP_TX_SYNCERROR
4 T, v& r) m5 U/ l. t5 m* C) \. J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + y# K% N$ K$ f8 c* S. g8 o& {
| MCASP_RX_CLKFAIL
. P; O8 T$ V# e' g4 T0 E: u6 ~ D6 t8 W| MCASP_RX_SYNCERROR
$ c9 m# ^+ e% \, ~0 v/ \: h6 E" p6 d$ ^| MCASP_RX_OVERRUN);
0 |- B6 z# p8 i1 t& r} static void I2SDataTxRxActivate(void)8 E, J8 |( E. a
{
, `& S. ?! F7 p) D8 g( @/* Start the clocks */8 ?1 t8 o8 D2 o" n% x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 F8 t/ H+ \! d9 }1 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* }1 E# Z, c5 x& x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. i! i/ L: ^' ~1 _
EDMA3_TRIG_MODE_EVENT);! y) f% j) Q: @1 }) N5 p1 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! U. C+ }. d: |5 F! a3 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 ~- L7 k g% A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. ]) ]3 [2 Z9 N4 }- _9 }( {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' z2 m0 v2 D) Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& \& m% w" g! j4 s, j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 ?% q* g% h! q' MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! W' v7 ]8 f, u& ^2 d2 A} ! W$ Z. k. U) z: ?' T5 g0 f T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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