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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' X- ~, w1 m [ L& \; `input mcasp_ahclkx,
. g, m; Y& O, H8 I a4 D9 I: X, F* @5 jinput mcasp_aclkx,, F5 v3 A: \. K- y; P: w
input axr0,
1 B" a8 t5 N7 g( Y1 d$ E K
% p$ u G- l" L; aoutput mcasp_afsr,
" D1 N7 ~: ?- y m( v( Voutput mcasp_ahclkr,8 k2 }' d" M# j, S8 ^. Z
output mcasp_aclkr,
4 j" u8 t( K! O3 Z: ^& Aoutput axr1,8 s% a$ A4 R w3 ?- w
assign mcasp_afsr = mcasp_afsx;" ?# t6 l X4 n6 R7 Q) y
assign mcasp_aclkr = mcasp_aclkx;, k+ f) H- S; B- Z0 U
assign mcasp_ahclkr = mcasp_ahclkx;' t8 m+ W6 Y0 V5 Z2 o. A& l- ^( j
assign axr1 = axr0;
; |8 w" M0 T A+ r& q" w. ]3 e7 V# c+ h/ a. v/ m/ K9 A u4 q. r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 G: ?/ d- P5 t! ?: ^, ^static void McASPI2SConfigure(void)
# ^5 p5 Y( M3 W& ~7 J, [{
7 T; ^% @1 }4 w' R9 AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 `7 L' |0 V2 }4 D: DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 R- d; q) u! I' O2 EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, L( G- P+ W3 L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 k2 `. w- `% S6 g6 \" D& x5 LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ M! ?* g: X9 w3 M8 x# U
MCASP_RX_MODE_DMA);
, [: F; b$ w: W; C, T8 O' VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ o& A0 |1 k6 B* ?/ ~4 i* S$ u9 VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 e& n" U/ {$ vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! Z; T9 g6 O! ?( m8 ?* L: j6 A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 M. s4 C1 S8 q9 q" c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # `" q5 _+ {! w6 W7 S1 P$ s" a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 F& i. o2 z3 e6 x* w+ ~+ f9 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 G* A. S# [$ t( L: c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ P% y& H0 n/ Q5 p) @" `3 a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 P4 M8 V" [5 z, c7 ? \6 t
0x00, 0xFF); /* configure the clock for transmitter */7 p7 b2 D( y+ x5 W3 B+ Q6 C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' k* Y, J6 L+ D. CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 r" `. o& w" N3 IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 x2 E8 |7 l- c. X! C" ], g4 o
0x00, 0xFF);2 l1 f4 Y1 \( x! H# `$ P5 S P
0 g( V- C: p6 p* {/* Enable synchronization of RX and TX sections */
3 y* R2 z$ k9 t$ X, ?; |5 T% s0 S& d7 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" X0 i B X1 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- `% Y/ r4 j) X* S4 v, X yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 S% i1 \( q' [; \
** Set the serializers, Currently only one serializer is set as
7 O2 \. [/ c( l) O** transmitter and one serializer as receiver.
: M% v' n# g8 s*/2 u: j" \5 M" H, D, r" k' f a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 u8 k7 s+ C8 V0 |: U9 v; XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** a. G, K) Z/ _9 o
** Configure the McASP pins 9 v4 K1 o+ [+ {9 H1 X. _
** Input - Frame Sync, Clock and Serializer Rx& c$ W) s* P; l5 ?7 B. C* H
** Output - Serializer Tx is connected to the input of the codec c) W' [0 Z; g1 N; Q
*/
% _; }; D* B( B* oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( m6 J7 I& U0 f$ O& T! m" C% v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 ~3 M4 C% z' N2 }" W5 t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ p+ u s3 [8 Z# [
| MCASP_PIN_ACLKX. K M$ `* M/ }% \6 W4 p5 r
| MCASP_PIN_AHCLKX$ o. {4 v, N) o2 P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 a* x* T7 p2 w1 l3 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! s q5 v- T/ C9 W( w% O0 n0 g/ v
| MCASP_TX_CLKFAIL
4 `5 B* I1 q O! q| MCASP_TX_SYNCERROR8 Y# L M# Y0 x: H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 y5 b- N5 K5 Z& i+ T| MCASP_RX_CLKFAIL
: K" p9 i: Q' a0 O" q/ i6 |3 s: X| MCASP_RX_SYNCERROR % ]0 j3 d9 z9 T1 |8 d2 r" p/ n
| MCASP_RX_OVERRUN);
! {3 ^* s! \: e* J} static void I2SDataTxRxActivate(void) B. b0 g4 R4 a; h5 I
{3 b6 b" {3 \0 R- `$ L. z ]! d
/* Start the clocks */
! ] w: G0 | E0 g7 \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, k) z+ n. ], C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 c: K6 {8 Z( k; M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 I5 T! }* Q2 TEDMA3_TRIG_MODE_EVENT);/ o! T% @2 o; E, F6 z( ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 F" h5 q; _5 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% L5 G. `, ^/ TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# N6 W& h# w hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% P# X# q% e/ u7 q" {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! t8 T2 l" f/ ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 K8 E3 B e4 |. o A8 o+ H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ H! o) z' d$ z, L' ~3 n- \! B0 ^
} 6 q Y" ?+ n# l' X& D0 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & j( e3 V( s, }' J
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