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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* b" q7 t6 N3 ?/ l" C7 K
input mcasp_ahclkx,
; E& |+ p U! |% |5 rinput mcasp_aclkx,, ~1 f! ?0 ]' t# O3 @& a
input axr0,; S* A. e( X( ~5 n( P" D( |" M
- i! I/ \( s( z$ T# E& O2 J- b- Zoutput mcasp_afsr,
" O# L0 T7 H/ k7 S& voutput mcasp_ahclkr," r" K$ m0 D( `. n8 n) Z S
output mcasp_aclkr,
& C- y+ ]4 U- _# zoutput axr1,
e) u& s- ~( M+ J' f8 F' k8 l0 v assign mcasp_afsr = mcasp_afsx;; ]9 s4 P. @5 A0 K! `: V
assign mcasp_aclkr = mcasp_aclkx;
4 H& |2 j3 s: C3 L% M# Z! b' nassign mcasp_ahclkr = mcasp_ahclkx;9 h$ v* Q, T6 v- F1 ^* Q( Z: Z: \- X
assign axr1 = axr0; / N3 F U, c. O' l; ^: ~
, L8 g! s; j4 y v6 `- [1 e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % {; g' L& z1 U6 o0 I) _& j+ q
static void McASPI2SConfigure(void)$ O7 D$ N$ E1 I. u% ^, a5 Q. l; a
{
$ A/ K/ w" l: _$ A8 g. hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, }3 \, W4 ]& gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 K7 ?. ?- v+ F+ G: ^7 w# _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ @. u* q% N& f; R2 I9 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 m ~9 w( L' g) M1 c2 Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, m* |4 Y- M. l, yMCASP_RX_MODE_DMA);
3 j' H/ F; H# m1 a1 Y* pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," E) K7 F6 P/ E3 i& T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 W% e& f6 ]- M3 M+ v5 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 [( y; ^" w9 k) qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 t$ Z& S6 k w3 V% C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 {. n; ~5 ]% D s* @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 v& s2 N* s7 V+ W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& x! @! s/ a8 q, {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% s8 {# B, n9 ?& J" e' mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' x' Q' p7 d' A6 P, T9 a) _0x00, 0xFF); /* configure the clock for transmitter */
$ X; W9 e+ j- c7 D7 hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ k4 T' s$ S* uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 _% z' v2 u" }( PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# A4 P! g0 g; `# G2 v0x00, 0xFF);
% c" [4 F' O9 z6 x3 h; l4 u1 l, m! b* H L4 @3 |* H
/* Enable synchronization of RX and TX sections */
& X$ k+ F; b2 ~! ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ c* R# X5 R6 g$ v6 M% IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# _5 [3 d: E. w6 u" P5 X bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 a. ^! S; E, F. T4 N9 D. q
** Set the serializers, Currently only one serializer is set as
+ d1 y! u( F/ a- y8 Q( l6 k9 q; V** transmitter and one serializer as receiver.( o5 v$ \+ B4 N6 X
*/ j# S" M2 ? h, f+ |; V0 k* y+ }- g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- k% k& G w2 p* B( r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 B4 t9 J) m- v o) Q" r- M
** Configure the McASP pins
2 s$ ?, X. N% o* m** Input - Frame Sync, Clock and Serializer Rx& y D% b3 k0 {( R% {8 R% y
** Output - Serializer Tx is connected to the input of the codec % N; d3 @ z8 e) o; Z0 Y+ B
*/0 B* I% Y( P5 _( r$ f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
i1 M) X- U8 q/ TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; e' m. ]5 w( q3 |6 @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- Z; K4 D7 P: t' F| MCASP_PIN_ACLKX% X7 E/ @8 @8 B
| MCASP_PIN_AHCLKX
. P' _( Q7 L8 X! s& `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 |+ r p, O- W) TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * m, ?! v- p* O; o8 e
| MCASP_TX_CLKFAIL
* \% x8 e. G, q9 q( s| MCASP_TX_SYNCERROR
" S& E3 C3 i0 V. `1 k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; f$ b8 G; Z" D" Q5 |: G| MCASP_RX_CLKFAIL
4 R6 x/ v, \7 B/ @ i| MCASP_RX_SYNCERROR # @: W1 @; w+ H$ ^0 q/ s/ w* ?* R
| MCASP_RX_OVERRUN);
. K# n, }1 }6 [ p5 m- N7 o} static void I2SDataTxRxActivate(void)0 D, B5 G) `% L6 ~0 s2 ?
{4 |+ r& ]0 k$ P2 o
/* Start the clocks */
# f5 `/ o. ?6 E& o1 n. ~$ |9 VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) }7 J/ T d" l6 s9 v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% u. B" t; X7 }- p l8 w& Q% X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; `3 n, V4 g" ], C
EDMA3_TRIG_MODE_EVENT);
4 Q- I+ T0 w: l! v/ e( fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( p* v, t0 R4 t/ SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* d- t3 _0 G, j8 U* U8 F& \# n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 b) x3 S+ P' _. r& eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) L+ t1 t/ M. U8 F5 V' owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# ?/ j2 r* n/ m3 y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 n# ~- s7 M3 y5 P+ E K/ LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 X' h" K, k9 z( K* {} $ l" `. r. ?2 }# H5 n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; Y6 X7 M( d2 Q' O5 Z
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