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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 m7 r. s4 B& K( S9 y. ~
input mcasp_ahclkx,. q! p9 s, V7 h& ]
input mcasp_aclkx,
! i( M1 c' n- D8 e+ D/ Dinput axr0,
) d8 Z$ i! g( w# `3 P" @& M* i9 M8 F3 Z8 W
output mcasp_afsr,' ^% v, p5 y# D: I; C5 k
output mcasp_ahclkr,8 [: {3 j6 N' x& n( a7 D z
output mcasp_aclkr,6 f1 @$ O" E3 W9 [9 q6 i
output axr1,
& n4 H1 h7 `) Q" |4 V assign mcasp_afsr = mcasp_afsx;' J) j' ]$ A, |7 ^
assign mcasp_aclkr = mcasp_aclkx;
, ]4 s7 _1 T( q3 m6 G2 W9 v9 Yassign mcasp_ahclkr = mcasp_ahclkx;% S7 q& o1 a- r* x
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . Y2 T2 Z+ A9 B9 W
static void McASPI2SConfigure(void); l8 V; Z; a9 j
{
, Q. l$ z4 G% y0 R/ F- TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 s; G7 H* e' Q& C& A2 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
P( |' n5 P2 B$ N' WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 C& ]/ e4 W8 K/ L6 h( M) wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! L7 q9 Z; S- ~; R! A9 Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! W! u8 W# ~ e1 G
MCASP_RX_MODE_DMA);
! e3 x; ^$ H7 R9 d6 K- vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, }/ i5 p0 }/ Q" q) }9 [9 }# `% U+ nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- C" y) C; V! I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 @. ^' [2 s: K5 W( NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
T! B$ L' a7 }* l0 K3 pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! ]* G# @ n9 n$ W5 M1 C6 w' |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 A+ Q9 W: U7 s; \7 F* u% G8 n* I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! i, g3 D* g- U: [; d6 q0 rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, S: {. t4 q$ W# IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. B7 S* O- u3 A3 h k6 M0x00, 0xFF); /* configure the clock for transmitter */' Q. R, t5 n3 ?) e2 W8 @" N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. z1 C' ?6 O* c7 L! D8 NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' ~+ u, b1 H& ~) d! i8 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* n- E. Y m1 _6 a; }
0x00, 0xFF);% d+ ^ `5 C( t8 Q- t
4 Z3 h- D3 [! g9 {/* Enable synchronization of RX and TX sections */
0 b- c6 o0 L& ?$ P- i6 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 |+ I( q9 d5 B4 T9 {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, M6 T0 E; O6 T o7 o; nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 R; w( W- a) S! c** Set the serializers, Currently only one serializer is set as; X% h; B% N1 t6 k; s$ E \
** transmitter and one serializer as receiver.- |6 q6 O8 X& G! N1 Y
*/
% z- y" m; R) B( CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' T. Z3 K' E) k: JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 `/ }" ]2 s' w' ?( [0 x4 r** Configure the McASP pins 2 E8 w- Q; o8 m. [$ J1 b3 X: w. N
** Input - Frame Sync, Clock and Serializer Rx
, u* d7 S0 m0 T' O+ r8 {** Output - Serializer Tx is connected to the input of the codec " |; M. B1 q: p
*/1 m u3 b! Y; v% n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 W, ~! {2 D6 r @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
A# l9 z2 v5 g+ s, Q2 f4 [; K1 KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# d# y$ E7 Y. X| MCASP_PIN_ACLKX4 P8 l! ^. x/ L& E; M# C
| MCASP_PIN_AHCLKX
8 I* P& N$ i0 N, g. z, b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 W( |/ v8 R0 W, d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) l: c$ s3 P- ?, {& Q
| MCASP_TX_CLKFAIL
0 g, v! v9 W! l0 ^8 F* A( }| MCASP_TX_SYNCERROR( W9 b, E) ?4 \. C0 M+ W- r9 v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- c1 t1 E4 U" ~4 Y7 d| MCASP_RX_CLKFAIL
/ f1 S) }- A7 p' E( `+ a| MCASP_RX_SYNCERROR
( T8 Q# O+ d; s4 P" h$ }| MCASP_RX_OVERRUN);; Z5 f9 q0 y2 ~$ J% [- ~2 i
} static void I2SDataTxRxActivate(void)
; U% p1 X* A# W [8 s" s' X{ o- u& [0 K0 e i2 m" `
/* Start the clocks */
& _9 N( p3 T# e' G5 [9 GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' {5 o) h. T# f- R3 M- _' V) [0 L% DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// Q# N5 a$ a! i* k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% R) _% T# g2 R. ^ \& h
EDMA3_TRIG_MODE_EVENT);& v9 Z" ~) o; x4 v- {$ [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . R% H. D+ V: D4 W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- F( D( ^& N( P2 \+ Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 @6 C$ \* }$ ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! l* G# T4 E# z2 U o& q6 F1 ^7 G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 b7 o* \: e" a5 y9 P+ tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 j. j6 a& k# S# {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 s' x3 P0 S# j/ }1 a9 V' [} 0 C) ~. _; B$ Z" k2 m% R8 n9 z( G. _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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