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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 \7 `9 ], i3 n7 Hinput mcasp_ahclkx,
- D) h; h2 ^6 @% Xinput mcasp_aclkx,/ @$ M/ J& M3 @& [+ Q5 p" f: m
input axr0,3 S( e; Q& k _ L
/ @ d8 j ?; ~# {4 W. J$ Xoutput mcasp_afsr,
) f5 Q e. e' b4 i5 k) z5 loutput mcasp_ahclkr,! ^+ J* Q# i! x Y8 L$ g, j2 A
output mcasp_aclkr,
$ R/ P) Y- S: P7 aoutput axr1,
2 { O; I4 [" X$ W1 X assign mcasp_afsr = mcasp_afsx;" l( q/ O! X4 M
assign mcasp_aclkr = mcasp_aclkx;4 \2 N2 |' V7 A. f& X
assign mcasp_ahclkr = mcasp_ahclkx;
* E2 d5 a. ]6 Y4 Z5 O6 F% s( sassign axr1 = axr0; * s i' U1 G7 g: n4 t% h
% c; d; c, ^1 ], L% r+ g* b7 M; F/ {( A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 P( E6 y. S+ v" @static void McASPI2SConfigure(void)6 L' B0 f: N! t5 M1 a: G8 V. s9 p: P
{2 X/ m) j& U$ Q5 O$ f$ Z* R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' Q' H+ m) F3 g2 y y- TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 C0 Z. n% s6 F$ Y. A( ~$ F( MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 N2 s5 T% i+ q/ _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 s, Z) n' C& l) i* J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ B& {( V$ q: @/ V/ K/ O. Q* mMCASP_RX_MODE_DMA);
1 ]2 n- n2 B8 d+ w( e3 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 G6 U9 b; r7 x- h' Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' L; l |. ~+ k( r8 {9 L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 J9 ~ I9 `4 p2 n4 b- P* hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& l* v! @6 H+ V0 l- A( ~9 TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 v/ E. T+ Y, t# C/ nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- i! ]! ?3 C5 `$ O5 E2 U1 l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 S/ p- @6 y9 a9 T6 e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 r0 K2 m9 r0 k" L8 c9 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% e/ L( F4 O, A. d
0x00, 0xFF); /* configure the clock for transmitter */
1 \6 ? W0 i* P. n. SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 _+ H# p/ `! [3 d2 _4 T) aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % k# v0 P* A5 k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) J6 M0 l: D, h0x00, 0xFF);* t. O9 f* i- Q2 K6 r7 w6 A& c
8 T E# H' n! j: {
/* Enable synchronization of RX and TX sections */ : _0 d2 L/ |+ R$ l2 o# k" ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( o9 Q! t3 j0 V# R' r/ E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 W% f( g4 B; w& B2 l0 v- QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 u: q9 N& C. U- Z** Set the serializers, Currently only one serializer is set as; h# o$ ^2 R+ q# [! a+ h
** transmitter and one serializer as receiver.
2 B- E& {8 N; L5 J. \" c ^*/
# E8 t6 j0 y* u2 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ Q1 g: {& {/ K+ MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* ^) l' H4 r2 x. G9 X6 i** Configure the McASP pins . X5 m1 a+ |% H5 e6 a
** Input - Frame Sync, Clock and Serializer Rx
; _$ r3 H9 p/ p- o U** Output - Serializer Tx is connected to the input of the codec # N# e6 p: H9 I. K$ } }& X, x
*/
* o, \& j% y1 ?+ \% {% Z+ KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ C# N2 t& M5 U6 A, B. V4 t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 m7 x# S" z8 b$ G0 {. g8 x& N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ U4 t U5 {" F
| MCASP_PIN_ACLKX
% b/ O7 W; y7 h" c+ i| MCASP_PIN_AHCLKX
7 j3 h7 c0 T7 M7 d- Z8 ]3 F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; h# U/ }; u8 a# m6 m: a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + d- `2 V5 G: C. c) N1 C
| MCASP_TX_CLKFAIL
4 W! X8 w3 m; S( i! D) D* q| MCASP_TX_SYNCERROR
% l0 G( Y% Q* h& S7 d5 c1 G& x% j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ ^. `9 ~9 W" K' v& O| MCASP_RX_CLKFAIL# M; U* [# ~! A# y- L% S+ i
| MCASP_RX_SYNCERROR
1 V2 o8 S/ d; k1 R5 s9 V| MCASP_RX_OVERRUN);; O1 J F, j/ x" X! S
} static void I2SDataTxRxActivate(void), V @- c- f2 S/ q* R
{ I l, D; h( q4 i
/* Start the clocks */5 j* Y- @; [8 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% t, ~) x7 U9 s5 i+ ~# Z" JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 S$ R& S1 \0 \- ` x Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 i1 l1 w' o! v0 ]" aEDMA3_TRIG_MODE_EVENT);
& s m3 h3 C. O! ~) TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, H J; l0 P$ I4 u( m) G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: R7 x# J6 X9 d3 _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- J2 c5 @" U% t$ m+ i! T$ A6 NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ O1 A+ i, Z3 Z& l0 C1 C Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 ~7 u S# u+ G ~ l- v+ ^! `( m' H( ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. b& z5 ^6 k% A2 L. HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 z: \, P, r% P( u
}
3 l6 @4 N& O8 ~4 j& i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # b0 N* ~, H7 [4 V* e( y
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