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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- Y9 v) z8 Z: o) @" A
input mcasp_ahclkx,
7 }) P5 e) ^) g% H1 U' S# H. [) Tinput mcasp_aclkx,
( f8 V# D- n6 W& R8 X8 ainput axr0,4 k" x+ K* }8 C' M- M8 [% e# \
6 L& d7 Q) ]: l) p/ O: [. q3 p- D
output mcasp_afsr,- C7 @- a! ]; w/ A& z. f7 X4 |
output mcasp_ahclkr,7 J3 |* ?9 g1 {
output mcasp_aclkr,9 k/ c- T( Z1 ~: F+ n
output axr1,
\3 ]) D1 N) U8 k8 x/ g, ~ assign mcasp_afsr = mcasp_afsx;0 u7 }, c$ z) w$ z7 _4 c
assign mcasp_aclkr = mcasp_aclkx;7 L! s5 F7 K! r! L* i N$ U
assign mcasp_ahclkr = mcasp_ahclkx;' U; r; x( D2 z V+ @: a+ B! G
assign axr1 = axr0; $ h$ p# D7 ?: F. [3 J
5 a7 t$ N0 }5 {* G& T: C9 D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 s" _% Q9 q3 M* o3 n4 m
static void McASPI2SConfigure(void)' z6 b' M$ X! w% t( w. K
{! `: k. x& Y, _( N& U$ Y- A" I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' V" p. I4 m1 V. {/ }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) T1 i T8 Y. d& i, B" {, o7 a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ j6 X+ `4 n% B, J, h3 IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( u4 Q+ |+ ]3 o0 O) p$ ^1 RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. R; U- W& z" d" Q! u: `* nMCASP_RX_MODE_DMA);
4 }9 \6 O- S# [2 W+ NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! V4 I' m9 y4 o* O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% T2 @* k! @# ^8 g7 k7 D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, L- R3 O: Q" X9 Y0 _7 [ Z( GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) w e: `- I; ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, A6 c! ]8 T& Z( c; E( wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 A* [1 R. }; u2 ~1 D6 u- `: AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 Q* Y0 A5 `3 H, G; Q9 b! [2 @5 L8 V. S+ lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- X4 x1 B3 B3 [# AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' b+ a+ w! k. Q& j
0x00, 0xFF); /* configure the clock for transmitter */0 m2 k/ f5 Z* f' ~ f* _. t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ h+ c5 B8 T, }7 S4 m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. _# b% l+ O3 t5 P( T; w' [# IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: v0 }" z. t/ O' ~ i! N" R6 l0x00, 0xFF);6 a0 _9 W* b; m- Q. g5 J" W x
4 F0 P! `4 n0 N5 h8 y }/ L J0 R6 ?/* Enable synchronization of RX and TX sections */
, r m2 w5 A2 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) N! {6 r( { N- u& j: j, L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 T5 L! \8 g% \/ r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ H0 }7 i! d7 B/ D; j* h
** Set the serializers, Currently only one serializer is set as1 e6 U+ ]% R$ J' L1 |8 W' ~: k$ K4 y
** transmitter and one serializer as receiver.
6 E$ g! ?1 A8 m. Q2 m1 a0 {*/
2 a! j* h2 }( v4 rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* Z# f9 [; E( WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ M O0 v( ~4 L9 m0 d7 [: B3 F
** Configure the McASP pins $ h9 w% ~* x. R6 h
** Input - Frame Sync, Clock and Serializer Rx
- s( `$ \* @# M$ w7 f** Output - Serializer Tx is connected to the input of the codec
& q* `- l4 q0 O) K( J*/
- t) j7 | Z: ?5 YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 x @) g5 X6 r( }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ t3 ]1 J; y2 D% W: j1 q( Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" \% d; g& Y( {; B j
| MCASP_PIN_ACLKX. E; ]0 A: E/ N" K# g
| MCASP_PIN_AHCLKX
$ o _8 [' M/ m4 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 y8 }4 V, t9 P" I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" |! P- B6 k5 \: m6 M| MCASP_TX_CLKFAIL # Z V0 n" {9 K9 g" F0 H
| MCASP_TX_SYNCERROR
7 f9 q* Z, D* u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ s: f/ E8 ~: E7 O3 ]4 o/ I: r2 n7 `| MCASP_RX_CLKFAIL2 l3 c& z9 z/ g0 O8 d7 J* ?
| MCASP_RX_SYNCERROR
# a# x9 [( N9 ]6 ]* n| MCASP_RX_OVERRUN);
1 V+ b4 p1 J, V! Y} static void I2SDataTxRxActivate(void): n8 }- s8 D$ n' W
{3 D1 I; m! K! Y, M
/* Start the clocks */# ?- t" f0 W( F/ n0 d6 w9 s7 E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' n# s) t; F7 M1 D) O! vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 d2 G2 S$ I# |# @2 m3 B0 }7 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: _' Z9 L" Q2 M+ eEDMA3_TRIG_MODE_EVENT);9 X% [: ]* n& V0 [; A7 r& O0 a8 t% a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 {3 w$ k1 u: S! u/ D2 x3 I! Y& K# K1 f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ n! Z c5 j& n5 Z; M% e; D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) G0 q. {2 T$ h v9 C2 {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 h' ]0 n& p, d" A) u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' k6 F4 E( N- L' ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 Y0 A8 V; M! M* o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- c! V# j* d6 |6 Y- z% _} + F3 f0 E C+ \- t. q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 g2 r0 }3 t0 v) `- g0 W5 x8 @
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