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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," i: q8 Z* D1 n/ R# b/ d- ~' e$ h
input mcasp_ahclkx,2 i; \! a0 z, S- Y3 ^1 A/ Y' F `; ?
input mcasp_aclkx,6 n( M( {9 Y" c$ B T
input axr0,4 `9 R- b' q5 y1 G# R) y
2 e# H+ x2 r/ o3 `; n* T
output mcasp_afsr,- b3 s p# l. \6 U0 o% [
output mcasp_ahclkr,
& a) t5 Q/ Z1 q9 |( Y3 Goutput mcasp_aclkr,
' y' o/ @0 |4 h' W+ w! @& W- f8 Ioutput axr1,! I" w( z! `& `' Y5 U6 X* S
assign mcasp_afsr = mcasp_afsx;# l6 i z% g3 n/ h+ P* H W9 D
assign mcasp_aclkr = mcasp_aclkx;! w0 o# P( U. u0 L
assign mcasp_ahclkr = mcasp_ahclkx;
; W2 M6 p1 D( C. c; {assign axr1 = axr0; - a, ^" {% w" @, D: e& q
& m& D, r F! ~, C8 ^* V, s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " m% F5 v: f& V4 X
static void McASPI2SConfigure(void)9 }- z! {: [/ |/ s8 x5 ~: `) }& K
{
2 v! I! m! I8 C, g( W' IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. m; C; p" V7 N0 _7 u. |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 @7 d) k! L2 Z0 F& wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 }, D( _. l" Z0 [) T( y4 H$ vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 o( |+ N) i' s; QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ v) M& r1 n3 d' G3 g* l6 G
MCASP_RX_MODE_DMA);3 ?& v% n# s9 q7 s; T4 ~& P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 h) U3 }( P* F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( ~' }3 _2 h" P/ }5 H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: Y8 M( R) E2 T1 KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 {- I9 {% `! p3 I/ `* w& cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 C$ k% j* a8 q# d% g) Q0 vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 q) W: O# L% @9 b: LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: b7 A5 V+ z, }: ~, S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% d, K3 @) H6 O; IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, l) L: e* H0 X3 W# P0x00, 0xFF); /* configure the clock for transmitter */
3 w) f! s9 s+ W F3 X( DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); z' m# ~) P- d' C! n. y2 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 Q( q/ `. l8 M& X8 k, ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% _; V+ q9 ~# M; f# U% T3 z: T8 X0x00, 0xFF);- r" G6 m0 q9 o) u' `
- H1 B, g l' @: Z; W" M, l- c& k8 l
/* Enable synchronization of RX and TX sections */ + T. i3 n# D$ |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 A/ ?- T9 C* q+ H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 J* a$ E# z% b9 J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( C$ j# p2 ^- ^& N6 O! ~8 p
** Set the serializers, Currently only one serializer is set as0 l! C! }/ L* w$ O7 M
** transmitter and one serializer as receiver.
/ F. m9 Y. T9 {! ^8 `*/6 p2 o9 r. [* J+ D* R* j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 |1 C' Q/ ~: b+ @" h! o' a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# S# O+ `' `2 ]! b- I! G( r( h: c5 u** Configure the McASP pins
. {5 |0 q; k: `5 r9 g+ ]' E** Input - Frame Sync, Clock and Serializer Rx' ], g8 s8 o$ I3 m; K% z7 R/ A
** Output - Serializer Tx is connected to the input of the codec $ u6 P4 l2 O6 {$ b: b* F, n; m
*/! K6 n, I9 V, c( z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); h* {& k9 H- F0 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 e5 g* C$ r. S! G- v J4 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% u5 ^6 D2 l2 M N# ^
| MCASP_PIN_ACLKX
3 l+ F1 J8 o" n( h7 g| MCASP_PIN_AHCLKX" d' u9 U" I: e2 T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# j+ E( ^% B" t: YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 h' E' x2 a5 X% a| MCASP_TX_CLKFAIL
6 E+ ~6 v: B( n% E# ~ R8 a3 R# a* C; u| MCASP_TX_SYNCERROR4 `, ^$ h/ ^$ j: ~2 U; i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' ]) o3 j. Q5 A- _| MCASP_RX_CLKFAIL
3 P! N8 F& I0 j% L| MCASP_RX_SYNCERROR : p! O$ O0 z: c1 g X; t' I
| MCASP_RX_OVERRUN);
% D4 Q! P" @, o, X b} static void I2SDataTxRxActivate(void)- {9 V4 Y1 z+ |& w
{" G, A- v' |- q& _5 M& {
/* Start the clocks */3 `) C* s3 G/ r3 K8 y' t |9 p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 h5 b' ]# |- V0 N2 i4 d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 J5 n9 J# o$ yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 ?$ P) r$ b1 V6 k* ?
EDMA3_TRIG_MODE_EVENT);
8 I. R) l- U" x; Z$ dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 K1 K |8 J4 C5 K2 N% d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 [2 n6 F! H @2 g1 _0 A9 Q* [" u, @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 N! }7 r/ `4 e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 P% K3 q9 _% t! s$ U% t& A! Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% d( u" f& E3 O1 Y8 `4 FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 c% l; g6 a I- P c; m: D* @ \1 yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: a+ W9 A. p" A9 E+ J6 A) F
} ! a; ?0 N. \; O& @: z" R( ~3 ^8 d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / [% h; U% E* j
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