|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 p8 |0 m" a! {1 x+ minput mcasp_ahclkx, @. X: N" q3 \( r# P$ S
input mcasp_aclkx,
8 g% y9 b# D7 }# \ kinput axr0,. D3 l& X$ q! B& O6 A
( ?% b+ } K' w- V
output mcasp_afsr,
' b9 l s$ f. \9 f) ]output mcasp_ahclkr,+ [; f. n9 L5 e7 O/ z
output mcasp_aclkr,
# s) E9 z) [8 D& W/ m' K7 k* q7 Joutput axr1,! R9 z1 w4 A' r, a* L
assign mcasp_afsr = mcasp_afsx;" x: {6 P% C6 T; l6 b1 t
assign mcasp_aclkr = mcasp_aclkx;
$ K* ]' M* W# S& Z# eassign mcasp_ahclkr = mcasp_ahclkx;9 w8 s/ |1 L0 z# A& D7 q$ F
assign axr1 = axr0;
: A) n% d2 J! K1 Q& X; c' ~; P6 z9 i
2 }5 b- w9 P' U! ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 B! W0 h J; ^5 G* S u! w: R+ ~. ?static void McASPI2SConfigure(void)
! F3 e8 L9 B5 `% v( @{
% Z7 p, H% N9 \' |McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! z( `5 K& B0 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* p4 j1 g2 K( K3 IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
t ]# G1 N4 g$ o- I, m8 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% y9 R! g. q+ l5 h+ l* w: V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
`# z' C) j8 _, U! VMCASP_RX_MODE_DMA);! I* \$ E& n/ }8 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 a- ~3 r H% F5 D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) [8 y. d7 ^& T; K+ G2 }8 O2 p3 Y* T( EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : i4 U) B8 v& Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; C* z i( B1 z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, A) b! E* W: m: K+ L* F' ?; e* q9 QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 t p- }) f) o6 K$ ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 w. V; {1 `2 P0 x+ l+ xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( M; q5 S/ @0 E0 B9 k% l: _( |- E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ F ?8 z) k. J6 _$ S
0x00, 0xFF); /* configure the clock for transmitter */
9 |" x7 o# r* V/ J. `! u/ yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" B$ g; _1 Q+ p# y$ n1 ]& U/ t: F" ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; j C! N& J: L# w5 ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 d1 z' W& o& S1 h
0x00, 0xFF);
. \7 N J3 o& b. S8 l, ^, p2 p O* O& l8 C3 u8 H: N$ t% w9 Z3 j
/* Enable synchronization of RX and TX sections */
0 {- L: v8 b. J2 M" j7 z2 `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: W, s; S* _2 s' C0 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# Z# r& m/ `6 x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 g8 Z) E0 y- P, O6 {% n
** Set the serializers, Currently only one serializer is set as
7 g/ m1 X7 e! }" k) u** transmitter and one serializer as receiver.1 K l* V& F3 v) ]9 l. Q. n
*/
x7 ]. r! y( f+ x1 B6 h rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 G, z# m0 |& {3 B# g2 a) u. NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 o3 B6 ~3 H2 f) X! }/ z** Configure the McASP pins
; r' k X. W/ ~# r5 n5 q1 h* v** Input - Frame Sync, Clock and Serializer Rx
2 e8 @8 K% ^! u) F** Output - Serializer Tx is connected to the input of the codec
" x. C" w) t. Z& ]*/
) S6 K$ S0 p3 L9 q* c1 \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 B# j7 |5 S" G1 ?" N0 R, t# _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ \' Y* E5 A8 t* `3 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 t; f$ ~! M2 q a( _# T! r| MCASP_PIN_ACLKX5 r3 ]" S" \/ c( k
| MCASP_PIN_AHCLKX9 ]/ D- r, _3 U" C- U$ i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ u& y+ d* G/ G) R/ t1 \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , p) [# |( u" V% q: ~$ Q
| MCASP_TX_CLKFAIL
0 j6 `. z7 V1 ?- ?. p% @| MCASP_TX_SYNCERROR
0 g/ B5 o9 i0 S. y, J' c$ A& k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / J5 S* `( H" [
| MCASP_RX_CLKFAIL
+ c0 {+ p9 w! G$ W| MCASP_RX_SYNCERROR ! I2 f7 I, i! I, E5 a6 w: ^$ t
| MCASP_RX_OVERRUN);/ q; S- @7 M+ @" Z" C
} static void I2SDataTxRxActivate(void)' {" b+ y4 q) h9 s& K& _& T
{9 P8 e! T- `; B
/* Start the clocks */3 T: x. V9 [: h) c0 [* N' |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' n4 c2 y( S. W2 K5 l& f7 ^; ^2 \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, u M [0 Z) q0 @$ _; _& A+ BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- L4 Q3 |* m& i
EDMA3_TRIG_MODE_EVENT);
! Y6 F1 s' y }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 n- m' h# }2 f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% e8 w- i0 d& r2 q9 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ u* h' S# l: U% t7 }. k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ k" [5 y. p) J6 |0 Q# j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ r. C4 D8 n$ l5 P' y! @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 K* f$ P! N4 M( {: [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ v; b& d9 g. T$ E}
& y) ?+ k B Y/ ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- v- l7 A( K' r' d, W |