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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 K6 F1 ~6 @) k. r; y
input mcasp_ahclkx,
0 Q' N8 W0 d0 F/ `; h A1 m) einput mcasp_aclkx,. n8 C B( t: I, M" V8 \
input axr0,5 u7 V0 Z/ _- o( g, s2 E
# z- m5 Q6 V- h5 E
output mcasp_afsr,& c& A/ U1 d+ B' L& Z% T
output mcasp_ahclkr,
% t$ P# [ v1 A; Q8 _ Soutput mcasp_aclkr,
8 V# @+ {9 G2 ]8 j4 g0 \& V& H4 ^output axr1,# N9 `. d' p2 R6 h
assign mcasp_afsr = mcasp_afsx;
* j' d2 v" s) v$ D) Wassign mcasp_aclkr = mcasp_aclkx; }) l; b# G0 d8 ~- ]4 E* F
assign mcasp_ahclkr = mcasp_ahclkx;' F, f* z2 ?' D1 C' |/ B: t
assign axr1 = axr0;
) h8 M) K/ B. d) V% |* @
' {) j0 }* M" K8 s4 U, ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & X' c$ J y4 P* m
static void McASPI2SConfigure(void)" s9 g; Y* b* P# m
{' G a4 y2 I T4 N# \! H6 O3 A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% S0 {% [! @! k# r5 xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 H- V- ^) f+ E7 J! |3 p/ g5 D4 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 K) q* d% n6 j% ~3 O6 L( tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 ^$ @ P8 {- k, ^& O9 d" Y) ?* k# i7 BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, }" N- ~6 F! t# K$ R6 ]
MCASP_RX_MODE_DMA);5 z0 m5 d6 s! W9 J2 V6 s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ {; n h0 I* {% R7 C; j* D# @6 y& YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; [+ K$ q I7 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 G. B( n% r+ w% W6 j( z0 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 m1 q9 M+ A. L, y) M- C) G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; A F- I$ H2 D8 Y- j, o3 m5 H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% k, b$ w7 y- M# b) S* |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ d6 K9 M% q3 P! z% ]+ aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : e% C" v; t% [2 [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: a. @. o1 \: U8 h+ M$ P0x00, 0xFF); /* configure the clock for transmitter */
" X& B3 ^, R! dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, ?$ y1 d+ H: ]6 ?! ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 h4 e: ~* E1 b: J$ K$ |( t7 v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 U: L [6 _9 g+ V) J* l* T0x00, 0xFF);
) s5 O# g' Y, N3 W; q) ]2 C) Q' U% a- A7 @" R# r6 h
/* Enable synchronization of RX and TX sections */
9 N0 P/ x" J( h% kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' W3 y2 s5 S5 z% r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- [0 D( d6 c# _/ O& h9 ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 C1 X: G+ F, S** Set the serializers, Currently only one serializer is set as2 P/ k6 L! F5 a9 ?2 g& r
** transmitter and one serializer as receiver.
2 X8 Q8 M, t3 u7 ]! M" t; V# K*/- `# L# p' C3 l! u" T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" Z0 A) y) s/ J6 R# j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 D0 V+ y- G7 r/ G: n2 P** Configure the McASP pins
* N( }- x) b" j- r( u9 \** Input - Frame Sync, Clock and Serializer Rx
1 d9 ~5 P! K* u( U8 \** Output - Serializer Tx is connected to the input of the codec , y/ i4 [8 M, q" z
*/( W8 p$ x/ O3 [' G r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% g' m$ k- T) \% f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" z6 p9 E3 V) {" x7 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% p1 \+ T7 c9 c) _; ~9 z' R( q| MCASP_PIN_ACLKX5 X+ Y L2 Y2 \& y: ^$ Q
| MCASP_PIN_AHCLKX
+ q' V* @9 E6 R! ?1 V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) g0 H+ T4 ]8 l9 M8 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* R( U1 C. Y8 B| MCASP_TX_CLKFAIL % a. b$ L1 t. u! B. [+ Q: H
| MCASP_TX_SYNCERROR# J# H! b) e, G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 t* h; f. l4 u2 |- D! z. f3 r| MCASP_RX_CLKFAIL
6 U0 f5 d5 O/ c# u" r) U| MCASP_RX_SYNCERROR 9 Z4 c* D% C/ c2 C7 I+ X2 N
| MCASP_RX_OVERRUN);
. b% R* R1 X7 I& [; o} static void I2SDataTxRxActivate(void)2 ]- n- s. F4 b; @8 ]- Y! |3 C7 M n* C
{/ G8 N9 e; ^* L, j
/* Start the clocks */
; |, C6 [ P3 E' T/ IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' J% U4 M7 w3 p u# _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 _; l# ^; v% oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 N. a( B6 |+ J- ?EDMA3_TRIG_MODE_EVENT);
8 [6 A% A6 g' H. B" W8 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 e- ^3 |$ u3 Q' V- A" R8 d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 g) l: ?. J. a6 {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 D0 I2 n$ U5 s# X' _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ ^9 h: N3 M; k9 J/ D# Z2 Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 _( ?. w4 f7 s/ ` i' f1 K4 R: tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 N3 T# X- s& ^( W, s/ G% GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 v# N$ B# C, a( C& J. P; C" @}
t K7 S; }6 i1 v; G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 ^0 P V( U9 [3 A/ Q
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