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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 F( p( U! l7 @/ t/ W
input mcasp_ahclkx,
) R9 Y2 b' l0 B# M% W& qinput mcasp_aclkx,
1 v7 G. Q1 K: H9 ninput axr0,5 ~4 V! V$ s, [+ V7 S7 [9 D. W
; b' y9 [8 p0 h3 {output mcasp_afsr,
0 k" b! _+ e. n- J8 E6 voutput mcasp_ahclkr,
4 t; B$ D1 C/ m, q+ Y* youtput mcasp_aclkr,4 k2 Q: O1 l5 z4 M
output axr1,
1 r, g9 K0 M( D$ }3 ^ assign mcasp_afsr = mcasp_afsx;" G \' K2 D+ L0 A4 e6 J# J
assign mcasp_aclkr = mcasp_aclkx;
2 n9 j1 S$ Z: y9 h& ?8 wassign mcasp_ahclkr = mcasp_ahclkx;
- B O) _! i$ ~assign axr1 = axr0; 2 S' R U4 |) F: |+ j% B
$ l0 G$ o, L' ~- ~1 }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 D' J0 h/ v* w8 t8 [9 Gstatic void McASPI2SConfigure(void)
8 x, l4 M: P7 [9 C6 m/ V5 A! Y{
1 t; G: L7 z: @# D+ b qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 [8 v' B5 u6 X8 @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, R( A3 M2 @) F9 R9 P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* t2 K+ z- p) a4 ?2 W. l, Q9 w% q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* z5 f/ ~5 I4 a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 c& H( e( W9 f) ]6 d) J
MCASP_RX_MODE_DMA);3 Q9 X5 k0 m) Q+ K! o* u( Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 P% f$ o$ g* B0 L. `" S* E! ^5 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ W: M& a" x9 H3 }+ s7 K5 t0 r$ [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 _# k$ {" ]# `- H$ N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 k" k y L1 k$ D, K6 |9 I; @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 f* ^7 Q, r3 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; N3 d3 C4 k: s. c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ P1 ]4 d6 m2 IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : ]8 o6 g0 H! r6 o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* Y0 x: |2 t9 G* q9 p q2 c) W1 E* o0x00, 0xFF); /* configure the clock for transmitter */1 t: |$ n4 e- L3 \2 O$ n: ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 i9 E, v+ a9 |- i: N- K0 N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% K2 J; G8 x5 z& k" RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, {9 S C& D8 m6 I
0x00, 0xFF);1 b' o" ]7 B" l2 ^: r3 z3 v) s
+ x7 J2 E, `/ [* ?
/* Enable synchronization of RX and TX sections */
7 L! j W6 F: E nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ F$ I8 P) n9 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" g0 z$ V! z1 j8 `1 K- U. F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" D6 j4 ~8 @5 F R1 Z
** Set the serializers, Currently only one serializer is set as
7 |. G6 R% B1 Q5 L9 D8 I** transmitter and one serializer as receiver.
% m% D& b6 c, L*/; g- O; e F: \6 @- x6 I; K" z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 D) |( |& S! U3 o. R( \) S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ k8 d5 L) Z* A' e$ A
** Configure the McASP pins / a, e) w$ v8 S4 W) f! N# n3 R
** Input - Frame Sync, Clock and Serializer Rx
9 h4 d: `" J# T8 a! a** Output - Serializer Tx is connected to the input of the codec " G, e, X }* W
*/
5 N! X6 F6 U( Q% f/ cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- [! R$ _3 Z/ g, I) C b. Q2 @% d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& d# k1 y; v! a0 l$ xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 l. \' c/ C! c$ L* l& V
| MCASP_PIN_ACLKX
4 X9 G, u7 \- E$ i9 N f; }( K| MCASP_PIN_AHCLKX
& o" ^2 V( @' j+ e6 V9 z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ A9 b# A6 k5 w {' [$ o; t* T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 f: P( k! k0 v& l1 y3 M0 {8 |" f| MCASP_TX_CLKFAIL 7 p3 l1 l8 ^3 Y! m' } c: f
| MCASP_TX_SYNCERROR k" I& Y4 g2 `, P* y0 m+ l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # \9 o) P. U% p q* e0 r' l
| MCASP_RX_CLKFAIL4 v0 L7 b8 Y2 F" f8 J% i
| MCASP_RX_SYNCERROR
. l/ m. q: f/ p! d% A# {& e| MCASP_RX_OVERRUN);
( h; F7 I: n7 I9 t9 W" m} static void I2SDataTxRxActivate(void)
. a) z( w% G+ E. }1 o{& y# x1 L# Y) O
/* Start the clocks */
' {3 u( w W" j/ r# x+ J2 dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 E7 Q& }& Z: ~7 u7 v- o, V6 ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 _) H2 I5 G$ y( aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& e& V7 J) a$ g+ @( p! D
EDMA3_TRIG_MODE_EVENT);
3 W' l8 m3 _* N% i( W8 f5 ~5 |. M% LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " r7 h$ j; a( f, L' @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& [) i) K( z6 _) c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* u' A8 b5 ^( K& x7 `( c0 {9 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 M. e4 }% e7 a% v: N) N. [8 f/ vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% I. U N, |1 I# C( g+ ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" Q, P0 W$ k- B$ F! YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ H& ]+ t' t( v* W( O
} # }5 Z6 G/ U# Z, X2 b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
3 ~0 y) Q! y1 p5 X! [- u6 p& G |