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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ ]5 h# C% P; Q: a' E" Sinput mcasp_ahclkx,
2 w& T" s" _' i* `4 K9 Iinput mcasp_aclkx,
# ^" a9 n) T) Z/ A1 Sinput axr0, V: r4 A6 t0 R3 z# S
/ U( G! s1 O3 m3 w7 c
output mcasp_afsr,
& \, r& i, T2 j' boutput mcasp_ahclkr,, b; h1 C% I/ D& X
output mcasp_aclkr,6 k$ A7 V: A+ c" _1 H6 p. M. _/ \
output axr1,% A) p, U; ]+ q9 ~! @
assign mcasp_afsr = mcasp_afsx;1 t8 O1 T" j2 _
assign mcasp_aclkr = mcasp_aclkx;
- H& P% Y- H9 L* m- N( Eassign mcasp_ahclkr = mcasp_ahclkx;) c7 z! D# ~/ y( x& \# H
assign axr1 = axr0; 5 n; L0 ~. k" H6 ]5 @
/ l% r A; b7 ^, R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % X# A1 H) F6 o
static void McASPI2SConfigure(void)
. Z) z- _9 M& {& q{
* N3 y: E8 s# D4 Q3 \& KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 {) n3 E7 L# s; a8 m* S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' I# [2 ~/ H& {2 M! w. LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ Q" d1 z- I/ |/ @0 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: |0 l0 J9 h" g3 o$ H$ }$ `' w0 ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 G% C+ Q# k9 g( ~- y9 U0 e
MCASP_RX_MODE_DMA);8 x9 \, p8 E) R9 P- j8 O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ o4 p* F2 V# d, u8 |# d3 C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) d% F0 Z/ v% f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 z3 p8 n' _6 D% y" SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 z0 o* ?* M i$ j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 R$ u7 _: Q1 W9 @/ K8 ]% r3 I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 e* x( e/ O9 q% C$ t5 K: k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) ?% \+ O- p* L! |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; r# y( A3 B" O0 \$ ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' H# l3 `% h" l. T+ M+ T0 R0x00, 0xFF); /* configure the clock for transmitter */* s5 F8 F G# h5 i# W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) `% t- @) V' w4 C* U) x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 I7 \% }% a& R; E+ B/ Y3 ?0 E4 e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. h6 u) j5 w( d6 `; W0x00, 0xFF);8 Y" ?) I6 G. j# f
& z% l; {7 M% l
/* Enable synchronization of RX and TX sections */
7 E# h- @- T7 }1 L. @7 z6 RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. V+ Y1 m4 _( h( Y+ L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' ^8 ?% u& A+ x! U3 S% f5 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ U5 e1 z- I( ~2 z2 L
** Set the serializers, Currently only one serializer is set as+ z/ X' D" I+ @0 K; p
** transmitter and one serializer as receiver.
# v, v. Y0 w' Q8 {: L*/
9 K: b% M$ u. E& D! @( sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 |) i+ {4 m* U, v2 [; O+ e' a NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# L+ Y+ P% R4 N** Configure the McASP pins . {5 @: D) F; I# [1 }4 c6 ?
** Input - Frame Sync, Clock and Serializer Rx
1 Z0 Z8 ^; H% T** Output - Serializer Tx is connected to the input of the codec
) N+ E$ x, @$ {! k+ H# H$ _*/
2 k. Z$ H* M, [) m& ~! _( H0 TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" n- X+ j8 u! f9 u3 lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" y1 v$ c) f H5 ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ T! \& m/ [8 h# X4 k/ |4 W| MCASP_PIN_ACLKX" {1 I" T* [0 U2 h$ q
| MCASP_PIN_AHCLKX
+ {; s( h9 I$ |2 u+ H0 p1 U* `5 V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; I$ }- U- _4 a4 O1 T$ a F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 n- Y& C$ P0 y. i! z| MCASP_TX_CLKFAIL ! q% N' f) b! f1 P- r7 m
| MCASP_TX_SYNCERROR6 a4 A* }& K' l. M1 f8 g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ t6 P9 n7 p5 u3 |6 u6 k% ]| MCASP_RX_CLKFAIL3 x2 o: U& W/ \: y4 C7 Z# I
| MCASP_RX_SYNCERROR * j1 K; u0 x! [
| MCASP_RX_OVERRUN);- |' `6 e% z2 r1 k) _: Z
} static void I2SDataTxRxActivate(void)( X1 f' f' Y2 R* @2 ~- l! Y
{
# Q$ C1 K& r2 [6 `) t/* Start the clocks *// ^" z3 {) e& W& C5 N6 @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); e: g: T3 n# d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! L! R% u. J! w# z+ x9 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# v# G9 q+ }1 {/ ~. U5 h( D) ^EDMA3_TRIG_MODE_EVENT);
; x2 f" j1 H) }, ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 ~6 k& ? T! U: p! L; I. GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! h4 s& {8 Q3 C: k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! [6 v9 T/ `/ J r3 [ JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 @) H" Z. e M: m9 r* P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% ~# a- G; S2 nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& W/ Y$ Y9 p) n: E' SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* R" ^. x$ q0 ^# n, \! {# D}
, ~% S+ E+ Q* [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - A7 S8 t8 B. l4 R
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