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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 ~) D0 m9 h: @0 Minput mcasp_ahclkx,3 Y7 M6 z8 }1 K3 ^
input mcasp_aclkx,
8 {- p$ X9 c) i% @input axr0,
) V! ]" N6 X8 v s) B: k3 s: V% T+ s Z' E" j6 u; ~7 v
output mcasp_afsr,
8 S+ F3 t9 }& L2 ?& moutput mcasp_ahclkr,: N! T" Q7 U y
output mcasp_aclkr,: c5 H; i! v; e5 W# w- n
output axr1,# M6 v* _8 `. B0 H& {
assign mcasp_afsr = mcasp_afsx;" ]; D. u4 W6 J( b1 y
assign mcasp_aclkr = mcasp_aclkx;
3 C3 u8 M/ s6 H% Wassign mcasp_ahclkr = mcasp_ahclkx;1 I- y. x6 ~6 I5 y
assign axr1 = axr0;
, B8 u( k" R$ U c( m9 t+ W1 `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( ]4 A$ s7 ~- {' W
static void McASPI2SConfigure(void)8 `+ F4 p1 L, {8 w% U* b" p
{( A* V$ i& y7 Q; x( v2 I; V& [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; K0 M) P/ V% I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* K! j/ X& ?- B6 f V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- n7 l! k: Q$ w* U) ~4 \" a) x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; I" n$ t9 X/ U& s YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) Y2 L- e* v( n5 tMCASP_RX_MODE_DMA);
3 Z1 I0 L$ P4 @5 @. T. x g' TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# W$ w4 O% b1 S$ |8 GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 E2 c. F3 ]/ V3 L$ r% hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 Y8 L7 K" A) d- }1 [' @7 i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 Q3 r* @, `! f b% [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ U1 z! G1 h6 `3 m% ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 Y5 H( n" B- H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 }) O" t" j$ D$ |& O) k3 EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # O4 [7 f- N6 I7 P: q4 Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 m; D) j. O7 p6 K2 v! t8 n0x00, 0xFF); /* configure the clock for transmitter */
! p8 N: j& U9 D/ C) b. w1 ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 A/ d. b2 Y4 ?, b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - c0 G3 p! |, E5 V5 f! J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 j9 G7 A- D( Y- b! J5 i$ s, Q
0x00, 0xFF);
1 E. B9 ^; t0 y& `7 v' t5 @3 ]3 [: Z' y0 J0 ^$ d2 T" v$ D0 h( V
/* Enable synchronization of RX and TX sections */ 0 v6 H& b1 r3 J" R- Q1 m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 k5 w3 \) W8 W G. _8 S3 U) \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 Z4 @) _% _/ L' D$ x+ w1 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& e1 s, Y6 J L" P* \
** Set the serializers, Currently only one serializer is set as
9 k7 r, K9 N: s** transmitter and one serializer as receiver.
" z$ z2 c' V; I8 ^* L*/( b+ h f/ c" N0 F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* f- g; q: v) L; A7 \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% ~4 G* V1 r/ e# l8 I( U. h, h$ S** Configure the McASP pins
( T7 i' {' g6 g4 J" q** Input - Frame Sync, Clock and Serializer Rx9 V, D! ^& F+ s0 Z! W& u6 ^
** Output - Serializer Tx is connected to the input of the codec " C! ~3 k, e; r" F
*/
: {1 m% }9 T/ B, h* Q6 @; D! KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 C& V2 U" N. A, [5 b3 d+ rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( p% x9 z' ^7 z9 k7 R3 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 w9 y3 d! t, W* m6 ^- X" u4 h| MCASP_PIN_ACLKX. n$ `- t( n2 \: Z- t
| MCASP_PIN_AHCLKX, Y' Z- W9 F2 K2 T9 g! u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 \: j! z, i+ o' ^, O% @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
D& W9 L6 S& V| MCASP_TX_CLKFAIL
# }5 ^9 F: O J4 k| MCASP_TX_SYNCERROR
( E; V3 @+ [) z7 X9 k% h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; [) V/ s. O6 T( m: N| MCASP_RX_CLKFAIL
9 e0 T3 \3 d: e' M, h1 ^; e| MCASP_RX_SYNCERROR
. \, m9 ]) g T7 _| MCASP_RX_OVERRUN);& C+ E/ b. `0 r: r& J/ F
} static void I2SDataTxRxActivate(void)( ^5 ^' ?( v& K7 P
{. L) m% I: C* Y
/* Start the clocks */
/ C" Q6 p2 A8 M bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, S$ ?& g* `: P9 U, W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) p1 h/ S3 K- ?4 F- v7 C& @+ o" Y1 ]" \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 [3 [: _0 R g( } Z- h
EDMA3_TRIG_MODE_EVENT);
, p& c1 J, V7 u* fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ i7 J( V9 U) oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' Z& H8 A- [+ q1 R& x( F6 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* J- x2 _5 E- t5 H( x4 ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 O6 G) V' ~+ W4 ^* C1 Z I hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; `( n `! j$ y- lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 Q2 [( k( P5 I0 U# L( L- XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( A% A: W! q5 |) F$ K3 j
} 2 W( C* A, _4 P2 [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! W9 `( r3 l7 G7 g6 l
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