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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; ~2 ~; t6 K4 b7 X2 z; h7 s
input mcasp_ahclkx,6 M: W& X. ~7 c
input mcasp_aclkx,! }' e( ?& K, k* T' n$ N
input axr0,
: K6 e/ u8 N: T1 w' j, \
- O+ @! R8 U. p# k+ w* F6 T2 E8 ^output mcasp_afsr,
- x+ a9 i: c/ n1 }0 W7 |8 moutput mcasp_ahclkr,
1 S6 [5 p1 ~' v: E( j, }! poutput mcasp_aclkr,
7 B, r- m8 P$ l$ g$ I/ coutput axr1,2 J- y6 E% w) R. i. ~, Y" E0 F
assign mcasp_afsr = mcasp_afsx;
. L& ^* B) ~0 l% {assign mcasp_aclkr = mcasp_aclkx;& @7 }) F* z9 X! d9 S [; h5 I
assign mcasp_ahclkr = mcasp_ahclkx;) F2 |& U# @- I" j$ `9 @
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 l- L4 `1 I9 q2 M3 E
static void McASPI2SConfigure(void)5 \' }5 t5 L# L- F5 ^
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 B/ T, D6 M8 fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" S& b& V& a) ~3 f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! L. n8 x5 j1 _8 k+ {0 R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" o0 m0 E' n# @. C( i4 G" x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 O! ^: [) J; V. nMCASP_RX_MODE_DMA);
* u) F& j+ `3 i1 P2 N9 t: F# qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ I! f4 {. M8 x5 f: `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 a, `4 P1 F B" WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + C$ t& Z# o; u( D0 L5 h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- z9 B5 N! |( v1 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 h$ I' s* U6 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: [% W5 ]& N; k+ M& Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* r; {& E5 n7 }/ qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); r( \/ C! H* A9 J( w* I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 x0 r& p: X( k" n+ F; D
0x00, 0xFF); /* configure the clock for transmitter */+ |2 j; t, R$ F& K) b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; l; y% g6 ~+ S) m# n5 j" \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ E3 @; ~, }+ C' T. kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- S0 h, l- O8 \& \4 M% V$ h9 V
0x00, 0xFF);
) p) w/ T* U+ A3 ^. {- N% Z9 f7 R% v% t' t% W0 F( i
/* Enable synchronization of RX and TX sections */
$ S" Y; x. e2 Q! M, V8 Z+ ^+ l% v2 gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: `( V, B' Q% N- @$ r/ R! OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ h- B( q1 C: O4 `' A) h, s9 D5 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ F9 r5 W8 ]7 T
** Set the serializers, Currently only one serializer is set as
9 v9 }; |+ j' i( \. U** transmitter and one serializer as receiver.% l: N+ r% \9 ^; ?
*/
& y c8 o' h$ K- ~8 ?. W# S/ f1 V- WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 B! G4 A' d9 e; j) U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 l. q$ [, v/ P2 S- m, Z6 u; _5 d
** Configure the McASP pins . H. }& i5 @7 w2 B
** Input - Frame Sync, Clock and Serializer Rx( E* U$ B: Q2 P# u
** Output - Serializer Tx is connected to the input of the codec 5 w1 e! \9 x4 ^) A" ~
*/: p7 y1 S3 y7 q; \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 ~% k/ J9 I: V' C1 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 i1 ^) f7 x; V+ P5 J/ r4 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& [5 L% c- \# I. U5 N8 \: e( i
| MCASP_PIN_ACLKX- m. l" b9 \/ q' \6 o2 I! h7 w
| MCASP_PIN_AHCLKX/ ?& {! A3 L4 ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. {1 G! N( ^7 C1 K- @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 C+ v0 ~% e7 q- a7 u
| MCASP_TX_CLKFAIL - x- `* ?2 W1 ~) |7 L
| MCASP_TX_SYNCERROR
7 f6 ^- y% `2 Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 b, W+ M. ^3 G: t| MCASP_RX_CLKFAIL
5 y+ H9 P* G7 F" Q7 e: c8 U| MCASP_RX_SYNCERROR
8 } F, d6 s2 n W| MCASP_RX_OVERRUN);7 s% e9 T5 f x9 C0 S0 n/ m3 b
} static void I2SDataTxRxActivate(void)) @2 h4 d0 W/ A- _' t( T8 o2 F
{0 b! J7 G8 m! m7 T* @
/* Start the clocks */ x. G( |7 B; l8 j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- t8 t: M$ K: h$ @; t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# i, e# { R5 f) c' `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ ~$ ~8 O6 A2 L" O% _% U
EDMA3_TRIG_MODE_EVENT);
4 z: g4 w! }9 \0 n z" B: Y" H! }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' K! J4 i8 G2 l# t% Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! o! N: o5 U) E" _: p1 ?8 q. z, }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# h0 {. n, p) \5 D6 }6 N9 n# {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
Q2 `9 ?# I" ?" q( D: nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' t: X& L; Y$ e+ E0 P3 \0 `$ A5 @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 V0 @- x6 I# t( s" i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( v: n+ J( [1 Q* w9 `
} ( l) J. ~; V: a- q. O( Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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