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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 I+ J" M3 ~' I- M
input mcasp_ahclkx,, O9 u3 i( `1 x, @3 k
input mcasp_aclkx,) Y, Q" J# Z) Q! X
input axr0,7 ~0 v3 p4 e; `5 i. S* w
; a$ a7 Y8 e1 f, _) C, K- r
output mcasp_afsr,( w/ ?$ {; \( `
output mcasp_ahclkr,
# x+ V1 g: ^$ G& X) `( Woutput mcasp_aclkr,( Z" d4 z+ E; W: D
output axr1,
4 C# Q# P# e% h assign mcasp_afsr = mcasp_afsx;& a$ ~, b' j* \! ]) S. o
assign mcasp_aclkr = mcasp_aclkx;' _7 \8 | a2 N' D
assign mcasp_ahclkr = mcasp_ahclkx;; M8 K+ Z$ k8 w+ p+ i( Z1 }
assign axr1 = axr0;
9 P$ m+ o3 d+ U8 R/ N. ]0 j1 V" o, V0 _) a$ ?5 v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / \4 S# z- f) k5 T
static void McASPI2SConfigure(void)
2 J8 s, F) S8 B2 }7 t8 q! S1 s{
; _0 @# t2 e0 ?2 B1 d; Z- Y0 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 ]% o: M) g F& y, VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 h8 d# c5 u/ S5 T- \1 O, s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ H3 e9 V4 D8 p- c) N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- Q; ?- ~/ `* T2 U% M) C* HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, T" f, m/ x: \% x* O" _$ Y( O
MCASP_RX_MODE_DMA);
5 ]+ i: k* i3 K+ Z5 T4 T) l2 a1 QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; j) ]& [& c! S6 Y P1 J" }+ _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 ~7 |) f O3 T9 |' I9 DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) w; \% S0 p! v# b! R b. R- g3 ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 `* U3 Y8 h( W& \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 L" v6 T4 d2 w* YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 L# ~' q* Y+ Z; M; s+ A( M$ G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); `9 ~ d3 s8 ?6 B; `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# ^( k" Q5 T, A# Z/ w; R- o) j/ @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 N. v5 Y2 d0 f( ]& Z8 [9 ]9 W
0x00, 0xFF); /* configure the clock for transmitter */: N$ F- g$ f1 D" i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! }) B6 a+ q r, J; {9 `1 C0 bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' b6 h' P( e3 {) E% E' w. GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, W! }2 i6 L0 u% L% d4 j1 @0x00, 0xFF);: o; C+ B/ G+ a+ `$ _7 w* F
" q6 ?' a) q$ c, h: v+ m. [/ X/* Enable synchronization of RX and TX sections */ 0 }$ C* D% @, f. Q! x' M4 { ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ J' C M$ G+ w" q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; \/ V9 X" b$ ], |8 S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( d* c2 ? J) a
** Set the serializers, Currently only one serializer is set as* v8 J) {, N3 f9 I1 Z& u
** transmitter and one serializer as receiver.
& j! @ ~, m) [; M*/! x; s* q/ K1 ~! M/ o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 z: C' u' C- A' \, Z! R8 B' jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! C& I, I8 D1 Q$ L; B; j6 L** Configure the McASP pins
?/ p( _# C% v* A8 }7 a** Input - Frame Sync, Clock and Serializer Rx
8 e' ~; h8 O# j. t** Output - Serializer Tx is connected to the input of the codec 6 }7 V, C: B( x; Y- i3 e
*/
' d( F/ ~$ t i! W- GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 a) q, H' F2 Y& eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 ^- w3 B% u6 d9 O. P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& H6 k; Y' I; s7 |5 c t" r' r4 f
| MCASP_PIN_ACLKX
0 J2 c; o4 l1 P% P, t6 N9 S3 ]4 {* d1 a| MCASP_PIN_AHCLKX- \3 O3 o9 p) a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 c; m. l, [8 u& G' a4 d T. o* u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 ^0 o4 F5 h$ K$ ~: Q| MCASP_TX_CLKFAIL 0 i. B: K; A& h8 {% w* ?7 V
| MCASP_TX_SYNCERROR: v# N% u) `! N( u, @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / ~ q$ M' @+ y
| MCASP_RX_CLKFAIL4 b: I$ X% ^6 X" W( {; `2 n
| MCASP_RX_SYNCERROR
" y* p8 i: O) B| MCASP_RX_OVERRUN);
, i) g7 J# y+ d- g; S# i} static void I2SDataTxRxActivate(void): V% k! |9 i9 B; X
{( _: X& E5 X# U9 z- J3 r
/* Start the clocks */# j' b. v6 C. V O. b6 E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: _) w& Y# C/ D4 B6 ?9 {, TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 I8 |" d" H# p; i& Q7 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' C( N9 W, \, s3 C9 [5 @
EDMA3_TRIG_MODE_EVENT);
4 R' c- s: n' j @, v+ E' p5 ~+ HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. H3 S* A) x6 P( N4 ?8 OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( l% i8 G. O$ u+ t1 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 s$ Q4 Q0 F/ |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( U9 X" ]3 S& D# twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% x7 O3 x( X1 r9 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. U& W+ O2 C# @7 z9 d" yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ @" G W6 u# g1 T8 H
}
( k' s; W) G1 w% O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % ^# k* A4 [$ ~% t& T$ a
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