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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ [$ \2 e, f( t0 H! V9 y& w3 K; Vinput mcasp_ahclkx,
# C" r: D# G+ ? a$ I9 i/ I2 D3 minput mcasp_aclkx,* f7 j* L1 U: p! [1 i
input axr0,: m; ]; A3 g8 Y5 ]2 P6 }
4 v0 g j$ N4 y
output mcasp_afsr,2 z- p' |+ D$ C. C4 k7 t6 [
output mcasp_ahclkr,! m: u x6 F1 E/ ^. B
output mcasp_aclkr,. K u- o0 T5 ^, ~" i, O) w; }
output axr1, F7 J0 I. Z- A& t( T
assign mcasp_afsr = mcasp_afsx;
' g9 s( K" G: S5 p8 b3 j4 hassign mcasp_aclkr = mcasp_aclkx;
& U8 n( j5 x! y2 _' aassign mcasp_ahclkr = mcasp_ahclkx;
9 ^; A, o7 |7 r3 S; m7 massign axr1 = axr0; & k% Z9 q# j J1 m) i$ s8 k) r
0 v/ _( @& e' T4 A6 Q( V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ @) K: i2 A0 }( B( [; Ystatic void McASPI2SConfigure(void)5 M! N( g" ~* O' E( O( j
{! z) {5 e0 H5 _+ X7 N# B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 c2 |. S* y$ \2 J+ |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; v, W$ H# W8 ]1 D- a# c* \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 R8 \/ M! \) o& s1 C. T' c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# |* i4 x8 W3 u+ A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# ~) j9 G; o7 n) D. A/ v% \" S/ W/ tMCASP_RX_MODE_DMA);
& Q* A( a% g9 |9 H- f! I( UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. H1 a3 p5 D1 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& O. F1 t2 c8 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 w+ A5 r) _( ?" S& ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 |$ k* {% b3 I: e: e' x" XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * j1 H9 c9 P$ ]; p9 w' x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 h% W( p( }( X! V5 E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 I4 N: l `( w. p( v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / u w. w& ]3 a9 \6 c7 |$ X1 Z" o9 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 Z2 q0 U: k) \3 V3 ]& f! s3 H0x00, 0xFF); /* configure the clock for transmitter */
' t0 M/ Y8 p* Q8 m" IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! ?; J3 d9 W2 U# I6 ~$ vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 y2 d, ?; b8 m) j' E8 Q) C6 N& vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; |% U* z+ T+ G" r& w
0x00, 0xFF);
$ x& J9 C0 W2 Y) r2 P/ ~1 h3 m: e) O2 C; ^# W9 d2 ~
/* Enable synchronization of RX and TX sections */
" J$ [( v" Y- e; o/ qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& ~ C: e$ R% @1 wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 G+ {2 S; R' S, ?: w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: v& _0 W4 e8 `! R& n/ Y' r* u X
** Set the serializers, Currently only one serializer is set as$ H) R# K6 E, U" A/ w/ j5 }) ]
** transmitter and one serializer as receiver.
; c( @0 Y: z! h, b, ~5 i*/( Y l7 @3 P" f' K$ ~. G/ A, Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, j- L8 D4 H6 s$ o" R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 T9 q7 D+ X7 O# f R
** Configure the McASP pins
/ m& w: t. [. ^" M# R0 K- X7 y** Input - Frame Sync, Clock and Serializer Rx
6 b2 q$ ]% H# i2 o! v( c% p** Output - Serializer Tx is connected to the input of the codec 8 `1 A4 Y! C) ?4 f- d' C
*/9 Q! i7 C1 |& a6 _6 x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ N; h- }$ E& L1 c+ ]' tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 I( V4 r0 h+ o' O3 u1 V8 F/ w+ R9 x NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 w6 C5 ^5 ^5 M9 ]
| MCASP_PIN_ACLKX
8 f# y' ^- {% S/ n/ d| MCASP_PIN_AHCLKX0 `$ z! R) Z6 m% s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) M3 W6 C$ a. h2 l* iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # {! k# Q+ v* U4 \2 x
| MCASP_TX_CLKFAIL
4 D5 Q% c. P7 {! l& d| MCASP_TX_SYNCERROR9 I# `- J' Y4 i7 p# n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; o9 B* C6 z+ V* y9 N
| MCASP_RX_CLKFAIL
/ O" J0 v6 w) w" [| MCASP_RX_SYNCERROR
; C0 J. K- I$ j- u% ^| MCASP_RX_OVERRUN);
: u0 A! v# P$ W2 u} static void I2SDataTxRxActivate(void)+ O0 t& H a: X' ^" T7 N
{
" ~. Y" I, f" q z, n6 z/* Start the clocks */( f& ?* p2 m. }: A" d: \# q$ X# ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 F( V# l: {8 V5 Y' F) pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( E. s) ]3 E8 m( x' e- j' y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: z" c i; G" `5 ?6 e4 q7 y; |6 F4 Z
EDMA3_TRIG_MODE_EVENT);
0 D! J; U% B3 J2 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 Y$ U% w* K0 {' ~1 |& AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ P) z9 |+ V c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" K4 d4 p1 P% X% i: y3 R; o: X k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 `4 D4 ]- A' L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 V; W1 x6 o& {$ TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 a5 A' H2 d- _- R. zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- c- G( F1 z8 k5 O" ]
}
$ f2 W+ E+ m! u: j6 R; N& H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 V5 M' J9 W) ~* v/ g; W, r
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