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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, R, o* [$ x6 M# Winput mcasp_ahclkx,
1 W; m) o! w2 J9 Z! T0 ainput mcasp_aclkx,
2 O& s" C0 [$ e# rinput axr0,/ d. b- W q) V( Q/ x% d
" S2 B# @. t4 W- ?( Moutput mcasp_afsr,
& H. h/ q: h/ ` z! Z5 k0 E4 zoutput mcasp_ahclkr,, d7 |5 M" }; x5 c; v B( m
output mcasp_aclkr,+ v3 V7 {$ D- V
output axr1,/ z' s8 _, i) V8 k" Q* |6 ?2 y/ R
assign mcasp_afsr = mcasp_afsx;" }9 ` h; Z* {
assign mcasp_aclkr = mcasp_aclkx;
! h. S( b# K/ V/ t4 ^( G& \assign mcasp_ahclkr = mcasp_ahclkx;
9 p- C+ w; _: n, ~. q6 s5 `assign axr1 = axr0; 9 d4 ]0 j' n$ M% Z7 f6 T. f* s$ \/ E
- q; U ^$ w( R y% I8 F" E5 y4 ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , B; E ~) k. F t" [2 S/ i, @( e" i
static void McASPI2SConfigure(void)
% e$ J) g4 C, E% U2 B' U1 j{
/ l2 Q- W- r% b5 } GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" L* A% R4 t I9 O3 @; e( y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, l; b6 L- k6 S$ h" U% MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ h, P( ~) N1 `+ l6 _, {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! }4 Q, H& o) X6 F3 w2 J! x3 n6 Q" `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& `! P& R$ @: K5 u3 y" kMCASP_RX_MODE_DMA);
! K( [- I% ]8 M- e% U% HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% L8 |/ T) u0 x9 C/ |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 ?% J+ m, l! E' t* n6 [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) L4 ` }9 B- K# s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ d( I) d1 ]# N+ ]$ }# s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! g0 p8 }" W9 G" S, Z+ r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# r) E: Q7 o8 @* C5 E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* N/ U3 M8 p5 a$ vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ H% `0 _' r2 y- o' s+ Q- SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& C3 P; d3 d( C7 h! x6 m0x00, 0xFF); /* configure the clock for transmitter */5 T3 @, n/ [8 ]8 q: |, p( F: G) M, [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; A- g7 R) W5 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ z- t/ L" P4 n) o0 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ K8 `" w( g: D/ x0 O6 F0x00, 0xFF);' L! k5 O, f, V% _
4 }0 {1 L0 T) q1 j/* Enable synchronization of RX and TX sections */ - r0 v5 T! ^$ \$ i8 m$ t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 E) o& S* a5 g0 S- ?" |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) B! v+ T) `% V* j/ a0 f/ \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 ` r4 E2 U6 x( _0 N4 G** Set the serializers, Currently only one serializer is set as
! Q" K5 v9 @1 L) E" ^6 N+ A** transmitter and one serializer as receiver.4 i" `9 `9 t0 A1 ~, c+ S+ `
*/8 D5 u, P$ t! W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 G4 w# w8 w1 ~- p' ~" r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 \) A" D1 b* D. @. _$ _2 R
** Configure the McASP pins 5 k/ m1 W1 C$ K0 s# M
** Input - Frame Sync, Clock and Serializer Rx8 J: y2 N1 l* l3 |
** Output - Serializer Tx is connected to the input of the codec 7 W+ C ~$ z, R4 `7 `( r3 L
*/
- a2 N; r" k% j- |* z( }# {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; e6 X7 d0 t- B8 s, n1 l: t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- F1 t1 u0 ]0 H" s6 RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 i9 K/ t! k4 l; w0 }- e| MCASP_PIN_ACLKX
; g6 E. P. @* L3 S: {| MCASP_PIN_AHCLKX+ b; o# {, l* j. G) y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 `: f' ~- l* @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* o3 j2 g2 f4 J9 v# F| MCASP_TX_CLKFAIL 7 N. `9 d3 T g# s2 e' f/ O
| MCASP_TX_SYNCERROR
; q, W* ]8 G, T. x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR g4 W; f4 m$ d0 S- b
| MCASP_RX_CLKFAIL
( v4 F, N0 Q8 p! b0 u; I| MCASP_RX_SYNCERROR
+ n( A9 A% b% S# [* c7 ]| MCASP_RX_OVERRUN);
+ d7 z- E, ^- e, ?; K" E2 ^5 e} static void I2SDataTxRxActivate(void)
9 U; g \0 g k{7 ^( j5 g& l x! [+ S
/* Start the clocks */
6 U8 K4 S! h i- M' E5 JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. T% F# w/ Z6 |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- o4 H; b `% k: Q& \% K3 j- B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* Q1 ~. M+ M- t6 W {! ? ~; z& e3 x1 C
EDMA3_TRIG_MODE_EVENT);+ z. d& b1 d% t8 x" B3 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, u) a. f7 w' ~8 D. n' D/ J% _, F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# m: q3 W8 s; ~' X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. V) ^2 v, I5 j% ?6 D! h+ t) Y% xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( `+ V1 k6 _1 g9 wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// y0 B8 q; U. ]3 V' |& j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: U! t2 f. z( H1 Z: t$ P2 R, j7 m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! I" a0 e4 h2 @ v$ Q
}
5 M1 f: a1 ]2 ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 b9 Y* _8 h$ A: Q
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