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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' e1 g- K' M! }7 A! H% l
input mcasp_ahclkx,: v) G& [' r) F
input mcasp_aclkx,
/ _" L3 s: v+ E+ ^0 E% U/ u" \input axr0,' w/ V/ }" J2 ^$ E
& F _5 L$ g( S- d' G5 W" xoutput mcasp_afsr,$ C( u# `7 c& o1 ]
output mcasp_ahclkr,
3 ?7 V7 m, q. a2 M1 H. s6 ^: }/ Doutput mcasp_aclkr,7 s- H2 [; {$ c. X) D
output axr1,
7 t9 E% R" w6 ^2 B assign mcasp_afsr = mcasp_afsx;6 m/ E9 B( |6 D, m& w
assign mcasp_aclkr = mcasp_aclkx;
# ^$ q* i' K" Y% cassign mcasp_ahclkr = mcasp_ahclkx;
% O6 k3 V* Z0 `- M# aassign axr1 = axr0; . V$ F @9 h. I9 H/ Q: t
l& a; ~/ r) e: m! U) i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' e) H$ s6 Q& G/ Y$ T1 ?0 d ^
static void McASPI2SConfigure(void)
$ `: D5 M' b, P2 _; Y; T, E{7 m; x4 e, X% J2 T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ D! y. q4 f8 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// {- y9 r$ v6 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 D- u0 A9 x( N9 H0 CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 @9 u* p' [! [- g2 C4 g6 LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 m; E/ u r+ M( ~% ^7 w! r
MCASP_RX_MODE_DMA);
" W8 I5 E3 E; IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* \, l1 j/ {8 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; j0 J7 S% B8 P3 rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: d- ^9 O+ D6 t4 E5 f; iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- y! @9 }* @! A: {/ H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; L2 k- [( h( j2 W& @) u1 w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
g' ?4 c; ]# kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" Z6 k9 p! P3 W$ mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, z: _* o9 B1 J2 N7 F pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) Q7 q: p2 G, L; x0x00, 0xFF); /* configure the clock for transmitter */4 i# X! e5 S% h) j" z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: N# a) b8 U/ [1 N" |2 z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , o& J- D- e" G1 r( C ?: j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" i' C4 B" Y, y: U1 J0x00, 0xFF);6 D) b& r. Y6 q0 \6 W' R
+ f2 [3 K b6 n/* Enable synchronization of RX and TX sections */ 8 a; n" d5 @- \" y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 n# c3 V8 H: d; K! }' _: V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: o9 l* N! R$ B5 @* s, _0 f; M+ ]8 s; jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) M/ U6 E% \- c& q5 \6 X& z% l** Set the serializers, Currently only one serializer is set as
% @! C6 G. R: Q' S" ]# _, _1 V** transmitter and one serializer as receiver.
& S% V; A) o* d7 A*/4 l: S+ W* H9 C4 P! d6 Z6 R( D4 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 E4 M; J- G5 `5 {1 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) M; i" v' y. ?
** Configure the McASP pins & A" d1 T+ s. B/ r! Q- p
** Input - Frame Sync, Clock and Serializer Rx
5 G; \! r0 [9 s+ I1 Y** Output - Serializer Tx is connected to the input of the codec & e5 E2 I+ O$ W7 N2 }& {: C8 h
*/& ?1 f6 w7 n7 T( U! Z1 E! E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ r+ L/ g1 Y4 D: P+ ^& Z$ OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# G( W/ z1 ~" l- t# S- X: C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 [' c3 e/ ?7 z' S6 c R$ B# l" ~
| MCASP_PIN_ACLKX
, |( V/ F4 O' |& j+ G| MCASP_PIN_AHCLKX
/ J+ Q; X; ^, Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. q0 f* r( T6 z$ ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . T$ z0 V& k+ G& D5 c
| MCASP_TX_CLKFAIL ! h7 `/ L7 n2 ?
| MCASP_TX_SYNCERROR
$ K4 r+ f7 K( a4 d: ^1 X1 K, j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 @* C, [" @' I6 p, y2 H$ N6 B. R| MCASP_RX_CLKFAIL
. k! e2 u1 ]4 N7 P| MCASP_RX_SYNCERROR
6 P8 l" d& E' G| MCASP_RX_OVERRUN);- s, E L& Z* {
} static void I2SDataTxRxActivate(void)3 r9 @$ N0 E% B0 x8 q
{
7 t9 }- ~: V5 V4 j& c7 i( Z/* Start the clocks */8 u3 j. F! ]0 Q, z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ C& V5 @% E3 l; \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# e! D; }4 _8 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 P- R* x0 r; X& A) s/ G
EDMA3_TRIG_MODE_EVENT);9 o8 x1 t3 a1 j! ]/ r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % d; z% u1 l( _) {; ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 E3 _7 h9 s" X5 ~/ s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% @! y; C1 W6 G% _1 e4 _- Q( v. U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, a8 W5 J9 F2 ~3 ?( iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# u: k: p" U: G) B$ e Q7 @/ p3 s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ K7 o, z u$ `: W+ O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ J8 m" I# t* L4 K9 a' M
} 0 f" ^. w2 m( U- Z9 S2 G4 A2 j' u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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