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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: f+ L: l$ K6 T% j# b
input mcasp_ahclkx,
& z- U* m- K0 i1 \, P: ^input mcasp_aclkx,' `! ^* V6 _: p2 Z3 }
input axr0,/ l) ]: d: w2 }9 q- Z; ?5 g
9 M$ h2 G% {# u% C" G
output mcasp_afsr,
2 q" x7 l3 h) j% d3 M. P( goutput mcasp_ahclkr,
: P7 V* p$ f: \' `output mcasp_aclkr,
& _9 m; p2 Y2 X( D$ O3 Foutput axr1," E1 x4 a" {) U4 ]& e
assign mcasp_afsr = mcasp_afsx;
# C( O6 N1 G. `' O' g1 Gassign mcasp_aclkr = mcasp_aclkx;
( r2 O5 x \' X8 M! y5 n$ Aassign mcasp_ahclkr = mcasp_ahclkx;
1 D7 |, X0 x: r; Sassign axr1 = axr0; ! y- a1 @0 Z% o
& e4 r: e# L" z2 p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 m4 I0 T5 ~/ P( X7 r8 estatic void McASPI2SConfigure(void)
4 w9 E" S2 d2 ]: s. @{
/ ?4 T" p( P! @8 q! `2 f1 fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 }! u4 H, I8 F6 a2 [+ B& g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' j1 u; c% ~) |* W+ r: m8 v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' ~: q5 W6 ?, M, F/ k5 rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ |" J2 ? [) vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" \* ~ V/ l8 j# P2 OMCASP_RX_MODE_DMA);* A! u0 ]$ A$ X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 O5 }6 O7 D# {# F7 f6 f2 I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 C! h0 E2 E4 R! K! M! R6 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : J" h- d2 X* y6 `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. y8 E8 k' n4 N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 [* H3 ~! ]! t! F" i) m- l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 @3 L1 y& X d8 I3 j. ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, x4 p* Q2 C2 O1 G, ~+ I5 g) I' Z1 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 z! c. }$ ~+ s0 O1 |; e: g% EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ w9 i) i# t5 D# F' D9 g
0x00, 0xFF); /* configure the clock for transmitter */, @' d, B2 N" |( D9 J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 h$ C7 i3 `1 j; Q, a$ |6 v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" O- d, z/ _2 |( ]" Y! D0 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 a8 w5 ~1 | J6 \* Q/ |
0x00, 0xFF);6 M( W" g" w9 x6 X
( L$ ]0 o7 h6 @9 M+ m
/* Enable synchronization of RX and TX sections */ : _ _; I) w2 J7 L) I* J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! }: v: j4 s% D# R+ `# C1 ^( P; W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. i M0 P3 W* W% {9 u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( F0 \( O- l6 \** Set the serializers, Currently only one serializer is set as5 Z9 q& E6 y& r% o7 D8 U. k
** transmitter and one serializer as receiver.0 x$ _, {% S* [8 ]$ U# J3 G
*/2 E2 D$ f9 K6 w- n- v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, Z% [' l5 o* x! L5 W2 o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- C2 n; m ]) H7 D$ M' k" t, Y** Configure the McASP pins $ i c; k( E' {
** Input - Frame Sync, Clock and Serializer Rx7 A6 V* i9 F8 U: z, d4 C' g
** Output - Serializer Tx is connected to the input of the codec 1 T% x8 ?! T' |1 G, p" r, J1 C
*/+ q' h" p+ X' T" \4 S) ], S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% \$ ~. U3 H( u! R8 j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# i1 L4 W6 l8 d5 U$ x+ u0 t4 v4 Q* W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; D3 L# O4 l P# X: {% j
| MCASP_PIN_ACLKX
: |' p: _ ^! K: H| MCASP_PIN_AHCLKX
& R! z6 R/ D8 ~8 P6 z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! H* r) B" ~8 c. m- t7 D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( r P1 q4 G% j( v6 Y* X7 G& t, J
| MCASP_TX_CLKFAIL ' C2 P, b& u! {7 _ S2 ?! f
| MCASP_TX_SYNCERROR# {2 {- G7 q2 [( T/ e$ y4 E0 R0 M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : z: B5 E& x. E4 f! ?6 |
| MCASP_RX_CLKFAIL5 \ X; |* t* O- x
| MCASP_RX_SYNCERROR - L( d; M- ^) \5 P0 ^- p3 r
| MCASP_RX_OVERRUN);
$ N3 e% p" h3 ~7 S} static void I2SDataTxRxActivate(void)
$ m$ g' d1 `" J" X V) p, e7 p Z{
- {# I" {# N! ]5 i/* Start the clocks */
' w- C$ {5 P M9 BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& L0 L( j/ W+ |& k' }6 }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ d; r9 t! R" y) E0 s8 N3 O8 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* t! a, a- g- G2 W) Y
EDMA3_TRIG_MODE_EVENT);
1 ]6 T8 M5 A9 c9 ?5 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / C) U* R L4 n/ Q2 g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% \2 L$ J0 J5 g: Y" O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' k8 k. e$ J, m6 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 o3 V$ ]2 O# a3 T5 ?3 M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- T* O! I0 D* y8 V5 I2 T/ i* t$ n) BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: V" c: ?( p% D" j g( SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ D7 Y) M* z. I- \- f4 Y4 e+ G+ g
} . J7 M4 Q. W& w3 h" U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 J4 H- v! E& a5 f9 `% L) m
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