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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 E4 P4 H; H# _8 W% ^
input mcasp_ahclkx,
6 f$ M& r- u( q/ Q, D/ m9 [6 Sinput mcasp_aclkx,
' T" r4 \% Z" minput axr0,
a* {: o# C; z8 C( c" j
+ [' @1 E1 b1 uoutput mcasp_afsr,7 N5 {' r. w. d4 Z9 q
output mcasp_ahclkr,/ u! g" W. u1 P9 t0 U
output mcasp_aclkr,
: a0 A0 R5 @. M) e' R% Coutput axr1,9 @* M, a- q( J9 K" m2 y- ^ l
assign mcasp_afsr = mcasp_afsx;& R; L% {1 Z- S6 p
assign mcasp_aclkr = mcasp_aclkx;; k: }+ s# P, ^
assign mcasp_ahclkr = mcasp_ahclkx;
9 `% @4 a% g( F; [assign axr1 = axr0; $ i7 E5 h/ H+ T1 H8 G
3 r# i) T/ F7 n' a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& b- ^, r% f' V- C2 B3 R2 J9 \static void McASPI2SConfigure(void)* X: w2 q+ ~, Y0 G" m
{( c4 P% j2 ]6 S$ l7 W2 V- W& t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" s! H9 l0 e/ o( q! y7 S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( K. |7 P4 k. qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 d, d w. p$ J9 p1 v: C r& lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! J' _+ l8 D7 e) B' P) w) }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ M- O2 ^, f. J" T- i" [MCASP_RX_MODE_DMA);
; y$ U% p% z+ B: f3 E( ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! r2 p( l/ M( R. Y# n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& A1 o$ e( d: w, m vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 ]" [% ~' w8 K% Y' ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 E5 ^1 V% L' x0 v9 Z9 e LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , q* B: r! Z* r# T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ y" Y* l! P" }" Z/ |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% \6 x- e+ w2 C/ d( _6 eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 P! p% ?- H! S( DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 _3 U' L7 x. p& {& q' F
0x00, 0xFF); /* configure the clock for transmitter */# ?" Z/ N3 H0 z" y8 ]" r+ u5 X8 @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' ~* j/ @ C4 S& U/ d1 ]' aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 C1 R- d2 A9 [ k6 |5 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 a# B# Z3 F: v" }$ r4 D: `0x00, 0xFF);
$ y( _6 @. P( m- F
6 P7 @/ p1 _( g% C/* Enable synchronization of RX and TX sections */
* @. I" q9 A5 z) z0 L2 M( j, ?* ~6 z) vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* C4 Z3 @% u7 H# C# EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: Y$ ^4 w" N; c1 a! ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, M* R$ ^, N% W# v" j& B
** Set the serializers, Currently only one serializer is set as/ l* |2 B: t- D' q0 O/ T; C3 C- Z
** transmitter and one serializer as receiver.! [/ R, T3 |" O8 A/ C6 J
*/
/ X2 s; q8 [& P. xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 T1 m6 L, V! W% m7 d' Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& L6 F6 D0 `7 G; p% b! j
** Configure the McASP pins
+ H2 A) }0 ?, y# r: {" U2 t** Input - Frame Sync, Clock and Serializer Rx! b' K% }/ ]6 Z- x9 B3 H& B
** Output - Serializer Tx is connected to the input of the codec
' l/ y. r: a1 i, T*/$ [4 s% k K! R3 m! a: Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, ~" M. X; G, O0 K* S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( t3 W9 G8 F, B" p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 p: k3 Z# K# X- g- C) U. w| MCASP_PIN_ACLKX/ d/ d% J& |$ [7 p% z: V# Q( {
| MCASP_PIN_AHCLKX
; v4 i) _/ Y; T# F% g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ r2 {9 B. U0 V. i* X, ^" F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " u5 b; { b( c, l& p" f* E! j
| MCASP_TX_CLKFAIL
5 X) O5 Q) C' b$ @% F| MCASP_TX_SYNCERROR, r, I6 S% a1 S4 K4 M; F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( C# Y$ ?' a# v7 Y& W( b
| MCASP_RX_CLKFAIL
; B b2 Z" h# o) k6 ^5 G| MCASP_RX_SYNCERROR + @$ _. L R- ^! m, H' D
| MCASP_RX_OVERRUN);, J6 ?" z' t+ \# e- P
} static void I2SDataTxRxActivate(void)
0 C( l3 I" k4 H' a" c- R( Y{) C' p# ~. H# _9 z: \, [& `. |
/* Start the clocks */% b) G ~, P4 @( l4 T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 U8 R) G# m9 \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 n! n1 x! ]- f0 e+ T. j8 J, `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' q8 q7 I# _7 p g# U9 W
EDMA3_TRIG_MODE_EVENT);
3 p* v" [' J5 i: j8 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & D' i' p1 {3 D
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 B: a7 g2 p: L, P6 D# z4 Z# p, Y, N4 r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ E6 u0 V. B, {) d0 S( c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' J5 c5 z7 q/ a+ L3 E+ Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 R r3 q" A3 W6 j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); F3 S; P$ W5 p6 d- x e1 z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% ]% [# |) _' j/ T: O; r( X4 i
}
; z7 q* X7 r# X3 a/ G0 l/ |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. n: P0 ]( m' [
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