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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 b$ ]0 \& e6 h& ^# T# Sinput mcasp_ahclkx,
7 F& K/ M1 ]5 l; i% \1 e% t1 ~input mcasp_aclkx,% O, b" a9 I0 p. u
input axr0,' g @* `( a! B8 ]9 i- s
5 Q2 u. W' Y2 {1 s5 D: Aoutput mcasp_afsr,
% ?1 M; K+ p! G+ l# Goutput mcasp_ahclkr,
3 ~' X r3 k. ]* G2 f3 V2 routput mcasp_aclkr,0 O, s/ \" t2 z5 `" Q" B* x
output axr1,
' B5 ~# k! E6 F, d assign mcasp_afsr = mcasp_afsx;2 ~$ @" m' z/ C7 d- l
assign mcasp_aclkr = mcasp_aclkx;; e9 t( U* p. [/ I) Q
assign mcasp_ahclkr = mcasp_ahclkx;
% O3 Q; ] A* R" G( Passign axr1 = axr0; 4 \$ O e0 k7 t) P, }
# y/ u* j3 a! @. n8 f% z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ v1 L3 n- n- O& r
static void McASPI2SConfigure(void)
# F7 F7 R/ C9 |& L: p1 X% k1 n" ?{
2 D! L% b5 w9 E- gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& N; b1 g% Z! z! t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" f- \3 Z+ M3 a7 c% bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# t w1 R r# q. m' G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# H; W! f5 ] u. PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" n* B" z) ~5 s5 c5 ^/ bMCASP_RX_MODE_DMA);
$ W7 f: H2 v2 g. S; c7 ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; R, ~6 j' t0 U+ t2 XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! R9 b6 o- c2 @8 |% r" m+ p8 o; \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 ]4 q' J2 j5 f/ N! W# q, W8 ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 W! X# _3 l. D& M$ DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , r% F% O( q6 \% u+ r& A+ p* g5 I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& n( Z* }+ [7 \( A" v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- O- P) F$ r& p+ h# U3 H3 @- R' KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 ]4 X- F( {+ D0 |, s3 O: W& A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# {6 Z5 D5 t9 w W
0x00, 0xFF); /* configure the clock for transmitter */
$ H2 r% ]- r- g& ]% vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* {7 }# g; F8 i) @5 s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - p: q2 i, K! } t( k. Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 q, L+ o, H* y# s7 @
0x00, 0xFF);9 f7 i, z$ I8 V
* h: v8 A) n! S9 o2 ^% |& ~5 L/* Enable synchronization of RX and TX sections */
7 o, u3 V. i! ^2 AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: G K9 w& w. ^3 D# o% R5 D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: r7 U: ~: M& @# Q% [0 d3 W) x4 e5 c& f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 r; o0 G9 ?, E: A& a** Set the serializers, Currently only one serializer is set as8 j5 \+ ?2 i k* j- v
** transmitter and one serializer as receiver.5 p& X( g0 Q& O6 h8 Z
*/
) ]" s7 \5 w8 G, \* d, ^: FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 g7 h: H% l Y& }& M: S, W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 |! ?. D2 l1 Z# O4 C7 n
** Configure the McASP pins
4 v( B E& x/ R** Input - Frame Sync, Clock and Serializer Rx
/ ^6 t$ T. ^% m P! a; O+ z** Output - Serializer Tx is connected to the input of the codec ' O! O( C( p F- g
*/
6 L8 U- Y: W/ j1 b8 lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" M' d/ G9 H% k7 W/ D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' B+ p0 B5 ?8 p& H; x; [& i$ L9 ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 ^8 Z5 D V, ] A5 N0 D
| MCASP_PIN_ACLKX1 f3 S1 R- z$ g) e, W
| MCASP_PIN_AHCLKX
9 Y L$ G( R6 i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 o9 N( w F' P0 P' Z! YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . L0 ?* ^$ P+ I$ i: v7 d# Y8 m9 ^
| MCASP_TX_CLKFAIL " w: g/ `' `7 H0 _( s
| MCASP_TX_SYNCERROR
A& e6 a1 P& E0 N' m$ Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& K- M( P& a2 ?# u. x) N| MCASP_RX_CLKFAIL
. z: N7 L0 ?" c2 h1 q6 s| MCASP_RX_SYNCERROR
9 ?5 z5 n4 ^- s* ~. K| MCASP_RX_OVERRUN);
4 r# y6 H. _- X8 V2 |; B} static void I2SDataTxRxActivate(void)7 }8 _9 _/ W5 a. B4 y' p
{$ O: `4 V" O# d, X& B, y
/* Start the clocks */
% z2 X7 D5 ~7 L* H# v% X m1 w0 U$ ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( g: \0 ?+ {! J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# `& b. `. O1 m6 l: dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. g$ {) i1 m! F; M4 @; f" x9 s8 n
EDMA3_TRIG_MODE_EVENT);: c# o6 ~3 O# y8 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " q/ i0 W+ Z) ^3 J# v+ ]7 C8 @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! C9 { h- b) r$ N2 C) ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- e/ Z! T; o* L# vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ @# ]$ @7 b; e `; {# l* L6 Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 `5 Z* |7 L0 t5 ? H7 P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 Z9 X7 u6 A: g5 L, C$ p; Y! |# \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 W6 F9 |/ g( [# [0 o}
/ c' s) ^& ^5 v7 a- F A4 m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - E4 C3 i; r6 @/ I1 d* Z
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