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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 e4 j0 B! ^6 ~, c L6 s* \
input mcasp_ahclkx,
# l' G# n4 B/ S( `5 s& g' Zinput mcasp_aclkx,
$ ?2 T1 Q1 r9 x ~& hinput axr0,
' ], Y4 o* k2 v; ~7 C+ W: ?: ?6 D; E- ]1 F1 i( O' ]0 O
output mcasp_afsr," ]! y9 n& `9 X* }; D
output mcasp_ahclkr,: Z4 g2 x- \7 B
output mcasp_aclkr,+ h- `, W: E/ {% o! d6 g
output axr1,
8 X Z% a9 h4 \* s! R$ C7 w2 | assign mcasp_afsr = mcasp_afsx;& b6 r& r7 ^& i+ j
assign mcasp_aclkr = mcasp_aclkx;
+ R: ?* b( l; c1 h6 v, V$ ^3 Gassign mcasp_ahclkr = mcasp_ahclkx;9 W: F# e+ S+ p
assign axr1 = axr0;
8 z4 R1 T# J' [2 R4 @) A' e" N) j$ M7 J! R) g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 O! Y5 R" t: P8 A+ F0 Nstatic void McASPI2SConfigure(void)
& p# s5 Q3 T# N: W' A3 ^{
: I4 E) s( f* [- A0 |6 ]& eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) |- k- \+ k5 w9 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& J e1 `$ w8 O* ]" h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' z6 ?# o7 m% F/ C+ m, o% C t( tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" R9 W O) n( b$ W2 L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( e% L: {+ P k; t) [+ h1 ?MCASP_RX_MODE_DMA);, G" H8 K, H9 v) ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 c2 @- a0 W# l) O9 v0 _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 p( @. c! E U% }0 `) g( e% O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 ^% W4 h- M. EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% c2 l* F1 L: Y# ]; D- l H9 Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' r. k3 `( g" @0 f/ y/ J9 ~' `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 Z0 Q; A9 C8 z& A( s# u. kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: _5 O# P' C# ?/ L: fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + m+ y9 f0 a: P3 K/ x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 p1 u {- H& T' M' G# v, F0x00, 0xFF); /* configure the clock for transmitter */
2 A4 B# `# x4 q- O( a$ X" V2 y; q7 \0 AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 ^: y/ n q- d0 S6 [4 s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 F% C5 ], Q/ Q1 @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. S, t! \! R/ K0x00, 0xFF);0 \3 O" c, L' \6 p" \) W! x, F
+ W" j5 _* H# ^1 d- r
/* Enable synchronization of RX and TX sections */ ( L6 L I% @! Q4 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# s H8 s* e' h1 J( l) z$ S% z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: z2 G4 n! D+ O6 s3 {8 gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** g1 Z) l/ p7 X2 s. l' { o- p
** Set the serializers, Currently only one serializer is set as
0 ?. b. O5 ]/ h2 W _9 |% |- B** transmitter and one serializer as receiver.- M! J7 f6 T9 M( A
*/% J9 }8 x% l3 Q, X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" y6 X1 `& ]& _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( X: Y9 B( _$ I8 L
** Configure the McASP pins
8 w& I2 X- @6 K ^' D/ _** Input - Frame Sync, Clock and Serializer Rx) q& {& ?1 M. \
** Output - Serializer Tx is connected to the input of the codec ' p. a! Z) w9 a
*/& P& a1 T8 I" |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 Q4 c8 j2 s- |6 c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) w: d1 R: U* y9 Y2 ^7 u8 Q$ `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 D! X8 m- z9 q. T7 F. d
| MCASP_PIN_ACLKX
7 d( d" u6 R. _: K4 I* T| MCASP_PIN_AHCLKX
$ f+ Z1 Q3 \# A9 `* y" d' K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 d# a7 v. f; i0 G6 j1 r: e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 s r( L8 D' X. Z, W* W| MCASP_TX_CLKFAIL
% L$ `) T6 F8 k. M: h| MCASP_TX_SYNCERROR ^- G C3 x* F3 ^* r* {. O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: t; _/ z( n% l' ~' }. P| MCASP_RX_CLKFAIL% A6 u* ^9 w* q
| MCASP_RX_SYNCERROR
, {/ k$ s0 X' D| MCASP_RX_OVERRUN);
[) E8 X# b- q: x# {} static void I2SDataTxRxActivate(void)% H& C1 Q! L' t, Q( H# u
{
) s2 T7 m7 ~( L v! u4 P. P/* Start the clocks */8 c$ [. v4 `9 i+ N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 G. c8 P8 a D: R6 e6 A) A- `/ M( v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 M' a! A) F. G9 t3 m8 c* ~% b0 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) b# w4 i9 \- g; |2 L. y6 @, eEDMA3_TRIG_MODE_EVENT);& D; b i8 x0 O3 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 i$ Q( k+ I$ v3 g- n( TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 d5 k- j/ a6 S1 D6 \( V' b/ r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 j' E; J" l, `6 {7 P$ L5 t% B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 U3 ?3 E. g1 k9 X, w% [+ xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, a/ u" R3 H( a3 A& AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) w% ?& y) E( @/ wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 s! a0 {) h1 ?# m( ^- R1 f
}
% O# ~! E' R% a. S) v V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 b* ~: Y- J( h' @& u# t/ t
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