|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' G' f P) y: p2 J% n- Q( Einput mcasp_ahclkx,
1 T( d+ I/ w- r2 Sinput mcasp_aclkx,
+ Z4 R5 }) O- G1 J# minput axr0,: }. P2 O( z8 k6 t/ V9 {& }
; R$ x6 o( T( l) [( J( D1 Ioutput mcasp_afsr,, j( N. T* M. h3 v
output mcasp_ahclkr,# c$ x3 \ x9 ?- z9 a/ l
output mcasp_aclkr,
: d: d1 d8 f2 v; loutput axr1,
& Z6 y5 S' t9 s. d. I assign mcasp_afsr = mcasp_afsx;7 K4 P* t# o9 C, E3 @5 m( p
assign mcasp_aclkr = mcasp_aclkx;$ d& K0 q: m: L1 L& U0 B
assign mcasp_ahclkr = mcasp_ahclkx;
5 X1 x: d3 K6 ~$ W2 p4 Vassign axr1 = axr0; ! Q1 L+ `: t W+ G
% u' b6 K& L! A3 H, G7 J' N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 _/ \2 F+ U/ s. Y% _static void McASPI2SConfigure(void)% M% H4 u$ N! |2 x/ [2 A* \
{9 v4 O" G" q( U9 m) i2 A' D) U& |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 v. I( c2 o o; \4 Q- u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 U% Q0 x# q3 G! A* Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); f8 h1 N. |0 x2 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ z" e: d$ Y% \: ]+ E& w1 v3 BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ E- o7 a! p: R+ p: M+ }" r! AMCASP_RX_MODE_DMA);
. |: s6 {- t3 q8 n) rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& s4 i, x$ I: Z. E5 K+ r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. Z/ R# i& H" T9 p: n, Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 F" ?" L( U% `5 D9 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ |, S1 _- x ^. C8 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 N A, N9 B% E! }, g1 }5 _1 P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// L. H; P) ]2 f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; t& p) G/ v9 P2 S9 I4 R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% L* z8 U% X3 t* m- jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* y2 o0 k0 Y$ }3 @) u
0x00, 0xFF); /* configure the clock for transmitter */
( j: q; I* H# z- \% R( C4 v! mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 x+ [1 ^; U+ f# PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 x9 D) v+ u- t6 j+ l RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ f! A* |$ r* H. w* G8 }0x00, 0xFF);: L( h, Z0 L. `2 I, C
5 V( V$ }: P! m2 m/* Enable synchronization of RX and TX sections */
6 d, M% m2 n* ?7 \8 Z- ^+ i9 _# EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 d6 d O- D4 B) [8 F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 f2 p8 ?: q4 d5 u2 F+ w0 g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 Q# R7 S5 p/ S
** Set the serializers, Currently only one serializer is set as9 w. O: A x$ Z" M- X& ~$ C! i
** transmitter and one serializer as receiver.; h4 |9 v- s0 e- s3 v! j3 e4 w1 B
*/0 X9 C. j( j! k# g' }% y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 H! ^. V6 B& v9 J. e O( G: E5 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% g7 ]' {& H. N1 j
** Configure the McASP pins & f5 w4 H% Z% H% C; N0 ?. K
** Input - Frame Sync, Clock and Serializer Rx; j! K+ w" Q2 b* Y3 ]/ N2 m& d" O
** Output - Serializer Tx is connected to the input of the codec
& ?6 {; E, Q8 {0 r& B*/
. X, f, r: `: ]: OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 \ w8 b) X8 ~9 j1 X/ CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- C/ G6 D% s2 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ ^# O) W1 |$ |& q) R- f' O/ {8 p| MCASP_PIN_ACLKX$ _& w8 ^2 t/ `$ K( p
| MCASP_PIN_AHCLKX( U# T# @" ]3 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& m1 s* A: ~% v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' z5 n% C$ _; W5 |) O8 T| MCASP_TX_CLKFAIL 8 Z) y6 N9 M/ M$ E& }( _3 k6 V& O
| MCASP_TX_SYNCERROR
$ K% C3 P. P' i' D0 `: ?; v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- i7 }2 A' f' i0 Y| MCASP_RX_CLKFAIL4 ]' S+ l; {5 p2 r+ S
| MCASP_RX_SYNCERROR , V Y$ n, K: G' k/ P
| MCASP_RX_OVERRUN);6 u) F# R$ G8 t4 O
} static void I2SDataTxRxActivate(void)5 D" s3 D! W2 g! `# }; d8 e, S
{
/ @( r" I9 c1 g/ d2 B+ ~; G R/* Start the clocks */
9 o C$ o) }2 N& [8 B- _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! R% r& t9 s- Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 r& e' r, {8 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 j+ B+ z b, ]1 a1 c. X1 p
EDMA3_TRIG_MODE_EVENT);
! s6 S- A7 F. i6 r: T8 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- C+ m) r9 z% Z! W9 D4 ]$ U6 sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* N3 r2 T* [' ~0 C. M- P/ J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 }: N1 _0 A$ t: p" G; \$ ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 Z( l' {3 V: | g# Z" |3 Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% N3 |! e' }$ P1 B, |& O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 u7 P# c& n5 z0 g( x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& |+ a# e3 O# i5 ~5 h N: i
} : V$ D8 V5 b0 G2 _; y( V2 a, @/ E( f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
, e" J& z3 g: C1 P |