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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 k* \1 u0 `4 h
input mcasp_ahclkx,7 m( g( i0 U+ Z
input mcasp_aclkx,( E: c* o7 K" @/ Z1 ^: x q' u
input axr0,
+ N% v. _& P, F2 G' B' J
" i! t" q" I0 |0 Joutput mcasp_afsr,
' l$ d0 L6 r0 I4 s4 toutput mcasp_ahclkr,
& _2 c' ]" c5 A! Y" @* Foutput mcasp_aclkr,9 M2 M4 I; W1 `8 h' z" v& _9 s
output axr1,
" |$ S7 p9 W' l assign mcasp_afsr = mcasp_afsx;
" ?" j# q$ {- B4 p0 }assign mcasp_aclkr = mcasp_aclkx;
& a" w, ^) x$ s5 C" w6 D" rassign mcasp_ahclkr = mcasp_ahclkx;' y% V( d/ ~0 V) |. L" m* I1 A" W
assign axr1 = axr0; 9 v$ r0 L$ n! V. B2 b7 s4 B' a
/ s! m8 ~1 a4 ^) H: M ~" U2 [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 x6 B; N( H! O; u: N! u
static void McASPI2SConfigure(void)
# i3 K' P5 Z) D{, l" _9 a( {3 j8 L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 U7 b# e9 M( v- \- r7 X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. w: D' [, o+ {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: @ r9 w; I$ zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- a, U" }. t I) l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 O4 Y A' c* d8 C6 m
MCASP_RX_MODE_DMA);
5 F! G& k* j+ z2 N2 lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 V4 \! J E7 b$ ?9 l" I3 l' V8 R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// X7 ~5 g7 D d; \0 j: S U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 h! R. h: k4 s ?7 j2 [6 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 l9 _7 u9 i) P } f2 I" C! ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 t: Z# v* p( R( [' rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' C" A( ]$ D3 w" M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# |4 t# m, B. V# k# ]/ u, {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - n. h2 p$ T) S$ h! [ E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 r2 l) r3 O Q0 ~0x00, 0xFF); /* configure the clock for transmitter */
# U4 w4 p8 T0 b7 d* GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& b7 g, z8 w9 z$ C; BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " {8 i/ c6 I V! a5 m+ }$ X( L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ X$ u' {/ C4 h3 u& o
0x00, 0xFF);
4 S, S f$ o; _$ G. l' h: Y9 o7 g. S+ R7 N8 ]
/* Enable synchronization of RX and TX sections */ 8 x# _6 I/ X# M7 g% h9 o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 J. }1 K$ W% W; S( C# |" ~) x; E' M; u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 G. k+ _8 v0 _9 f* m/ Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, A, F W. ?' h9 V& ^2 ?8 p8 _** Set the serializers, Currently only one serializer is set as% X% z* W0 `# s$ G# B1 q
** transmitter and one serializer as receiver./ g* Y7 e$ X$ c5 h! e
*/% C5 l a, Y6 p+ r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# m J. e7 A& {$ `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 v+ O- B% X, c0 P8 D9 G5 u9 }** Configure the McASP pins
$ A5 H7 G x! v3 `** Input - Frame Sync, Clock and Serializer Rx; p* f9 o1 U. r! Q: m! L& Q7 ?
** Output - Serializer Tx is connected to the input of the codec
: H# a% Q. W# b" w*/" U/ E" ^7 U5 w( V" U) R( |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- F3 V; D" ?8 b) l v5 L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" v4 }) X7 N4 W/ B5 l/ _2 e2 f! H! R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- I) Z5 q b" g" \& U| MCASP_PIN_ACLKX
5 U5 v7 I, f/ o: X| MCASP_PIN_AHCLKX& v' L: Y2 h% ]; n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- R0 A9 {- e3 g Y# d4 ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + m N. }9 R3 B$ Y
| MCASP_TX_CLKFAIL . D* E. Q( c5 X5 D7 ^1 a+ ]2 {3 I
| MCASP_TX_SYNCERROR
# i t- r% Y* T0 g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ S- ^% c8 o( `| MCASP_RX_CLKFAIL
) j' X1 } H- ?7 ]4 j| MCASP_RX_SYNCERROR 1 `+ ]% l3 M0 a/ Z
| MCASP_RX_OVERRUN);, ]) r2 W7 }1 M2 K
} static void I2SDataTxRxActivate(void)
. H8 Y# U/ a t; R/ A# B{4 |+ e d% ~# U7 B( ]. N( ~
/* Start the clocks */
* ^ J( W0 M3 W' n5 _2 i7 jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& F/ K" P7 Y1 E) v) g+ H: TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% k; q, N: |; F8 Y$ ~( c/ d P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; s/ c0 N( A) }" |0 V
EDMA3_TRIG_MODE_EVENT);5 i8 a& }2 B, J* f$ L( u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, J! M5 m7 T8 H ~4 k2 _$ MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 [, w: q7 G. C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. ~* w, b2 p5 J3 w- P( O- D: U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" Z' J4 V3 X2 c8 U6 G. M- g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 e! A, D% C9 a) J$ Y6 a8 s! |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 l% f8 N* e6 r: u+ M5 O! v5 R; r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 c- d2 u. ]# }6 l/ N} # i3 L' D3 r" h b8 O0 f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 f) I8 c6 }3 Y9 W5 z$ O8 m3 Y
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