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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: m1 B4 u' y4 P- Y- oinput mcasp_ahclkx,
, M' t9 t+ `# v3 Y0 \; qinput mcasp_aclkx,
7 a, K. y" F6 W( B. t9 l3 [% _input axr0,
/ t* ?0 Z& F- D* t" d
7 y4 v! L+ d7 w4 Q7 ]output mcasp_afsr,
: K5 j* R1 W/ J0 h3 koutput mcasp_ahclkr,# I$ P0 I7 F( v7 T$ w( A& W' ^9 p
output mcasp_aclkr,
+ i" g. e9 ?" C& w& `$ joutput axr1,
1 {1 t4 u9 ^ |* a$ B% Y. ] assign mcasp_afsr = mcasp_afsx;6 Z' E0 X) y, j; X5 z0 I4 x: M
assign mcasp_aclkr = mcasp_aclkx;
) @7 `+ a) t! b/ j" P6 u7 B1 Z# xassign mcasp_ahclkr = mcasp_ahclkx;
. p& G5 B7 i/ f W, T6 g9 h* jassign axr1 = axr0;
5 F/ Z! m$ L: t0 |4 x
$ W4 Z2 p1 R! [) J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* O/ a; l" _) I& ?static void McASPI2SConfigure(void)
! o5 J. d7 j V$ P{8 Q' u3 t8 A/ ?/ ?1 x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: y' H* N" ?1 ^/ |& V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; b! d) ~! A; x. }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 H' u( @5 h; _* WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 F+ Q. k$ v0 c* ^8 V4 |' vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& y2 g1 a* K0 w$ l' |4 w& K+ m
MCASP_RX_MODE_DMA);9 }. b# [; E6 z( n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% q0 v. m% ^! i) Y+ m" C1 f6 c# G, yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: l- ]% i# I7 v" \/ i: V( q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 J" E" ? y1 }+ {9 B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( I1 X9 O* r. K. m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ `; v, I! V o1 T1 [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 m; H& x/ I4 _0 L, g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% ]) B! T5 w8 u+ m* T. Z6 q- ]; vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - B! q1 T! c% a% o, W* Y; n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 `/ V. H) T8 h5 s6 M0 n: ]5 g0 C
0x00, 0xFF); /* configure the clock for transmitter */
) L/ J# e1 ]4 w, r6 z. bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* e I. w: n' x7 F; G. mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 z' _$ }$ Q: \, r3 ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, L' W+ E" R% G& l$ n0x00, 0xFF);- Y3 d; Z' @+ Q& d/ K: o8 h
; W: d; i! M6 B4 F! M( M/* Enable synchronization of RX and TX sections */
; {% A2 v0 U- i S) H7 _* D6 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, I" l- r5 F* T4 [+ r1 M! i7 B5 h0 z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 k3 h2 d8 \5 Q! H4 f6 N& {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( n! t/ y6 s7 u2 ~** Set the serializers, Currently only one serializer is set as
5 m" w* F+ t/ p9 X( r! d** transmitter and one serializer as receiver./ O/ E- n! T+ r& r8 h9 z8 G
*/1 H; P7 m0 @4 R8 V5 P; T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) x5 s% q$ ]5 Q% ~; yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- U, Z, N1 |5 _& a/ R' {** Configure the McASP pins : |& T3 D! Y( }* S
** Input - Frame Sync, Clock and Serializer Rx
% |! P6 M" J$ W# ^" Y( c** Output - Serializer Tx is connected to the input of the codec 1 S% w/ T0 [+ S0 w! F
*/, E, y- `# A& C0 Z8 v' l. {. _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); C7 ~* P7 v" y5 n9 m. m5 [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, |2 f o- K5 t; L( T, O1 UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 N2 B; o g! N+ f- D* ^| MCASP_PIN_ACLKX" U3 u$ F0 f/ S8 }6 n0 A0 h: Z' B
| MCASP_PIN_AHCLKX, _8 G; n) t6 O( f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& R r1 O7 Y4 }) K* P2 S% UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! O2 J* v& D5 F' K; y9 W3 E
| MCASP_TX_CLKFAIL
- T; a+ P* b3 ?' a$ X/ W7 A2 ^| MCASP_TX_SYNCERROR' z) m5 K' L% a: s' a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" [- T! i2 D& ]6 z1 R1 Q| MCASP_RX_CLKFAIL- j" c1 q' W" M; i& {
| MCASP_RX_SYNCERROR 3 `* ?' D I. K# i& F0 H3 L# M7 F
| MCASP_RX_OVERRUN);) m% n1 t# H6 R3 M
} static void I2SDataTxRxActivate(void)
8 M: z4 X; Y; k3 i# q+ {' p6 B{
* f& }0 R9 V/ a1 C/* Start the clocks */9 c0 B% X: ] L& ?3 B0 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 i) Y0 L) ~9 P4 m5 C. f' m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 f4 O Z* U+ x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- x+ ^/ w4 M% a7 c/ T
EDMA3_TRIG_MODE_EVENT);5 Z2 N- T9 l' K9 k2 ?* |1 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: b$ v) i: T( VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 ]4 i' p0 m" [8 i5 ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' }% x( L* T, g! y- A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 r% k4 c" V- z6 d2 c: E ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* h1 l3 o: u! b0 w' O7 x7 a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; y$ R) C- R. T! hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) N% T" ]& K/ X2 o}
: o. Q* s7 F7 g& \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 |$ P2 b8 i0 h/ q( t& \# |
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