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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% E; A! i8 z- a) Binput mcasp_ahclkx,
$ z# M( t1 n0 e8 Q; yinput mcasp_aclkx,
2 ]% p/ U* _: p$ G( {6 Q0 n4 dinput axr0,8 Z4 ^3 N% }: P; I$ P
I$ W& n4 n0 c; C
output mcasp_afsr,% }2 C2 i1 B6 X4 C* |
output mcasp_ahclkr,
6 @; Q& P g" o$ p% z" Z# _output mcasp_aclkr,
3 {) n- m: V* @: ]( poutput axr1,
$ P. Z( T. r6 ^ assign mcasp_afsr = mcasp_afsx;
: Q- A. Z% o6 t2 h. Wassign mcasp_aclkr = mcasp_aclkx;
9 }0 F @5 F; ~8 Gassign mcasp_ahclkr = mcasp_ahclkx;
3 Q- P) q4 O# R% D3 C+ _. N$ Oassign axr1 = axr0; * x# t4 F% O' E4 c
. D7 T) U/ ]1 Y' E8 J" k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 i2 m2 ^ C0 j8 E" H% Nstatic void McASPI2SConfigure(void)2 F- x t/ Q( ~0 L1 h
{
4 P9 j# G5 S4 F; ?% t" ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 e" U9 i6 P5 G5 b3 H3 |, E2 nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* ^" [/ Z: B; UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); ^0 ^* ~; T6 L- }( V% i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* k3 d0 u- l3 a; R1 ?' i5 q, sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 W l$ L: _7 e! h
MCASP_RX_MODE_DMA);& G+ z1 J8 u) J( ?+ l& j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ o3 h! p; A* ~) X# I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 O" z1 D0 h, qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - D. T% W" {' {* K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 u& ?9 p# p# g9 o5 O: K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% u3 j; H* ?3 N7 @7 u8 U0 `; aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( m2 g7 n# x4 k1 T% lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 G5 V3 C, f% I# z' W, hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" V! Z" j6 F3 l7 |# HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# `3 G, Z* w! a0x00, 0xFF); /* configure the clock for transmitter */
7 W- U5 M9 k9 _& a$ L$ n0 V" WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- y- v# z0 z% X9 M; V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 n2 H0 C8 i x3 A. _3 F" D( d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& O _* S" B4 e: U! y s$ E2 X9 [
0x00, 0xFF);$ \1 F6 E4 f3 W, J
: p* p7 L* j' b j$ {- N& c3 W' }/ n
/* Enable synchronization of RX and TX sections */ ' ^: B" p# _# U+ x# A5 c8 y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 d0 }+ a+ ]- t; K1 H8 }4 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 W/ \! a& i. k, D" dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* X4 |6 z1 a! ?6 R
** Set the serializers, Currently only one serializer is set as
$ m; t6 |2 f* }0 A** transmitter and one serializer as receiver.6 h) ^9 q3 S. A% }: t
*/
' E4 N9 H0 H, Y: a) uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" q8 S# q' i6 G' D- Z! u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" O( \* V8 |* l, r/ B# _' `, i" ~& T
** Configure the McASP pins $ d& [8 B6 M! F3 D) ]. C! f: n
** Input - Frame Sync, Clock and Serializer Rx1 ~* F! s' D$ f* L- b+ L
** Output - Serializer Tx is connected to the input of the codec ) a2 Z6 Q; G: A1 {4 J$ b
*/# v' q* ?7 M; w9 j' q, Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 C2 @1 I2 x& j! @- ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; d1 x! h5 @$ V' r8 q: V) x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# x: B+ `) @2 m* v! J2 U K- d| MCASP_PIN_ACLKX+ r+ L% D3 L, M! L8 {4 n5 w
| MCASP_PIN_AHCLKX- L3 p& M" x$ }: S( Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
?; T- L- b9 s; H; b" R6 L; n2 b$ tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 n' S; T+ K* \" V& ^% s4 \| MCASP_TX_CLKFAIL
$ K9 X" j' f [3 L7 \4 o F% m| MCASP_TX_SYNCERROR0 |9 P' Z4 K0 o; A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : l" p9 v( E/ @$ v
| MCASP_RX_CLKFAIL- w& M% S+ ^' Z$ l- i
| MCASP_RX_SYNCERROR
! Q" z" z) r4 K1 D, C D/ V2 b$ V" w| MCASP_RX_OVERRUN);
$ s" W: A( w4 I8 d! V} static void I2SDataTxRxActivate(void)' s6 G' p6 z" t2 c
{
5 {, _2 X7 b+ K/* Start the clocks */6 D/ w1 _6 |8 V8 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, ~# q# Z" ]# [6 T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; U+ n& C9 ?$ c- X' T& nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," ?2 x' C) J5 x) X( J+ E4 y
EDMA3_TRIG_MODE_EVENT);
% l( c3 x: a: w0 D5 f& HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; z$ N0 J. k! b) ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 K2 y9 I) n2 ]$ D! D/ [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: B% Y6 j8 O- _ M) P$ h7 q% AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 U& T w+ b- B0 N) Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- O4 R! W% z) vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& W$ r% F, s. L' z, c% k( R- q% `& `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 P+ E4 \% |- ]4 {} ) b1 l( Y% Y, k* N- |) U3 R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 \! U' P) z' G" c: n# L) G, S
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