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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 P4 h5 f6 w3 X5 X4 i) i
input mcasp_ahclkx,
# A- c' g5 X. Q. ?4 hinput mcasp_aclkx,
" p9 F1 u2 u8 E" H1 @8 {5 Binput axr0,% o; w" h) Y4 Y
4 [/ f4 H- ~, ]4 F2 ]; Q, y; M1 x
output mcasp_afsr,& H4 c5 l9 }& w, k! w
output mcasp_ahclkr,. L$ ~$ I( v" @
output mcasp_aclkr,1 G9 l, j+ H" r4 o5 l6 a) }2 M
output axr1,
5 @! U! R" M% A8 _0 [* k assign mcasp_afsr = mcasp_afsx; X* h! x0 C$ k( w x: I1 R1 l7 K
assign mcasp_aclkr = mcasp_aclkx;
( a9 V8 e/ n" `) I& w, H3 E6 L; Y$ Passign mcasp_ahclkr = mcasp_ahclkx;: @5 P- B: z0 m6 {/ T
assign axr1 = axr0; 3 D$ ^- q/ }- {* ~' r- h
6 F& a b% {$ G$ b( R3 t* E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ j$ G. [2 Q" q- \1 Q5 Dstatic void McASPI2SConfigure(void)
$ u8 U O- K0 l+ Z{
5 S# W( c8 s6 [; P2 p+ ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 s5 m. [# E$ N* p+ @- [* BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% g( g3 G3 V4 v% @* W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 Y+ U* v3 @8 x/ `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 F1 [. k) M3 a8 E5 G) l) r# C5 ?5 e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# i0 n6 _3 Q" p. v. W& Z- ?% {
MCASP_RX_MODE_DMA);
! E4 i0 P5 d5 ^1 R% \8 tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ T& s, [- M3 n) D3 d/ MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 d3 E+ h. r( {* @& ]4 _& s( _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 s2 Y4 g) o( G+ l0 S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& G* H' d: f3 D O9 `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / P* H3 J; d! o( A) J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. N) E/ ?9 y; S1 ?( M# S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' ?9 c# b! b/ \6 u6 m4 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ \7 \$ N+ J% w0 f$ H/ @9 K7 [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" X2 h2 g R8 ]5 P9 V0x00, 0xFF); /* configure the clock for transmitter */4 h+ ?; I9 T5 T) p9 {+ I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! v' P+ w$ S3 [& e; ^. U% M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ _$ [, H. ^9 v; e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 G. N% \' H2 F, _# V
0x00, 0xFF);
! v7 `. C2 V+ P V
- \" m$ d. p* T+ d/ s, p# I0 ?, N/* Enable synchronization of RX and TX sections */
% w0 f2 C; _/ m2 R B6 }5 a+ H+ ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! }& P+ k( s; zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ p6 a1 x; s. G5 s( I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' y' Q, o& |0 p6 W4 Y
** Set the serializers, Currently only one serializer is set as
: H) J% H! @5 [** transmitter and one serializer as receiver.1 o( U; f& b3 P- _! Z0 h; p# g) X
*/' X2 D7 ^9 H# d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 t& J0 c" W4 j% Q" m# tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ |, @' R+ v2 h) Y- M** Configure the McASP pins
9 M7 o+ B+ |5 [+ z** Input - Frame Sync, Clock and Serializer Rx
/ S1 q% q* d7 K2 W. j** Output - Serializer Tx is connected to the input of the codec 9 z4 q3 a: M1 U/ g0 ~- N7 k
*/$ }. F p% w1 W8 u B. V8 w2 [/ k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 r+ j# K/ S% B+ s* i0 I" L. z0 RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 ]0 F1 H/ c# p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- ~3 _1 T8 N, W# b, e
| MCASP_PIN_ACLKX+ Z, A# ]! n v0 g. u s$ |- d
| MCASP_PIN_AHCLKX9 u2 v, [/ q, n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) F& B1 I( L y" h4 OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . F2 l1 v. Z* ?: l7 L9 T
| MCASP_TX_CLKFAIL
, g( [0 j# e8 c, u9 r( Y& F| MCASP_TX_SYNCERROR
/ ^9 Y* Y5 c6 p1 b8 X Z. Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 C- k7 |( _4 ?0 \( a( r, D6 q| MCASP_RX_CLKFAIL
( B; |; Y" z# Z; m+ E| MCASP_RX_SYNCERROR ) ?3 B* z9 c) B" }# R5 H" o$ M
| MCASP_RX_OVERRUN);
# z: e' {; v" n* m8 o7 t: b+ O} static void I2SDataTxRxActivate(void)8 G! n: F, {; p: _
{( q1 e! k3 x5 Y R% l) f
/* Start the clocks */
+ G8 w o5 Q. K0 E% |) X- s1 oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); D" z/ z: w! u* I1 x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( ~; h9 ]- F9 B0 h5 q/ EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ f$ G( ?: z$ a& b' e
EDMA3_TRIG_MODE_EVENT);2 F0 ^: w* H3 V" v) u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 j; D3 ?* M" i3 p) fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: e- g( p# c6 q- Q7 h6 b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! P- I0 T2 P) Z/ aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( g4 C4 C$ U) n& n* {1 D, _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 I2 V7 Y1 @, R6 S- M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& ^5 q* d, o: HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 {- n! k2 Z( T# S
} : _6 P! d0 I' b3 s T% L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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