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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 R r" |4 @6 {% f+ Oinput mcasp_ahclkx,2 |& y7 L( A% `( K
input mcasp_aclkx,
; E, U0 `. R: M e O' x/ O' einput axr0,
( ]5 @. k/ k* Y! y: Y8 x
5 D0 R2 k8 t' \0 r4 R$ z' ~output mcasp_afsr,
( X4 @: C" n" p, D5 Woutput mcasp_ahclkr," Y! g' g% g3 X0 a; x
output mcasp_aclkr,
9 Z6 O/ v' k: Q5 o+ b" ~4 goutput axr1,
+ Q4 N$ `2 U0 F* D assign mcasp_afsr = mcasp_afsx;) R4 `3 m# H5 T0 b9 ~6 \
assign mcasp_aclkr = mcasp_aclkx;1 e7 g% k0 x* A9 Q, m" n" ~! v" Z# o
assign mcasp_ahclkr = mcasp_ahclkx;
X1 Q# s( U; k1 n5 q: Aassign axr1 = axr0; . N% b2 N$ p* n: T8 _3 O
/ h5 D9 l; w2 q/ O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: a+ q& N8 l2 Rstatic void McASPI2SConfigure(void)
% A0 P: @8 \0 s+ L- b: t J6 R{
. g) R8 Q5 B) x& v7 o S+ x, S: wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ m: o; B" y& ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ U) w) O. g! v, j! V3 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; Z6 {0 C$ V# I: ~* W" @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; Q7 b# I& @- \0 q0 M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: F( R" l( d8 G5 i# ?
MCASP_RX_MODE_DMA);4 S& u# V2 u* p# @$ q6 u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- |+ c" t9 t5 @$ |6 M( e# A9 GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 u9 F |0 T+ FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 ^+ f( o$ t; m2 P, I+ X; lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 q* }& W# k; b$ ?" j8 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % P* u; c2 H! A( n& b2 ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 q3 q+ C* c9 f: a2 {. ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ ^* M# f( c RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' A5 B/ L1 N) N9 W1 FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 h6 E e% D) B5 E' I, d" }$ h4 S0x00, 0xFF); /* configure the clock for transmitter */
( L9 i+ i$ g9 JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 k$ [. j; s) l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) B, {8 V! v& Z; C6 d$ s5 fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# ?7 \5 T$ V( g
0x00, 0xFF);+ x) d: v9 c6 Z6 h5 K
$ `+ T" g& l& W! v6 Y9 B. T: g/* Enable synchronization of RX and TX sections */
3 u6 }6 k* r& f: Q9 w/ j( X& OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- a' e: g3 X, @0 JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 Y( M0 k% y4 N# ^5 JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) U$ K3 J" A: v
** Set the serializers, Currently only one serializer is set as
% l. x) b( z, ^; N+ P1 M** transmitter and one serializer as receiver.4 ~4 U# o+ H0 G/ p3 D: P
*/9 Q; k. e/ a! c$ c0 L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( B# b" O$ y; G% y$ K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 b" G, S4 f, U: T: v* m! H5 S
** Configure the McASP pins
* H2 d& I' K% `* T** Input - Frame Sync, Clock and Serializer Rx/ t B6 p5 W S: q
** Output - Serializer Tx is connected to the input of the codec 7 z- }' E9 ?9 u4 @
*/
6 D, k- O5 ~1 o8 U: N" e% HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 `4 z9 Z/ ]7 G# T( LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ Q3 ]0 s9 c# e$ J8 A4 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 f& s8 w/ v) E% X# E9 l6 p| MCASP_PIN_ACLKX' L, n) T& g# H% ]- r8 f2 n
| MCASP_PIN_AHCLKX* _3 [) |+ c# r# k. e, [; l+ x% h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 b$ h+ c$ G& l# @: i1 [2 X( D: dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 @# S. H* m2 I2 a/ m* p| MCASP_TX_CLKFAIL 2 z# z% N* G' E Z
| MCASP_TX_SYNCERROR" v* a5 z# g% ^( K/ D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 G* L" R3 p6 R| MCASP_RX_CLKFAIL
! j* i/ ^% t, B4 H2 [6 ?| MCASP_RX_SYNCERROR # w" F( f' d% T; f' z4 }
| MCASP_RX_OVERRUN);
_- I6 k$ D! Y3 U} static void I2SDataTxRxActivate(void)
[ S' b4 [8 L6 n( J v{8 \* O: V, E3 _- f- E4 ]$ O
/* Start the clocks */2 |) ?& p# v" }& y) Z" o! Y& P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ T6 v D& P9 _ o4 l, RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" h1 s( e6 J4 s5 y) y" }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 u5 Y* N, D3 _4 ^4 h; ]
EDMA3_TRIG_MODE_EVENT);
' ^" O, G1 K4 g1 K5 i$ O, zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + z0 ?$ E- F7 q/ T/ B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" N$ ]5 i8 |+ [5 T+ p6 T. y; t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 {% X; r4 M. p1 fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ M# j5 J l( a. ]9 T& c* V, N/ ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& z& R+ s8 e3 {9 o4 C) U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# _% U( c& |* L# U% E7 X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 M# K2 v2 a [% n} , Q, E) }2 ^. _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . H5 v6 d$ `' _# v% B. O: T9 q
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