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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- t( N3 @0 Z! d+ O% z; Q
input mcasp_ahclkx,/ {2 `7 K/ Q7 H% c+ l2 `
input mcasp_aclkx,
* X$ C" X9 L5 V2 ]$ l- C4 Qinput axr0,
- {$ c( ?( I, x1 u' O8 [) C+ [
1 {9 {' ]6 G6 W* @4 g. ioutput mcasp_afsr,
2 T% g# ?$ |- B2 W# Z% Xoutput mcasp_ahclkr,
# K- A4 t6 s |3 B0 h5 p, joutput mcasp_aclkr,/ X6 ~6 D; i+ [6 a6 b, v2 P' a5 T
output axr1,
: r1 |1 \- [5 P9 L8 l assign mcasp_afsr = mcasp_afsx;6 F, }- p* U# u# i! [1 U
assign mcasp_aclkr = mcasp_aclkx;
9 g6 V5 s8 e7 u4 |assign mcasp_ahclkr = mcasp_ahclkx;
0 p, W6 B( b6 j2 Z& M' Q3 Xassign axr1 = axr0;
/ Z8 f* S8 E$ U: w! r1 i
' O9 A. c3 ?8 i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 h' c3 v3 X. V
static void McASPI2SConfigure(void)3 [. B( V0 `1 w, x
{" Z9 x7 Q( b8 Q3 f6 b. u- o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 C9 @. u/ A( p6 P3 SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# v2 s7 ^ j/ `, k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% U7 x( S7 z( r: T* ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! O9 f6 v; `. s8 u# _ j0 @' mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 {0 m5 M' o1 o/ u* h& b0 n7 E1 b* n
MCASP_RX_MODE_DMA);
" }6 }, s" v1 x; v% w' GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 L/ M C' u1 G5 W* AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 V; S2 ~& c3 k2 s: V) _5 v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 Q$ E5 A+ A8 FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ }' h) K2 \3 b! eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! B1 O5 A- T- z0 n: r4 P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& l4 z$ p R; o& r2 P) @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; [) }. M3 R% [+ xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& Z* ?# ^! m, m5 UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, @# f) a. N" R- F7 [& s
0x00, 0xFF); /* configure the clock for transmitter */2 d. _ i0 a3 V. l# o- a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; a3 r3 z' y" ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . L# o; n" i! P5 C: L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, v" W2 F- W( J( [+ ?/ L0x00, 0xFF);
: ]$ c, u; N/ T0 p; C H( ?2 k! T2 {! s; c7 c. {5 v
/* Enable synchronization of RX and TX sections */ $ R9 d) [- T6 ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% a8 x: ^% ]% U, T9 p1 Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# q/ v5 s8 V5 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ T* M, ~" j" V1 j** Set the serializers, Currently only one serializer is set as: j2 Z: \3 }6 H/ p* y1 O; M
** transmitter and one serializer as receiver.
5 g' ~ |, T% B( R% ]# l ^*/, A, x' b. `* q" A8 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 ]$ p D, d6 b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# ^& n8 n G* ^+ [9 j2 B; ~
** Configure the McASP pins / X+ o/ K4 d5 |# L) B
** Input - Frame Sync, Clock and Serializer Rx; y" K6 V' Y4 F+ U# H
** Output - Serializer Tx is connected to the input of the codec ) R8 A8 t4 H$ w. U d
*/
8 P8 ~) A! ^9 UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& K' w8 ~1 n( U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 z! L7 E2 ^3 K _ \7 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 k7 i3 H: w- E1 _0 _
| MCASP_PIN_ACLKX. U* i! N7 C- `4 \! M* d
| MCASP_PIN_AHCLKX
2 \3 h b& d% ], {# H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 }; C3 d5 T6 r' YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% a7 T: P9 c& T| MCASP_TX_CLKFAIL , v, m5 |- P+ G. |5 E" K
| MCASP_TX_SYNCERROR' t, D6 g' P0 ^9 K, W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. S- A$ `& E) z# Y| MCASP_RX_CLKFAIL( M v( @$ J/ x) @) A
| MCASP_RX_SYNCERROR ! d' Q4 q5 t G5 |9 h
| MCASP_RX_OVERRUN);
# p5 h. T& r- g} static void I2SDataTxRxActivate(void): I+ P) c3 Z" x: X
{% r4 E# @: p. `
/* Start the clocks */
! W9 ^* C* t) r/ pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 T! \* |' l: M6 ^2 e |7 L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ b( d: @- T Q3 u: \3 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 r- p. x9 d) m4 W) i5 S
EDMA3_TRIG_MODE_EVENT);
' x( |3 x& s* IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ c! H" Z# T/ u4 `# mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ q+ z: x0 ~+ R' j2 i0 J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) I4 ]# z: W- F$ i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: \2 P+ b/ N" b5 M& \, s! K3 `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# J5 ~) G% m* bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 I6 X0 ~, v3 \+ JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: o7 h$ f' R1 w- d5 Q: x# \" Y}
2 ?/ l- h) ~, f% L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' @* U$ q: |2 f7 B/ k) i/ n
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