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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," s* S7 l' G8 e' j( K* R
input mcasp_ahclkx,; R- t2 z4 q! p% \$ ~7 K$ B( M+ F) \
input mcasp_aclkx,, X* Q, c9 p4 A& o- P" l
input axr0,9 d: {9 A& X! Y8 S! }+ Z9 K4 R
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output mcasp_afsr,
) r# p% z" N+ l1 T% S$ doutput mcasp_ahclkr,0 z! o0 ^4 j h2 f
output mcasp_aclkr,3 Q; B$ B; e9 E. {; a
output axr1,
" S }, v+ e+ Q assign mcasp_afsr = mcasp_afsx;
" l6 U1 \% J8 q* U& zassign mcasp_aclkr = mcasp_aclkx;* f) X9 j8 J: y! ]9 _. t: x/ o
assign mcasp_ahclkr = mcasp_ahclkx;1 O3 s' M, {- N' P, |
assign axr1 = axr0;
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7 k* l! g: Z/ d4 z: |* r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 D7 R$ i5 h \, f, Sstatic void McASPI2SConfigure(void)
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/ {4 Y7 @* C" ?4 Y1 R: P# XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! j8 q6 w! I2 h( k, E- I' d+ pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 g9 A1 w1 z2 h' r4 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# `, A: X; P' [" J; |( J7 R8 [( XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 F+ }9 R4 B; p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: V$ d/ A1 J" w! S5 zMCASP_RX_MODE_DMA);* b. z; ~+ ~9 T" t1 k+ t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* n4 u8 P! C2 x4 j( |% z0 V% K: m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! U. ?; _: T7 v/ v! Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% H) c+ z/ c- fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; E8 ]4 S3 ^8 Y7 f3 i! k. j3 j& DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 s8 s- I ^. x4 \( @3 U2 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
s* H6 U* ?2 N1 A) I3 x6 _ hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. u8 N; X4 V4 s: y1 R1 e0 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# E1 e- M( O& D7 ^! ^4 v" X _& Z2 dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," f6 c* w/ e/ f
0x00, 0xFF); /* configure the clock for transmitter */
3 t6 M; r( N6 [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ n; y; @$ J& S$ R6 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 f* M' E0 O, i; U+ I- {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 a; ]" a* p0 @8 g7 M
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ 5 ~+ x2 h2 P% C s6 w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. R5 ?* v- ^: |6 [) y/ V! A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 [* N+ B. j) }% Y" O4 Z* M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ O( P* Q4 D3 l/ ~( e** Set the serializers, Currently only one serializer is set as
' @3 s5 ?9 U2 ^" f' `; E** transmitter and one serializer as receiver.& z8 u3 g5 U0 F6 l# O2 _* E
*/
6 i5 S @& P o3 e/ a; u lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ x/ t( _( l; }; J/ z1 @5 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% M! p4 z, Z" v8 K( E* K. F- W9 ?
** Configure the McASP pins 3 E* a) Q7 S3 q( @0 Y! s
** Input - Frame Sync, Clock and Serializer Rx
* y2 G4 Y5 y0 _3 K7 F- w _** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 n& ~( T& z% q6 S5 s: e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 a7 d9 M+ j6 E/ ?0 KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& O/ Z- D3 v9 s6 {
| MCASP_PIN_ACLKX& O8 W- q7 h' }: Z
| MCASP_PIN_AHCLKX- O( t( P# V9 {5 e" z8 ]. p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 _/ V8 A1 v( h# b" t: W- f0 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 e, w' v6 h9 ?5 \2 ^6 I X/ S
| MCASP_TX_CLKFAIL 2 }& b' I& o! N" i
| MCASP_TX_SYNCERROR1 \! ~5 Z& X$ B& H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# b( u) |0 i' p6 ?| MCASP_RX_CLKFAIL
6 Z+ F/ J$ x" a9 A* a) H| MCASP_RX_SYNCERROR ( u6 M* v7 |+ M1 G- P8 z- e4 f
| MCASP_RX_OVERRUN);
" ^$ x5 U0 w: M* [2 k} static void I2SDataTxRxActivate(void)
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/* Start the clocks */) f7 V& I1 |& v9 h- F6 I: a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) w5 S. u9 |2 T5 y8 S* M0 b, `) VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. s$ D/ W$ W. O Z% Z9 e6 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 {9 W6 u* Q' n! P, }
EDMA3_TRIG_MODE_EVENT);' S7 y1 Q% C7 @9 d& d$ n1 e3 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : h4 f0 z& a, O/ ^9 y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ X9 J) Y6 {1 P: rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! m* V( Z9 \5 L# p# ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- k! ?5 g0 f5 Z( ]; s+ }9 L) L* ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: U+ c6 j! m2 Q. _+ n% T2 d' I" e @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
D$ V; e& x% ~. ^ W, XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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& @4 k; Z' K j U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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