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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
e! x6 d; W0 V* `2 Ginput mcasp_ahclkx,* v* \3 T) I! E3 r6 G; \& N
input mcasp_aclkx,
+ U( ^) i5 C% l/ `1 ^input axr0,
" r/ [$ C7 ?# b. b0 u, Z# ^) R& ]1 [+ b+ C
output mcasp_afsr,, n8 K- D8 A4 ?
output mcasp_ahclkr,, R, ?. P2 Z# ~8 ~ T7 m; `. G' q
output mcasp_aclkr,3 Q4 P; N% z% H; K3 H1 R7 i% B
output axr1,
% o% B. t9 R% Y. n: [ assign mcasp_afsr = mcasp_afsx;
, @2 k/ Q& u6 V9 k fassign mcasp_aclkr = mcasp_aclkx;
]! D6 h8 i9 b/ o) {6 Kassign mcasp_ahclkr = mcasp_ahclkx;
0 @, P1 t% t7 ~( a* e: `assign axr1 = axr0;
' h5 }8 Y' C1 l2 C* Q* p# ?. r$ _. }8 s1 B- Q( q9 t& [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ j" n7 v8 `, i; y8 Jstatic void McASPI2SConfigure(void)' C5 w/ |5 j7 u6 z8 V) e; G
{
/ s& g- e3 W/ D' W- T7 JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ |3 d: }9 m' f# TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 \& n, \9 G/ t" M& \) y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 v5 v( C2 y. e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 c+ x; y$ x7 {( I) T3 O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ l2 k- P) u Z0 J3 D g$ K
MCASP_RX_MODE_DMA);
0 ]& g3 @- L7 |# @, f+ O2 S; W! QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 I: U" M! f9 @4 Q; z/ LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" _. ~8 N4 s& v7 A& x8 aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& J# t! V( p6 G, p+ xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) U4 C- [$ x$ k( Z1 \! Y( d7 v2 SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
l* U( F( A8 K) t9 _$ wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: T3 A' O4 N' t+ ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* c; ~$ k: {' J! C MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 M% ]9 J }- W P; ~1 U) a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( M3 E* e) y8 M8 l' ?0x00, 0xFF); /* configure the clock for transmitter */
- R. A+ x9 W7 {! ?. f( cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); w2 x' h9 J9 {3 Q. z. k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" W& Q- @' d! R" `2 j5 _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( r8 I g( c9 Z: n. s9 e7 K0x00, 0xFF);
a/ V+ j0 W' o/ ^% s
9 `; n( e# G6 q# T# U/ d, o# R/* Enable synchronization of RX and TX sections */ x6 ~: N% c/ A! l3 `2 o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! c6 c8 _1 B' s6 i6 K+ B5 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 z# t' e0 L a4 o/ j$ SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- @" d& F2 a- C9 D+ K
** Set the serializers, Currently only one serializer is set as2 A% q; w$ k! |$ p, z: F8 L
** transmitter and one serializer as receiver.
3 D- K4 C# E5 \9 w* U- U# K*/
+ L" t% e- I* C( f6 P# C( SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& G: k& F/ R2 _& N; R0 U% H8 H( q1 sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ d( J# L2 h6 T( ^ [# r0 a' i8 {7 S
** Configure the McASP pins % ` L! A% {; L8 W7 j/ N3 `
** Input - Frame Sync, Clock and Serializer Rx$ ^# O8 @' {4 ^* }3 L
** Output - Serializer Tx is connected to the input of the codec 4 {2 ~& R2 S( I
*/. A, {8 Q/ C+ x# r; F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& s3 t$ k. ^* m& XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% J+ R" d* ~: V& W% t$ gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 ]* X# g2 Y* Z6 o0 |" d ?8 ~. ?
| MCASP_PIN_ACLKX8 Y% F! k1 Y) o* Y) i
| MCASP_PIN_AHCLKX% J7 L( A2 b4 _" Y! x$ F9 |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 F" }2 |0 X7 i& s% R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 ]& r; p4 v2 `* c$ w| MCASP_TX_CLKFAIL . k* M7 W# q4 O. C" @& _3 ~& {
| MCASP_TX_SYNCERROR6 h, M' u9 F) j# T& y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: r6 _+ b- j, N J7 @8 \| MCASP_RX_CLKFAIL# Y. H3 p5 |$ f+ n% h Q( r% ~" h
| MCASP_RX_SYNCERROR " e) E) h# P' b! U
| MCASP_RX_OVERRUN);' E, U! O' i+ w% x" F' V% V, v
} static void I2SDataTxRxActivate(void)2 G/ y* O$ l0 k1 C+ ? X) }' f( U) ~
{
& L: ] T3 P5 T/* Start the clocks */+ _ m0 ]* V& [, K4 w5 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! W6 [0 W2 T' d3 O, ^1 q7 y3 a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 z8 _& q: o8 ?$ x: p6 O3 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ W" F9 c% w2 ^5 |EDMA3_TRIG_MODE_EVENT);, P- y P% f$ R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 V) K2 [4 b6 r: Z8 X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 Q/ z+ A9 k* b5 F3 W9 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 j- c9 U$ Y6 [/ K# [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( A( d) m* f& y$ Z6 Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% ~/ u6 z- l6 b2 v( u, DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" i B4 M$ e4 e" f6 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: t9 o6 Q2 {$ E' Y8 A1 \}
/ p) X% m' A6 ^6 F) I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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