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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 L* t) e* n4 N4 F$ D) X: n0 n
input mcasp_ahclkx,
! f% X3 K5 w' v1 h( Oinput mcasp_aclkx,2 Y( e. m$ f$ @9 `$ t
input axr0,* C, [0 h7 ^+ n/ H3 n7 v' g
0 h7 o! z0 E3 ooutput mcasp_afsr,
! v3 ^+ c8 Y' @2 o0 Qoutput mcasp_ahclkr,
& z" O0 A$ y: j5 Z2 l) goutput mcasp_aclkr,
* N# z: n- |/ l( M7 L5 ioutput axr1,
8 z+ p2 o) `2 l3 Z, h1 G* z3 [/ \ assign mcasp_afsr = mcasp_afsx;
6 F( H6 O! E% X$ P* P# b. d& M7 oassign mcasp_aclkr = mcasp_aclkx;) f9 D B; r3 W/ p+ y2 ]1 b$ S; b
assign mcasp_ahclkr = mcasp_ahclkx;
1 y" \: N. C" G1 b. Rassign axr1 = axr0; 0 ~( y( O z9 S( v; h Q) R' h5 Y
% Y& f5 C4 ` a) E+ p) I9 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - f/ V& [ {7 m& }0 D6 h
static void McASPI2SConfigure(void)
, Q9 v' h8 b- B, `& {{
% f5 G# y! Y1 m$ x; lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' e, q# ~0 b& k5 t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# ]8 w; \! o+ X! V, H: c1 zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, V+ v. Q8 ?) z" T. c( v) \* q" ~0 hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( w8 n$ @. z. H: p. n5 _6 J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( m" `: l8 W. l% mMCASP_RX_MODE_DMA);6 I/ w: R; H9 X( K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& z6 U- H' `- e7 G; R$ GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 t7 y" \0 F" u4 S7 _& r [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; [& h8 D9 L9 H, C. ~3 `6 B! BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- ], Z* ~" N& ~( [4 `1 nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 U+ p- R2 v: h* Y! P c, l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 F; V3 |, m5 ?) |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& t' I7 g- v) @9 I4 W+ FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 z d* i1 i7 ^# r5 I6 y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) g0 q& R! r; e }$ A7 p
0x00, 0xFF); /* configure the clock for transmitter */
8 O4 h! U* r# E7 L# c1 LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 B% o! }9 U* G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , _4 n5 ^$ L; B( ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 n* y r4 o/ x3 I9 X+ N/ b) ^2 C
0x00, 0xFF);
6 y( h2 V5 b* ^" r' l: o# q" C7 h* ?9 t+ p$ C: I5 t' D+ a
/* Enable synchronization of RX and TX sections */
& b$ [6 b! M$ K0 m# HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, ?( ?* t; F! ^ |! L6 I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! ~7 g) b3 {$ O1 O% v1 eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ c* ~9 t% f' G0 S- Z1 |. s
** Set the serializers, Currently only one serializer is set as
. ~$ |, p$ v3 w6 {- K/ Z" Z; P' h U** transmitter and one serializer as receiver.
7 ]/ P& r5 i3 c; e8 {6 P& H" C5 F*/- C) c0 k' j& f- v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# u' p0 T. \3 Y# D0 Z4 E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 @7 p" o) ?0 z% e0 D5 I/ _** Configure the McASP pins
+ @& Y# f" A* E& W3 x3 g8 f** Input - Frame Sync, Clock and Serializer Rx. M6 {9 z- _3 @
** Output - Serializer Tx is connected to the input of the codec # }' X, I- h; B% G
*/' I$ Q. P+ K! z; K* @% Z& i) W- m& G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 R9 W: s! }* P& k* Z% S. U+ p0 kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. T C$ x$ ?+ p7 h6 I; Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ Y v% s" s; L3 o3 O* P| MCASP_PIN_ACLKX
0 w) d: K/ V3 O/ y0 a! e| MCASP_PIN_AHCLKX3 Q; [, o2 t' Z* B' w% f. G0 a d- ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 W$ R1 t: }; U R8 t$ `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ C6 z H! p9 b; b- c N& C9 y| MCASP_TX_CLKFAIL
) ]& B/ I0 V3 V& X7 ]. W. Y5 M| MCASP_TX_SYNCERROR
1 ] X/ Z" s8 @/ e: ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; }% d$ f8 D$ U; N T9 e& ?. d- d| MCASP_RX_CLKFAIL
% R$ {& D3 w# p) r8 I7 T| MCASP_RX_SYNCERROR 7 K* D% o! b9 `: T- _% e% ^" v
| MCASP_RX_OVERRUN);% f- y7 R, W( q j8 d4 ]
} static void I2SDataTxRxActivate(void)
8 S1 v* J* \: ^" ?- f5 _{
5 `1 I0 h" I+ b% n' I. ~9 O/* Start the clocks */
% E0 C0 R/ _2 O, R; V( V/ A# |( AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- K1 y* F( y% \# q; v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- Y: X u" p0 H o$ ~% {3 d; `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) \% U; y, k$ Q: i
EDMA3_TRIG_MODE_EVENT);7 ?/ n" K* Q+ e0 G* m* \2 P1 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& E( e8 x0 f% e& rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: H8 I0 ?0 `4 [0 t. XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 k; b% {# X2 H$ S$ xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- j F' m: c; jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( j$ q4 \1 u& Q+ V. Q/ ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- e* j1 s* O+ |0 j4 W* E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ u4 l2 C& e; U( ^# w8 i} 6 B3 H. E3 a6 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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