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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- m$ Y1 y( W* h8 L" V. D8 n
input mcasp_ahclkx,3 j( Z/ I) x- O/ e- x$ Z& S
input mcasp_aclkx,
* I* o% y( C, R/ o, j7 S4 Finput axr0,
/ S0 h" B! E$ H/ [: E
0 U, b3 n3 S) l/ t5 a2 {output mcasp_afsr,$ ?" }; p. ]" O
output mcasp_ahclkr,
) ^# [4 h# ^5 Routput mcasp_aclkr,
2 l9 s; z& `5 Q0 C. y" boutput axr1,
0 n; v: F. g. Z. d assign mcasp_afsr = mcasp_afsx;
$ O2 G2 r2 ^0 w H# eassign mcasp_aclkr = mcasp_aclkx;
9 s: e" ?: t. u9 y; i+ E& }assign mcasp_ahclkr = mcasp_ahclkx;
) s6 D, @# x E% O8 b3 Passign axr1 = axr0; $ i9 s8 l8 l8 |& [. }
3 p: s. X4 P/ v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 K( o7 X% M# u3 ~& ~* V: sstatic void McASPI2SConfigure(void). H9 z- P4 @3 @! {$ b1 g; ]: b* P
{
?" w9 s* C U1 n* DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* R3 p$ d! i" U3 X8 Q# c+ V7 X( KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: ?2 e0 V) x6 A( d, U2 k X% l8 z5 a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! D% U: \3 k7 c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 h: y! d4 l5 yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 ^1 Y# _/ ?3 D4 S% ^
MCASP_RX_MODE_DMA);) Z' P d' y4 p. d V7 e0 C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 d3 t+ l1 Q) B) S, X: Y" bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* l; c ^8 }& D! kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( Q S. P* p B4 V( I- Q; h! eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 E) `$ \- g& b: M5 g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 [1 D, ~7 L' K- W+ q+ o( k y* ?; U4 z, P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! A; @2 A j3 _* U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 ~* x* I" S5 g0 U+ Y- KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , F' J5 y8 v* E' M9 b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ F$ b* B" U4 E8 A* J) Q4 j" N0x00, 0xFF); /* configure the clock for transmitter */$ Z; O, n# K3 O7 G. |% v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 p4 i7 r, V3 o uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 u8 w$ G+ F- y8 u+ c1 h( P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! b$ k0 W) J r0x00, 0xFF);* v# D) Q! O7 r- V e) C( e
4 `. P( [7 O; t- i! p( }/* Enable synchronization of RX and TX sections */ 3 U2 Z" q- I, u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! L9 p5 K4 K3 X) i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( u/ I3 j# |! h7 s, g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 u5 ?. t+ v+ k) X** Set the serializers, Currently only one serializer is set as/ c: h3 Y4 ]5 j: W# U) [6 `8 X
** transmitter and one serializer as receiver.
' @: f% @9 s' A* G! e*/
2 M' f/ d' k( n7 d7 j1 J' T0 EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 Y5 x& ^ m% X; u+ w$ k# a o7 sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; M9 f, n8 V$ F1 K% T! |1 c* V) D
** Configure the McASP pins + a: d. P" v2 s v& T
** Input - Frame Sync, Clock and Serializer Rx
! J& p8 |. V7 q$ H1 k** Output - Serializer Tx is connected to the input of the codec
! H! u' X l) a0 g" X*/
9 Q: h* n, V! B7 `# Q0 e( Y4 _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 i% i8 o- b& F5 G$ y5 M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- T9 H; I5 B$ `' U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 |: r: q& K. R& n- I7 G
| MCASP_PIN_ACLKX
$ }- w2 \0 Y0 f$ ^& V% W| MCASP_PIN_AHCLKX
6 l6 k0 k0 Z) y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 v& l) Y1 Y( d3 rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / E7 Y! A) T |; B4 L
| MCASP_TX_CLKFAIL
8 M: F0 A0 A1 T. v* c0 w| MCASP_TX_SYNCERROR
/ }& p6 l0 R4 H, b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% K0 j7 _8 }* t6 t# J& I| MCASP_RX_CLKFAIL/ o o) T( z6 C3 {) c
| MCASP_RX_SYNCERROR
/ G/ y8 C& b X# ?/ \ L/ Q| MCASP_RX_OVERRUN); e6 m+ S% a8 f) B' A8 j
} static void I2SDataTxRxActivate(void)
) j0 r: Z+ h+ _& O- h/ S{6 \ M0 X3 ? |
/* Start the clocks */
4 ^3 ~! k/ k1 l* I- r; k2 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# x5 V; J9 K+ K# g; c& h# n4 VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( I3 H4 y9 ^% N/ J( K& k5 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ i. u8 r0 S! S9 L+ W: k9 y
EDMA3_TRIG_MODE_EVENT);: A" r: N# C3 P/ U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 z7 J6 g% ~9 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, R* D( N6 h. K8 c% JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. c2 ]: M1 Y0 a/ ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 H( m. E; x1 \' C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, v1 M0 s V3 x; C- H& o/ F( W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); |2 c& ?0 v, P, [. `! n/ r2 w0 g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! a/ x# m& l5 \3 b) u& }} - _: ?* {/ R; R( b2 P- Y5 i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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