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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 Z" S5 x0 Y' f
input mcasp_ahclkx,
% l4 _7 N, h! L! D* @& C* rinput mcasp_aclkx,: Z5 K1 W+ f/ u( o; L8 { G7 Y7 ~+ w
input axr0,; \# p- a' }, x% C9 C
) c3 C6 \0 x9 Y. [7 ], @* q1 [) @output mcasp_afsr,
1 `8 P* J$ \9 q( Y" T h7 o" q6 Poutput mcasp_ahclkr,
3 D& f5 V$ N* y ?output mcasp_aclkr,7 Z, Z6 ^! I" C, Z1 o/ y z
output axr1,
2 b8 A3 w" y9 a! ?( z" P assign mcasp_afsr = mcasp_afsx;
4 ?# Q/ w% ^, _assign mcasp_aclkr = mcasp_aclkx;3 l) f, E t+ M/ v! v
assign mcasp_ahclkr = mcasp_ahclkx;3 f, G) D2 i. {' `3 M9 Q8 [ Y
assign axr1 = axr0; : H! d# ^' W, \
9 R- E: j7 U( U% K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 ?/ j4 H2 L! R ]static void McASPI2SConfigure(void): Z1 [) Z) @ B' ?& B9 b
{
3 n2 n' O2 v+ L+ Z$ s+ iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# Y7 D& P. o) ~1 g/ t, t- UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// D+ J2 I+ n0 D7 u' O; D$ }8 ~4 a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; {8 Q3 f4 R7 B1 L- k* FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; y3 ~) O% I) y+ B4 rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, g2 |0 T( R: v1 C& ?5 H
MCASP_RX_MODE_DMA);% ^+ C2 p, n0 [, c$ e$ C, j5 L3 J; ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, s) i# o F5 R+ O) }, A* |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 x$ ?0 O+ X! n7 e- k3 iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 _ T0 d+ Z7 i, e0 |) S; f- S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 H' l/ A- X9 p5 W5 @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. z+ \ v2 d! q. ^1 X3 l+ XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 X. D9 x% I9 L1 `5 L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, x Y) S; X$ e( J4 S& k4 Z/ `- HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 R0 P) Z6 X8 CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 r( d1 `% J" D- F: t: h
0x00, 0xFF); /* configure the clock for transmitter */
) L9 l! O7 m- a( d1 b- e$ |, NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 J& Y/ R# I: B5 a$ vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 Q' x% B; s# F3 h9 ]; A7 x, }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 \! h, N! ?, O) }$ ]
0x00, 0xFF);0 ?5 E; V S# z: O8 r/ a
$ |% s4 o- r% r8 f0 {$ d/* Enable synchronization of RX and TX sections */
1 T' B4 o0 @/ @0 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: z2 w+ |( C& w# D9 ^9 L( X# ]9 q; KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- Y3 E+ x. }( o6 Y! v1 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( s8 q5 K" r2 j! R9 R
** Set the serializers, Currently only one serializer is set as
! `' P& u5 m, b5 H" c+ N, P1 d** transmitter and one serializer as receiver.6 o! p, M+ X: y* \' l0 J
*/3 u, Z' q* q2 G/ G0 u& Z. b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 @ j, o! A3 }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& d. W: `9 P9 h2 r" b# d* P
** Configure the McASP pins
: H) A: L! N5 [" @, O** Input - Frame Sync, Clock and Serializer Rx
; q6 D! h5 Z. ?) L5 C** Output - Serializer Tx is connected to the input of the codec ! d- t. r% r2 |+ G3 J
*/' l9 K+ J" v1 V/ V n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 f4 t ]7 s! s1 H5 ]: h7 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 {* q+ A6 T7 I: o( c1 xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 D4 e% M$ Y$ P. f
| MCASP_PIN_ACLKX. j5 [& o1 N0 J: }
| MCASP_PIN_AHCLKX2 V" Y& h; t$ l5 H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 q0 z# [8 `: c2 ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 o# @3 u+ y# g& U; T| MCASP_TX_CLKFAIL 4 i( D8 ?2 K, l
| MCASP_TX_SYNCERROR
4 h) {' Q1 n5 i+ e. G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR h0 F: \* @' R+ T0 a- A
| MCASP_RX_CLKFAIL
. E: M2 W! c( G3 K| MCASP_RX_SYNCERROR
$ |' T( K+ G2 _3 \4 a| MCASP_RX_OVERRUN);
: |8 u; g5 }% w0 Z} static void I2SDataTxRxActivate(void)$ @9 b! h1 G$ j5 E" i
{
q# Z/ } I* [/* Start the clocks */
) B" {0 Z* B7 L) z0 N, NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 [% j& e, U$ G0 i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 p w5 X" c; Q7 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 l4 J; U F) yEDMA3_TRIG_MODE_EVENT);
% J, Z. H. n, f8 q. _6 `: ~8 t& CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 a; I$ m8 _7 k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; J1 B9 e& j9 N2 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, \2 Z) L" W! V6 ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# z0 u& t) [+ |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' ]- E0 ~$ P* k( @" [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, t- R3 ?- f. kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# [: j9 B7 _2 _* l3 e7 _
}
0 c3 m8 |6 u D+ A1 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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