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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 N. |' x. |2 @6 U% M$ l; V
input mcasp_ahclkx,$ W6 t8 U; S. N1 s- p
input mcasp_aclkx,* d$ U# t" h. ]% y+ R" A9 g
input axr0, U% T, c9 T ]' e6 c
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output mcasp_afsr,
/ Y) O: `5 c6 i {- goutput mcasp_ahclkr,
7 Z: f0 W" `1 Xoutput mcasp_aclkr,
9 @; ?* h# B& _! ?9 l2 Qoutput axr1,
$ u$ J' {7 m& b' r; Q d assign mcasp_afsr = mcasp_afsx;: ], x6 a, W4 w4 I$ n
assign mcasp_aclkr = mcasp_aclkx;
4 \: o" J+ _! m1 {2 massign mcasp_ahclkr = mcasp_ahclkx;) I6 Y! F5 A: x+ r4 o/ V, P
assign axr1 = axr0; 2 T# w b/ m3 a; M+ c; n0 U9 m8 w
% a; d* r9 w0 [; e, U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 e0 S8 @5 M% [' y0 }) A
static void McASPI2SConfigure(void)
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B' f b7 i, EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; ~( D1 K+ E5 O- g7 }( U& G( _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ [5 p/ b1 d0 B9 u+ ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* u: c& o/ W+ ~/ o* q9 W2 g5 B. L: q0 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 o# z5 N! U) G1 [7 yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 H+ @- S/ r% c* @ R1 Y: n
MCASP_RX_MODE_DMA);
g9 k0 A( a* g7 e) l- c2 Q. wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% O+ H% H# _+ fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 E& n/ Y* R, c6 d' K6 ~4 K, S5 jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- w; R, O: |6 A, M, L+ wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# W) G/ h& Y- H7 v _. _7 u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ Q$ d- @" D7 @8 h4 A" f7 `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 H2 A; |. n$ t! \) F. OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* f- ?. P6 A$ m! h. M# ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % V- r2 n+ |0 w- a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 @7 ~+ j) o7 F7 W1 \3 \
0x00, 0xFF); /* configure the clock for transmitter */
, E# b3 h0 [/ ^- @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 N# E- L; A2 Q& S# \" M0 n. l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! H# q& }0 s7 _5 `8 R( cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# U( i/ ?% C# Z7 K! ?
0x00, 0xFF);& r& _# j3 C( k* Z7 f
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/* Enable synchronization of RX and TX sections */ ( O9 D+ d4 b& q- d; N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# D; U& q, V$ hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 g2 f% z* ?5 q) |" Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: N. u6 ~0 T6 p1 b
** Set the serializers, Currently only one serializer is set as1 {7 F, @4 j; z1 t2 _* V; E1 l
** transmitter and one serializer as receiver.$ P: J- t: @' }3 w4 E. }
*/% e S% w9 @' O- v$ H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) P" ^9 z4 @2 H: F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& H7 q0 U6 A7 p2 ^; [) }** Configure the McASP pins # j8 Y+ d! I+ J. e
** Input - Frame Sync, Clock and Serializer Rx6 @& X, R0 p! G' y) e! R5 H
** Output - Serializer Tx is connected to the input of the codec
8 x! x+ _8 N2 p3 S6 T) l; ] k0 A*/
. f: X5 A1 W+ |# k6 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& m# D$ a* ]; T0 w* Q& m& r( J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( o" X& z9 o9 w+ c6 @0 \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* p/ M( K) |5 L$ q3 g| MCASP_PIN_ACLKX
+ \% X4 Z. r5 b& I! ]& c| MCASP_PIN_AHCLKX/ ]1 e* `- R1 N- [, {7 `. U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# r3 i: }8 p% [6 q7 E \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 N0 u" ^* a7 x
| MCASP_TX_CLKFAIL
# _6 N C7 R$ t' Y' N6 J| MCASP_TX_SYNCERROR6 ~" g: f) H- @6 Z: F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# D' L' I6 e) h| MCASP_RX_CLKFAIL
1 `2 _2 [5 h2 d n+ S3 x4 x| MCASP_RX_SYNCERROR " h6 i1 Y8 Q* h5 r u8 c' w
| MCASP_RX_OVERRUN);
: u( o* S o' W6 ~} static void I2SDataTxRxActivate(void)8 C5 X% `: K6 p" x: E# \+ U
{6 W3 S* X: Y- ]
/* Start the clocks */1 _0 ^" v" N% R3 @3 V6 l; R9 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( a8 { h1 Z. z) f" n+ E. wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 t8 ~% A% X3 b( Z( x9 E6 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: M3 P3 ]$ U Y6 R. J1 K/ w
EDMA3_TRIG_MODE_EVENT);
* l! W! L" x* `3 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 g @6 R; Z9 E' A' M# UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 d t z& k+ j( v& YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ A# c! }/ P, K" X4 O' Z* Q9 h/ sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 c6 D6 m5 p4 J5 l; y3 u/ C; I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' T3 y# P: l, W/ ?( a$ W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; }, `% n# ~) _McASPTxEnable(SOC_MCASP_0_CTRL_REGS); ?; x" Z" d( I! o. q4 P
}
! t/ i3 x2 z, q- y0 q5 N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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