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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 z& m0 y$ \' J$ Kinput mcasp_ahclkx," P+ R) o8 F4 {
input mcasp_aclkx,
8 D2 @1 q3 @. S; X5 I1 O' n+ ?input axr0,- v8 @1 F& ~( T+ D& t9 r
- G; @8 n1 Q. o4 Y
output mcasp_afsr,
/ V7 _5 q4 g% e* _% u, f) d6 H Ioutput mcasp_ahclkr,
8 q/ u- P" Q; O- ]7 X$ Uoutput mcasp_aclkr,' f- J, T+ x/ I
output axr1,
5 V" f; {6 Q; k( K! c1 K" t assign mcasp_afsr = mcasp_afsx;
; H. s" p# f! ` A+ [# `assign mcasp_aclkr = mcasp_aclkx;6 l# h: u0 r4 R: _- F
assign mcasp_ahclkr = mcasp_ahclkx;& D, H: L" ?1 o; @
assign axr1 = axr0; ! g7 ^) d5 Y4 l+ |7 [ e/ W+ h
5 U- @6 V) g5 n" \3 d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) P0 ^( E* k; w! J( Sstatic void McASPI2SConfigure(void)+ A0 u* X) P/ K
{' C) S0 W% A" c% D+ L6 K( n7 R: C+ U1 c6 F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 a% }* n- n4 k4 v0 @7 S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ \7 `$ s! \; |3 l$ c7 }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( S4 R6 K5 ~! FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ Z e Q' z8 V/ xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ]; ]8 F' m0 I: x( c
MCASP_RX_MODE_DMA);
% X2 F; V; E$ e5 M5 R# E! a! GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: X, E& W* z0 oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 y; m" h% T& v' t+ A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 _( q& c- s. }7 w, o9 C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 P3 z- G1 [$ b5 N7 ~( G9 x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ K" S) h3 f/ T6 e& m0 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ m& H E8 b" {3 U& p& ?, S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 a6 V$ j. u5 Q) h( V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* ]2 S& Z; g4 pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; W& o3 e1 [" S$ i0 q+ U" R8 l0x00, 0xFF); /* configure the clock for transmitter */
) t) u6 t9 W( n( mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) n3 | g" j1 F6 h6 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* R1 K, A. w9 B- [" w! dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 C% j' p; c2 R+ z" S- _
0x00, 0xFF);! s4 K* i) F- W u+ U
% l& R9 T/ n0 Q( c; h
/* Enable synchronization of RX and TX sections */ ) {4 v- ~1 G% d) q. i; M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' \) k( E7 o* j) V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 B5 m2 v# t2 b/ t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 N7 e6 {& F7 g! g `8 _9 x** Set the serializers, Currently only one serializer is set as
* J! D) H# W, ~0 V' x) S** transmitter and one serializer as receiver.
i, m+ h; m0 R' }+ ^*/
- X. v% c" z0 ]3 c hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% K5 m+ c5 v$ ~$ i) n* ^ OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 a( Y: w' W2 W$ J) G+ v, a/ S** Configure the McASP pins
, k1 t+ t% f! z5 S# }** Input - Frame Sync, Clock and Serializer Rx1 ^( |8 _3 J. F% K
** Output - Serializer Tx is connected to the input of the codec
0 h, X' S) C# b*/
+ S0 h% h3 @5 Y6 N8 r, B8 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. ]- W) K# |) L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ m1 w' l6 s7 r( xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" f# [4 q" t2 P9 i3 W
| MCASP_PIN_ACLKX
R' j9 u3 T. S3 P5 c| MCASP_PIN_AHCLKX: h1 S) Y$ m- p- x% l" {3 K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ Q" U5 l) K8 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' J& G3 t4 B- }& g* t
| MCASP_TX_CLKFAIL
; m' O- Q& k8 w. Q| MCASP_TX_SYNCERROR
" L3 t4 N( D+ Y; g: T( T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ f( N& D& v3 w" y4 u| MCASP_RX_CLKFAIL! W8 l& [% G& E
| MCASP_RX_SYNCERROR 0 v/ N2 I/ i0 x0 D! |/ x0 w# q
| MCASP_RX_OVERRUN);
% S! c) ~; E6 v7 x, p. J* k} static void I2SDataTxRxActivate(void)
% y+ w8 L; A6 ~{
) }/ a5 Y% w7 p$ ^6 m) b3 m/* Start the clocks */
. V' {; U+ k/ O) ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# h5 K! M8 M( v5 _, E" M: x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" L, n& W% r+ B2 f" e4 o e# O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 ?& w: O8 o; T8 c4 r" TEDMA3_TRIG_MODE_EVENT);
+ h" a/ Z- \6 y, c* J8 r3 w3 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' T. D( v8 E! lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! v2 z" ]. L' s$ _0 D, ^+ u# d( c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. I" n0 H& U) p! vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 B+ ~9 `+ I+ l$ C: H2 J+ b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" Q/ d6 j/ [' d* b7 @5 t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, A7 I( ?. @5 q# U. B* ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ z- \; Z8 @8 k}
" n. J; j9 B9 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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