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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. r" {+ w' C9 N) N* A) a
input mcasp_ahclkx,) a: }: y6 G+ x( x
input mcasp_aclkx,3 @5 E5 P8 c- T) B/ a ?
input axr0,
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( h# n7 x5 V7 X* G9 j, v, ioutput mcasp_afsr,1 [0 _$ t" e5 l' Y, G! @
output mcasp_ahclkr,
) e$ N: \8 \' Noutput mcasp_aclkr,
: v" h$ }2 x3 L# B( Aoutput axr1,
5 @9 ~. b2 |# F* Q: H* g assign mcasp_afsr = mcasp_afsx;
- d: l) w! M* ^) zassign mcasp_aclkr = mcasp_aclkx;. `) r/ b" M7 s3 L4 h
assign mcasp_ahclkr = mcasp_ahclkx;
( a+ u5 f+ N/ Aassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & W1 C- [; X( o0 }- m! D
static void McASPI2SConfigure(void)
2 Z* \! R4 S, @8 k5 A{- B7 G1 a) M& B3 e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. E# k: t$ N0 v% w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 y; f) |& |8 n o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ H+ u3 L6 G) RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% {" g) W! U, B3 ]9 V6 U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 k8 n* w* Z4 V8 t) ]+ P1 r7 C% LMCASP_RX_MODE_DMA);
% K# Q( p7 x: R4 @! J7 g5 Q/ wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ ~* T* ^# O- f) P* j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! {* S& R3 I s+ qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' y3 S5 I8 K5 B: t l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 s9 O- r2 m' s( G- _- m6 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) Y% q8 i* V8 i2 B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ W8 o4 A- L9 @- _: _8 ~3 g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& M; R f2 b( {% G" P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , z3 U) `5 u) v2 f. G
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 K" T- a4 j6 Z9 }1 }
0x00, 0xFF); /* configure the clock for transmitter */" ]3 ]% h- v+ u3 V4 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 d1 X1 ~0 e2 y; e! ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 q0 |! n5 i: T4 T$ tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
Y+ |6 u: x' x+ ]" F0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ 6 I) J7 x" C8 N; |1 p" O" j* y1 |$ Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' }& {9 K1 R5 J9 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 i/ h6 l1 N: g4 u! ^2 tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' e2 r: F9 ]7 A5 ]% x
** Set the serializers, Currently only one serializer is set as; u8 {* X; r# l0 n( A5 m4 K s
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ p: q, A, q) ^$ e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 S( p# X9 @5 L- i6 d& G* P* [2 a** Configure the McASP pins 1 d( }& t' g( b2 h* k# A! @
** Input - Frame Sync, Clock and Serializer Rx
1 f, Q! H: ]# m0 y4 _2 m1 I** Output - Serializer Tx is connected to the input of the codec
1 d: f: j* Q$ o/ F9 g. k; A*/+ [ p% R; Q) U, Y5 j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( L A. _, s& [4 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; z& T% b9 e$ k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* S! c% [. m& j5 J0 K c
| MCASP_PIN_ACLKX
4 U" b. B. a& ?6 h/ [ l& g- p| MCASP_PIN_AHCLKX
1 a2 U# P( d" c; h1 P; L, H% @ R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- U& i- r1 [) |( h& s* u! V/ H! xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 R. p+ i9 z6 s9 p0 K| MCASP_TX_CLKFAIL % p* v m- v, \2 D
| MCASP_TX_SYNCERROR
5 S! X" T8 l8 N! q' F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. ^4 D6 m5 ^7 K| MCASP_RX_CLKFAIL: M- ~$ @- b$ Z
| MCASP_RX_SYNCERROR
. _9 l# E+ f( L& p& q. y| MCASP_RX_OVERRUN);5 {: x" B5 t" Z( p
} static void I2SDataTxRxActivate(void)5 m% ^# R0 `7 |( E& l8 V
{% j8 [ V- l0 x' J) s
/* Start the clocks */% V& {9 k/ v6 f, q! ~* a; |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: E/ p3 T! D5 [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 `/ e& ^) [$ A! @+ e# ~/ g) J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. \& Y/ z. x8 p# X6 s2 H% hEDMA3_TRIG_MODE_EVENT);" S6 ]& o% ~* N* J0 `9 e: R7 A0 T/ i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 k8 h( Y0 b {' j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 I }( @$ n( B. W& E7 e+ t. iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 d) t% x( D# t+ E0 J. R3 X; pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; X% D+ j8 J; g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 N$ T! k8 ?: f% M% j2 z' P) l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& ` p' z) v) @+ Z) @9 q4 V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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