|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
_0 \3 n! K; ]4 R+ x+ Minput mcasp_ahclkx,) x0 a, N" c' @( c2 e# t7 u* l D' p
input mcasp_aclkx,
1 F7 k& F1 A S) c: [6 Oinput axr0,
. U( b( B! x- M0 v
9 u2 {1 R r7 ], Loutput mcasp_afsr,
5 S$ ]7 p4 Z; S6 U0 I/ J1 {: U9 Goutput mcasp_ahclkr,- h u* c$ X, R A9 Z9 P/ d
output mcasp_aclkr,$ h8 ?8 U3 o: `
output axr1,0 M3 r: g- t. e* w- S
assign mcasp_afsr = mcasp_afsx;
: H* a% e2 [9 a7 j' e0 ?0 V6 Tassign mcasp_aclkr = mcasp_aclkx;
" }9 q- r& I! b$ V2 A1 X7 x$ Passign mcasp_ahclkr = mcasp_ahclkx;
. `3 `/ _# O. Z! h E( lassign axr1 = axr0;
, O8 t2 P0 Z- y z' B! X8 S0 P K3 b- U& r% m3 m5 b4 z& D( Z" u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 f! }) P& A+ g9 p v
static void McASPI2SConfigure(void)
0 c8 K6 Z- u+ f! k0 r- ^3 Z- a! ]{: |& O2 ^9 A2 H1 F0 X8 |1 u8 Y1 b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 b j8 a7 V s: K8 w- lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 y0 f$ ^$ t% g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) [3 _: k# u! c* P6 b/ q& G& X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 [5 F: M" `( l7 hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 ^3 [" T. Y- {5 j8 X
MCASP_RX_MODE_DMA);, U5 t& ^- M) y) ~' C+ ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) r! p5 d& J! WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' T% w. W# T( Q3 HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - c* e. ?2 X; `; I9 g( v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 L. b8 [0 [7 F b {% m$ BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 O" d" W: K Q+ L) F$ N: O( x) n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
L0 }/ s1 B- p" v, d. lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! B/ w7 v. s, [$ g8 E5 r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! g; r; w$ S6 l2 E$ w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 h3 h8 _) z8 x
0x00, 0xFF); /* configure the clock for transmitter */8 H' w& x0 C; i0 q2 w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 R3 Z U2 M: T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 Y4 A, n: o% s! LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 y8 h4 i1 e4 T1 S8 p0x00, 0xFF);. _& a; ~0 P B. l3 p* I
0 f2 o' A2 {' F
/* Enable synchronization of RX and TX sections */
) g6 W1 m7 r) V4 g. {7 Y8 \. CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ Z; o+ M0 k# pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 k2 o* O4 l% F7 X9 M+ I1 ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; d' {: }% h" ^8 p0 @
** Set the serializers, Currently only one serializer is set as
% l7 x$ }2 F' M/ `$ g4 {** transmitter and one serializer as receiver.0 d; V1 H3 \2 D5 b
*/# d. B+ o% f1 k/ F- S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, H& Z7 L$ T3 `' B, }3 @/ jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ R. x5 `1 q' @# R. n** Configure the McASP pins
' i7 ^; r; v! Q8 h" M** Input - Frame Sync, Clock and Serializer Rx
9 w& M7 n: f8 s** Output - Serializer Tx is connected to the input of the codec
1 b( ~5 M/ i N/ Y*/3 A9 T/ c; _1 E/ ~; {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 U( e% r% N; S% e0 b' mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; t, `% ^, [# {1 g1 T4 G6 s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% b3 {: R; Q4 E/ m: f5 z. J| MCASP_PIN_ACLKX
& Z, g( \/ p3 l6 V: v| MCASP_PIN_AHCLKX
& H& q# e2 ? e+ c3 O, \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 ?3 J1 C7 D& l! E( V$ kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% i+ K! _. X3 z; I# {6 w: M6 K: J| MCASP_TX_CLKFAIL . g. P# {& q. C2 Q/ N5 c
| MCASP_TX_SYNCERROR2 _+ Q- b; _, u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: t4 F$ Q/ U- L( K' i9 {) z% y$ X8 D| MCASP_RX_CLKFAIL3 ^' y6 N& Q2 q& g3 C2 k, O
| MCASP_RX_SYNCERROR
7 T3 C0 L: z: [1 G i# }) A| MCASP_RX_OVERRUN); z8 |* u. m- E" Z
} static void I2SDataTxRxActivate(void); |- e0 x1 c3 H: Z' V( Z
{8 J4 j: S( _9 r# A
/* Start the clocks */
4 |" C9 ~/ A2 [1 ~# N8 P' M, EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 N6 j8 v% ~1 A9 b& MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 ]) _- z7 M5 P7 Z v7 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% @0 V& J$ ^. ~9 v. u. {' ~
EDMA3_TRIG_MODE_EVENT);/ N, ^ {" C/ w6 A% l5 p' W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 e9 @/ m2 F- @4 j8 C5 a$ e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 \) j* j3 b% a, P/ k6 X- G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- p# W5 o3 n; i! JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ D& R+ N2 w% ~# G1 V" L' c4 X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// i1 O# n3 \; t, t* h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); w; f9 _, D3 t! Z5 A: n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! c' T8 H6 h! z! \7 g$ H9 ]8 A
}
8 o+ F0 B9 u: r; P# ` q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
" u, |- X# `, v! c/ r |