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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- }& {% `6 {8 @. Q3 Y
input mcasp_ahclkx,& K8 I. q; c0 b s
input mcasp_aclkx,% |+ A3 }+ m6 C- J1 m4 @
input axr0,4 u. c- d6 r: w. z4 l
) k- `! U" F. {4 B% L8 g# \output mcasp_afsr,
5 U2 ?; I' g# D, u. l Goutput mcasp_ahclkr,
1 m$ H$ T, C$ e m, S Coutput mcasp_aclkr,2 v- q G9 h8 W" {' r$ u: V
output axr1,
7 J- E& @1 `3 c$ W assign mcasp_afsr = mcasp_afsx;" y6 ^" E8 _: U" H2 Q
assign mcasp_aclkr = mcasp_aclkx;7 ]% O) \) A- Y0 L9 I; m% j6 _$ }
assign mcasp_ahclkr = mcasp_ahclkx;
2 N1 @+ k7 U F; T, iassign axr1 = axr0; 1 g0 b/ K; {& n9 X) o! H8 W
# L6 `) n6 i0 Q4 N; N9 s$ \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- s% d. v: y: r- y. k5 O X% i) Dstatic void McASPI2SConfigure(void)+ P5 [0 |' ~1 E& L
{
7 `/ R4 u) a- v* PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' i: O' ~8 b* U7 v z, n& o( mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ X4 K: p+ o; a& ]; f8 l7 jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( }1 G% u9 @$ c- ~) O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; D; X$ e/ V" [* I+ J$ |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! \+ F$ O- I' ]7 k) f. W# ~MCASP_RX_MODE_DMA);4 U Q5 y1 e5 ^, B: z3 L* j+ a" i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ r2 k- G! u8 f, _5 U" UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 x+ u9 ^1 G4 k" I* k+ `0 A" X, h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 R, p {2 k8 l" U, |8 c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 O8 O$ q% m% [+ e7 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ g2 c' b( o" o: e% B6 J' w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ o6 A% z& q9 E; g% M8 n3 j/ NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- _1 ?7 g( }( e: X9 p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 Q9 I5 @7 |& w6 n9 d& w( fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 D- @7 L, H- }$ S& m0x00, 0xFF); /* configure the clock for transmitter */# |+ p( o C, R; Y1 r7 R! Z/ r. X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 P" h6 R$ v @- ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; s! H1 I- Q4 ^7 N1 t0 ^9 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% ~" f- l/ M( z9 n9 H
0x00, 0xFF);
h; g0 a# l8 V) t t2 @
- N) u) G0 R& f/* Enable synchronization of RX and TX sections */
' E/ }/ H% ^( n0 Q4 x+ {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& \1 {9 q' G- i4 h7 e, DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 G1 O- F g/ h- \& C& X4 W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 {/ m% I& e4 D* k/ {3 f5 F6 V0 \9 f
** Set the serializers, Currently only one serializer is set as
0 z, J3 D7 C, K, f0 ^$ {** transmitter and one serializer as receiver.7 L; v$ S. v ~4 H
*/( Q, c. P8 n9 c! \ k% ~+ U5 l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 }! B' w' m$ |/ [4 Y- ~! eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" ~& t: X2 ~# c& b) j- H
** Configure the McASP pins
5 E2 S7 {, I% N$ _9 g* Q7 Y** Input - Frame Sync, Clock and Serializer Rx3 l& x2 _. j( X0 j) @" }+ r( P- I
** Output - Serializer Tx is connected to the input of the codec
4 M- U4 C+ T, g*/: L3 r4 K4 l0 X% F$ m, g9 \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 K* u- I8 U( s# z" b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 a) W& x O7 f$ s$ M/ D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ u& r8 `" Z1 |) P| MCASP_PIN_ACLKX! S# O, [7 I$ y6 T& y9 l
| MCASP_PIN_AHCLKX: h5 ~$ b! Y/ `0 N0 \) d+ Z Z0 Z1 F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 L* e; n# X- A6 p5 Z% wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 V& N# n/ X0 \& d2 y6 L
| MCASP_TX_CLKFAIL
. r( P. n7 A" j) t: u' V; S| MCASP_TX_SYNCERROR
! R6 X2 H4 q& ~& b* o" B; I& \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" H; E% L' C x% J5 V9 d| MCASP_RX_CLKFAIL
& H2 W3 b- ^1 G$ O$ J1 \| MCASP_RX_SYNCERROR
, r; X' K. z c0 T( a| MCASP_RX_OVERRUN);# E, _- p* k2 z4 ~$ \
} static void I2SDataTxRxActivate(void)% j3 m( y. B: k1 A/ L; Z' d
{: D5 p7 v) Z9 ]+ O1 d* E/ U
/* Start the clocks */% q% H$ A6 K. T g. s, K, R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" L. V1 `/ A7 d9 L/ Q3 xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ q+ r$ Y4 W( w9 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ c4 c' {0 E0 ]1 |0 [EDMA3_TRIG_MODE_EVENT);
$ v ~+ s2 x# s. c/ MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
M+ V/ v1 T/ NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ ^3 Z# g0 @: x9 _3 f* E% a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 R5 c% p# _1 w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. y) }' x: h+ { F' E2 G8 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 s' u0 _! V/ u4 w* C. EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- h3 M" x `4 w7 i! k' E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 `8 L+ v! S# \, }) i, U}
" D. u1 u5 R$ V! }9 f- C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! X3 [1 k/ p7 F2 S
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