|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 Q( P, f; X4 e h8 ?
input mcasp_ahclkx,
! W; R8 a7 n9 ^& _8 Binput mcasp_aclkx,1 D$ k* g% x# D$ F, M6 z9 S
input axr0,2 H5 l3 x* C9 n l6 F4 @
9 v3 L$ Y3 L* `4 ?- V* Zoutput mcasp_afsr,
: P4 |9 S+ |5 {4 Doutput mcasp_ahclkr,6 O% x; c7 Q7 B$ C6 y- D; S: t1 q
output mcasp_aclkr,% [* l8 K- V% A3 ?/ Q* n1 \
output axr1,$ U# Z( B8 o3 h9 ~9 V# B7 D
assign mcasp_afsr = mcasp_afsx;2 a! K- s- U! V: ^6 X
assign mcasp_aclkr = mcasp_aclkx;
! K4 ?$ T/ ~0 |assign mcasp_ahclkr = mcasp_ahclkx;7 M, E9 _9 x1 l! Q. R& T# I
assign axr1 = axr0; + q% b: V; d! Q
4 s/ P# {$ R; B: f1 R+ i- W' W- F5 Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # j- O9 t3 g/ P, W
static void McASPI2SConfigure(void)& D, B* A/ o! ?( L) I. Z& D
{
) v* |# l% O" s$ `! P# h7 ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ G) U! c/ O: H4 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 X' r I9 P0 vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 V/ |: D2 V b5 r: yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( e. `) V' m! H7 H6 wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) a' o4 n0 U& }4 l' d, ?% DMCASP_RX_MODE_DMA);
) K% N' N3 ~/ Q" U4 d# }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, C/ Z% h& z1 E4 OMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 P& \9 L1 O4 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 N; j+ y0 y- c9 _3 q: D' ~0 ~/ W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 L% @1 ?$ D" O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . i9 [3 l: r! V* Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) n4 h M( Y9 a, y( n5 Z# G7 `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# \# s' y5 S7 S0 e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 u! k& R$ p- t' q aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," U ?( A2 ]0 ]2 J3 G& d
0x00, 0xFF); /* configure the clock for transmitter */
# f& ^" {; {2 H! ~, y. GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 K: B# d& E, W0 s7 m. C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 x5 _& h+ `& k6 ?# s$ H( S9 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 C" z& q+ ~6 H- g" t+ d0x00, 0xFF);' z% U$ z5 ~! ]0 c/ P1 R# A; T- \
1 m# F. \6 w) a+ B& U. ?
/* Enable synchronization of RX and TX sections */
! P3 N/ F, D( r( B) w8 hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ T4 H5 b. L0 m% _" P; cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ g/ M! d' O! `, N( pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: \( I& M. N1 N7 m0 E5 {2 }
** Set the serializers, Currently only one serializer is set as; @6 F4 a( F& A9 `& A) F
** transmitter and one serializer as receiver.
3 G- {. m3 ~% O4 _$ d& h*/
& O* H) O @9 t$ n6 p5 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( @1 b4 Z$ o% `" eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# V" x& |( W6 b$ X* S3 q** Configure the McASP pins + X- x" ]. z0 a
** Input - Frame Sync, Clock and Serializer Rx
% {) w% E0 r" x9 |$ S8 B9 U** Output - Serializer Tx is connected to the input of the codec 4 N- \- z+ f l% Q8 u
*/4 j1 E @; j- g% m! ~% C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# P! x$ f6 _$ W5 V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 L; T8 q+ ?( [' K5 Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% l3 r" ]4 X% [7 M: P| MCASP_PIN_ACLKX
0 v$ c s. g. t| MCASP_PIN_AHCLKX- ?- Y+ o, ~) y4 F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ U# ^& K2 M( Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 C5 L3 E& S) i i6 U% Z ?: m( X& \| MCASP_TX_CLKFAIL
( @5 A! N$ h: ]+ S* R; U5 f6 J| MCASP_TX_SYNCERROR
& e4 D4 V, G' `1 V1 a3 A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; g% u5 B& ~- \5 d; ~& C| MCASP_RX_CLKFAIL% e; K+ m4 {4 A0 d9 ^
| MCASP_RX_SYNCERROR
* W( ~' Q# Q$ [| MCASP_RX_OVERRUN);
0 G, y$ |0 t: r5 |} static void I2SDataTxRxActivate(void)& m" f" i3 q- E; K, l
{ O% Q: X& {& j1 @" C. m
/* Start the clocks */
! R1 d, D" g) g/ lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 B* G1 x" n& H. _( \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) d% N; i. ^ m# Y: ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( p* Q1 E+ ?; Q/ u6 S9 ]EDMA3_TRIG_MODE_EVENT);
- ?5 F5 H# `. [& L- ?9 G& hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' x% i7 `* v# n; _$ FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' E, a; }' g3 j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); E2 B) ^' Y R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& Z! ]: J, e: d" ?3 Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 T. d1 U3 j0 k. M' c0 jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. v, `8 k! W' P' W& `+ L! r0 d1 Z/ J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ @0 `1 w/ O3 v9 \, H" s
} 5 X8 x. V+ j! [, d8 h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) u" q! W% I6 r' ?% b, f/ e, _ |