MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
. v8 Q7 t' `" pinput mcasp_aclkx,
7 H0 o( H  Q) g6 pinput axr0,
) c; [$ ]! J, d5 M5 b4 ?9 g, b* w/ R
output mcasp_afsr,
output mcasp_ahclkr,
: `6 x8 ]- m+ H; \; Soutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
2 D9 `# o2 N# f- _1 Nassign mcasp_ahclkr = mcasp_ahclkx;
, I. t; N' M( P3 \, O; i* j' _assign axr1 = axr0;

1 T- Q" ?; ^: t: _4 N& h

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
4 P$ U1 g; [5 a8 x{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 h& h6 z. N1 @+ bMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
/ I6 `' G0 J% c/ c# T5 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 g& z( a0 N* ?/ o5 s4 x3 |MCASP_RX_MODE_DMA);
: T! n. W; Q9 P6 d: IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, p. I) y/ ]9 M9 z$ ~% X5 \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& R' k- I6 K/ N. e! B5 t+ G2 V2 @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 L* v/ k; q3 W+ K- ]: VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 `$ G7 ?7 v# I: G4 l/ x5 V5 M1 W, b0x00, 0xFF);

/* configure the clock for transmitter */
) _4 X; A* Y( A( E  n6 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ O' O! O! t& Q- R0 mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

+ F! d0 ~" a$ v$ M/* Enable synchronization of RX and TX sections */
: ?  I0 S/ P% xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! f( e( b# F9 X! p- c' y. p& wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
. [" c$ b% x8 d# S/ Y" MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 \/ n1 U, U: fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
4 Y0 ?, Z0 }# c6 M: G** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
7 i" z+ p7 z1 g& R6 d* L1 n( @8 L** Output - Serializer Tx is connected to the input of the codec
*/
: O: f! A1 Y* R0 F6 {! vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 v1 _) w$ A7 A) R, P# Y, oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 n* X; a9 ?* H! t2 h& WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 d' P5 `" }! }# p) q: R| MCASP_RX_CLKFAIL
9 z) D, e* b  C| MCASP_RX_SYNCERROR
- J/ w6 \; I+ G6 P| MCASP_RX_OVERRUN);
1 P# m% G( J+ W4 h3 P}

static void I2SDataTxRxActivate(void)
- H  f( [0 R6 h6 L3 H{
: X2 P& w4 n' |! U: H/* Start the clocks */
) _/ q! ~" L* X, x4 oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# _" ]; _: h* w: {. A5 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
% I* w8 ~# y8 VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
/ H7 N9 C+ f+ N$ Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. W$ |. O/ |4 y. B7 a8 UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 {7 z' S  O8 }+ F' J2 c) r}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

" W' i9 }  o3 O2 n0 [1 h