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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( Q7 X) _2 ~! {input mcasp_ahclkx,
- t9 [; S1 ?9 C+ c* k; Hinput mcasp_aclkx,; l0 l- k' k; |1 j
input axr0,
& @& d' X9 h+ v% O
5 K+ v' t. P% ]3 U1 coutput mcasp_afsr,
. T3 Y: `0 \/ Y0 H6 @output mcasp_ahclkr,
2 n) p8 J7 I7 P, Q! Moutput mcasp_aclkr,
3 T/ G1 o; ^) E, Y# z/ koutput axr1,
! c. W% [9 f6 a2 m4 a8 y# ?" z assign mcasp_afsr = mcasp_afsx;5 ^, M' V1 v8 [6 P0 B
assign mcasp_aclkr = mcasp_aclkx;
0 y; _& m% q2 Sassign mcasp_ahclkr = mcasp_ahclkx;
4 e' U1 ^0 j9 N7 \ f7 j+ Z0 Jassign axr1 = axr0;
; T0 n8 q! N! y% Y% D1 l
- p/ z, d$ w. O7 A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * K6 J. o3 v+ ]
static void McASPI2SConfigure(void), c5 N) l& B- g
{& ]) j* A9 d9 [- t' v. p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- I3 l7 `' l1 I& y) OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: \( _: z# ~7 S; j0 u- B9 a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 Z1 U& B6 y- N, R0 y5 Y! p" i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# b3 A' @# d |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* k5 b( t3 a% S, A( e0 d" V0 I( I) R
MCASP_RX_MODE_DMA);
1 X. t1 M3 s" |7 W F& t! HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: C5 _' w, m/ x, N" ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. e4 m( ~" h! z+ r' @, _% K. M# WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : d# d- V( y$ U+ X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& p2 i9 k9 N8 f" r8 NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 K1 B* A. U. d* p* v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 U% _- S5 F L1 p7 HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; `, F4 S: ?' ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . X* D _& F* u+ S. ^4 D+ T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 {) S8 w! j+ m- s" Y* r$ i
0x00, 0xFF); /* configure the clock for transmitter */
9 K) z8 s8 {$ b( {$ f2 hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 h1 q6 m: D, F0 B0 _4 n! `4 \- kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); z8 Z9 W" [6 D7 l, R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," ~" M) s3 b. v w V' V
0x00, 0xFF);
4 H0 D$ \% Y; d) R0 R. ~- V1 d* \4 W1 W# M: E' p
/* Enable synchronization of RX and TX sections */
: p0 b& M+ a% oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 ], G5 O q1 R+ u4 ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 ^! J+ K0 R4 p% \' n/ N2 JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% T w6 y; H7 H0 v) G- V: ~- }
** Set the serializers, Currently only one serializer is set as4 J, z: U ~. x8 s9 l* e! p
** transmitter and one serializer as receiver.: a9 c& i1 o! B8 ?; e6 s. _. z
*/. v$ P. e& u4 Z# X* ]$ s6 R; D: s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, n! ]( c( A6 k. O) r( o/ k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ v* O, g. g7 i u** Configure the McASP pins
7 c. J" z ^( @; n# S% Z0 K** Input - Frame Sync, Clock and Serializer Rx
6 [: m- G" O( P. F% Z B8 F: g/ J** Output - Serializer Tx is connected to the input of the codec
# t# n/ ]- j) h, P: p1 ~. l0 G*/& n- P' s: P4 C( P3 b" o: C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* x% \, G1 i6 ?6 O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! R( z: {; {# L+ g$ s1 }8 n& v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( |( a2 l# v* D1 ~1 Z* c
| MCASP_PIN_ACLKX0 g9 e2 E4 w4 w8 u0 O: `
| MCASP_PIN_AHCLKX
7 S- p; @ D1 r" k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 X5 I! {+ v N0 A7 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 W' S3 H+ x V+ ?, V
| MCASP_TX_CLKFAIL
. q5 ^0 A- S5 \+ n# N0 A. u| MCASP_TX_SYNCERROR% |5 B# t" C. n+ r2 k2 c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + z% A8 U% _& A7 b4 @
| MCASP_RX_CLKFAIL3 N& C+ [# L4 L7 E" n
| MCASP_RX_SYNCERROR " [* n( l0 H! |0 ^& z* K
| MCASP_RX_OVERRUN);
6 m; \" s: M& B/ \( [, C! y/ A} static void I2SDataTxRxActivate(void)
3 Z# i! j5 y' ^) x& v8 T& L- t+ m{ E* x. J! V0 }3 o( k
/* Start the clocks */
" ~2 v6 g: l: x( n \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% O" S1 ]7 a; S& `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 k8 E: U9 t3 d" \8 H# R& Q, b/ d- G8 f1 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. D3 S( U$ i4 N. S1 HEDMA3_TRIG_MODE_EVENT);& Y' y/ v/ z! y' y4 M. H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; I4 d, @3 |7 K3 u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 i1 i8 D" |# J7 E: j4 TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! R+ _& L* t) ?# m& r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: t5 i9 q; Y5 R! v5 l5 H( c' ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 h$ B, C# S# d2 CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 ^, w$ M& F# `' y& N7 ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 [% F/ y/ ^3 [# Z' }}
z: r4 {- d, P5 R" ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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