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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; Q' ~3 ?! F6 b) Z4 I* n
input mcasp_ahclkx,, |9 Q! G. P/ x# [3 L2 c/ [
input mcasp_aclkx,: \" l/ x6 m/ ~( c, S
input axr0,
0 O7 h/ N/ W. z: d8 ~7 f; w, s" n8 `5 U: Z4 L/ w5 C
output mcasp_afsr,9 m2 }) x! e+ y- |+ X+ A+ O9 \
output mcasp_ahclkr,
. a( d& W) _- y: s: A! @5 routput mcasp_aclkr,
. Z8 n. x0 v0 w( D0 ]& o/ Qoutput axr1,
. q1 d& _. D3 H% u0 U4 L2 Z+ f assign mcasp_afsr = mcasp_afsx;5 a' P* r' ^7 o9 Y% F4 D5 F( r
assign mcasp_aclkr = mcasp_aclkx;' f! F% _; V# Q
assign mcasp_ahclkr = mcasp_ahclkx;! L3 D3 I; T b; {( k3 N% {
assign axr1 = axr0;
1 Y' s& O3 y( P$ w8 z4 H$ f) \4 G/ P6 S. r8 n. Z% N( K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ t2 J, x6 c) \% \) p J* `: Z$ j% ^static void McASPI2SConfigure(void)
- ^) u; n A# ^{ j7 y- z A' W7 |+ V. M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* V) C( C- ~6 D6 R' g, H" E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! \* B6 w/ |2 z& U5 BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! }" {+ t" _- L/ _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# E) I7 x. r* v- |4 B! s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 M- [1 T* s1 w; u# tMCASP_RX_MODE_DMA);2 r2 [& p% J" ]; y6 ~% J" L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 Y1 O9 n6 s3 v" I/ w9 R; M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 o2 F9 O# ~+ F' \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 ^1 G8 P% S% i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 c5 K/ n8 U$ V M$ N% \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: `0 R5 ?( G2 J, cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 v4 o- D. Y$ B8 l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' H1 [2 t; x% A8 u9 MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ U' b: O8 @8 EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 U; i' D4 ~4 x* u: d
0x00, 0xFF); /* configure the clock for transmitter */
- E3 q' w1 ^ e4 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# b F2 j: E8 V& ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, ]8 e2 M. A; n% EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 U6 T% Y& X! @( f9 K0 p, ?0x00, 0xFF);
W6 g0 s4 ]2 r# m
+ u; s9 P( K4 y9 G# r/* Enable synchronization of RX and TX sections */
2 \! z9 U2 I4 ~7 t }+ sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 r# }# {% f; M+ M/ S) R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 s6 @. X0 V; K5 B0 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; [% @9 q8 W9 H( t
** Set the serializers, Currently only one serializer is set as
; n* _; @9 n: O/ ?1 b$ I** transmitter and one serializer as receiver.- t @1 J R, M) t8 G5 x4 u* o6 n
*/
, c& X$ Z. X- I6 Q* I6 h2 [7 C" zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ g# }( W; M: x) Z4 @; BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 [9 ~) [7 _+ D6 R f1 I( ^
** Configure the McASP pins & D/ }, T+ @* `; k' b0 u
** Input - Frame Sync, Clock and Serializer Rx
7 d" x6 u# z: j( b& Z4 k** Output - Serializer Tx is connected to the input of the codec
) D; t! t% U' u2 u& c*/
$ c- Q7 T! b" }! i/ {7 q$ o; h7 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" [6 F' h" B2 L- L( n! }7 ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# W# L, B" }1 m( g. b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 E% l/ O* d3 T, Z2 T6 a| MCASP_PIN_ACLKX9 V0 M. c: C, f% b; G: G7 z
| MCASP_PIN_AHCLKX
" J: ]! a' W! z+ b0 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ C3 j# |0 F4 N9 V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 i- o- c# G5 k. @& K+ a| MCASP_TX_CLKFAIL
: m6 Z. K$ Y* d5 P| MCASP_TX_SYNCERROR
7 P! F+ D b& S; H9 L- F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# o8 T! A/ `; B| MCASP_RX_CLKFAIL
+ i: j y) |( j4 V| MCASP_RX_SYNCERROR 2 x0 T1 P u/ i, h% e5 Q
| MCASP_RX_OVERRUN);- O. V: ?1 R4 n- z; S. u7 a/ v4 f$ p
} static void I2SDataTxRxActivate(void), P$ ^ L* K* O
{3 V/ Q" h1 T) H- |% W
/* Start the clocks */
# R0 K# L8 V7 q+ _1 ^! A' p1 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% S# B& M g+ Y: e6 s9 u, a7 o R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! Z* l* G! O# R6 L: w" B8 d# v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 H3 ]2 ?4 v6 v7 h* g; u
EDMA3_TRIG_MODE_EVENT);. R4 m( n- k, V$ ]; e; o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' O: ^, X' N, w4 h! G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, E* N: k/ O' a2 b% H: x7 S1 K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. N% t6 x! ]5 z) ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) h3 s/ T8 J7 B) u Q1 Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; f% ~2 f8 ]$ o0 `1 a9 OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 g8 D2 V. u e; h- L" L) L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* F o/ m2 f' @$ m
} : x; u1 ?( E3 P0 h" j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 G, I8 T* ]; v6 R, r
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