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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* g- F" Q. ], T9 u( Z3 y. d
input mcasp_ahclkx,
5 [+ {* o% J8 k9 |8 u7 y) Pinput mcasp_aclkx,
; i- z& G2 B' U" Z# t* pinput axr0,
3 z3 ^. s' l3 M$ |; c3 M! b
% m# G% U l. Y, a! [( L9 [output mcasp_afsr,
3 T; s. G: A( f" i ~: `output mcasp_ahclkr,$ E! U5 Y' u! w2 a" c' H
output mcasp_aclkr,
6 Z k2 O# o/ X O* L" h& M: Joutput axr1,
& H5 U4 p9 p% v. F assign mcasp_afsr = mcasp_afsx;
4 [- H5 ?+ ?+ i5 ?7 H& k! dassign mcasp_aclkr = mcasp_aclkx;
( Y S4 j* n+ n2 y6 Eassign mcasp_ahclkr = mcasp_ahclkx;- V; ^0 K$ o! W4 t
assign axr1 = axr0; 1 f- o' F H5 j: b: G
8 }4 P. {8 f6 V! U4 B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 d& f% ?; n# N( B$ ?static void McASPI2SConfigure(void). P2 i9 ?9 Q+ j( c0 G9 x
{
- }- N- B7 T! Z% F) k6 t3 ^0 xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 p0 U" B, l; vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 c2 x1 \( o% ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 `1 M5 s- @ m- n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; P; X) ]8 ]% E9 ?+ UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 T& {8 D4 P8 F, C5 |MCASP_RX_MODE_DMA);
, I# `, r4 e+ O. O: j6 MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 O) ~3 m+ z, l' ?2 S* k+ M; ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 Z: [, b% _" t! z: d) [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- s3 K- t! ?, K# @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 }1 b# \3 h' f# T# ?4 q- r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 {1 g( c, B5 R1 h K0 u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) L& Z+ }" H5 z, kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); W! q" U, N- u2 @2 V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: g3 g* d6 r, O# Q% w* N/ ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* |. S, ?+ c% r- Z/ Q& z0x00, 0xFF); /* configure the clock for transmitter */* d3 L% W$ g( o. Y6 }/ n- `1 A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 |9 U9 e* ~, F3 rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & m+ z0 c/ M6 f/ t" M" i+ w1 Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( ^ v0 M/ j5 \1 X/ w/ w+ q0x00, 0xFF);
* j( x, Q0 E) b* o( I) z1 `, t
0 L! \# C8 a0 z( k6 D/ g$ p9 |1 g' I/* Enable synchronization of RX and TX sections */
+ b9 F. s$ O4 m. i% U! v& q aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* C* Y) \( J9 o( @- o" TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, W6 J" L6 t# Z6 k+ g7 }* h8 n) dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 U0 M3 ? c. x: p8 z
** Set the serializers, Currently only one serializer is set as: `: y$ o. B% L! P/ f
** transmitter and one serializer as receiver.0 V4 |+ Y( s$ n6 F6 F( J+ \5 X
*/. H( j% J# ?6 \; a. P6 V- x4 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, P& j+ |1 h( O; U3 TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 a& G3 A: @- k9 V* }
** Configure the McASP pins ; A Q+ ~' b' W2 P4 o% o7 C
** Input - Frame Sync, Clock and Serializer Rx- v4 @8 z- h/ u* A
** Output - Serializer Tx is connected to the input of the codec
* e7 Y" _, Z. B# ~1 b; W) ?*/
+ C# F' g( { E! [& [% S* S9 OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. Y5 `+ _0 c4 T8 Q0 }' P# T! g5 o' mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 B! Q. H: F6 gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 c: A$ k8 o: U| MCASP_PIN_ACLKX! }% R& Q$ v# d
| MCASP_PIN_AHCLKX
( _( M$ m& {6 f# Z4 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! B2 g- R6 U9 L+ N& `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! y# a, {/ ~: E4 S0 n8 j9 e: z# Q| MCASP_TX_CLKFAIL
9 l; q' Z( L4 J. d2 p) R7 D1 ~| MCASP_TX_SYNCERROR/ s0 \! I! @- e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 K) k3 p& n6 O; @7 r, A
| MCASP_RX_CLKFAIL
: ~) w5 `% r. g- j| MCASP_RX_SYNCERROR + D6 g/ Y6 Q7 V( [/ J
| MCASP_RX_OVERRUN);
+ g2 d) I; G! s9 M4 J" b2 L( E} static void I2SDataTxRxActivate(void): w0 i! H4 i7 o/ E' m
{3 @7 b$ r/ Q& p) b! @
/* Start the clocks */5 O2 _, t% D! l+ R6 N5 J6 ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; \ t, T" d7 n2 J% a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. x# [+ z, ?2 w: V0 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& w6 u9 `. }7 C# @3 REDMA3_TRIG_MODE_EVENT);
1 ]+ Y/ B7 C7 E1 Y1 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / f. y. ]/ p- Q# t" `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( |: F' e, X6 e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* K3 Q, R) Z7 n# t8 ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 @% t: }8 I* ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: t6 ?- Q" |1 \, T! N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 H& z2 ]/ Q5 q6 iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 V+ Y; {; B, Y7 b}
' z0 D( `, }& p9 u* [* u* t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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