MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
0 c4 [; S$ j. c' P$ _2 x& `+ d+ iinput mcasp_ahclkx,
) V8 @: k: I$ Linput mcasp_aclkx,
input axr0,

- j& \+ {) L$ F0 voutput mcasp_afsr,
% X. ?7 C+ \+ K7 B. Coutput mcasp_ahclkr,
output mcasp_aclkr,
% a2 [  X, a: Y$ q+ Voutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

, i. {0 i4 V: }- V

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
4 j6 W2 ?! a/ }# j: k/ XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, D" |5 W) E% s, ?9 z; VMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 L: M% s9 [* i( ], D" v" ^9 oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' }+ u) O7 L% z; x  \6 _: aMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 K* D' S% j( D7 X; c) F& O5 SMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# u8 U* L' c& W; m& y+ C, TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# ]3 M- j6 x1 A  }% WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
  v* J) K) _; \2 N' O8 e7 }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 M- t# e2 o4 P! EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% B8 `% |2 s; P8 O7 h0x00, 0xFF);

/* configure the clock for transmitter */
$ Q9 T  z, [$ ?! ]" xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 _' b6 w3 h9 W0 H. H$ k1 uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 c, f) ?5 p- J8 q# L  HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
$ l% G  \4 x) y/ y5 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ Z$ B% x( b+ \' l/ S# Q; }/ o% iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
3 b" L# {+ z- x& F** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
/ m4 ~4 r; [! V1 ~*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
6 V- Y5 F/ H4 A7 [8 e, ~( {** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
) z0 l  i* h5 V9 c** Output - Serializer Tx is connected to the input of the codec
$ M# t. M2 }) f# r/ t- U# Z/ n( Z*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' ^' o; n4 Y3 R' w4 h- t( x. JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) G5 H& U& M) r+ D) f| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
& K* w; G' i, L/ I4 R1 ^# k4 gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( Z7 ~  [5 r9 }$ K| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
" w( @+ W: i' c* v+ ?6 g5 }9 o| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
/ f- W6 m0 O3 y- \9 h0 u% M, H9 t: E2 l| MCASP_RX_OVERRUN);
& E# h9 |) Y4 T; ~9 Q}

static void I2SDataTxRxActivate(void)
/ L8 Z2 N) v: j# e6 U' k{
: G+ Y( S; F! o8 u+ F- T/* Start the clocks */
: _$ K, U# Q! s' o/ b8 H8 ?! uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 x9 k' L; ~( L7 M5 U, C$ PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
. u# R; P, z8 u3 B8 ^, `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
0 Q* H; s& V, s- ^; b0 m' u# aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
/ w( l, r: ~( n' Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 A7 b! C, C8 X; C, ^}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

/ @' c1 u" G2 d8 x