|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% s8 m) c# P9 i* ]) C8 E
input mcasp_ahclkx," Y$ k8 z7 y, ]" v
input mcasp_aclkx,
, _5 M0 F( Q4 V7 v: winput axr0,
' }# u( D/ q! l8 B/ z6 m+ \: u$ g
5 w' v3 z; v" Qoutput mcasp_afsr,7 a3 b: _2 v' a9 X' S5 ~. m v
output mcasp_ahclkr,
' a" X' Y0 ?! M. A5 z0 q3 ~1 ?output mcasp_aclkr,
0 c9 y, \9 k+ c7 l K, ?0 Goutput axr1,
$ X# D( ?/ e/ B5 f. X1 g- Q7 J assign mcasp_afsr = mcasp_afsx;7 e6 U. F! R- K) J& l
assign mcasp_aclkr = mcasp_aclkx;
& Q4 k5 m" g/ l4 P+ C8 lassign mcasp_ahclkr = mcasp_ahclkx;8 q7 x$ V$ P$ G* P7 X
assign axr1 = axr0; 5 [" m) x4 C3 K# i: A
; g8 f& F3 i* r: ~5 J+ G) l, C5 ^& M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. m* p, t& @+ V/ i, I0 ?; @2 a# cstatic void McASPI2SConfigure(void)
$ ]0 ]) ~0 R c6 D& n{
# H! y% E* c5 e; k1 A& a. OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- x% Z: |9 Q r8 J) J9 GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: ]& ^7 R# |7 k7 v4 k& SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# X6 g; K( S, y ^# V9 \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! H' T1 Y1 \1 I" L- ]( k5 u& d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 g2 D' i7 B% ^0 vMCASP_RX_MODE_DMA);' V0 |/ b" v0 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ }! ^ T& u, R6 ~6 j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% l# g3 w8 T/ g& B- J* U% oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( j3 _! X x: d( U: wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 y2 o6 J- b+ ?9 J" C; A: o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 c) I; h: q: ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ J: t% q4 g4 e! \: dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. `- L$ X. l; e/ s7 n! ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 P6 {8 t/ ?+ i. j4 I4 y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" [# R: C. }/ k+ l8 Y# E0x00, 0xFF); /* configure the clock for transmitter */
0 w4 Z. C( H- \' g B/ g% hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); O) K' L' v) o2 V' T# U8 s) f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! d3 [0 n3 ^0 @) \2 N& B c- XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 X" C/ s1 i$ j2 G0x00, 0xFF);" v( Z) f" Q8 @& L
) F' z! o, f' _) s0 h/* Enable synchronization of RX and TX sections */ * H1 }& i( ~& z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 x: V9 m2 e3 E# x) dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' L$ u9 j3 i9 Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) `! l5 H9 T F/ Z$ v; \** Set the serializers, Currently only one serializer is set as( R; m2 X+ ^& Y7 X4 s) i+ r! f3 {
** transmitter and one serializer as receiver.7 d6 Y+ ^$ m5 A$ ]
*/
+ r; d) G1 P+ w& SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 d8 p8 z1 X% }; x* h' TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 A/ q1 Z& C: k$ b, ~** Configure the McASP pins ; o8 a. ^/ R% A7 l, T8 y& Y
** Input - Frame Sync, Clock and Serializer Rx9 P. g; m! s0 e$ E8 _3 v: [& U
** Output - Serializer Tx is connected to the input of the codec
- d7 \9 b. o4 x8 \- I1 T*// S; K' U$ u5 ?. ~6 M E$ T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 ?: `& e* e5 ] C, {* GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 B! G2 w/ F+ v) e( {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- D# t& w s1 T$ o
| MCASP_PIN_ACLKX2 J, A8 \" T: K
| MCASP_PIN_AHCLKX y6 K+ @% u0 u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! ?* ]) o/ b( v7 E/ z. i; @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . {- Q n( W8 y6 ~% ^& }# U
| MCASP_TX_CLKFAIL , k! c# N9 I! _4 B0 @
| MCASP_TX_SYNCERROR: M9 l; P6 d: Q5 `# Y" G2 L8 B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # D6 M) M% X: ~ z2 ^5 Y
| MCASP_RX_CLKFAIL
7 n5 `; i! D; @' K3 |4 E| MCASP_RX_SYNCERROR
) S! Y( n/ ?2 z6 v5 A' u| MCASP_RX_OVERRUN);/ Q+ c( Q% A( d: [0 T
} static void I2SDataTxRxActivate(void)
j2 o0 J+ e) ~2 d1 w, k{) M; N" l* i1 Z5 K, z
/* Start the clocks */
1 `: t$ u+ ^1 X, C Q1 Q/ W* q; |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 A: u. i8 _+ cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! O: {# q* m8 h- h6 E2 @5 L4 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ f& E* _0 Q: ^
EDMA3_TRIG_MODE_EVENT);, i: P Z @. G* O9 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 E3 A6 s& I4 [: ^) M8 h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ l0 b! S. |3 K$ d8 j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- c l v, c8 ]5 S e0 w& u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 }4 O! F, \4 P3 g( `; uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: ~7 G+ f/ P. B, H1 h5 `; @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& Y7 }9 R9 ?1 Q' F3 ]: {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ t8 @* a6 R. c
} 7 F0 F: n! g$ N" u' C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( X6 ~; S% |. E5 }" X
|