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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 F7 ^! \) G2 r- E8 `( vinput mcasp_ahclkx,
6 z& ]3 `0 F" N2 A: c7 h. Ainput mcasp_aclkx,
5 }$ l6 ~9 [4 W- Q! ~5 ninput axr0,
' T/ ~7 w: ^0 j) H! l% E/ u6 }4 E. K* ?/ I: b
output mcasp_afsr,9 M: q7 D6 m8 V6 q% {3 z3 h* p
output mcasp_ahclkr,% e) a) L2 F" W+ X. d
output mcasp_aclkr,
7 m8 T( u6 F) P" \2 m% o+ eoutput axr1,+ P/ Y7 m/ X, |1 _
assign mcasp_afsr = mcasp_afsx;
" z( ~' O% X( Massign mcasp_aclkr = mcasp_aclkx;- j% @) I- ^0 l4 j0 O" M3 R' G- `
assign mcasp_ahclkr = mcasp_ahclkx;
( s- h/ G r* G1 nassign axr1 = axr0;
. Y6 G) n2 j' T" `9 ]* m
6 E2 s& W T: c N" m# X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! f" D7 ]8 `, w3 v/ r% O. K; M
static void McASPI2SConfigure(void)
0 e2 c( b; v( b: H$ E- z{: Q- G0 @7 Q) \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* e+ i4 d/ q( B0 R9 N" \8 n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. S* `& `9 h. C0 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" w3 z8 P3 z* |0 D2 W( Q6 IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* N7 V3 j0 v$ D7 D; j. ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' a ^7 \3 o; I" Z* ?0 }) E( q1 F
MCASP_RX_MODE_DMA);6 p' ?" d. J5 l* i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 g2 q& w/ @7 |, j# CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ s; e# z" e, S( d! x& x2 M8 D; [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 Y, f7 X3 ~; v: u. HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# F% a, t0 K( Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# u" A' ]4 y/ D( |0 \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 Z' f$ b) K4 u2 E+ ~* d( @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 ~; _6 h( Q- a0 B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 S( \. o: t; P, \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 J: f3 Z4 m+ E9 |/ ~# E
0x00, 0xFF); /* configure the clock for transmitter */9 e/ g) U O6 [/ T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ X. I% w: t" ~; @4 L1 i9 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( {# P& L5 x. W7 b$ C5 ~0 TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 Y: s7 b0 X" ^2 [1 @, H
0x00, 0xFF);1 R; ] P; v5 J/ v# x9 B) _0 r
D( R# R6 u- z' f. `/* Enable synchronization of RX and TX sections */ ; Q4 T, F& ^, U5 j, Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 z6 b+ `. l8 k* z5 \* C( V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; X Z8 C5 a; p; }& C& N$ R& M* \- r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 c4 r: f) F( J
** Set the serializers, Currently only one serializer is set as
4 C& x- @+ y r* I7 r' x. c** transmitter and one serializer as receiver.. n7 Q. V3 j- W6 Q
*/
& G: g, s( b5 }# M5 c, QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# R2 Z7 ^9 ]- t! Y, a: U! }5 T l6 qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 j: b w) v1 L" \9 Y% H5 f** Configure the McASP pins , P( X5 I. x) b3 T3 i
** Input - Frame Sync, Clock and Serializer Rx
1 Q3 P: _0 e4 ?; q** Output - Serializer Tx is connected to the input of the codec ; M! y Y- N" j
*/
7 u/ \; \, J8 w; L; bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, v; q/ q% b6 q6 q% RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* {" ~+ v5 ^3 G) r7 I* m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) n. z: z2 O' _/ C
| MCASP_PIN_ACLKX
4 X7 r/ z6 J' {, i8 {| MCASP_PIN_AHCLKX9 v% P. U/ a* w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% Y; l. ?' U' W X/ SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- Q, A& `' V- A" G1 _2 L, @ ?1 L| MCASP_TX_CLKFAIL 2 m/ b+ t" M i$ d9 v# s
| MCASP_TX_SYNCERROR% ]3 P; T; \6 s* a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 f( M: K: U) G$ k( P| MCASP_RX_CLKFAIL
" B2 ?: U8 R) h" b5 i) V; H7 A| MCASP_RX_SYNCERROR 8 e: q3 }) ~% t' M# D- u
| MCASP_RX_OVERRUN);
0 G+ s- r X# e6 Z( r5 }} static void I2SDataTxRxActivate(void)
`2 m1 [! X" k) j{
: D! Y2 e' q, f0 ^( k9 Z; m/* Start the clocks */, c& d- ?/ N2 A! H% h4 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! ?8 w( ~# _0 l! r, YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. P: Z2 H1 v' q) p* r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 ~+ c- t2 m) {+ o, I+ HEDMA3_TRIG_MODE_EVENT);9 t6 C) B5 @* P7 {% O9 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, P: e( B6 o3 `. |" N* ~: O e0 j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* o3 K6 I; U2 T5 J5 Y- v) LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- o: @9 U7 h# R* l' W/ ?3 IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) P4 V5 `3 t/ Z% N) K! y3 H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 ~& h8 `8 C: ^) Y; AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 j) Y" v( C0 z1 RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; N' _8 o- n% W# s
}
9 Q& Q% c7 j6 H& E- y J# F, v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 T3 _4 v7 C, E: P. G% ]. G
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