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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 b l; r% H2 t- y/ Y9 Tinput mcasp_ahclkx,' Q+ d+ I5 j+ w' H& U0 c1 T
input mcasp_aclkx,% B! P9 t- C5 V1 T/ i+ }
input axr0,8 ]; A; @0 I# X% ^$ S2 Q
' [7 m% A3 }9 V/ Koutput mcasp_afsr,
1 m+ K `. q3 p0 Youtput mcasp_ahclkr,$ z1 s% T1 T; F8 U$ q6 s* U
output mcasp_aclkr,
$ ?: t) X' ~' Y) E* x2 k- _4 |output axr1,& l9 L' p! o7 W% M. k( @
assign mcasp_afsr = mcasp_afsx;/ b T, i6 d& j: [$ d: r2 P$ p
assign mcasp_aclkr = mcasp_aclkx;
& p+ p9 k4 z" ?( j; R# A' lassign mcasp_ahclkr = mcasp_ahclkx; W7 C1 Q% F$ J5 R. |: S+ w
assign axr1 = axr0; ! n* J/ |$ x: d3 V
7 E" e& u: `3 f- `$ T) [' ^) k( n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# k' M; A' H7 o; hstatic void McASPI2SConfigure(void)8 y8 r M" R, n- m, O6 o! N$ r
{
9 |8 z) L/ W( Z" a) rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 c2 q& i8 U2 |: I& @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% u( G+ J, l2 K" {' C; SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); i: R6 J& N! Z% c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" a! x g$ M0 a% k6 U4 z; rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 F& f* y0 v" z" K
MCASP_RX_MODE_DMA);
+ ]; O: Y: H* W& Y7 {* G/ DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 A( o( h" N9 m, ]1 CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( X2 E! R' _" |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 \; o5 q( @+ G3 _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- K; x( V: h W& HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ ~ ~" r9 a0 v i; @% Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
{/ H) [9 C8 {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' m+ D* G" q2 ], a9 b6 D {, qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) a' F) _; R. R+ ?4 _9 F! X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 M) k! Y# H& v0x00, 0xFF); /* configure the clock for transmitter */! |% v" B* J2 z: q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; q/ O! y, d2 _! q6 BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 V+ \7 k2 }% f7 B5 C0 q2 ^! yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
g; S: r+ U) J+ O0 D# @( }0x00, 0xFF);
+ x! c. r5 e$ v9 h6 M1 h9 f" u( c8 `" E3 N6 o* a) r) @& Q \2 F
/* Enable synchronization of RX and TX sections */
% j C+ C+ H8 f# X rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 e, U1 @' O$ b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% ?& ^; r3 N% F0 JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 y- H! y' b1 `- G; E: G
** Set the serializers, Currently only one serializer is set as
: ~& J$ |4 l, b% T6 \- R** transmitter and one serializer as receiver." }& t8 z; Z7 ]
*/
. Q: U2 H, a6 X- a* F/ R$ K; ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% w" o% N1 g) S1 E; \1 [. {0 AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% n+ E5 n. `" i
** Configure the McASP pins
2 h9 K0 ~ _: g+ n& f2 \** Input - Frame Sync, Clock and Serializer Rx, n4 ^+ I( { C+ ]) L
** Output - Serializer Tx is connected to the input of the codec 6 I- o& S0 C9 w# O7 S. ~
*/
& {; k, c# k! H/ V" ?- `8 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* n+ X% z+ z1 i- y' ]/ L f* A, d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% ~) Q( R; o1 K* u1 S* w1 s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* `) _$ \: p! n2 N9 z| MCASP_PIN_ACLKX
6 h9 S7 {( _% u9 H2 r3 l| MCASP_PIN_AHCLKX4 d/ y+ m8 O" |: }& n8 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, ~! }: |7 ?" c6 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ `5 t# `' @, x; f, @| MCASP_TX_CLKFAIL
[6 o' b" f" ^( _0 i1 ?: K| MCASP_TX_SYNCERROR# A7 _! R* Z& G* m3 Z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 g$ D$ j1 U2 [7 Q) X8 k- v| MCASP_RX_CLKFAIL
, P$ i/ y, N! k s% L: {$ n| MCASP_RX_SYNCERROR # L S* e3 q9 q+ k
| MCASP_RX_OVERRUN);
( ~# v5 H0 Q# y8 T6 |} static void I2SDataTxRxActivate(void)
( [0 H1 x2 q, M4 p5 z! j" L{" ?' B( \5 I1 S4 O8 u
/* Start the clocks */+ S4 _1 h# p7 J: o9 N) F+ ^. _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) b) l8 C% t2 s3 J g7 w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; W5 L# x/ v3 L. V# A# XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 U+ e% x3 _, I
EDMA3_TRIG_MODE_EVENT);, a; K; Q5 t' L5 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 R2 s" `4 g% ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// @- y% K/ w% N$ }2 ^( m* t8 |, P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 E2 u' ^0 Z$ `- @' `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 l5 G, b, g F- U/ A, j6 S% Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 @8 j. S% p7 y0 y s" @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 U3 \ `4 R2 G3 X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" K3 M, h. C2 j3 @/ L7 t( r
} , o N, Z `- G( _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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