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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, E7 M* z- Y3 y9 G* iinput mcasp_ahclkx,1 V9 e' A d- P9 [* K" v G
input mcasp_aclkx,
* v0 [& R: g. @! Z, ?% k1 @- J* \8 z5 @ @input axr0,
\; }; i0 S% ?. ?1 l# Y7 n3 W- G; \+ g5 X g
output mcasp_afsr,
$ m$ k4 s: {6 w8 o. _/ X+ H9 I5 goutput mcasp_ahclkr,
8 i/ q* c4 R g# Q" uoutput mcasp_aclkr,
. @+ ]; G7 e6 V2 i5 Q- u7 G1 ^0 x8 X# Moutput axr1,, J1 C- b3 P; x- D( K" T0 x/ P- d9 [
assign mcasp_afsr = mcasp_afsx;4 s0 _4 }/ j" O# }% a
assign mcasp_aclkr = mcasp_aclkx;
* @6 w0 X$ e8 b- x L; j; @assign mcasp_ahclkr = mcasp_ahclkx;
$ e6 f H) v/ w; Vassign axr1 = axr0; - o. H$ b! |6 A% S6 K
) e& Y* M+ g& o2 L+ e7 G6 B9 c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 ~$ V3 ]! ?; ^4 Y7 O
static void McASPI2SConfigure(void). g: {1 r' r" O2 H: M6 R/ l
{+ V" U: }7 D, p* `$ L. C' T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; A0 F$ y$ `$ ~) u; c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% N' ?+ Q& Q J, HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 K5 r" L& a F, M. Y B9 h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! B' ~7 k+ ]* \8 g# JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 N" w9 \3 P5 D' T& K2 R3 JMCASP_RX_MODE_DMA);
4 N' X, C- m( {! N YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 o G. Z' ~3 Q2 p; M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 ?, {! [3 m9 G7 A8 L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 ?- `0 l9 O8 o& r; l+ GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 ^3 d6 V( R% ]7 ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; j# e r) a3 }& m, J$ B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 G1 |* [( N/ \: c$ Q" }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); B& L. f7 W1 L- l8 C4 t+ Y6 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 J/ s% G. X5 e! B0 X# I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 s" p3 v" h0 s+ o' {( N9 G0x00, 0xFF); /* configure the clock for transmitter *// t/ y* k$ u B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 {$ p- |- e1 e d0 a$ DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; A W1 ^# D, DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: X% I$ l" F9 o R' T; d( Q* G
0x00, 0xFF);
) G( p- j; t+ v: D, W7 T: V, E c; Y, ^
/* Enable synchronization of RX and TX sections */ + b9 v7 F' }& b6 Y; `- c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ s7 H& o/ ?5 G7 L% o. O+ O/ ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ d7 l# g; _( F; ]% K* ]* C' s/ q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 d8 G9 m8 ]1 o. o& w$ g1 N** Set the serializers, Currently only one serializer is set as
) E6 v6 p4 t8 z9 a4 r7 d** transmitter and one serializer as receiver.2 P! d# o" d7 j( d7 L# q$ P
*/4 U$ |4 i4 l+ M5 k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. w0 N \/ r6 `: i- m9 ~9 U5 M: J+ GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, H( e, j7 A- N( L# T: w** Configure the McASP pins 1 ~5 D' g" B8 ^8 L1 E8 [! S
** Input - Frame Sync, Clock and Serializer Rx
' I; ~' {2 t0 x& Y* W4 x' P** Output - Serializer Tx is connected to the input of the codec # a2 f: R1 k' r( X
*/
2 X% z' |% B5 w+ @7 _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ y" }9 G) k7 G# w Z8 ^! c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 e$ ^# K/ e9 g8 jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ [' F+ U4 G2 z$ n- @: q3 V! D
| MCASP_PIN_ACLKX
: Y: t" X+ }+ l| MCASP_PIN_AHCLKX
7 {8 k. Z7 I9 P! O; G/ Z% W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! |2 s: N7 M+ K: E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . }! t( m& S* E% y' m
| MCASP_TX_CLKFAIL
* _6 P ^8 h, }; i| MCASP_TX_SYNCERROR
4 a8 S* r- } f) e9 N) `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 n0 K4 ^/ v1 ~( ?! v/ J
| MCASP_RX_CLKFAIL
* E3 c8 u- h8 H| MCASP_RX_SYNCERROR
- F3 N; T5 P" S1 U6 @+ j8 `| MCASP_RX_OVERRUN);
]* T& d! A" p6 ?5 O3 d} static void I2SDataTxRxActivate(void)
6 o1 u( L7 T! K{
& Z' U+ f. b L; g, n/* Start the clocks */6 c0 p3 t2 i/ O! a m. B/ O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" A! M, V3 l) f4 y% v; wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 {+ d8 K2 ]9 W' B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) }: y7 J! W) C2 T$ V. J
EDMA3_TRIG_MODE_EVENT);, f. I2 H4 P) w6 {: m! o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- g3 }; C" v! H$ r! y( A, C4 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) V' }, b9 l8 m/ m2 I L" rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 D- R( ~) P* y8 l2 U$ B) G3 p, r1 dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 u* K5 S2 m2 h% v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 }! l' u1 v. w4 a9 o9 D; x& F3 T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% s+ m% c# z+ K2 ^: m) M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- Y& |( n: ]! B! x. [- E* }& J* l
}
! N: z* S1 R7 Z" }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 g7 O P$ n: w) n% t
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