|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* t; ]$ \, V4 }6 X# i. I3 T+ |7 \
input mcasp_ahclkx,# m, z* z- M) h! R
input mcasp_aclkx,
2 O; ?1 D/ B( U5 y$ @& _5 V' zinput axr0,+ m) L- |- c7 ~' {
- L0 P# n( A) o6 U
output mcasp_afsr,% Z7 _! M% n9 [8 o; c0 C
output mcasp_ahclkr,. s1 ~9 _2 _9 A
output mcasp_aclkr,
8 \# c, C m- a) xoutput axr1,- i2 {4 ^' A- G4 `5 e
assign mcasp_afsr = mcasp_afsx;
: N8 B4 W- M+ M& Gassign mcasp_aclkr = mcasp_aclkx;8 O$ I- m. \6 P+ r& u' ]) m: f! b
assign mcasp_ahclkr = mcasp_ahclkx;
) R' l. H2 E6 uassign axr1 = axr0;
. G1 D: X% Q: L+ t, u2 E& |
# ^6 T- H0 |7 w6 g& _$ K1 b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / n* O, V+ t \9 W6 m L
static void McASPI2SConfigure(void); W3 w0 |5 A( t6 v j8 ^
{
' i8 l( L) {$ M1 w/ S& nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ z' h6 J0 k/ V: q! wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 O( C- F/ f" d/ O$ r3 d& e& \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 w- _2 M% b5 _: r1 H- D3 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 U9 v4 Z" ~7 {
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% n0 \% U; B! [MCASP_RX_MODE_DMA);
, \9 [+ C+ y+ `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, ~" ?3 [; Z! L. N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. V1 s% t' _9 u2 _! Z$ {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, g( T2 b; a$ XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 Q* w& S1 Y$ w+ }5 m, N$ YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 E7 R6 P+ i3 ?7 y; c( vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 c7 B9 V0 D$ j5 i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) h- r% _- O4 V+ `9 a7 L7 b+ L' P2 |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 V2 Q$ [! c& u# mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 j6 b8 {- ]# [& b0x00, 0xFF); /* configure the clock for transmitter */8 `5 L; Z7 X2 h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# X9 s) }6 g/ U. Q* W+ a# uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 Y* _$ H' |: h6 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" V! D5 l* \! p& ] g" x5 w# \0x00, 0xFF);+ T( Q; S" U% ?
6 K) A0 a3 W8 R- y) \+ Z/* Enable synchronization of RX and TX sections */
6 {) I7 p* m/ QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 c+ ^. J2 B- q9 Q+ u( V. E vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 D4 R1 i# z! H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 x% x1 o! f$ F0 }0 p' e) [$ A
** Set the serializers, Currently only one serializer is set as9 h) c8 p# h! t6 t
** transmitter and one serializer as receiver./ Z/ J' s+ t$ x( w2 [6 \% i! e
*/
& W9 O8 e& b+ @+ V" ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# A1 _" N6 c) y- U/ uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, |, J# I* n! A$ \/ E
** Configure the McASP pins / U; L) L1 b. T' N; O6 d
** Input - Frame Sync, Clock and Serializer Rx
w9 b0 |; ?) y7 _** Output - Serializer Tx is connected to the input of the codec 2 F. `. s$ {! Z' X: `
*/! j2 a1 N+ p5 N4 b* K' g' b* M* s' w$ U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) G* j1 {! F8 Q% ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" J+ S$ X* ^3 ^) b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, K- m' B2 R) U% Q+ v| MCASP_PIN_ACLKX" C; ^" ~' f6 G5 Q# U. W+ X
| MCASP_PIN_AHCLKX' i; O& N4 `) j& N9 K% ?3 c$ p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 A; |$ l7 k1 g+ f& uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ o/ h! B" q _: Q" h% [| MCASP_TX_CLKFAIL ; ?( {" l, m+ F
| MCASP_TX_SYNCERROR
; ^6 o1 b1 ~% K: b; z7 h/ G/ c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% M& b& Z+ }; Q2 n, I| MCASP_RX_CLKFAIL, n3 O' @- {. I( w. g' P0 v2 _ o
| MCASP_RX_SYNCERROR ) {$ f9 o# B P
| MCASP_RX_OVERRUN);
' {) E5 P/ Q! r} static void I2SDataTxRxActivate(void)
, m& E; I0 ^0 i- p3 N+ E{
( C4 O0 p7 v( h t4 `8 C$ ]/* Start the clocks */
- r/ Y# h( k, v0 m8 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& ^3 b) a- X, }+ Q& oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 U/ D. |8 y* L$ |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# f6 |. ]0 @5 A5 F& d/ x
EDMA3_TRIG_MODE_EVENT);
L4 b5 q0 ]+ ?+ \0 s3 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 @5 A% Y: `/ H; s% q8 }* QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& U5 P0 X* y9 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 v8 u0 d! q6 T: N0 ~7 e; c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 i; N9 ?0 X4 h) l5 w* k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* A8 z6 V6 T4 JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% |0 B; z% w: gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& n1 [% u4 S8 L+ `
} ( k: W/ ]( ?6 x% w' B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
, L. e+ n% |2 z. M! H2 L |