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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ g8 f" a$ U5 X, o& c% p
input mcasp_ahclkx,
; h6 [1 I5 T5 |6 k2 w8 Dinput mcasp_aclkx,
/ X- I* C! v1 {# q4 l' V3 M2 Winput axr0,
% v% j# m! w- ?. |3 t9 E4 m9 U$ s7 y: X* G4 S0 @
output mcasp_afsr,
! C+ W$ a# r4 l4 l; y1 E8 Uoutput mcasp_ahclkr,' B0 n* K) q, ]1 m
output mcasp_aclkr,4 b; g( k: ~% V! D2 e# u+ u0 j
output axr1,2 `5 o' a% F1 r! A
assign mcasp_afsr = mcasp_afsx;
4 U' m7 p( L6 n: r/ kassign mcasp_aclkr = mcasp_aclkx;
/ o5 |4 c' r* X! ^assign mcasp_ahclkr = mcasp_ahclkx;
7 I" s% _1 n+ d3 k. i3 aassign axr1 = axr0; . O9 C: x- U0 g! Z& P' U
8 n; u3 ]! \- B/ A2 G4 h6 ?2 w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! L5 K4 r- e2 ~
static void McASPI2SConfigure(void)
% k' l( D# h6 h{
4 P1 Z. t" C6 F1 X. k! W+ _McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 q( | \# Q8 |0 `& c: i, T, M0 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ \0 E! ]% Y+ _, S& t5 aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" d, X3 l) a1 O) i) B# W- YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 Q+ A+ s$ [6 x6 N; F+ @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 ^4 p0 I, v7 m3 M( _0 a! I/ sMCASP_RX_MODE_DMA);: S, ?+ h- D j/ W' x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ f& Z; Z4 k) S$ \$ {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! i8 B6 e) `% A2 M! ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + n4 C. d8 K9 u" @' t+ Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; X% \5 s) _: L. v8 Q2 d$ n7 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 u. Q$ q4 V, W* d/ H @) M* jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 K) W( D T$ e) j- J) GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 j, c9 F- {$ ?' ?2 @1 zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 @ `/ P( \! @! y4 d* gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% P! T/ S' e( F( g# r$ v0x00, 0xFF); /* configure the clock for transmitter */
* t3 q- K8 s* m5 c' n1 S" lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 h4 d2 q5 |% X. d& s) x2 t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 c- G, y# e7 O# h& k0 t9 _5 w$ uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ m" W/ H' y. s" R
0x00, 0xFF);
) k: K9 y, _5 {5 i% U' V8 V; {& A- U% P: ^' R! v
/* Enable synchronization of RX and TX sections */
8 f; x3 G1 D+ Y2 T. c, cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 y$ L5 z* _: {6 E$ XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); G9 v7 P% y5 l) A- |1 B; K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 X' C6 ]1 o9 @) i** Set the serializers, Currently only one serializer is set as
5 [, u$ T0 z! W; u** transmitter and one serializer as receiver.
' q; S) [0 I, v1 }- {*/. q. S# e: r2 U$ t% }4 z, G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 ^: h& ?. P, o4 k0 A$ BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% `1 o2 C* Z8 G** Configure the McASP pins 7 H) N4 o6 x# @/ z3 V' S- y
** Input - Frame Sync, Clock and Serializer Rx9 d0 V9 S1 u, q' i7 U/ g" F
** Output - Serializer Tx is connected to the input of the codec
4 u, w; T, G, I. h8 |. H1 P2 }*/6 Y9 d+ Y7 h0 D0 D! T4 a ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! o8 y o+ ]/ d/ G: V0 M: tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ \2 ?7 a: [3 c" x' EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! s r8 K; r4 k0 v9 `1 n5 V) P
| MCASP_PIN_ACLKX
9 g; \( l2 |* I. T' {1 Q0 h q| MCASP_PIN_AHCLKX& J a( \( M/ C# W. f. }1 {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
A" F8 _) n) j- F9 v& g5 eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% S$ c' s7 n: |! P8 w- `| MCASP_TX_CLKFAIL " N) N0 V) ?/ m* [! E3 j2 x
| MCASP_TX_SYNCERROR, V0 ^/ q6 u/ B7 a9 h$ l( @* ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 t$ S' i$ l9 B2 }9 }6 a| MCASP_RX_CLKFAIL
; z z0 y- O) s0 W9 h8 b2 n| MCASP_RX_SYNCERROR
5 X# _4 W4 _0 {% Y/ ]| MCASP_RX_OVERRUN);
% o2 \4 z0 r8 s, o} static void I2SDataTxRxActivate(void)
1 O7 c& y$ a( \- f{. o( l( |5 o9 F4 b. x3 V# Z
/* Start the clocks */1 m. W; o) G9 c3 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& \( U" X1 K0 _9 Q. [: G/ }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) A9 Q* l3 }: a$ M$ ?; P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, z3 F) \ }" z
EDMA3_TRIG_MODE_EVENT); A) x$ }* A/ u! O! b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : z" L; `0 l* ^; u; J) t$ u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# d t" n" Z: g5 T3 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 r, G/ W- B1 G$ `/ YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# M0 q/ ~+ s" _6 L" h6 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# h* p9 ~/ d+ {/ n) Y- d1 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) _7 O! j" o" p' p6 ~8 m2 ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 q! G+ x$ d0 l& t
} 7 m. b/ M- D, P; ~6 [) P, U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 _. s% a( L' w/ c4 \7 ?! H/ _/ y4 S
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