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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" `5 M( v1 \9 g8 Sinput mcasp_ahclkx,
$ a6 I2 d' L) V0 r }* J! Cinput mcasp_aclkx,$ Q8 N2 Q/ a M8 @1 C& |1 e b
input axr0,
0 J! g+ o7 r+ [' V2 C7 t; C9 {0 w
0 }- u: V4 L9 b6 ]. `+ [output mcasp_afsr,
5 j, N) C; ^' ?output mcasp_ahclkr,
+ _- N5 L7 V' E1 Joutput mcasp_aclkr,, l# f& y) v4 Z9 f6 q
output axr1,
* u# E0 |# X: w$ m5 ~5 f' A4 C assign mcasp_afsr = mcasp_afsx;. z: a- x" O) Z0 G( p: e
assign mcasp_aclkr = mcasp_aclkx;
2 E ?. Q0 a8 Z3 Y# u4 rassign mcasp_ahclkr = mcasp_ahclkx;$ d1 N' B9 G; h* ~0 N$ K$ K1 L
assign axr1 = axr0;
N' X! X( I; Z0 Z) t: T
3 V0 N4 |4 P. L- W0 W- Z9 F( e6 R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, U2 G- o. h$ I5 Nstatic void McASPI2SConfigure(void)$ W& T5 G; k3 J6 ~/ e
{
: H K0 c9 ^( C, j: S: KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 l2 q- y- k( e' s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' V( K7 B/ u6 y f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 d# k6 W5 V- e6 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# A7 |5 B; c2 K% F7 f' y X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ M0 ~8 S' b4 U ]) [MCASP_RX_MODE_DMA);
- ^# I( m% N5 B) F& OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 a# C& O: y" z, n! u" |% R2 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// g* y; G' N* |4 R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 D$ J' N G2 d: p) \7 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 a& l: f _. J" a% B1 f9 x, vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( n- z4 x/ _! L+ O' g) GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 ^4 Z8 e' N5 O7 @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. J$ O' e! b0 n0 [, T9 M0 x( ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ h9 G+ d* g2 _4 w! L# d- @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. v% H K* O- ?' m) A
0x00, 0xFF); /* configure the clock for transmitter */, j! W" w/ u. s- N+ f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) P& u" t- c* J. q. x$ ]: u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 U6 a+ X1 d" _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) j/ L; W* j2 {! |, b* s( H; E0x00, 0xFF);% [$ J% s3 o) f6 s
0 M' o3 a" n0 ^9 g
/* Enable synchronization of RX and TX sections */
& `4 L) h1 ^: V6 y2 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* P+ p. i! Y8 d& Q) b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' R* R! b5 W7 Z. p0 r& HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# O# a4 _9 P% h, H* A
** Set the serializers, Currently only one serializer is set as" b; g1 Q9 @1 k" `' i1 Y
** transmitter and one serializer as receiver.
8 T% J0 s2 n2 h) x*/
8 t, o% Q$ F/ y! U, W& k& _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 w4 @, q( K8 A) E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 `8 V1 `# l; O- l** Configure the McASP pins
1 Z$ {7 X& B7 d: v* @4 r** Input - Frame Sync, Clock and Serializer Rx) z5 u% r; \& E( @9 R3 i) J" G
** Output - Serializer Tx is connected to the input of the codec
( X2 u" U# L9 s" [6 Z) ^*/
' `, ]; v) g/ l9 ]2 L- H7 xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 r1 J/ H/ e# V9 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 r! V8 t; Y" I! Z4 u9 i2 t* @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 B+ F6 [4 n& s2 `$ || MCASP_PIN_ACLKX
3 Z7 |' d- S/ |7 K5 t| MCASP_PIN_AHCLKX
7 s8 @# Q$ i' A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" U& [# D9 w8 }2 {. u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' t9 L. M8 b* Z7 P, ]) {| MCASP_TX_CLKFAIL
5 E% H1 d7 N0 g5 _" F: i| MCASP_TX_SYNCERROR
. w5 `$ b; c! x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 N$ r! b+ v5 p. z% c$ N| MCASP_RX_CLKFAIL
3 K6 t3 _: ~3 Y9 b- ^4 v| MCASP_RX_SYNCERROR 7 @8 e% d6 k0 t" X/ J" w, [% W
| MCASP_RX_OVERRUN);
0 i& r$ ^5 C2 w' p L. h} static void I2SDataTxRxActivate(void)3 Z. B$ d1 Y( ~3 a" n o0 w0 c
{/ ~7 h: A( a7 U' e+ A
/* Start the clocks */
* w5 T; Q1 `/ i- F4 a& _4 E6 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; K/ M, v2 @; j9 x1 v. p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* S4 n3 C2 x* E9 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ S3 ~, ~' H7 H% C/ EEDMA3_TRIG_MODE_EVENT);
" H9 @2 j( O4 {8 @& Q4 z) }: AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 X7 ~, h9 ^4 H# `2 s8 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
u J" R- w$ S1 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ |, u; V1 `8 x$ y5 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 F8 s% t. N0 k: x+ ?9 ?' u: iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; H3 z L( H+ K- h* EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( U+ q! U1 i2 y5 t" z( Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; ^) H9 h+ v% @# u& f
} 1 K/ ]$ Y9 t7 A' b/ f+ }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * R r! E4 u" Q) K1 I; S
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