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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# X0 V4 @+ j& N1 r1 n* ]! Qinput mcasp_ahclkx,
1 p9 W7 u% d# E6 [; \1 cinput mcasp_aclkx,9 Q7 p- Q" G m: E: F/ D
input axr0,
/ s3 F0 k% a6 e
* h3 t+ @! _$ t# ~/ \+ ^: Ioutput mcasp_afsr,
, F3 b( |# ]) T: Ooutput mcasp_ahclkr,
) T6 U) E4 M8 e1 s0 d: Woutput mcasp_aclkr, C% w8 X' V4 ?
output axr1, J' y/ p7 i, b" z
assign mcasp_afsr = mcasp_afsx;
9 M5 Q( h8 w, f4 v) @/ h1 Eassign mcasp_aclkr = mcasp_aclkx;$ G/ w( M; C$ \ A
assign mcasp_ahclkr = mcasp_ahclkx;
5 f. ~) l% o4 z W5 T. Lassign axr1 = axr0; ( p+ P: u* f: |4 N' Y4 R5 _8 k
4 Z% B4 P4 ?- ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! y" T1 p( ]4 o& W/ w" t' u4 fstatic void McASPI2SConfigure(void)+ p( S8 Z" d3 p* F; v) |2 A) p$ m
{: v6 M& _( U% q" ]' o/ f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 Y9 U, @. w8 l6 E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 Y5 n: N/ ^* e* D& RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 I: U! L$ V( `7 wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, a$ \1 ^! ]( O3 n4 y7 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 j0 ~$ p6 S* |! x& EMCASP_RX_MODE_DMA);: Y2 y, A/ ]+ j6 `) X* s0 Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* b s9 g0 a8 B; }2 A- M* t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' j, Z1 Q+ z% b; @# p+ h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 @- h3 @: ]5 P- [/ w" wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. S; K o1 V8 I" _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " r0 b7 a6 G' S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 v# q$ O! `! q: k! g o/ W' {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 p Y D. \: w- b E/ }! SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; P0 F# P( R! l( R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ {( D; [0 S' \: n0x00, 0xFF); /* configure the clock for transmitter */
7 n3 D. {; C6 J9 g) [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 ?0 J4 L- ~" q; s7 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- q% R% f% K. @& t! S TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* B4 N7 p1 ^. F2 D; ^6 n8 e* B& S8 O0x00, 0xFF);# `0 |, |: Q. n7 C# @/ N
$ B5 e2 W2 `) L; \! b4 Y _/* Enable synchronization of RX and TX sections */
- k ]4 j- k- kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 g0 L6 C" ^! q2 G0 O: [* i3 f# X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# T* o) E3 _4 M8 @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 B4 v+ M1 g' u' d** Set the serializers, Currently only one serializer is set as
3 J3 X$ p8 J# V! i** transmitter and one serializer as receiver.0 Y& z0 n& W5 s& t( e4 P
*/
. C% \8 O! ^$ s6 E7 HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 V7 m% ~! g4 B$ H: ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 i" @7 M% n( ~2 t. u** Configure the McASP pins
) S6 y& W6 a7 b4 J** Input - Frame Sync, Clock and Serializer Rx
4 c3 z9 f! F; V- \6 }** Output - Serializer Tx is connected to the input of the codec
( z3 ]; u5 o; K# k0 h$ @& |+ n*/
; w8 u; O( @: C6 `/ i2 c7 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, e) {" P5 y0 e3 T9 d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; e: w Q# F8 L& ^+ m5 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ l+ f4 D* k& P! ?* L| MCASP_PIN_ACLKX' N: O& c! }- S. I7 S
| MCASP_PIN_AHCLKX
" b% d) a9 ^6 I; `6 T. n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// w* c7 `9 G, b% O& w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR m' B' ^( Z1 Z2 z) `
| MCASP_TX_CLKFAIL
+ b* E) S" u" F! I* \| MCASP_TX_SYNCERROR( w7 K. h6 j2 v \8 r% b' D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - r! l9 X1 S& b1 X& X% [5 A4 `
| MCASP_RX_CLKFAIL0 O X8 D f0 S6 A
| MCASP_RX_SYNCERROR
; f8 m( i2 E; {) d7 {6 n| MCASP_RX_OVERRUN);2 r5 D" O9 R+ E" p, q' N: N$ |7 e
} static void I2SDataTxRxActivate(void)# _: u1 F6 b: C5 @' T1 z
{6 s2 U( S& i, E5 r; _7 {
/* Start the clocks */
' Y3 F" l1 q- q4 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 l% B" o5 G ]0 K& R, C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# J$ ?/ ]. G$ FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
o1 ~8 I c) m% i2 GEDMA3_TRIG_MODE_EVENT);
) |' d5 Q: _* p% h! eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) h5 w: B n% J8 Q4 |* H& F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( E9 Y5 i1 \8 r0 x. nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 L* P. }; ~6 @' }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& g7 q. ?: T+ U! }$ hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 M" e8 s% n7 @: F o* W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 n4 _+ M& @' R/ xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ r+ J9 R, V1 P( `
}
. A" a* I- n, a; S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; r h9 o5 L) ~* J: }- b% s. J
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