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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 _, D2 l9 u& i) `; V) F h
input mcasp_ahclkx,
- e# H6 H9 l& E' @/ {' winput mcasp_aclkx,/ R- n, T: s# m! F
input axr0,
- m6 U; }7 C6 L& d( S! x# P ^' i5 [: {! Y" A; f0 G
output mcasp_afsr,
) P O$ u4 g8 ~! ?# H# L4 Moutput mcasp_ahclkr,
" ?5 m& S& h. }output mcasp_aclkr,
! k: \6 a' h7 ~8 i/ `$ Y& ^output axr1,
3 N9 E# e: D- J3 p assign mcasp_afsr = mcasp_afsx;
% Y7 g" c8 m2 eassign mcasp_aclkr = mcasp_aclkx;
% f: A7 r3 l& p, n7 T/ b! yassign mcasp_ahclkr = mcasp_ahclkx;$ c O$ H' l7 @
assign axr1 = axr0; # l' ?& ~" C4 t, r+ J5 M
! H$ v9 T! k9 U5 N. ^# N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( Q0 G$ L# c" G3 c, p( Z. ]
static void McASPI2SConfigure(void)
. n' q, n, a/ {% e6 y{( T2 i, j4 D& a- k5 `% y/ o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 g% a7 `0 b" w# f1 aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 n+ X3 x$ Q5 h& {3 e8 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" D3 p8 d0 C2 ]' j+ s8 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 z" {( }6 g, k' l' kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, a! A- i( Z2 c; Y4 G1 d
MCASP_RX_MODE_DMA);
' ~* Y( ~. t1 w' ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* G; N3 ?+ a; T$ e# w. BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 g7 q; t6 \$ x# t: C% _" _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" P) L) n4 Q7 [ E k" x: l SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( m: @* h& {/ iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
O/ \& M. c" H* t7 `0 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 J/ b' w/ T# n" Y: A0 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 I# Y9 u8 O6 R0 T: I% o, B) AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + ]; J/ f4 _0 c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 ^" r5 Q6 K& D+ i& p9 @- o
0x00, 0xFF); /* configure the clock for transmitter */
# q+ s9 }; ~/ U9 A/ qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- w( H+ b1 ?/ H. }3 t# {; W8 p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 Q2 p8 F7 ?! I2 D7 D9 DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 J' y# g& o; y" j$ C* i8 r
0x00, 0xFF);
( g1 [) Y L" Q# K
) j+ s! |* n' U* Q/* Enable synchronization of RX and TX sections */ 7 |- b* k6 h+ z6 j4 V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 N6 K# [' N1 }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 G h ?1 |+ _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! l) S2 X2 q- V8 y3 u! b
** Set the serializers, Currently only one serializer is set as
' b$ C9 E5 R' D: [2 O! y/ W** transmitter and one serializer as receiver.
3 c- z0 `5 }# y& W*/: n* @, h' n5 Q' m; D5 A4 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; J# F; S+ P# Y4 l" `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( P( c' T- Y0 ]2 B) {" H** Configure the McASP pins ( l# z( q% s1 s/ z0 K6 S$ Z
** Input - Frame Sync, Clock and Serializer Rx
* a8 Y9 P" n+ Y. Q; L+ g* L** Output - Serializer Tx is connected to the input of the codec
, n* r0 n& s {6 d6 Q# Y8 E*/
7 u8 l2 O- B( cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
`4 q% e2 I1 A" qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ X0 K7 y6 W0 z' G+ p) ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 J! s& d: q2 M8 v8 V0 p| MCASP_PIN_ACLKX, R9 y* U' F, a" \9 D2 ~6 a/ \
| MCASP_PIN_AHCLKX- b( [! W3 |. z- _8 c4 }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 Q5 H( Y4 \& @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % ~. e1 b+ s$ j5 y2 g q# I$ `7 r
| MCASP_TX_CLKFAIL
p. k' O: v1 N q% g. T| MCASP_TX_SYNCERROR
- N+ H) ^) t; J8 c p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! \. `5 g2 g4 b8 i| MCASP_RX_CLKFAIL4 w3 _/ V+ T1 ]' |
| MCASP_RX_SYNCERROR G4 E/ P* s3 w7 c* V) n
| MCASP_RX_OVERRUN);, X" }! u% F- g* @
} static void I2SDataTxRxActivate(void)
& ]% f- A1 ?4 p4 [2 q: n{
6 l: t l0 g7 C' ^. j% w/* Start the clocks */4 a; V4 m6 \6 c! T# h6 m) k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 Q8 y, [# V$ g8 E- }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% L6 d# k6 }8 i# }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 a+ {% y2 T6 o' U$ O- y( E$ I& ]3 H7 kEDMA3_TRIG_MODE_EVENT);' m2 B u1 T4 r/ A# b& q: Z* N- d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 C8 i5 V) U, d7 }5 D5 ^% g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ ]' t" E1 C1 tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; X T& n# H7 G, y2 z) ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" r. h$ s6 r) \' H( S4 B; i/ D% V3 mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 ~1 [; @' w' `, y' Y8 ?, n& [+ v/ EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ R3 F! V* ?. _9 aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 F- W3 `. o4 m( K* Q} , j) |0 h) ?, @& _& E/ s# ^; a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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