|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' x5 i1 o& A0 ?6 J2 Pinput mcasp_ahclkx,
5 p4 M, R8 W) linput mcasp_aclkx,- V3 d, o5 ?. J/ I, W' n: H
input axr0, d$ | G8 P* A# J, l* {- C
3 Q+ v( U) U+ e- ]% a6 Doutput mcasp_afsr,
! c. R7 T' w" x: @ ~ Noutput mcasp_ahclkr,( u$ M1 B! y' L- L
output mcasp_aclkr,
1 |2 ~6 z1 h9 m5 uoutput axr1,
6 f, i m7 V! Q; e# B assign mcasp_afsr = mcasp_afsx;- t6 R" n- W% E0 g& `# f
assign mcasp_aclkr = mcasp_aclkx;
: w% y' w* O C8 p/ Q. T7 Eassign mcasp_ahclkr = mcasp_ahclkx;7 n1 f8 j: U- z/ ]5 W0 @
assign axr1 = axr0; b4 @; ~+ X) a' r" p
4 A. F0 d8 F! R3 p4 u/ U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 R- P: e/ k, d( V( W3 jstatic void McASPI2SConfigure(void)' Y9 f; R- X1 a' ^) x
{# A! A4 V! g/ M" Q* h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ u+ m" q6 I, E: O& Z( I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# ]. a- o8 @4 d4 {7 @9 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 C/ _6 r6 S, {( h0 ~1 s( A) `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 d# X: h, j$ [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 Y# I, u+ k8 E1 `' h2 h
MCASP_RX_MODE_DMA);
( g1 Z1 l2 O3 e, H4 p$ J* Y' m( }% gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) h7 B# w" } H2 {" I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* C0 z/ ?# l# T+ M, D( i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + t/ ^7 ], R& c7 G4 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% o/ D5 i& c& I" [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' P0 p1 V+ h! A9 u" k; O: D6 T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 A. S% i$ G e- N2 f2 o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 n* i0 M3 S; s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 I+ a$ k; n) s! b) X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ o: }! r; s- j
0x00, 0xFF); /* configure the clock for transmitter */+ e& _+ ?. U+ o3 b, P; n9 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. H& ]9 E9 p; P- t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ k$ |% ~- S6 O8 e( [. X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 S6 O9 t1 @& c6 @5 o- m0x00, 0xFF);% T7 y% n8 M" b: C2 u" `
2 H. B$ }! _0 R( M4 _
/* Enable synchronization of RX and TX sections */
* I& O& v1 e" o( f0 k5 U$ dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* G6 E3 }& {6 A- @; w# [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 B2 _7 z; n+ ]. i8 R' ^ F: kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: X8 C7 l/ u) V- _$ e
** Set the serializers, Currently only one serializer is set as
3 Z0 w P" L, Q K9 ]7 P** transmitter and one serializer as receiver.
2 D' s f$ @; E4 w*/
: @8 C& g* U4 O0 OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 \$ B. O6 u4 a. U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 g: H# u; P6 K, o, L! C
** Configure the McASP pins
& z! X: I* @5 L" v$ m% Z** Input - Frame Sync, Clock and Serializer Rx, P' ]' J: e3 p9 q# H
** Output - Serializer Tx is connected to the input of the codec
: R: N8 c) _* g*/7 c( c9 t5 o8 ]6 f/ ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 U- {, \7 b; J3 {4 y5 o: g0 K0 ^; ?* TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 x! J0 [4 `* W8 ~1 {* n6 W& E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( t' X; r# b8 m( p: k| MCASP_PIN_ACLKX! [$ v0 K/ j) f3 r5 r
| MCASP_PIN_AHCLKX
2 U# l* j& M: g0 @6 u' D! i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 @" `/ A3 {+ o; _! sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* N0 f2 _! F1 Y- p| MCASP_TX_CLKFAIL " i' @0 P9 X% i" J$ ]! [
| MCASP_TX_SYNCERROR; C3 F- i8 b. e3 d4 y: H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: }$ n3 |5 I" m% }5 k# ^/ `$ O| MCASP_RX_CLKFAIL
( Q9 q) Y0 T) |& ^9 [' ^; i- m| MCASP_RX_SYNCERROR
; b1 R( F6 H) i5 @6 [! r5 B| MCASP_RX_OVERRUN);
U* B3 R1 F1 U( C) f$ \/ l} static void I2SDataTxRxActivate(void)
) r8 d& _) G( |' O4 W# z{
8 y+ U; z4 T( f( l4 U0 ]/* Start the clocks */9 A) _% U0 U5 `8 Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' d Y H& S& v0 B1 w3 ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 ]( j9 M9 R3 T+ \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% U* n9 ?9 d* I8 XEDMA3_TRIG_MODE_EVENT);
2 Q J" U9 ]' m; ~. @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! m! l# c& o/ z) OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. T6 K' R, @& t, X+ F; n2 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) g4 h7 S- M% R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 o) K; i9 Z0 m3 |: p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 s9 U* O; \) l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* i9 ~* n( D' j2 O7 j$ M5 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 e; r' F6 w. y: T7 p}
8 A8 _1 p: d! S8 r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' `% T% K3 Z G3 E" `5 C; r( s
|