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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% p* |0 a( e! p d) ~) c
input mcasp_ahclkx,
- T ^2 e2 z3 X* c$ t* a* P* Y" Rinput mcasp_aclkx,
; S; Q0 i- s' H8 kinput axr0,* Q0 v3 \# x. F2 E7 t% s
$ |3 _" ]4 _* s0 I3 x9 C6 T
output mcasp_afsr,
: Y; p& N0 h$ T, {0 v* v" Xoutput mcasp_ahclkr,
7 h0 u" ?1 t5 Z6 h$ y+ eoutput mcasp_aclkr,
* L/ [, L" D2 P9 C6 woutput axr1,1 w @/ U& g" y1 b: S* v) V
assign mcasp_afsr = mcasp_afsx;
# g/ O$ t0 O" Dassign mcasp_aclkr = mcasp_aclkx;
; Q3 b2 B8 |2 ]! e: P1 ?assign mcasp_ahclkr = mcasp_ahclkx; x; K9 X( }7 l
assign axr1 = axr0; 8 @2 d0 K& X: z4 q& g3 `) e2 ]
! F1 L1 z( ^$ d' M! S* m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 z8 ~- b# g, f/ o# X
static void McASPI2SConfigure(void)+ X e$ a. L5 J% s' [4 H
{
" H' q9 t, [+ cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ ]% l0 J9 p. A- dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ R7 B3 p# i$ g. `" m1 EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* V# Y- V' L2 W; ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 _/ k4 R& N8 o7 m# b8 _$ y- I0 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ O$ @2 v* Y- j2 w/ o
MCASP_RX_MODE_DMA);' n1 u5 J; R0 H0 I: i& v8 W0 }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ C& B* K* G* N- r0 O C; X# R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* u L* S' }4 H9 _7 P+ l! Y& _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + M. P/ P: [7 }) q: E; K- M/ q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, ^4 W" F: h. P5 E" E7 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , U, ]( \1 [& x3 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( y e/ K: u8 N2 }9 F' p D) k, nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 ]7 [9 R( ~* M1 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 ?1 h L! [$ \* x% `. j& A6 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, ^0 i+ Q+ l6 q! A9 k2 K8 R3 r d( |0x00, 0xFF); /* configure the clock for transmitter */
0 j! X E E( o+ _; Q( m: g" D% l. eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ \, Y# _) t- B: m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, i3 V& n5 o9 q! Z' w9 F" b) qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* f' f' R- e2 u, m% @5 N4 X0x00, 0xFF);
) f4 `) |+ m" P* B" I0 K+ O1 v/ D2 D& x# k0 r5 q5 c- t
/* Enable synchronization of RX and TX sections */ 8 } _7 `) W. [! @% r! C& U' B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 C) l7 {4 I9 z: f: Z |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 m( u5 b# B, J' z, C; _! k% BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. c# h) O. I+ Y+ k
** Set the serializers, Currently only one serializer is set as
4 U, Z' [) `! ^0 P: p** transmitter and one serializer as receiver.1 K1 k) v" Z9 [2 T
*/
( D' e2 W2 Q$ X; K jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) z2 _" z1 d1 k4 y- D! ~# m! EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; P1 s; Z4 o o1 L6 u
** Configure the McASP pins 6 A: [+ U/ C5 a2 ?% |/ m
** Input - Frame Sync, Clock and Serializer Rx
9 y; G! U: H+ O** Output - Serializer Tx is connected to the input of the codec
( I6 h5 C S+ E u/ A1 q6 w" U6 t*/
J' r1 K" x8 S5 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 N& k4 {6 ~+ m9 V: G+ wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' P0 H4 @" d( I, A6 {7 TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 q* q+ @: i+ W) T% Y% a" o
| MCASP_PIN_ACLKX
9 I8 X+ {1 f$ o! P) t| MCASP_PIN_AHCLKX
2 y$ |3 i8 h, m) y5 v1 j. l7 I% g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ h8 h/ O! {, b+ w5 Z# F$ @+ ^2 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 ~$ g1 C# d# q. B| MCASP_TX_CLKFAIL ! U9 A, n' O8 |5 B4 ?7 ` |3 l
| MCASP_TX_SYNCERROR$ I: b# o( n9 {& a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ P. {, X H4 a3 A) u( h0 P| MCASP_RX_CLKFAIL
. [+ R9 w$ C' b! j) V2 K' ]' ]| MCASP_RX_SYNCERROR . P4 n! [/ y; O5 S2 _5 b0 I, N
| MCASP_RX_OVERRUN);
" v0 Y3 l- b" [# e9 s% z} static void I2SDataTxRxActivate(void)/ R9 R( `0 E" S ], v8 n/ z3 f* T
{
3 M- T+ _) e0 j/* Start the clocks */6 @' E7 C5 I t* b4 M. m: B _$ e% `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# H5 H: L X1 L# M: W v' e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. s' x2 z' V) O( z4 i- x" F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ }7 X0 W; f& Q7 V+ V5 X- gEDMA3_TRIG_MODE_EVENT);& B1 [' J! H' j& B0 A9 l( c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 t1 S: }8 g% w. e1 y q/ K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- _7 O. W3 m2 }( h" oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 z4 W6 [* [7 j0 ~6 z `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ R9 s8 {" w0 c. Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 u5 S4 l( ^0 c. L8 u, e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" G* e, P) D7 H' T7 h' |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! O: a, j. \) }0 X, X7 S& G, m}
- P5 g- A0 k7 A5 r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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