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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, K m: o3 r+ E9 y* T
input mcasp_ahclkx,
/ A4 W; S- \" Z; y# o& Linput mcasp_aclkx,* f" e' ~+ k' z. \8 V" r
input axr0,9 I6 _" E8 w& _7 G
) _7 ]/ w; l9 y+ v: S0 t8 @output mcasp_afsr, \: L* e) w/ \8 c; |
output mcasp_ahclkr,, F9 p7 P4 E& v0 C% Q
output mcasp_aclkr,
- r; H P. x3 B) m# z9 {2 toutput axr1,+ P4 n3 e* s, t* k, g. c( [
assign mcasp_afsr = mcasp_afsx;; H& j' W/ u) A0 F
assign mcasp_aclkr = mcasp_aclkx;
. ^- N& j# A; eassign mcasp_ahclkr = mcasp_ahclkx;- x- r4 {6 }4 H
assign axr1 = axr0;
+ l- h1 M$ A/ L; }0 n/ f4 v4 O. i5 o* P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- c- @# g& R8 G* Mstatic void McASPI2SConfigure(void)
/ T) V% K) W) A2 R1 r{! ^' i2 b) d7 `# E3 c0 v; e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* v ^ O' c7 j- xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 T# u |+ ^8 M* q8 q/ `, B5 O" uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 t6 @$ f8 [6 gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" G' a* w0 {5 a# C. U# v3 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, [; i% W. n4 g: c) D$ r
MCASP_RX_MODE_DMA);- g3 H7 E$ i- C% z8 B" k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. e( o+ f8 W- G7 Z( ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 {' D; G% A+ @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 T. L9 e8 k$ d8 ~) cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) ?2 ?5 b" x% R+ R! k- W4 t! ]6 i2 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . R5 i4 ^$ {0 G- n; N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- z8 }; m: Y4 [# @/ j" G- h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 Y7 u4 w+ M8 }7 }8 u( CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : P; L7 P9 M1 ]9 G b7 z1 H0 B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' n; V0 z3 P5 Z+ ?
0x00, 0xFF); /* configure the clock for transmitter */9 A8 N J @5 i: m5 u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 o: l; J, W0 Q8 G7 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " G0 @. S' `( T0 j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. _% _/ {4 L# ]
0x00, 0xFF);
" C. G2 G/ I( i* M7 {( c
5 t9 ]1 f9 x9 d$ t% q/* Enable synchronization of RX and TX sections */ - Y4 |3 t2 H( w! T7 l7 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 @# s1 k$ z. I% gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: ? z# l: ~4 B+ D9 \! lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" f& v6 }2 e& ]+ {, A** Set the serializers, Currently only one serializer is set as
: K7 G$ F& G( r; T! r2 `" X** transmitter and one serializer as receiver.
; g# u% W8 \* A9 Z. B0 T* i$ U*/
1 O J& [' G' n- o0 ?- AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& O0 e2 v& F; o( NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 H& \& u5 c7 i. ]7 _
** Configure the McASP pins
H( }% a1 h! q) v4 M4 a** Input - Frame Sync, Clock and Serializer Rx
v F7 V0 v. L, I' E" R** Output - Serializer Tx is connected to the input of the codec
3 {& t+ N B- P }9 S5 T*/8 R+ P6 M6 ~8 X$ E6 G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 e' G& I# B8 J% P- t7 {1 oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' a7 h% t( ~- S& ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ g0 t2 ]* Z9 a+ K1 V| MCASP_PIN_ACLKX
% m3 O1 A3 F7 g% c' z5 [# ^| MCASP_PIN_AHCLKX
& @! ]% z5 \1 D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; u3 {# U4 I7 YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 @6 ~' b2 L8 C/ q6 [* x* I| MCASP_TX_CLKFAIL
; O6 s8 L& n8 t' E& f| MCASP_TX_SYNCERROR/ j4 C' ^& B& s0 Q! V! a2 e, a, u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 r7 J- r4 O3 K
| MCASP_RX_CLKFAIL
|4 @0 V# `% G% v6 C* A+ q: }| MCASP_RX_SYNCERROR + ~, s& j) O* X( M0 K w$ b
| MCASP_RX_OVERRUN);
# X* } u0 B% c7 I: q4 a+ S} static void I2SDataTxRxActivate(void)" P4 j5 z7 E. L. R
{
. `) R3 ~# p, m/* Start the clocks */* D; d" U# J! ^7 Q* } T: a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' G4 r# z8 u/ J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
w. m2 E8 ~. Q0 o: \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 j5 x' K, G1 yEDMA3_TRIG_MODE_EVENT);
" o) A: B! \* R4 W) L. EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! q3 [4 f, X$ M% C4 F. s/ f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: z3 m, ~2 R. YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' ~8 S# P, v, ]0 y' W5 _ GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 I" c! |8 }3 p) K" C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 L$ q7 r: u* g/ {9 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 z4 W, Y, Q t! W' b/ c: wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 I/ P4 X4 n; L) I4 I. P9 x
} 6 G! t7 C u" s1 U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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