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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 P9 O' u4 N7 f7 M8 k, E$ Einput mcasp_ahclkx,4 [. A$ n- v) |" x/ _* S2 V% i
input mcasp_aclkx,# q( ?! x( h/ t% }
input axr0,9 C" {- H+ Y1 r8 Q
" C8 T- W0 e% y
output mcasp_afsr,
# S0 x- i% Z! C0 O8 boutput mcasp_ahclkr,& |8 v1 t# t" @! q
output mcasp_aclkr,5 t! g& G A+ |' [
output axr1,
5 s5 a; z. T7 Z- Z6 y9 A assign mcasp_afsr = mcasp_afsx;/ w% W7 M3 Y' h! B
assign mcasp_aclkr = mcasp_aclkx;
9 S' S6 r$ D7 _, H. @' c% M6 Passign mcasp_ahclkr = mcasp_ahclkx;5 E$ `/ h+ ^7 e
assign axr1 = axr0; 9 ]+ Y$ u2 m; J% S* s
; V! W V. q% U: B0 A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 v* f9 G( d+ L: D2 }7 g9 L- I
static void McASPI2SConfigure(void)
4 i: [$ X! E: @' b" j{$ V7 V4 c9 h) k. Y3 r! o2 X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) q. g/ P$ [- U2 Y5 MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 {1 ^, _- q3 @2 TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); H5 T. J; z; e& q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" a$ i! {0 z, v! e( e6 RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 ~) W: A, ^3 k0 D) Z- r& ZMCASP_RX_MODE_DMA);
Q' x: G( ^2 o- y3 y5 N& ^( Z; l: lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, o" c& d4 v% X& F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ [) A; A# e; [1 x6 u4 S" v. KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 \+ } N4 ]% f \- `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 z% _! g0 j. f) }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
M* v9 `* T, A* i0 [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' N5 h* G6 ?% h: PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 \' I4 V- `5 t6 H Y- t8 L+ X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 j n; {, c: X7 h7 e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 l1 X h+ h$ l7 Y/ [2 A# ?+ ?
0x00, 0xFF); /* configure the clock for transmitter */
% f( k7 n( }3 pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 g( n3 ?0 L% l z3 \5 w, K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# I' h+ ~( e1 U& }1 lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, e# e1 ^' B( S0x00, 0xFF);
- e8 v" N! G8 _; J2 p |3 G8 _& m
/* Enable synchronization of RX and TX sections */
5 p; U$ l! A& ~+ mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 ?: W* j) t% W6 U8 TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( y8 ]( c. G9 Q, s# I% E4 mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& r6 l. m6 ~' ~/ A: c** Set the serializers, Currently only one serializer is set as
9 T0 t5 \5 U, W4 S$ K7 L+ L** transmitter and one serializer as receiver.7 _+ h& r7 Y8 Y
*/
/ b7 I8 ]; j- f L4 Z% eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( G$ V' ]* {/ A( P5 n" qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- ^$ Z8 A" t4 s
** Configure the McASP pins , Z. v1 d# ~* x# Z
** Input - Frame Sync, Clock and Serializer Rx
?- Q k/ A# c** Output - Serializer Tx is connected to the input of the codec * V) N' u: k( L$ B
*/
9 `: w( G7 p2 h, ^% kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ T* q( ~6 j' L7 ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 i6 y: n% [; E* n! {$ {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" q$ m: K9 o% ^" u6 B8 V9 ?| MCASP_PIN_ACLKX! o1 r; {8 |8 d( R
| MCASP_PIN_AHCLKX: G* E {* R1 N, v6 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- A: y0 Q4 j( c, S; V1 ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 e, [$ g1 W3 _# _* H| MCASP_TX_CLKFAIL
8 p/ {, L- {. p7 k1 P| MCASP_TX_SYNCERROR% h5 v) o( j( H: g( X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' f9 P$ Z8 j. Z| MCASP_RX_CLKFAIL
) M, L& \9 n7 [+ O3 d| MCASP_RX_SYNCERROR
) i3 @: w& I6 X* z6 v0 L2 ~| MCASP_RX_OVERRUN);
1 \3 g: S; u# y" p! V% p} static void I2SDataTxRxActivate(void)
& |! a& V* S/ U1 `1 @% s; [+ `{. j" N7 L4 ?' W
/* Start the clocks */
" V0 p. i9 p, R+ C GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 z1 D! K P; J1 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; N. R4 {3 w# }* T0 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& M, i2 O% s: {EDMA3_TRIG_MODE_EVENT);- K! b$ e/ z6 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 d. W) t2 M/ n$ I! YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. V: T, U+ j$ M/ P% UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ h9 M8 n' h# b5 b, ]9 IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 J& v, k" l# q9 P" k& ]& O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 [3 y1 E" Y: v4 R# rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) Y8 f8 O1 R$ Z2 J; n+ oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; u. k( v) H* ?) I5 [ M" V}
. c" t( f; v V9 q T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 w2 f9 k) a6 |
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