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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% C# T8 c" p0 U# S: linput mcasp_ahclkx,' C" o9 v* w6 Y" A/ f$ D
input mcasp_aclkx,3 k3 P* c8 X# i4 F" G/ I; b# k
input axr0,
2 j/ f9 k3 g8 D0 h
3 Z7 U- m- V5 b4 s2 E/ ?output mcasp_afsr,! \. @# C# J( ]* W0 ?8 L; w6 Y
output mcasp_ahclkr,5 ^7 V% `# c: [9 Y2 ~
output mcasp_aclkr,+ U. h, |( b, K$ q& u0 B
output axr1,
$ u/ _/ D; @5 \: n0 ^ assign mcasp_afsr = mcasp_afsx;
2 q0 z1 h3 e0 C1 yassign mcasp_aclkr = mcasp_aclkx;/ O) A& U7 K w+ Y t+ s
assign mcasp_ahclkr = mcasp_ahclkx;3 ^5 L0 j4 N$ U- P- V( W
assign axr1 = axr0;
% x3 _) s4 Y, ?5 {4 b
9 k; |& J% a' F/ w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: y- U0 x& R) _* Y, ^% \static void McASPI2SConfigure(void)
- J5 m% Q2 ^" L' g. ?{
4 Y" _3 j0 K; A! ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 |$ H' u$ B c. M. e+ a/ Y1 ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# R! s; J- \. S: c7 M! b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" h" w! f O+ E+ Q$ CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; R: ~0 ~9 G0 W; c2 d4 Z* X# }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' m2 l$ I2 D: Q# A. L% f# d6 a8 qMCASP_RX_MODE_DMA);
" }0 W' s& | {: n! I" kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 ]( C) ?, w, @9 F( A. T+ [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 w: t& e3 A7 A8 n4 R# qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 C0 X0 M- \& P% ] T a( g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 w- |5 k r0 Y0 R; d3 Z9 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % f" w% }6 h6 G9 T3 m. D" a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ B) D+ X! n/ ~, I+ F7 I) M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* E0 n9 R& x$ I$ A" p) N- E* y" V0 ?$ oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 J/ ]4 c3 ?" N5 {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- z& |& `& T& \9 D! a
0x00, 0xFF); /* configure the clock for transmitter */- v0 `/ i& f! U# g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 ?( z9 c: k6 r0 J$ }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, R+ M5 J: K) }0 cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- i% M. C, _9 R7 J- k; V
0x00, 0xFF);
j& S0 O' h, C0 E0 l; E
# J( {1 ]+ ]6 q1 |/* Enable synchronization of RX and TX sections */
) X: ^2 O( Q$ l9 s# ^6 zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. j* C$ x8 P+ @: v: a& h; y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: W4 }( A" R# x0 B- ]5 A; `; i5 m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# n, n* x; g# W1 R- P( ~! s
** Set the serializers, Currently only one serializer is set as
: f3 f! s, i" P, f2 Y. I5 z7 q& S0 o** transmitter and one serializer as receiver.+ o( ^# g$ p4 T1 g
*/1 u2 V* s( X. u! w7 D$ v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' I% o. D$ }2 }; f! t! H. q& I. ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 g& ?3 E3 R" G4 a* J: F
** Configure the McASP pins , F8 W" J" W8 a" n
** Input - Frame Sync, Clock and Serializer Rx) z6 E+ d) Y6 S% P" k
** Output - Serializer Tx is connected to the input of the codec
+ q8 G3 U4 c% {3 B& @*/
9 j; u' B$ D2 }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ Y, v( Y- V+ b' P* k! u6 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ V3 I! X& V; u6 O& N' z& p) a dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 x' y( p1 D a6 ~5 [0 c| MCASP_PIN_ACLKX4 H# z3 B+ j7 v9 v: z% t3 y
| MCASP_PIN_AHCLKX
0 P6 z: z+ V2 R, I3 K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// |! e/ l# `# Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 v# ~& c2 o! r+ l| MCASP_TX_CLKFAIL
: C+ o* u6 ^4 `5 E9 \! V| MCASP_TX_SYNCERROR- H- f$ W2 ~0 s0 F. I2 A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% u6 o$ x0 A5 |6 q| MCASP_RX_CLKFAIL
/ Z! q+ t* K+ s: B% B5 Y. J| MCASP_RX_SYNCERROR
' x! u( U" m6 ^1 }6 }* R| MCASP_RX_OVERRUN);
3 y8 h! K2 x: D# S1 _, I3 h} static void I2SDataTxRxActivate(void)2 {, b! R, T) M+ l9 I# V5 s' Y
{
2 Y$ ?0 ?* i8 o0 h C8 O/* Start the clocks */, Q" _9 ~/ g0 k7 N/ }, {2 [" Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 ]% V3 B6 s6 d( j1 ]& R0 ]' ]# T: `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) {& `/ R& s) j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. v u; b7 n* O0 [; [& w
EDMA3_TRIG_MODE_EVENT);# l% C! k$ W- I, f. G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# p2 h) k2 M5 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) D: O1 j% _2 i0 O; k8 G. @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! J D7 i3 o- X/ VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; L: b' M; y# p2 Q5 O% o* o9 m/ j7 t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' {5 G! S: |2 Y- {- S" j2 X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, |# V: b; _+ M2 L0 Q4 r" f& ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 V% G- ]5 u; ?/ Q} 6 g( s. i) S% S) \& E, M7 e7 F0 Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; Y1 o$ }; p# q) f+ \
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