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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% z2 ]/ Y8 L$ Z4 m/ z
input mcasp_ahclkx, X5 Y/ j; u) u0 S/ D
input mcasp_aclkx,
4 W" s- Z' d& N) O qinput axr0,
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output mcasp_afsr,2 F/ b5 o7 J: e- A7 T3 Z
output mcasp_ahclkr," `9 U5 o/ [# g: ?0 S; M' h
output mcasp_aclkr,
* P/ N, A# M6 X: L0 `" S0 ^9 eoutput axr1,( l3 Y4 m; W" B7 Z! k3 I
assign mcasp_afsr = mcasp_afsx;
2 Y" j2 H% c3 A1 Uassign mcasp_aclkr = mcasp_aclkx;
0 n5 H5 W, P, Zassign mcasp_ahclkr = mcasp_ahclkx;3 B% y9 A2 V$ ^- D7 g" s7 J
assign axr1 = axr0;
1 q* j5 C. |" x1 b. @$ W" z3 a" h& N& X: p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ R `( z7 H; g. `6 L
static void McASPI2SConfigure(void)* G# ?! r8 q5 E. q+ V" v
{4 j0 T- X8 F1 f5 l, I8 a! ]. R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' P6 ~' C) G! G+ o0 }4 z* MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 }- F! C: }1 t4 I2 G! iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ G0 I% K: h- I- t& u8 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ G3 T; ^5 `# d4 M4 b p% NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ o+ W# }- Q4 v0 k9 T
MCASP_RX_MODE_DMA);$ y' `" W) [2 |$ m; R$ z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( R( [) j n" s7 bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' m& z# W) \2 |- ?: \: ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, s* _+ E) ]; }* ]/ ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) J, J3 U( K3 l, l& g" B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
[, f7 h, y" N" ~6 r9 c+ F) hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: D& m+ p6 K" w4 n. lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% j% f2 M- \1 X% G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' V9 [9 x$ u j7 a6 e) dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 a) u) H0 l# {; a0x00, 0xFF); /* configure the clock for transmitter */
' l5 H( [6 {0 q* k. TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 a7 v. B+ ?; P7 d0 X y- UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 g( n) \# i7 Q) {1 U6 u7 pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. x+ Q) Z3 f- L& r: m4 O
0x00, 0xFF);
0 I" x9 O# J9 f* }. z6 i$ L* W* s5 M' e5 |! ^
/* Enable synchronization of RX and TX sections */
( q" o# E: a8 [; \7 O* vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ O) |% U$ u/ [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ n/ ?3 h( J1 \- O! P' b& U2 ?2 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 S9 W8 z/ U) F6 B** Set the serializers, Currently only one serializer is set as4 V7 |& m% V1 N8 C; X
** transmitter and one serializer as receiver.5 |3 P! I2 B6 V- N- b1 r0 @4 l
*/
. s' b1 \ a6 q0 m, e7 z. A. tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ {( Q& B- g( n% P4 e* c$ ?9 _* hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 a2 _. e, q% O; q
** Configure the McASP pins
7 T7 c7 w5 R$ A {6 s** Input - Frame Sync, Clock and Serializer Rx) j" ]# {. Y7 k8 r) v
** Output - Serializer Tx is connected to the input of the codec
. y+ T; ]3 M6 y# G3 @$ f( V*/$ R2 I# J8 b p" I* `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) j0 W. O" u. A; z& Y* _, W. oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ L2 T, g+ r4 n7 o8 [7 _3 G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% J, g0 P. n% \# _8 z5 Z3 N6 u
| MCASP_PIN_ACLKX
w: k0 V& R0 Y5 [) {| MCASP_PIN_AHCLKX# ]; l2 L6 q3 k2 |3 x) I6 @/ c6 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! t9 c4 o$ x' U a1 e( W. d- KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : n6 ^) a8 w D5 j! ^$ [
| MCASP_TX_CLKFAIL 2 R% U2 r4 n. u& Z+ c2 a
| MCASP_TX_SYNCERROR/ p& e$ Y, I9 n1 x' `5 S, j6 l- a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; d2 C9 f9 p" Y/ |
| MCASP_RX_CLKFAIL q, D2 M8 {9 }( e _- b I# B- F
| MCASP_RX_SYNCERROR @% T% _; V5 A2 k( \" A1 ~7 \; {
| MCASP_RX_OVERRUN);5 J8 k" K* N) r# d, \4 ?; x* t I
} static void I2SDataTxRxActivate(void)
7 \# T7 i ] |' p% O" ]( @{( D1 c& \. ? K `! S( S
/* Start the clocks */. j4 |/ d& x% j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 j; ?% t* [ u6 T: \: sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, [: ~: ?. Z1 p4 j vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 T! u/ ]2 X* `! `) x ?EDMA3_TRIG_MODE_EVENT);7 }5 r0 z4 X7 V n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " H8 L% ]+ s& u4 `# o, W9 L: G: q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" N, K- {9 b( M" y2 y) }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! e: T; A5 |* b" Y: }! ^, HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# B' m+ T4 ?3 N( p8 lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# S1 H T3 H2 `6 @5 [. oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ A+ L8 {+ [1 B2 ~' P! t( l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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( p. u* f# t* l) U5 X0 n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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