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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ n# O. _3 R' ^3 r4 g3 ninput mcasp_ahclkx,
2 J# k$ c4 ]% ]3 d' zinput mcasp_aclkx,5 C# Z: j. D. ?/ W
input axr0,
0 A) S! x$ m. f3 d" ]
; N/ b: P+ r& V- U5 ^output mcasp_afsr,
( ` e f8 M4 coutput mcasp_ahclkr,
! N2 ]# F7 a4 A# U" I! Woutput mcasp_aclkr,) h0 x. \! g+ T3 P+ R( G2 h: }
output axr1,
$ @! S! ~3 |% F assign mcasp_afsr = mcasp_afsx;
0 t3 ^9 x# Z. _: Jassign mcasp_aclkr = mcasp_aclkx;
3 v4 g- S1 f0 U9 bassign mcasp_ahclkr = mcasp_ahclkx;
6 [; K! Q( R: G9 e, gassign axr1 = axr0; 9 p" T$ R- o' C& ?3 P, H& U( z, i
( f4 N, d# i+ |$ u l% |4 @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 u+ F% e2 }, N! a) Y& I) dstatic void McASPI2SConfigure(void)
3 O# ]" k" _# b8 j* V# }6 L{
y- L- N+ T8 [& r+ O4 }7 j& i NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) j) S& m4 J6 N; C( U% R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& \: d% {' V$ QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ W3 a) y5 T7 y# f! e. R4 s$ wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. R$ [- W, q; n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, H2 V" k! ~0 J9 ]7 ^6 d
MCASP_RX_MODE_DMA);
+ C Q7 r! H* t9 c/ gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 n: V4 ~, c: OMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ r% {6 M6 s2 w; C( L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 o) a- [% I& j6 MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 ^; \' S* m! T3 @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 J# g6 e6 Q* V' N8 C6 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, G/ ~( i4 b. J" Y; B* D. tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( J# }0 K( n+ C" h. J( P {5 C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! n; ]" o0 W3 z5 M5 _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ T$ U- w$ d2 s4 S$ k( n' Z, [0x00, 0xFF); /* configure the clock for transmitter */
& D! o: v6 c7 K' |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( x3 ]8 r/ o, i- J4 X7 j6 P' }2 g# XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
L7 {& N- m% v5 MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. E& T2 { W u9 [9 ~0x00, 0xFF);
* n: l4 d' T; P: S% T
2 A% @7 ^* }2 W3 R% k# r/* Enable synchronization of RX and TX sections */
( D" i b' B* |) q4 L mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) R- L- ?. F# s2 ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% |+ K$ e: h9 n$ RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 D3 H9 A+ ^6 P; x; E
** Set the serializers, Currently only one serializer is set as
- \2 Z/ W+ b1 x5 Y* z** transmitter and one serializer as receiver.
A- l& x* @: R7 k7 S5 y*/
9 G9 j7 l# M8 BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 S) B, x' f% O7 S* S# bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- C+ n7 r" u( H
** Configure the McASP pins
# l. r/ [% N" R5 o" n4 u1 V6 P* U** Input - Frame Sync, Clock and Serializer Rx
& r( F3 B, [9 D0 Z- }** Output - Serializer Tx is connected to the input of the codec
9 k. u" O# f0 [9 g C/ h) ]*/1 V$ X$ j) A% O5 i( P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 m7 ]( _: X- c& \) |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ Y! e1 ^0 E5 Q' L+ P: R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 i$ K" J- v1 P| MCASP_PIN_ACLKX
/ }1 J+ X/ }% @' @, [| MCASP_PIN_AHCLKX
- ~/ \3 Z* e, v% j4 ~+ H6 i! `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ g8 F' {9 d; @& X0 F& s7 G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) |; B0 \" r' H( g: b% t0 N2 Z' v| MCASP_TX_CLKFAIL . u; b. j5 c, @7 R8 ]2 N
| MCASP_TX_SYNCERROR
- r, ^ R. d$ t2 D/ O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 w2 Z8 K; ~/ X) g) u M. s% w
| MCASP_RX_CLKFAIL
7 a' ~2 s; y7 n| MCASP_RX_SYNCERROR 1 p2 P* R, e6 m4 U/ ~# z- e7 i8 W$ V
| MCASP_RX_OVERRUN);$ P K: K( W! S5 F% `
} static void I2SDataTxRxActivate(void)( s2 ^9 n( F+ d' Y/ ?& c3 q# _4 w5 W
{6 o4 v, p" S! S
/* Start the clocks */5 G+ [8 s8 t2 L% z% ?! N/ K7 ?' [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. J! `4 h- G& j2 S7 N8 ] G7 bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& |' p" p P6 `- k) D9 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* i- P9 M' O! u" n
EDMA3_TRIG_MODE_EVENT);
% Q) v A8 n" K+ g( S) [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % \9 O+ V+ r! c2 r+ a) d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 [7 X( y& A% x! T/ c) tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# [) Z$ O& b! {, _- m5 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- Z/ g$ X, ~, w- n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: |! [& e( `3 S6 G `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, }$ O6 c/ S5 n1 U# h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, V+ l9 O u# _( a+ G; _+ _1 W
}
, W; o4 B. v* ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
5 K) y% q/ Q4 t% X4 j |