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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 ?# N9 @( ]. V5 a+ ~input mcasp_ahclkx,7 R- f4 E+ Z6 M3 G7 S
input mcasp_aclkx,
0 k2 k2 e1 a: s8 E! d& Iinput axr0,
# F0 q7 \; G* O* z' z( K; z' p
4 d' J0 y$ S- O2 Q( Noutput mcasp_afsr,+ b- W+ y6 T/ G4 t# R' ^: ]
output mcasp_ahclkr,
2 G( U [3 {* l; @output mcasp_aclkr,+ K! @8 z& m2 g1 D1 u% d
output axr1,) d+ [; B4 P3 R y! ^' u4 _
assign mcasp_afsr = mcasp_afsx;2 ?7 _) ?( Z0 ?. _
assign mcasp_aclkr = mcasp_aclkx;# Z% q+ [2 M( x' z- G
assign mcasp_ahclkr = mcasp_ahclkx;
9 r3 K$ ?( g% k7 T5 n% N- x- h1 Hassign axr1 = axr0; 9 i9 t2 H! y. b; G
# O" ?4 f) ?0 a w$ h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 Y2 o$ m* G' u y5 g" kstatic void McASPI2SConfigure(void)
; B+ E7 t8 _$ I; i8 D{
z+ d. a% V: |# ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ Q# I$ X$ {; D* b" U& }* aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. z' \: p8 x; S1 V6 m! J' H5 G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, i! z! r$ ^8 T( a( p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 h# L' U$ L! ~, bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. s: @# F0 K4 m. L3 Q0 N/ D* TMCASP_RX_MODE_DMA);
$ Q: p6 g- |% s* H# J8 \) [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; Y% A$ ` K5 E1 d5 ~3 p% L7 {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 @: x/ {* X/ A' D/ U# W- L7 X0 SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 q0 e3 o) U, V1 i8 n+ m9 IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" m& t, J8 J, eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 m. Q0 d2 F" a. u8 l G6 R# vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 u! e$ d. j- p/ Q) @% R) B8 Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 n Z" P; s& b1 eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 B4 g; r: a+ A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 g8 G0 A- i* F% J* y. U. H0x00, 0xFF); /* configure the clock for transmitter */6 P3 ~1 c8 Z8 D- O/ D1 u \4 I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 ~ }8 }3 u! p3 ], N$ C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 w- N, ]+ ~1 ~8 Q4 j7 p% w2 Y; y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# ^( E2 i6 l! b0 l6 d
0x00, 0xFF);
) G+ @) ~% c% s, l$ e- | Y
: q$ M, d5 `; Q: L4 `/* Enable synchronization of RX and TX sections */
+ ^( y; i% D1 U2 ?+ o5 X# `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; h$ I# t$ l9 M+ ?, n4 A& n `8 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
|& N4 M' O6 N) e+ n7 JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# Y; y4 C) q* J' T/ P3 M+ |
** Set the serializers, Currently only one serializer is set as1 ^0 F# Q# R/ x& \( r5 w
** transmitter and one serializer as receiver.
- _" g. _' Q; P: `*/+ @9 G* q8 ?( |4 U7 M8 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) t/ u2 r) Q1 R2 H# Z: l9 w$ T- F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ ~7 }" _' |6 N! A; {
** Configure the McASP pins
( e! T5 e- ?& N: l7 X** Input - Frame Sync, Clock and Serializer Rx" S$ J$ _2 w2 R# T% k- P
** Output - Serializer Tx is connected to the input of the codec 3 E2 `* c4 }: y P& R
*/5 b3 ~0 h' y, k: Y8 u* R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- }. K1 U' M h% dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! h3 y0 {! c8 A7 g9 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- B z s$ U, l
| MCASP_PIN_ACLKX! e i/ z$ P6 a- q7 G
| MCASP_PIN_AHCLKX6 ^+ x3 R# u9 T; W% h; t4 ]4 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 E1 \. x; [8 _8 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 I; b4 H* k9 v; V+ B% C| MCASP_TX_CLKFAIL
' g' L! T- U7 i+ p/ T- q. `| MCASP_TX_SYNCERROR
; r9 }' C4 v# j- d' x7 h' u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 o3 O. W# \& z! U' _4 }$ ?
| MCASP_RX_CLKFAIL
$ F; \4 Z k1 n8 K' e) s/ T| MCASP_RX_SYNCERROR
0 K1 [# g0 P; B4 M4 N8 Y| MCASP_RX_OVERRUN);" L! u' a' P1 \. F& V8 ^
} static void I2SDataTxRxActivate(void)
7 y" }( e7 B1 a" i- _$ G{4 \$ h" b# b. n
/* Start the clocks */' v5 W2 x6 b* J7 z/ c4 ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 T5 I8 B9 |; D0 i3 K2 i2 E, `3 u. s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 M( X# b/ O' t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 S0 E/ [5 z6 ~: b- s
EDMA3_TRIG_MODE_EVENT);* n, d( h5 m+ a% S8 ?' m9 z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% u# C5 {3 c! t! i1 g* K. rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ W/ H) Q2 k" V) J3 ]" F, d4 j0 m5 Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# v/ b; s- _9 f7 h) B, rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' l! l& c2 l+ ]0 z* L" x, b7 |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
[' _6 L. C# w8 E+ u4 m0 @, MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 J# `8 f# R- _( N/ Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 ?; X, M9 V/ j u1 b6 X# p+ ]} . K3 t( s E! n# C7 f. N$ I4 g* x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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