|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) m1 q5 x+ ~% X/ x1 v! L2 w: I- Finput mcasp_ahclkx,
& m1 l( r% ~( J9 M2 d& \input mcasp_aclkx,2 E: i- d1 T" O/ A8 d7 Z( J
input axr0,
% f- i. j( i6 a# @/ w r1 o' W' j0 D; |1 {8 \5 q
output mcasp_afsr,
* A# r3 n. O4 i" S& \7 ^output mcasp_ahclkr,
( i2 [; I; i7 a( N' i joutput mcasp_aclkr,6 _* e3 Y. j1 h4 Y3 G! z
output axr1,
- a5 }/ \- u' {' X5 q7 g assign mcasp_afsr = mcasp_afsx;
, b2 C7 l8 o6 @assign mcasp_aclkr = mcasp_aclkx;4 k" o& P* E, H. f2 ]: {4 q; `
assign mcasp_ahclkr = mcasp_ahclkx;
- B& [5 y, m: R1 u( C3 ?assign axr1 = axr0; $ o @* B: M: f% z# g; ]$ o- w
- t* e' p+ ]2 Q/ Z% |: I% z- R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ q! d0 B& d! q6 n- V7 Tstatic void McASPI2SConfigure(void)$ W. a, T0 \" f8 Z5 L
{
6 ~2 F9 k. q/ E" c' {" f+ Q3 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ H6 w( z$ K3 c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 k( A2 o0 Y* O8 ~1 r+ F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' ^4 u: I. z" e7 \2 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% n; y% q3 d! l/ u' x h( MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 @6 H5 m2 W$ r1 g' ?
MCASP_RX_MODE_DMA);
( ^* A6 \5 y$ v( _6 JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; s6 B6 f; R. ]8 t+ C. [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 d& y$ a' F" y1 E5 GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 H2 ?! P9 t6 a& _$ [3 v, ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* H" W9 ?) G& f: qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, e9 I W' A- r- y; L0 T# WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 ? K) a8 o ]6 F Z, GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* P$ a; E6 C- B% s3 N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * O) l. x2 Y" ~. I, g2 L" _& _5 Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. E/ h& b3 g' v9 L9 o8 x0x00, 0xFF); /* configure the clock for transmitter */! W0 _ [8 |; u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 J. q3 |+ C, z- pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 u( J3 \+ A8 h2 x% p% ` _- QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 Y3 {& Z1 I F+ v6 U9 X
0x00, 0xFF);1 ? q* {4 U: B6 N
7 n% m8 m. Y" y2 V+ [
/* Enable synchronization of RX and TX sections */ % S5 K* l: X$ ^- ?( v- G) f \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 L( [: n4 j1 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& O1 } C, O9 C; b7 X9 {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. m* P; E: T2 }- G/ {
** Set the serializers, Currently only one serializer is set as
; T. F9 r" T+ i** transmitter and one serializer as receiver.; H! j. z X# x% e
*/
' z( N; e6 \) `" m6 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' y0 k' H" ]3 K! e! K/ f& fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% l- `, S% z5 I& f" b3 N: t* {* A
** Configure the McASP pins $ I, m* n" U2 n* b
** Input - Frame Sync, Clock and Serializer Rx
) b% |; D% D" ?) e3 W( X7 ~** Output - Serializer Tx is connected to the input of the codec 5 A% ^4 Q# g z% |, F! W
*/
2 U4 P f* _- T2 | O& xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 X0 L0 m( u2 l9 rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, y# z% H" P* ~6 U6 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: K4 {2 K$ L/ a6 `| MCASP_PIN_ACLKX
& M2 z: w' q8 i( f3 w' z| MCASP_PIN_AHCLKX
+ ~$ y/ `9 A" ]2 X1 y0 s7 Q# Z& Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( [" D) c$ v4 a! {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 Z5 Y1 h, |% X8 m! R* `$ U| MCASP_TX_CLKFAIL / p: b: Q& |2 q4 e3 @3 Q% t
| MCASP_TX_SYNCERROR; P) C3 r* ~* q9 Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" x5 @* ^- \* x! D# G| MCASP_RX_CLKFAIL
& K& `3 E6 r( k3 h: ~3 j| MCASP_RX_SYNCERROR * `& P5 ^5 ?' y! k& S5 B0 V% C0 S. A2 n
| MCASP_RX_OVERRUN);
: G8 \" h8 v, z; k( j} static void I2SDataTxRxActivate(void)
6 I; e& b! K% V7 p( c( S$ t{
1 C" P7 C/ Z) V: \/* Start the clocks */1 k+ \( ^% G5 s" `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 E$ b" W) C" t$ {* TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- o# s% [; A1 r: A2 w f0 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 Y% m3 C( T/ } y9 }3 T. X; y1 m
EDMA3_TRIG_MODE_EVENT);
& Z' u9 I1 q" X! Z* @1 }' SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ o* `% w) t' u& s' ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 L8 t# k; M1 J# g, w$ ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ K1 T) q7 ^, P( JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 D+ v4 ?, P" c3 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' q. K. B0 E: a2 j9 tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); G! k( @% j( r# ]& w" { z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 |/ ?0 x, r; t+ t4 F% v}
7 E7 c: v" Y$ \6 v# i6 C" n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 ^* H2 H/ {% B6 ], w
|