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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) q! ^) Y2 P9 s: Z7 I
input mcasp_ahclkx,/ G. O M- z1 }$ m" ?3 z: M$ |+ }+ e
input mcasp_aclkx,
$ e8 f( u+ O, x2 \& einput axr0,
$ M4 L: ^8 e. ^! S: J5 X
# p' k/ V Z2 q0 U) S# [/ f( G2 f' noutput mcasp_afsr,
- \2 T3 b) q: N" R( e, Poutput mcasp_ahclkr,
# b: F4 E6 w- U7 ?8 w0 Z: I foutput mcasp_aclkr,
% E% v2 R/ e( H' Q1 q* routput axr1,6 t/ o: X: g% |- }8 V% F
assign mcasp_afsr = mcasp_afsx;* U# ~ S6 i0 \$ ?
assign mcasp_aclkr = mcasp_aclkx;
# a) C; f; ^2 G8 W4 `; j; k, S! fassign mcasp_ahclkr = mcasp_ahclkx;
$ K5 q2 R1 I5 D4 u' l! Tassign axr1 = axr0; ! }( w5 r/ v& K# J+ {7 Q0 R
& \- P& ~+ P |, u; n2 c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * Q! t) c0 }. ~8 R& `0 B
static void McASPI2SConfigure(void)
9 I4 {8 X( ?# B1 f9 b! v{
9 Z; A. ?7 h, x. qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 J$ x. V6 q8 _. u8 S) m6 U( AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ b U0 Y7 Y: I& eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, K9 j- D% h+ i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 A6 s" T1 @; k: u' s$ ]5 l0 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: [' K, E; |* @: O+ R+ L2 ZMCASP_RX_MODE_DMA);
; u1 \0 n6 T0 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 `1 r1 f/ a, o/ L/ k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 V! N0 B' m+ y5 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & R1 d: B0 N, P# O& n. }$ S0 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! w# e1 l; _! H. ^6 u( J( wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % M6 J+ _; B2 T: g$ ]- K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ U- n z: D* @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 `9 w0 n& p9 ]- W( h( s0 n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 q; E2 v1 q4 U, @8 r7 _4 a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 j" c7 }6 u" g5 Y0x00, 0xFF); /* configure the clock for transmitter */
* u% U( A) I- b' b& L& RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 O0 ^. h& P# Y7 g, y; Z4 Z7 AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 v+ h$ z5 H! d1 R$ Z4 D5 w- `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 G( t+ u+ |6 M6 d0x00, 0xFF);
6 d: {! w1 C1 |
( Y5 r5 V, n: [/* Enable synchronization of RX and TX sections */ & p) o( d! P9 c, n) v# _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( ^5 a) G$ g5 q4 ^% u0 s1 J, FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 x: q% Q5 q0 B- W3 Z e5 c
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 `9 _7 N/ q% F, f# ]5 l+ ]! R
** Set the serializers, Currently only one serializer is set as$ Q* x* C+ R& t3 l o1 n1 M$ M4 m
** transmitter and one serializer as receiver.
0 G: ^ k2 R3 r" E. L$ m$ S/ b2 A; U*/7 A# N; a/ X9 f8 d7 w1 u5 Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# k* f; d4 R" @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** e, `. z8 z4 b5 l9 C8 L
** Configure the McASP pins ; t& g7 s2 z1 }2 u5 E
** Input - Frame Sync, Clock and Serializer Rx
5 c9 s% U! W1 I" @$ `3 U/ R** Output - Serializer Tx is connected to the input of the codec c- A5 ~" i7 }
*/
: {6 }0 ?: o8 d$ F& pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 M, {, H$ o$ YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 h& h5 D) @6 h8 P* \* A+ c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: {* l1 `8 S$ c
| MCASP_PIN_ACLKX
1 C- M' F$ _# H; T' d [| MCASP_PIN_AHCLKX
, m7 k \8 N+ K4 ]+ j5 a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ {# U; h, A7 B1 g4 q( Z9 ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 x8 ^) X2 M6 i0 }
| MCASP_TX_CLKFAIL
7 B/ Q# l! k2 K9 J( J$ _| MCASP_TX_SYNCERROR2 Y- N$ c8 Z% o+ i" u, R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 t5 P( \+ F; K0 l) H
| MCASP_RX_CLKFAIL: A4 f: O# p# S; ]4 x0 R& i8 j
| MCASP_RX_SYNCERROR
. p+ T4 e0 M4 B' _| MCASP_RX_OVERRUN);
; B. U1 O& R. c} static void I2SDataTxRxActivate(void)0 k, P; t7 B9 `1 o6 u6 ]
{
' d4 p. O, t t7 X/ l" f! \/* Start the clocks */
1 Q H: k/ U7 \/ Z/ \9 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. ^$ _3 u9 w# t2 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 h& g9 i' R( S- ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 T. V% c. b& B8 F+ ?
EDMA3_TRIG_MODE_EVENT);5 _# r+ \$ `2 c$ C* L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / L* y+ e, U( M, T: R$ q. }5 Q6 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 ^$ h: I3 S0 X% p7 I3 BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) R3 e+ {$ N5 H1 y( y' s7 W) r! O. QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% Q o/ L' l+ J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// B' G! P# r3 Y- E6 D- U( o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 y( d' |8 a5 O% s8 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 ^2 _- d! t, X5 x7 k4 ]3 A' Z
} c0 }" Z3 x1 k% p8 L# S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - h4 X. j9 m2 y- B1 P
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