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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 P' V- K; U1 N* J% E" h% S( yinput mcasp_ahclkx,
2 B- t6 r; x% a. jinput mcasp_aclkx,
' F& V2 d4 x" U& J3 C2 E, dinput axr0,
/ G$ n$ ~9 d( K0 r m |6 h D9 \" E
output mcasp_afsr,
2 ~9 a/ p$ v5 G3 n& Z! C; N( houtput mcasp_ahclkr,
5 R/ d/ h0 h) ~' youtput mcasp_aclkr,
) q9 \' F5 b- M) Noutput axr1,
+ R+ h# ?8 j1 Q assign mcasp_afsr = mcasp_afsx;6 M# x ]" _; {# Y; W
assign mcasp_aclkr = mcasp_aclkx;
, Q/ }0 q% l; b9 O4 z3 Z+ {assign mcasp_ahclkr = mcasp_ahclkx;. y- y8 o* o% x5 W; ]; @( m+ N
assign axr1 = axr0; % O+ N( {/ }! Z, z( B8 `
; _6 V' z; v" N$ P5 @- ~" f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 `. b8 h4 z% }1 Fstatic void McASPI2SConfigure(void)
z7 r( W7 W# O- U' l, p6 B{
4 v/ }2 o" a/ zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ Z3 B1 |- E6 A* g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- Q% t" V; p/ O6 V. r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, |5 ?& i9 U. h6 x3 l- yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ o3 g% T3 h5 W- v1 T) T8 ]" t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. @# ]7 M6 J- z6 ^, BMCASP_RX_MODE_DMA);
! W" T+ E, Z$ b3 W. m& F# m, ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: D+ [( S& Z0 _ `# F: H, j; i! _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. z9 @2 q# n- Z/ y6 W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' O' u7 w9 v P5 D( m' T+ Q: r+ t4 s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( i: L$ E# ?) X! \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % J8 t- o+ n9 X9 U- a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 l8 P/ V$ t5 [# Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ [; L' V( g# C; j& U# z- G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' {7 |! G! K7 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- u% t) L- w% c6 o; T, ]0 I
0x00, 0xFF); /* configure the clock for transmitter */
& h5 J# k \$ U: g/ F; ?4 |: a& NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' G7 o% {8 n1 T0 ~$ O6 l8 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* V; X7 c R! c6 t7 C& [7 ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
T0 K: \# D& e5 g; k9 N$ S0x00, 0xFF);" p; {# b2 ^& @1 R1 j' c: N
" }0 [4 X8 S# f9 z/* Enable synchronization of RX and TX sections */
4 ^" v4 j! V! ^" C: HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" z0 d" @* c- @( y2 p% GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) }4 G7 u% P7 e/ c: QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ x0 p+ W7 C2 A/ ?6 t1 l: o** Set the serializers, Currently only one serializer is set as
& n+ P1 c# U9 T& ]5 D0 q** transmitter and one serializer as receiver., o( O$ @4 Q. X# [8 e5 R" K
*/# y2 x' j0 [) j3 h7 @6 s/ I" d( z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
c# j/ ~: [1 x1 e: TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- k7 ?. M/ @: A/ Q, P5 n; _$ v: o$ c
** Configure the McASP pins / U% t0 U4 F0 o, A1 K$ j
** Input - Frame Sync, Clock and Serializer Rx5 l; g* t+ [2 p" y, B
** Output - Serializer Tx is connected to the input of the codec : W; m; n* b) ^1 N7 t& m1 j8 T
*/
5 l& p8 S$ s2 W* |) K nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( M9 C c% L7 J$ q0 a% ?6 t% h% `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 l$ A! p+ E% x8 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ P8 O& V3 z0 f0 x0 p9 W
| MCASP_PIN_ACLKX
3 @& ?( k! X( G+ u4 || MCASP_PIN_AHCLKX4 |% J# f% d! Y. T1 b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! r8 R0 R$ {5 W! S1 E3 m' m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . K) [/ C7 R( v" o
| MCASP_TX_CLKFAIL
8 k9 w" [9 V! Y' I3 H$ _# Z| MCASP_TX_SYNCERROR- g% }# o: ]/ u2 e- M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ |* A p9 ~3 X+ p| MCASP_RX_CLKFAIL
; A* } \# {6 M4 N4 Q7 k$ v; ?| MCASP_RX_SYNCERROR ' X2 N. a! y: V! P2 C8 i h. J
| MCASP_RX_OVERRUN);
" @. d1 `8 r- _! t; B- R( U$ p} static void I2SDataTxRxActivate(void). W% A& x; H# }- k. f j3 h/ p3 Y
{
& C5 C0 K: {: a; S' V& ]* K/* Start the clocks */) H' Z% O# C4 L8 y U* @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 E+ R" E& l% R: H8 T; WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 H" v! M0 N/ n# l. [) l/ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, u) A( m7 ^$ n+ E% w9 w; s
EDMA3_TRIG_MODE_EVENT);, r$ f8 S" P3 g; G" I5 P( f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 S1 Y) I9 I: A d5 H" n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' Q; \, ~6 g$ q/ ~$ e. o! {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ j& J, i0 e$ C5 ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 \7 q v6 s7 a% K" m: n5 }7 j. w0 k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// W, O; V- i2 b! T8 T$ k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% Q: H. b; R8 s: AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 x9 r, r+ | {% b7 c' t
} 2 b! J$ A+ B( R" F3 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' Q, G' l7 O% X$ L2 R- m$ k1 K
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