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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ X: _2 C/ b$ K0 w6 T: Yinput mcasp_ahclkx,
+ U9 l/ O/ H0 J0 b' Binput mcasp_aclkx,- z% s, \9 k. H, n. H" ]# x" A
input axr0," e' Y0 D5 ?% b7 F4 ^5 D# Y
\0 [6 B4 Y2 ~output mcasp_afsr,
2 J# O$ e$ q3 }. z7 ]output mcasp_ahclkr,/ `8 h* k, ~! _/ f
output mcasp_aclkr,
- d) f/ U6 |$ B. Ioutput axr1,
5 F; d$ C- \; l assign mcasp_afsr = mcasp_afsx;
]8 f. V0 L; q* E4 n6 passign mcasp_aclkr = mcasp_aclkx; ^# _2 H7 L0 m! Z/ l
assign mcasp_ahclkr = mcasp_ahclkx;
R, A# ~$ E+ O$ y* w1 @assign axr1 = axr0;
# i3 y2 w& f7 \1 q B- j/ a6 h3 O/ f! g G$ h3 ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 d3 T0 h: O+ f5 c
static void McASPI2SConfigure(void)
+ A7 R$ o; S* C% a: p# p0 ~{
& R- V0 t% @3 r, V0 N$ W. r& @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 X/ @# U2 j$ b W) o! x/ LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 i- U2 L G9 d. H7 O- JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! F# ]3 n8 D8 k$ j8 _) P- T7 v9 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# h$ \# g% {$ |8 a6 {" b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 J( q9 p& A* }# N3 ]3 zMCASP_RX_MODE_DMA);
) F0 d- H& m: W* Y9 f- DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* w! I! Y3 C- B2 G: V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- M2 ~* u1 x4 Z. z0 C* U% YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ v7 O5 Z' B* X/ |# _7 |# U/ i2 oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. p0 k4 q: F( s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 u1 j* s0 p% w9 d' U# `7 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 ^& b$ _* E# v( s( A, u3 V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- E% k9 U6 r3 ?$ p" x5 [/ @) TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 |2 ]% G1 }0 {- E; b4 EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: i6 Y2 J* s% K1 P
0x00, 0xFF); /* configure the clock for transmitter */& d" a' g8 ~) _/ t( q' T" N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ T& Q, v# V/ B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / ]! Z `4 J! z9 U0 H9 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ O2 ]7 S$ R0 D0x00, 0xFF);1 i( \2 J- C& O; w0 ?3 Q
4 R( t2 k7 M9 J/ d
/* Enable synchronization of RX and TX sections */ " x% ~0 B+ N1 M) e; |( u0 P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ `$ b/ s" S: t2 `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 k4 V9 { r# A+ l P+ @4 h2 G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 M* u% m0 c" Q( q1 ]0 z3 V) S** Set the serializers, Currently only one serializer is set as
$ q. H4 Z3 t) s( A' U/ ?** transmitter and one serializer as receiver.
" k, m# L( j7 A*/
# W5 M, l* i, S& Z K8 ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) p- I: D {. x3 A7 WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 b9 @3 ~8 S; P7 Q6 u S
** Configure the McASP pins / C# C& `& p' [. o
** Input - Frame Sync, Clock and Serializer Rx# L/ l C9 d% w7 r
** Output - Serializer Tx is connected to the input of the codec
" j+ R% ^* Z3 C' [7 E3 G*/
8 o1 ]6 _ O+ s- ~1 nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; L+ f6 j5 ~' v2 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 ^3 L) t8 y) j+ b* P# jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 R" q& x9 Y5 e3 ?8 G3 T% `. g2 V
| MCASP_PIN_ACLKX
9 q$ b0 d+ Y- Y' f| MCASP_PIN_AHCLKX8 T, M, {" c1 A7 w" j5 k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" c. f z8 _5 I* t% C$ PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! T2 v3 G8 G8 ^1 S: ?% k| MCASP_TX_CLKFAIL " j' \# i) r" I) p' k
| MCASP_TX_SYNCERROR& x* Q5 S1 V7 i; B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % h) a- `6 t8 \% G/ [' Q- d& O3 [9 c, v
| MCASP_RX_CLKFAIL" h8 N a4 v" ]
| MCASP_RX_SYNCERROR 0 H1 C" F" X. h$ q
| MCASP_RX_OVERRUN);
/ d6 i" z+ P' v* i! _# {/ v} static void I2SDataTxRxActivate(void)9 Q0 L) h& z# \$ n. ~1 g1 l
{
- g& m3 q M! P# @/* Start the clocks */
: M y8 f: a& w: d& ^% fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ e& |" i' G, U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( E' V3 @' a3 n- @2 ]+ I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, l3 B9 }! S! n+ t6 C( R8 I. SEDMA3_TRIG_MODE_EVENT);
; |6 \" s& S; F# U6 e* g7 u4 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 ~/ A: e* P! `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 u X) L, P% f' _- ^2 g, S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 z5 I" k6 k5 n' s$ T) ~& ]% y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% M& N, C6 m. H; S+ d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& Q q0 E: c8 P" n5 HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 `! g! W9 U7 j: ?1 i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- Q' G! V1 J# u$ a9 @
}
, X5 U& K' _6 k) n) K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; E5 ~3 n( H9 Y8 l% h
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