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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," d+ a& w$ F# N2 ?6 x
input mcasp_ahclkx,
$ Z( p7 J( V# A( E* A5 t1 w3 `input mcasp_aclkx,, Y3 w$ H- V- p. h7 A
input axr0,& e5 J t% X6 N( e( {
; C! v* n1 s8 y
output mcasp_afsr,
3 c, x2 C/ T7 d, foutput mcasp_ahclkr,# i, H3 n9 T& P$ e9 e X0 _5 d
output mcasp_aclkr,
$ ?. [* e x9 |3 c- koutput axr1,5 {3 n2 {+ j) f
assign mcasp_afsr = mcasp_afsx;
% q9 F5 u# G! `; l5 T; y; q) uassign mcasp_aclkr = mcasp_aclkx;7 A/ f& N! J+ `/ B D( d5 M. R
assign mcasp_ahclkr = mcasp_ahclkx;
8 p0 {7 o1 X% B" P/ Zassign axr1 = axr0; d; W5 l7 y3 |$ g3 j
$ P6 R+ B$ \( A, c9 r, [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . J! |- d+ ?9 A
static void McASPI2SConfigure(void)
& | B$ f; b$ |. W1 b{
" Q2 ?$ Q& H4 S- oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: Q7 h7 B5 ^7 nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" f. p9 J$ |/ [4 T7 O% mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ L+ f& @& U l5 C. {' OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 l* c# q" e6 p5 N s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. L6 ~7 @3 ~: ?9 O
MCASP_RX_MODE_DMA);
" R/ i% P, u/ RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, v! r5 s6 w% h6 o: @" Q1 M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, ^" C0 P) `, k, l+ k1 hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* d% Y3 R a) p: A2 m. @; MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- p' M* V/ w; F9 t7 S$ QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* z2 }9 x9 S i. ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% ^) o$ j' t4 X6 O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& `! f1 |/ l9 S5 q$ [. ]4 b* W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " y4 U. b3 e! L, `) T' c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 f* k- A" l% ^9 i3 u5 ~/ l: H$ c# K
0x00, 0xFF); /* configure the clock for transmitter */
( @8 `$ E1 [: `# e# q% u! pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 Q; ~! T1 O; p5 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - j$ j4 L/ s- v4 `% f. P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. d3 _: ?0 S' }
0x00, 0xFF);5 P f0 g3 X7 N F6 b Y3 ?' `
$ ]& d" @' q7 a, |, {! q/* Enable synchronization of RX and TX sections */ + U6 g$ g, }- n8 ]- N5 g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* t1 Q/ g8 h! D c& i8 A2 LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* k) y1 _* z+ e a; Q2 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. P6 h' U6 O9 T) x8 {" l** Set the serializers, Currently only one serializer is set as4 n( ~7 ?; K8 M
** transmitter and one serializer as receiver.; Q- K C& v. R7 {+ ?% o; R8 {
*/
; E6 y" I" e; H) z: i p- _- GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& i7 d9 q. [8 p! KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 R" c" k5 w: }7 L5 S& _
** Configure the McASP pins
" }, ~8 X( A+ i+ k** Input - Frame Sync, Clock and Serializer Rx
; L# B! f5 _( }& T1 z** Output - Serializer Tx is connected to the input of the codec ' H: {- @/ O' e. M c5 ~1 M
*/
E! b1 }5 y$ T$ tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 `/ C* h P; w/ [' T8 d# ]. VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 i1 u& H R3 p- ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
V1 ?" l$ L+ K }6 A& N. }| MCASP_PIN_ACLKX
: ]! P7 ^9 i+ f. l- b: W$ Q| MCASP_PIN_AHCLKX4 A/ w, |; f( f/ J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 D, y# h' }1 J( mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 q& D5 D% z5 l: y
| MCASP_TX_CLKFAIL
7 X9 y8 Q6 k/ Z. \1 i- X$ Z: V| MCASP_TX_SYNCERROR- {8 ]) L, U8 ^2 r9 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* U" L) V5 j; e0 T. _' i( b7 d e| MCASP_RX_CLKFAIL
p) @0 o! }9 E* N2 X; E1 U| MCASP_RX_SYNCERROR
! w7 O) f* Y2 W4 s| MCASP_RX_OVERRUN);
$ |# R/ \! u) J} static void I2SDataTxRxActivate(void)/ ?, V- y: |8 ?& {) L) D
{7 w. S1 @+ @; l r+ ?: s5 } K5 M
/* Start the clocks */. W" q9 p' p" H1 P& C/ g. _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ g$ B; }! i( }7 ^# d: y3 _( OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: O' h% \4 @6 W$ l) [" S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) D# A f4 P& S9 S' \, J5 ^EDMA3_TRIG_MODE_EVENT);
% s9 g2 C V7 F2 t$ X/ k+ iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 e3 t0 H9 \% OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; i# Q7 H, T* e% { o% }' i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 P# N. {9 o2 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. i8 J( o j6 Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) g4 v7 H$ u$ ^9 A1 a3 `8 v' GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
E1 \. g# W4 L, wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 x+ S" v$ a; T) h/ @' g
} ) P6 |9 z* k' `4 R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 K( f/ e) j- g+ }: g* a _
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