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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, Y' l a% c+ c- i/ K
input mcasp_ahclkx,
5 ]( j" J; ^* x j* h3 s7 ~input mcasp_aclkx,
) s0 K1 E2 X( a, m8 W3 Finput axr0,
2 {: \# S' E6 H- T6 Q( t# x ~
& K. q" S' T I. _" O) S- ~ c" h" Aoutput mcasp_afsr,) N# p1 E7 |' x1 d
output mcasp_ahclkr,: q3 o6 T( n( q/ Z& D8 a
output mcasp_aclkr,) E# D! `. ]" F% _; Y X1 ^# o
output axr1,) i( S, f" n# w- H
assign mcasp_afsr = mcasp_afsx;
" G5 W8 P- i( I9 Bassign mcasp_aclkr = mcasp_aclkx;
6 ]* t" g2 ]' D2 E, Rassign mcasp_ahclkr = mcasp_ahclkx;
3 z* x& m. L2 P6 `0 G6 F% S# _assign axr1 = axr0;
2 B4 x4 `* J, e: V8 _5 i/ C" D$ F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) T! Y( F3 H, D$ J1 f' u4 \
static void McASPI2SConfigure(void)3 H9 ~# ?, i2 B2 O
{
$ h( k0 B. p# W( I8 M( o; cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 h, f$ f+ B6 q; nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 ?2 l# P7 Q* ~ j/ T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ ^( h( _# @, c+ z2 k: D) qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; C/ j/ B( S' l9 `1 z% b! G7 X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' R/ _! s* n, x: D) a R6 p) h- f
MCASP_RX_MODE_DMA);& ?2 ]6 ]9 [% a2 p# z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 n3 H& Y6 n& }8 AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# y2 _: [6 B6 s% b3 CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( w, j( n; t- [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, F" r) m- U" y3 F6 p# y# a2 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
J% J- m8 D5 o- x; E. |" H4 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 v; W) X% l: J2 w6 [* x7 c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 D3 r g1 t1 i7 W t7 t4 D& O+ jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 Y) t z; a4 s' p( b) \$ o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 c ~" s8 N" y0 S2 C R- O
0x00, 0xFF); /* configure the clock for transmitter */( H/ C4 V3 X5 T8 {( C3 h! ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: G7 c8 s V; a% `* b# n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( r6 M3 y! {. O. Y4 l9 r2 s* WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; g) q, w: k, h- k# U0x00, 0xFF);
% M, `& D' A7 R. [ ?' c: a+ A2 S1 G6 M/ J
/* Enable synchronization of RX and TX sections */ 7 \4 C# a* w7 }4 }/ E7 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ D( l. E8 b" O& q# u2 s9 S7 Q# I* GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 m: s1 Z% p+ d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ U; |5 x4 W$ i7 q( n
** Set the serializers, Currently only one serializer is set as5 k& f' N! h- i" w1 `7 ?" p
** transmitter and one serializer as receiver.
' i' r- m! z$ {+ K*/
3 _# }: A9 Q9 pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 C# K: B9 i. z3 e% hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. l' A u" M, @; c2 B5 H
** Configure the McASP pins ) V; S/ s% J" h" f4 o
** Input - Frame Sync, Clock and Serializer Rx
8 V, I% ?* k" t** Output - Serializer Tx is connected to the input of the codec
5 o0 U4 g' T0 x' ?4 |, d- N*/* }; @2 }4 @3 @0 A0 u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 G* z4 N$ G; o% ]7 o8 I7 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 J% X( {- U( q7 `: MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 K {6 m. I. D
| MCASP_PIN_ACLKX' j l, V: Q; S0 Z
| MCASP_PIN_AHCLKX$ g7 m: f9 w- Z2 O) C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 n1 K3 |7 |) S f! f. ]) C; f _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* h6 g4 {, |7 E' q3 E! y| MCASP_TX_CLKFAIL
" r( q2 t+ X& K4 I| MCASP_TX_SYNCERROR) U( t2 n( I7 Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 i+ @# N+ R7 C/ ~/ l
| MCASP_RX_CLKFAIL
4 g0 r- [0 }8 p- J! v, ~2 ~| MCASP_RX_SYNCERROR
( l2 S* ]0 s+ Q5 W6 H% {| MCASP_RX_OVERRUN);4 H& o+ Q. {( G1 k
} static void I2SDataTxRxActivate(void)
, W' u9 {+ y( }7 ?- F" @! O{
' r" `- ?" R* [8 x/* Start the clocks */9 B( ?$ \ C, w" Q; x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 I& Y f w2 }* `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 b- @# l0 z: ~( |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. j k4 A% I- a! g
EDMA3_TRIG_MODE_EVENT);
2 C' w3 k, |6 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, {' W* G% n3 s: f/ hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 O5 x. i; w: j+ x% {. d- E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 {: k+ m9 [* Y% BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- L# `: F" r% [. ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! b; p; O! h& N9 n' I: D" P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. ]. ~9 m* P' X- K. c. I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 P8 m# a e! v; S8 x0 c* u} * U) t5 X+ c9 a+ @! s' y( x7 _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 J1 p# m9 H1 g
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