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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" O2 r/ s! T- ]6 Oinput mcasp_ahclkx,
( F# W6 v# G& ?- S6 {6 [ ginput mcasp_aclkx,
! h9 | z( B0 e; zinput axr0,
* h; V# t7 K9 c+ W4 }! D0 o% w) c4 V+ ]; K: p0 s9 q
output mcasp_afsr,. [- i% d5 v1 A" E
output mcasp_ahclkr,
: h8 k5 m [* z' @% H6 a- w- Z Soutput mcasp_aclkr,
. g. Q3 W# j' a5 m3 ?# l' ?% Boutput axr1,) M6 R3 Z4 j' J# Z/ m% l
assign mcasp_afsr = mcasp_afsx;/ h" s4 b4 E2 ?+ e* x
assign mcasp_aclkr = mcasp_aclkx;
% Q, g8 D& \, P0 A# y4 e7 O, Fassign mcasp_ahclkr = mcasp_ahclkx;
5 ?- @2 X) I. b& xassign axr1 = axr0; + E3 O; A6 M. d& [9 `
7 q8 D7 k$ j5 ]. G1 ^ f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! J1 C C: y" o! R# X6 d5 }. m
static void McASPI2SConfigure(void)
& n6 F0 K: I- U3 p9 |{- p8 e* a& V0 W, j/ R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- x) B( p# G* U3 M' Y; v9 Y2 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 n% a7 m$ G3 A1 W" DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 n7 @5 x$ s: R5 j+ S: X' l% H0 Y; Z! s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ w# E0 A6 I8 w X, C. \+ vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 V( l( {5 `' [/ Y' k! ^; ?7 V
MCASP_RX_MODE_DMA);$ c2 F. E3 w$ E! c1 Z3 a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ x' r. E+ y9 x* G# z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: i' i- R4 Y9 }4 I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 }4 g) V$ e2 q/ T/ j; [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 d5 H* {7 m7 W; j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 M7 v i( I M6 Q+ w uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" C+ A" b& G; @' A8 m& `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 u, C d q' hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& r8 v! k, `* f* JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ T2 J5 B5 P+ K1 y: f" Z6 ]5 G0x00, 0xFF); /* configure the clock for transmitter */
7 L; s2 P y4 L5 r1 ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( x) X+ k2 q! R. b, Z# Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( M0 {9 R% Z; K' Q/ YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ s* Q9 {2 U4 [# `/ r1 r; \. w0x00, 0xFF);
) Y% q' \& |1 \9 `7 r+ h- h6 R+ T/ f) B. j
/* Enable synchronization of RX and TX sections */
3 ^/ O+ z( @9 yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% v( j3 n% o8 IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) ]! @5 ?8 }& S1 p0 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** C( d0 M# l2 U+ R) U# p- V
** Set the serializers, Currently only one serializer is set as
$ [+ \- e6 Z3 g1 W- c** transmitter and one serializer as receiver.6 D: T/ g! F; t6 n* e$ Y' p1 `
*/# @8 |- [) H/ m; H9 G5 N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" a1 E, X3 h* h! |! [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( [; x3 l' b- ?5 f
** Configure the McASP pins , A1 T4 u) L& z' ~$ _! r f+ s
** Input - Frame Sync, Clock and Serializer Rx
- b6 C' C% s# r3 z. M& F** Output - Serializer Tx is connected to the input of the codec
! t* p; m% \- h- \" Q- _*/+ ?/ f$ p0 }6 T( \, z# p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# x, ?( @5 y1 V. M7 D& d* S+ ]6 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# F/ C/ R4 N" {. {0 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 k- c0 l" p( d- ^7 B3 z$ i; D| MCASP_PIN_ACLKX/ O3 B9 s/ f# f m
| MCASP_PIN_AHCLKX
* Z h0 H( [. A; }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 q J/ c& `& S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! I- l2 t6 F9 k8 D' W# d! |* V| MCASP_TX_CLKFAIL
4 ]: C/ J: g$ ~2 T| MCASP_TX_SYNCERROR2 L% Z6 i% \! g) D7 o* f( p9 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " U/ [4 w* f- A h
| MCASP_RX_CLKFAIL( c4 p6 j4 p1 h% @- Q
| MCASP_RX_SYNCERROR ' n+ M% R! t7 V' ?1 ?
| MCASP_RX_OVERRUN);
+ w1 ?. P$ s6 ~} static void I2SDataTxRxActivate(void)
4 q1 \0 y6 h) L' k6 B* I' M{
, B/ {7 f3 f) r8 C; Q/* Start the clocks */
5 n- G/ L2 y/ t6 i. l1 T% VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; v- _) g4 H. Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) E% J, l) }# J' o, l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 ~" R7 X! N1 iEDMA3_TRIG_MODE_EVENT);
' }9 y: [8 S: R! }& ^3 M' DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 F7 K$ U9 p' U9 w9 q1 c/ L+ o2 G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) w% H& Q* w8 S. y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
k, [; l4 w: `6 g0 y, l7 fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 c( E. a5 A" e8 u" y# {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 R+ I& q& W7 F& u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 z0 x0 B2 M. KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, w. N7 Q5 F' e* u& W}
) q7 [: A2 C# l* E, X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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