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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 ^: R6 ]9 u6 F7 ?% Winput mcasp_ahclkx,
$ A. I5 h5 U+ T9 Einput mcasp_aclkx,
& e z( \$ Z" Dinput axr0,
- C2 q& j) J) z% i: ?& _& z: f& u: d |& }/ s$ U4 B7 `" w
output mcasp_afsr,
8 y* O$ T1 x( P$ R9 {0 g7 Doutput mcasp_ahclkr, I7 Q. G3 u8 A# }% q
output mcasp_aclkr,4 n0 i) [! D: K9 K4 w9 [4 h
output axr1,. _/ C" m# Z+ L$ S5 |
assign mcasp_afsr = mcasp_afsx;) w' q3 a6 x- i" G( S
assign mcasp_aclkr = mcasp_aclkx;
: f4 u6 G7 k4 O+ S" _# C/ \assign mcasp_ahclkr = mcasp_ahclkx;" i; q5 I& a6 ]) w- u# x# X
assign axr1 = axr0; 8 J9 V: T) Y3 k! z- M
l% E K5 |0 f% h* g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # ^2 b* g% C$ |+ M. P, |
static void McASPI2SConfigure(void)- ]. c, f7 V) H* E7 V
{
q' U" U1 q/ Y% oMcASPRxReset(SOC_MCASP_0_CTRL_REGS); [8 \! p: `# ?, ]* q7 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( p4 b& U* F, {4 r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& Z8 Z2 w" p( i0 B5 _5 M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( l- h0 p( b( s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- {$ L. r' C, |: D: q' nMCASP_RX_MODE_DMA);" E& S' ?: j! p' H9 W+ c, {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' i' z' A D( V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. q M! ^+ e) V" L! T9 ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 _: R: W5 ~# G3 OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) J* f1 f3 M) `* v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 S) m( I, Y: R8 v$ b! b3 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# R3 ~" y1 K# R; o6 ?8 J7 U1 R6 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, X5 S# M9 q' m6 U, ^1 v8 eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : O' U4 U: p ]: I) G! n4 Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 G4 k( B: T+ x, A9 Q0x00, 0xFF); /* configure the clock for transmitter */
) H- a8 Z( e, M# [$ \( P0 e# vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) \3 A4 `8 v0 b; [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( f: z8 K3 k2 g. o+ u; gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 a, w8 g0 D8 |0 e
0x00, 0xFF);
1 S" u( r3 v) c, ~) L8 p7 _' K& x
- y/ ?+ }; r- i6 u+ i/* Enable synchronization of RX and TX sections */
4 Q8 D7 i- f1 `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& T1 V4 i* @ J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; Q7 f% U- [) \/ D6 x; v5 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 s4 Z( _! p2 }* b7 a7 g, `+ T0 o
** Set the serializers, Currently only one serializer is set as
% {) \6 p+ [1 {, s** transmitter and one serializer as receiver.7 R$ k$ x* [9 I
*/3 t# ?5 N. x, g% X, y/ g+ _( O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' G% x* f0 c$ w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ K) U+ b% V% Z/ E" U" a M
** Configure the McASP pins
2 k, y) g# f! I- t& C( O7 ?0 s2 O** Input - Frame Sync, Clock and Serializer Rx# p& }' B! N9 z! p) H+ k C
** Output - Serializer Tx is connected to the input of the codec ! O7 d/ c- L# A1 V* r' G( X
*/ x# I8 j1 `% m. M( q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 M4 j. R5 _# C4 q- N" h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 B' d8 j1 E6 q+ n( |* jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 j U. ?7 X, a3 Q. T; H, q
| MCASP_PIN_ACLKX
% J/ d9 c# J* H: x3 z| MCASP_PIN_AHCLKX
+ ]+ E2 H1 ?) [7 I4 m6 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 P& p& G6 W" l8 k* j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 | H5 D6 N# O) i: ]5 a! N: p| MCASP_TX_CLKFAIL
. {& ] H% S! T' r& J% @5 X! L| MCASP_TX_SYNCERROR
, Y2 E) H& f0 w+ |2 l1 ?9 |8 U% ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 t/ l; d+ P z5 j7 |7 P( M5 {3 O1 v
| MCASP_RX_CLKFAIL
) K7 n' A- |1 }. ~) M h5 d| MCASP_RX_SYNCERROR * r1 ]6 F3 i/ `; p
| MCASP_RX_OVERRUN);7 @) B: ~0 ~6 C6 `2 R7 `+ I, O
} static void I2SDataTxRxActivate(void)2 m5 c" ?0 j$ M4 U% f3 h
{6 P4 u( l- Z" L' M: ?3 A0 v9 w$ I
/* Start the clocks */
- K1 W s/ n/ sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" @2 I2 C/ t7 x) h) y0 \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 E2 E6 b5 w7 J0 }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ W. O! o9 d6 w
EDMA3_TRIG_MODE_EVENT);
5 g# x- G& O9 ]3 d) J$ bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" |2 r& C* w! n4 E: dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 Y% t+ z: W- V! [$ d; mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 ?9 y! K) @) ]5 l0 S# z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* D- b8 p! H$ `: }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* n9 i& ?. Z/ W- P7 Q) M' C$ x9 W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 T) _+ d0 h' e6 v- i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 p( g% ~: }2 y
}
2 m" P( M! H# W; `( b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 N+ S! C# a o6 J2 V$ p4 O6 Z( A8 X
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