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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. t$ Z& s9 `, w( t% o* ^
input mcasp_ahclkx,
! F( n6 f* t8 ^$ Qinput mcasp_aclkx,
& `* X7 H2 k8 |) pinput axr0,/ E* D* ^" Y3 i% C% r
# _: i" i' F: c/ x( ^' routput mcasp_afsr,
9 k0 |5 u" C& m# B' Coutput mcasp_ahclkr,
' K& i; J. N& x$ ~: foutput mcasp_aclkr,
0 C( P# K o. z, n1 w Aoutput axr1,
0 P# Y0 w; G2 A assign mcasp_afsr = mcasp_afsx;
/ j) j1 C+ {/ ]8 J/ M# O. C0 t" v! W, Vassign mcasp_aclkr = mcasp_aclkx;
) H8 V7 s- k( r; f1 hassign mcasp_ahclkr = mcasp_ahclkx;
% s9 M- c4 q) Passign axr1 = axr0;
+ {* G+ i1 e# `- B
9 S4 L [/ f) y7 V" I+ p: [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% _ ^: I8 X( ]static void McASPI2SConfigure(void)
4 b; z9 a; Z; d7 m/ u{
8 ~- ]0 z0 F+ h3 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" H9 {3 Y) a; v- }8 LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
~$ n: ~* c4 m N% a" ~! K% GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# P1 E% a: [7 r! ~1 q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" X5 w4 x- _: N# a1 o( fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 K+ |, A' b% ?* ^9 l/ u
MCASP_RX_MODE_DMA); F0 @: c) ^$ u" N$ U$ X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 P! g" J* v& U1 ?# {8 {% U$ aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% P% G1 p/ b4 a2 r6 cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / e- \* r. D1 E& o7 z0 b* Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! ]. V4 {' ~( _2 E, x( b1 q0 jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * f) E1 W6 V9 E2 E5 s* \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 S% ~' |/ T* q! e0 k( kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 T- W+ m# w# T. i. k3 l0 L( c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 S4 q% b' P: a6 k" u0 X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ _. d. \3 R* Y. s0x00, 0xFF); /* configure the clock for transmitter */3 b5 [' y9 |6 X$ Y5 Z. u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 J* J& j# c4 ^" Q# h' r jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
S+ N Q, \( [; C' J# FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ _6 D4 v2 Y9 I; b% U5 n0x00, 0xFF);
7 a" j! H' Z0 I
/ x9 k7 {% T' M2 Q/* Enable synchronization of RX and TX sections */ . E/ Y9 {) d6 F& `4 ~/ o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' s' y; v5 j2 V7 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; Y$ }' y/ c+ y- bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ G6 o$ I' w; r9 ^0 B9 D' M# ]** Set the serializers, Currently only one serializer is set as7 ^; Z6 f* \1 h$ P
** transmitter and one serializer as receiver.( C* T) j1 F$ a/ Y/ z9 h/ y% k. g
*/; x. h' O/ H. W( g; k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 L# D* V7 m3 |& N: K% a1 m* ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( j: J4 X5 e6 L4 I* P/ D
** Configure the McASP pins
2 n5 p8 B% F5 U, r: ~** Input - Frame Sync, Clock and Serializer Rx7 L. c, J O& ^0 D- `
** Output - Serializer Tx is connected to the input of the codec ; F9 X5 _% z2 `; K$ D) `
*/1 F- w0 _1 T9 d& X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 I) j# O9 |! @, z8 |( H$ h8 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& W$ k5 u3 I' u$ KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 S$ _5 W5 H3 || MCASP_PIN_ACLKX1 X. A" ^# ]( V. O" b) p
| MCASP_PIN_AHCLKX
" V8 Q3 ^5 i/ o2 b& F, B' j* r; T- }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( L: A8 v7 i- n6 K2 VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# @! u$ u1 `1 W: I& Q" ?& ^| MCASP_TX_CLKFAIL
% V$ C8 Y- W0 z% N! R6 _3 L+ {| MCASP_TX_SYNCERROR9 i" X) i( }) i- p# ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * Y3 e( z3 M3 ]3 g1 L. p
| MCASP_RX_CLKFAIL' S1 y" V/ v- } h* v4 Q
| MCASP_RX_SYNCERROR 2 }* F2 L, l% T
| MCASP_RX_OVERRUN);
' Q4 C& w! e3 R6 a4 G* D} static void I2SDataTxRxActivate(void)
|7 T8 l' s) g; c; ~) Y' E) T{
0 u9 d& y( S; x3 G- f/ L* N/* Start the clocks */7 [1 f. ^9 K/ K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* V1 ? j3 X0 s' s% O$ o" ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 |; m% `6 K! {# J8 B5 B% L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 a/ a, S# a2 u
EDMA3_TRIG_MODE_EVENT);
4 q) t0 i+ W OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ j+ H# _0 w$ s. { Q3 `" ^) aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 C" `! O7 h' J# _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 }, K5 l9 \/ J: o( ? m) _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- B" k5 O( }. \6 o S% Z. ~5 C% _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) U+ m: m) O$ f b& T+ m8 W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ o, F4 B0 Q" v. s0 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' d8 x: P/ \: P( B3 c8 b} & _) q' W6 ~: Z4 D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , w4 |" e% Q/ B7 n; q. ]' l; M: T; `
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