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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: x9 z& }. g7 w" s, W4 \ K3 ?; linput mcasp_ahclkx,
, R( L* w0 K0 l$ p% Sinput mcasp_aclkx,
% i9 l; A$ B3 zinput axr0,
+ ~ l3 I+ u" y% f
7 X9 H. L! B/ i+ H2 joutput mcasp_afsr,& x$ Z% Q5 J4 b2 C. ?% i* ?
output mcasp_ahclkr,
: J ]: y9 q" e2 t, O e8 Uoutput mcasp_aclkr,
% G& S" v! Q# ?output axr1,
) g1 |+ l$ E+ y assign mcasp_afsr = mcasp_afsx;
& f) i% |/ `4 S+ G* E+ Lassign mcasp_aclkr = mcasp_aclkx;
; N& l8 t3 `5 E8 jassign mcasp_ahclkr = mcasp_ahclkx; k" W2 O$ P2 W5 Q: [- Q- r
assign axr1 = axr0; ) ~0 C7 o, C: m+ ~) E' E# |* `: O
4 f/ C4 i h" ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 r) m! e, l* \- ]) Q, q, [4 ^
static void McASPI2SConfigure(void)' J( W: k" Z: N8 W( r" P) T( |
{$ n& i# b2 n2 ?# F1 P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: S: q! m) k% e! k+ S1 g! {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 H0 E% H- J- X# M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% M" u/ s( U, R- [3 c( Q. G% `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 t0 U+ J& ?7 m/ Z6 }7 N, }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 n0 Q- L0 p7 b+ L* B8 j0 e% V$ P
MCASP_RX_MODE_DMA);+ y8 j- w0 u! q5 @4 a8 [" B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! Q2 K8 Z4 i' K. ^% K8 d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& O: a& v1 x% ]" ~6 T2 rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 W) l! e' C- Z! k3 P8 ^" D, X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: L7 u' P7 C g: l5 [8 a3 J0 u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% j! j! D) J5 J* |0 |* G# f$ jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
z! d: _$ P4 d, q; `7 wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 ]1 p# c; t8 k0 z3 R+ C }. p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 O+ m( C; T7 ^1 X& K! b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# j, t! h( u. r: S8 k
0x00, 0xFF); /* configure the clock for transmitter */1 @6 R6 y8 K4 c. ^3 a8 e/ O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# m- I( o Q0 G0 o' i( _1 i+ H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 p; u, w& L1 x! V& I. T; o, q; t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% M. J( X/ S" h" i2 n3 S0x00, 0xFF);& ~" H, {7 @4 a7 L: S9 }
2 d4 d( q+ w0 f' i/* Enable synchronization of RX and TX sections */
7 n. D) A/ o8 y' @0 M: sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! e# l* @' f A/ \, b7 } oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" a9 i* ~" }4 L5 J0 |# ?8 {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ L T8 \+ } z
** Set the serializers, Currently only one serializer is set as6 C* S5 T! q( R+ T5 d. S1 F) S
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 M5 c y: { O7 b4 P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! D8 q( S+ L1 i5 F1 ]3 C2 n
** Configure the McASP pins t4 w5 l" h, X, o
** Input - Frame Sync, Clock and Serializer Rx4 Y# ] p4 v5 w- r2 J
** Output - Serializer Tx is connected to the input of the codec
& }! G, p4 P/ a. n" ~( j*/' n3 t3 {. j$ |1 Z2 X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 U, y1 _+ T* T( L* Q) R8 yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 j% T* v) T5 a' ]: k1 E0 k: u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
A( z9 B' s6 G% m% d! r1 ]| MCASP_PIN_ACLKX
! ?7 m s: D% S$ K' n, n& `| MCASP_PIN_AHCLKX4 Z) l! H0 p6 G+ q5 }; a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& M& G1 N. A* G' I, C& rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 d# ]' R+ W# f! R+ y, B% ~1 f
| MCASP_TX_CLKFAIL 6 I0 X, [! C- a
| MCASP_TX_SYNCERROR
J$ `4 i1 }* ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - t* m o! e! |. c1 m/ I6 Y9 C6 p
| MCASP_RX_CLKFAIL2 s! U% y* N/ a, Y& f* J
| MCASP_RX_SYNCERROR ( _. I5 f, ?) k0 x* p2 C
| MCASP_RX_OVERRUN);
& e8 S7 m' i* V8 o, T} static void I2SDataTxRxActivate(void)- e: a* a* S p) F+ `& D( G. x
{
4 _8 h2 m" E. r" Z. d' r7 V& ]/* Start the clocks */+ J- F8 i- z6 J+ [4 w3 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- @* f3 l9 B1 D3 d* ]; CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* ^. ^% c9 t5 l6 W' [4 i; A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, m6 q# ^7 k# O* V/ _) `# K$ q$ ^9 v
EDMA3_TRIG_MODE_EVENT);" h$ S; |4 X+ }$ Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( s9 m5 p" t5 s" E. _& X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' S; {/ W1 H" R5 r0 L2 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ j) `( t* C: S5 z) R# T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ m9 J* m7 Q, E9 U. T P$ y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ A& k/ j8 G; T" Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 Z7 F* [6 H- E6 ?' H* o$ ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 I, y F) l1 {. Z& Z6 K, u
}
, o9 T9 Y, Q4 V7 }4 U( k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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