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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 ^9 q! u% A6 t) ]+ l
input mcasp_ahclkx,
5 v( C* E! R- d- B: H5 Dinput mcasp_aclkx,
% e7 u" l9 Y3 V3 ]input axr0,
! C$ c' d, f) w2 ? x0 d. v6 ], e$ {
output mcasp_afsr,: r% d3 I" X1 J: T7 R0 R- J
output mcasp_ahclkr,
+ z M& l: ^& ~0 M7 b7 houtput mcasp_aclkr,
3 H- Y+ V5 [- E% t7 d# h, i3 B, D) ~output axr1,
/ u+ ^: p3 ?' q1 J assign mcasp_afsr = mcasp_afsx;
. O9 C- P4 u( p6 Wassign mcasp_aclkr = mcasp_aclkx;7 v e/ w5 [% k3 M; ~2 x, j
assign mcasp_ahclkr = mcasp_ahclkx;
2 Q4 \* `# v- n1 yassign axr1 = axr0; 5 X* H$ `/ L; m# T% I x
: _1 Z& U% W( b( I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . r% S' O" U% i9 X1 ?' c% y0 K& \
static void McASPI2SConfigure(void)+ T2 Q5 C- q. c( d, q7 Q+ P
{
6 a: [( Z: N! T$ eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# D3 j( q$ L7 P jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 l& R1 ^$ P' e% N0 M9 ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, l$ p& o+ d8 E3 q; YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 m1 w: ^! a1 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& k) @% j8 @) N, ?3 {+ ]
MCASP_RX_MODE_DMA); }5 s3 a* D* i. X. Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ K, k% Y) L1 z' ~) ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% ]' c. b( {: ]# C* ?3 u# \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % S1 L- q1 ?7 u0 O: `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. `+ U) }1 D/ u" V8 Q, F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # C% [) W( }2 R$ b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! X, `1 D& p2 s" ^* ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 v4 j% q5 t0 k3 T! k; U: ~. cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); `: ?( a5 p i5 l' }3 S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 f$ U) t6 t& J8 v+ }0x00, 0xFF); /* configure the clock for transmitter */' H4 `$ z) Z* R9 O, V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: z5 Z5 g: K& n( k; aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 h! f0 R( J% @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 G8 A: ^7 D! X/ ]" h1 W8 z. Y" [0 U0x00, 0xFF);7 a- s: }$ d) V, N8 ^1 e; N
# b- M9 z7 ?8 h5 a/* Enable synchronization of RX and TX sections */ ! @7 ^' U8 F: g- G) q9 J: b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// K1 ~. q8 C3 N3 S1 e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 f3 ?# p6 g6 E- L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ F8 B- j- O9 ~- s) z3 ?: q** Set the serializers, Currently only one serializer is set as0 y4 Y( c. h$ [
** transmitter and one serializer as receiver.
/ I1 @: o$ u! h# k; p3 p*/2 Z1 K- N) x. T; h9 }% @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 H7 Z, N) x) t; G3 s' MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" a2 g' I( n; f8 N0 o/ V" n! {** Configure the McASP pins
5 q+ H: {# ?7 D. I( W) X** Input - Frame Sync, Clock and Serializer Rx
. Q4 o2 { E, G9 j6 V4 u0 Y** Output - Serializer Tx is connected to the input of the codec 8 z0 k) s* r3 M; ^7 P
*/
m( `" b) d2 _8 p4 ?: rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ } Q8 u, B4 P* a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ ~/ b6 T1 k) G* ^2 MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, j0 A& H' g6 N- h9 J! [! S# Y! Y| MCASP_PIN_ACLKX
) [5 K3 ~ M; X" p' c! w/ M% Z6 o| MCASP_PIN_AHCLKX
, m" w5 ?$ Z& r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% {+ v F* N4 H1 G, L$ z9 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 e0 q6 H8 E" J
| MCASP_TX_CLKFAIL
, N/ S, _) f& m( H/ L) ~" K| MCASP_TX_SYNCERROR5 u+ N: {# `7 [" i) j8 I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . E9 O7 S7 D0 g7 e+ A6 Q3 X
| MCASP_RX_CLKFAIL; `. Z. D* ^- l* d$ j
| MCASP_RX_SYNCERROR
1 d1 M) i0 G( s' ~! h| MCASP_RX_OVERRUN);
! M6 x G- {8 O8 T} static void I2SDataTxRxActivate(void)) p C5 y) q, W' A) N
{) ~6 x2 |5 _4 g1 o
/* Start the clocks */: C0 K% d2 z- L5 g7 ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ E+ ?; `# `; H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. G8 |1 [5 Y( G3 D- I& U) W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 _. |1 U7 ~6 S+ y' h7 S% N8 QEDMA3_TRIG_MODE_EVENT);. r C% M; E" U: c) f" g( z3 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 x7 S) p$ T3 s G Z8 \! E0 S& ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 s6 I# N/ C4 h# v1 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; W% H1 J- Z+ U; N2 o+ m. `8 AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 C% W4 S6 L/ j M- k+ M3 O. ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% v% i6 Z6 i0 F# K9 [. dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( C- o% x7 s, H- I7 c# C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# ^/ i" p! E O' B
}
* @) {. A, I/ Q4 Q3 l9 C/ g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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