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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- n3 A! m( n. ^1 _% ~, F4 q8 ~
input mcasp_ahclkx,9 R7 o$ }& r7 e/ }
input mcasp_aclkx,0 z) k" n0 c9 |
input axr0,1 j+ k7 j, {8 Y5 R ~
1 n/ W1 g5 ?$ h$ Goutput mcasp_afsr,
- y9 v+ T# M& o0 z- }1 ioutput mcasp_ahclkr,
z! o8 n) Z. w2 H- z5 d% Qoutput mcasp_aclkr,
. N! b' B4 c2 s& i7 Boutput axr1,6 k/ S5 i5 i' p$ o8 A
assign mcasp_afsr = mcasp_afsx;
' [" M2 \# L# ]6 X9 h( M9 q: a% xassign mcasp_aclkr = mcasp_aclkx;( [. g, ?) y) Z7 i7 I; b% A
assign mcasp_ahclkr = mcasp_ahclkx;
9 h( C0 b4 ~& e1 w4 s* E2 X+ \assign axr1 = axr0;
7 u& o, s3 t7 p2 ^* w5 K1 r# x4 u$ ]4 U' U# w) r# \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , W4 _0 a. C. ^0 ^( X% y: t, K
static void McASPI2SConfigure(void)6 @; e0 J& O" o
{/ I) Z8 T; m' s n' {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- }6 J2 h5 f- d3 v9 m3 U( v0 b* i5 ?3 B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 R& e1 X, e. f. w l) @! EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. r5 t, l; R; r. W: _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* W1 u7 y' T# \3 T* ?% RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! @# {% R* f( qMCASP_RX_MODE_DMA);* I% n6 v2 i# P+ t( L/ w' I& H, [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: M4 m1 _5 ~8 ^0 k0 U5 b! U; hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
o/ j4 _' D# L2 u9 s8 j4 a; c7 iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 \) X: I q" v" B: X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 f" [& T3 ~; q n RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: Z0 b; U% E0 S- k7 ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' V* s$ _ x. m' L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# ?3 y' A1 c! jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * l1 `7 O6 V1 `# M; i: b7 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' w4 E! m& l$ L) Z& k {* X
0x00, 0xFF); /* configure the clock for transmitter */
$ G) k. W7 \" \8 k+ }' H- A2 [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. W% q! P6 m% \% J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 E6 B7 C# f/ h3 O7 c9 R% s! vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 E) d8 s6 {' H4 L8 K* o0x00, 0xFF);
( L7 P4 M9 q' i5 T
/ G! p. t9 |& u/* Enable synchronization of RX and TX sections */
. t% ]- |% f9 \, ]8 `) QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ u2 Y5 A6 S! x4 Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- k, ^/ A# H0 X$ V2 m, M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! o, G8 x/ F# e+ P- }9 b" i. a
** Set the serializers, Currently only one serializer is set as
4 R4 b, y6 Z7 O" _" ^& ~** transmitter and one serializer as receiver.( U7 q( S {. P0 K$ u$ k+ R$ Z$ _
*/
- k$ K% N* A K) |! HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 S; U3 j+ a# r! t+ J. @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 y3 W8 D( |. B: i( B5 q: n8 Z
** Configure the McASP pins & {9 r9 Q5 }3 |- D
** Input - Frame Sync, Clock and Serializer Rx
0 N/ s! e0 \ r! F** Output - Serializer Tx is connected to the input of the codec - J% e4 v/ ?4 | M
*/
~7 ~$ y- f, g" f7 FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 k: B9 w% T; z% ?' IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 q9 X/ t4 n6 |% p/ `3 |7 M4 B8 K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, N% Q5 H# q) f( \* V
| MCASP_PIN_ACLKX
" c" r" J" m9 s3 c8 U" l, ]| MCASP_PIN_AHCLKX
% {! J& X' L1 ^1 D" F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 t. l9 `6 S, T# M( [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& n8 k! X( @1 }5 O# X ]9 R7 {| MCASP_TX_CLKFAIL * a+ E, f7 s* U8 v2 R( w
| MCASP_TX_SYNCERROR
; e& R0 ^# e7 O* E2 P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' m; ]- V+ X A2 l1 \% l| MCASP_RX_CLKFAIL2 V1 a( @1 {$ ]
| MCASP_RX_SYNCERROR 9 [2 c: k" L$ C: k) V
| MCASP_RX_OVERRUN);
4 C, N* U7 x6 P, x J} static void I2SDataTxRxActivate(void)
' J' I+ z7 o3 S# W$ v! u9 V2 y* R{
- f$ b. c& O5 o& I9 r/* Start the clocks */
* H% ~8 f, @4 E0 l8 d" X) pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* z: e; b- D" V" G+ h! P. K# EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// H& ~2 M9 F8 c4 ]/ g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! U% N3 e; m2 b, n
EDMA3_TRIG_MODE_EVENT);: G9 P' `7 o2 C6 b' X* G7 C' u4 F! o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, p; f4 a# K( J: p" D0 t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* U, ?, |! d/ [7 tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ k9 h) \2 F" R4 G+ W* }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 q7 }& G" a" F/ @& zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' J) p( }8 b' i5 ]7 v. bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# L0 t3 `- A8 O1 z8 `: t8 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 ^9 P) t4 @+ Y: ]& ]2 T
} - A+ T& o% R6 E& c+ c% B; G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 _8 K, u5 t9 b% \7 v
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