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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' \4 a# V& c3 A' \# vinput mcasp_ahclkx,
5 L" V5 f! T+ x% C, x' Iinput mcasp_aclkx,/ g, R) Q& v/ Y9 A) \/ @% C5 q
input axr0,/ h# [" C$ w+ h+ S* O- V
9 Y( q7 J$ H0 houtput mcasp_afsr,
4 z5 [: E1 [3 E. coutput mcasp_ahclkr,7 X9 x7 J, I: X0 s/ j+ p e
output mcasp_aclkr,
3 m& v6 n: ]0 uoutput axr1,) z% x8 }1 s; p# V/ w6 r
assign mcasp_afsr = mcasp_afsx;# m: U/ R1 S* X2 G% Y
assign mcasp_aclkr = mcasp_aclkx;
- a, T7 o5 y, k& S; rassign mcasp_ahclkr = mcasp_ahclkx;0 X- B6 u: ]3 C' Y S( `$ _
assign axr1 = axr0;
% J/ R# G$ p; w$ [( Y
' g$ B9 ^. y! y0 U6 F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 F/ S& B6 {* ^4 C, ystatic void McASPI2SConfigure(void)
' O9 e8 v+ m j6 R' Q{, G0 o; c* [9 b# e1 ^; Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 Y6 }) A- ?& v: V0 u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ ^1 W. {0 ]% Q1 D) dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 s V0 o d3 `0 y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) K6 }5 s# w9 m4 ?! x( xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 Y2 O! h! T9 f8 D$ ^- o& F
MCASP_RX_MODE_DMA);$ r( J7 G X% W% a G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 C! T0 P* G$ e. c! R" iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- _! g+ X8 n2 |: u# T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! ? p* b, R! F1 i- f& T. _7 M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! p% J3 U1 O' q- F7 VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 W% f: a# `! c" A9 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 z6 _+ s+ z/ T% ^$ n, i& A+ }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ F% W5 ]( J, TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 q/ H8 p5 @+ y1 A* Q5 V' @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( o; q. O; F! s F+ P7 o* k. s; E p: a0x00, 0xFF); /* configure the clock for transmitter */
9 I4 E0 w- S0 s1 }% EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 w- p: n5 f0 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 A' r0 C! f) `( _! X5 D# A$ E( }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ w- e: z, p+ [3 \( t; l0x00, 0xFF);5 n* q' j. t9 F: g' v4 ^
; ?1 F5 A: u& [; r( J m/* Enable synchronization of RX and TX sections */ 3 p( \; u. H! w, R2 O# j' n& a4 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! K; |" k$ y+ G* D9 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 p3 U. k: c+ z' _0 ]: K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# P' z6 E( ?) A% H! Z; R' Y0 B/ a( j** Set the serializers, Currently only one serializer is set as) x: Q9 i8 E( J2 f) H
** transmitter and one serializer as receiver.$ |" d4 A, ?$ a' T
*/# h' ?- I: z1 }7 S. p2 M5 l9 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 P+ |; ~( J% Y0 ?/ b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 x+ S( d+ ^; K& v0 T, @** Configure the McASP pins / k$ c( A9 i2 h& Q' Z9 @% o
** Input - Frame Sync, Clock and Serializer Rx" n8 _. U2 z1 @& S" Z# z
** Output - Serializer Tx is connected to the input of the codec
^$ s6 K2 M% C5 ]*/
# v' t7 i2 f* A9 s# cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 N, {) H# A1 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" {* n; l/ x; zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 H/ |9 `* R1 v/ Y- q
| MCASP_PIN_ACLKX
9 P5 {( r) T }$ F| MCASP_PIN_AHCLKX' @6 i$ |! Q7 Z. m4 H" R/ S5 e2 Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, H) P+ ?4 S# }. ]: x( \1 o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ \! x" c( M q2 X. h| MCASP_TX_CLKFAIL
% |7 J1 x1 D6 ~ t" F1 \| MCASP_TX_SYNCERROR- a+ W# a. N s% [* N% ^
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % M/ U. v) |8 R+ I( t
| MCASP_RX_CLKFAIL V# G1 C8 y$ ^" Y \) Z3 |: K& f* [; D
| MCASP_RX_SYNCERROR
% A( \' @0 _9 w6 Z4 A& ^| MCASP_RX_OVERRUN);0 m3 _! A N7 x. j6 R& d
} static void I2SDataTxRxActivate(void)/ l4 w# c; }* C4 ~0 c* y* a
{6 |+ M3 P, Y H$ _$ P
/* Start the clocks */
8 M+ \( i2 n1 TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' F O$ C- P0 n" X F G t" Q5 YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ o) ~* U* y! N2 [8 t4 C& W7 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' F6 @ ~3 L+ b4 e" w" j) pEDMA3_TRIG_MODE_EVENT);
5 ?* ]" k0 e: K; k$ d) H" A0 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) h7 [! j2 Q) @" d0 B/ k- rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- W# F4 Y# H# P7 z* i* JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 J4 W0 |& K; g& e4 y3 S8 G$ k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 {5 [+ ]8 ~& Z; i6 `0 W' C4 i8 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. h# S! |& u4 D/ G+ x$ ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 @. s& b; S( x/ q2 r1 I* O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 s0 Y2 v( ]4 a' b- N
}
4 \9 V1 ^ p; ]& A B8 F' Y1 ?' c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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