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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 F" ^" z" _" pinput mcasp_ahclkx,
" R2 r! B% P& S: [input mcasp_aclkx,2 S3 r* J5 g4 O8 z* x3 Y2 e: B
input axr0,/ \$ j3 `' t" `' G4 I+ p* t
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output mcasp_afsr,0 V/ C7 w2 k2 ~
output mcasp_ahclkr,
% S1 M& _: C4 m: K2 [output mcasp_aclkr,: x1 w" ~* E. W+ e( e7 E
output axr1,1 k) w! O4 `& U$ t
assign mcasp_afsr = mcasp_afsx;, E$ L: X, r' {
assign mcasp_aclkr = mcasp_aclkx;
9 `5 z' v U! q. @# r- Nassign mcasp_ahclkr = mcasp_ahclkx;
9 h5 o5 Q, I" f* ]assign axr1 = axr0;
+ l; c( U0 v' W" w
b. |1 `- l5 z2 c( k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 G' [) s( y& e' [1 T. ?
static void McASPI2SConfigure(void)1 a$ V! T. Q' V% @# [1 q" I, Y# O
{" x3 ^8 b' ?" s; z( ~- P4 @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! S# m2 {9 @7 b4 w* t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; C3 V( p* w. X* CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 z+ R& o% P. L7 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 S& `, Z6 g( @5 B2 H0 q* N- [2 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ w% F" u% C7 R5 Q9 S
MCASP_RX_MODE_DMA);$ L- r, s5 n" S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 C1 U) x5 B3 z, P' ]* _# }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 |+ X r4 X& t+ G/ DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& I1 j6 Y# b! N( r2 G6 _# IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ {9 z$ p ^) Q+ e; A" w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 T* N' u6 Y: Y) q8 u3 p# b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& L0 g$ d0 Q* xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 v% H k% _8 n' G. J' D( a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 W" C, k9 Q- G# j# w- Y& e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 \ b1 m- u% |
0x00, 0xFF); /* configure the clock for transmitter */
0 J5 Y" R+ s( c; T0 X: \: G+ o: eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ s: w( R* p+ QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; ~$ ]+ ^* }: ^+ B2 F5 w& V8 x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
_7 S8 N V9 c1 O0x00, 0xFF);
% u6 C8 K) @$ G: g. u! K
! `1 m" C; d$ D: d' m/* Enable synchronization of RX and TX sections */ ) b7 t7 d$ }/ @$ O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! Y' ]* |9 {9 J4 i0 W. X' ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 x; T! C& C% p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- o: T% i3 G4 ?** Set the serializers, Currently only one serializer is set as' a g& ]0 |% P" o% M+ I
** transmitter and one serializer as receiver.
) N& ?8 S. X- N*/
8 @* q8 k7 Y! f% F5 g: UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 d7 C) i2 p6 N$ a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' Z5 Y7 x( G, P
** Configure the McASP pins
1 `% R$ t6 C5 g4 |7 m, q5 @7 |** Input - Frame Sync, Clock and Serializer Rx
" \: r) a* n. A5 q/ [/ |** Output - Serializer Tx is connected to the input of the codec
4 }5 c- W1 w. _1 U/ |. y% Q: I*/
9 o% P1 s: e/ a0 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# R, m# f; n+ D2 uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 _6 c+ R6 \$ r. m" p$ N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ r% f( j6 c( f2 s# g9 h+ A( }
| MCASP_PIN_ACLKX+ n% j7 D [5 p+ m: ?8 e
| MCASP_PIN_AHCLKX* h" F5 A3 u: x+ O% N8 v/ N5 H9 N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" w, p7 D. l# O/ F: T w5 D) m9 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / y; Q8 Z( d4 p8 ^5 G7 E, T" Z
| MCASP_TX_CLKFAIL
1 Z: g& R' X2 T; W' g2 L4 C| MCASP_TX_SYNCERROR: s3 N& D! n N4 C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 C6 J, \; _3 M- _* w
| MCASP_RX_CLKFAIL
0 ^. z7 C( ?8 s: V| MCASP_RX_SYNCERROR
/ q0 w9 Z" L T# || MCASP_RX_OVERRUN);8 J5 ? u. s2 H( Q
} static void I2SDataTxRxActivate(void)
5 E( R+ P. W0 x4 }' z5 v) v{
' Y" f- _9 z" _0 F2 ~0 l, _/* Start the clocks */
) D0 g. w& `$ q" y# vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
b4 Z6 W/ K1 z. S; D# V# U) jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ n8 M9 r+ M d; L( ]3 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& S( K% \. e) z9 P/ Z! k& hEDMA3_TRIG_MODE_EVENT);
, Z4 s5 n% q2 k3 z7 v" SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 J* l: s, L8 C* N8 J* j- `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% z7 b; e# x! @8 o) j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 Z3 L$ F3 g- Q5 }- J) m- ~# j7 z) h+ d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# n. Z( j6 y, R3 \" B/ V+ h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ {3 V- K0 u( Y; G0 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: u. e; W8 k; `1 F2 t7 u9 ], P. g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 ]1 j, ]' k! ?9 {0 l/ C L. n/ t
} 7 J: Z% e5 [9 M! K0 e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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