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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# m' L |3 @- ?input mcasp_ahclkx,
. |2 J# O; T. Xinput mcasp_aclkx,: Z, q% F1 G1 d2 h2 p% K8 l( t
input axr0,4 ]/ D+ k8 i: p1 b' R5 x: N
3 Q Z# @& ?1 P5 g6 R5 i, h
output mcasp_afsr,
" b& X7 J2 g9 \# X+ @0 n0 }output mcasp_ahclkr," z' P8 |& o4 w% y
output mcasp_aclkr,0 m' z5 _. X; p- g
output axr1,9 E" X! \2 s: ^3 k( b
assign mcasp_afsr = mcasp_afsx;; N; |8 r- T% ^' c; A9 j8 N8 @
assign mcasp_aclkr = mcasp_aclkx;
+ w3 Z) D# X {& Q6 L1 `- {assign mcasp_ahclkr = mcasp_ahclkx;3 c$ @# |9 b% f$ o
assign axr1 = axr0; , ~8 ?( w( o) r: {- |
& B6 U. O$ p. V: ^& q$ s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( H; K+ z7 ^$ h& Astatic void McASPI2SConfigure(void)
% w8 }5 `5 A8 H{
# B: X% T6 K3 aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: _# J) w7 U) C& O9 P3 p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* [( s3 D4 \7 d# `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 G; v2 ~8 S1 W" ~$ e8 NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
N4 S* w$ h& @" J' P) HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( o2 \- F) R" `8 T: X0 I
MCASP_RX_MODE_DMA);
$ P6 b& P! w- g# rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* P$ G( W' `0 }% U+ _2 d6 D8 m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" \/ M! j2 D( u9 E* x1 O) q4 D! |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # C' B( E0 W) H" L+ ]* o/ X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" j+ D3 A# E5 M% M& P) p+ ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( f/ v% a& U. g& j) k6 UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ s% E$ y% y! \0 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# C5 g# P+ @9 k2 N" Y: J- YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! |0 F- [" s: C# P `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) ~1 Z2 `- D3 p5 \
0x00, 0xFF); /* configure the clock for transmitter */
& k2 z9 }, p9 Y0 G2 ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
b8 _4 y! @: _9 m1 x, NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 ]7 Z" w# D- @ @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# f* @0 N* H G Y1 I3 ]' P0x00, 0xFF);
, i/ Z* G# \2 \0 L" d Q
8 ]: J9 i' X+ |& T" D; M/* Enable synchronization of RX and TX sections */ * [0 n u4 Q- e0 ]) B! ^$ U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) s# G+ U: g! ?5 ^7 x' B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! q) C% A; o" f) DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 @* j: G# k7 c( t- U; f6 o2 i
** Set the serializers, Currently only one serializer is set as, Q, I- s# Y. i, {7 d a
** transmitter and one serializer as receiver.
' K) ~, w4 o: |& m*/
5 Y2 `+ G) L9 G- F/ G# e; d0 DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( N; B+ ~" P( [2 I3 c" aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( t5 b" x5 W2 o7 S$ [' x
** Configure the McASP pins 1 w. e0 F6 y {% }
** Input - Frame Sync, Clock and Serializer Rx
9 X: _( _6 \- f; ]6 m; p** Output - Serializer Tx is connected to the input of the codec
i9 E! r6 O. \" }* {! G5 Q*/
8 n2 K0 y" v1 X% s/ }4 a) P" {7 o! lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 c* @$ X X3 T* J* l4 g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ F; q* V' k& O) N& A. y% E' P+ d9 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& }2 I0 w; a" U
| MCASP_PIN_ACLKX' n1 Z/ J2 c4 O4 q' I8 x4 i$ v0 z
| MCASP_PIN_AHCLKX7 z& [% L3 ?* [. X& Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 c% ], V3 d7 M" }% d/ ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . S! T' {% l7 J- j( K3 T
| MCASP_TX_CLKFAIL & G+ y2 R, ~+ U- _/ c. r& U) L
| MCASP_TX_SYNCERROR
. ?( r" m# J+ e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, w: J& I; k- C8 P, K| MCASP_RX_CLKFAIL( Y; I6 R) l4 ~ t/ B; C
| MCASP_RX_SYNCERROR
9 U& z S: i- J* k: d1 k| MCASP_RX_OVERRUN);
, D- e5 W8 D1 m7 Z} static void I2SDataTxRxActivate(void)
' h `* d% Y$ ^2 ~{
+ [- d# y: Z7 h6 P4 C# U/* Start the clocks */
# Z& U! k5 \+ [5 ?, ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* x- p8 w+ k7 { ~, }5 X* Z0 q( d+ fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* |' q4 O/ @* Z1 k/ `2 F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 [# W' k: Y; e6 \) l5 MEDMA3_TRIG_MODE_EVENT);
~/ W- v. N. }8 ?: oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; l5 j9 v% [6 A' h# K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 k+ F* V! C6 P# k1 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 O6 C, Y( e7 i8 C5 x; D4 \3 G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' J6 j5 t1 X6 i& v' J( {' Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* V! t6 x0 {7 F2 x3 D+ _" j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) x+ y# h F+ X: L7 x8 m) H6 U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 V1 z; F- Q8 P} ) a4 | C5 R) X7 g3 c4 g5 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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