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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# R2 H$ L6 ]1 M3 h- W
input mcasp_ahclkx,$ s+ g' H, Y! \; U4 a0 H2 s
input mcasp_aclkx,
6 Q! w% X! m% linput axr0,
: r% w- B/ t5 i: y
2 ?% e1 c& e8 coutput mcasp_afsr,# l- W0 @+ A( |4 p8 o8 f# @
output mcasp_ahclkr,
' S8 e& F9 m3 [. z* Routput mcasp_aclkr,1 l4 j# Y! W( o$ O5 ~* \" u
output axr1,
/ L' F5 x) i0 h assign mcasp_afsr = mcasp_afsx;/ Z+ A4 d8 m, y: u. @
assign mcasp_aclkr = mcasp_aclkx;" q; C/ M* ?9 `7 C
assign mcasp_ahclkr = mcasp_ahclkx;
# p5 h9 I1 J! ?2 ], ^assign axr1 = axr0;
7 H- B4 N( U( z3 R8 V% U% e9 }. ~$ r# F9 D* w6 e; _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 H% C/ n5 U2 g. X+ t
static void McASPI2SConfigure(void)
5 l" b6 k) ]0 i8 _7 C1 v4 g{
4 k: V' _, y. v1 V# t* A/ hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 ~- O: L( c% G- k5 GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 k9 p1 r7 O% g" q- N& q# ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! h& j7 ~' W9 r: [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 n% C9 Y# X& U$ L) c" O, G; @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; _$ b! l" I- Z) I. ~MCASP_RX_MODE_DMA);
! h% A$ C+ O; C2 w% u7 y" {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 k& L6 E w! ^$ N$ s, o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 w, u/ M4 Z" a, j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: u( `: V8 i I6 |1 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( g6 Q& n: ?$ n- FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 ?' u! d- T9 t- t4 YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# ?2 t% F0 [* P; [ F# IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 T8 B3 k: Q H( ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! D* B3 G; Z3 b4 ]4 F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 S/ i( `5 ~& w5 T3 H+ K
0x00, 0xFF); /* configure the clock for transmitter */; ~, I, V, u1 Q0 A9 w3 S7 l m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 n1 z0 E$ ?2 qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : a. z1 g; o/ G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 z" J; l6 p( c# B+ m# {8 t
0x00, 0xFF);, E t% S1 C% m" t
9 J3 J/ i% E9 l. @& o7 S" c/* Enable synchronization of RX and TX sections */
# G+ I! C3 V# d7 B4 a$ e yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) ]- {! F5 u: i: r+ {, iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 F0 ^1 F* N# `' P# C; n0 F8 W* D2 }; N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! E R/ n' ` ?+ X: ]8 P* B4 r; g8 i% g** Set the serializers, Currently only one serializer is set as& p! X6 P# O5 i5 [4 C* v
** transmitter and one serializer as receiver.; V4 @4 e5 y3 J8 u/ n6 Z0 s
*/! W1 o8 l8 n, o# N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- Z1 m' ]# {5 x" G) ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. {/ g: }9 _1 c7 d+ W5 C, h** Configure the McASP pins ' P; R4 z# X5 P4 j
** Input - Frame Sync, Clock and Serializer Rx
9 q9 _0 n6 F8 Q% L( m" l** Output - Serializer Tx is connected to the input of the codec + j& ^0 \- k1 E; l3 `
*/
3 F3 E. `: a0 @" U" T' a- ~# v8 BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, g: P! i- C& ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); B" ^, A) x. g: ]1 w0 `. I6 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: G% U' Y. o7 Q9 d0 O% r| MCASP_PIN_ACLKX
) l# [3 d4 A: _& s+ f# G| MCASP_PIN_AHCLKX' X1 J7 I1 n" G- W" M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; Y1 x H. @" m; y2 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 Q9 X# j% {, P
| MCASP_TX_CLKFAIL
, s& Q5 u) J0 {| MCASP_TX_SYNCERROR
/ Q/ V E( z' x% y: s. T- m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + \# ~# l' j ?$ O
| MCASP_RX_CLKFAIL/ d( q- u% w" }& w
| MCASP_RX_SYNCERROR * Y! ~. |. p N( d6 W d; O
| MCASP_RX_OVERRUN);" Y$ Y7 k8 s, N7 a0 u
} static void I2SDataTxRxActivate(void)( |, ] \9 L: T9 V: P
{9 r8 q3 A% a9 t5 r) K
/* Start the clocks */
b& K4 t' X8 r. yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 E6 u" ~- G: F* R) RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% X5 x1 K1 ]9 i: yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ b+ O, C( B6 TEDMA3_TRIG_MODE_EVENT);
. k* V* i' {* f5 T6 K7 \7 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 i: ?- _! t+ c3 a& b9 j+ ^+ Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 _: @! \* |6 ]! k/ A" j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# [/ \' j, k) q3 C4 y0 o8 @+ ~6 g8 ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' X, C" i/ N1 g; l& {$ h# @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ e- f5 c0 {: t! s+ [. M, j0 h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# v0 f, X2 ?+ `, o1 @0 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# ]) \$ Z/ l; `0 }" i/ Y9 Y9 j8 W7 a}
7 z6 h4 H9 }% n, _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 w( _8 c% h3 U4 B3 K& G( Q4 P
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