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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 N; h4 q& Y4 P$ H! c" v: ^" {
input mcasp_ahclkx,
# L0 s6 |, l; Winput mcasp_aclkx,
0 c8 Y# d2 L0 c* U4 k- G* I# cinput axr0,
$ H9 w! T2 J, X& R1 {( {5 b8 n. b' F4 f/ D( O
output mcasp_afsr,+ \6 U! ^/ }0 j" g
output mcasp_ahclkr,
' S7 H( _ o0 d$ moutput mcasp_aclkr,5 Y$ y+ j) ]$ q
output axr1,
5 T2 o; l- J% R assign mcasp_afsr = mcasp_afsx;. l4 M. Q% [8 |+ {! J% p+ l1 b/ o
assign mcasp_aclkr = mcasp_aclkx;/ v: U6 F9 X" u D( ?: g
assign mcasp_ahclkr = mcasp_ahclkx;. l' }2 O y7 F& a
assign axr1 = axr0; ( ?' z# b7 w3 e/ e' }; _) R
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . F, z( G' T0 r7 K1 g$ R' Y( b" g) \
static void McASPI2SConfigure(void)% e8 g, _2 |/ Y$ w/ `! v3 c
{7 e: w6 I' w3 j, w$ X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 E, I- }9 O. S1 e2 m! D: t& [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) u4 E( U4 g0 O1 k6 [. @- tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- f$ \- v. R& L5 ^* G1 }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* o5 o6 ~( o6 _0 x ~& p0 M' @* Z. FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* a5 ?, {5 N$ W+ S! I8 r# o. iMCASP_RX_MODE_DMA);5 t( p, _0 _, [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) M$ h& n, [5 U5 I; R3 m8 p: H1 T }+ {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ X, z7 @: k7 B3 W) Q8 L8 gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ T5 R; @) u( F8 I" z% ]$ n7 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 h5 P5 F% ~) W, j" Z8 u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) J& B: x0 V& s8 T: ?5 OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ O" Y4 L" N+ E! f. \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 k, P1 T9 H. h: _" E$ L6 C/ D. P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & t% @- g8 N$ h3 T3 X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 O3 Q% J/ F/ o1 o0 \ H
0x00, 0xFF); /* configure the clock for transmitter */
( H8 \/ b/ [& d* x* x: f$ S2 x% pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; Q# _* V# v; _8 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% W" g$ M. A$ S0 EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 a5 G! { j, O$ ]7 Q6 C0x00, 0xFF);
6 w2 t6 V5 U! {0 H) A6 T
1 G1 i7 o: l% x6 h/* Enable synchronization of RX and TX sections */ / p1 [7 R1 ?0 Z4 J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! H- @% Z( w* R( D. y1 }! p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ ]& s5 g( x0 v% S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. a+ D% ]+ X+ j0 C: Q7 f2 R
** Set the serializers, Currently only one serializer is set as
/ t$ F9 r/ e( c. Q2 _: y2 v* A** transmitter and one serializer as receiver.
# d, `$ B7 q& t" r; ~*/
5 f/ e# g4 n5 RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 y$ b8 L4 _8 I' Q) O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 G% x3 m! b, W# `6 U** Configure the McASP pins 7 ~* G+ O" }- C0 W6 [$ y! p
** Input - Frame Sync, Clock and Serializer Rx
6 _3 |$ t* u$ i# }8 g** Output - Serializer Tx is connected to the input of the codec
# N- L5 @ q, V2 G+ n*/
, h& H3 {9 t w5 OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* P0 T) p1 @' ^$ R- {9 f/ ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); u# u0 I R7 x' T5 I, v# Y& ~4 m/ V, n- p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. c' t% w- |2 S% q| MCASP_PIN_ACLKX- i% Z9 y1 Q! ~. F3 V9 m
| MCASP_PIN_AHCLKX
- e+ k+ C+ k4 ]1 {5 w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ a3 f# r3 o4 m8 U3 T: n7 \, LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 R5 T* ]- n' e+ s7 _| MCASP_TX_CLKFAIL
3 R+ @' S6 k$ ]% E; e8 ~+ ]| MCASP_TX_SYNCERROR2 K; v$ K6 ]" p5 R6 y0 t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& q1 t$ P, W& E$ C+ j5 w9 E# G| MCASP_RX_CLKFAIL
/ @/ A: ~* F3 L9 K/ Z. @" w. D& \| MCASP_RX_SYNCERROR + W& D/ K; ]* @$ ]7 @. m* _
| MCASP_RX_OVERRUN);
9 J; b- y3 ~( o8 Z) `3 K} static void I2SDataTxRxActivate(void)
( L7 Q# B* R) w{. I1 ^+ }# v% W# r$ O
/* Start the clocks */
' M& ]1 t, B0 H/ JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 x) N& q4 k) e* i9 ~: L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" ]/ ?1 n! z# q1 e- g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- t. D9 N& B7 O
EDMA3_TRIG_MODE_EVENT);
! E5 I+ K( n% oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 N7 p' j) { D' `5 q# T4 ^+ h4 M) q, P, }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 B8 a0 F0 o- W. t+ UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' D# b, J- p1 g8 q% I8 ^5 E* MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* G5 m, ]% y- ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, @: A/ s) E: z/ iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 o+ ] r, j# e+ l7 U7 E# P J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 [* z8 ]" Q7 q# }9 @+ \( H
}
4 A8 g- L! n. n6 }3 u! d& G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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