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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. x7 B3 ^8 v+ o% e# t% |! x G
input mcasp_ahclkx,
- o9 G4 q& y$ Cinput mcasp_aclkx,
7 v$ w7 J4 l' C% C( A" h9 z2 _# minput axr0,
2 C( U4 H( \- \, `3 b3 V, H0 ?* W/ ~ B$ Y/ O1 F; t E( r
output mcasp_afsr,- l+ r; s$ z4 q A
output mcasp_ahclkr,
# `# }* n& a. t" S/ X- x" p, aoutput mcasp_aclkr,$ S W) ~, c4 C! |/ S5 R; J
output axr1,( ?$ @: n T7 x3 u5 r, b* j
assign mcasp_afsr = mcasp_afsx;
/ Y8 Z; M0 D$ d# |* T/ s1 xassign mcasp_aclkr = mcasp_aclkx;$ c- _' r0 F5 d' w9 z
assign mcasp_ahclkr = mcasp_ahclkx; P. U' z7 }. V, ?( o& B6 F
assign axr1 = axr0; $ ?- D& ]( m, f! O# C1 }" ?4 ]
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) u. B, Y2 Z8 T! hstatic void McASPI2SConfigure(void)
& m5 I! F% A, ]) v# u( y N{9 L: F" \9 y i3 G% U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 Y$ `& K" n% I8 w7 m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 i: G% D1 u) T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! w, K! X; P- G$ j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# e: `$ d q; u& W3 w$ p6 m9 VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; j4 w3 p5 l4 o$ WMCASP_RX_MODE_DMA);
q9 L# X3 A9 E4 EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 Q B3 f* O! R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 c: U: l4 D7 I" H4 d# P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( w/ i; \' F m% w5 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& n. Y5 p) ~7 b2 L$ q/ B) A0 |, x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) b! N( }3 r7 x. f* o! N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( ]+ k5 f0 X" N( j5 v, \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 P5 b# ^/ C9 F% {6 }- tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + g1 o! K, N8 E. Y+ x. L& O# P: J/ A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 i! a, R' i% o$ k
0x00, 0xFF); /* configure the clock for transmitter */2 P/ ^, w O( S& ] {$ B! m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
Z2 A3 `2 j# T. e- S* S. gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 N" b3 v( [7 u1 fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 L9 [8 Q! ^ d, d7 i0x00, 0xFF);5 f- @; t4 T a3 f3 F" I J2 a& Y. T
2 [* T0 R5 N2 D) F1 q+ r+ k/* Enable synchronization of RX and TX sections */
2 r+ P& h2 ^7 p( r7 E8 t& y4 ]; i! r* BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- ~ e s- g$ e: B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 s' O/ C1 v: d X& n' G9 h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' L A/ B8 w' \4 J** Set the serializers, Currently only one serializer is set as
( s/ Y6 X1 k. |) N** transmitter and one serializer as receiver.
! |8 `; G) j g& E" i$ p*/- p5 B# m+ P' D- ]. g$ ]& a* h$ \1 f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 O j. D o% _, ?% J# Q* E( x6 JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 p3 r1 V: E7 ], H. _0 \# h
** Configure the McASP pins $ w8 X) P: X% I9 u ?
** Input - Frame Sync, Clock and Serializer Rx
$ Z$ j2 ?4 [: F& F3 o4 L** Output - Serializer Tx is connected to the input of the codec $ r3 t- O: I; v6 N. q) {
*/. K$ c% m. S; T8 B! w+ ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 b! T3 Z( A/ ?( E& `+ i# UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 K2 d# O' z8 |. y3 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
J0 k3 w, K2 x: E- K| MCASP_PIN_ACLKX
+ ^2 T$ L6 n1 O* V1 u: Y| MCASP_PIN_AHCLKX8 J6 F( @, b4 O6 P9 A% X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# u) T; i4 H* g+ |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 u2 b" H* L& |! p5 m| MCASP_TX_CLKFAIL
+ o/ c- ~7 h$ k9 k| MCASP_TX_SYNCERROR$ N+ F$ S2 y. S( T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & [ z# R: p1 Q3 u
| MCASP_RX_CLKFAIL; U9 }: k9 w' B2 {# F$ H* X
| MCASP_RX_SYNCERROR
6 A ]7 [1 J, T| MCASP_RX_OVERRUN);
& `! \( h0 M& {7 ~} static void I2SDataTxRxActivate(void)+ T5 u) y0 ]' ^) t8 ]6 r
{, T9 T* \9 r$ }0 x# Y) Q
/* Start the clocks */' ?9 n' M. X4 L9 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 f- w$ L6 b ~, F, t% ?% yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 Q2 m/ v6 h5 b- w( u! }1 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ ?. b `% M- @$ o7 P5 d- KEDMA3_TRIG_MODE_EVENT);
) n$ F- ^7 q. n4 ^4 }+ t1 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 N( h/ |! ^9 \$ [& gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 B2 ^) k2 \5 oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 R. j" k- |! N1 k0 K/ a5 _- PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 Z! L, b/ r+ G1 X) w$ r$ B3 y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- l- ]# V, p) ^/ T# l+ jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ v9 N( G: |. g2 N: }* @; E- E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# }( M$ T6 Q( x, p' p& I1 P/ R. q( m+ c}
1 E" s# f8 k) _/ w/ I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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