MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
% z7 X& M" W+ X+ t$ d: k/ x/ @input axr0,
: e* j* O9 _; V
) S* L3 Y/ G9 t) B) \- @# Zoutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

. e% ]$ R" y; M  v5 T. l
; |% ?( }. Q5 u

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
* A6 E4 R8 V& m* j1 q6 ?; n- Q$ bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 S$ u5 ^. b* g/ d: G' Z- f- s. uMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
9 D* x! A4 V& \$ K& X8 y. xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
2 i, x" T6 F+ W# b; _& XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
1 K& @6 x+ W/ _! e4 [5 hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 e0 j2 J5 ?- Q3 N: m- K$ d2 eMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 y! \! B" h7 V  s- t1 R: yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 S7 b$ w; ]1 b( IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 s* Q$ y9 T6 t9 _4 n8 fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" `7 l! S, X/ L* B  hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' m& h$ F$ f. b; I/ W4 ]4 w" [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

( b$ {" K; c) y8 i/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 F6 z3 ?$ Y9 e. J# wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
; C" M; q; I8 C- l  {1 }/ C% Z3 c** Set the serializers, Currently only one serializer is set as
$ j1 z8 u1 {; v- K** transmitter and one serializer as receiver.
' i, H( j" |( X; O*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 r2 R# j. P, ^, n2 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
9 E# S( b0 f0 I( v** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
6 d7 ^. x: t6 e- Z** Output - Serializer Tx is connected to the input of the codec
2 ]* o  z- C* g  A0 j5 \  C# M*/
/ L6 b. e2 c2 g* o) F5 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* o3 K4 n/ ]! |2 _, L" ?1 l7 mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
1 M% V2 L0 z+ t/ M# [. x| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
5 r) |* n* m& G" C* `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( j' [4 F0 M& h| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
) m" ~9 w% P& s# V7 b2 A4 {/ K| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
" q/ n+ V! D  L* A| MCASP_RX_OVERRUN);
5 ^; A" A& d7 A1 w' c2 b: K}

static void I2SDataTxRxActivate(void)
& j, y4 X- G4 P( z; k6 y{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( S  O+ A. K5 {- W- ^" CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
# M7 H' o+ h9 z4 x& CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% c1 p0 _' i/ W( \2 G' v/ MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

) |" G. Y3 {1 Y4 c

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.