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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 K& \' p z3 Ainput mcasp_ahclkx,
1 |% j3 f9 g5 b- }input mcasp_aclkx,
; j% n# b4 |! A+ Y5 t8 q: o8 ninput axr0,
+ B E: g1 O* a9 @4 E$ ~+ T; p* _9 L+ g
output mcasp_afsr,
' v$ W( y% {, t# C1 Doutput mcasp_ahclkr,3 V; D8 i: F( D- i6 Y
output mcasp_aclkr,5 S7 j' `/ F g4 i' _; k& _
output axr1,
$ B8 h1 J4 e5 t% `* l assign mcasp_afsr = mcasp_afsx;
5 z1 z6 l! E( ?& Q/ D( n5 yassign mcasp_aclkr = mcasp_aclkx;( P+ y% W, C) N0 l2 ]% t
assign mcasp_ahclkr = mcasp_ahclkx;
$ M2 F; H& O; ]7 P, ^assign axr1 = axr0;
6 X+ D$ T5 Q! P3 ]3 V0 C2 W2 t' }- O" s0 k$ `2 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* {5 A/ u, K, C1 |. e2 q/ istatic void McASPI2SConfigure(void)
+ X9 d7 a# D3 M* l2 o7 d, G{
- s; p; G' g) ~7 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! Z7 X9 R( r- }- e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ h [7 R$ P% ~# z5 n4 l* nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 \: z; h9 ?( \- }/ d, \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 I6 _! e( k& _2 U; M! u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 A% `) w1 x7 W" v, U2 JMCASP_RX_MODE_DMA);
& t( r6 C) y" o/ K: i! EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- I' }: @% M: _4 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 q! |3 m, e4 {4 r1 N7 DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( \/ X7 u- Y: [0 D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" X. V9 y* F G' n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ M2 `# l6 ]' s1 L" g7 KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. C8 t4 R( H' X* _' H0 G* AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 S2 n+ Q, A g7 T# N; G6 N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 X/ g6 F4 x3 ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, e5 }7 @. L0 ]9 @0 _- V
0x00, 0xFF); /* configure the clock for transmitter */$ F+ J6 E1 R/ `0 e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- e3 x1 Q5 M) E4 Z$ sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( H5 s& f1 c9 m& A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: _5 | ]9 V4 ~( o
0x00, 0xFF);
' h1 P9 k4 V3 j
1 n5 @5 f9 J" ~2 B5 E; p- C/* Enable synchronization of RX and TX sections */
: i1 p1 t" I ?& ?( z- P7 RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% |8 f* t3 S1 H7 D) ?; y: `+ I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. A! R7 z8 U1 X# H9 ^3 y& \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ D& H6 c1 j. H0 W** Set the serializers, Currently only one serializer is set as, O/ o" V% T0 Q: m
** transmitter and one serializer as receiver.$ A# u6 @0 d) F, U& w5 _1 E/ `7 h
*/
. R" h- L; K$ I3 @$ i; y7 W3 K7 MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 L, Z* Z8 l- l Q1 t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 j) c; w& }& c: i# p" z' k' T** Configure the McASP pins
# Q% a2 I' x* v3 I; E5 N7 h** Input - Frame Sync, Clock and Serializer Rx
& B2 _/ s, p/ @4 F9 J** Output - Serializer Tx is connected to the input of the codec 0 Q! M, [8 g( M+ o
*/
, x3 @/ m* a) i4 l4 k1 W8 cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) j& _ A* ^3 D" R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 k' c5 {' O6 ]9 o/ m& \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& W9 ~9 d# `- t G
| MCASP_PIN_ACLKX+ o/ r1 Z! J! W/ b* h% b4 k
| MCASP_PIN_AHCLKX( U, z% H" A' Y1 b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- b2 e" X G: e8 ]1 eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% J/ K: R7 g% Z! S: c- U7 E| MCASP_TX_CLKFAIL
9 p" D7 Z+ t0 A$ a| MCASP_TX_SYNCERROR* J4 ~( L# k+ l |3 M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ X/ X6 W m- Q: q6 ^| MCASP_RX_CLKFAIL9 B/ v% u1 ^2 u4 i6 N J5 P' P) s
| MCASP_RX_SYNCERROR
' \: X' N5 X s6 g| MCASP_RX_OVERRUN);, ?7 t0 ?+ v& H* N6 t; k2 a
} static void I2SDataTxRxActivate(void)
' T- ?5 t6 Q6 I- w4 d5 M' ^ p{
7 S8 X: d9 W. u) P/* Start the clocks */
, m. G& h5 G3 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 _3 m* _/ n5 d( j* [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 I( K) U! e$ C" S: M, F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 ]8 Z: P4 g3 _ t2 g5 l
EDMA3_TRIG_MODE_EVENT);! K f9 u+ O+ [( J$ b, @. {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 u/ R$ B# j8 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& n4 ^0 Z9 x8 U2 P2 F. J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, F6 M G+ j1 l' @3 r6 b1 fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( P% i7 S7 @1 I1 l' q" Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 X9 e# j E! y" ^; o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- @/ E" b1 i i! ^0 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 I$ O0 p' I, ^8 y}
; f, g3 i' l4 V* n) N9 o: u( \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
& `3 C$ e9 R+ ~ |