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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 i& k3 w4 \! oinput mcasp_ahclkx,
/ o5 k' ]4 r! o5 O5 O$ I2 uinput mcasp_aclkx,
8 _/ Q2 t8 n8 k+ c7 _6 @) ^input axr0," U q- p7 a1 V- g4 W- b* {
* w2 ]' W1 ]6 c( J( v/ Zoutput mcasp_afsr,. w: N: s/ R2 ~) o# d) M1 \% W
output mcasp_ahclkr,0 M4 r3 h* @1 l- Q9 o; ^
output mcasp_aclkr,2 Z1 N$ h8 Q3 V `% D' e
output axr1,
7 h3 s6 D* I7 R6 C/ X/ U assign mcasp_afsr = mcasp_afsx;/ o c9 y5 C/ k: R: v5 [+ K
assign mcasp_aclkr = mcasp_aclkx;: r: c" B/ M7 e1 B! f2 E8 {5 d
assign mcasp_ahclkr = mcasp_ahclkx;
) x" O9 n! g+ r2 rassign axr1 = axr0; 6 K1 n8 z1 v7 I
) q0 C, v3 p! E+ c/ C! J8 n: {% l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' g# M( c/ S5 s' x$ X0 F* M1 [
static void McASPI2SConfigure(void)
4 E d) E+ q& @+ S8 G9 a# F1 d{
; q7 x' j8 m9 V5 {" l$ Z+ \McASPRxReset(SOC_MCASP_0_CTRL_REGS);) N1 u3 ?- A3 H$ ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" p4 r$ z$ u6 w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 o- \# H" d% Q& C! H2 P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( x. W) E6 L% o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! k6 E' w) V: ^% _. H6 v/ p/ [- n
MCASP_RX_MODE_DMA);8 i1 h4 Q$ ~( B% J4 P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ t! ? W" p8 p4 q3 b1 }; U# j7 A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: g6 T7 P2 D B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* ?7 N' l X! [+ Z$ JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* ^# A5 c; _1 ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . E. }5 i1 ?' p$ H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 C4 K) h& w! t+ I8 v' P# u7 r. K6 p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" j# E& g! S! V# x, G. ]3 r2 q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" N1 ?1 T1 j! p* R: u; t2 j @6 kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ z- H1 `* r/ ]5 ?3 @
0x00, 0xFF); /* configure the clock for transmitter */$ f% ^- Q) h- V6 C9 d2 O: Y# k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* @5 d2 T9 \/ E3 O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); l" K g% x; N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) m1 ~. j$ U+ G# [5 ^0x00, 0xFF);
+ F6 L* j9 e$ I& w' i( f; @' T* i$ e, F. R
/* Enable synchronization of RX and TX sections */ ) j% s6 B* H8 U" B. U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 U, W$ \' z. U( V. _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 }% r' h" n" v( }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ C( } b5 r$ t& D: M3 L k, F** Set the serializers, Currently only one serializer is set as
! a& e& X3 ^! O/ k* N5 a** transmitter and one serializer as receiver.
' V+ e+ `' H; K I" y*/) w( w' O3 f: B( R- J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* c# y& P/ W0 P$ [* k) K" p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& I5 h' h( r& V& S4 z1 ^$ b6 t
** Configure the McASP pins : r9 b, I$ V9 J/ K8 g
** Input - Frame Sync, Clock and Serializer Rx5 x. c; O" }6 w3 a/ d# M# _+ \
** Output - Serializer Tx is connected to the input of the codec
( S7 N! ]' c- \' c8 c5 t( d8 z3 K*/3 P1 q) c: ]+ ~6 L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 n) w6 {0 `$ h7 G2 ?2 [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 v2 j/ W# f' Q9 N- _ MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. v ?( N ^) ~( T# n
| MCASP_PIN_ACLKX
& S v* R& ^% X4 {- E6 ]! [7 ?0 Y| MCASP_PIN_AHCLKX C3 {% Q6 ^! H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. X% {2 X! s/ E+ g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- r3 z- A9 ^- Y' L9 u9 K( h& Z9 b5 y| MCASP_TX_CLKFAIL
" K0 l c; }- |9 ^! K( || MCASP_TX_SYNCERROR
. {( M V1 i( v# L3 l0 @' P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; W* t( B) F8 W/ F4 |9 p| MCASP_RX_CLKFAIL
7 j+ t: H3 y ~6 J1 w: L5 o6 e3 I| MCASP_RX_SYNCERROR P' l, i/ p! Y# l7 Y1 W$ n
| MCASP_RX_OVERRUN);
, D2 [9 V" q2 o6 }5 j9 {} static void I2SDataTxRxActivate(void)3 l4 z% {6 P* J& f
{9 g* J8 U( F: l) S& u& v' d4 f' t
/* Start the clocks */
4 j" M' D5 C+ N$ f3 n9 G- ?# i3 C3 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& t# l1 z% G1 O0 N$ ]! `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! V# W9 j6 Y4 D/ s8 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& p; x, ~& R& S/ N j
EDMA3_TRIG_MODE_EVENT);2 y& J( X3 t, ?; @- s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, l* g5 V' p- H( o' I, {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, a. A, b) _' L1 }0 B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) f0 S. l: y' j# Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% B" E7 v8 L: t4 Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ j2 R; x+ t! X1 |/ T" C& nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ f3 q8 g ^ ~, H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& R7 `& b$ v3 }2 M* h" q1 C7 l}
4 j8 n! Y1 I4 _/ h- c" k R$ ^- q& K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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