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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' L3 w4 }: R* r9 Y) uinput mcasp_ahclkx,
3 _& F5 b* E# r% V* c/ ]input mcasp_aclkx,5 R$ c' v3 a3 O& p+ H' D
input axr0,
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output mcasp_afsr,
# V) D! A1 W! e. |9 X1 Uoutput mcasp_ahclkr,' y$ A, m2 ~, Y B/ q, e1 g" I8 d4 D. K
output mcasp_aclkr,
6 C. F4 B3 K" V" R, Loutput axr1, _- e2 T- i6 E6 N
assign mcasp_afsr = mcasp_afsx;
* e1 v* D3 I! f8 L9 T; Fassign mcasp_aclkr = mcasp_aclkx;
I/ x! R0 w/ Z* W4 Q1 `6 Iassign mcasp_ahclkr = mcasp_ahclkx;) R7 T8 k7 c1 }! d3 N
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 j4 J, ]0 |6 D4 d% pstatic void McASPI2SConfigure(void)
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, n' x! f# t$ M$ ~9 t3 s& ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! k( w* e4 e0 v5 q+ r* h' y, iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% j }6 @& F6 S1 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, \; L0 E8 B6 P r8 J4 e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, l8 ^# B) t7 }, f% n1 O! _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% @0 {* L5 d% j# l
MCASP_RX_MODE_DMA);* I7 ?0 k7 _; t8 {* E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ v+ L3 G" b: K: s/ U) r$ qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 T; z+ B6 H' I* w6 d. @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 y7 H( ^; p7 x7 g' g* N/ g- ^) XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 c; N' E d5 Z3 p; |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 _) r5 x N8 Z; j* d) h {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" b. j6 h$ }1 I$ z' l4 E. O( GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) y- V2 u! I* ?0 PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * q7 i, k/ o& n- o7 ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: \% j9 n }( w# a9 {% Z1 q: o
0x00, 0xFF); /* configure the clock for transmitter */
8 s- z6 Q: }2 t5 \8 ]& O/ r9 fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ _& m W0 e$ o& eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 H8 `$ j$ g$ S- J5 i0 ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* i3 }3 ]' ^: D. `: P
0x00, 0xFF);
$ ~+ v% F( ?! x9 [5 u( q7 t7 r
- l0 S* B" _( i+ k' ?1 z/* Enable synchronization of RX and TX sections */ 3 f3 v( w; _+ k1 ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 ]* _' Q9 u9 b) x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. t e7 H. r* d8 _! N" z R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! m" c. F! {5 v& \8 \8 o
** Set the serializers, Currently only one serializer is set as
( B. `- Q0 g1 C# Q! C* u2 i' T** transmitter and one serializer as receiver.
% J: `( l6 r. @- Y*/
% b" C8 m7 o! z- o6 _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ g5 T8 S1 V/ u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' O6 U8 a( ^) t( S$ g1 t** Configure the McASP pins
2 |! j! p' F5 D# p/ E** Input - Frame Sync, Clock and Serializer Rx) _! U+ m% G1 j6 I- \
** Output - Serializer Tx is connected to the input of the codec
% Y8 c( D% z6 f*/' T1 Q1 j( c2 o1 ]! j3 c, ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 Q/ {2 [+ S4 P2 SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& X1 A" V( s2 s% A; _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. ?- w! }! j/ d; m6 A2 a
| MCASP_PIN_ACLKX
' ^2 t% t0 `2 x* B| MCASP_PIN_AHCLKX
# p" f6 q+ ], c; x! ?& t% G) U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 x; O1 M$ c1 H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 \! u) l2 {9 ?# h4 m| MCASP_TX_CLKFAIL
, B4 Z! D2 v0 \! Y; f- q8 d| MCASP_TX_SYNCERROR3 }. E1 k E" i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # W$ t4 K/ y9 ~ Z
| MCASP_RX_CLKFAIL+ g4 h$ R1 Y- y' u X; X+ n
| MCASP_RX_SYNCERROR
% U" O2 L9 m- `4 W( t| MCASP_RX_OVERRUN);
' q* ^6 Z/ Q3 M} static void I2SDataTxRxActivate(void)
; Y! {6 ^) ]. _1 }9 ^- d$ k! y* C{
1 o, c# V7 ~6 x7 Y, y$ a' Z/* Start the clocks */
% n- K# |# a; W7 K; d, y2 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 h3 c& M% a+ O3 z4 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 A9 V. K' i0 x: p; Z9 \, DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 Q: @ D6 X% f+ G9 [9 L4 d1 N1 TEDMA3_TRIG_MODE_EVENT);, v2 H! `5 @: n3 l W+ i9 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - h t' `& ^) b" n8 Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- a s* o4 `3 d/ `( `% @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. J6 s8 I* i0 Q2 F. I9 KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ N: h. M$ v! G! J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" c9 E9 o& R) sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% E1 P) [0 P4 A. lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* c0 B! T* q0 H
}
- {( k) n) ] o( M6 R2 ]' L2 g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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