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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ [8 n+ T8 Y& s4 `% a
input mcasp_ahclkx,
) U2 @9 t" p( hinput mcasp_aclkx,
1 ^( w. h U; n1 J5 Hinput axr0,/ O& f4 k% K* y7 B$ @- ]
+ O1 E8 s1 ?! l/ Noutput mcasp_afsr,
, M! ^) P8 e* W* q( J, eoutput mcasp_ahclkr,3 A7 h8 E1 s' r$ }7 D4 ~3 g
output mcasp_aclkr,
3 n' W/ z5 `: m# Woutput axr1,
' z; w" F6 _1 g8 e! X d0 s# f assign mcasp_afsr = mcasp_afsx;
7 {5 \, n; O8 @3 d8 y1 massign mcasp_aclkr = mcasp_aclkx;8 }# Y6 K% l7 p( q# z; d
assign mcasp_ahclkr = mcasp_ahclkx;! g) o4 Y) I4 o+ {0 m, ]7 i* f
assign axr1 = axr0; 5 x1 c0 q: d' z# o* n. ?. U& A) v
2 q2 f0 V6 W& S& o0 ~- p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 z, f! g( n# [) U. z
static void McASPI2SConfigure(void)+ e) I3 b* J* p. P
{
5 r/ K' \7 E C7 E; V$ ]3 ^( j; _McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 M- g8 g6 [2 a4 d- M! l3 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' b( b: z: T$ K( h& h3 I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ e4 l9 H1 R# {5 K( |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# V9 w: G9 x; d4 q* bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 w& ]% F- A. @, S# {1 ^ J3 p. i
MCASP_RX_MODE_DMA);2 S- k$ Q+ Z% Q7 G1 V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, v- U$ u2 H' E8 R' d1 z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& A6 e: b; O# e4 `( K4 Y' }) {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 j- ~% A% I- Y8 N+ D. C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 Y' k% d' A$ K8 A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 |! [; E6 m2 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 [1 Y Z2 N) S8 I$ {4 q# QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 x. J# v, Q! [- Q' XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! z+ i. t' x( M0 w$ s& {1 h( x- XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 H" p- e$ M8 u- `* I% l+ @; P
0x00, 0xFF); /* configure the clock for transmitter */4 `- \, {; t! k0 m& G2 `4 T( s! G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 q& t- M7 u0 t+ D8 y5 n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
@6 ^ s/ ?! O7 n# iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- Y: M# X) u i# M2 r
0x00, 0xFF);
* G8 v, `9 Z' F3 V$ x
! Q \) e i# t/* Enable synchronization of RX and TX sections */ " s( V# x' h/ f0 m3 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( b5 J" W& {8 B# ?' nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ q8 g8 j/ D: gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" }* J; F3 d! L9 }5 P$ y** Set the serializers, Currently only one serializer is set as& A; X& u; k5 l' Y
** transmitter and one serializer as receiver.
8 i2 E _2 ^ Q" C7 i( f*/% F' P* b# F5 e- f% F( g2 V/ G; d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& {; b# L# B9 B3 B" [6 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- f+ M2 \% v% G$ |' x6 w
** Configure the McASP pins
" K% i: @2 r/ B- c9 ^** Input - Frame Sync, Clock and Serializer Rx
7 {* Q7 M, D* z% F, J0 d** Output - Serializer Tx is connected to the input of the codec
# [0 A6 p- E8 X, z. d0 L9 n1 ]*/
& N$ b( u6 d. X7 A& u7 J$ M ^/ sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, X- [+ T! k& L: J M z8 j8 gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) S2 T! k( }5 V" Q( v% T4 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" x* H! u) X3 r6 y
| MCASP_PIN_ACLKX
3 F) Y$ Z6 N% }' ^1 d& E| MCASP_PIN_AHCLKX
w3 ]/ I3 i* r+ a2 w+ E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: O; P1 E9 I- ?( p$ q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * W7 J5 l* l7 a, w. O, f* b
| MCASP_TX_CLKFAIL
' \ v0 }/ U" @. `0 _* b ~, F4 {| MCASP_TX_SYNCERROR
$ g0 d: Q2 E* e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : q3 ?2 i, B' m d' _
| MCASP_RX_CLKFAIL
0 H0 }5 i1 M, I; K0 p$ x! f, @| MCASP_RX_SYNCERROR ( a$ Q, n& ]+ R7 t4 a0 @7 o, B
| MCASP_RX_OVERRUN);' e0 N% g/ j, G% p8 r
} static void I2SDataTxRxActivate(void)' ? ^# a( C# d+ W
{) J \6 q& a+ ~% [8 B# O( j# {4 ` p/ w
/* Start the clocks */
" ]' [2 F+ i) D3 X+ K4 TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; F$ ?2 J; N+ {" ~& t- ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# x t) ?: U4 B* {7 n4 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 L9 t3 f( F# h D
EDMA3_TRIG_MODE_EVENT);
: F) z! W' l: k# BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 J& W: v8 [; _# L. o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 q( \& N6 |' y$ vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 d2 [. Z3 R; C0 ~( P' a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 U ]5 a: r6 P+ r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 {7 F% H7 P1 t. _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" N2 I* W ^! v: J CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 G( u. Q+ P* }5 y$ A; v8 [} ! ?% Q; K* }2 O( C3 Z( r3 x5 M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( L* B7 [6 |6 A% P
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