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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ j) `/ Y9 P u' A7 g
input mcasp_ahclkx,4 a2 f1 B, ?3 J/ E h4 H8 u9 g
input mcasp_aclkx, w: ^0 t0 J: z- C' u9 m7 ]8 P1 K
input axr0,* E. o/ F) \# l) ]/ Q
# O$ ]' c7 L% e/ u! k2 W( Soutput mcasp_afsr,
) F3 h' e2 |" `, g" `0 u4 Poutput mcasp_ahclkr,
' t* f# d# X! y9 E% Noutput mcasp_aclkr,
) X- Q! r h Q$ p& goutput axr1,
) i) \3 D) I# Q' `3 H8 F assign mcasp_afsr = mcasp_afsx;* d3 G. S9 c- C6 s
assign mcasp_aclkr = mcasp_aclkx;3 `/ M! C/ c- u' l
assign mcasp_ahclkr = mcasp_ahclkx;
0 k7 Y, a1 p/ B5 yassign axr1 = axr0;
( W7 G F: U" F z8 V9 s
$ C3 r1 r" _; ]* @- I' E5 Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % k8 p" g' a% o/ T4 C, P L
static void McASPI2SConfigure(void)# E$ @; @& _/ ?6 v: y( Y
{
# h9 J+ `: b) _( B+ U6 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; q& H7 E8 r9 C6 V# @% O0 P! l1 m" Z0 A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 r' ^! A# e8 D- l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ P: K4 T: L8 R( b3 \# |. S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" _$ Q8 q9 A+ P" }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 \/ k) B" b6 A! m6 VMCASP_RX_MODE_DMA);$ D& ^2 ]) d) L; I; S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 q7 z" U) z' h; M: ~8 |9 z W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ i1 y- z! ]6 CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% ]) U* F( k; t" u2 G, M: }7 WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 K4 B6 ~, o3 i: Q0 B. ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' {9 A9 f5 \( W# T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( k: l. f1 w; h3 w3 P: ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" y5 }$ q. E# V0 L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & P6 }7 D* S1 O) s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* I U) {* F! C' ]/ B) e4 l1 W4 d
0x00, 0xFF); /* configure the clock for transmitter */, Z1 C9 R/ m7 U3 K3 ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) y* u9 F+ d) g& M1 U* f2 E1 A6 MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: P- W* ]: ~0 PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' [; q& g9 v0 D% B' b; V$ {( s
0x00, 0xFF);
! i0 s/ l2 [1 C y0 w: {1 {7 n6 h5 M9 H- g+ M
/* Enable synchronization of RX and TX sections */ * e: U- o* F, G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( z& Y8 W2 A1 s2 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( D3 }- G- P- x/ S, P# S6 ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 @# R8 G" O/ A) T0 U& B; q/ P5 s! ^** Set the serializers, Currently only one serializer is set as
, F. R4 [" c; N, I) Q+ P" S8 S** transmitter and one serializer as receiver.
$ p+ Z0 h7 y+ _. l*/
8 P, F9 n) ~2 ]& A! G; X( lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( Y& j t! u' s: W/ d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 b8 i% `. N; g7 a** Configure the McASP pins
" d! I5 M7 Z; Y' z% e** Input - Frame Sync, Clock and Serializer Rx
$ C" w8 G' F3 q" y1 k1 Y" G** Output - Serializer Tx is connected to the input of the codec 9 i5 \/ H+ o; s, p; N
*/7 L/ x+ U c5 q! L4 h# y$ X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' Z. h1 p5 K- m* m7 ^3 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& P* Y( T' r! U- YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* r1 y( Q# U4 f9 E/ x
| MCASP_PIN_ACLKX3 i( W2 Q, }0 T& ]; o) l
| MCASP_PIN_AHCLKX/ ^- S0 o$ p" A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 ^ E! U3 A4 ~- v1 I3 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
q( m/ o5 F, b$ N+ g( D| MCASP_TX_CLKFAIL - H% d% J9 v: y3 t8 C
| MCASP_TX_SYNCERROR2 L9 m f" b2 M) ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. d+ q0 s: a& ]- H& j1 U2 m| MCASP_RX_CLKFAIL
: S0 q S/ h& O: U- V' A9 B6 M| MCASP_RX_SYNCERROR : ^# J* L$ J' g* B& S! w
| MCASP_RX_OVERRUN);
. H. R* x* j2 r. O0 h9 p} static void I2SDataTxRxActivate(void)
2 A( F2 c& K1 g- G# X/ y{
2 k6 X+ Y: a3 d/ |4 G; f1 P/* Start the clocks */
1 |( k+ @# a9 J' IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: ?/ Y' c6 O. |$ n. F4 c( F2 u5 f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' a' m: g. }- V3 ]* s* P+ N8 c3 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 ]% s9 ]! a- T6 @
EDMA3_TRIG_MODE_EVENT);
6 d4 @( U3 f3 q* t1 L# Z% IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) k& l2 q+ G! R7 w" m hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& o6 p3 O! A3 ]6 G2 J+ G0 }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 z) C% @9 f) A" M! tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. l8 s" X Y2 {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 p) ?3 X- @- Z' O" _- r2 sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); Z' V p4 @1 Y0 N0 C0 _, N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 c& r' ^+ I4 W} 1 ] k _7 }: ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 X! x8 W0 ?8 S3 _- Q* s
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