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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. a& H( d- b- S( o; `
input mcasp_ahclkx,6 m0 g5 `; l& w( p. o% s
input mcasp_aclkx,% F& H, ?5 g# W4 B
input axr0,
: J" r6 D) b. e3 F4 `; {' |# w/ n
output mcasp_afsr,3 Q" j. `: |8 t5 S( h2 K/ Z
output mcasp_ahclkr,, q4 p4 b9 b/ F! U2 ?2 Y
output mcasp_aclkr,
& b2 e7 s9 D3 y- I n, i. uoutput axr1,
0 d& ~) d2 P- E1 g" b assign mcasp_afsr = mcasp_afsx;- p4 e7 V, J0 B# m& N4 t3 H
assign mcasp_aclkr = mcasp_aclkx;% T* s7 O1 i. l' |. {
assign mcasp_ahclkr = mcasp_ahclkx;: c/ I& b; a8 p8 c, h
assign axr1 = axr0;
! }0 V" Z3 A+ s3 b( W- K1 s+ T1 a/ d" c+ k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 `$ V7 M8 z- p) Y$ Y" p% \5 u& Dstatic void McASPI2SConfigure(void)7 I/ p; ~* @4 n. {+ k p: H% S4 U
{
& `9 b- i q9 x+ j, q UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 ]1 N: H4 l: m8 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ H2 v' Z: c& M5 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, R+ G3 J e+ i4 z/ m/ ?7 c: lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 J8 k7 {7 y4 j) k3 NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* A& E8 Z# t% A; R6 \' N
MCASP_RX_MODE_DMA);
- f9 C; b3 ~( z6 g. D' } A* [3 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 t c% N" J" F7 m. S, }8 k, oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 d( B G) P/ i% J! x, _" zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - `* x4 w; H+ U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 S; I7 Q2 B: I# e$ p6 jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 V8 l y6 d4 U7 _ z8 @4 y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- e2 @' O' @. k6 f8 y5 h% J2 j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 }, t- j U4 c7 Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " h% n2 R2 T- F) O: \! q* G
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 E+ }4 ]- G- q* \
0x00, 0xFF); /* configure the clock for transmitter */& n r7 I/ L: m2 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 i# T8 A3 v. F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 m1 ] r- P }; pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* _" N+ j3 x, ^ R5 Z, p0x00, 0xFF);
- l! ^$ y; C" t" T4 k, N0 I* M4 u6 Z% j* E8 r! C
/* Enable synchronization of RX and TX sections */
) e) D+ }( {1 t. e9 a9 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, e2 K7 A* k2 q. VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 l E0 A/ x# dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; F+ x& `: }7 v- X( R4 _** Set the serializers, Currently only one serializer is set as
8 J- `/ ?; t R C** transmitter and one serializer as receiver.# W2 B% P3 y+ i, _
*/
7 X2 ?6 G+ j% e" Z5 |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: @1 E D& G$ I# N+ d* j. k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( u; e: Q6 T2 p4 c
** Configure the McASP pins
) Q3 S: {$ v& D, y** Input - Frame Sync, Clock and Serializer Rx G. }/ A+ k, A0 Y3 i2 C0 {7 p
** Output - Serializer Tx is connected to the input of the codec
7 y0 C$ U# h0 e: {/ r*/
! T3 c5 ^' { K; O0 ?: pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; k# V( R1 D8 m; F& Z6 u5 I N0 N0 z( gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; {3 P9 ?7 ^8 o% {1 J" Z5 m0 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 J" g6 X# n4 G+ l| MCASP_PIN_ACLKX
' o: y; R3 r) L8 k- X| MCASP_PIN_AHCLKX! c; v: V% V7 R# x! d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' t3 C4 E1 `! i% ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 R5 b* u c D; n, z$ e) M2 ~% _
| MCASP_TX_CLKFAIL 7 H* V9 H" o% p3 I
| MCASP_TX_SYNCERROR% o% y P. m5 C4 B, E7 _; u9 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % G. e9 F! k- G/ t* U8 Q9 W) u
| MCASP_RX_CLKFAIL
3 h; I* P* G) b% r: D% F* j| MCASP_RX_SYNCERROR & t1 j' x# y6 V9 q
| MCASP_RX_OVERRUN);+ [9 I1 o* N3 l& I2 x2 I+ }
} static void I2SDataTxRxActivate(void)0 n- ~8 Z4 O5 Q1 A
{
% j/ I* Q8 u( z# h0 [1 ?$ s: j/* Start the clocks */4 V1 p" Q2 x8 h0 \8 s( @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 S/ y J* n! p( F# v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! H6 B9 w. G! t0 pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 ?5 p d& V0 y( H
EDMA3_TRIG_MODE_EVENT);
0 o) t0 s" H6 ]* rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* o+ Z) x5 L: t5 I$ K" c" H5 OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 x! f5 T! `/ f. f3 t1 V+ V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- K) ?5 f' a' U' r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 s* A: V8 V9 nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) Z* |( S- v# E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ a0 h1 F% ~- I# F# ^ X# d) ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 h4 \% J6 l8 [% P( W} 4 O& Z" g3 T% v1 J5 B7 l# f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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