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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, f4 ]* f2 z1 J/ c; @3 Y$ H
input mcasp_ahclkx,
+ ?4 \+ r* x( u8 c$ R; z3 v! O! qinput mcasp_aclkx,- @& L/ ^# [3 a6 E
input axr0,
$ L7 \7 L. h% Y1 T2 \& |% f; o8 h0 M6 u: y
output mcasp_afsr,/ p( o5 ?$ ` }4 j$ I* s) X: @1 D
output mcasp_ahclkr," i1 ] U* s5 R n* s0 e
output mcasp_aclkr,
# x. J p* D# D* `output axr1,% I! `/ v3 b) F- C) O5 |
assign mcasp_afsr = mcasp_afsx;
D: {6 ?! x' B# `( b+ j; J; t: Passign mcasp_aclkr = mcasp_aclkx;) d9 P2 d6 s) I7 F
assign mcasp_ahclkr = mcasp_ahclkx;& ?* M& C5 a1 ?4 I# U" E2 z
assign axr1 = axr0; 6 ~6 M9 B' S( \# q
) l" C# G. k9 e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # P# K$ Y$ g/ E+ H6 ~' Y
static void McASPI2SConfigure(void)
2 }0 \; g$ G- C" d, p' x6 V7 X{
8 W+ ?; w: w4 W( L, T. GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& `" G* f$ |* ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% @$ N6 M' j8 S& cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* Q+ w+ f2 Y! \$ ?- }$ K" N% `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 E8 V! j/ O4 E8 l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* e4 d; A8 X$ f9 U. xMCASP_RX_MODE_DMA);& g* z \6 W% t z2 ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 A- g& O: Y$ ?, X7 M$ i. z7 J/ KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) ` y7 A2 D" @+ H& O1 t' p pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
i* Q, h% j R8 f8 D. Q7 TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ c' X% r. m) m; L* k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) w, W) L: ~* z. K9 h3 r9 O" i0 X" Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! U2 [! h9 g. O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); Z. Y+ e; @: }% b6 |* |# Q& u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! X0 K, Q+ {# |* X$ h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ H( ~5 H5 C4 _6 Z0x00, 0xFF); /* configure the clock for transmitter */0 Q# B7 C3 v+ P1 K6 C7 i, L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ j) X' {% h3 S; ?2 ?5 f2 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ |4 `0 ~' x, h; U5 K5 M" yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
L1 G' i2 \) X1 E5 c0x00, 0xFF);3 @- @- l8 e: _- E9 w X
( n- _, c s# t8 C2 R/* Enable synchronization of RX and TX sections */ 4 `1 |( E! q: f* ?/ e( L, z- Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 F4 _# L1 z, O$ h* x2 G9 Q( d2 BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' b0 b1 U( {/ G' c& xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) k m! V9 U- H: R** Set the serializers, Currently only one serializer is set as
6 ?& C( \* y! e2 a' O" J. Q2 c** transmitter and one serializer as receiver.
% G# b5 o7 o% z5 ?$ q+ [* K8 Y*/& [9 a1 d8 m3 Q2 F" ^& @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 p4 \' M5 Q2 M i, S8 u- [+ H* ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 W! ?) O6 ^+ [0 v9 h3 E; y** Configure the McASP pins / [: {5 t5 @) O7 Y# r' a
** Input - Frame Sync, Clock and Serializer Rx# U6 `2 p1 A6 e" R, A' y1 B* f
** Output - Serializer Tx is connected to the input of the codec ! |& y) a0 I: I/ B" v' U: A! u
*/6 E) [! w. p. T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' Q0 d! e7 L: j4 B- {, ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" h8 p8 B! t! r9 n, A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- ^' @6 S' O M
| MCASP_PIN_ACLKX5 @" I8 O9 l9 X1 ^2 |, N
| MCASP_PIN_AHCLKX& b s( B/ N' g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 Q, p8 W |& L ]% J2 f" cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / C5 M% c: u( G
| MCASP_TX_CLKFAIL - n; ^, _2 t$ B# l& l' o
| MCASP_TX_SYNCERROR
9 ?% F3 c! U3 ]0 W% g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 ^! a+ U" X- g- C
| MCASP_RX_CLKFAIL
4 X4 }9 g& ?2 k| MCASP_RX_SYNCERROR - v4 R4 F* I( _% }
| MCASP_RX_OVERRUN);& m7 t) Z* W6 T/ q! D3 C0 m+ g
} static void I2SDataTxRxActivate(void)
3 P7 b9 |% _) K{( Y! D4 k) |$ n/ h* H; A) F
/* Start the clocks */
' A0 l( ?" ^( V$ HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 w e% J: S$ Q$ ?- }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& K) a. ]' F( V% }/ T$ ^8 ]0 l& pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) F. v* A5 k% {EDMA3_TRIG_MODE_EVENT);
4 @+ K l$ n8 _9 U+ G AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' q! ^) D6 g1 r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; n0 D0 R. ]( H' K* F7 h% L: n/ \/ lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 R: g5 ~: Z1 k, K6 q" x& n5 a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! O: C( y1 e0 ]/ Y* P+ H7 q3 G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; p5 \& |' L s6 o2 [1 J. ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 L6 a. F, {" C, u6 M& x2 w0 ~, zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ d7 a3 F% w. {) A
}
8 b/ _: ]% B8 {5 B3 D6 r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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