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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," ^& k. L( d6 F0 S' A# @8 b
input mcasp_ahclkx,! `! d2 ]! o) V ?$ @4 }# E
input mcasp_aclkx,/ O, b( F8 e x( p) k: l6 s6 F) H' J: o
input axr0,* d0 _. x/ l3 H6 T$ k# [8 o- O% G
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output mcasp_afsr,
7 b4 o, Y4 v% p3 A# K5 Youtput mcasp_ahclkr,* a) h0 x; L* D, x( c
output mcasp_aclkr,0 F' p0 ]% f( C3 }, s
output axr1,; J/ V y& p! N3 v+ ^" s% F
assign mcasp_afsr = mcasp_afsx;4 @# D5 f L& ?7 F. f* A) `
assign mcasp_aclkr = mcasp_aclkx;8 Y; H$ N' z3 x, e O
assign mcasp_ahclkr = mcasp_ahclkx;: p# Q" I- t1 J4 }4 y
assign axr1 = axr0; ( v' X. q: J2 c: w0 {/ h) W
' W, E% L6 k- Y5 Y3 K, K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 }$ _/ W [2 }' {; o d7 m
static void McASPI2SConfigure(void)+ X$ y% `7 A: k) } j9 x
{& M% d5 e" a, E8 F# k4 X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 y0 I( G4 u9 i- l, }: @/ A/ q2 U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, ]) ?/ S5 W3 T( @& A+ EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 y2 c8 Q. c# G1 aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, S* ^0 b" ~1 \: V2 G1 _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 H4 \6 e" T( X5 vMCASP_RX_MODE_DMA);9 s7 O/ a- O& \, y0 @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 J% c- }0 |) W- I; y' C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; }2 M0 _( ]. R) I4 f$ p, c8 l5 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / W' x* `" f3 Q" b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 r1 w' [5 D1 a# Y P# [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; G% u) c7 S0 P" r% m7 X |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 f* L7 ~ A# J& P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; U- {- ]: O9 v9 G) r. a, m& \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 ]3 W" x3 \ c2 Z, ^6 @8 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) i# l( D( p- l8 ?$ x" {
0x00, 0xFF); /* configure the clock for transmitter */
$ ^7 X2 t1 Z$ S+ qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. c" ]( }- [, G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 j: w2 a# G5 hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% \/ N) j' E: ^% W/ \3 Z& d
0x00, 0xFF);
; M& P/ i2 g3 M
; n' Y% i, b8 H4 `& l$ U* |8 |/* Enable synchronization of RX and TX sections */
3 n; g0 S; P1 G1 S: OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# ` T4 r E% V& c+ d$ _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: X* F8 f6 D, u% s# y5 Y$ NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- u. g E7 r4 J: \7 x6 p
** Set the serializers, Currently only one serializer is set as
' `1 u5 r/ k0 c. \** transmitter and one serializer as receiver.
1 ^7 \$ Q4 O- s*/0 H1 e& R2 }4 z. @. A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. F7 c$ c: `' i4 t+ X B* wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 Q7 j, e7 S1 I% ?
** Configure the McASP pins # B) @/ }: l2 Z* p! B/ }
** Input - Frame Sync, Clock and Serializer Rx
( H: M" x9 j4 d' v- S! q** Output - Serializer Tx is connected to the input of the codec % f! ?) `* m( H! b( m
*/, g, r; L/ x% t- }/ t' b; O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 k6 H% \0 x' c! S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& F4 u7 c; W/ t: uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! t3 S6 e2 C3 |% e( _
| MCASP_PIN_ACLKX
3 }7 d8 d" c) |' l: Y* @| MCASP_PIN_AHCLKX
, B) D) V0 A8 o- X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& u! g$ L7 T( z- I; Z# E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 ?# m- `# {7 V) m| MCASP_TX_CLKFAIL ) R/ S, N1 ]* M9 ^
| MCASP_TX_SYNCERROR: B( v+ |; z X: M+ e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - X0 @5 \- u$ k2 k
| MCASP_RX_CLKFAIL
( n4 o1 c" P. a# a! x. F# w8 O X| MCASP_RX_SYNCERROR # J/ Y3 z6 _; C6 I% H% E
| MCASP_RX_OVERRUN);
3 h# b- y- ]/ S' H& u} static void I2SDataTxRxActivate(void)1 H/ ~, Y7 S5 M+ o, L
{2 Z' `7 Z. U- _) K' B: L( m
/* Start the clocks */
: z1 k6 P& y) q* o& c& hMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% Q$ Z6 \+ H2 n: S4 t9 HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% }9 z* K d3 G" y! l BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' M/ i) K/ w" H% r$ |' ], j/ DEDMA3_TRIG_MODE_EVENT);3 I9 `- B2 Y. V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 n. m9 O! U `1 k$ K* l8 G& A/ qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; l. h% u# p% A9 r! ~2 gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ Q% K/ B% D6 j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 w: O7 S" J3 R( [5 E. l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! V8 e. i8 a: L1 x/ t. q1 V; BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; G) f, N, H& @& YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% e3 e" T7 O" m! c
}
) X. k+ y( K- N. P0 g" }: |- O8 y4 o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % C6 f% m5 } z8 s+ I @8 j
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