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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# I% o: F9 F! O; y& Q7 {2 P# cinput mcasp_ahclkx,2 N9 o, y' e* t& x0 O- \
input mcasp_aclkx,
* l! {' t, _+ Q* f) w" kinput axr0,
8 d4 i# A0 ?* v" k: L/ K9 e7 E! `7 ?' b i9 d
output mcasp_afsr,
% j9 |7 [7 y# M& P$ Q0 `8 @2 Foutput mcasp_ahclkr,
, U( b$ t5 }# S- qoutput mcasp_aclkr,: ?8 J' c; r3 W% S2 U/ x
output axr1,- p3 [# U' k9 k# n
assign mcasp_afsr = mcasp_afsx;( k! z% c, k% Z2 d) p
assign mcasp_aclkr = mcasp_aclkx;0 U. T8 y$ O; e- X
assign mcasp_ahclkr = mcasp_ahclkx;
; |/ j% p' y! ]& B" rassign axr1 = axr0;
4 P) t& i5 e, A _
2 l: z8 z1 n! E8 X+ q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 F0 z N8 E- O. P; w( n) ]; A
static void McASPI2SConfigure(void)& f" c$ A3 l# s. D
{
& q0 Z( `8 M2 ]' {8 v& _( tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ k0 x( q9 `2 |0 g* E7 d. `1 aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; ~8 J/ u, _3 k R" `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ x8 p) q; Z- ?. N5 s4 `, Z" v6 dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* ~) I$ P e f! h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* O- K6 M2 P2 I! n. u
MCASP_RX_MODE_DMA);. a5 s; Z0 f: c3 f2 @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' ?! ~6 B0 H/ }' v4 {1 n6 V& v" \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& l$ h; z7 T, `; J" F" ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# p. E* ^" T- L/ D GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
X, y$ Q- _& h! iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 h: Y2 K, s: PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 K, J9 L3 y/ W; l6 e- JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
T0 |2 x$ S8 G# m1 KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& X" v- [1 b3 dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. b1 N# t8 _$ W$ X" D1 o- x0x00, 0xFF); /* configure the clock for transmitter */
6 Y; j4 H3 z$ r2 \5 YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, s1 P7 F0 e8 ?3 i: WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" D! Y7 t0 `" K3 J; @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: N! |/ V3 R% J; H2 J- m
0x00, 0xFF);
" U$ n2 N8 e% x+ A: I: H! x' v" X
& {! z0 B9 s: z* y) m1 f/* Enable synchronization of RX and TX sections */
/ j. w3 D e- ^8 G, [, TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" G7 U5 |- z2 C9 C# x# \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 K# \5 R7 o; K8 R1 ~* N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ ^0 Z. ]0 d8 n: Q3 |** Set the serializers, Currently only one serializer is set as$ `3 A \, N. q' L
** transmitter and one serializer as receiver.
- W/ _, a% F% r6 L/ F. i*/
( X4 @7 S2 ^7 Z& V5 K& I# vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 x9 n% \, {7 h" R' n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, l3 a. j+ B: q* y** Configure the McASP pins 5 z3 A- l4 K& G; n
** Input - Frame Sync, Clock and Serializer Rx; k' i* y' P4 w; A
** Output - Serializer Tx is connected to the input of the codec
* C) `9 q: P- K; w& P*/4 a% H5 |4 x+ i; |. O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- U& Z! G- J+ H$ F1 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% `) f/ [ A: Z# Z% k) I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( D* }; J5 s; e" z: a
| MCASP_PIN_ACLKX
$ i5 p* X/ ?6 f% ~& @2 y* ~| MCASP_PIN_AHCLKX, h* s( w$ g1 i% T3 `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 H( q% x( A; [" s/ `2 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 O# p! o* I5 \| MCASP_TX_CLKFAIL $ n b1 p* Y' c/ x* Q& Q! {: F
| MCASP_TX_SYNCERROR
" M: y. g0 k8 e2 h% c! ^5 o4 \3 k. S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; m6 G1 S; n4 J2 G
| MCASP_RX_CLKFAIL
' [. \" X* |) u3 W' o| MCASP_RX_SYNCERROR * q. z8 s% U2 V: u$ `
| MCASP_RX_OVERRUN);% I( n& i0 z7 [9 B0 b" d% Q
} static void I2SDataTxRxActivate(void)# z; r0 ]- [# \6 X: t
{
/ W; c! C% {% H' a/* Start the clocks */5 }5 s8 t* t5 g8 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' z' j! D; e7 l: M, d; q( lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; s/ N+ K4 }: L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' m- ~% r$ a2 b- F; v; A2 X
EDMA3_TRIG_MODE_EVENT);
' e' N% y% c w& X# |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' w4 Y8 U" O" B7 }, {1 y6 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; z- `1 X% B v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 V) f9 x3 x- _# {% s; ?3 C) M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 \% a+ P% I! b( X) b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 ~4 ?6 u8 L2 t) F: sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ i3 W/ S3 Y1 Y& \9 I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 `) y5 O. a% m# ^2 z5 Y1 V5 D
} 5 L# b6 l0 p* T; Y8 \( s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! _! I2 d: \& b( d: d7 L) g+ f
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