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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( M- D, c) k$ zinput mcasp_ahclkx, A* p( }+ j# {0 q" M! K5 o" n& E
input mcasp_aclkx,( \( s# Q+ w% V9 ^# R2 ^
input axr0,
0 y. G. c- C6 K9 l \$ O7 F3 Z
* u9 C7 [% X9 o" ?- h- ]% ]5 u+ Voutput mcasp_afsr,# z$ U: o( w% E3 a2 X" m
output mcasp_ahclkr,( c2 X3 e* Q3 y) i* | N
output mcasp_aclkr,
6 v z' ^& e& a/ woutput axr1," A3 v8 j6 i4 j8 S
assign mcasp_afsr = mcasp_afsx;
( L4 B& o! a! `- U; G. Passign mcasp_aclkr = mcasp_aclkx;6 g0 A! ~; P# _" o" ]8 `1 y
assign mcasp_ahclkr = mcasp_ahclkx;4 v/ ?0 ]# H. o( K; g
assign axr1 = axr0; " `# y0 |2 L L6 Q6 M8 i
+ E( w/ b i) \4 n8 Z. R8 n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , {" I% |$ z; g5 k, _1 |' ^3 w
static void McASPI2SConfigure(void)6 F' R6 T& A- C- ^ ~$ ]
{
9 D) `/ f! i( s* R# K3 ]: UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( @8 v! ^ W' x" e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 |9 b0 q+ `8 u5 V3 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 [$ ?9 I( l2 z, V& C* R5 \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 a8 t7 D/ m( A4 Q) `0 N4 kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 U& a- z( f* s8 }" U$ Y) F6 cMCASP_RX_MODE_DMA);. H$ ~6 E' h: p n5 b7 ]! F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 {. r* U1 }; UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, P% [( T& M& j4 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( S0 F6 |2 }, L; Y8 y! {+ \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ U& `* V$ J/ y9 b$ O: hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. o P% M0 ?- m9 LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ n7 A& J0 P9 a- H1 ]& P& ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- {, |2 T( ~% B, jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 E$ v4 ~5 J0 aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 [7 m G( C# f0 n1 M- n7 I+ Y: y0x00, 0xFF); /* configure the clock for transmitter */
8 f) D' F& q8 B7 O$ LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 A6 ^7 n( `8 o8 K" _, J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! n# u" e2 d& c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, P$ Y1 c8 |& X
0x00, 0xFF);
* J- u! n: i1 L4 H9 b: G( |/ g) ]/ i% ]2 m9 v* S, U5 ]$ i" }
/* Enable synchronization of RX and TX sections */ % K- B4 Q% _$ p! Q; }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 n H1 R' C; U4 t5 F) s% wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* s E5 O# e( t* qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* t4 P* G1 F; R- |( t
** Set the serializers, Currently only one serializer is set as o! U- W# C2 ?; K( M( u
** transmitter and one serializer as receiver.
; g' x" `& ] |/ c' y8 r, u*/+ @, j5 X8 M0 J3 G2 R* Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( o/ y/ ?1 H7 i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 r7 Y( b2 ]2 M. h** Configure the McASP pins
# v0 ~; }5 l: A0 B4 k** Input - Frame Sync, Clock and Serializer Rx
2 \4 s4 X6 Q, U$ |** Output - Serializer Tx is connected to the input of the codec
' J8 e: T1 M7 T& Z" b3 H) T4 V*/
7 H+ ~/ N( W/ MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& U* r+ R9 l8 d3 v8 h% K0 K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! C0 k8 T. ~- L2 z' L) q, q; h$ _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" B# i5 u: d' {- ]. b| MCASP_PIN_ACLKX
) |- F t3 I/ `) l2 c. A# m1 z. _| MCASP_PIN_AHCLKX
N2 d e' [2 r* [2 U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: l* c0 f1 ~3 e1 }; \% |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + `& u1 I5 S1 w U2 v
| MCASP_TX_CLKFAIL
( G- E7 P7 K/ h4 j3 z# l| MCASP_TX_SYNCERROR4 o/ I! @5 {1 ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: R3 `' D, ^) O7 P8 ~6 h| MCASP_RX_CLKFAIL3 T" I+ H: X& x8 r, j0 R
| MCASP_RX_SYNCERROR ; q% t( w; T5 |$ Q' {6 o! s
| MCASP_RX_OVERRUN);, r% y3 ~& E; M; u0 s5 A
} static void I2SDataTxRxActivate(void)
/ m$ J* a" E* M+ I' f: e/ L/ {{5 r2 D, w, q' Y+ J+ g" t- E
/* Start the clocks */
$ O' Y. K5 X3 l% x3 d- UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- D9 `/ b# d- O& A6 e: qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
T+ I1 L# J; g" S4 v7 {5 \1 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ D. U; O& x1 V9 t! r; q
EDMA3_TRIG_MODE_EVENT);4 m ^6 d$ o* j4 e. F' s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 w( A: ^* \, W0 I' N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 l1 D3 i% l% ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 W A: A. s8 q' j$ k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 D7 G+ I' r& E" z; x9 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 w1 y; }' O& N7 m1 @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 K- N) P7 ~/ Q2 _ L4 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! k' E4 ]) A; W" b" b2 H4 e
}
9 a% J; e5 q. J. x. ^! w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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