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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. `/ f/ \5 F' v: E' }input mcasp_ahclkx,9 W+ |. f) T4 J2 Q1 b
input mcasp_aclkx," n3 N5 M& y, d6 s9 O# f& h: g Z
input axr0,
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) K' v# M0 f$ }6 j koutput mcasp_afsr,3 L" f* }1 K! C, K
output mcasp_ahclkr,
* L+ K8 Z% ~! s# ^1 Foutput mcasp_aclkr,3 v. ]( k* w/ T: M/ x
output axr1,) K( A; x; ~: P1 u
assign mcasp_afsr = mcasp_afsx;: U4 s( B: {3 v. b
assign mcasp_aclkr = mcasp_aclkx;0 S5 _0 k( h" Y! ^8 ?% P* p
assign mcasp_ahclkr = mcasp_ahclkx;4 i- _' x0 l: `4 Q% e* e
assign axr1 = axr0; 1 D; p" Y* k: \- e* [, K7 y2 M; r6 J7 f
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& b9 @& z1 N. P/ K" k; rstatic void McASPI2SConfigure(void)
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/ ?. N/ y7 N, [* D! `McASPRxReset(SOC_MCASP_0_CTRL_REGS);# a+ ^/ R% D. |' L) N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 L3 W8 _3 Y) g4 T+ kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 U/ X, i; M% O2 P. K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 d3 p' o4 O9 S3 s! f& ?, y8 L5 ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, ?$ g; T- G) l1 q( K% B
MCASP_RX_MODE_DMA);% c) N% O' m! r7 C( q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 S# e0 l% C9 ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// l2 A* R% C' Z `/ u9 l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 @7 C: o# c: u& R) c: z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 U1 W' H7 A, k( o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 b, d G6 x1 T5 O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; G; z8 t+ S4 o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- I& J: S3 f5 MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # ]9 }# s" a/ K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: @% d- n ?) D. s+ W% Z
0x00, 0xFF); /* configure the clock for transmitter */
6 ^! T5 y# G# ~- x( wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! h7 M S7 g% a. i C# y4 I% m8 ~2 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + I' W, R# i3 ]) C' u c% g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ ?/ L8 n9 y$ D7 S7 o
0x00, 0xFF);- L- U1 `" t4 [" o2 q
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/* Enable synchronization of RX and TX sections */ 6 q3 W- V1 [% p2 p s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: Q) g8 \% X t7 k5 y6 Y& Z2 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" m4 J- U; B! W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 X- M& ~- M# W+ `& x- b( o** Set the serializers, Currently only one serializer is set as
, j3 H/ m$ ]/ r0 e** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 F; `9 `% {* Z6 w' m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* P2 b, A/ I5 v2 v9 ` e' }
** Configure the McASP pins ) ^/ V" u# h7 B7 [, _/ G$ y+ ~+ ]
** Input - Frame Sync, Clock and Serializer Rx
# m0 s2 Y% z2 W** Output - Serializer Tx is connected to the input of the codec
9 K4 B) K6 l" `+ a* V5 Q# O. l6 A6 Z*/
/ x! l; h- ~: f7 l( y* p* I) {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& r6 i. J4 r0 D. t" g9 x$ g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 @/ k8 Y4 r" e) y$ t7 H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 } A- T% ]" V9 j. n! V L9 V: {| MCASP_PIN_ACLKX
8 u# |* e$ i# y6 |* ?( @* w0 U- a1 H| MCASP_PIN_AHCLKX+ {: T Q" x0 @/ P/ P& I/ l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# Z7 R6 J. P1 SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& r( W% Z; H. Q5 b5 a| MCASP_TX_CLKFAIL
6 E( |& R5 A% }* O9 C| MCASP_TX_SYNCERROR
. S0 @6 f' a7 Y2 I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 z6 O7 J9 X! U
| MCASP_RX_CLKFAIL1 k* ]: k1 f* g+ t$ L, M
| MCASP_RX_SYNCERROR
$ s4 S0 ]& t- D| MCASP_RX_OVERRUN);+ f* @: b5 ]! Z- c5 N7 J
} static void I2SDataTxRxActivate(void)/ l! Z3 q, c1 T d5 |8 A4 C# d
{* o1 L0 O2 s/ e# ?
/* Start the clocks */, C6 a% D: `/ R* h& r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 L8 w6 h; O5 ~) B% ^, K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' `( V' p! r; A. |6 A. O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
[2 w8 ?4 [( ?$ Y: wEDMA3_TRIG_MODE_EVENT);
* k6 z0 s& e G3 }& S; S" e! H* OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- N" a$ a2 {& K0 S# e1 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// H8 S0 w( R& c5 k5 ?& i' x& T+ `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( _" ]; I$ z6 U8 ?. d( p+ gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* J6 f1 V2 B1 j9 y0 \0 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, W" w- |5 u1 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ L6 @9 x* Q" t+ [/ ~6 a/ x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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