我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 m. L$ R# f& j1 b! g$ \! R C3 u
input mcasp_ahclkx,+ g5 |! w4 R9 h& N$ d3 _ X
input mcasp_aclkx,
4 N& B5 A5 I/ ~9 l' ~& Vinput axr0,6 L8 |: G# `/ Z n2 F
# y) u! q: }: [& D& y$ I2 ~$ Coutput mcasp_afsr,0 k, }" }: Y+ d
output mcasp_ahclkr,
& S; @# U0 w0 ]5 }$ q7 Ooutput mcasp_aclkr,( G1 F* T( e2 }" E
output axr1,* Q; S+ r+ M' z8 \
assign mcasp_afsr = mcasp_afsx;
" B7 R9 l/ w- v: Sassign mcasp_aclkr = mcasp_aclkx;
0 j# D/ }6 _' X: m2 N! z/ s0 M4 W- {$ _0 cassign mcasp_ahclkr = mcasp_ahclkx;
5 D! k F( A% `; q4 q4 Wassign axr1 = axr0; $ N x9 r- b$ Z
+ P a% {% j6 D0 V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ _; a5 @9 j% y M) P
static void McASPI2SConfigure(void)/ u8 s9 p5 ?6 L' R
{
: g. L& C) z; EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* x8 m& S( J, ~! b2 n6 @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ h# {. s# M6 L; f2 ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ @& M8 `7 u% f/ F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" ^' p G/ m6 N0 o0 z! pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ h& F+ N3 S: f; T0 o3 U
MCASP_RX_MODE_DMA);
; q4 K2 _% J& Q# I! jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( M6 }+ r3 q! T/ o, g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" l9 W) |; n! r, d* q G) L3 Z# O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. z$ G8 B4 h5 X0 P: v% m$ a6 FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ Y5 d0 Y6 S8 V# ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 {5 R |3 X. V, MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# F( r; U# o2 z! o5 P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ e& @! S( ]. e FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% _4 q; L+ \- I: [$ _! ]8 M' v6 [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, ^4 @- W4 ?, v
0x00, 0xFF); /* configure the clock for transmitter */" u; X( s% N; D# F' p; q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 `( d! X! W: w* l0 \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " M" X4 F' k9 ^1 [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ V8 {4 P! i* ?0 E, ^) l, T9 e0x00, 0xFF);, f; T9 o( |. t/ Y; Z
/ {. r: N0 [. R+ N2 R( E9 |* w
/* Enable synchronization of RX and TX sections */
6 N* u4 _7 K7 l0 w7 GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% x" [( l1 ~. [! ^: ~9 G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( O% q3 g& k6 i9 E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! c% z- M9 t$ I; z' k8 V% P** Set the serializers, Currently only one serializer is set as
: d2 w! l0 E6 c! L** transmitter and one serializer as receiver.' E* T P1 Y( g* J3 A0 U
*/
' [6 X9 {4 B( I3 N5 @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 T+ }- u$ B* y' @1 D, H& K; a AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 p- n9 T! j' ^+ A- Q- g
** Configure the McASP pins
c; E. |, Q! @& G7 b& b** Input - Frame Sync, Clock and Serializer Rx
/ L# v0 [" n0 |; k, s: \8 E1 d0 |** Output - Serializer Tx is connected to the input of the codec : }8 L: {7 r* m
*/
- F* W* ]8 j# _7 Q6 ]* T7 `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- {! ~! l/ z5 p1 r7 QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); I: m& [0 U8 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- B4 b4 e! r( q- o- D
| MCASP_PIN_ACLKX
4 ?) Q; T& f2 X9 u2 P- ?) y. g| MCASP_PIN_AHCLKX: c3 L( P2 w; z+ d9 K$ [/ M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 F# S! U) j$ M3 iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & Y7 |% Q4 g6 F7 u- L4 e# Y
| MCASP_TX_CLKFAIL
1 e& K1 ? I# ~1 q9 B2 R4 B, l| MCASP_TX_SYNCERROR+ u/ r3 K; M' i3 y6 {' B) D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % ]6 I: v3 m8 v# @
| MCASP_RX_CLKFAIL, r' ^+ p" q* {& P8 z
| MCASP_RX_SYNCERROR 8 R5 y# \. \; S# p# T7 I
| MCASP_RX_OVERRUN);( w" {& ` e, @
} static void I2SDataTxRxActivate(void)8 K: ^! F/ G" Y& Z6 }" X/ H
{" j8 @ `% S$ x, w F. I7 }. I9 [
/* Start the clocks */
. e+ d4 E' C& k5 I5 V! n2 rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. a5 v9 e. D' L. q! H! O( rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 a, ] ^& B$ e1 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# K+ j) a9 Y, @ W: b
EDMA3_TRIG_MODE_EVENT);
/ Q/ y4 ^8 T( C8 L1 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 q3 L1 Z% C' j4 d: @7 s1 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" D. d, P! m; u v8 X2 l* e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; c$ T7 a/ x% i, ~) R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- z u/ r2 v& g7 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ @. P; X6 Y7 X. Z' N7 m& pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* j/ @ ]% Z3 `9 b+ N, iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ \) f( p" E1 t' n, B) t} 0 y: I5 ?5 r/ _, E, V2 ~+ o% Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
+ |) `& `# d: g7 c1 c; {$ ~ |