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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' o/ J/ o3 T% J, kinput mcasp_ahclkx,
4 a( D5 [4 |' v3 o$ R& n/ Sinput mcasp_aclkx,
6 n8 T6 b+ A1 g1 a5 e" Binput axr0,
4 z7 b5 z- w! }5 U- W- o9 H6 j! ]+ w4 z: x9 @
output mcasp_afsr,
6 B3 K# n( u% C$ P1 S' E& soutput mcasp_ahclkr,: l% b7 m5 n) g1 _
output mcasp_aclkr,
/ j! d- k! _' P6 V9 b+ \. Poutput axr1,
# K8 m- o% d i assign mcasp_afsr = mcasp_afsx;8 L) M# `2 l2 ]; K0 ^& l
assign mcasp_aclkr = mcasp_aclkx;1 e: ~5 I* T# i: {1 ]5 f. H, _
assign mcasp_ahclkr = mcasp_ahclkx;
! t* [ _6 F; f7 z' ?6 vassign axr1 = axr0; y4 y/ Q# H$ ?: V+ C: } o
& y2 u4 K2 S. [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 s& f; w; p' s: y
static void McASPI2SConfigure(void)+ A8 S; N$ y3 }, v% F% @- W
{
8 N! v! f+ D* n r7 j8 hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, j. t( Q+ Q% G2 A+ d& @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, r, W5 J6 t3 T( ^' H: T7 JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& z. ?' J6 g" [" X4 _+ e0 B( mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ _; }- A+ n; _3 t5 T: d- v8 AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! D' ]. d3 E, w
MCASP_RX_MODE_DMA);
6 @9 ?$ Q: z3 X- X- z5 Q9 u2 ^% }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 a0 a! j c {% Y/ u2 C. @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 ~, Q/ t* g( t9 o! Y+ \8 L% @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ I/ S9 l% M2 B$ c: QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. p8 N& F4 q, `' t8 ^' R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - T6 j* M3 |: v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ Y* m: i! N8 e# ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% }/ I, h' V( n+ W& {* p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( A; D5 A1 x9 ]! x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# D0 L# Q0 B, D5 w* _
0x00, 0xFF); /* configure the clock for transmitter */, S3 g v( D$ G! t7 x5 h1 H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- h7 k" q( E2 V+ S) y X1 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! O& j. s' J1 V; ^, x3 F/ n" {7 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 u( _& C; F- N5 }0 o, z6 K4 E! r; @0x00, 0xFF);
8 V4 l3 w. }7 G& P) b0 o8 D9 {) u' o
/* Enable synchronization of RX and TX sections */ / P) p2 E4 Y: K% K: Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" ^7 o9 K, B2 j+ {. sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 R, O5 s! F. w7 i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) j7 K1 o8 _4 n8 d* i3 A9 u! R
** Set the serializers, Currently only one serializer is set as( V/ H) b$ Z" G8 W
** transmitter and one serializer as receiver.
/ c* J$ A; ~( J | S9 C+ c*/
8 a: d! K; z/ v1 a, ?# LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; g# Z3 U2 I5 k+ o4 r/ |# R. kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ }1 f3 V- K! ]" B$ }1 S
** Configure the McASP pins
3 e- d/ u) l- B' X3 v. O" t** Input - Frame Sync, Clock and Serializer Rx3 P0 m0 z& O: j. |
** Output - Serializer Tx is connected to the input of the codec
9 Y. q* \: g, z2 S*// d. v* f% [8 E3 _1 \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' Q4 c% F' n( S: ]; R2 N) ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 B: p" o p7 m0 uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& a3 {2 B- g( N) s' M% W
| MCASP_PIN_ACLKX+ C- n0 m' S( K0 k4 ~
| MCASP_PIN_AHCLKX
! Q2 W- r- @6 l2 L' ?- n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 |+ E/ m5 d t1 c9 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! t. S8 {9 U& O| MCASP_TX_CLKFAIL 4 j+ Y, k1 Q) H
| MCASP_TX_SYNCERROR# z4 d4 {# Q) Z* C2 O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * ~ P" k0 V9 H: X# R
| MCASP_RX_CLKFAIL% h; Z% L1 h1 o1 _6 X5 b
| MCASP_RX_SYNCERROR * u3 H& g5 p8 t; `
| MCASP_RX_OVERRUN);
7 X4 I. A5 Y% l" X4 X' U} static void I2SDataTxRxActivate(void): y/ a/ m- ~6 R5 s; @) P
{
; |3 t' V% J; i5 E; c7 M+ P/* Start the clocks */# T; {$ D' c/ @5 f, Z6 w+ s4 H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( p/ ?% K" Q3 D* r- mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ m; O3 z+ m* ~1 N7 J! @5 |- HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," o/ V& D. O# s4 u+ F O! I1 a
EDMA3_TRIG_MODE_EVENT);
7 Z& `3 [8 q) f; ~& `9 T. zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! ^" h* s# |4 e$ y# p1 U: } ]! ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; v$ |9 Z8 j3 e$ e# ~& V4 n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 \2 a3 k' \% J( F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 [4 f- V, D5 @% x8 s8 S% G! h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 I, i9 x8 o, J2 C1 S, AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 b: r$ A- z& p& GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
[" Y$ w; B1 H1 f; {0 C} 0 _5 b4 N+ r. N5 E2 D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 O" P) @* {8 B1 n, ?/ j- v
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