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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# B8 j4 f! j3 T! p; G, \/ u; Minput mcasp_ahclkx,
- I- i$ ?7 _* B1 g' Hinput mcasp_aclkx," ~* d5 M% z/ s( W( h1 Y
input axr0,
! F A$ r L/ @0 `2 T
6 e+ Q/ c. T: T( loutput mcasp_afsr,
, O4 U9 j7 c! s# k$ b& J! Loutput mcasp_ahclkr,
9 s& O( A* Z: t) {! ^! joutput mcasp_aclkr,
8 _7 a! d9 b- Q0 h1 A4 Doutput axr1,; K r' _* g! Q" f& l& m U' _
assign mcasp_afsr = mcasp_afsx;3 ?) A- @1 x( O7 ~6 j2 O/ x
assign mcasp_aclkr = mcasp_aclkx;0 o K5 P/ Q+ S; Z/ w6 m" Q) d) c( I
assign mcasp_ahclkr = mcasp_ahclkx;& X3 S2 e! k/ f: I e7 U' x
assign axr1 = axr0; % t+ z1 v7 I. S" |; ^5 L
1 J7 }5 J3 v( b& @. c; Z) t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. z, l5 P6 w" estatic void McASPI2SConfigure(void)* n7 X, B7 ?3 h: F5 W1 R& O/ O& Y( W2 M
{
6 T3 t, S; ?" G4 Q; \ EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 o8 ~0 }2 ?" F2 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. @3 s6 Z0 c. Q: `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 y) s/ w% A% U- R' e3 l( |1 dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 G6 P/ s6 F _. p6 w rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! u! N8 U4 N) ~% z/ [MCASP_RX_MODE_DMA);; n/ [4 h# F. e E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 y. N$ r2 U4 z T7 w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" r& r1 d, T VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( \' b! V5 j: A$ E7 o l! |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. J2 T, f0 K' b0 `/ g# A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' E B, l3 V6 _" \4 w, e4 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
U5 J$ p1 M' m6 ~6 G H7 rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 ~% P1 y( i* g' |. r* bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* \+ \ k8 C' I" ?+ T& N5 w- QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) j/ a8 W! t" }0x00, 0xFF); /* configure the clock for transmitter */; \; e" T6 W' v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 @) A9 k# B. {- v$ pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; P g0 t; N; e" ]5 Q# g" z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* J# X% u+ J. n8 L! D. u# m
0x00, 0xFF);( n+ R1 t. l; }
, z8 G7 ]- H: ?8 Z6 J/* Enable synchronization of RX and TX sections */ ) E; l, ^4 V7 E) J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* e# k6 `" N# j0 @" S% z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
?" j6 Y6 [7 n# r3 l9 WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ P! L9 N9 M, Y0 c+ A0 `( q
** Set the serializers, Currently only one serializer is set as
& R' ?' Z( T* N2 L+ \' n** transmitter and one serializer as receiver./ B* ?( Z! L5 S( Z d0 Z8 G! z; H5 Z
*/
$ @8 r# ?1 k+ L* j. HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& E5 i6 R5 r2 r$ K8 C+ GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' `4 s& z/ q& D" O3 }! p$ V/ W** Configure the McASP pins ( e, u7 C' s/ i' s& g
** Input - Frame Sync, Clock and Serializer Rx
. ~7 K9 Y: W; B# [; W** Output - Serializer Tx is connected to the input of the codec
; n# t# e1 L& v+ O5 f9 R. V \7 c W*/
5 \- G1 N5 {8 T3 N+ ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 ]' q* v7 ~: C/ {* E( m( p ` A1 Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 e: f0 u/ t2 @: _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ Z0 p% F& l' E' G! t7 A
| MCASP_PIN_ACLKX) x7 {! U* T, ?$ U7 W# I+ w
| MCASP_PIN_AHCLKX
8 Y/ k4 [9 ?* C$ D- s2 c- ]* z5 a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; q% O9 ]& L5 u" O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 C5 `: Z6 w; A: T3 C+ a% S
| MCASP_TX_CLKFAIL
/ Y( h( F; G6 h" G" Q| MCASP_TX_SYNCERROR* K+ N- f5 m4 u+ y9 ~: Q `! C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 L8 k/ N) ?' } _8 ]5 |" l. D; f| MCASP_RX_CLKFAIL
% d( e1 T# z4 g |; p7 g| MCASP_RX_SYNCERROR + t8 y |9 E9 X1 t2 \5 [) f
| MCASP_RX_OVERRUN);) Y X) g+ P' K$ p4 g B3 V
} static void I2SDataTxRxActivate(void)) N E* `) y, q7 V3 X
{' ~: Z/ ~ u3 o+ \2 j4 Z& V
/* Start the clocks */5 }" L. [9 X2 [1 {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# u' s0 _* {0 oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) r0 A* x6 G/ M- L6 j* j2 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: ?8 A' U7 k! L1 N& U) \2 o, ]; H
EDMA3_TRIG_MODE_EVENT);9 t7 l, I* O3 A3 g* V$ l+ N; P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) g' X. H3 h2 p* uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% B+ P5 K' F" O0 ]# z7 u2 K! s& b3 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ }: @2 i2 L& E$ \; c% Q' g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 f) F0 O: s: e4 Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 n1 [2 `/ G; g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" n" r# w' {9 P7 G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 `! r9 T3 ?4 @+ P3 \, u/ D) E' c}
: n; L: U1 D: ^- Q& }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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