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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 E5 Y7 C" j8 A; C1 e
input mcasp_ahclkx,
2 ]0 F8 e) w, v+ e; Z& [% jinput mcasp_aclkx,+ f X% V2 L% n( }
input axr0,
, _7 O4 S+ ^: h4 g+ d: u
2 o$ t1 F$ ?" S: i) X7 v; Joutput mcasp_afsr,
. u2 N. D/ _8 z s8 d4 E6 n" Eoutput mcasp_ahclkr,* a, T" g7 y7 B+ d) n
output mcasp_aclkr,
! K: C5 C3 M9 D, h9 X2 Houtput axr1,8 O/ O7 a% R3 f( C7 @7 h' ?
assign mcasp_afsr = mcasp_afsx;
3 k) J6 }9 t( \, h* c; L5 sassign mcasp_aclkr = mcasp_aclkx;, U' M7 f5 o7 k, S& M( N" l
assign mcasp_ahclkr = mcasp_ahclkx;
; W% J$ c9 G* v- @% U5 q& G9 a1 xassign axr1 = axr0;
# v( U; S) |) V( N( \0 T1 r4 S) o* W" _) V9 U& A5 N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 o# p: S# S7 t
static void McASPI2SConfigure(void)6 o& s- |/ }" o1 E; E
{
* j- \/ q, I" f7 c# N' H' eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 f; k6 @/ h5 c: WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! ?) {6 e: W( N Y- m2 {+ C! ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% {& O$ ?% ^# iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 B$ T7 A: Y3 [! a" d% J3 y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, \. L2 w. R$ O
MCASP_RX_MODE_DMA);
7 m- a' U: b# N7 E. @( YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 ^! N K1 M: |6 J! p& w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) j2 T {9 E+ g' E) ^& T% p+ n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, [5 w# ?6 W5 }# D6 g2 Y' nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 z# c3 l4 ], u, C IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 U4 `" e0 X# [* S& s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. t/ x2 ^# \: Z2 F. n# \" DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ Y1 ^8 `0 h; C( w0 S) Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 P! w8 e K9 p2 |% \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( f- O; C% G7 S1 v# m. I9 i0x00, 0xFF); /* configure the clock for transmitter */
7 F6 L4 N, u( |; f" V8 q( vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# g: r- y$ ~0 u0 A% M( ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ ~/ x! v$ o: M. tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 d% B7 Q6 R- w0x00, 0xFF);3 h" O2 y' U; Y8 y
$ z$ J e) C6 i& L/* Enable synchronization of RX and TX sections */ " N6 E# f4 f& Y9 I6 i- F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// p% N; |6 B- ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 J5 W; d4 ^0 m* G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& ~8 l4 ^: M- W% l9 |2 ]& F
** Set the serializers, Currently only one serializer is set as) Y4 v- t9 @; O& c) i2 c
** transmitter and one serializer as receiver.( v) e, A' R- _4 k
*/; T* G3 l7 y2 C5 H, i! q) U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 m y; z0 k3 L( a) yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; |! q7 t2 ~1 b1 x0 Q6 {7 b8 [** Configure the McASP pins 0 A" o1 f2 w4 I
** Input - Frame Sync, Clock and Serializer Rx
8 z+ W+ C: R" S" |$ `% L** Output - Serializer Tx is connected to the input of the codec 3 G! A" _: l E
*/+ D' ~" C. Z2 c t& ?" V! |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 ^) B9 j- N( `1 w8 xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: W- `/ U8 \; q ?8 E+ LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 I+ V" D) d9 W1 e* l
| MCASP_PIN_ACLKX* M1 v# I q. ]% ^
| MCASP_PIN_AHCLKX* P! E5 P8 y! |: b. u: ^% P" U# B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* }) ?) m& C ?2 Z4 [. R, l7 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 }5 @, t3 y6 k) e
| MCASP_TX_CLKFAIL & h8 h+ T% e w. A* Q, D+ o
| MCASP_TX_SYNCERROR
2 b) c. { v+ v5 `9 r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: X$ v# j& S7 w0 X& P- B4 T e| MCASP_RX_CLKFAIL
2 n# v2 |5 R" B+ T3 T/ ?| MCASP_RX_SYNCERROR ' Z8 z- e L$ G
| MCASP_RX_OVERRUN);
, y0 ^1 M9 i! Y3 ^2 K7 g} static void I2SDataTxRxActivate(void)# J' i% \0 |. f; k
{
# Y- o5 I+ k# K" k8 _# s/* Start the clocks */6 R; u: a4 b& ?* V; V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* Y" J# A' i* t+ hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- s0 U$ M+ ?- hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& L8 j% D! ~" zEDMA3_TRIG_MODE_EVENT);6 c5 [2 B( @, P4 Z4 c9 \3 h0 j5 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( K9 T) T! J% M. M. U6 F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. ?& ?8 x, r O/ pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* [5 `" f: H- e: d9 ~7 D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; A- [. D6 U" n* [& e5 G& `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, R9 @% T, }2 S- S5 ?# T9 x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 ]4 \( G; O. O' U( A9 Y$ q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% o8 v: V1 c, B6 l i) s
}
3 e; z& q/ w; m& G/ L+ ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 M$ C+ p- H3 g. H$ d- q) Y
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