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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ |1 L+ h3 m- K) a& u) Rinput mcasp_ahclkx,
2 T" J- f5 Q' uinput mcasp_aclkx,
% o- r, V% O/ w6 E9 finput axr0,
* R: u2 D# w1 D0 ^2 I7 Z8 Z6 j$ G
. y, ^# q* ]9 I# j" ^) Voutput mcasp_afsr,
! _! f+ w5 ]7 m1 moutput mcasp_ahclkr,
' ?7 u% z; E2 j3 c& S0 loutput mcasp_aclkr,
9 @# A- i# y! moutput axr1,6 z+ |9 _ s- V
assign mcasp_afsr = mcasp_afsx; H; C4 Y" H8 c) A
assign mcasp_aclkr = mcasp_aclkx;
8 y: X. K6 z$ L: v8 n- Bassign mcasp_ahclkr = mcasp_ahclkx;- ~ p. D9 _% ~5 b
assign axr1 = axr0;
& o9 N- O# |# g+ l
4 W% |+ v: p4 \! N/ F) [+ M! W/ S8 U# n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 N& e4 D1 A7 H- X. G8 O3 @static void McASPI2SConfigure(void)3 T" k, `- }* c- L6 l1 V% k
{5 h) P& Z0 V! C" V/ g- f8 O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 c% j+ q' [; U( s D7 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, m, r+ o, l! N( I1 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 M7 n- t& f$ U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# t8 @( J% V* QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: A9 ^; k' g+ U0 U
MCASP_RX_MODE_DMA);8 V. W7 N: n- n8 }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) t) C" @& @" ]6 D1 g: m; ?5 MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! q2 t1 K( S& `/ y/ O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # |- x/ E; {4 O' U" g* N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ Y/ @9 f( S2 I+ O. r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 x3 w H, J9 ~5 K! t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ G1 Q/ c* F5 w% |4 w( ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( |7 v Z! e1 j& ?0 {. }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. i8 t: a! L' l O# O8 gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 ~$ ?2 t8 ^, q3 m
0x00, 0xFF); /* configure the clock for transmitter */
$ V$ L; A m, n' r4 B& `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! A- u- z% U7 ~( V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 Q: @' R; {; O) b: U3 AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 p4 F) l& f& |/ `9 p/ Z0x00, 0xFF);
. y6 m* O& S9 |8 m5 z4 M ]1 U: Y- Y+ o6 [) w+ }" e, @7 l
/* Enable synchronization of RX and TX sections */ & Z5 i4 U# A% |; m- j: _# V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ y: [+ W z7 h8 X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) C5 D2 d1 A; h# C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: @1 D3 F; ^1 t
** Set the serializers, Currently only one serializer is set as
, Q6 ]9 M; F/ v) E** transmitter and one serializer as receiver.
+ [8 D0 I S, _; O0 e*/
, _: Q9 f3 Z( k, ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: T6 b1 N: k; b3 h; V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. f0 E/ {+ E T) ]: N$ a** Configure the McASP pins
) A+ X9 T) K0 a3 B9 c** Input - Frame Sync, Clock and Serializer Rx( w6 O9 g: n+ i' ]0 `/ O! z1 \
** Output - Serializer Tx is connected to the input of the codec
" z2 B+ b( O* C*/$ a1 T8 o1 W* ?# G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' b- ?7 W/ d. ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! J F& L- f/ x: G8 I8 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( F8 H( ]& L u5 K7 I1 z. ], |
| MCASP_PIN_ACLKX. r, [# k) j3 I
| MCASP_PIN_AHCLKX
7 W+ J8 r: I+ h+ B) i! h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% T, |: |- N$ m n7 Z) O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 N# L3 q3 x, \0 [
| MCASP_TX_CLKFAIL
: b. w- G9 p6 F| MCASP_TX_SYNCERROR2 s! P6 _& |4 N; _# _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; s4 T( R& H( Q) Y& C* l( ~& L1 H
| MCASP_RX_CLKFAIL: r* k) r$ V& k
| MCASP_RX_SYNCERROR 4 W5 j. |2 p* Q
| MCASP_RX_OVERRUN);
7 H( ~8 D5 ?3 j' V} static void I2SDataTxRxActivate(void)
; v9 ^3 y( [9 \# b j+ y" y{! b5 v4 b, r7 x( }; l- x+ ^
/* Start the clocks */
* U& T# n$ ~. t0 T/ c4 S: n( fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 f) d' u' T1 {: lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( z% v1 r0 u& s* [- UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 n7 k1 C2 b( y$ Z) F2 R ]' vEDMA3_TRIG_MODE_EVENT);
' u0 d; n9 ?: ?$ A& K4 r7 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 s; f2 s q/ g" i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 ]2 e2 m% [5 u3 m7 l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ e! P6 n& U# r% \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 y" O' b1 Z3 ~0 [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 `( _+ |: f( Z5 A: h: x) {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 q: n& q5 [% o* d' `9 X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- w' S, Y* I, n. u$ Q} 7 X) p: L6 W3 T( w* t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 a& _# f3 E1 x3 s
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