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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, J+ T0 y" O. z$ {. Ginput mcasp_ahclkx,
* a' F1 r9 \; y9 ]# V$ Yinput mcasp_aclkx,
" @" M A& Z% N6 U$ Finput axr0,
1 ~8 b( _0 ?7 a: _+ E! n
1 _! K' \1 T1 m) toutput mcasp_afsr,
9 F8 I! K5 o% Z9 [! K0 W$ P8 h% z6 Woutput mcasp_ahclkr,$ w: H6 \7 {) n+ d* o* i6 k0 R
output mcasp_aclkr,
M0 m3 S7 {+ k' Zoutput axr1,
4 g: N( Q' {/ M( k: m' d3 } assign mcasp_afsr = mcasp_afsx;2 @3 h" M- A: X! k! Y3 g( A$ S, ~+ l! A
assign mcasp_aclkr = mcasp_aclkx;0 U/ o# h, }( U: A! R. l5 Q9 i
assign mcasp_ahclkr = mcasp_ahclkx;
2 W2 b- }7 L8 ~2 Sassign axr1 = axr0; 6 l& [" p! P5 z7 r6 `$ G5 ^0 D
. T$ N" J2 M* n: S' N" N/ A2 o C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 ~* H5 H2 t3 j/ C0 \4 N4 y
static void McASPI2SConfigure(void)
" ?9 B8 ~; M8 B{
5 _/ }; Q9 i) x8 hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: g: Q& I0 n3 ]8 W' uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 k1 N, L; Z* p& W {; o# }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ p( F7 \/ m6 n p) ~: F1 a+ BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ H# @0 Q3 o- p1 jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% f2 U. q& t: c: B2 P, Q$ k- n
MCASP_RX_MODE_DMA);
( Y8 d. @- I% @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' ^8 s0 x! T' Q# a2 T6 N& Z: L7 O( `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// c1 d1 e4 ^/ v. c- b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 s9 }* W2 \2 h* P' W: N! f6 u) D2 ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 e4 M9 r; B. s' i9 QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& A0 `" L, x3 _( M; V' sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) e; |" t2 K* n- e/ k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; j. u" _7 ]( `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% s8 c2 [8 u9 K8 D0 O$ Y' s! kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& D7 y- g4 C7 C5 |: J# w2 A0x00, 0xFF); /* configure the clock for transmitter */
' H$ z& T" H# D: c( }! KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 z! v# z% _ h7 ^" y4 YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- Z9 U' U: B' @) R7 DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- a. f9 T) s$ o( s/ S! V
0x00, 0xFF);% H6 h( p* H. t. |+ i5 J
) b! O* d E1 J0 H% W7 B/* Enable synchronization of RX and TX sections */
6 A8 j3 D$ E9 i! V1 o' PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 j5 o! `7 v5 e/ SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* ]5 s. I; X! u0 i0 B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 p# O$ u8 o1 Z6 B# O4 _
** Set the serializers, Currently only one serializer is set as
* Z9 Y1 |6 _8 a& W6 J1 I** transmitter and one serializer as receiver.
& ~. X( Z& Y' K2 s+ x*/: U- o1 n5 ^, A% o! @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 M3 C0 B. M% q+ e9 O- A$ a D% l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ r& i/ Y) M$ Y& |( D9 H( @
** Configure the McASP pins $ s) e* o! L3 {, l' u/ r0 s
** Input - Frame Sync, Clock and Serializer Rx
* y* J/ c7 M6 d** Output - Serializer Tx is connected to the input of the codec + l% q; ^* ~: m- p: o
*/
/ G& D; H; k# ]! i( }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* r0 i* t7 {9 H, N1 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ _3 H7 J- {9 B5 q& }$ \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 Y" n& `& [( r6 e: a, _
| MCASP_PIN_ACLKX
( Q p9 M9 g. v# n+ `% S" b) X| MCASP_PIN_AHCLKX
& [3 C& H% p7 _) _2 [1 W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& l& K; A0 M7 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ h0 d* h' V7 _! @| MCASP_TX_CLKFAIL N9 u, n& f! ~6 }
| MCASP_TX_SYNCERROR
- o& Q& M6 E7 _7 Y$ m2 v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ {- Q3 B2 y' c. h0 }: G! P. l0 ?| MCASP_RX_CLKFAIL
7 P4 J! z1 C. j& g3 M( b| MCASP_RX_SYNCERROR 0 T2 g2 G m N; I9 ]2 a
| MCASP_RX_OVERRUN);
. C( p2 S: V, f3 x} static void I2SDataTxRxActivate(void)! R( L F( i* o0 _
{; ?8 d' g/ Y% H# I
/* Start the clocks */
9 n& ~( Q2 \9 V8 {+ zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 {4 D0 }8 W3 |5 R6 v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 L1 |( ?; h' F+ b" f5 N2 G* \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! ]( X* P9 @( KEDMA3_TRIG_MODE_EVENT);$ \/ g" n0 ^' e; v" V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 _+ P8 ^2 }7 U& e# [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! K R5 Y& o0 o; d' a( u1 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' J& _ b ^+ Q" S- I8 t5 @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 U/ q0 T( x2 z6 H# Q/ Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! c L/ h* j, ~) k6 k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, Z* }# m1 C" g, c8 l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 [3 q3 Z- N! \. n}
7 n7 ]$ {: A1 g/ V+ e' m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : ~$ u& M* q5 s) r
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