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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 z9 t8 d; u; f1 A# Finput mcasp_ahclkx,
: M4 l2 d. Q: J* K9 i W0 E( A) winput mcasp_aclkx,. d; V. h/ p- ~( ~9 P) E9 u
input axr0,
3 C, q/ B5 M# h) }9 ~' ?- G
2 w1 k' b. A4 G$ b1 N0 e: y% routput mcasp_afsr,
9 V; O! o3 w. ^. X1 Q& f, v0 doutput mcasp_ahclkr,
+ e/ J& D; b, e$ L+ ]# U' z- u1 qoutput mcasp_aclkr,: y: F0 x2 a- C; Q: N0 t6 p; M
output axr1,6 B# x+ n1 a/ p; _4 @
assign mcasp_afsr = mcasp_afsx;$ ]) u1 x* I2 G; Q
assign mcasp_aclkr = mcasp_aclkx;9 L$ r2 B) ~6 n+ P4 q5 M$ r
assign mcasp_ahclkr = mcasp_ahclkx;1 t$ y( t* h: l/ b3 Y
assign axr1 = axr0;
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& Z! I! ?6 m2 P4 k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 d4 S' t" S3 n2 c
static void McASPI2SConfigure(void)
1 M! c3 A) w: g" s& T: A{6 c3 [! |2 S. ~9 C$ g7 S4 `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ F4 j! V7 v' F4 o: Z l9 j/ T9 i# s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 ^! w9 n+ x1 _+ a* @5 l: k2 ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! z0 m9 f H; n* }3 D0 o+ f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" p* i7 w$ O2 VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. n5 B3 u" _4 M1 K6 y% \
MCASP_RX_MODE_DMA);, w. L0 {- ~) ]* N3 [; t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. r( c. \8 F. J- F7 S. O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( x/ f5 X6 Z# Y7 A9 Y4 dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! V ]# y! b3 EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 P4 P! o6 A; f0 w- _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% g0 _9 r2 J O( w% ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// @8 v- Q! A. a, N+ F2 B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 K6 V! k. Q b* q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- f) F2 h" J% X3 ^$ |% m* ?+ t/ hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) e+ J. K# n: h5 h r$ A
0x00, 0xFF); /* configure the clock for transmitter */
! f& i. v" ]5 ]' tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 I( t4 z, Y- XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
T2 |+ w9 Z$ i! r; dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% I" L5 d& r, D
0x00, 0xFF);" m" L9 |, T: o( b3 M7 w; w. N
" o, {# V- \( @# C4 z3 X: [9 z/* Enable synchronization of RX and TX sections */ % v( y% s; u9 N! G- O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* V- W r" C7 O. `) ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 U4 E9 n8 q7 o* |( V$ E( }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 g# J. g P6 D# T @9 c5 |
** Set the serializers, Currently only one serializer is set as7 Q) X' u0 }2 c2 x& _6 @& D# f5 F
** transmitter and one serializer as receiver.
" S( s1 |+ p; d& _6 k*/* c5 q( e1 l+ x' I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 D8 Y9 t* O9 L5 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* o; M$ ~" y/ W2 B ]** Configure the McASP pins * f1 O5 B" d& X$ c! F
** Input - Frame Sync, Clock and Serializer Rx
# h# x' k1 D2 }5 a; d1 K k1 V** Output - Serializer Tx is connected to the input of the codec
- ?% w. l4 a- \9 _, }) ^; ]*/
9 h: n7 Q5 r4 k) [! wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 Q$ j* C# ^' T. O1 y. iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 {+ `6 E9 [( M" V2 A* O( D' mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 S) _+ _& i2 Y| MCASP_PIN_ACLKX* g2 m8 X1 u+ N7 l! i) Y, r6 h) g; V' \
| MCASP_PIN_AHCLKX
! f2 m. e3 t7 h( e3 o. R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' @- V m. L. F5 ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) s' K7 C- W4 a' e
| MCASP_TX_CLKFAIL
4 J: F) E. c) R. [' w$ z6 `| MCASP_TX_SYNCERROR4 F' V3 a$ M* ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 L2 y. Q4 B% N# ^
| MCASP_RX_CLKFAIL
) f$ A% f9 h5 e1 s| MCASP_RX_SYNCERROR
: f! K( N- D( o0 z| MCASP_RX_OVERRUN);) t* E$ q* k _5 ~* Y# X
} static void I2SDataTxRxActivate(void): J' O/ ~/ z5 ?, J$ `, p# `
{
+ d. n& v' n/ A2 D) P" f! }# f/* Start the clocks */
- z! D4 v; u" c) _( `2 RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. N% t9 S& |: w+ u7 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' Q2 h, u- H# s$ n- r2 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 }) Q0 N% w Z$ v. z
EDMA3_TRIG_MODE_EVENT);3 R( x) T# a/ a. w1 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) p% s# k# l% A) F* [- XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 y! a# x. e; b9 V* oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); ?! l3 {+ x; W b, m) K0 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 r' z( v* H6 U7 d! bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. }+ R3 i W% A# a" L6 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 c7 k* x/ R2 n0 s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* U1 g7 e s# I( R( B}
- }/ u8 V4 `9 G+ W" e4 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , F3 F! d0 G8 n) [, p+ ^
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