|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ N+ v3 b% z, ?# U
input mcasp_ahclkx,
: o H0 z/ p. Y- P1 { Winput mcasp_aclkx,
9 K' N. X3 ^4 V( R9 ~input axr0,5 U# T5 k. y$ | ~) T3 q8 _- \
. u3 ~7 E! \6 ^" C# goutput mcasp_afsr,2 i/ d% b5 r7 i- l% a6 w( Z
output mcasp_ahclkr,
$ E8 g8 P: [0 ?, {output mcasp_aclkr,
4 [/ ^3 f* K% H6 M! i Zoutput axr1,. K P" R- q; W9 Y! E! }4 d
assign mcasp_afsr = mcasp_afsx;0 y/ v/ ?9 E; F" s' s# ^9 Q8 Y; ], X3 U
assign mcasp_aclkr = mcasp_aclkx;( v8 ]5 ?6 m+ a# ?- d5 }$ [! O
assign mcasp_ahclkr = mcasp_ahclkx;2 z" j+ c: H/ H' ^& V7 D4 o
assign axr1 = axr0; % M4 \* c: x2 Z5 |' v; v& m
; o/ L: U7 X; c7 ^0 z! i& Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % l8 a% J/ f( q- ], V6 b7 Y- w$ K2 H
static void McASPI2SConfigure(void)1 s) A# s1 q+ O
{
2 V% U- g5 a4 r! ~! EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. d0 Q2 ^5 R9 @, J6 q) i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 a! H# O' p- G1 CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 T6 C$ Z3 m$ ]' ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& z( v; V3 X5 z# cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- X- t( O8 v n. M% y# c& t
MCASP_RX_MODE_DMA);% V5 ]0 e3 U- v! h9 }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 T* W9 Q/ Y4 h! D$ ^, W% V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) X& w V/ B0 c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & V! N/ I& O( o9 y. B; {- _& l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. q6 k7 e8 `) c% I# k" b$ _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , q9 R) F2 o" G( H$ _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* T% R3 L* v$ i/ T. Q+ |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% @. K4 `) }4 {( y, S4 F# R( w; R2 s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ ]4 T& X" T! e. t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 y& k2 W3 O$ B. Z0x00, 0xFF); /* configure the clock for transmitter */1 B) j+ X2 z; P7 ?7 C+ w( \" C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ X4 [3 ?) F) O7 }, B! X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 B5 |; |0 O5 l wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 i0 D: I. K9 J- z1 O
0x00, 0xFF);
* ]) O3 |9 X F9 G6 h @$ k- A7 ]/ U9 ~9 f% J4 {5 ]+ a, z
/* Enable synchronization of RX and TX sections */ ! m" Y# V$ Q5 N" i' F: s8 y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 S9 {: [& U9 I: q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! a3 A. w8 ~4 H0 J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( h; a) d3 O8 d1 \
** Set the serializers, Currently only one serializer is set as+ k4 N( h. t6 M t8 ^& _% I5 q6 E
** transmitter and one serializer as receiver.
6 d! M% n" C7 G" M6 T# E*/
) J+ T/ P" g% E' T, dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 d. f; }0 j0 EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 e8 G8 q0 Z% X/ ^0 }** Configure the McASP pins : ~+ E. Q; i5 V
** Input - Frame Sync, Clock and Serializer Rx: s' b) i: c% j/ a$ O
** Output - Serializer Tx is connected to the input of the codec
# t0 @$ D/ R1 ^' x. M2 ?! M4 ?*/2 y; D A9 |7 {7 n. w' S% G) s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 ~. e( K0 A8 C( a5 [. ?9 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 F; [! U+ V3 hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 f, H) R" q. [# ]' L$ R/ d1 G. O
| MCASP_PIN_ACLKX, {+ m: b# i' D1 [0 t# m- O& ?6 P
| MCASP_PIN_AHCLKX, _4 p0 [2 T. Y0 I. ]0 z# a J% _: S$ `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. v& j' m3 b0 h6 {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( H4 _. C9 x$ G. H| MCASP_TX_CLKFAIL * N; w+ J- I0 Y+ `" M( `4 F
| MCASP_TX_SYNCERROR E( I! u: h7 Y* ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
B* J8 {, j/ n* y! t9 I| MCASP_RX_CLKFAIL: Y' h# _ y/ c k' T* E
| MCASP_RX_SYNCERROR 1 T" ?8 \# _/ h# a4 b1 X7 ^$ c
| MCASP_RX_OVERRUN);. T; r" v& q+ R, v, A v
} static void I2SDataTxRxActivate(void)
' G9 @, p! t# c0 ?/ x/ L{
9 w3 b( q+ E, q* \9 O/* Start the clocks */, t6 l- B" @' Y. _3 B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" Y( Y. y3 ?3 ^& X8 @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 x8 [6 r" c _0 f, R% F% }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# p. @& a0 d+ c4 }: N4 L7 T* ~5 mEDMA3_TRIG_MODE_EVENT);0 D. y* a, [5 [+ T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ A& k! H( F3 y% z. hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( u0 Z i( M9 I" J! }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 t# U; v$ U- Z/ tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; [- X5 F6 j: j: d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% _- h6 n0 K. A# m* I+ n7 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% D/ d7 s7 E* {+ N1 u$ eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 D0 k* B% X3 @0 ]! z% H, G: U- D
}
$ h: n$ |) Q$ P( t5 R. T* R' ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 ^& g. w9 l* y. u: x! Y. J9 y |