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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 b9 X$ S1 ~* ^0 @9 H0 W
input mcasp_ahclkx,' L3 D$ X" j! }- U
input mcasp_aclkx,
, v9 T# y3 s; |1 |$ Zinput axr0,2 B8 F8 y& D' w& [1 Q
+ C2 _2 T; }. ]5 d- L. k! S# @% b
output mcasp_afsr,
3 u. U* a \$ Y: y. X& n, Coutput mcasp_ahclkr,
" x: o( S1 c/ w9 b. ?output mcasp_aclkr,! k( H" N2 d5 C) \
output axr1,
; m" A# G5 t" H; V assign mcasp_afsr = mcasp_afsx;; n7 r8 s# v3 k" m; d/ |
assign mcasp_aclkr = mcasp_aclkx;3 p( G9 V) n( h" n# a
assign mcasp_ahclkr = mcasp_ahclkx;9 j; p# _- R6 T3 t
assign axr1 = axr0; 2 x+ v9 g/ ^8 y$ {3 j/ s+ F. d
- G' Q+ B7 k2 W) ^( T( a" i& i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 e( _7 e6 B0 j: @# p6 H
static void McASPI2SConfigure(void)
. l* c) \' p- s- Z* t( g3 E/ y- }{
' E+ N; E! `% oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* W6 H0 k9 G8 l$ y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, X6 C5 \- T$ |* |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: c3 w5 `3 F) `1 s, H K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! w0 Z' Z) W& }- {6 B+ c5 FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( e: D' B/ g! s: z
MCASP_RX_MODE_DMA);
9 I/ _! p9 X# PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 G. ]$ W1 G% f$ S. r% _& ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 r3 _6 E& V1 w! o" |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) i6 r- h, s: n' k) p3 y/ ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 _9 `% t0 d$ i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% I4 t* z1 r3 |# \, _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 g- T- a8 G5 t; H. G) ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* W& g1 A! O0 MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) K, v3 L% e" K4 u) _+ }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& x& U, A; ~0 P9 w, _0x00, 0xFF); /* configure the clock for transmitter */
' A- O, L+ J3 |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); w9 l4 {6 Y$ g4 B1 `1 x' J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 r3 t% H6 w/ q/ d( \8 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) }, s5 P/ R/ N* m+ L0x00, 0xFF);
0 C2 l2 m8 ?- X: ?8 }
% R4 x: A5 h! A/ E/* Enable synchronization of RX and TX sections */ & W' K( c" l, F" A# G/ y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ [8 Y% T- R8 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 i! Q4 |! Y. P7 I2 P' S1 |3 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** l$ Z* {/ R% c1 n! T- N) F, L
** Set the serializers, Currently only one serializer is set as
5 X# c! V/ e) s6 `* I** transmitter and one serializer as receiver." @8 F' X" a* g
*/
/ \+ ?/ R) Y! D; n/ _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ r6 C" o0 I2 }" S1 G; B) `) o1 LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 s$ u$ W: T! v' g. Q, U
** Configure the McASP pins
' {; I7 k2 N4 l* v** Input - Frame Sync, Clock and Serializer Rx- t! l) s5 ]0 c# N* N% F
** Output - Serializer Tx is connected to the input of the codec
4 p* x7 L; ]& j# _" l! t*/
/ M" J4 Z$ k3 L2 O) m8 s/ e) W& hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: b% z# l& T% o& G% o! rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: M5 o2 n2 a. c3 H8 q& GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" X$ O( d. O* p
| MCASP_PIN_ACLKX, @- p# _$ T3 o
| MCASP_PIN_AHCLKX+ t/ H2 ?1 Z* D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- \$ j( I& u$ @7 Q7 l7 \" eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " b5 v, n6 Z; J% F; S0 R& E
| MCASP_TX_CLKFAIL 3 l* l9 _* E$ v, \+ A$ m2 `8 \, S
| MCASP_TX_SYNCERROR+ G5 }! y2 C$ }0 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' W. T# G. [& R1 s& `# a| MCASP_RX_CLKFAIL8 ^) Z! Q" x( x3 q4 z0 W
| MCASP_RX_SYNCERROR
. {' S3 B+ i" ~+ P. v( f9 F| MCASP_RX_OVERRUN);/ \) ]# c* t8 S2 j
} static void I2SDataTxRxActivate(void)
: K. a5 i* B# s* a2 s# P9 M{ J" g% B0 Q" U
/* Start the clocks */& w$ s s# n; u/ r M6 h- k4 T, Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# A0 _8 s, u4 k: HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, P; a" m% ~+ K5 d' F. @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 }- G E9 u: O+ X. u* ^EDMA3_TRIG_MODE_EVENT);+ H+ l2 P: A/ y5 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" d2 S9 j3 {$ v K9 f3 ~, @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* _. b5 A3 [0 }8 j8 F! m6 YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 M" J9 N8 d3 E. E v6 z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! m+ r- d+ G$ R) awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& M0 Z- T; j$ W. v( \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ S) b& z" L3 J8 h [9 ]- A3 u* T5 fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# L! b% Z N: v1 }; J
}
! ?2 o# J7 p1 A4 z( z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " K/ h k' z. u; V
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