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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' E& A: O9 Q" T# Einput mcasp_ahclkx,# j4 L& W l* h D8 a* \1 E
input mcasp_aclkx,
9 U0 e; ^1 k8 |input axr0,( B3 q$ \5 Z8 w- M- n
9 g3 i+ v1 x; r+ y9 w9 ]9 n0 foutput mcasp_afsr,9 X' ^ ]& m& Q6 O& H
output mcasp_ahclkr,
* s3 Q" Y, f1 R) d) S4 qoutput mcasp_aclkr,
. |/ [1 G% _3 w1 B3 ?output axr1,! u+ ?6 \2 {1 W) T
assign mcasp_afsr = mcasp_afsx;) I. I- M5 {4 v2 C
assign mcasp_aclkr = mcasp_aclkx;* c$ a- L2 T6 w2 M1 w* X( ]
assign mcasp_ahclkr = mcasp_ahclkx;
" |: Z5 ]: j+ m$ B# M' x9 oassign axr1 = axr0;
: p: }7 C: U6 ?8 p( L" `% N+ A! [
$ k" l* z) t6 }4 s6 e D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- Z: f! A( G l7 J5 [static void McASPI2SConfigure(void)
1 e6 W0 U1 {' B{
, T9 x; [7 I t) P. k9 y. S* C' `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& \8 ^) m) H/ |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. x, @. L3 B' q, Q$ XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) Y6 a" E/ `7 h/ q8 c. L$ \! c0 xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 s+ w/ i6 |7 v8 n. F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 ~2 y* {/ r7 t0 @8 w; Y/ T# TMCASP_RX_MODE_DMA);
7 E: l$ p$ Z1 _, QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ l' X7 k$ D; c8 CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' R; T4 f5 Z: I8 I! rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( y7 E/ d1 e8 e5 A. F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( O5 I6 x) t, r2 f7 [$ ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, X# t$ Y3 _0 x) H" \1 G% K# DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; k1 w5 F% z. X& |* G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; ]2 v3 ]: Q# S2 ?+ {* ^, F$ {- C f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # i0 x! W, I" ]/ k) K$ n5 R7 B( _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% {* Q" E# H8 E
0x00, 0xFF); /* configure the clock for transmitter */8 x7 g' T3 W/ [$ S! w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 l1 o% g3 L* {( q/ Q' w4 z& WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , \' T+ I9 V2 u! }8 l+ N5 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: {0 J. J. n f! M3 [' N" Y
0x00, 0xFF);
) f4 C8 O7 R6 u% Y& X6 Z" y+ C; r) p5 P+ F& e" Q( f* E, Q
/* Enable synchronization of RX and TX sections */ : Y! e$ H. v8 h/ [* M' j; j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 g/ g% I, Y7 X6 T/ p/ Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 R; M3 y3 O* ~/ r8 t B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 [$ r7 X9 t r: y7 F _- b8 t
** Set the serializers, Currently only one serializer is set as7 B% A! |8 @( M4 Q
** transmitter and one serializer as receiver.
! i& l& z4 ]6 F$ H6 b6 N*/- P9 C$ D- y0 e! l, p/ h5 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 _+ @+ Q L, ^2 l* Y% v* NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- q. u# X5 V% P( z9 n" E** Configure the McASP pins : H u5 A$ A, p" D) x
** Input - Frame Sync, Clock and Serializer Rx
& g0 a5 k2 Q1 u8 \- Q N, v** Output - Serializer Tx is connected to the input of the codec & M3 u$ [0 {5 m! Y! M+ w/ U# L6 s
*/! K2 W+ S$ B: w/ ~# M/ h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, t, r+ X) Z0 vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ @ }- T! s6 h- c- BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 u: v: [9 c9 N/ U a+ H3 S- T+ @7 j
| MCASP_PIN_ACLKX
# ^: z0 ^% f2 Y6 w$ U; ~! a1 x9 R| MCASP_PIN_AHCLKX
% c0 @! B7 q) O* f D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* m5 {3 h* D$ [- z( cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + b5 k1 B. E' s; p6 Y+ E- @/ O
| MCASP_TX_CLKFAIL
% ~6 r2 f5 K$ h9 B/ D: l" r| MCASP_TX_SYNCERROR9 P" n; f$ o/ |! [, G: _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / U1 s, K# N- E8 y( C& d
| MCASP_RX_CLKFAIL
2 l: Z' J4 m" h+ s| MCASP_RX_SYNCERROR & o2 s% T( q7 _
| MCASP_RX_OVERRUN);
) ~3 v0 k' L0 z; P* E1 i& r- D* L8 V} static void I2SDataTxRxActivate(void)5 t9 G% ?" u: [' u: u: t% T
{
3 f3 T, u+ E7 A' Z7 ~9 w/* Start the clocks */2 g# v8 v4 L( _7 p4 q7 m6 |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& B7 y! I$ |/ \8 d6 ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) ?3 j' l5 f. ^1 D# ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! K: T5 d, u1 X; z8 x% y
EDMA3_TRIG_MODE_EVENT);
6 u# b; S0 y$ j/ `& a {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) j$ P. S! \" S9 u1 H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: }* }4 K0 q, A! {( a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: D3 B# _8 A1 z" o/ j$ b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 N u# F+ D3 w7 {' y3 X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) m; o+ u+ g1 g+ I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 E, r# D7 d8 yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ g4 [, n$ Q, H
} % S# z6 L# ^5 n) P' }1 U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 s# c+ N$ |! r! U, k% o% K6 W/ B
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