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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* z. [' u; g* s; Z4 a$ K+ uinput mcasp_ahclkx,+ w! C% D/ C. g& ^4 x/ ^2 M+ t) u
input mcasp_aclkx,( q5 e/ r6 _' y4 l- \
input axr0,0 R! d* v0 b. R7 N9 H/ o, I
$ [2 K! j* B" O' p8 n1 E1 L6 G) C
output mcasp_afsr,
0 w7 C8 v( \) e% T! p. v- k4 [output mcasp_ahclkr,
" Q/ K9 ~0 A. T* e# ]3 q7 joutput mcasp_aclkr,* M! u+ p- T( U) `8 |* H+ i+ Z
output axr1,
( b6 p0 t0 _3 j; A4 a& O; T Z assign mcasp_afsr = mcasp_afsx;
" g, f& X; o8 w& uassign mcasp_aclkr = mcasp_aclkx;
$ h9 R2 [% I3 ~' M7 i: Y/ ^assign mcasp_ahclkr = mcasp_ahclkx;8 V# Y* H. @3 G) j. q7 U
assign axr1 = axr0; " C; x0 F9 t+ |$ i8 n+ Z
R c6 N) O# e0 y9 ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' u4 G& e9 P1 |* z% w6 F P( w! a
static void McASPI2SConfigure(void)
- b# h9 w) o1 d{
' `& X* }+ s% P2 T1 `McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 v4 q* J7 H! n6 B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 w; [; D, k% p' p/ k; F$ I; O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 d! S+ j# x6 T7 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 o' n3 r% Y; N5 ^7 I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ y4 d; @3 Z; m2 ~MCASP_RX_MODE_DMA);
" T" Y* e& v1 l8 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 Z2 }9 F2 d- h! m4 m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. D m( m$ y! k0 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 J3 n+ v( w( Y3 u" ^% ]3 v' Q7 r) Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 x5 H- O2 ?7 `( g1 X9 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 Y2 \# ]( i1 g. K H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 M5 m% d% S. @: Q( R- ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% p; b6 ]1 I) R2 z" uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + ]& T4 R% q1 E' A6 H% Z/ c0 c) J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 ?' L# P; m F6 @/ ~3 p" i, V: m" D
0x00, 0xFF); /* configure the clock for transmitter */. t) l0 ~" G: }* l& T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% G! v' l! I6 w5 ~" ]( }' _9 ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 Q3 A& {$ l; HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- Z! n1 |" T- M: _
0x00, 0xFF);
7 t: I b9 @: j. v) n& z6 |
& f$ W6 L* O. H6 s5 E/* Enable synchronization of RX and TX sections */
" o+ ^7 w2 o8 J7 I y3 UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ ~. [1 l2 j) P" p, @$ e7 D7 g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( @- }* w! X/ O$ V$ ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& h7 h7 B4 C, W8 M- |7 T: S, B$ C
** Set the serializers, Currently only one serializer is set as
' W0 M5 b5 e0 c/ }6 E! ~** transmitter and one serializer as receiver.
; a2 J! Q) x" H3 j*/
( z) S f3 o. `/ V! D, {) EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" P4 E# l, n/ _& B ~; l. h+ sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, w; `( t8 w& [1 c** Configure the McASP pins
( Z( z1 W. |7 h+ N; n** Input - Frame Sync, Clock and Serializer Rx! D/ a4 y5 s, T- v. X3 J/ k
** Output - Serializer Tx is connected to the input of the codec
* M( y* F8 Q5 T) t# q, R, ~*/+ Y/ J" n2 l6 _, l' P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ c0 R s# j+ k8 w n3 d; J% l( WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. ` k' H* E9 A9 P Q* d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 ^& \8 M! x. y. E
| MCASP_PIN_ACLKX; u/ k0 ?! \3 i- f/ c- B
| MCASP_PIN_AHCLKX, f2 ~% G4 {" n7 Y2 |9 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 _" n! ?4 O y9 E. f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 l/ q( I& |* ]; [" H| MCASP_TX_CLKFAIL
; a! E! \- k' V. ], W/ E9 `| MCASP_TX_SYNCERROR
9 `2 e8 m) L8 @9 K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: y' e8 C& F$ X X) u+ ` ~| MCASP_RX_CLKFAIL
5 D/ K ?7 i% R| MCASP_RX_SYNCERROR . j; `; n8 H1 _# s% e0 x# ^
| MCASP_RX_OVERRUN); N! v/ f: ]. n& W
} static void I2SDataTxRxActivate(void); A: j% q+ ^$ M" W
{1 ?0 W; t3 A! Z2 T& o! ^
/* Start the clocks */
& y( {$ Z! X ~ R: \2 U3 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 W: S7 y9 E2 V2 R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. W+ m/ u- [: s' j9 m `: p. O+ A. w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; I4 }: Y! v, P/ L2 T3 N/ h
EDMA3_TRIG_MODE_EVENT);
( p0 ` I- h9 V: M$ m: HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' n$ M( D4 j. @2 O7 N4 y* x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 c& H, o4 v- D$ cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ v$ A7 |$ _$ W! W3 {2 u0 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 R1 ~$ M; X: K% }& L7 s) c, Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, y$ b) i; ~: @# Y+ _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# G: c* |' }% WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 d( N" B% ~" |0 L0 l} ( B5 }4 P/ _+ w7 b! b3 a; n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 n! M$ B$ G, v$ ?: B, H
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