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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. W; b' Z+ D% ~7 V6 C6 J- F) q
input mcasp_ahclkx,
' T3 j4 {' d7 s$ d0 n6 y& W: einput mcasp_aclkx,
, a, y! ~* O$ ?: D2 Ainput axr0,
; [, [% I# X3 s% k9 J/ Z4 T) b2 E! |% Z
output mcasp_afsr,
6 O: @0 [6 e" b: N7 P8 g$ boutput mcasp_ahclkr,
4 b% S, E/ y- l/ ^' J$ zoutput mcasp_aclkr,2 e) n { [- ^; M
output axr1,
: E1 \0 W! \) t0 i7 O; n, X4 L: w assign mcasp_afsr = mcasp_afsx;
" d! J6 D r6 }7 G9 ]assign mcasp_aclkr = mcasp_aclkx;0 a* u* ] ]$ |9 R) n% b5 z9 N
assign mcasp_ahclkr = mcasp_ahclkx;
; i ~: r- f M$ O) _) d) z0 Kassign axr1 = axr0;
* i7 m$ S; F$ E+ E+ b
9 Y) B+ Y2 o4 y! W" X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 l, |' r3 h& c2 q3 v, n) zstatic void McASPI2SConfigure(void)
4 a+ u: j4 V. V) \4 E S, z{, }$ E' a+ | }& g/ F2 }7 p! V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 b& [) ?8 f& T; C1 C/ E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( v4 V$ ~4 ^/ k# Z# |$ k2 w" G) g! UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ {( U3 K0 a+ J2 e) \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 ~! f8 Y F& X1 }6 k* a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 T9 I' A8 z# M* K& a$ U
MCASP_RX_MODE_DMA);
! U2 H9 H/ }9 EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! l; C) k+ W( BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' M) j, O0 Q3 R9 b5 oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ Z. U) N" q' _( J6 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ Z. V. t5 O) ?/ tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 t3 K6 s j2 l4 V& }/ UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 r n; g7 g1 Z' Z% QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 w, q) g* W9 f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , }% e% }+ R) D" q: [) @5 [ I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, o, c% X$ Y1 O e- @( s
0x00, 0xFF); /* configure the clock for transmitter */3 Y) e2 c! m( X0 c. @7 n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' v0 d- t: }/ K" }+ S1 {' oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . g& m9 O" @6 r5 ]& d* E, c# |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' h9 E0 ]) x: U; c! ?0x00, 0xFF);
& y) Q# v$ t* P6 o* ?9 z. X/ ^+ }8 M9 h7 K$ f
/* Enable synchronization of RX and TX sections */
4 x: Z* [0 h t% j/ fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" ^) D* G0 H. V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); p- j! g& q i9 C6 o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 v% b8 \) ]% o' \" i& \6 h5 ]+ K% T
** Set the serializers, Currently only one serializer is set as' C% P3 H+ i5 ?1 P/ b# x3 J& G
** transmitter and one serializer as receiver.
) W% J: }/ X% E! R1 f" B*/
" c6 b0 G0 C9 q( pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* E- B' h) J/ z9 zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' i' K* C& o+ W8 G! \* F5 K( N** Configure the McASP pins : Q( u3 x7 e/ t' R
** Input - Frame Sync, Clock and Serializer Rx9 C" M. F$ _ L2 }& t- s, R5 d
** Output - Serializer Tx is connected to the input of the codec
2 \! z. O0 A9 W*/( g% I5 A5 h8 m" m0 R' b% z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' V e2 R5 U0 a3 h. ]0 yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 x$ ]: U2 f% H$ J: u6 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX h/ I/ v: @ N+ S7 |3 Q& q: x
| MCASP_PIN_ACLKX b, K N' F, t: U8 V# r$ Q
| MCASP_PIN_AHCLKX
. r9 k, T* K- r+ j2 \* o| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ P7 n' ~, Q1 |# A( o4 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 X# R: K% M% b4 A) h
| MCASP_TX_CLKFAIL
* z2 C j, E' k6 S8 C! m$ m| MCASP_TX_SYNCERROR, @ ?9 k! `0 x( Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' G8 |0 ]/ r) N9 f0 ~- |' J; {| MCASP_RX_CLKFAIL
: t L( N, A7 A# m9 P! h3 X| MCASP_RX_SYNCERROR % A3 r$ G4 A5 d9 U& x+ n
| MCASP_RX_OVERRUN);
0 ?3 A+ \1 E/ E3 H( s} static void I2SDataTxRxActivate(void)
3 P: W' H! {6 H0 z7 ]- ]{7 x' g( S: K, e6 I! ]; `, X4 f
/* Start the clocks */0 C# @7 r! h9 H9 q! ^ I( L/ t$ R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' M u4 k! o) U" G2 _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) _( L* E% b% l: M( G4 o% A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 b) w5 A( j+ {, |& VEDMA3_TRIG_MODE_EVENT);5 F. g4 d; }( V! S2 S7 m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 T% d* ^0 g& D5 YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 H+ p: [) l: A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# b( e$ R% k8 ?- c9 G, I& m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ s$ v0 k2 p$ q9 W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 A, k% t5 J( L1 P; Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! R8 v. p s/ CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! k( w+ }- @- c% B9 ^
} / @* v) o; I& C/ y) l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + {+ v, D' O- A3 W6 E
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