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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ T# @* D) S9 ~7 x2 K0 binput mcasp_ahclkx,
8 U* P, U5 j, J+ e8 t, o8 Iinput mcasp_aclkx,
0 w; H& o+ j! T% A& [& L" _input axr0,. r# W: A1 Z& B8 W
$ w: T' ^ P) N7 ]7 houtput mcasp_afsr,
9 Y+ ~' | H: routput mcasp_ahclkr,
3 J% J6 O3 w' e2 s: d: q' l8 Moutput mcasp_aclkr,$ R* |6 j1 E% w! J: V/ S- K
output axr1,
2 a+ X7 o z2 ~) o- \ assign mcasp_afsr = mcasp_afsx;
6 h3 F2 [7 W; {3 X4 V/ C, ?! dassign mcasp_aclkr = mcasp_aclkx;8 y2 ~$ N% K5 o* x9 x9 v; g* f
assign mcasp_ahclkr = mcasp_ahclkx;
- c9 @; C, @1 c$ sassign axr1 = axr0; / L& |6 I& l9 z+ ?5 ~" p
" z+ }! {( Z/ E8 z1 f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - \# ~6 f" W5 y0 V; F
static void McASPI2SConfigure(void) O0 s8 H' ]% C$ ^2 B. D ^ B+ p
{
2 \6 l; y: s4 g( HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: M) `+ F* p+ B9 q; x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# X# Z$ E* `& @& A! Q" LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 ]2 O) n4 b% I* MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 u* C9 \2 A9 Y4 uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' [$ [& |. u& t% ]MCASP_RX_MODE_DMA);
: c9 y6 M2 E- w- |) b7 iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. e) K Q+ s3 LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' o1 P( Z: G) O& n6 D& G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& k8 }9 D: y5 P0 X+ l O* ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 T7 u% e+ b1 X7 lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ f' Y/ o0 s$ e4 O+ M, Y3 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! O9 y0 c W, J+ t1 I, x% P& DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) w2 y& p/ I2 _' c; I' CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . ]; X. }) [, N9 }* T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, g6 _; B2 z0 J5 L+ c9 }
0x00, 0xFF); /* configure the clock for transmitter */
: D1 H6 \1 b: i6 {) t4 R+ ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; x4 n! ~" i* M4 U, k4 g. iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: e X2 H3 k* W: p, f* gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. W8 r- b, _* s1 V: f4 |0x00, 0xFF);
! E- o9 o7 c! h; W% H) }# B
+ }) a r' d {1 S/* Enable synchronization of RX and TX sections */
# A. D J8 Q) v" H9 w$ h' e* ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; T% w; j7 b( o$ A$ t, v# L/ g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* @) v" l0 B# o3 z. E/ E. X4 }" aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
O0 A5 R1 G3 V/ {% e1 M1 e** Set the serializers, Currently only one serializer is set as
8 a4 K) ]# k3 I; n) }8 K Z** transmitter and one serializer as receiver.% N6 Z6 l" R7 Y# @! O
*/
; O3 ~; Z1 T/ }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ M/ X u$ ]# d. d/ L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* `: ^" {6 n/ v; u" r& c4 W** Configure the McASP pins 1 d8 e2 U0 f+ h/ X7 g5 ?
** Input - Frame Sync, Clock and Serializer Rx
- h, \- k9 M! k3 g" z9 K. Z% x** Output - Serializer Tx is connected to the input of the codec ) L' a) A( J/ ~8 Y( b- z9 y) X
*/# B0 K/ X- l3 d6 D2 l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, p4 t! M, C* Z; f: fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 s/ g# J$ c9 |+ |" j6 R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: C, R8 n2 a. [0 j| MCASP_PIN_ACLKX5 S9 x; ^4 W! ?& c
| MCASP_PIN_AHCLKX3 y" P6 B( m, s; n8 l# i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 u2 X* K- B- V- i3 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( P2 X1 s0 W+ D f! ]( h
| MCASP_TX_CLKFAIL 0 z5 B. n- H2 \, d% Q1 L1 Z
| MCASP_TX_SYNCERROR
0 ~+ g d) R( ]% k/ _4 g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( _5 V$ R# R7 o5 h7 c9 k| MCASP_RX_CLKFAIL
# z' Q- S+ X, v S- W' m| MCASP_RX_SYNCERROR $ n+ G& ~% r9 Y1 i. u
| MCASP_RX_OVERRUN);8 B% B c0 `& w9 ]
} static void I2SDataTxRxActivate(void)
5 C: @3 ^4 F" c3 ?7 Y. J{% E: h; g* i9 c/ d
/* Start the clocks */4 {6 [5 f5 T5 P6 T1 M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* |" w7 o- l0 p) P' ~- rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ o& s1 M. Q5 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 M- u0 q! |* s) K, ~7 s8 Q
EDMA3_TRIG_MODE_EVENT);! y# ]+ Q+ j: G) N6 z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 L. E9 p4 @0 L. {; c7 P6 B. KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, F$ C( ?/ u# x! F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: v: P, ^2 @/ _0 pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 `: @+ h0 W$ u4 m0 [2 b; O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) u& h& M1 G' I o1 p6 X/ I- cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. h7 u8 b/ Q9 j4 v1 W1 y- S& qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: A. O1 _5 \3 [& C
} # v P6 H2 R( U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) N7 G+ ^$ ~6 k2 E
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