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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ `& R7 v" ]/ M' T1 n, pinput mcasp_ahclkx,
9 C- v% J( \1 Zinput mcasp_aclkx,
1 l. ~: ]! P- tinput axr0,
4 x* ^0 y0 U+ r4 F1 a* u8 U
3 b0 x5 U( E7 ?) Loutput mcasp_afsr,
Q7 ]8 }$ b$ k( houtput mcasp_ahclkr,
e' F2 W8 |8 X2 N* o q8 t: qoutput mcasp_aclkr,; n4 E& E: B% R8 L# b
output axr1," I- p/ ^: {6 o& J" z
assign mcasp_afsr = mcasp_afsx;7 B8 N- K2 ?0 ~4 s9 f# M8 s, l
assign mcasp_aclkr = mcasp_aclkx;! s' |9 V/ l0 k! A( I6 t V
assign mcasp_ahclkr = mcasp_ahclkx;
2 U, _8 w* {* q1 p4 I; w# {# yassign axr1 = axr0; ; ]5 [! J' b* N( f4 @0 W3 B0 V8 n
: o4 }# T5 ~( m1 g. E5 K V7 l4 n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# F: F# J9 q _) k* F7 T% qstatic void McASPI2SConfigure(void)
; ~4 h8 |' ^3 q& G{
& u, t8 o: ?* ]9 I. OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, O$ s7 P' M A! [/ Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. {; r2 l) _$ u/ i0 [; W! ]0 j+ I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# I( Q/ `; R0 M9 O# p; PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 ?9 P+ p+ t, ^/ v+ ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 M% j4 {$ u1 U ?
MCASP_RX_MODE_DMA);
6 w) n+ U% j4 v! S6 \& `% g" EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 r" t) ^7 B8 y5 b' m% P2 fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& K( u: j* J: S) w$ D _4 F+ ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 V* W, Z: I) `! d5 l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) X0 _$ ^* L( j4 Q3 k2 z* J9 n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 u! N+ S2 [! a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 ]+ ^. g3 r r. W0 L( q1 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ i4 U# x" U9 }- a' [& Q, ~# }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % X( {4 f' g% D, ?9 F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# N4 W4 ^9 p; u4 P0x00, 0xFF); /* configure the clock for transmitter */
- j/ B9 [1 m0 O( D8 z0 RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ C/ l; R1 O G( e% Y rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : m7 F# K3 q" x+ i0 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% z7 Z& g4 P0 a, p. N0x00, 0xFF);- K( n5 v7 q8 }2 W
! s4 c) \" I }
/* Enable synchronization of RX and TX sections */ $ [& V: x& ]& ^7 s, c2 D6 v; K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" }7 m9 P1 ?3 Q8 l! AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 a1 K+ e( B2 ]: h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 n5 v' M" e9 M/ {* P+ l** Set the serializers, Currently only one serializer is set as9 Y2 g; p! ?3 o1 @& Y. K
** transmitter and one serializer as receiver.
1 Z- L2 t6 b& [3 Y8 q*/6 ?3 N, e( Q. `1 B a3 j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- T6 f: y0 W% A7 \2 d+ U) E1 U" VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( m+ U0 C$ [' q% L' c** Configure the McASP pins
2 w7 \5 J- {+ e$ p2 c** Input - Frame Sync, Clock and Serializer Rx
) W8 @( i* h+ x7 R** Output - Serializer Tx is connected to the input of the codec * g% u+ |. M/ e0 m3 A1 Y
*/
" W3 V3 [ |9 nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# w2 t7 {8 S5 H6 i* m% e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ v. o" f; M5 H2 V* RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) h8 C2 Y4 _+ Y2 ]
| MCASP_PIN_ACLKX
: q( `" F6 L, r, R0 X| MCASP_PIN_AHCLKX
" h! F2 C( x+ d: q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) e$ I. Y4 p' r% `% d8 h7 e0 E; R8 eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 H. H+ g( m+ i- E; U* t
| MCASP_TX_CLKFAIL 2 H7 _0 B; [7 u( J% m
| MCASP_TX_SYNCERROR
: [" T. c; H6 a! m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ `( }0 E/ |$ K5 i& n, d1 R X' ^/ `| MCASP_RX_CLKFAIL
V* i! k% g9 ^8 q! \| MCASP_RX_SYNCERROR
; O. Z+ |8 i3 h& K| MCASP_RX_OVERRUN);
4 }5 L5 O" B: j- Z$ Q" F- S/ `1 N} static void I2SDataTxRxActivate(void) P/ ~/ v. r% n
{8 K8 @+ B/ ^. `, E- J4 i* o
/* Start the clocks */1 J( F* {) \; t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 }# H( Q* H) y5 F( P N& S# N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 w; s. b+ t* o+ oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; {! a% E5 u1 D3 I/ J/ D% }EDMA3_TRIG_MODE_EVENT);
" P! P& t9 K0 D! {' u1 W" W0 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" ~. E# q! D# B4 g6 V- O- VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( A3 p1 S- h" i, c; |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% P6 \' q- h3 z# N [4 F, N \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* B! ~. j- }8 P) R- dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 j6 A m" l( k" i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* E1 u, o I+ Y' V" [. eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, P% o$ r" t& R" ^6 g( S1 ~9 \# g
}
% {; b& C: N+ b: a! P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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