|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, T( e+ `* _' ?4 N0 l3 winput mcasp_ahclkx," R& J V2 \. o( J2 m( [
input mcasp_aclkx,
1 q! N) t# x- p( sinput axr0,4 \6 ?! \$ m/ D3 m! v
0 }. f+ ]" l5 B+ d: z8 \output mcasp_afsr,
8 [" W, d' N2 c% s: h) Moutput mcasp_ahclkr,: F. F7 x; e8 [0 n8 l
output mcasp_aclkr,% ?( |( Z% y3 z, @6 b. H5 \
output axr1,( a6 z! k' A' L% D( ]
assign mcasp_afsr = mcasp_afsx;
1 K2 e1 X$ S' e p: Y! p( `assign mcasp_aclkr = mcasp_aclkx;' A. y8 G! u7 h" U
assign mcasp_ahclkr = mcasp_ahclkx;% X3 x2 U4 x+ a2 v! ?
assign axr1 = axr0; + M% V0 Q6 _ q
& B+ Q/ ^* r/ n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % T" t0 r+ H- F3 o8 Q& G
static void McASPI2SConfigure(void)
" [6 d- k7 A1 ?) U{
1 y2 F+ }1 I: |" u" b* ]' ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( h& @1 I- s6 z' C4 \" a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- u- Q# M+ q* b- I0 K" |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! `# i6 C) S2 l8 x+ }8 N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 B3 r) C6 u W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. {" C/ M5 D0 Z' j9 z( {( `MCASP_RX_MODE_DMA);
' V X+ t+ o. a9 F2 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: G' Q: r1 `$ x; D7 i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" }0 ?$ M" D4 y! G% ^/ k6 Q! aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( ?* X' p+ }" w9 v: R/ k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, E8 |3 r, p4 o( ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 t- o; c( A7 n8 n3 WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" L( m; j1 j2 D% jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, |& {9 t- \ s$ iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / y9 t- v' c! q& ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# u, H4 v$ f6 [8 t* f) ]0x00, 0xFF); /* configure the clock for transmitter */, B9 R6 Z# i$ ^$ M1 M) ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; J8 W' T9 d( w3 \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 J5 Q( c' `$ {+ X; ^+ [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ z% l/ a$ ` B' h; F6 d/ N' q
0x00, 0xFF);- E! M, g6 Y2 T
: c* J& I( H, H1 z, B( E/* Enable synchronization of RX and TX sections */
5 J* F( p1 i) w# vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- r3 v, q2 ?8 w5 |. L* I. k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 b" l; H3 y0 P1 [+ i" Q0 `; y* f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 |3 [. Z& a7 r7 `
** Set the serializers, Currently only one serializer is set as& d6 {4 t& t0 K3 |, Z9 m
** transmitter and one serializer as receiver.8 e- O' ]0 H2 V6 j
*/( i% o7 g7 y5 I: K& k$ ~, N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 F: _' I, L( [7 a2 }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: N$ ]5 y* C6 ]5 z# c x& e** Configure the McASP pins
7 p, j; g. F. \, j. M** Input - Frame Sync, Clock and Serializer Rx: \8 S1 A& ^# X9 c' o! a. c+ a
** Output - Serializer Tx is connected to the input of the codec
' O7 p3 J, W. ?3 l0 c g# E6 B*/
, O1 w. Z5 N: d6 ]0 u) \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ a' j' A, R: ?1 K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 t6 o* E# q+ \% c, h# kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ l% |# N) O- y' U4 b9 @
| MCASP_PIN_ACLKX
/ d; Y/ }5 B9 F$ X, @+ h$ E| MCASP_PIN_AHCLKX
3 T4 I% W8 \% ]) y! _7 [* V; p( Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 s2 d { f7 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ _9 y; x! L# L5 g! u# m j! l| MCASP_TX_CLKFAIL 9 m; _6 [4 X0 ^ z+ S
| MCASP_TX_SYNCERROR
$ {" H+ w" Q) Y; R3 R9 _+ S9 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / Y0 ~1 _6 R: t7 O$ L! \ J
| MCASP_RX_CLKFAIL; j! R! Q8 a" T6 F( U- Y
| MCASP_RX_SYNCERROR , k: r& |: P! J! A- |0 [
| MCASP_RX_OVERRUN);
3 u8 { a3 Y2 X8 @4 ^" s/ u( B} static void I2SDataTxRxActivate(void)3 j. Q: p$ B k2 V& |
{
7 C& `* Z9 C A' F7 @! S/* Start the clocks */
! K; S( Q4 N# [$ _% N6 }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# D( _( V0 L! t) e8 E% E2 Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& E3 x9 i( D3 ~* N, QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" F- @0 y1 }- q$ l) nEDMA3_TRIG_MODE_EVENT);: l, |; o- a* e2 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 u/ X2 {' M' s1 f5 l3 q1 s/ TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" ]. T. C3 i1 K! `* j9 v4 I* nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
u- o/ ~: y+ _2 N/ rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) X+ K3 W2 B2 O2 B, X3 Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 ?+ D. x1 P$ d; L0 `" q" \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 M7 Q4 r9 C5 a3 n+ C9 _3 R* s% H3 z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- R# _' g7 y0 n
}
0 v4 t9 J' C6 A5 d9 r M' N7 Q* c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 }- ?: L* X; X4 H
|