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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ Z6 v0 a( k+ pinput mcasp_ahclkx,5 _1 m N% i+ y0 o
input mcasp_aclkx,6 Z% S3 b1 J5 f4 K+ n2 P
input axr0,$ C( D! F2 P3 _0 r c% \
4 e2 \$ T N3 }" Aoutput mcasp_afsr,. h$ \; m4 w2 f5 o
output mcasp_ahclkr,& P* x2 J y5 P% v
output mcasp_aclkr,
+ o% D5 A$ h1 t* t- J7 C: P1 foutput axr1,
# ~6 l- G$ D( p4 c) ?$ ~ assign mcasp_afsr = mcasp_afsx;
% w- \! i! k$ N+ U* C" x$ [assign mcasp_aclkr = mcasp_aclkx;- @, B0 s5 ?" x# C Y' l
assign mcasp_ahclkr = mcasp_ahclkx;+ ^* F6 u }* A, D
assign axr1 = axr0; 3 O5 u" o" m0 q! V4 p
/ x7 r- U7 b S2 V/ M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 P6 S; \$ G1 j+ F5 s, k
static void McASPI2SConfigure(void)3 ], o. ~% q7 H9 C9 c
{
& \. z5 B* D$ B6 ~$ J9 C/ |McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* f2 E8 U( i" A' {* K9 e1 FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# p+ A% C- S: i6 f5 o8 T: BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; X4 z& }7 A) ]; H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 l+ j9 R& [; n: [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 c( C8 g4 M* `5 t% s- i5 jMCASP_RX_MODE_DMA);& c- ?& [- y( b4 O2 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 a0 T7 B1 | i0 M1 M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% D8 ^ B* H6 M6 e1 M" z) ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 b$ p1 X$ C: s( dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' D4 n- r2 V6 Y, d8 X. |% n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, ?3 T. z, D' w& _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ c# i. h( [1 p* W5 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% _: r. E T( N- a; I4 p; C7 ]( @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 V1 H8 H P, O6 J, D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ f6 F- n& ~. c6 L/ G0 K3 y( [0x00, 0xFF); /* configure the clock for transmitter */# |, |- {* [2 a& f1 b0 p+ D7 H" t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- d9 E4 O5 Z$ D! ]; A' [/ EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; V* _$ T$ M- Y# F( `' ]( n* I7 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- ^. q5 [9 L. ?2 C5 s) H+ h0x00, 0xFF);
% l. q2 U8 u7 c2 Z$ J5 r
5 I! Q# p/ U& D* x/* Enable synchronization of RX and TX sections */ ' w0 ]4 p3 r: X# C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 G H! x! y$ k% t" D2 h, i; Q- X6 \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 g/ R' O v7 [- k% vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 i( I$ a( \1 N. ]& o6 }4 _
** Set the serializers, Currently only one serializer is set as
* k% F# `2 P2 F$ Q# r$ Z2 _** transmitter and one serializer as receiver.
, C# v" x+ R2 C*/3 T \: q( V" ?8 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* ~$ Q P8 S/ E, D" jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* K, o2 C( P, |! c** Configure the McASP pins Z- s2 ~; u; A0 X: f
** Input - Frame Sync, Clock and Serializer Rx: S; ~, N0 S: [( R5 R% N
** Output - Serializer Tx is connected to the input of the codec
% P1 o- I- O4 X% v* G*/ p0 `& E1 }$ G. i1 \1 c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' o; a- G8 W" l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 {" ?7 f/ H! y" g1 N4 ~9 P, G* f" t: FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 w: x+ ?9 u1 |' I r3 \| MCASP_PIN_ACLKX: L! f ^8 k. H
| MCASP_PIN_AHCLKX
: A0 B3 T$ B. Z% s. A' _+ _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 F+ ?2 b) ~, F. N4 FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. j+ `- `. ~) l2 h4 Z6 ]. r| MCASP_TX_CLKFAIL ) J @3 J; Y* O; K2 e
| MCASP_TX_SYNCERROR; w4 ~1 t! _& \: [" V5 p
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& }- ]' E2 W) }" R* X| MCASP_RX_CLKFAIL
! T9 W# o$ A8 P q, [| MCASP_RX_SYNCERROR 2 `3 Y2 }. r9 l
| MCASP_RX_OVERRUN);2 I4 `/ P- q4 v' R7 [7 @
} static void I2SDataTxRxActivate(void)
0 A2 H% y5 o8 w0 Q{
' m& v2 p4 o$ F+ a/* Start the clocks */
0 t6 h8 C0 U9 [: M. F2 X0 g0 ^( IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# s7 U$ B9 R4 I9 y J- r1 TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 i/ y: w3 [2 K: U( F: t' f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ A& `1 X, a: A, r7 S4 A/ [
EDMA3_TRIG_MODE_EVENT);4 r& G. c% ^" n& f. R; w2 s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( v. B4 Y, D5 ]9 \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; _7 j! R7 `/ G- }' d0 v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 S' a1 v7 p4 F& d& x9 L, E/ L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- h4 G, l1 [+ `7 b! |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 |6 q* j7 b. y* D2 ^6 k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- T* B# @4 h& X( t3 dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. ~: m; W9 v6 g) B( [9 [- K4 Z
} 5 r; r5 U! ?! E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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