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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, ^: |! m" C) f; I0 k$ einput mcasp_ahclkx,1 \+ O- d, S$ G" i3 U
input mcasp_aclkx,9 [8 \5 I6 N6 p( |6 N+ M
input axr0,
F5 j3 K: S+ Q1 ?' o2 H0 a
2 E7 c+ g- [) s' loutput mcasp_afsr,
: d9 B) k0 G6 M2 f% o" Soutput mcasp_ahclkr,
9 q! l0 `8 ~; t. qoutput mcasp_aclkr,+ p' J) a' T/ z0 C1 Z3 t2 t
output axr1,
* o+ v5 ^# l+ _1 B assign mcasp_afsr = mcasp_afsx;3 n- g# F0 s$ |& z) d: `: E
assign mcasp_aclkr = mcasp_aclkx;3 L* M. o" F" r0 W
assign mcasp_ahclkr = mcasp_ahclkx;* Q! F2 n) U* F0 D3 y6 C/ w
assign axr1 = axr0;
L/ ]+ O1 o8 x/ Q- ^# A: l" G" r" z7 Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 M; a5 u: u3 t# Istatic void McASPI2SConfigure(void)8 e* j2 T, }; e' M" a& {
{
5 w$ ]# z/ U9 E8 i+ v& NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 Z) f2 {6 A- u1 \6 {4 AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 R% ?6 c- g5 z/ g' \5 Y' UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 S. O7 O/ f+ ^) P$ A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 `" p6 L$ }. z% j: s' ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. t, L5 }4 D5 R/ ?# \5 G& GMCASP_RX_MODE_DMA);
, O$ k+ l# q4 f- L) e) OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- ?- v4 j. U% o, p$ a# W5 Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# R2 [) ]1 G( o# k: c2 t, V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / q% I5 A1 D+ o. m6 [7 G3 {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; I {% d$ ?6 \. O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' e6 e- P/ g& N3 Z- Z# ^ l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 `' q, w. R/ z0 z8 }2 h, pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ g- P% C% n1 W6 r7 H& d# PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 k- {# G, Y5 GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- Y! ^& C% A( z6 G# [0x00, 0xFF); /* configure the clock for transmitter */! u5 |# ?( v" W6 t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 K2 F0 s$ z0 ^ x5 d' S" S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) n2 ]6 i; |3 V" ?, c2 D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. o: l/ q6 y+ d! v5 _" z# i
0x00, 0xFF);
2 h$ [- Q! V8 Q1 y. y
9 Q9 n/ e) d4 p7 X% [; C/* Enable synchronization of RX and TX sections */ 2 Y- S" Z3 @; [2 ~3 x8 ]: @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% A) U5 w" O4 v; ]$ z: v! H+ fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. i3 _' f; }: Z( |' t$ {' \) OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* }" J+ F& ]- h' z: q1 @: s) q5 D** Set the serializers, Currently only one serializer is set as& ^1 u+ K% Q3 }- x! B5 S5 }
** transmitter and one serializer as receiver.! T3 X& ?, A$ n. j- f' n
*/) ^- }7 Q$ ]6 p1 Q& m$ ]* Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 j- |" S# ~# F7 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** s' Y+ ?. L5 E! A3 p
** Configure the McASP pins - G5 {8 Z% }5 q1 P% F6 |1 k: B
** Input - Frame Sync, Clock and Serializer Rx7 J$ ]* M( Z0 n9 N8 Z9 ~
** Output - Serializer Tx is connected to the input of the codec
. @ |1 }* B( ]! u6 _2 k5 L*/1 a% {) }( M* t/ F$ K- ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ a6 w3 K7 n: n! P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 s0 |" E; l' p% x/ ~! ?6 w" tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 b8 n( j8 D( ?| MCASP_PIN_ACLKX0 k3 ~ W+ M) P4 T/ Z. t o) F
| MCASP_PIN_AHCLKX4 g5 B% I/ f$ v8 v( V- T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 i& E3 z: p' x& b: _/ i1 U. zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' S# O% A+ }( |) |7 l
| MCASP_TX_CLKFAIL
5 C) ]( ~& K5 J| MCASP_TX_SYNCERROR0 E5 s6 j/ ]) _1 ^% E" G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! G9 F& C1 @ g* X9 m4 o. x) j, M* B
| MCASP_RX_CLKFAIL6 P& y$ Y% A( x4 U% ]+ h, T4 C; ~
| MCASP_RX_SYNCERROR
$ d: r7 B; ~! [* S1 w; C& t| MCASP_RX_OVERRUN);
/ F7 p3 R# t" A* o8 l$ h0 C0 w5 d7 o} static void I2SDataTxRxActivate(void)
/ G/ p; l* l3 _4 P( z/ F0 u. U{+ ]) @6 D! z/ M+ y, z- E0 j
/* Start the clocks */
0 i9 a" I/ h/ |0 e: M) Y, A# }( KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: O. \9 h J6 G2 d1 }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. Y9 x# ]- {6 l6 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' v, E4 _- ?# Y. y+ P9 E7 t0 W
EDMA3_TRIG_MODE_EVENT);! a: b7 Z- B( w1 ~5 T" E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" t4 G3 q2 S* x$ V- B: UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ \, @5 {* g. Q" S2 X r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 T! l$ U1 q h' \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* V% b) f+ J; E; s0 b; U: L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' S( N3 w) s# |9 E' _# |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" j) c* ]7 l6 o% P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" F, t4 g( S s. L1 _}
* F0 H) O. x' z' O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 W; p w# G' d& l
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