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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- r) ^; T0 m$ F! Rinput mcasp_ahclkx,! {) d2 W7 k9 ~: H2 e% [6 h0 [3 m
input mcasp_aclkx,. G& |5 |; F0 m! ?* l$ r
input axr0,
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output mcasp_afsr,
" X1 r+ }2 O4 qoutput mcasp_ahclkr,
- U4 I! p5 [+ F7 toutput mcasp_aclkr,
! b, N' Z) W& D, ?5 |; Loutput axr1,1 l3 W- C/ s' L4 Q
assign mcasp_afsr = mcasp_afsx;
v/ T! h2 c5 @, R5 u* @assign mcasp_aclkr = mcasp_aclkx;
! x1 ?+ J5 s% N6 R& |4 Fassign mcasp_ahclkr = mcasp_ahclkx;
+ F& L) X# q; `) f n6 x: `) qassign axr1 = axr0;
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& F2 {3 z# f6 L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # w1 W! S# g1 F1 ~
static void McASPI2SConfigure(void)5 M( c% N9 v" t" m
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! i% U: @! F7 g" vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ F* c4 i; a% H3 oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: q. ^9 P& w: B4 M# LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 q" ^# }! T* b* Y- z$ p" L3 xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 o6 z0 C# q, G9 r6 gMCASP_RX_MODE_DMA);, @5 U, r T3 c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( F# C# c6 j; u, t+ _. BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 K; ~# H. l2 I" P/ g: m4 B# RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 S. f& n' W6 L, U1 q! NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- p+ U1 o9 d& ]8 ]/ \$ j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 o6 W; O" {5 ?; ] P- m. q6 XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; n. _6 L! w" i, [1 @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 z d: ], @; i/ K5 J2 i. h7 P, dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ s/ S3 P: @; D1 j4 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 Y* b! E( e- d& k# c$ c0x00, 0xFF); /* configure the clock for transmitter */
# Z, }! C, S j4 u b' u. WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 P v& H; x/ l/ X% h' u, e9 j/ xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " i6 L% W w( r$ I0 L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; l( I, g6 y! \3 e0x00, 0xFF);" F- e" t' @( o- V. [
2 r; n5 F- H. m+ [4 I; i: }3 E/* Enable synchronization of RX and TX sections */ " ^0 h8 k1 b+ @3 J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) j1 N1 `! {: W! a4 E4 h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
T3 Y- z5 R4 l9 Q' Z/ KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) H5 `7 N& r! K6 }: | M7 f. E
** Set the serializers, Currently only one serializer is set as/ E( ]; x2 u# f1 g
** transmitter and one serializer as receiver.
0 D* V: C- N8 j1 s3 ^) {8 |*/
( R' N3 W1 ]! k3 X6 @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* W' {9 k H; H; lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 V) X+ i3 j( A% S- y: j
** Configure the McASP pins
" h2 k9 |6 @3 N$ @** Input - Frame Sync, Clock and Serializer Rx
\' g* i M8 ?( m/ y5 N! _, g** Output - Serializer Tx is connected to the input of the codec
3 A. g/ ]3 \# g5 L! b$ r5 o; a* d3 ?% F*/
7 ]( b1 t. v" \% w, ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% Y7 \( o6 V9 Z; F# p0 XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# S$ T# O' d+ a2 Y# B i- o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# u) }/ R/ K2 J- E4 O1 @7 @
| MCASP_PIN_ACLKX
. z, m# q: P. m' G3 a Y, Z| MCASP_PIN_AHCLKX- m% b- z5 e4 u# ^9 S' a& H6 e& v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! A; v4 p+ O o6 `+ ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR C0 s. X, b* O: h6 l
| MCASP_TX_CLKFAIL
! e S9 V0 J0 T' o/ t5 i| MCASP_TX_SYNCERROR
8 d( c. Q t# x$ r) h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 _# L0 k2 X; O* M" W3 Y# l- u
| MCASP_RX_CLKFAIL% b6 A% ?2 u, L, o' T
| MCASP_RX_SYNCERROR ( j) D" g6 G7 Q/ K* }
| MCASP_RX_OVERRUN);/ x& R. D ?2 _. y$ m4 p. K
} static void I2SDataTxRxActivate(void), y$ e$ x" |; W
{& c9 E; [+ j l( O
/* Start the clocks */
8 a B9 e4 j4 j g2 D' L: @4 n pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* S: y# g* n |! [, s/ z6 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; ]6 F( K; j8 W7 L8 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ r* W' ? F% ZEDMA3_TRIG_MODE_EVENT);" k( Q" Y( J0 O+ F/ e/ B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 N( g1 q$ b( {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 v/ w0 M5 Q/ s. qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( P, u: n( k$ g- I P/ ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& N! X/ q) \ c6 v. g& s# P( U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! Z+ i% G' m. l0 k4 E, B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ e; Z. }* J# t, s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. Q# N- _3 V. U! o! S4 n} 9 J J6 p- Q) F# ~) K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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