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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- S* N" ?, M" o2 k9 k3 `! }" {input mcasp_ahclkx,3 i" e4 ]. ]8 Y, C1 x" a
input mcasp_aclkx,8 i, b$ Q [* W9 a- r2 l
input axr0,
* b5 j0 s+ c1 w2 X' l" z( e4 t6 g: U" N
output mcasp_afsr,
$ A" V ~0 J$ b* o- `. d; Loutput mcasp_ahclkr,; |- X8 y/ ^! k, s1 q
output mcasp_aclkr,! t9 t: r7 c; Y4 D5 y1 q( `
output axr1,1 ^+ z! V, Y' B3 {3 j" j: D8 F
assign mcasp_afsr = mcasp_afsx;
) u& B( H7 J# w& R- U4 Wassign mcasp_aclkr = mcasp_aclkx;
1 ]; F2 m U9 r, _# G8 X9 bassign mcasp_ahclkr = mcasp_ahclkx;
. o; P3 X( Z$ lassign axr1 = axr0;
- ]* i* i9 L3 k$ R/ z K* b g
5 X; ~- m# a. x. ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 z& O) k7 O/ n% S0 K9 M- K
static void McASPI2SConfigure(void)
) M; ]! |. P7 T/ O1 V{, m( }7 ]5 L$ H ?, @/ C* o5 |, O4 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# }' t& y# ?! w; f. {& ]1 j+ F9 m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 w/ w5 \- }7 |& h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ p! N2 s# s7 } _( g$ ~$ }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, W! e5 H- u& D* d. K1 u' D+ h2 p' kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# I, `( U* i& c, b! JMCASP_RX_MODE_DMA);& v' O: a) H$ h" v; x' E$ P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 v) K( @8 |8 V6 y. N" {/ @: J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& l _3 W& }! sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 O2 G3 W9 D9 ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* @ p9 O u j- T& cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # V7 b: J0 @( M( K5 e" ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& }6 z1 I& a0 f. O0 E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* ?2 B, R' K G6 QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
m" O$ i# |8 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 h; m, H, C- N0x00, 0xFF); /* configure the clock for transmitter */1 v. v# ?8 }6 K4 Z; H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ V7 h% G& p& H, ]' A2 |# u4 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 W+ h$ R* [7 i v P, S: q+ o: b7 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 \' q- r1 L* n1 \9 f* u! K5 S
0x00, 0xFF);0 [0 G6 A Z$ a+ ]; r- k5 }& J
. y l2 l) t& s/ c8 x/* Enable synchronization of RX and TX sections */ & k; H, F8 J7 Y: ]- P& P& n* {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( p4 a, K) C( L2 W5 yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; w* q7 j8 n [1 ~$ P% E$ B% }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 p/ m( \ [( ?! n$ |
** Set the serializers, Currently only one serializer is set as
2 {, m$ t2 L5 Z3 N8 C- \. Y** transmitter and one serializer as receiver.
! J4 f6 M& B+ A1 v6 f*/! f0 @3 E+ ^4 x! A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# I9 C' z" ~' y% GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: U1 E8 I( n g6 c** Configure the McASP pins
% I* {! Q/ A N" \1 O/ ^3 ?) Y7 h** Input - Frame Sync, Clock and Serializer Rx3 M% p6 Z) h2 v5 t
** Output - Serializer Tx is connected to the input of the codec 4 E( A: _" @ `& e( N" R& h; \
*/8 b; B g: g8 e) |* `+ T0 n4 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 s+ v0 ~3 W0 c3 [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! Y3 p" `. r9 { i& hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 t8 c/ g; N- q. w8 U8 P5 i2 m7 Z
| MCASP_PIN_ACLKX
' L7 u" n- `" n: ~# t' ^& ~2 z| MCASP_PIN_AHCLKX. F4 [7 y6 y5 i& O" M2 x) b8 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% S9 w4 Q6 h# N3 |% FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- H4 A; R1 y; D- A| MCASP_TX_CLKFAIL
. M$ l/ a* J9 V' f| MCASP_TX_SYNCERROR5 V* a9 n8 A' Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : J% ]: `9 h7 g* j* Y
| MCASP_RX_CLKFAIL3 S$ m5 U+ {9 w1 x( D
| MCASP_RX_SYNCERROR
1 z. a% B8 o" B- L| MCASP_RX_OVERRUN);% a) F3 u- Y* }9 d
} static void I2SDataTxRxActivate(void)) G: b2 M, R4 O! ?
{0 d' x% Y6 R% ?6 A, S
/* Start the clocks */
4 s; J% _7 f1 e' _2 w+ T& o) HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% b6 p, p3 W+ `3 v) w. |- {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( f( t( B% i5 ^, ^! ]! q; M, [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 H) S, F1 z( `, e
EDMA3_TRIG_MODE_EVENT);
" u5 y' F3 f* t# {9 _4 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' ~8 s3 V* C1 J/ s4 k* G( VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 S! ^3 ]8 [' @; e8 n- x K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% p1 J5 v3 X5 n6 G) u' |1 T( |0 @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. f; w8 a2 W6 _% Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 ^/ d0 f1 ~0 L8 \9 Z" W. J* ]/ k7 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 q) d: f- k& J! M) ^4 ~/ s) CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" z$ O! V; J! A1 I$ M7 w, [4 p}
8 V; r0 @4 v) ]9 F% W3 Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & Q) Y/ w D9 s$ T
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