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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- o% g1 h: p! |( Winput mcasp_ahclkx,
! J" d- p4 _4 {8 x8 X7 tinput mcasp_aclkx,
' X' E" T- ?# p, {6 m$ p$ R9 H8 ]input axr0, s7 n% c: X4 N4 |
2 b9 Y& k8 C/ [& q' O6 _) Doutput mcasp_afsr,
( A% ?$ n7 r& V- g# p/ o2 ooutput mcasp_ahclkr,
7 o* L) m1 T( h) b/ O; U$ ?output mcasp_aclkr,
# {# g1 `: t# Goutput axr1,7 \9 [# F+ q( b* u
assign mcasp_afsr = mcasp_afsx;
5 T9 {7 }3 x) N* passign mcasp_aclkr = mcasp_aclkx;: t7 S/ L6 G J- b$ |3 Y6 y
assign mcasp_ahclkr = mcasp_ahclkx;7 f: b z, h' _$ z9 I
assign axr1 = axr0; + z. F: {8 O; q
2 i6 ?1 K4 T' E) O) a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 h% x; y; X8 f8 F9 xstatic void McASPI2SConfigure(void)
* i9 q1 M* q" q9 f( R% m{: a# p$ `& d$ l7 l& \; g# U* K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 g& p3 F2 B4 `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 [% k; J8 Q; U# ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) g# \2 a* R: i' ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 N6 ]6 N$ r5 L0 Y. L# ]0 R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ N/ R; J% [8 l% ?7 A1 J) tMCASP_RX_MODE_DMA);; a3 q& X w5 }$ [/ m5 F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ C8 K: O3 l! S4 L; ^& QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 K: w7 Y Y0 h/ k+ Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" o: d# Z8 ]" j tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 {+ O8 c z. C7 _- i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 F8 V9 f6 s* ?' @7 DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 P# [4 W' |. e/ L& @& ` y6 q3 s7 BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 r" x* H3 Y* E. P8 Q* T( D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, F5 C( C8 W0 H4 m0 Y" s' GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* L$ s6 q/ j7 B+ d/ _
0x00, 0xFF); /* configure the clock for transmitter */
! E+ h6 q5 [7 I5 G* b6 k! ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* b6 H; m, F/ U2 f: j8 x9 uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( s1 i" h, ?: j7 u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; s- x1 t" X- K }* f3 N$ t
0x00, 0xFF);" T# Y8 P0 ]% q7 P0 C4 [
+ r/ n! y, y/ W# A$ }$ G# `" x% e( ?/* Enable synchronization of RX and TX sections */
# t3 S9 J9 Q( n$ ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. Q$ r$ y6 ^7 X9 C- V0 e$ c/ I, fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* s) k7 Z/ l- c: TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& F% x7 }* `9 \# T9 u; a
** Set the serializers, Currently only one serializer is set as5 B5 A x" B4 {& _) v& j
** transmitter and one serializer as receiver.
4 B- O6 G- z9 r*/3 Y4 Z% G6 x: b X2 ?. {! L5 i8 g4 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 j3 l+ [! U" G" u: t- P: c2 x- Y; uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 x' k/ u( L# k* {3 c7 p8 U
** Configure the McASP pins
# k2 w; o. Z: W** Input - Frame Sync, Clock and Serializer Rx
4 u5 o' [: N+ g** Output - Serializer Tx is connected to the input of the codec & E8 o7 b0 X; Z) J& }$ T
*/
- ^6 I p& |8 G: e% m. o1 G6 g. FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ X# f& R1 f- M$ K5 U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" r0 C2 G# e9 Y: x( H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. s% i! P v. }3 S| MCASP_PIN_ACLKX
o$ F: q' D6 b+ {| MCASP_PIN_AHCLKX
5 Y. @' B* ^: r9 R) Y$ || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ N4 v; X M7 A- {8 p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 ^% f! a/ Y" b( L* P+ v. b
| MCASP_TX_CLKFAIL
" D: f) Z; c4 t- s; Z& ]| MCASP_TX_SYNCERROR8 i" d9 b' Q$ E5 A/ k, A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , z6 L) `- P* i8 i) K* T8 ^
| MCASP_RX_CLKFAIL+ \; g v, \6 J8 N z7 d4 P0 C7 i" X
| MCASP_RX_SYNCERROR
6 z& E2 ?% H* P: O| MCASP_RX_OVERRUN);, N- H" H2 A- W, ]5 j
} static void I2SDataTxRxActivate(void)
: y! v# {4 N; V( i( L1 B( _1 L{
" w$ [2 b/ u" j1 g* J% f" a3 J; F/* Start the clocks */
- f& C1 s( b/ \' h2 r* NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 _, A3 J3 @ e' d0 K# ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 C' D6 ~+ W" @9 F# ^6 i/ C8 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 n) g* S& u, ?9 E/ S: h' s
EDMA3_TRIG_MODE_EVENT);. o, ]; r' a0 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; |* S! T0 M, hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# w7 c$ \6 o$ x3 \6 [0 P3 u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 Q! O4 t' M- b, W$ f7 YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# P* P/ K6 ^5 z- K: a2 \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
r4 h3 m% D6 I" HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 w5 `' m; I8 M+ R. d- H0 o: _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( E4 b$ y" P+ R6 ^: f6 Q/ H} 2 R) j3 A. `8 m$ D6 y6 k. j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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