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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* K8 g% I5 [8 |) o. ~/ ^. rinput mcasp_ahclkx,7 H, x. \6 }: t- i
input mcasp_aclkx,
# u! h& Q0 o0 J5 T' }! S1 Linput axr0,
8 H& X& s6 k" c! M7 P m2 T7 X0 v1 s3 J$ Y" k: K7 J- ^& C
output mcasp_afsr,, e$ l; w& ^& n4 I' d
output mcasp_ahclkr,
1 h: Z# u- N0 Y* i$ ]output mcasp_aclkr,
3 o: S- L2 e! Q! i3 Noutput axr1,
. ^7 y7 X/ B3 m, v assign mcasp_afsr = mcasp_afsx;, j+ N; k9 J6 e, W9 m3 o, f
assign mcasp_aclkr = mcasp_aclkx;: Y' [4 ^3 n% o6 s3 Y3 ]$ V3 D
assign mcasp_ahclkr = mcasp_ahclkx;
% j1 S P3 w& M) Passign axr1 = axr0;
- ~8 z8 i) _' n6 E6 Q- f0 W# B8 s4 ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 Y0 k8 `) D* i/ D2 L3 i' C0 Xstatic void McASPI2SConfigure(void)
- q* K& L j$ L9 L. q1 _7 H7 z{
$ r( Q9 H' W6 ^1 I0 n! M3 `McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 R r8 V' @" ]" {$ S) O% ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ M: e% u3 L. n, A G" H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 C% }. k5 @( M4 n" }4 nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 ~! U( N9 y4 U# Q) A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% v; X9 Z; u- J. o# N0 q$ [3 WMCASP_RX_MODE_DMA);
^, b" c5 }# H( z" Z6 y4 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 U3 X9 ]2 w% I, a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 l) D% a5 g; E1 p; h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - O% P/ C3 I+ s* C+ c& o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ Z: Y$ k# t& {9 I5 P, MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 U; a$ F% C4 l3 a7 T; c G; x! X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 U; Y$ S y `( W" w# ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 I/ i0 B, V7 p1 m0 w' sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
U/ P" N9 x0 R; {1 p+ g2 C. ^4 pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 w5 k% p$ U, k6 D2 d5 I- M5 v% `
0x00, 0xFF); /* configure the clock for transmitter */
: k5 c5 @4 \8 ^8 d: MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! f# T3 a# T$ K0 r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
c5 o4 l2 H' y" ^' r2 N" NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ T& N: R7 y$ r
0x00, 0xFF);
9 P( s# `* J8 g- c8 m- P# ]8 @# I9 \ l* s% [4 W
/* Enable synchronization of RX and TX sections */
% v& e: M s1 ^7 P4 o$ V( IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: K. m l' T6 H. b5 zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 ?" n+ j5 b6 j% a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 L9 [* o+ A8 l) [" S1 Q* h
** Set the serializers, Currently only one serializer is set as5 s7 x) T, Y/ ?
** transmitter and one serializer as receiver.
7 w l! y: H1 |) H, O! o( ~# r*/# }0 ` H3 {+ j% h' E: k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ D, a( x( Q3 y0 |) xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# p7 H% [" S6 U& s5 N
** Configure the McASP pins
1 w, M1 R# L k** Input - Frame Sync, Clock and Serializer Rx% z& d0 k: v2 r5 g+ Q! o: `
** Output - Serializer Tx is connected to the input of the codec 0 \' r' v( Y- w. G) n
*/
: X1 z) s0 W! N; l, s4 A9 P- a( UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. ?+ r! }& s5 y1 e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 Z- [5 q5 P" ^: |* Y( _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 c9 D- W: _! F
| MCASP_PIN_ACLKX. }7 {9 @, j. q
| MCASP_PIN_AHCLKX0 V" `( ~& \/ s; Y) w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% F: I/ U4 H( |) O w4 q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 A, g* L. b- o( l1 I
| MCASP_TX_CLKFAIL
. c4 I& x v: E! L| MCASP_TX_SYNCERROR
4 E( D' l& ]7 l- {" u7 D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" I. e$ }; T% g| MCASP_RX_CLKFAIL) X9 Q& s8 T5 z( g' l
| MCASP_RX_SYNCERROR - G* ~( ` a8 o- w# a* P
| MCASP_RX_OVERRUN);
# d5 G5 Q! S% s8 b} static void I2SDataTxRxActivate(void)0 c2 X$ w7 c/ ]/ m% ~, b% ]. p. q
{. F* O r* c; l. G& a
/* Start the clocks */, Z5 I5 ~% X4 c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ \: V7 V9 q" M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% @9 E7 f$ \; p AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ Q* f0 s' J3 d/ N$ ` d1 c
EDMA3_TRIG_MODE_EVENT);$ s4 R0 L# o8 L1 X8 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 \ n! g6 s' {* x+ OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( H3 B( y: j5 B$ O9 A$ Y; ~. F1 y0 fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
a* f$ `( @) ?# jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ l/ O# S/ t& n# Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 u8 ~2 _8 L# z% u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# K5 _3 m; x0 j z H$ x. ]) |6 [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 L6 B& @/ w6 ]9 |
}
D0 K) R2 R1 m; ]6 |( Z' ~9 `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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