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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! V' ]8 s4 j6 U' y4 b6 ]& Vinput mcasp_ahclkx,
% G5 y- a7 s' n0 c, W3 o$ finput mcasp_aclkx,( ?# }* k7 D7 U7 |- `" @
input axr0,$ Q2 q' {& I+ h6 l. u' u _
% L/ k* w9 {: _4 L8 ~" A* {0 Boutput mcasp_afsr,
! p$ u* _! Y4 f7 K& c3 Poutput mcasp_ahclkr,
4 s3 v" p" Q z$ f5 _$ Routput mcasp_aclkr,
8 c- g2 R/ c- i9 Z/ F$ E5 _, ?output axr1,+ z+ A8 K& o6 A1 S6 ]7 s% M2 K
assign mcasp_afsr = mcasp_afsx;' {2 j+ ~( T, `* D
assign mcasp_aclkr = mcasp_aclkx;
$ i, a& e) |8 P8 tassign mcasp_ahclkr = mcasp_ahclkx;& O8 W3 x# i9 e8 B" N8 k
assign axr1 = axr0;
% ]( C7 ^! V# }/ v, [7 [$ ]6 \& u8 `+ ] y6 \: j+ o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ D2 ~5 \7 P1 s8 L) D2 G# y* Y
static void McASPI2SConfigure(void)
* b. T+ V ~- L0 Y' i# A{5 R2 H8 F* b, h7 t: K" F5 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& S$ J3 `" P* }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 j' W% `8 z! {- z7 h) Q% B4 L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! N/ N0 h9 ^- S; V3 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 `5 R$ F& e/ |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& N5 s1 F- g; M$ W* n. k' W; aMCASP_RX_MODE_DMA);
* ?4 @1 w7 {1 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 x5 _3 {( }+ x w$ G9 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 m5 I8 p. T7 A7 N; AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( A; k: } f0 s( |- m% y' r) u! mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) b& g. U9 H( C% k& ~ O2 n% Q2 @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 }% o3 S# s V, X$ R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) W! l8 j y" D# K8 C/ p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 F/ G8 o3 l- p3 B7 f8 P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 k0 F7 ]1 ^( V& O3 f; S! q$ F, R3 dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 } e" }2 N) Q6 ~5 G$ P& H
0x00, 0xFF); /* configure the clock for transmitter */
2 W0 G- }! _4 p% b4 _& M" ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 o( a' Y: B( V% V' JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 w" M" U: r+ H" x6 x8 RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% ]# n/ m) a c" R8 k% V/ a0x00, 0xFF);
! ?7 @0 F$ u$ q& v S/ B1 u/ e' d! |8 N
/* Enable synchronization of RX and TX sections */ . m1 w- O5 t* f/ h- c' o$ A% S% A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// O" H/ X. B7 \/ E* ~* N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- H+ J& r% G! x7 RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; g% F1 a1 y) i& `
** Set the serializers, Currently only one serializer is set as
: P! p! g3 _+ G** transmitter and one serializer as receiver.
5 x5 [. {1 M4 q/ W) D*/
$ G/ w( p4 t/ [/ E$ V3 i/ `& iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 ?4 l% {( x2 A2 H4 ~( ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" K4 S- B' Z6 a1 q( O. D** Configure the McASP pins 6 a3 G( }# C: b1 Q! H
** Input - Frame Sync, Clock and Serializer Rx
5 r- {% ?/ Q: |* ^5 C. N** Output - Serializer Tx is connected to the input of the codec - I; M9 b u* H& n: K$ e. p
*/: u6 Z/ U8 Q J; b, f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 u; `" f/ H6 q1 v: E$ EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% a1 O. v; j( M/ f1 c' U9 FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* s4 G5 h6 O+ {' k9 _4 n| MCASP_PIN_ACLKX9 i# T7 L( [* @; H* j
| MCASP_PIN_AHCLKX3 T( Q2 d9 A: s" K( L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ c u7 @6 J: J: X! ]3 BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 ~6 b/ o* B4 @" {| MCASP_TX_CLKFAIL
) Z7 h4 ~3 o$ L% C- J6 J| MCASP_TX_SYNCERROR
8 Y# s( ]& v& n: T8 h6 |! K0 h# W7 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 U' S. u0 q/ k% ]( F. c| MCASP_RX_CLKFAIL
2 o3 \' O s' T6 w| MCASP_RX_SYNCERROR
+ w8 A8 F& l% O1 ~| MCASP_RX_OVERRUN);- g; O/ T5 Z! \
} static void I2SDataTxRxActivate(void)# ^8 n: ^# y& z; g S0 v9 l6 l
{
8 \- T! H7 y! j/* Start the clocks */% i8 N! m N- a2 M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 |1 T9 ^( N. X3 `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 Q9 Q9 Y/ T* EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
g# U, v- d; ?) g1 [1 L6 `' Z$ \EDMA3_TRIG_MODE_EVENT);
' Z+ K7 O0 o0 m& i, C# K. p' {: CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, n) T$ y9 a2 }' l1 QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) n, R+ Z9 W1 l* D5 i! X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); }& }/ |# n3 t1 [ i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- k9 R% O$ a! W1 Q; pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* \7 c" M ]- k' o( n }' _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 A2 D1 H5 i/ B, w6 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; e5 J1 @. w) x' r
}
K c$ t9 n, b5 i, m! p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 R. k7 s8 _5 d( v
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