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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 m2 `. D7 N6 A8 B1 V9 D1 y5 E/ O7 K9 j+ H
input mcasp_ahclkx,: C5 @- R0 A7 q& P: L
input mcasp_aclkx,
; t& `" j' Q/ J2 jinput axr0,' @3 c$ K& P/ g7 W* G" H" v, r
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output mcasp_afsr,
; l* {+ z& ]3 {; J! i. xoutput mcasp_ahclkr,% r' T+ A: p i0 I; T
output mcasp_aclkr,+ F6 S$ g9 h( E5 H+ d( c$ ]8 I, h
output axr1,
" v. B t$ j% t7 L5 h assign mcasp_afsr = mcasp_afsx;4 M/ X1 c! d, {; H7 ]; R6 H9 D. ^
assign mcasp_aclkr = mcasp_aclkx;, b: w# E9 u& b) v: x$ {0 Y
assign mcasp_ahclkr = mcasp_ahclkx;/ Z) t/ O- A: ~+ b" N" Y0 m
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 D4 l7 p" ~- N+ a
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 p9 H% l& B$ w# kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% T* o# y1 M. }4 I/ w* j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: V5 l/ o: k& n2 Q/ [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; ^4 z5 Y C ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: x, u, G$ x; g! c8 f s# p4 a- `MCASP_RX_MODE_DMA);
# f6 q [8 i% }5 Q4 j6 WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ O, Q! ^1 D0 _% i9 K& N/ p2 TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. e/ t( E% s6 a$ ]* E( [/ Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 k0 z! G$ W) }$ F9 `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 K) l% B1 G$ [: v4 |: SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 C( |2 C& @2 D) W. NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ u( @; D& p% V; t' @7 @, k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 Z3 e7 p9 |+ ^ Y# @6 uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 W" [' y8 L9 W! |. D0 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 f4 g3 \; U7 b4 q0x00, 0xFF); /* configure the clock for transmitter */3 E6 m8 m, B7 v6 w) _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* J5 s$ z4 G# o- B. T" L( Q! d! V _+ w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 e0 J& Z0 P8 U& l& d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' x. h' z( d2 }; B, t$ M. H
0x00, 0xFF);! p7 ^; r5 Z! x: l* c
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/* Enable synchronization of RX and TX sections */ ' r6 F+ |9 L; }5 d/ e3 N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ @; o0 C/ D) ]8 I+ {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- [6 K. z v: |1 T, D1 l+ z) q% b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# \! Z3 J$ [5 Q! `
** Set the serializers, Currently only one serializer is set as7 v* q" t% m) ]( u( S7 a. q% n# ~8 X
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 w# j/ @6 ?* p! B" H1 q" RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 w- b# v6 L. k7 N3 o** Configure the McASP pins ) L: m9 w# X1 R6 l- P
** Input - Frame Sync, Clock and Serializer Rx
: E$ v( A- O7 o9 M** Output - Serializer Tx is connected to the input of the codec 4 ?' T: D" n/ z; |; B3 A" {3 D$ U; k
*/
0 }$ F- K U6 o# l2 r% R9 EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. p7 X0 h* k. i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 P, ?8 e! ~5 jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX h0 D& C6 g z8 i, T* K9 I
| MCASP_PIN_ACLKX
4 R6 C1 s) t" Q4 [& G, Z| MCASP_PIN_AHCLKX
# s. `' L! s x* P) ]( f- f: S& Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& F2 K& O) z* z0 i- fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " A6 F- `9 U, G! E; T4 v4 |3 p
| MCASP_TX_CLKFAIL
% \ ]' X+ a# i1 Y* A2 m| MCASP_TX_SYNCERROR
6 |" _: l* |- y. ?* r8 T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' l& w; K/ X2 U! y# p# u
| MCASP_RX_CLKFAIL5 ?$ I5 k0 q0 M: j- H9 v
| MCASP_RX_SYNCERROR
. T: ?/ J% \5 w0 h7 T9 c# A| MCASP_RX_OVERRUN);% ^+ b# c, H# L' ?& X! y* @9 d) V3 e
} static void I2SDataTxRxActivate(void)
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/* Start the clocks *// ]3 B- `$ d5 P+ M* B0 K1 L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 ]2 e/ L' z3 _$ cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 c, n4 y; F9 p0 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 ^8 d! x, e0 A4 c! Q
EDMA3_TRIG_MODE_EVENT);
" E* j) Y+ U1 N& O# H L! b4 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % M/ z& ~) A4 L$ |* D9 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 R5 I% m" h* d5 _% nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ G* |7 f2 w: R) j- FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 Z2 Q* a/ m, ?6 ~ s' ]$ Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, `3 l4 ^5 k* fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! G- d! s/ l* J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); D O7 f7 z* J. ^2 L( G X/ i" |
}
2 M$ u' @/ e J3 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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