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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* D3 W* t2 j0 yinput mcasp_ahclkx,
: B1 U) b) Z( [3 |' Ninput mcasp_aclkx,$ N3 k: a) p1 U* k/ q' s! `
input axr0,
# J" m; T$ `7 H" ]) W
- z0 n) Q0 l+ uoutput mcasp_afsr,$ j0 l# ~5 I) l: m4 F; D6 V1 b
output mcasp_ahclkr,' r0 o/ p/ G/ k
output mcasp_aclkr,( _& ]8 `; f3 {+ K7 _
output axr1,6 u: C" E0 A4 v. y8 a0 p& p
assign mcasp_afsr = mcasp_afsx;
3 ?% @4 T' w' L$ p" b" Fassign mcasp_aclkr = mcasp_aclkx;
0 a o8 u' `- T+ A# F" Sassign mcasp_ahclkr = mcasp_ahclkx;
2 n' ]( s( |% n/ W2 jassign axr1 = axr0; , w# m0 Y- x. s$ g7 y
5 k( k; U: G, m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. a; l- `1 L0 o o. Lstatic void McASPI2SConfigure(void)/ M9 F! I$ ~- v6 p" M! }6 v" e+ ^
{
0 J, p- N- j7 x J8 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ v# E3 S5 _1 B1 F- o$ m0 s7 W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* E0 _* V7 q' q: |% dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( ~7 I5 ]; N% W. S4 FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ F7 i. g2 G& [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ i# p) o- ~7 B" iMCASP_RX_MODE_DMA); Y1 V! S' _9 R; O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 K+ N7 j) V% ]0 g+ gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, H7 C6 ]+ s* ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 F$ c* A' [/ K0 [+ O V2 C9 SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" u$ V- v& I- z; ~$ \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! r% |( C- C; n, M) Q6 H# u mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: E$ a5 k2 p, i+ _/ q) U( P3 a. `) s* BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* q# H+ z, U' U6 Y) y; j, N* \1 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % q4 J' y' Y, s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 G8 t8 A. H8 G4 l4 U# `
0x00, 0xFF); /* configure the clock for transmitter */8 i8 v& s5 w3 b( [. @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: Z9 F: f# {7 F% c+ \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) J$ Z2 u u3 E) `: dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 O* @- J5 y; e5 `& l0x00, 0xFF);' h: i3 l& o+ k
5 n. N/ V3 B4 U* z0 C2 H: X: D
/* Enable synchronization of RX and TX sections */
1 t' H+ D9 F: j! e' l7 hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 K( G' f0 s! _1 F# J) R/ {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! z: u7 B& F: s& x# bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' u( S) i. l5 ]* O3 [5 f
** Set the serializers, Currently only one serializer is set as
! @7 Y4 Y- k- ]* ~$ h3 M** transmitter and one serializer as receiver.
( g" R; E! W: M. k*/
, c2 ^8 G# q, _% _7 c1 F5 F& \+ kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ s0 o% X5 e6 G( a7 t- q, }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: y, c1 N6 O+ ^9 o# ~7 d+ j( u' O** Configure the McASP pins
- c- K+ N7 W- e! i# N: A7 j( J** Input - Frame Sync, Clock and Serializer Rx# Q! Q! o1 F5 c; ?8 ~8 z/ O
** Output - Serializer Tx is connected to the input of the codec + n! k1 E a" s+ e" T* e
*/9 G0 U. e0 F1 L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 x. U* ]" L9 z |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ G0 i2 n* r8 N- h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* N9 m1 w3 p1 d/ K' s7 E
| MCASP_PIN_ACLKX B4 b! i! i' }% n( L g
| MCASP_PIN_AHCLKX
7 v/ ~; e8 l$ W6 t& w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 n' |" j7 t; M4 y+ s% zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ D0 W7 S- u n+ Z8 V+ U| MCASP_TX_CLKFAIL
4 U" b. w" e0 T9 B5 i7 f| MCASP_TX_SYNCERROR
! q/ h' {2 _# N! \$ t/ || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ F) k& q; J. `8 G _: [/ p| MCASP_RX_CLKFAIL
& ^8 d6 q; }" }/ P8 S| MCASP_RX_SYNCERROR ' Y2 s y0 \. m: C4 V- A
| MCASP_RX_OVERRUN);
5 o1 [8 S( o# q% X; v6 \} static void I2SDataTxRxActivate(void)/ e+ d* N( r5 W8 y- Y6 i5 E: Z+ [
{
+ S9 w5 u# v4 Z' S6 R1 C3 p( R( B/* Start the clocks */5 j1 U5 X2 R4 p+ Y" r/ H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 [2 I' w0 e/ ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; e9 O3 Y: p1 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) N u+ @1 q, a! ]: U
EDMA3_TRIG_MODE_EVENT);
% n' l( U% e/ O0 ]. N8 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 O1 V9 L! L- q: C( [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" ]5 h F2 Y" Y. m9 b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& I6 g; T4 b5 ^, K5 W1 {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 _8 Q. v6 [- {9 |5 e. lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 G& z* w1 s& S3 |% L9 q1 F; _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( v3 h0 W5 p' U# L Y' i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, m4 c; S& E5 \2 g}
- h" R% l% y& I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( G% z# T# q' [1 d( x
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