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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- {# u+ `1 _" u) [3 @6 Xinput mcasp_ahclkx,, {/ P* j; a5 e9 R9 @9 S; S
input mcasp_aclkx,7 ^3 ~& ]/ N% N) `4 g) @0 T% N' y+ @9 K
input axr0,) ^; j* ~2 G" r7 Q
: I8 e9 F9 z0 ~" s; Q5 ]
output mcasp_afsr,
) m1 N+ d: d; C0 D* ]+ a6 K7 m5 aoutput mcasp_ahclkr,
" D. i; g1 g8 A V2 \output mcasp_aclkr,: ?; I! @$ _* |
output axr1,# `# |7 D) U; d4 I
assign mcasp_afsr = mcasp_afsx;
# a. y C4 ]5 ~* E. l: R! J4 lassign mcasp_aclkr = mcasp_aclkx;
. a S: x$ D% v/ R6 Bassign mcasp_ahclkr = mcasp_ahclkx;
6 {" m! Q0 n$ y L/ Wassign axr1 = axr0;
. n: w$ p0 H5 L" J5 C0 L0 b( g) X" ]/ M' H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 c7 a0 O' b T' o& P# O$ P
static void McASPI2SConfigure(void)
. t4 d s+ Q; w1 l7 @{
7 \7 e/ `% i( E4 D! DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 t" X" K9 r5 A2 V1 q" oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
a) F1 G9 M. W0 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 K5 J% n1 V8 z2 V! R3 |1 Z# D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ D' O) ]8 x+ L: I ?& h# RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* U) ]' F; ]8 @+ e9 N9 l- A$ WMCASP_RX_MODE_DMA);
, F: d% L; B4 @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( c( \3 \( \6 p1 ]6 mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 E. R, i9 J9 s: y7 jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 F6 C2 Z7 R6 ]$ Y7 K- D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; F* b! L4 J6 p/ fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , J/ k7 n( ]8 i0 x6 H3 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! r' ]1 ^: j/ s/ I5 H: vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ D5 a# Q, x# m+ tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 f$ \) o$ g8 `' ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, {2 M, m8 q6 @9 R
0x00, 0xFF); /* configure the clock for transmitter */
, b# x0 Z4 c3 \' T2 C: u- OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: X1 }- v- Z9 W; k q4 v; QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 X6 \6 k! T4 m2 f) i) l, xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ \5 P( T) m' h! _ \
0x00, 0xFF);' o; r$ Q+ @: d. @' W6 g" A( L' d4 `
# v' h7 r# b" S4 f9 h/* Enable synchronization of RX and TX sections */
) s: G$ B: z& x; C# TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 P: X$ B5 n: d3 D3 Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); }0 }- H7 r+ g6 b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' }" G$ @; c& ^" H$ {
** Set the serializers, Currently only one serializer is set as
6 W8 y: J4 h& C4 W. D** transmitter and one serializer as receiver.
, ]: Y3 U2 b! ^* ~*/1 ? _- A& ^! o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' N7 }: _& r2 D0 y+ ^6 |7 E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 X8 W1 @9 |5 Z7 g5 H0 G* `6 X; Y
** Configure the McASP pins
0 P8 R$ c V1 R6 K0 g% D: @** Input - Frame Sync, Clock and Serializer Rx! h# \6 Y& q+ n# t% n: [5 v
** Output - Serializer Tx is connected to the input of the codec # t; ?# E$ R0 f
*/( X' Z: r6 _: E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' `0 d1 G. [. ^4 ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; R O7 Q, x; Y$ E, l: x( ~' K: \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 i6 {( u$ q: \# ?3 R
| MCASP_PIN_ACLKX
, m* u* i' c7 P, M" v. Q| MCASP_PIN_AHCLKX* J3 y1 I. f* t# T; f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 h6 P4 p1 e3 ]. @, PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
_2 z o0 N4 x% Z7 _+ E| MCASP_TX_CLKFAIL 5 o5 h A* A( N, @- C) F7 ^
| MCASP_TX_SYNCERROR
) m4 d8 f1 X+ r! \: W1 l, S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , [* |" E J* ?+ E) ?2 ^1 |
| MCASP_RX_CLKFAIL
7 ~( m; Z: t" i: K2 Q) M| MCASP_RX_SYNCERROR
* r _+ |" f6 T| MCASP_RX_OVERRUN);
$ c' e9 F& V: I} static void I2SDataTxRxActivate(void)
3 l* T$ p9 E6 Z9 P{) M" f% y3 ~ g5 V' I# o W, b3 b/ D1 J2 M
/* Start the clocks */* \0 x' _ b8 d% z. \$ M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, {% p$ d: y$ }! p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, M7 s9 J! k& w% G! e% oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ {- R8 Z6 G1 O* G
EDMA3_TRIG_MODE_EVENT);0 X, S+ L9 A* y0 s9 |/ U) d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( y, T7 g# U: R. w4 Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 P% `- z' k% p/ w& v2 rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! p' F) r+ b5 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; N, o! b2 ?% z& H) Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& f: j3 y/ I7 c4 |. P+ k* G# M0 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; b' Y" H6 a4 aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* F+ V6 O7 [1 H, }: s2 \ P
}
- l2 W9 m5 ]$ `* ^1 z5 H1 T0 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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