MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
9 N2 n1 a4 M* o* u$ M: Binput mcasp_aclkx,
- b+ |- T$ V; t0 y: P, L' ainput axr0,

output mcasp_afsr,
3 Q# K: M) B$ t+ t" Uoutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
8 K) k$ z: K& |) `% Q

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

$ Q8 b0 X8 b0 D5 t1 ]/ h
8 K* N6 }% `; b- p6 ~% a

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

: ?/ T2 h) K( |; Q" X8 E

static void McASPI2SConfigure(void)
7 }$ Y% m; ~. \3 ~& v{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 g' p. H* c% Q3 _0 m/ wMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
9 F; P1 S+ j, M% z) r& n9 z% iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
5 K5 O6 @" A  Y' C+ C5 W. \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ c% z) d7 N6 M* y' pMCASP_RX_MODE_DMA);
; x: _& l$ T- SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 B$ c8 ?  X  v8 w2 ~$ SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
5 t( k1 j1 o* J4 z* _$ ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. G' ?: {% i" W( Y  T) F& d" `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
$ \# s( P9 \4 z* j1 z4 M8 z: Q
/* Enable synchronization of RX and TX sections */
( q3 O5 V' d* v3 A& m0 [  z9 qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ @5 ]% W' Q) y) T) c2 o# wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
# ~# @8 A; m6 p. q: Q: m! O2 h** Set the serializers, Currently only one serializer is set as
/ G* n, w6 V& C# c: ?0 W; X0 h** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& e) R9 _! B* l- u# uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
( P2 h0 G. s0 G( }# F** Input - Frame Sync, Clock and Serializer Rx
* b/ S- O4 ?: O0 ^+ W8 ~5 F( t4 r** Output - Serializer Tx is connected to the input of the codec
- U4 q# N: h7 Q5 N7 N*/
, j0 U$ i+ @5 \# S: hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
4 D* c0 t/ E+ || MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
. Y: v$ \+ S1 ^. H* SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. r! U& m- i: f| MCASP_TX_CLKFAIL
/ W& k- l4 O' J  m$ u1 q| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
6 _7 W& W( J, Z) }, `; a8 G| MCASP_RX_SYNCERROR
) J+ f# i- a0 @6 j| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
4 C/ |6 }# R; K1 I- v{
/* Start the clocks */
9 P. z$ {+ N: e7 ]. g$ zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- Y' X2 F* g4 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
: C+ L/ Y; A& K3 d2 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
' [/ }* W, d5 Y0 V0 W" v5 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* I6 T/ z3 e9 P; R* \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
1 {& d9 \. U, b: V( Q' q6 Z9 Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

2 }* _1 j) Y5 s( d/ ]% }

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.