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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 `6 f- x3 d& e+ ~$ Rinput mcasp_ahclkx,( g' L6 h; @/ E# v# w7 _, A
input mcasp_aclkx,
+ Q# \* B6 P1 C5 |' @# w Uinput axr0,! l* W1 |0 s; m T9 Q+ L/ A
& i1 t7 U$ X+ m1 \output mcasp_afsr,
& K6 Z- V8 r/ r J! y; D# Z9 doutput mcasp_ahclkr,
0 {. z0 Z: y) @. y5 poutput mcasp_aclkr,! Z# L% _# B" |: q% f
output axr1,
% r. [8 @" L: g y' v: g assign mcasp_afsr = mcasp_afsx;4 X: Y8 n- c3 r* ` q
assign mcasp_aclkr = mcasp_aclkx;
2 k! E+ h# a( _( [assign mcasp_ahclkr = mcasp_ahclkx;! x+ o/ ~1 V5 T! K ?8 ^2 A
assign axr1 = axr0; 1 q6 e- E5 J X, q6 w
3 V: a8 {3 H2 w9 D0 [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, y. {( p2 x/ f! k- o& Kstatic void McASPI2SConfigure(void)3 j# N( p4 E3 y5 q
{
9 ?' W* B" d) Y0 z7 `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 \4 W5 o8 {9 rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" T" x8 N0 e+ X. n7 C9 t$ M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 {9 I( t" U7 c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 t9 }- `7 w0 g! k eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 H% [9 j6 c. t3 p4 cMCASP_RX_MODE_DMA);1 w% q) `* X) \% K6 i6 A6 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' [6 w) z6 `. e: l7 v! |$ l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 i/ h# x+ n K9 x8 e' O/ eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* r$ o/ T- T i2 PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 Y. `0 U$ y" W7 ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - V Z: v; A* H! o$ F" F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 n, Q$ |' z. ?8 I \" I# S# EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ A9 Q# b1 Z* m3 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- p0 @: a) r( r& Z, i" F0 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 z0 j! s; B0 O# d' A% Z) ^0x00, 0xFF); /* configure the clock for transmitter */& x) z9 ~3 ~3 x6 d) u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& M4 Y r5 _7 m1 u- \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # X( V1 `% h$ o1 a+ q4 k) Q, W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) v) o4 U0 u# o; T8 j2 `9 O8 V& Z! c0x00, 0xFF);# [6 g( L: n' A
1 k, g; Y5 v H# e) _# R7 r# B/* Enable synchronization of RX and TX sections */ u6 h0 d3 F) m6 ?6 U. [5 {2 l7 Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; N. \1 l6 ^1 }* `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 o2 c/ M% ~! R1 w& BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 d4 g" U& ?, G
** Set the serializers, Currently only one serializer is set as
) a% ?- V) ~, O" S; E5 X% _1 {5 {2 ^6 n9 H** transmitter and one serializer as receiver.
1 e0 r# e6 g0 ^0 r, y*/5 E7 Q8 L& p7 o7 X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ R: m; W7 W5 S# {- QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 _8 P. A# G7 a** Configure the McASP pins ( ^( ]: u9 F/ a
** Input - Frame Sync, Clock and Serializer Rx" e: d! t( y* N$ {
** Output - Serializer Tx is connected to the input of the codec $ g/ _+ n* ~; V) ?% M* ?
*/0 b: M2 O, B, ^! }/ c7 ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. j. n6 l. v" R' [5 e q. V6 y8 C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 E* U( a! _# N/ @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 \( D# a; C8 T: B/ Y% z! z3 ]
| MCASP_PIN_ACLKX
/ _: u4 j, y0 Z0 C$ Z+ y) ]. f8 V| MCASP_PIN_AHCLKX/ W2 ?& D3 v& j' e, n1 o \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 S1 r, |: N. N7 i* L. i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 @2 i; x9 r7 s6 A! C# \9 V* j: G| MCASP_TX_CLKFAIL . {2 p, u9 }: y% a7 M3 K) ?" R
| MCASP_TX_SYNCERROR" \5 D N2 L4 [% V2 f" \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 L, D$ ?! {. q( ]# I! W| MCASP_RX_CLKFAIL. U9 |3 ]& m8 X; C9 o" u
| MCASP_RX_SYNCERROR
: f- ]( L( X4 p% F; o3 E x| MCASP_RX_OVERRUN);6 h1 @9 { |2 N. r
} static void I2SDataTxRxActivate(void)8 R9 ~; X2 I% n0 |4 ~/ V
{0 T% I( H; z2 S: m5 ]# v0 L
/* Start the clocks */
) k5 }/ `* G! P: t9 }8 C! u) EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ U. H" o+ d+ P$ L! c8 E$ ]% rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// Z( _* u2 n$ o- R$ @( |4 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. K8 \) Y8 g/ A4 S4 {% R& m
EDMA3_TRIG_MODE_EVENT);! {1 U9 ?* W+ v. e/ {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 k; k. T& J3 O, ]( z$ P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! w e* W8 P8 z' h/ WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 `( ^4 V; U5 H* P$ Q- l: a" m) T+ I2 J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 {* W; o5 D" X$ o# x, U* `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! N! J& H. E5 ?+ w% A4 v8 E3 z- y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 C) g$ `* e$ {1 R2 l- s* L {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' d* u" v2 W2 z! I3 \}
, `- Y: w1 F }! s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & t" A3 z1 h( b& l
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