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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& X- b9 J; G) L; s- W6 S4 m8 Iinput mcasp_ahclkx,
( T* \# c( n) J" `! winput mcasp_aclkx,
6 o+ h0 s2 a1 rinput axr0,/ h o2 ]" X6 q) K4 N
# M( q5 e" y0 }9 g3 t) K- c9 ^
output mcasp_afsr,% {, o! W# a, H$ O! G, C6 u
output mcasp_ahclkr,
8 s& Y; s" Y! `0 qoutput mcasp_aclkr,
: V5 J: H2 U/ W1 f0 b0 u# ioutput axr1,
% c" e1 a/ l: `+ ]2 W/ ` assign mcasp_afsr = mcasp_afsx;
7 c L/ f6 X: g/ e% D# N4 Xassign mcasp_aclkr = mcasp_aclkx;
3 H7 ?, \+ \" o! d$ z4 D$ Bassign mcasp_ahclkr = mcasp_ahclkx;8 g( f9 |( |; e. f' ]
assign axr1 = axr0; / c, N6 R* U- X1 H0 E' U s! i
1 C. b( {: N8 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( o" A# s. M+ v9 r4 q1 C. Y$ `
static void McASPI2SConfigure(void)3 H" `5 D) B1 V
{5 g \0 b/ l& C. G: s' J/ _9 V& n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, K @ z" p6 O0 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 j" U) w' f9 m! [( ^* bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 `! a. p& U3 B/ u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// N3 e& ]: @1 r' t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 g% p; f! P: {# ]5 nMCASP_RX_MODE_DMA);
* W; L q- K1 \+ cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 e4 W1 Z8 h2 M! j* `3 G LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, }. `, s$ w" U1 t7 ]) `: }4 [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 z) J7 o' L8 m) q" w7 M8 i& z/ _3 [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, H+ ?! e! m; I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# y3 S7 H! j4 S. B) mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 X8 Q: R! F N9 ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 [. y/ m/ B2 N6 I) I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& r& H& x, b9 {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, @: [, w! h Y
0x00, 0xFF); /* configure the clock for transmitter */! K' V! n- f4 ^3 n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 B- A+ W8 Z+ |$ d) W: g! H* I( \7 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , U a8 D7 \* T9 ]5 f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: A# J: ^' x7 Z6 s+ L( D0x00, 0xFF);
2 I4 `) _1 X0 s, q* g% N
3 C- u" f# N: b% m3 h& Z# K" S2 c/* Enable synchronization of RX and TX sections */ ; L* Q; k, N4 \( H& ?% l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 [5 g* Z8 i6 H$ c4 H! u, m1 sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* f1 z A* i/ ?- r' Z1 K( GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, \5 ^0 z5 p& e; ^2 x: D9 K9 Y. u** Set the serializers, Currently only one serializer is set as" _% ^) Q5 A' L$ P% M% b' m7 C% d
** transmitter and one serializer as receiver.
! i# F% X3 u' x' n1 U, K2 V*/; \8 e0 y/ `7 L- x: H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 Q% ?' v7 f; H" S9 Z7 d& |3 @. AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ O4 R9 H" n. T! q- L0 W+ w9 Y
** Configure the McASP pins W. t% M/ _1 B/ w/ V: O6 `2 a2 z
** Input - Frame Sync, Clock and Serializer Rx
6 j+ f) S5 A, m' C** Output - Serializer Tx is connected to the input of the codec
* @3 a- Y1 d @# y- ]*/8 v, X, V/ F- w: c( B- g& X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" d$ z: I. e, m( Y6 VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# |) { p1 j7 G1 i& i0 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. ?$ }5 Y" g' P| MCASP_PIN_ACLKX
d$ r7 g6 b! r: z0 ]| MCASP_PIN_AHCLKX
2 Y. ]4 V; I3 }# I6 a. C( E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# `( N5 M7 H" QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . b: _% z" |8 ^( r# K$ g# B
| MCASP_TX_CLKFAIL
3 Y' Q+ m( t8 W) o0 I' H! H$ [. w| MCASP_TX_SYNCERROR
; u- X6 j6 K! K1 k' R2 f( B' Z+ o' b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 f" w3 ?* P; D- n5 u" p| MCASP_RX_CLKFAIL9 ~9 S+ ^$ J. Z7 q1 @& g. Y5 m, R3 ]. b
| MCASP_RX_SYNCERROR ; R! [* }0 j& m3 Z. a
| MCASP_RX_OVERRUN);
E( E3 A* u' D; r} static void I2SDataTxRxActivate(void)
( g( W4 @# f4 e5 Y{
3 d8 B2 q X7 L/* Start the clocks */" V5 r# A# F# K0 x/ V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 Q+ z6 Y' g9 R/ ?5 nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# ]* G7 E l; Q+ I& AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 _! Z2 x1 ~1 O. m) F- c2 z8 mEDMA3_TRIG_MODE_EVENT);
& i$ S7 x$ q. k, k! UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) V2 [) D9 Z7 W) p/ s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 r% O5 q0 m6 a5 a y2 X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( H {# R; `4 }* i! I4 f. YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, C1 G9 j5 j1 T3 k1 [2 }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 \( G3 C5 e% D9 `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& n+ s8 I$ F3 Y, ^& Q LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! V% ]/ B# u, N4 @9 y- o}
4 {0 d7 `. o9 s/ U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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