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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ @! G. l- ?: U0 [- |
input mcasp_ahclkx,: l; Y+ z, i6 b1 | D$ r
input mcasp_aclkx,( \7 I+ o3 R* R' v/ `0 f6 G& m, c
input axr0,- o/ J; t: n; k# W! m
( U' w7 `1 n( ~1 y d- x
output mcasp_afsr,: J$ ^- b" X; v" q* P
output mcasp_ahclkr,, ]; C" ]2 n0 e1 H" m- \; x W
output mcasp_aclkr," Y) F1 L4 q% W% K; o0 ^" m
output axr1,1 l& k- N `5 U V9 F* p3 N
assign mcasp_afsr = mcasp_afsx;
! d" d! q& V! Q1 Q( massign mcasp_aclkr = mcasp_aclkx;
( V1 o2 a. n, e3 b5 z3 wassign mcasp_ahclkr = mcasp_ahclkx;
; l6 ?3 U7 W0 yassign axr1 = axr0;
! Z1 ~% M* e0 |9 P
$ e% w: g/ A m! n/ O/ a% b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , a: M7 O8 \ Q. P% P0 Q
static void McASPI2SConfigure(void)1 T/ F8 e" ^- ]: p
{
B ~1 I/ F0 v2 `; vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 u* S; _5 g* A4 C- I: yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 z% W, \1 i8 z+ K& s4 \. `4 J$ MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& z7 J* f3 K6 E: PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* |4 B. K+ q+ j( @% D- c0 ^2 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 f+ i& A6 Z. m
MCASP_RX_MODE_DMA);/ [8 H: e5 [' U- U" _6 F g: }6 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 T" }7 x8 X; u) M. |+ _7 H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 U* M9 B8 } K3 }4 Z2 LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' I9 G% A2 a* V0 [5 Y% ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" h' g/ @4 A9 g5 Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 b4 y$ b6 Z! U1 \" f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, ?; l1 t ]1 o3 F4 r" A% {# k% EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; |9 Z/ G2 I' J) h! S3 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 Y" I' P4 T. P5 JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ \$ d" o5 o+ Y0x00, 0xFF); /* configure the clock for transmitter */
% }- d9 [; ]3 y- KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) h" i! _- b7 U" K- {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% d5 {2 O+ r1 b5 FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 c! M: n. q3 z2 q$ A& W7 H0 l
0x00, 0xFF);7 {% N* c5 x7 E+ k0 G$ k
% D. S- l0 p1 a, O7 J1 m8 }/* Enable synchronization of RX and TX sections */ * \, A. Y7 n, `. v- Z) K0 p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( K2 H" X: P" @% zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 w* n; Q }. {4 Q: HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
r" e" l; g* l( } H) d3 l** Set the serializers, Currently only one serializer is set as
0 g% ?, u/ N1 W1 y- N# f** transmitter and one serializer as receiver.' J1 h/ P$ Y2 _2 ^7 d; [& n
*/
8 O# `& J- G) E) A+ W) fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( `: V- j5 G4 x$ G$ ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( E7 t8 l2 j' t5 d0 o" D7 j r4 D8 F** Configure the McASP pins
- f0 \+ a! P" {7 l** Input - Frame Sync, Clock and Serializer Rx
- D8 R" U9 B' d+ s$ R! ^6 J; W** Output - Serializer Tx is connected to the input of the codec
& S# q/ L l2 z*/
5 i- q; ]& |9 NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. [( S, w: `) X% d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 `4 L8 k: L0 q g2 ^$ bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) {/ R* p; L, h0 \% |
| MCASP_PIN_ACLKX
! ~: C2 L$ c' G5 d| MCASP_PIN_AHCLKX
$ R( d/ G8 V3 N* l- a( F7 C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) f$ O; t( R! S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 K# K4 |# K, O' s0 s- H) `| MCASP_TX_CLKFAIL : i" Q! l* {% V/ e2 P
| MCASP_TX_SYNCERROR8 U9 W* M' @% `0 ]4 `( [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 r1 d7 A. w! {4 ], _| MCASP_RX_CLKFAIL
4 ^! i2 R' k( u. q9 w0 H; i| MCASP_RX_SYNCERROR 7 W5 }5 E7 P/ b1 t A. a
| MCASP_RX_OVERRUN);) U5 |! r1 \& [' v- w+ s
} static void I2SDataTxRxActivate(void)
$ m- L& f5 m0 F& n{
8 z/ I2 v# V, r0 x. h8 C' P, w! X/* Start the clocks */
b% p) G6 {0 F- EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& q; c, U. T8 y, eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 n' V' O# w$ m$ n; i; V2 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% m/ G* t. f% L
EDMA3_TRIG_MODE_EVENT);* _3 J* j+ N" |3 a5 s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* p. [1 f0 ~! ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' A. @. T( W+ x$ z1 k6 M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
~! ~" F. P( NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 P; v" q) ~, p) V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( l* c& Z. O8 o3 I0 j; h5 F: ~$ s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ X9 n: ^# ^0 k: qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) K- W5 M+ a: [& t9 S}
! n _! j2 ^, Q2 n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; D4 J- y; v5 }; j$ I9 ^+ j# M
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