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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; r& {8 z9 g$ ^4 q3 c4 Hinput mcasp_ahclkx,; B- E7 D5 o! L8 Z
input mcasp_aclkx,4 u0 q6 A: a( R" {1 M5 S) _
input axr0,
) q0 R* @8 N# l* s: C3 W; X
9 v# J2 w4 ^- `" f' v0 N/ Toutput mcasp_afsr,+ S/ G$ M- h5 z4 H* t1 l: o+ \
output mcasp_ahclkr,
& @* W5 t2 |, j& N' F, e2 o7 Poutput mcasp_aclkr,
5 |! ]9 u Q, s l( ioutput axr1,8 H/ e7 U8 _' t& ^* b) g
assign mcasp_afsr = mcasp_afsx;6 d t$ y! I7 @" n/ |" Z
assign mcasp_aclkr = mcasp_aclkx;) |0 _; r I# S) }) Q' g9 z
assign mcasp_ahclkr = mcasp_ahclkx;
# S: e+ b6 O% }5 O. m+ s/ P0 Kassign axr1 = axr0;
! B+ u: W$ i8 m9 w( O, M2 F+ a' m% m' T/ o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 `5 y' Z& l1 F: E1 V8 R% g, o
static void McASPI2SConfigure(void); |: p8 l0 i( s6 q1 r5 ^( \" v
{
E. ^9 M. w9 m6 mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' t; R* a }+ q$ q* |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- D6 N# P' }* ]0 l' T% B6 G) W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 m6 P* t% t+ J8 _: }% W. H9 z# y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- s& Z$ q( L0 V9 s V0 P/ lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& B: P3 w9 T- Y% l7 X4 V
MCASP_RX_MODE_DMA);
" N# D' O, Y0 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ {& W8 R6 P# n0 z! f3 A# _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 N/ n/ i9 W* w9 _8 B3 W! G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; }$ T: h& w' H- i( e( x0 ]4 W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& F- |- F! g! g& c; S9 d: |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( K+ }: n) m4 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 L# w! V4 B$ B% J7 j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 b1 B% y, K/ D* YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( b& E6 C7 K6 J& s% w3 E6 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' G$ A0 d8 x9 |/ ?2 b0x00, 0xFF); /* configure the clock for transmitter */
7 n3 u$ I9 E. k6 O2 NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: f! j0 t& w1 u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% U' i2 ]3 e' n3 Y, lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. D# r( ?: S# m9 [; g0x00, 0xFF);
" b [, ~, r# o4 h0 u$ e7 i) Z& f. T
/* Enable synchronization of RX and TX sections */ # y L2 z U2 J V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ N+ p/ e# G. O0 F! _! l! z3 p, I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 Q* z0 a1 {. S- D7 BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, |5 w1 c% e1 M1 [+ J4 D
** Set the serializers, Currently only one serializer is set as
$ \: O; e. R' Q0 y** transmitter and one serializer as receiver.
/ K; k7 d/ J% Y0 X( t5 J*/ k [! E' ~( e0 y4 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ ~+ ~$ a7 m+ c1 j. l4 C2 ~ WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 N& w/ i- e/ X% I) d6 P** Configure the McASP pins
8 q B7 m& g: A% k9 d* t** Input - Frame Sync, Clock and Serializer Rx
% `: F1 G& G8 W* y2 B** Output - Serializer Tx is connected to the input of the codec
6 D3 ]; M/ b9 c; y( J! n0 N*/3 Y. W3 v4 ]8 z" O C* X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. P9 [' N) E+ _6 K/ S1 Y8 b& ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# d* @. z; l$ C( P( CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 g4 n/ O6 s6 t, D4 ~& f
| MCASP_PIN_ACLKX! l6 h1 q" s; `
| MCASP_PIN_AHCLKX/ C% z9 ]. u2 @9 S* b' R) F! v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% b' h2 g8 |" C1 j w+ EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 W$ t0 V7 K2 t0 {| MCASP_TX_CLKFAIL % R3 U: f6 }4 W
| MCASP_TX_SYNCERROR
$ b0 \8 R1 ~- z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ L; ]: y% g. E. o' V
| MCASP_RX_CLKFAIL) u% {4 Q3 K2 D+ X1 Q5 j% T
| MCASP_RX_SYNCERROR 2 v* _: X$ d( i
| MCASP_RX_OVERRUN);) I6 M5 K. d: o, l& V7 Q/ n
} static void I2SDataTxRxActivate(void)
9 s* g' C% X0 c: }6 P{
0 S# ^5 {9 f$ X/* Start the clocks */6 k( {$ H& _! \9 p; @- ^( g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' p. F& P- l9 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. J- `/ ]( \# g- z7 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 r5 O6 j; O$ [! B* o
EDMA3_TRIG_MODE_EVENT);
5 Q' `, s, n0 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 ~" ?1 A6 V+ }, [9 r2 TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 K! `1 N1 \" S; w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: u% s' g2 D* e |. M$ a: ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 Q+ k. E, B3 E" [! Y) ~; X. q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 X h0 ^% w" n+ f% P" R5 C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 O, R6 M& u0 ~ I) t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 c* j' g3 S, y, l
} u! R! r3 Z( J [; y8 K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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