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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ t k# s* E# b7 ]; t S
input mcasp_ahclkx,- _" z5 g4 I( S$ J4 O4 {9 G
input mcasp_aclkx,6 r1 r2 s r; _
input axr0,
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output mcasp_afsr,0 y, f7 Q4 r' g" }7 Z! Q
output mcasp_ahclkr,% G, \0 e' E" E+ E( U' b3 m
output mcasp_aclkr," E# U2 `& ?' ~! B: T
output axr1,
+ b4 w1 a, Y ~" B# H7 Q$ \4 k8 u0 l assign mcasp_afsr = mcasp_afsx;
) N# e2 G5 @7 O4 bassign mcasp_aclkr = mcasp_aclkx;
" E1 D/ ^$ Q1 t- passign mcasp_ahclkr = mcasp_ahclkx;
, ^/ v/ u; U* \; i: ^assign axr1 = axr0;
% ?" a# G* d3 z, M d
8 `$ E; [& P' j9 z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 I2 @ l1 [+ z$ x0 s I
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 k, Z; y3 r5 L3 J' yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, E8 V5 S% l7 I. h+ [% JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); m9 e* o, U4 o3 ^/ Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( k8 H9 y* E+ @5 r P+ y6 e6 C+ v3 P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' L g% `& n6 K3 t wMCASP_RX_MODE_DMA);6 z" C0 \# u; v2 j3 \* J/ G- u, `3 f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% s$ P8 p+ _0 a4 a6 o; K( fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 C! g+ {0 Q' L4 q4 c1 r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 T: y6 l5 [( u# G" `/ ]( u( d) XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% @0 Y3 i3 U* M: o tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ `- S# \/ f9 \. mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ {0 ~$ v1 {2 G) o0 O# K9 ~/ A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 c& g( U- a* ~0 Z, b- I' d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 S0 d9 |7 s. v; _- Z, @) E$ v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' h9 `$ I: d' U; I- d7 n
0x00, 0xFF); /* configure the clock for transmitter */
, E; C* J$ J& R( n# K! `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- T L% @: M- ^# c; C) dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 {4 P4 K2 E: [$ g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 g8 l* L2 P5 x
0x00, 0xFF);
4 ?, v/ L P* v5 e
" z/ [4 \7 S0 n! o/* Enable synchronization of RX and TX sections */ 5 A- `% q4 d- P. r- O1 X: A0 r0 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 n* s1 r& b% {. cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 p7 R* n6 ~" u6 k# Y% s2 a4 a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" S, D: p% k/ T6 ~+ d7 w
** Set the serializers, Currently only one serializer is set as. X: z9 Q/ K. q* s
** transmitter and one serializer as receiver.
/ S: G+ [0 X; V/ [ A*/
: h+ v; H. h6 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! x ~# H v$ C$ N( HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( r# i, w; W* c: \** Configure the McASP pins
4 \# \, f! {" Q% z* c** Input - Frame Sync, Clock and Serializer Rx* f2 w/ J8 R3 X1 N1 A; P2 b2 ]
** Output - Serializer Tx is connected to the input of the codec . j9 R- I, Q9 z
*/( R2 ?- @9 T b* P: ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 t" u! k$ P* `% D) V: E' ^ LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& n* ~8 u& Y) s# T8 c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 \2 `; W- b( ^7 t3 a$ {* {! z
| MCASP_PIN_ACLKX
n' l$ }$ z+ a& j( g| MCASP_PIN_AHCLKX6 S, `$ m* f/ Y5 Y1 J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 x7 _. A, ^( NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ m/ K6 y( H" e$ w* X" || MCASP_TX_CLKFAIL 1 c$ I9 Y: t6 h6 [& |0 b+ ]" S/ ]
| MCASP_TX_SYNCERROR
) q, p- @ {( U% ?; }7 W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ f6 z, W: _& k' b9 Z9 h; H; O| MCASP_RX_CLKFAIL
* O; J y$ @% T+ v& D' v| MCASP_RX_SYNCERROR
# L9 A. @* r* {: p7 U| MCASP_RX_OVERRUN);
3 ?7 b N% t8 P" |& D} static void I2SDataTxRxActivate(void)
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/* Start the clocks */3 @5 G1 O4 W. i* Q1 M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 R; R f4 `- _2 x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 l' o1 l1 [# l% b0 Z2 l* x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. k: O( X2 T ~/ ]3 m$ Y7 p
EDMA3_TRIG_MODE_EVENT);. w/ U3 A( C4 ^$ N' O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! f1 q& D$ R" z p8 G3 i" \6 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" I& P# \ _4 w! h0 b2 }5 I Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. l8 t& y* j' Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 l9 J- Y- y! q9 E' |* L( ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 y8 f( w- T* [' m5 iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. e# A" i a" ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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