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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& d6 }. f4 Y6 g' i( H5 Rinput mcasp_ahclkx,9 h- R0 \( \) U* R/ N
input mcasp_aclkx,1 L$ d# Y2 \9 n: v* V4 o# Q
input axr0,5 Z b8 n- o3 [$ ]
: s! @. M. Q1 w* B; F$ G- ^' eoutput mcasp_afsr,$ b% t0 ~5 ~1 o6 y" I8 O" m% f: [
output mcasp_ahclkr,
* B3 z3 c( W5 Y& N0 `output mcasp_aclkr,. N) M R* Q' f& ?' _ t
output axr1,) u# B$ b3 r8 M1 g, d, u
assign mcasp_afsr = mcasp_afsx;+ _. H! c6 U4 c/ ~
assign mcasp_aclkr = mcasp_aclkx;
- Z, V8 \! N0 yassign mcasp_ahclkr = mcasp_ahclkx;
) G5 C. y# d2 x- h& |* U8 qassign axr1 = axr0;
: o8 w' v* w2 I3 j# ?( G5 ]# c+ @0 q* Q* e3 z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ _$ _! b$ P# @! X# W) K' [: Mstatic void McASPI2SConfigure(void)8 A* i0 [, @+ v; B2 C
{
& r1 U, ]. `1 a6 q- kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: @! L& ~8 q. Z4 t' ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 D4 s9 Q3 s0 ^- j7 `8 eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, @ J d1 O5 z: QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" d2 w, P1 o% h" x# ~7 bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 v$ m3 J% \3 @# Q3 \
MCASP_RX_MODE_DMA);
2 ^; s3 S) O; j( h5 x: Z& @( ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ l: ^. K- `+ C9 x* B/ c. J& @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ b5 s9 w8 c ?& `- ~3 C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % v) g; y' Y7 Q$ j9 q- s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: r0 Q0 m( R4 b8 U( h- r; l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, |, m; o- l# H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 l8 _( S" o c1 C* [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
W" T& c* d- B& |5 n; G) V6 w7 lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; x S( G' V$ a! A0 k pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* m! @. s) m; E# J+ A% w* t0 x( T0x00, 0xFF); /* configure the clock for transmitter */4 A; I; _. a' s- v) @/ x* h( B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 s4 M$ ~& y) C! d' {' W6 GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 z# x5 J c" |" h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. u, x2 h) B/ B5 n
0x00, 0xFF);
( o! K4 v5 {, t1 A0 Q$ N9 J2 X7 j5 z5 N* |3 |( B
/* Enable synchronization of RX and TX sections */
2 m: L6 V# R0 ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; A1 @8 b7 r ], \' P4 [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* o; I- k% c6 Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: N$ e1 x: L1 N& U$ Z/ g
** Set the serializers, Currently only one serializer is set as
( A& V: S1 C1 J: Y! B& c** transmitter and one serializer as receiver.
8 l% q9 e* A8 x+ E- n4 ^/ ]*/
2 }$ i3 }7 u% ~- q7 F MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; l+ u' n9 x+ l f0 e& iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 y9 Y$ a. g* p6 D+ i7 Q** Configure the McASP pins
6 L8 i7 m" |* q: P" u, U4 l** Input - Frame Sync, Clock and Serializer Rx( R% }6 {1 {/ N% m) ?- ^* V+ }
** Output - Serializer Tx is connected to the input of the codec $ N; q7 E4 u/ p3 a0 \. B1 S; d
*/
( L2 E) w W0 o# A( S: R1 tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); B$ j2 L' T9 m5 L2 H1 e& v3 R$ w5 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! i# {0 y9 D5 O" p% s+ w% j: PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 i# f% M6 V9 [; W/ H% L
| MCASP_PIN_ACLKX8 w" C# r6 ~' F0 w1 x
| MCASP_PIN_AHCLKX( i: ^" p! J- b" W) n+ ?: U3 }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 A$ O- x8 |5 p: h* DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 y; s. U8 R# e5 c6 ~| MCASP_TX_CLKFAIL % ?8 \+ Z( ]( t9 w
| MCASP_TX_SYNCERROR
% s% t- S) p/ w# n- i; O; [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' L4 s- D1 i/ L5 W2 W( C
| MCASP_RX_CLKFAIL f8 U# W4 r* ~* e3 r: k
| MCASP_RX_SYNCERROR
, p, k Q/ g+ }, k: U; a9 G| MCASP_RX_OVERRUN);
4 d3 B% i2 J" f( Q} static void I2SDataTxRxActivate(void)9 h! U/ W% P2 B3 Q! ?
{0 e: K. Q* E7 B8 v$ Q
/* Start the clocks */
9 [% N T& D) aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 j0 F9 R+ W5 x: K4 |8 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& ?( D; L- J* w! T; wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' L! U0 e; o1 QEDMA3_TRIG_MODE_EVENT);
5 ]$ i7 I U, q7 u: EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 A3 u) G" T% j; f, _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ T; W5 w6 u8 r" qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: s( U7 ^) |& f* }0 s# q: _3 v* `7 N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ ?2 P; w Z2 G4 I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 S: R& |4 R9 Y4 o1 y/ @) l. YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( B8 q! x% H3 G4 Z$ g. l V7 c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* o7 ^: A9 I* p; E4 j o& S}
2 k) x) K k0 i: G1 i: L2 L% ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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