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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," `+ z' Y% Z0 Y( g6 A2 q2 J
input mcasp_ahclkx,
, _' N0 q7 u6 |; f0 Q4 u% a0 {! g0 linput mcasp_aclkx,
/ v. l2 V) H, ?! `input axr0,
& ~! r9 C, `0 j3 N# D6 _) |! L* r+ J+ C7 h) o
output mcasp_afsr,; ?/ b* s8 I$ w g& P! ~0 Q
output mcasp_ahclkr,' `/ \% m+ [* l& z
output mcasp_aclkr,; X4 Y+ L& C6 ` F: o) W
output axr1,
y. {1 X* L! ~, P0 `/ y, k! k assign mcasp_afsr = mcasp_afsx;3 [# m/ }% `$ A$ B' S7 t0 h m9 ^
assign mcasp_aclkr = mcasp_aclkx;
" P+ r) i9 ^1 g& s0 P; passign mcasp_ahclkr = mcasp_ahclkx;
5 C4 v2 e4 O# Aassign axr1 = axr0;
# s, {7 `+ r) U0 c/ ?% p
1 {. Z1 s0 U" J/ e* `# t/ t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 R: x) T. N. u) b! E% qstatic void McASPI2SConfigure(void)( r K: I# v" \: c' Z$ C
{! B9 S7 i' h# x0 o, e
McASPRxReset(SOC_MCASP_0_CTRL_REGS); n' g/ }7 p4 b6 j+ ^! s5 C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 V4 W( X/ O3 f# |5 ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 h( q2 f7 f9 I/ e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! ?3 k0 _) }: z5 j; a# Y5 J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 q. e9 D; j: a z: c: l L3 }MCASP_RX_MODE_DMA);# \: Y. P/ Q( E6 }& W$ n3 u- t; h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 q) ]7 Y K) L& K. m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 l2 G! ?# ?/ |: @5 d: KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' x9 F4 ]8 p5 n* }. W: q4 z) k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 `2 Q! _& f: ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( t$ _/ m6 e8 b* I' D$ sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, w S3 u$ s* m, |( ]/ GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# g! x6 F0 p- F1 l% S( u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 G" v! s0 B4 ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- R! a" T6 ]" Q0 b, w+ y. Z+ B/ M0x00, 0xFF); /* configure the clock for transmitter */! Y4 w- u5 G9 M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 B* j& P7 J+ U) Y+ ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! r3 h+ L$ e6 X: AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 @6 ?6 J0 d) k. w! C
0x00, 0xFF);1 a$ U, v' u6 C7 h; k; v
; a0 Z+ G# Z( G0 R% R/* Enable synchronization of RX and TX sections */
m. U8 v/ N) q7 e4 k g( ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ k6 r8 Q8 E, V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 q( S, v* k( q0 L! k6 w* X% ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; d1 M! ~' T g- e$ E* W+ u) x
** Set the serializers, Currently only one serializer is set as5 b, u* c8 T2 K
** transmitter and one serializer as receiver.
* ~2 z H+ {- k+ Q*/2 z) R5 s+ G5 l- G; I" U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" _" O9 X, z# u" t* b6 N# }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ y+ r2 E% D# Q** Configure the McASP pins
4 S$ [- k+ Z) e, x O** Input - Frame Sync, Clock and Serializer Rx: h. @8 t; ]- l9 N9 r4 n0 r
** Output - Serializer Tx is connected to the input of the codec
3 q2 O; }' r4 l9 O8 W0 p*/
- T6 Q/ w9 h+ B! i& ] P6 ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& N; G- c6 k" L: N( |# T$ f; v0 a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ E( E4 T0 m2 _2 [0 L$ B( O- rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 A+ }3 ^7 L3 v/ `; J1 H
| MCASP_PIN_ACLKX
( d5 n5 N. O( D2 A2 |- D| MCASP_PIN_AHCLKX0 [& P; ^/ \; L5 o. r3 |3 \, `" R" m) V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 a# S: C8 S6 W* y1 r& N/ r9 B6 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) E7 K* h& g$ r6 h$ E" r$ Z/ Q| MCASP_TX_CLKFAIL
" P' f' w$ B8 S" R* Y6 t ^7 E| MCASP_TX_SYNCERROR
- w$ r* e# M2 q+ }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# e: I0 K5 s5 _$ l* E| MCASP_RX_CLKFAIL
8 ?0 K8 w) C0 P4 f| MCASP_RX_SYNCERROR
& _" Q* W0 x9 l| MCASP_RX_OVERRUN);
- r. A8 O) o" r- x. m$ _} static void I2SDataTxRxActivate(void)
/ t- W6 c9 i( Y9 ?3 K{
' }( C3 Y- Q' c2 ]4 y X/* Start the clocks */
3 k9 k# a0 Q! E8 f5 ?" V+ KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% I1 a# q& G* O: e* z6 \, S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( j2 @% k0 d4 A" ?9 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 P0 m% e* H4 j6 O8 L% h6 G& g& c4 B% Y
EDMA3_TRIG_MODE_EVENT);- d. T3 N" e- F' Q- X5 V: ?; Y, ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% ]7 x' O" ~/ w* A: d/ aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 N" I3 a4 `- SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' M. S7 l* _: {1 x" hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 b' J0 P; s- D3 b! j$ v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. D* j8 n" M0 h! _1 a0 n2 ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) l- g7 n$ O! q" k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ D& I! f" n- @6 a1 r6 V
}
; B* b; d! S7 e5 G! S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 ]9 U {; {$ U: `7 ?, Q: U! N3 X
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