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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ o3 W% n# T, h+ B/ O9 f& O7 a2 qinput mcasp_ahclkx,) |/ x2 d- p! i. p
input mcasp_aclkx,& a. B" M ~- V3 z: h
input axr0,, S6 x! k: C7 s" e* X
/ g; S7 Z3 b: J7 U( Ooutput mcasp_afsr,9 b$ r6 s4 i! T
output mcasp_ahclkr,
" f/ x+ z }" x! z9 Y- b" ooutput mcasp_aclkr,
+ `5 A( K* S+ y% a, p2 b" G3 `output axr1,
% o6 B6 |4 r: w4 c. r. n4 G1 ^ assign mcasp_afsr = mcasp_afsx;4 U3 g5 M3 N5 V0 b/ c# e6 s
assign mcasp_aclkr = mcasp_aclkx;
7 |: A q& ^& n! D. f# T4 D# B8 e/ u) m! ~* lassign mcasp_ahclkr = mcasp_ahclkx;
' s9 @2 n6 c- s; g2 w) s/ S0 R/ T/ Lassign axr1 = axr0; . r" j% p+ c; T
: j8 z# Y0 P" f3 y' P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % x* W4 S- R! Y" x6 h) V X
static void McASPI2SConfigure(void)
' A0 j2 ~7 ~; R' E{
8 u0 D! j- I n" B$ ~# |0 g1 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 H7 H7 b# ~' q% M8 }% EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- a$ E" `3 p& n$ J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: C4 h$ G# x) G* H2 `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// F' }+ N" o% A. W9 \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ K$ D, @0 _1 }2 D* b s
MCASP_RX_MODE_DMA);+ L8 g8 G$ o. t( e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. h0 Z J- X- T/ F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' k7 S2 }7 ] n% T% U* s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 g) d: l% T F! I |/ l, y3 w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ ~4 |- \) l' x. M; J4 d0 L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " {* H# A4 E8 m; W$ c( w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% _) R5 S5 }& b" T7 ^% n, f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 v) t5 i5 k3 I3 ?# z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" F6 [" s: `" i2 ]. k3 JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) \ N1 _3 X/ ~- l$ B# s6 |
0x00, 0xFF); /* configure the clock for transmitter */' d. a, l' u' z! `! |7 H9 e& J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. H7 v: v& c, z1 K# n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* e) f8 _: m+ Z4 F9 t1 dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 H/ e Y4 D+ ~1 ?, ~0 G" n% i: ?5 y
0x00, 0xFF);
- t5 _9 D; r: i1 g1 u- \, ]9 @' n# v$ P& n7 o
/* Enable synchronization of RX and TX sections */
; u8 ~& C; k% {; u2 ]1 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 O q; n/ I( e( p) ~$ U0 L2 JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" l) s! B: r' Z+ FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" @4 c' c# i7 _( q' |, [. D6 K* s** Set the serializers, Currently only one serializer is set as
2 q1 `3 }3 ]; ]; O** transmitter and one serializer as receiver.; Y5 k! @, l+ j; L1 h
*/4 [) ~$ }9 |* n$ F5 _9 c! \+ n3 B1 b0 u1 c/ b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; @' k9 \2 J$ }. x6 W$ w' {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# e# w9 Z1 j3 @
** Configure the McASP pins
( j: f1 e2 k* |/ A' L! L** Input - Frame Sync, Clock and Serializer Rx0 p$ y! h% N8 N1 P. q2 D
** Output - Serializer Tx is connected to the input of the codec
! E9 E/ N5 n. t: h*/) @6 q! v. i1 L% Z8 s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: b8 h1 B+ t. }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 q% \- l$ V( E+ v6 \8 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 o6 s% K8 @# |7 x) R| MCASP_PIN_ACLKX
! l# C3 u7 G. v! D4 g$ J. {| MCASP_PIN_AHCLKX
6 Y; \& c, Y6 p( h) T' X" A0 W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; u/ g( Y' d: R2 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 x) Y& P* V* N
| MCASP_TX_CLKFAIL
$ ^( g/ S0 Q- b; E, z| MCASP_TX_SYNCERROR3 s+ e* d* L+ I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 R9 j/ y0 f: Z \1 V; Z
| MCASP_RX_CLKFAIL% z5 |, E# s8 v& i6 [! v
| MCASP_RX_SYNCERROR
4 u" a* S; a/ F7 J/ o5 N| MCASP_RX_OVERRUN);
9 y1 N% M" ^- Q} static void I2SDataTxRxActivate(void)+ ~$ M" }9 M7 v! ]
{
6 Q9 l1 n# D/ K6 Z/* Start the clocks */: D+ Z# ~7 d w3 \8 ?7 k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' a6 A* N0 Y6 [+ n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 o: T6 G; h9 c2 f( j- C, GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; U# P! P1 W6 |; s. R8 P
EDMA3_TRIG_MODE_EVENT);# k/ y" ^1 |$ L. b0 o: W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ S- J1 ^$ o8 u2 V+ G _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 K4 k* u' y4 ~3 @7 p: K2 J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; m$ U( z% f6 `* \" S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ A8 ?( A* g$ S* C9 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# s8 {( C) W. t, q* X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# f7 Z7 t0 n1 Z. l- T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); u+ a* Z/ x5 g. ?) n4 s$ t! o
} ) K+ c+ |4 f' n* u" H( r% Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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