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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; y" L$ h) n- I0 {
input mcasp_ahclkx,
5 B4 Y! }9 `9 F" t7 sinput mcasp_aclkx,0 b* Y; E. ]. H. ~% }
input axr0,
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' x/ m; O# _$ X: a2 voutput mcasp_afsr,, K- q& B, k2 r' n& {) t6 \
output mcasp_ahclkr,4 o M0 v7 H" N
output mcasp_aclkr,
4 O4 l7 E( f' I3 a! O6 W; q' E3 koutput axr1,( S% D2 |/ a1 S" G. N. _: f* @! [" x
assign mcasp_afsr = mcasp_afsx;
$ k! `8 Q" Q% K$ ~6 K* q% ~* R' Y2 zassign mcasp_aclkr = mcasp_aclkx;
" j$ n$ O8 p" c2 j$ ^assign mcasp_ahclkr = mcasp_ahclkx;) T! \) r* k- E G+ f
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( g6 p. {0 i: n* O6 r# Q, g
static void McASPI2SConfigure(void)2 x# w. g8 u, k2 y% b+ c
{: d; \3 @( o+ G6 }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 ` {; s5 }6 l% M3 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 l) [' C; }' H0 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ Q! l6 o+ W' O+ a. T5 c c: s% QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# O2 e. g/ {6 [6 I+ ]& MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& `* h1 x# G g3 \9 J
MCASP_RX_MODE_DMA);$ u* ]- y5 ]& g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' q% W/ G, l, M/ F1 @, K8 m0 WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; ^9 N/ i j( gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , n. @( u1 Z6 c" m- }8 b# }7 C* H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% R/ S; n7 U: b$ k4 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + [/ p% q" N% {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& @" U7 C2 e. q. x" W; hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 m- }# [7 S q" g4 GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ E$ `) S8 Z; k8 r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! l% O3 H F9 [$ }1 }# t# g
0x00, 0xFF); /* configure the clock for transmitter */
3 s. k. P( u, n; b0 I( J3 g. XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) M; I/ T$ x: L# f3 V+ j7 e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 w, z& {1 f4 s& l! |: f- Q2 n" s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- j6 M6 D1 G) f$ ~! k e5 q2 [0x00, 0xFF);5 m9 y( o; |& y# o( i
* o0 t7 y( G# Y+ Z$ e s, L/* Enable synchronization of RX and TX sections */
0 e8 j) f+ |+ c) f4 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 L- D, g6 S7 r4 H& i$ i$ x8 b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( r& O# ^8 I8 \/ }! N( F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 [. P* z* Q7 G( V* U, b+ U; i
** Set the serializers, Currently only one serializer is set as
! x$ h$ O' T H** transmitter and one serializer as receiver.0 H" s9 q4 `' f7 M, Z7 f' _3 i
*/
# f# l: {: K* j- r" \" N" d4 G/ \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ T7 J. u! j9 ^$ u* pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& p3 d& v6 x, J/ M; [$ m0 `** Configure the McASP pins
/ [& z$ O7 M* l# a8 V! e+ q** Input - Frame Sync, Clock and Serializer Rx/ ]: W: L& {( b0 e1 `
** Output - Serializer Tx is connected to the input of the codec
( L3 f4 _/ f2 a/ w0 @ b5 h*/0 V3 k, r9 p! L3 z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 D8 M. e7 Y& aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' Q% B! u' |" h: d; d7 l$ ^! _$ B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' \; R" `( @ E, [" I% i| MCASP_PIN_ACLKX
" ~5 f$ b9 v' @( R2 l, l; a| MCASP_PIN_AHCLKX+ k; o* S7 s( \: \' J9 c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! @7 ~- `. O- m* W3 V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - r: U7 x7 {: d+ C
| MCASP_TX_CLKFAIL
; d+ \( a4 W$ Z& S& _% W& F) r| MCASP_TX_SYNCERROR1 {) ^7 u: n( n, Q$ @* v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , Z" e& `( @" w4 N9 p* R/ U- H$ @
| MCASP_RX_CLKFAIL
: t. G1 G0 a9 D* y T; F/ ^( s| MCASP_RX_SYNCERROR : [8 Y. G; e( \; B. o
| MCASP_RX_OVERRUN);
* \* w+ y# X! e$ x) B; s. j+ u" c5 D} static void I2SDataTxRxActivate(void)
7 |) i) M: i I& n* a% y! N{
$ ~& h7 T x% _; {# l% R/* Start the clocks */% u, @, {8 Q1 J `" q8 v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; X' ~+ b2 M/ D$ _1 P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 r: q8 L$ z' f& c4 T9 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, F, M- ]0 b# C& i$ _! u
EDMA3_TRIG_MODE_EVENT);9 D/ F7 L' R2 P& E9 @ U3 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! n. n' q( Z+ @, H# l6 \% OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& q0 {9 I% [ V$ {2 e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 @ H, D7 h7 L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ O/ L$ y1 `$ M7 mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
x: Y0 ?" A$ }0 m8 }+ D* j8 X( DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, F2 I: U% d, B. k# h" HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# l/ ]0 Y. Y' g7 K$ B( o$ d}
+ A n6 m( f. y1 X2 b* m( l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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