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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 ?0 ]6 o" {( N0 H' E
input mcasp_ahclkx,! m* G* h' ?$ ~$ Z; z2 k
input mcasp_aclkx,
& J/ t. [6 t4 o4 sinput axr0,
/ r; R1 n. X4 g7 d6 h# ~$ g& H; D6 [
output mcasp_afsr,) ]% R4 _7 m, A- A* _# ]
output mcasp_ahclkr,5 _. ^, \2 f' f) S; a
output mcasp_aclkr,0 K* r' ~% ]2 R/ o# t- l1 k
output axr1,
1 s. e# v' V3 z/ g6 }& H1 j, v# q3 Q assign mcasp_afsr = mcasp_afsx;& q) N5 u u# ^+ e: U! t8 i3 v
assign mcasp_aclkr = mcasp_aclkx;
5 q3 W( U( O8 I f4 ?assign mcasp_ahclkr = mcasp_ahclkx;
$ F! @' {* j4 _& X0 V; u8 ^# qassign axr1 = axr0; 7 ~8 b4 G' ~3 s! }: e/ O' Z3 j! Q8 ?
+ I6 V9 |9 d' E6 q# F7 k# t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) G" \ S# J/ C1 n( k3 U# v
static void McASPI2SConfigure(void)
) y' |5 c* ~9 f( Q+ c+ u{$ W* [5 {7 l5 r) B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 U' t o7 K2 I H3 RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 n1 |% j/ r" \2 { [' o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ M$ ~" y, @6 u9 B3 g4 XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& k/ M" h$ }- g4 H: O( w; r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; ]' ^; L. a4 l8 {3 @
MCASP_RX_MODE_DMA);
2 u, `5 r6 e0 c+ ?3 [0 t& B) ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! P0 y. s& W; s0 O2 E5 }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: K2 n4 W+ }) h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. \ H: R. D& a" W1 P% K1 r/ NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ K I0 T! c3 ^/ i# L. ?& z* [& E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 H' @$ g" |! ~- |+ l& l9 P; PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# o: {4 Y/ p1 W) S/ u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 w2 {5 j4 a) s8 t% x( V# w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 L7 J( q: I4 H# P0 n, e( GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: l) m9 [' H5 l1 p9 t' n( K0x00, 0xFF); /* configure the clock for transmitter */" [* ^. q/ W; ~* `, f) p5 w. b; |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" W, c7 l0 E. R) G( }( g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; ]9 J) M8 r# [6 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 o9 }5 C/ V/ H ?5 c$ q
0x00, 0xFF);
5 g% V. y* N9 N' E: H% X! T/ f. o+ X, U
/* Enable synchronization of RX and TX sections */ 4 h* Y% H3 h& L: ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( h# j, f/ V, [ T/ a+ m8 m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 ^9 }1 L/ a( ?* }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ a. O7 d0 @; B** Set the serializers, Currently only one serializer is set as
( e3 x+ b8 T9 U+ h4 a$ w** transmitter and one serializer as receiver.
6 S% Y- S2 u3 `9 }+ Z7 x( P2 R8 O5 N*/
: a; W7 ^1 S/ E0 ] E% |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- [& [4 ?* n& y1 E. ^) S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; T a7 Y/ Z8 g- w
** Configure the McASP pins
' L/ K# Z/ g N; N** Input - Frame Sync, Clock and Serializer Rx
& D4 Y$ Y( b9 M0 X1 ^/ b** Output - Serializer Tx is connected to the input of the codec
+ Z) r) S; d$ J S; j6 k' X*/
2 N+ z* B3 |- @7 }1 W5 GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 \+ Z5 x; r. g+ g$ i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- B7 {1 \* |( \: R2 \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: ]) P- f) J" D; W7 x. a
| MCASP_PIN_ACLKX
* e& y$ S2 R( k' W8 b| MCASP_PIN_AHCLKX, ^1 \, M8 |2 c# f1 _" _3 C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ d! M- R6 e3 p/ Y: e7 @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 A5 ^5 S7 f: N/ s1 h| MCASP_TX_CLKFAIL
9 d& Y/ U0 a, K. k! ~* b| MCASP_TX_SYNCERROR
3 h5 F# C3 h* X" ^6 ~/ W" Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & w. x% F: F! h8 n0 i! z
| MCASP_RX_CLKFAIL
; m8 ]3 j5 G" w4 r9 K% R5 P| MCASP_RX_SYNCERROR
( _3 u5 ]% d. P- L1 U0 L| MCASP_RX_OVERRUN);
0 l; Q5 y) C* k; c3 a} static void I2SDataTxRxActivate(void)* L9 |9 V: Q; j2 X& ]
{4 b' g9 J# H' }' }6 O
/* Start the clocks */
6 S5 ]- @/ `, P$ a7 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" G' F1 q; a! B2 YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 y9 N" @4 X. r7 c- k% C6 j9 z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% J" Y1 x' {% v" Z0 v% T0 |EDMA3_TRIG_MODE_EVENT);
3 \; _- T `3 P. dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 R n2 {! I. \/ M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ L! U6 c2 [; o( ~; \- G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. H1 O3 X4 c# A# r4 W; o, @2 ~/ o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! H+ i5 Y" W6 y& y: t6 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' v3 b& Y- t/ h# K0 U( wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" w: Q: `2 p8 u' A, G6 Y2 r5 y6 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 W8 h. u; J; P* T' t. b}
; j4 x7 R; s6 e t; l+ k e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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