|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ i" `1 i+ _. @% n, a2 n
input mcasp_ahclkx,: @& m- m) x# w5 d
input mcasp_aclkx,2 M, D" |* _, k2 b' \/ ^
input axr0,
& ~" ~; e" K a) I7 z. H3 k8 N! r! B- `# R( J+ @5 {) M
output mcasp_afsr,
9 K1 \% t! A+ |1 P1 T. R/ Houtput mcasp_ahclkr,
3 E# ]' M6 I: v( goutput mcasp_aclkr,2 j+ G3 @0 w* j# F4 H9 Q5 I& q! p
output axr1,
; q# ]. ~1 @$ O" s8 q P assign mcasp_afsr = mcasp_afsx;
+ p+ E4 h4 G' Z2 Lassign mcasp_aclkr = mcasp_aclkx;
! L( r4 p' R+ U$ x) q: v; tassign mcasp_ahclkr = mcasp_ahclkx;& d# I9 q% K6 K3 N/ w7 R# @
assign axr1 = axr0;
) z2 l+ T# Y+ o2 x! P+ v* M+ |- p+ G" d1 D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / q+ G9 m$ W0 M7 P# r
static void McASPI2SConfigure(void)2 r) v! \ ?' E+ a! [" f
{7 o% i( O G+ W& d6 Z. a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 v+ H2 X3 F3 e; p5 e2 @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" U/ I4 `, i% d1 WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" a8 `$ x* p3 F' W) s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# _) M/ T) F8 E& c- e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% v( s V8 I4 y" x5 t5 y9 O/ h
MCASP_RX_MODE_DMA);- C" _. l' b9 m: e) P7 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- O, T: e" c! {- J5 a6 aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 U6 S2 @7 y; o* `% z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : `9 n* m [3 C; ]% U% l8 Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% O P5 l, G ~* ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ ` b0 I0 P3 e+ CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) X! o! y% X$ |/ c8 c. |* MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 V: t$ D/ o: {% x' {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 ?+ R V% }: M' W! Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& a8 \7 S T8 J6 j1 S* h' B
0x00, 0xFF); /* configure the clock for transmitter */
6 X7 h5 ]9 j: g% g8 cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ j! H. i3 u! G/ | j$ |4 z$ r* C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; |6 H' p7 K) J+ ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 ?4 m% v w. O, D" `3 r* J$ |
0x00, 0xFF);
+ s; t: a1 C. Y9 l- p0 y) ]' d* p5 V( j) \- r: b/ Q0 g# q
/* Enable synchronization of RX and TX sections */
! B0 z, ?! C T5 YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- H c7 c' t% t0 `0 OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 F& {: T" g+ u! v% S! k; p+ M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! R e! t' l; Q$ ~
** Set the serializers, Currently only one serializer is set as# B; y h8 y7 w5 V( s. T
** transmitter and one serializer as receiver.
1 c+ w; v) _2 L*/* z7 l: [. g8 z) E: |' F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
P; S# o& S P( M0 B0 jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: e- u: m& b$ Y: k/ @& F. [! V
** Configure the McASP pins ( A) ]: d5 l8 X$ B
** Input - Frame Sync, Clock and Serializer Rx
! I N8 [& m- o) u4 i** Output - Serializer Tx is connected to the input of the codec
i* l( o- R# l) o: l& ] u5 y*/; q- [: O% e9 H- F) ^) D# w. K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. {7 e9 Z5 M+ k7 ^" i/ uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 T w8 R0 y" r5 H8 r! }8 h, BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 t# e0 {. |- o3 h# E! D, E| MCASP_PIN_ACLKX
# s: D9 J3 Y, D0 l, j1 A| MCASP_PIN_AHCLKX
0 V& M; n# _7 n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! D3 x; m5 z s, X. h# q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" M/ u* A8 s5 }7 p| MCASP_TX_CLKFAIL 9 ^- o/ [& p4 s7 ~
| MCASP_TX_SYNCERROR! c* I( T& \: S- D* l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . G& S- K) ~ y0 m$ F
| MCASP_RX_CLKFAIL+ b) r- ` V" U) m6 y
| MCASP_RX_SYNCERROR " Q+ |: r$ k, b. g$ f7 H
| MCASP_RX_OVERRUN);, e" D9 t0 S7 J
} static void I2SDataTxRxActivate(void)# [. s( B" ^7 D7 Q
{8 J. B. `; h- t3 V' s+ d
/* Start the clocks */6 D r# G; Z# i+ X2 C7 E9 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" p$ o: Y6 Y, e* U0 V; gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 B- ?6 f1 L# p5 A; e0 \9 T3 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ d L8 |( {1 K* P8 pEDMA3_TRIG_MODE_EVENT);* K1 g8 c6 E4 W/ Q( j2 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 n- G3 Z# N( l/ e# {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, H) W" K) @7 w4 @+ T1 }$ q; yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, L& P2 }6 @8 w1 ~5 ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ m4 F1 s2 g" `1 r* q- U% Q" X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ Z! G, G/ W) g3 Y8 W0 \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- W1 q/ @5 p, D8 B7 J6 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( a) P" t z$ g8 h3 f; h, c3 Z( w
}
5 I$ k) F$ X% V- Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. m( Y7 t" c8 ^! T' G1 ^8 h n/ T
|