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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 g2 f7 _# q# W" sinput mcasp_ahclkx,3 T* J5 T# o0 e* m# U8 c4 I6 P/ r# J: G$ c
input mcasp_aclkx,
& n+ P4 M" E) a* B c8 xinput axr0,) d6 E7 b% o3 }
( b" _/ k0 s( ^1 [5 a ^7 ~output mcasp_afsr,
" q: ~0 g; ?8 t/ Loutput mcasp_ahclkr,
# p9 Z( @8 m, t1 H! k7 E% P, noutput mcasp_aclkr,
3 R# P+ y! j& ^1 Xoutput axr1,1 |( f, Z# i+ @) K5 l, {' K4 Z
assign mcasp_afsr = mcasp_afsx;
) @( C" F+ Q0 {+ t$ _) i1 \$ cassign mcasp_aclkr = mcasp_aclkx;
0 V: i& @* M; q/ s/ a% p+ Massign mcasp_ahclkr = mcasp_ahclkx;
+ B. [- m3 M) d* w# B Kassign axr1 = axr0; 8 s) x& {6 c, Y( H" s5 Y: N
0 d, W. r2 ^! `- J ~( J) t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# I/ P' B1 ~7 fstatic void McASPI2SConfigure(void)
) z1 k+ Z [* h2 c. { u5 j{: G6 P- L, |/ }+ H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& f5 N% X" w* }& d' e3 dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ A5 P, n5 n% X8 K4 R* \5 Z2 L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# K' }5 X- n5 Q& l- e! p' i1 MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: e& n0 E: K- @, c9 ]: X7 C" WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* P4 @* G! ^4 Q) v" Q2 [
MCASP_RX_MODE_DMA);5 l9 Y4 K+ t* k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," p; G* T4 ?* Z7 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& S- x6 i( s. O! R* v" [+ ]9 L) O! A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 O6 M4 |# P) |6 O! EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 O# ]8 d7 L0 z* U3 F/ Z5 }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% m* R8 l: F* ^4 i e. r7 [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& A8 ^% v# G) v S( c! n, N4 c6 UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 E) x) @) f. L2 v4 _' A& JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) H$ {$ b! {. ^' a% z+ v; V% z KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ b: r& I3 O4 O" Q1 E0x00, 0xFF); /* configure the clock for transmitter */5 E) G2 n3 w6 T2 ~& i9 x# A/ b( E5 _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 _9 y- C6 b ]6 T) hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 J0 U, h H3 U& cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 l' R* U1 A4 y9 ]" `: B* ]9 s0x00, 0xFF);5 |3 r) d. B* ^* g$ H& n
" s8 I( g0 ~9 ~ q" b4 x$ |. O/* Enable synchronization of RX and TX sections */
4 }, Y9 U3 _# R6 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 i& g2 r2 b" i/ M( n( S9 TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* A& w$ V) I! p1 K6 V* ]0 vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** E! {8 T' L# q w5 b# S7 J
** Set the serializers, Currently only one serializer is set as! E0 ?2 e j# P! M
** transmitter and one serializer as receiver." A/ k [6 X i7 h$ k G# ^
*/ L' X8 X; b7 F+ N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 A2 w6 _$ u5 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# `$ Y [/ ]+ t4 X' \! a+ e
** Configure the McASP pins
. T* S( T5 V2 T" ?6 ^7 o: [' ]2 w; z** Input - Frame Sync, Clock and Serializer Rx
. v5 C1 _* m( a0 d# _$ o** Output - Serializer Tx is connected to the input of the codec 4 \' H+ E+ h1 \
*/
$ a$ [4 N. F0 x$ c1 cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) n2 [$ j y5 B6 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# s& J" J' c3 s; r% ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, x! l# I9 x B| MCASP_PIN_ACLKX& [# k# e: X4 J0 W3 k) n0 A, N
| MCASP_PIN_AHCLKX( n' z! Z5 w ^) L. p( O! Z4 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: v! U+ ^ ?4 B) O6 j0 ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - y7 P5 C) m0 o F: b) K7 r1 q
| MCASP_TX_CLKFAIL 8 t- S4 ?( C- W, P9 @
| MCASP_TX_SYNCERROR; p" P( a) d5 c# B5 @6 f) a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' ?3 O, V; [6 R7 ^; G4 ]" D5 k| MCASP_RX_CLKFAIL
) W P J3 C2 i }7 H- X# ]% ?4 || MCASP_RX_SYNCERROR
0 Z/ w- n% ]$ G$ u2 C| MCASP_RX_OVERRUN);) f4 T( R4 f, L4 q
} static void I2SDataTxRxActivate(void)
4 w; |' G- Z( Q k: F9 g8 l{/ k" f L5 ^' O# i9 _3 d
/* Start the clocks */
$ z" P& e4 a% E0 i( BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. h( o- O% H2 @/ C/ }5 C6 {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 s' }$ @# V1 W5 V- s- T3 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 n3 {1 p. u& c8 A6 c8 U- \EDMA3_TRIG_MODE_EVENT);
0 A/ \* q$ U9 i' GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 n$ N% j# d0 F1 y/ n- K/ m' Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; X* }4 P4 Q. W' Q8 C9 \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- E+ W) Y& F, e( s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. B, _2 i7 H9 q9 W# l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ d" @& v( j8 O+ R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. N+ A2 W; `' T L+ e& dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 q" w# d' T1 E& P, y7 u) I) C
} # s3 [$ {6 J! C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - r/ y' X1 ?1 h6 I5 O( G
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