MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
- x% t0 [; q/ B$ L1 [" y6 h; xinput axr0,
8 q4 A% k& m6 F! l  {4 W
/ u9 [" M  O' ^5 {/ |) g7 |+ ioutput mcasp_afsr,
output mcasp_ahclkr,
' {; i1 l" z7 d/ `+ ^output mcasp_aclkr,
' Y5 z8 A/ H& Xoutput axr1,
/ M/ h$ u' z  d0 V- V1 N% v

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
# ~% X" C. D: J7 C4 {8 }  N2 O# Oassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

9 ?2 \' H; a( R, A

static void McASPI2SConfigure(void)
{
8 M1 Q. g- U0 Q0 m, PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' [* B# |5 s- G, P* TMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
; a( I5 ]8 T+ c; p. \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 {5 Q+ [; H/ FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
' k0 J* F6 L/ NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, p: i/ z2 K4 {+ bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( n; u" z3 I) J" ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# m0 a- ?1 i" N1 z0 @! s, GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ ~" }: K. C) w1 N2 ~& j1 K0x00, 0xFF);

/* configure the clock for transmitter */
& b0 r( H  Z/ h+ k, y6 @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 @1 K0 I5 u9 P9 w0 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ K$ V2 R6 h/ l) G0x00, 0xFF);

+ M; s0 |9 u8 f: g' ^/* Enable synchronization of RX and TX sections */
9 e4 ]+ y: r( H) J7 m7 G, lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ B0 [, J) p$ ]- l. S; f' T4 P8 l4 ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
/ s# p$ H2 u4 X4 k7 T: j** transmitter and one serializer as receiver.
) T5 u1 c+ _8 D*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% n! \: V; _5 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
/ f2 w4 J1 h! O4 ~0 X$ q** Input - Frame Sync, Clock and Serializer Rx
3 x, W# Q" e- R% d- D** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 L: A+ E+ N5 ?) ~; ~& M( nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
( Y% W. i' H0 n' o$ }$ C' f! G* O" {| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
4 B% z$ p  t7 ?4 I1 G* ?| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* u% y  q: @: \8 a4 S- @3 ?| MCASP_RX_CLKFAIL
. i) {7 n* M2 V3 ?) M| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
+ H; }, p' b8 f; k9 U4 ^}

static void I2SDataTxRxActivate(void)
, J- U+ Z6 w: K5 P: h6 s8 `" v{
/* Start the clocks */
* i+ T' r2 Y' Y/ \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
4 |! h; i+ M6 r, C$ dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 T- Z1 ~1 `; J  T1 \) ~+ UEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* [* @1 w/ t! X; c0 UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
0 F& t' d5 S+ M, YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 `& `! r1 J( {9 [  f) d* qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
2 O. }% G, o7 ~$ O3 P+ @$ UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

/ n7 V3 d: O  e' t2 C  C/ m

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.