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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- Q' h/ S+ s5 K2 Jinput mcasp_ahclkx,8 O; } w7 S0 b! J1 m# b) L
input mcasp_aclkx,
) o9 D3 \& Z( f" Hinput axr0,4 E/ c/ D1 o; O- c( b& X( G2 [
& u2 }6 G: f4 k; woutput mcasp_afsr,. B' F( H0 e# E( D8 y6 l6 m! D
output mcasp_ahclkr,* i+ S j" ?( [# o
output mcasp_aclkr,/ f& Y5 s0 l; z, O6 W
output axr1,% Y. X% P3 E8 v) B/ _- Z) e/ T
assign mcasp_afsr = mcasp_afsx;% G1 S2 j) h* p5 v% J' V: d
assign mcasp_aclkr = mcasp_aclkx;
- U* ~% E: }% R3 q& U- Bassign mcasp_ahclkr = mcasp_ahclkx;# F# c/ x- D7 ~/ y
assign axr1 = axr0; - D2 X' X# Y8 K
" M6 K% k5 ]& u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , [( L$ r# X. h( {$ b& o/ `1 n* [1 e
static void McASPI2SConfigure(void)) H. C% |- z6 {( U
{
6 F" f+ A+ z1 [8 {- qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: V7 \* [. u( q: d: u) ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 Y' V8 E3 |/ t+ @. v6 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 ~. `- P( V, ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 n# t" j, L- }- |6 NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! K' q, ~) j; w
MCASP_RX_MODE_DMA);) O5 y! K' z) c0 _' L) S( H( n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ k7 k. J& j6 `$ d, {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' ^" g/ J3 C6 B" c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + F3 d6 F7 M" Z$ U; x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* X7 f* k8 ~* A3 S$ j' O! uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 W. z! @5 x- E/ j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. [% X/ z% E) A* r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 ?1 F! E: y, }! F# \! t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
F2 k4 U( h9 k* @6 ^* _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) h( M/ T7 j2 o' B/ p0 l0x00, 0xFF); /* configure the clock for transmitter */- G" F% W: W. g: B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 O! @ `: `3 A3 H3 b9 I0 a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 c1 P( z6 n* ~( z( w- y0 F: x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 B, M7 r3 l! T7 _" c4 g0x00, 0xFF);: q: j& y) e- y: j- g; k
4 g8 D. M; M6 C! v, e1 S
/* Enable synchronization of RX and TX sections */
2 o) D; `% M* H9 K' zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 A0 n( z* e. E+ k4 H* cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 R, {+ m, \; V. I/ C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 v: U; B5 E/ \( |9 Q
** Set the serializers, Currently only one serializer is set as
- ~1 X. M& F b7 u7 j** transmitter and one serializer as receiver.
& z& q& d0 C" I*/
+ c4 l0 {5 \+ A3 kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 K- M- G# S L* K6 ?$ p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 P- k4 G7 W& |# c5 H0 A** Configure the McASP pins 0 }4 C4 }- I! B; m. f0 \6 [
** Input - Frame Sync, Clock and Serializer Rx0 O7 a& [& a# a+ r
** Output - Serializer Tx is connected to the input of the codec + }2 i. G/ w F n
*/
- [0 L3 m; Q5 sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 l- P2 r+ s+ R K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ _: N; \9 m# f: B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& @# X( J4 T3 j' U
| MCASP_PIN_ACLKX
' W1 ^- O5 U4 O: F- m, {$ ]/ D| MCASP_PIN_AHCLKX, |* Z$ z0 K0 r0 O5 o/ ?7 l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; M l. m5 P3 L5 g3 H J1 n& X4 ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & G# W' \% x+ O: u- d* b: n& Q$ w
| MCASP_TX_CLKFAIL
1 [, h7 c7 I) v7 `0 N| MCASP_TX_SYNCERROR# q# L" d" |) d' ~; t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 h6 g9 p# |# @& _+ t; L| MCASP_RX_CLKFAIL
7 b( L6 _; j# F| MCASP_RX_SYNCERROR 3 g& W* x6 x, M+ _2 d% ?
| MCASP_RX_OVERRUN);( L9 M, e7 b/ V
} static void I2SDataTxRxActivate(void)
- I5 i5 y! b8 h; I/ k1 |8 R( A5 ]{: q& s+ G: q3 Y1 R* [
/* Start the clocks */
8 e* i, t! Q8 j R; \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 e9 D/ k" b7 w. w. e6 a p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// I0 v, U; w* ?! L7 S9 P7 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
W _! f: ~% nEDMA3_TRIG_MODE_EVENT);
q2 p! J" \3 |2 I1 \! c$ n7 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 S' D+ F) i! E: P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" h: t# P* M" Q/ A7 Z8 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 U" b/ Q' j9 cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- n2 X1 {* Y: r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' ~; s4 c+ @: p' m1 u; m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# @6 r; J$ O& r' m2 L9 \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) J3 l0 R- ~' `! y}
w4 E2 f" t, S& r, K3 V" _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( F+ H% q. H, O7 i
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