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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; a7 a9 d& x! f: G& Iinput mcasp_ahclkx,9 s% x* N# @% R; G: k
input mcasp_aclkx,
, j6 h( Y) q' T Sinput axr0,
* X" b& e5 K, N9 h+ D
' H3 ^! b. ~7 u$ s% Goutput mcasp_afsr," T/ k8 g' \: ^+ E- a. q. H
output mcasp_ahclkr,
6 Q& S, O: X+ T; ^/ W \% R4 toutput mcasp_aclkr,
, z/ ?8 n) m0 N, m# J2 Koutput axr1,1 J, c4 a+ \. M' d1 I8 S9 ? f
assign mcasp_afsr = mcasp_afsx;8 A o6 A# i" \: i: @. G1 o8 u
assign mcasp_aclkr = mcasp_aclkx;0 W$ l) H5 v! |# D% ]
assign mcasp_ahclkr = mcasp_ahclkx;. G$ o: I% h; C! ~, a3 M
assign axr1 = axr0; , g, {0 r3 w* X+ `. W5 |9 Y
4 j% F9 X8 k9 r# b) o! E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% @! }) d8 o, `2 W2 O+ v7 Mstatic void McASPI2SConfigure(void)% F0 g! d% C# b% k' r
{
2 I& }6 h, R$ ^/ C# ^3 R0 UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 \# A; p4 G# j$ L, i% y$ |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 d# |& F3 z0 a2 S. M# ^( P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 e2 i! v* j# {4 F6 y9 ^ PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( Q( X1 U! Z) ~! [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 B) x2 D; y- {1 K& A2 p. kMCASP_RX_MODE_DMA);# D" M E! Z1 N V1 R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 S! i% i; S" H/ f8 `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& C* _3 O* w5 ~+ bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 E$ U% e9 C" s- U1 G7 dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ S1 W) @. v' B _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 u1 P. {# e R. h& N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 K: E8 K$ v. G* |' sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( c1 Q5 P* W7 BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) Z3 U5 l' o" _/ j! s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% Z" Q+ @' [# p/ U9 Q
0x00, 0xFF); /* configure the clock for transmitter */+ L) y& \8 c$ ~0 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# l8 W. H+ z, vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + n$ z( H5 A d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: ~. f5 _6 D6 J6 e0x00, 0xFF);
T$ I# y( ^; f7 A7 J7 b1 T+ R; J& A& z+ V- G
/* Enable synchronization of RX and TX sections */ Y T/ q) V: |8 A8 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ v9 v' t) X: \/ F( B1 N; T/ ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 ]$ p* }0 V9 ^1 n0 {- u7 g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 J, y) E3 n @; l9 `** Set the serializers, Currently only one serializer is set as# Z4 D; L7 k# q; c3 v
** transmitter and one serializer as receiver.6 ?% H6 \% \3 f4 P+ F/ s
*/4 X; @- e8 E3 O2 W. L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) X- w7 O) V) B3 w6 }4 M1 |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; L5 {$ w+ h4 e: l; c** Configure the McASP pins % B F4 N6 M* s1 [- Y% f
** Input - Frame Sync, Clock and Serializer Rx7 f" _. H. {0 F
** Output - Serializer Tx is connected to the input of the codec
' A; [: p9 x6 x, G*/6 ]5 r {9 h( v- N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ Q: e% L% E: B c: X4 GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 L- ?8 x- p! x; t1 E! g4 KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 @* h! h3 ~, A6 X| MCASP_PIN_ACLKX1 L9 I. e9 g8 C& U
| MCASP_PIN_AHCLKX/ ]9 b5 G( T- c: N: g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 B9 V; @) o M# Y$ ^4 c+ a5 mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 A" @: \9 l* o+ C. p r| MCASP_TX_CLKFAIL
4 |; Y3 W" j/ ]0 j- {| MCASP_TX_SYNCERROR
1 m1 c5 g% N5 ^0 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . z" e. z5 {- Y8 G
| MCASP_RX_CLKFAIL
; t+ C: p4 M' _7 p0 v| MCASP_RX_SYNCERROR
2 ^1 u( L9 L5 U; U| MCASP_RX_OVERRUN);
, V! W; ?3 R; }% Q' ^ F} static void I2SDataTxRxActivate(void)% f9 {6 J) o6 ~! L( i: t
{
+ S* A: W' X6 @* z( h0 R/* Start the clocks */4 C! O% {* K, p1 Q# h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 _. |8 w. l& H8 e C9 L) g: ]4 P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ C# z1 p ?9 b5 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- T) O+ j+ B0 |& ]
EDMA3_TRIG_MODE_EVENT);1 V, p9 Q& ^$ s0 B5 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: C: M: d* ^8 T3 q# @: J! e, p- v" ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 E+ s; L9 ]1 `: @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ c- n% D2 O+ M( j" sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 e% m3 b" Y( t7 O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* M U! n5 C' l0 u: T* s. xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- g4 m/ i+ G/ ?# D: C4 D6 x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" L5 X9 W+ B8 _5 K: Y' [
} * q9 U9 f- w' S1 F- r9 K* P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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