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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& f8 m/ d0 j3 tinput mcasp_ahclkx,* U8 g3 ^4 H/ n, K
input mcasp_aclkx,$ i: s( B4 Q) z# j
input axr0,$ h2 k5 V1 K& v: a, D5 f
: r1 W! o/ R# H& H
output mcasp_afsr,& c: Q. A0 Z t- N- Z2 Q" c
output mcasp_ahclkr,
2 x5 P$ ^3 o) I8 y3 {9 y& moutput mcasp_aclkr,
) y. L1 O4 w( U, H" B# voutput axr1,
& c- @; O. R) u' b2 a* D x% X; O/ w assign mcasp_afsr = mcasp_afsx;
7 [6 y y4 N0 E; a. Y7 m4 a( tassign mcasp_aclkr = mcasp_aclkx;
+ G7 d8 Z2 F9 j0 x/ J) Yassign mcasp_ahclkr = mcasp_ahclkx;
" t- U+ S0 _/ j& [2 aassign axr1 = axr0; + _9 \# t$ @# j% W3 e' i6 ^
, T! [5 C: A6 x+ D. ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
b$ G. d6 ]3 V6 e; T0 Hstatic void McASPI2SConfigure(void)! Y2 g* ~5 c# T: C0 T" Z8 Z
{) N6 h/ t# w+ l) t) U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 S' ?$ Q) S: F5 J1 f8 B& f) HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" J1 X; X1 k) ^+ a" hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( r; n8 ]; |% ~7 O- \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) s/ H% Z' h$ F) \# Z9 B gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* b8 O2 V( c+ J
MCASP_RX_MODE_DMA);! R5 ]2 i8 P1 o* O* P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! _, z3 O" D7 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 H' E4 d; V8 r9 z2 h! o% nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) L! q x9 V1 F o* B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 c5 n, s) e4 P: z$ E9 c8 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ @6 K) p2 y1 y* zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
M+ P3 X/ j! g' j' ]( n0 r9 m3 j5 LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' h# G3 d6 e sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, j: I5 D2 Y5 c& P; W8 M4 [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! p8 \% \# R; ~1 {& t% n
0x00, 0xFF); /* configure the clock for transmitter */
3 o% w/ U# ^# T: y6 r9 n1 LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ @( p* g' o( y$ y2 h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; N, x2 \( j. K l$ U5 B( B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& m9 F- q1 U" N& g0x00, 0xFF);3 b8 {& V, m5 ~* \' j
4 O( @; A* i( u, g& x8 P/* Enable synchronization of RX and TX sections */ 3 b. |2 t. j, u6 D8 P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( C8 l5 @" X' V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 ?2 r+ Q5 O- K) F/ Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 p( g5 y6 T7 [- w8 L2 E* L** Set the serializers, Currently only one serializer is set as
, E- ?5 m; O/ `1 X** transmitter and one serializer as receiver.
6 s* r' X- y& s; L+ Y1 C% Y*/& y( ~( l, g% ~/ V9 ?% m! m9 E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
c* o# _8 z/ j2 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' H8 C. J- _1 n" e; m# _** Configure the McASP pins 3 ~" V5 Z. X1 v+ L4 K9 F. b
** Input - Frame Sync, Clock and Serializer Rx2 X+ `* P0 M, i- Q9 A
** Output - Serializer Tx is connected to the input of the codec 6 R/ N4 D! w) Z, H
*/
" m& h" X m! U! ~/ V9 X# vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; s9 l. F S% b# r6 [! K, s% b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 C$ }% L# C3 O8 S# o2 ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& F9 @! _! [. f* a, e8 d5 I
| MCASP_PIN_ACLKX
+ y, I- j5 {1 x, N| MCASP_PIN_AHCLKX1 ~" R6 f" ?5 v) m9 ~! |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 b" u7 N- W4 |5 H, U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 _ v9 U% e0 {" H
| MCASP_TX_CLKFAIL
& l a2 h6 P0 ~2 h) @| MCASP_TX_SYNCERROR+ O7 v7 b! A# t2 U+ e7 h8 o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . i$ Z# M: G# l, [# ?) k
| MCASP_RX_CLKFAIL, f5 b* A) z' j4 a7 l0 L7 M% Z
| MCASP_RX_SYNCERROR 3 m5 x3 c7 _' n: H; m1 A/ M
| MCASP_RX_OVERRUN);9 ^ U: K1 y% i
} static void I2SDataTxRxActivate(void)8 {$ a5 t5 q9 s( a
{
/ Q/ v5 L1 C, p7 u8 S; w7 d* [/* Start the clocks */4 w2 s( R* v0 u0 R" d: x% [& k3 V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ N3 U/ N: N# R& j5 `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 I: U! { D* h% s- `) Y: t8 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% Y. ]; m1 G" a* _ U% K5 d- F
EDMA3_TRIG_MODE_EVENT);! m+ V* M; z# X) h0 j8 @" N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! @! G# f, Z! W/ K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) t9 K/ l# d: E sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: u5 o. ^" ~$ ?1 o( d! _3 w, j$ fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 j: P' R5 L P) Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 j' p3 F, \9 R2 H( q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, J9 {% k1 h* P! H" \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 w% v1 A* P, Q# p4 `}
# O5 q" N! x1 N4 m( \+ Y" y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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