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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 T" k# ^4 K3 D4 Ninput mcasp_ahclkx,
! w9 r) C/ F: e; V. ?input mcasp_aclkx,5 |. H1 X: L$ z6 L
input axr0,% A) L/ J. N6 j7 l2 d$ G: o
A* [( v r5 O
output mcasp_afsr,: T6 B/ P, R/ D3 D+ {8 g
output mcasp_ahclkr,
, P+ W& H6 {) y( L( }5 [8 R5 Houtput mcasp_aclkr,* v/ y1 d3 K! f
output axr1,, R3 ?; e. o" I! n
assign mcasp_afsr = mcasp_afsx;. o: Z- u. Q7 ]( f, \; F2 n M
assign mcasp_aclkr = mcasp_aclkx;
" Y, v- G7 e; u2 q, }% @0 uassign mcasp_ahclkr = mcasp_ahclkx;
, ?' x* K" X' m# Z+ p2 A! zassign axr1 = axr0; 0 K2 i. d' g% H" ^3 @
/ @9 W" u# L, J0 G4 o& N8 S! f \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# q/ B+ R6 z+ m4 zstatic void McASPI2SConfigure(void)
; H+ P- n8 [. B7 u9 u$ c3 U{1 O4 R: m2 o% R& [4 P+ }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 L- b% g0 `1 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! o* P' J7 w5 g( `( FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 j" F8 G/ r$ {, ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! c3 ~ x' C; [6 A# P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 A! H$ O9 j" U' |5 C
MCASP_RX_MODE_DMA);8 E/ c- G! b( C5 G' J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 m( D1 G% v+ ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 \: l. ?. u& L( w* G: U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 Z0 I1 j7 I" cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( i0 y0 z- Q! i8 IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % D9 ~/ |, |% K$ v* w: f D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 M1 f9 z" {7 O& C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& E! F, i) ^; J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( V' ]" }5 B, |: U( N6 \3 Y: l2 x! Q7 z W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& V" O8 Y: }! E! ~
0x00, 0xFF); /* configure the clock for transmitter */
7 }' }2 J8 n) u& J& s3 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 J2 o) |4 W, }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 I1 c% g b' s- `' b: ^8 N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: l/ I9 I5 g' s8 C
0x00, 0xFF);
' z! N, V. o5 ?6 Y. b Q
! z9 z$ G! Q0 c r/* Enable synchronization of RX and TX sections */ j' T( H8 t( Y5 u: T) e; i; A$ ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ F8 _: T j* H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- o, h) ^. h9 ?# w6 G& S# |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& ^8 D0 u) ^5 z
** Set the serializers, Currently only one serializer is set as% V/ L/ G/ d4 J7 i
** transmitter and one serializer as receiver.
% L4 H, o; x& J7 j3 B*/% H% s/ M8 }" Y4 K* b% z! e6 I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' _7 `4 p6 W6 M' x( L6 o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 a& b6 f9 ~& `: A" l8 R
** Configure the McASP pins ; J& k7 G+ ~. P+ ~ S# r- K% x) Y7 R; M
** Input - Frame Sync, Clock and Serializer Rx9 Z9 Q$ a0 R6 Z6 O
** Output - Serializer Tx is connected to the input of the codec
1 S- u# u, w. Z4 s- [9 m5 A, D/ o*/! |$ L2 A' n- e6 @ ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 Q3 `$ O* g- E* r3 \6 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( H4 I6 e0 Q9 b4 E% J! {8 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' H& |' {- C7 u, N1 X2 n9 E, |. L
| MCASP_PIN_ACLKX9 Q: q4 L% K H
| MCASP_PIN_AHCLKX
8 i; f R" U; r: N( W- B1 f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 H# {: d7 y7 x4 w3 N! v9 n) zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ |1 Z3 Y) N f| MCASP_TX_CLKFAIL 2 _6 ?3 v P6 Y# ^& \ ]
| MCASP_TX_SYNCERROR
8 ?- [% O5 ]. K) ?. {, z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 T# Z1 c7 x/ }$ X
| MCASP_RX_CLKFAIL
6 R5 F, ^- e+ y; D) k8 K| MCASP_RX_SYNCERROR + y: G+ ` @6 c: N! v# v; _
| MCASP_RX_OVERRUN);
* h4 ~" w, k `% h9 ~% n% _/ \} static void I2SDataTxRxActivate(void)
" x. ^4 D: Y7 V4 O* Z2 A. F{) H' \; Z0 Y6 w9 M& D
/* Start the clocks */% l- ?3 o6 S; \$ N8 p; @. |$ z: S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 o# e7 R% Q! E* v5 f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 B4 }+ T& B- q5 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; Z+ h# ]4 U. W
EDMA3_TRIG_MODE_EVENT);
- f4 M4 j- J: u& k _' BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - [8 M9 Z+ m9 K ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: @. ~, q }9 h/ G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 g: w' z/ J5 x4 K, uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ j7 x1 Z8 k" e5 `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 O6 K' j$ ^3 a' mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" a2 O* B* G$ Y' ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ _% a4 H% e! J; P& K1 {4 N* {9 U3 _}
5 }5 Y1 J8 \; w/ c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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