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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& T9 R8 Z$ ~4 E, D( W( Winput mcasp_ahclkx,
4 m) z; j$ r7 r' t7 ^, `input mcasp_aclkx,
2 T* P( q9 y8 ?$ O/ F1 }9 B8 binput axr0,. M$ P- l9 s; k4 A1 {6 s" z
( o1 K2 d5 n5 u9 h9 o7 s) O+ n
output mcasp_afsr,
# V% g$ |6 c* |7 ]! N; Doutput mcasp_ahclkr,
3 I: \; H' f9 E9 c3 {$ g+ Eoutput mcasp_aclkr,5 b& v1 `( Z, H2 O; H
output axr1,
! e% U. `& u( o' U$ e$ E assign mcasp_afsr = mcasp_afsx;
8 d9 B$ t" \6 _* P2 Hassign mcasp_aclkr = mcasp_aclkx;
5 l- f3 S; N* B+ Q2 Wassign mcasp_ahclkr = mcasp_ahclkx;
/ E( }* `2 l. T) Q$ J% lassign axr1 = axr0;
' _. _$ {( t7 ^& ~% O( Y: C4 a m0 [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* ^* W$ ^/ u. p9 J( g' g6 zstatic void McASPI2SConfigure(void)
2 H0 m J7 F! a! n{
% P# h% d. h6 p) h( z: ~4 P/ ~; YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& ]$ }" c# q2 v& aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 f( K# g, ~4 F7 w+ s0 w; p4 s6 x/ ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 V& o3 X/ E1 m9 K* @2 O& {5 s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" X* \1 c! P4 |! C) X+ q& N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: {7 |* V. y: Y8 D! bMCASP_RX_MODE_DMA);1 i" Z2 f _) `7 N h+ D, T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. {; g# ~, P! G8 q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* Z9 c+ q. @( j2 v, Z/ p( _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( [$ @ I1 ?, F$ k6 E3 X% [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 o! _! Y/ I; A F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 X+ o# s) t& I5 E) U# n+ BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# L7 r2 e1 `/ T9 ]5 h2 fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 ]! i2 O2 g5 [) K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 c3 I+ T3 m) GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 |$ n) k# J, {5 `3 ?6 r5 S. L
0x00, 0xFF); /* configure the clock for transmitter */
% i% \$ V2 L, d# q' e( X0 V; eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' \% r) s$ y# u) R8 d4 y: ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 D! Y) Q# d' v& CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ b2 k. d% N: ~& q- r C: }6 p' E) R
0x00, 0xFF);
9 V2 X+ C9 |8 p" T3 e
1 t. U% S, y# e$ O/* Enable synchronization of RX and TX sections */
( i4 e3 B- h+ P. NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ L4 Q p& C5 X$ v9 `3 NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% t- J( ^9 H* r6 X4 |# eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 B! p8 [# h1 G) }* d+ t2 i8 z% x** Set the serializers, Currently only one serializer is set as' p4 O) R# {/ h! t8 X& @' m$ c/ G
** transmitter and one serializer as receiver.
5 _' e) Y) G: a: Q7 \*/
% ^1 p/ [" w' L2 D* KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 D; T/ y8 J$ h% v0 IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. g6 X) @ X* V$ f; W% d
** Configure the McASP pins
1 B, ]: V8 a) U ~- W4 ~0 w4 D7 M** Input - Frame Sync, Clock and Serializer Rx
, ~, h* ^. R# Z0 U& n l: { b** Output - Serializer Tx is connected to the input of the codec 7 v/ M3 [1 L! c) d: G8 A3 k
*/' d, p7 f; ?5 {& U% k3 L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( i- ?& @' Q j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! K0 Q0 h$ `: B4 n5 k) DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) N9 ~4 C0 R T# |2 s! j
| MCASP_PIN_ACLKX8 a! q) e! g i; t6 W1 \. ~
| MCASP_PIN_AHCLKX; J. X6 ]+ ?( j' G) w8 g8 v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 `) }6 J) g$ b8 _0 G4 w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 J' n2 b5 C7 x# R2 ^* W! v
| MCASP_TX_CLKFAIL
' v% @0 w+ @( I| MCASP_TX_SYNCERROR7 w% p! c8 Z$ ?2 z# B7 M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 w) F. }. b2 j7 x6 b& x( K6 K6 V+ K) h| MCASP_RX_CLKFAIL
" D) ~' k, z( v4 I+ c| MCASP_RX_SYNCERROR ' x( ~) X0 W1 x; M3 Y% `
| MCASP_RX_OVERRUN);
4 w5 J! |4 m% e; M# M} static void I2SDataTxRxActivate(void) `( g- J, Z0 v/ e1 K9 q
{8 {9 M+ K$ n" M: ? ~; B
/* Start the clocks */1 k0 U4 u+ l) V" S2 ~+ d: \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" Y! a+ S" ?' W3 SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. J3 a( d( }- l" s' LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& y! a" k2 N+ W; B2 v3 ]9 Q kEDMA3_TRIG_MODE_EVENT);- s; K1 E9 ~* Y: x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " q% N$ v1 Q" @' Z" G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; r( m6 `" h KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- g+ Z. a' I1 `+ _8 r3 xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' g- J9 o7 [2 L Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% \' }* Y1 a* F- U+ Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 v; p+ A: o+ ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. Q, L) } ^* ^8 }}
/ ]# X8 y, F: a! C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * O0 D& [; c- K; y% ~
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