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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: X/ E. o; g( R# O
input mcasp_ahclkx,
1 o, k+ V( o( W X; O7 Minput mcasp_aclkx,7 a1 B! ~2 F7 G+ R- L
input axr0,+ s+ |9 c& D9 E7 a! x
' Y5 U8 x' c2 R! T/ toutput mcasp_afsr,
0 x) w( a) X3 ^) U6 e! koutput mcasp_ahclkr,
/ }5 \9 u9 {5 \) houtput mcasp_aclkr,( X C' f# k& {! S4 d' H
output axr1,
; [2 _2 \& c0 H4 J) _) y4 Q assign mcasp_afsr = mcasp_afsx;3 W! O9 o$ ]* \+ G) v' ~) {
assign mcasp_aclkr = mcasp_aclkx;
* F* `( s0 U; ~! Hassign mcasp_ahclkr = mcasp_ahclkx;! q3 q: [" {, G S; S: Y0 Q
assign axr1 = axr0;
; h; [4 I( x7 E# |( T$ X. R) h1 y* t8 u# [7 ~/ S* K$ S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % A8 I8 B7 {/ z, `
static void McASPI2SConfigure(void)& P h$ x4 z. I! h I H" g! ?
{
- i8 x* N, ?7 V |. J% z/ @: q$ NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; F! r9 `; x$ W2 D8 }3 _0 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- g. f8 g3 O F9 U$ k, cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 c; _# O, q7 U ?' S4 w0 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 v B9 {" P9 A2 J; N2 w8 h& f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) |; w. h7 c2 SMCASP_RX_MODE_DMA);# ^2 h1 a/ e( F6 C- m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( \# u7 d& D2 {" t6 Y' D, N; k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( M6 l& W6 P/ a6 G- S% _' @% m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 ^4 Y* _' x0 x- F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ u! s" D5 w) z' E7 H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 Y: E Y( u" s, L$ NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 K! d, H$ ]) I+ J1 H' rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); {" R2 }; Z* x( I6 `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 r; z3 [4 g7 R. H9 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: c& g- q5 B; l9 ]. @+ T A' _
0x00, 0xFF); /* configure the clock for transmitter */
" V3 u% T) i6 M: |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 T3 X4 k* S1 R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( p. P% f; a+ [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 @1 x3 a* a( m( j8 e
0x00, 0xFF);
: s3 U( v" y2 d; u( j+ `9 J+ b0 m/ }. V. R( k. Z. w( L
/* Enable synchronization of RX and TX sections */
, d* }9 ~" x8 ~8 i$ B1 pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& }$ k. u1 q8 a# b6 V: D* C5 C& j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' M# X9 C' \0 v, x: xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: b$ y+ O& g8 q( K# u8 z; J' U) ~** Set the serializers, Currently only one serializer is set as$ _( V( @% [2 J) _4 q/ Y6 Q
** transmitter and one serializer as receiver.5 ?" U6 ~8 z( K8 f1 ]9 y
*/
8 R& W% s; \8 m5 F) vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' U8 W; Q) l, i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* L7 K6 b5 D9 J4 _4 Y** Configure the McASP pins
) _# r4 L+ R, u; ?8 `3 P" f3 E5 x** Input - Frame Sync, Clock and Serializer Rx
, S4 T. B/ |$ \; l3 P** Output - Serializer Tx is connected to the input of the codec
! j; R; i& I2 i*/
( _4 Z$ C7 p* p+ ?# p2 H8 F5 ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! i1 X( I+ M& S- w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 [% r7 U, i% O5 C% Y9 uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. j# o8 O/ a- Q0 o- _5 Z
| MCASP_PIN_ACLKX
: `7 m" ]+ z1 G) ~( S| MCASP_PIN_AHCLKX+ C/ _; n# Z# P! ^$ D$ A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) x' P, P5 G* O* k$ H; |) s' dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! t: I' ^7 X1 x: d# z2 ]
| MCASP_TX_CLKFAIL
7 _; ^2 y- A! `' o0 `7 ~' A| MCASP_TX_SYNCERROR3 {7 {7 A6 p% e* l# [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 X! K$ _! j' J3 [
| MCASP_RX_CLKFAIL
* H: ?, b$ `+ f6 h- U, w; u| MCASP_RX_SYNCERROR
! Y# O; ?, \3 c| MCASP_RX_OVERRUN);
' [& w) ]3 R# w; \2 i} static void I2SDataTxRxActivate(void)1 w8 |- f+ t) Q* h
{5 X/ ?, G6 N6 J6 J
/* Start the clocks */
, X5 g4 V) S1 {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( v# I4 c6 R( h0 jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 J* J1 ]7 l) T* y7 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 X# s3 F: G1 C$ {! n5 I2 O
EDMA3_TRIG_MODE_EVENT);/ g. ?/ c5 L# p) Q( P; ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' h, W; {3 v) n' K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" | D9 i: Q) g3 z$ Z2 z' B6 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# |/ o2 t) v5 E. d7 iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; C) e5 k0 q Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* m. ^& S( b) n" N8 zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" v' S P' }- G0 v8 a6 d/ }0 ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 u5 S3 f/ f9 q3 C5 }
}
) S+ j) E. v- I+ Z0 M1 P2 \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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