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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ |1 f/ `! y R+ C xinput mcasp_ahclkx,
8 q( s. m5 l$ N4 O9 T( W! |" E+ b2 Minput mcasp_aclkx,# F1 V8 U% A3 t8 e; [
input axr0,
* d9 v4 ~; v7 ~" B( d. l4 A: K1 q, d8 C/ b2 q% f: m5 h1 s
output mcasp_afsr,
/ O7 H; v4 K* v* J* }" r4 ^$ goutput mcasp_ahclkr,
2 z- J' r: z; \output mcasp_aclkr,
: ?- N# C3 G! o- c1 j& W4 loutput axr1,
1 y( T: N* G3 j0 o# u assign mcasp_afsr = mcasp_afsx;# p* o$ G8 c$ o: b0 l( _6 m
assign mcasp_aclkr = mcasp_aclkx;% T. g3 a! |2 d0 }& J6 H$ d2 }( I& Y
assign mcasp_ahclkr = mcasp_ahclkx;5 t! d. C, A0 ~3 J
assign axr1 = axr0; ) L) O1 ~8 X. i& K2 Q8 q
( m4 b# ^( _0 V6 I+ y0 a" Y+ @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 O8 D3 N i3 r( _. ]) u. c! d9 w' Ystatic void McASPI2SConfigure(void)/ F& X" C& I: P L
{" R. s6 a# a! d* F7 u% h$ x4 \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. A& h- X) [ g1 Q, ~$ H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ Q9 M ]0 x! _3 @$ Z& F M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' o: O: t+ N k" }. t# x0 w+ l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 K$ Y% k, z' U: ?+ _# o5 o7 A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% t, Y- Q, B/ t1 R$ iMCASP_RX_MODE_DMA);
6 s, |# u; K+ |' `, c5 y4 ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," ?, |: X/ C( _& P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 B- O4 O# l0 s3 u% S9 l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, J. }4 r" _, f1 u/ MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) x$ ?7 h. u. T" m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 y* w# D) t2 ]7 ^% b! YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( J5 z9 f7 ~' |0 C( pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 }2 T2 e/ y/ X9 p- {, k$ \# L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 x4 L6 v6 ?1 p& \4 uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 C9 U9 y( l# }$ {* _: |, p0x00, 0xFF); /* configure the clock for transmitter */1 T& \( x" W% ]/ O/ F+ @* o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& J2 |! `% i' B3 `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 C# ~* e" S2 o5 q- m' ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" F1 n7 g: a. a) L! `/ K' v7 r0x00, 0xFF);
9 T1 F: A1 i" W/ ]( h7 J
' ^$ K7 I$ N/ g6 U/* Enable synchronization of RX and TX sections */
2 W% M/ P: P7 w5 w& A# tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ T: E r( b' ]+ D) j5 PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ ^8 h* R3 {2 O! e' q2 F+ `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 B+ q$ K' l& t. M1 g** Set the serializers, Currently only one serializer is set as9 M! v! ]2 K; J, ^; H- ?
** transmitter and one serializer as receiver.
3 B) y1 ?. ?0 n8 e2 w0 W*/
$ E+ C5 I( s8 r, C8 o( g" ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 w' X+ u+ c8 I/ L8 _9 \: q4 EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 V! E5 W% n( M; W** Configure the McASP pins & [+ I$ e- |* b7 y
** Input - Frame Sync, Clock and Serializer Rx4 H4 \: b/ z$ T9 M
** Output - Serializer Tx is connected to the input of the codec ( ]7 f1 s" Z) b, k& K' U2 ~$ q7 L
*/
. Q' o6 q1 P! W- B/ k/ r3 MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 V2 e* F+ X+ B4 F: KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% G7 ?! I- O% i; mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( ?8 D# u. @1 M& ~$ _0 G) x
| MCASP_PIN_ACLKX
% A+ t3 D; |1 R( k$ ?| MCASP_PIN_AHCLKX
`* d0 c$ u2 T) d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" u' l+ A7 P+ k+ q1 {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& _2 D9 W4 r5 ~1 b, d| MCASP_TX_CLKFAIL
! F4 I/ S+ M5 u| MCASP_TX_SYNCERROR2 C7 q+ {- N0 S- H. Q/ U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR v5 t' g* b6 ^& I) @/ @3 C9 B
| MCASP_RX_CLKFAIL
. ?, o2 T! v) T8 h6 Y/ F| MCASP_RX_SYNCERROR
" p! g8 b5 w. d- q0 {| MCASP_RX_OVERRUN);- \& B3 n/ h, z) n$ a/ ]3 T
} static void I2SDataTxRxActivate(void)2 X- G: z) ?3 \- A5 ]0 e$ p. Z7 ?/ o
{
- N; A* V$ n' @) A/* Start the clocks */$ |. q; v; F- u. a2 s- H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& H, _4 G _8 K' Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 W/ P; a) _9 r6 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) I0 a- W- Z/ j% L3 Q
EDMA3_TRIG_MODE_EVENT);
- Q) v+ x7 F' P4 E+ r8 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # }$ a5 X4 }; X, ?: l, q% U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 b/ n& L, o3 c) B. u1 L: ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- m. H! q) }) q# X+ r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" @9 r' o' p7 l7 J" s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: m/ W' A2 _# IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: k# a L! Y# }8 [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ e' o/ C# t& B+ `
} 4 ^& w6 S' n) P: c: D4 u7 E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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