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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" a( R* x; B6 J; L. I. @input mcasp_ahclkx,1 }* o1 q* y3 Y; Q5 A2 ?9 _! B
input mcasp_aclkx,
* b! [6 ~" S1 F8 W( rinput axr0,2 I6 J2 K9 N* {& K9 n& r. R, C3 s5 d
0 {. A+ T; {6 C2 S, \' |) Xoutput mcasp_afsr,- c% e# p, G. a2 l6 D2 F/ K
output mcasp_ahclkr,
3 e v- C& |% @( \" Y0 H2 R }output mcasp_aclkr,: w7 [9 G! u, z2 k" S
output axr1,
/ _" u% f W* P m/ W assign mcasp_afsr = mcasp_afsx;
; e" \1 F: U: M H- [/ o2 T; Iassign mcasp_aclkr = mcasp_aclkx;
8 `. }4 g; O8 a9 B) K. A/ F9 lassign mcasp_ahclkr = mcasp_ahclkx;0 H3 e$ ?0 d( a, e" L, r
assign axr1 = axr0; : b# K! e6 A% q4 T) o8 y
# V6 U! r5 W) W- C/ r9 X4 c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ I1 b9 a5 E: ~. I0 {' b
static void McASPI2SConfigure(void)
, [; W3 Y* R; q{
) {+ k- E# j8 K* P) p5 \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 R2 ~8 {3 ]% p2 ]/ _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! ^5 m/ v n, l/ Q" g4 f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! ~1 A* P" F$ B' |; N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, a9 r X6 V4 \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& k0 V3 ]% h! w/ u+ |0 _! Q' E
MCASP_RX_MODE_DMA);
9 j4 H3 ?6 C( D$ b/ Z0 E( lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# L' a+ I6 e/ c; p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" H y9 A& v# t$ D$ V$ z; y+ }6 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 \' `7 A: }# P# S0 u ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 H# h4 f; d7 G$ @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 t1 U4 C+ s# y1 n, p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 x8 I; v6 [: U4 J2 c! tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ z; E x2 V H* ~- dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ _ i3 Q+ ~9 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 b. [# A( Q, A% S# J
0x00, 0xFF); /* configure the clock for transmitter */; r+ a9 o+ V Q U8 [6 e( f( D7 _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ F ] V% I Y7 Z QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 B& Q, l, S3 G i( v7 t/ FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 N# ^# `. w. i$ r! D/ D2 m2 B& \8 g/ Q, `
0x00, 0xFF);
1 f. H; _) O4 ?# F6 G% _) y$ U- R E. X, R3 ?6 D6 T u& X I: e+ x6 X
/* Enable synchronization of RX and TX sections */
7 z/ i9 A5 U* I0 C7 n3 O2 D8 G. jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 p" I6 N* q. a- \; L* d* T0 J- ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 r& M8 z7 }# N9 u4 G) r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 S) B6 u. J8 o
** Set the serializers, Currently only one serializer is set as" p+ V5 F& C/ ^) `1 J/ Q7 m4 A! b0 r
** transmitter and one serializer as receiver.* H0 a ]2 j& Q' p8 t. Z
*/9 r+ m" |. l; A! J# Z/ m8 Z: \9 i% }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( ?5 W& N9 G6 j" ^- wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
e8 e1 W3 J" E- n** Configure the McASP pins / \0 J b4 b" _+ v2 l8 d- W
** Input - Frame Sync, Clock and Serializer Rx
6 B! T4 w$ y1 q( w" f0 f' i** Output - Serializer Tx is connected to the input of the codec , t' k1 `3 a! X9 W
*/
6 d; B/ M' ?) TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 O# x0 Z; ]# L& p' Q& V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 z s7 | R5 D5 _; l7 `! g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 E' M( Q( \0 x. Y
| MCASP_PIN_ACLKX
L& Z# T/ t* p| MCASP_PIN_AHCLKX, H& ?% n$ e0 m9 c9 q* Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 c; J7 X5 Z& r7 U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 i7 \0 h+ E& p4 y6 E
| MCASP_TX_CLKFAIL : h: u/ f, |9 D: U& w
| MCASP_TX_SYNCERROR; B" w/ T3 ]: `/ S4 q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" G3 V$ g9 J& l7 J| MCASP_RX_CLKFAIL
j: T1 K; i& u5 g! i| MCASP_RX_SYNCERROR
, E% o0 Z7 z5 q8 v| MCASP_RX_OVERRUN);, f3 Y$ d! p+ Z0 m9 ?# [
} static void I2SDataTxRxActivate(void)
0 J. y: ]. j7 j{
. ^5 c1 @8 f, @+ v0 `/* Start the clocks */
0 w5 p( T5 [" R, Y# ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 a$ x/ g9 l( s1 U) G, cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% A8 S- P% p; t+ r0 F! YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, ~) N- I: i$ f/ CEDMA3_TRIG_MODE_EVENT);
: ^3 J& Y O7 P. u: x) GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % g* h- ]; p+ j& B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 i5 U- o y2 M8 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" X0 }0 u% p, K! [& T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. B3 ]4 Q; A5 k/ Q' n/ [5 x! O/ ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ {; {, A! j$ D# @4 A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% F) i7 J/ R) o, ~1 Z9 m4 W6 y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 ]# X1 O! O/ g0 _ ~' f" M8 S} 4 q8 D* {* R( ?+ s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 n% a! R! n4 _1 n! l' H
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