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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 H9 e8 h3 T) T) |% D% U( C' X
input mcasp_ahclkx,) Y% X. q* c9 I0 a6 N* E3 P4 J$ Y
input mcasp_aclkx,3 F7 M$ c' l* }4 f1 B1 |
input axr0,! P% l1 `% ]& _, I
" V1 S; C4 |' i1 Toutput mcasp_afsr,, f; ?7 |7 ?; h) E% @9 t. l4 b! B; Z s
output mcasp_ahclkr,7 e/ ~# P: P7 _5 O! ]
output mcasp_aclkr,
2 L6 W& Y: O! S) v/ i/ Y/ ooutput axr1,7 Z; E* f# q& ^5 Q4 A$ B- c
assign mcasp_afsr = mcasp_afsx;1 E* n, I; U) ^, h
assign mcasp_aclkr = mcasp_aclkx;
8 T4 n8 a* D: N# N1 ^3 \8 Q8 }assign mcasp_ahclkr = mcasp_ahclkx;2 J" ]) L) {* X1 j j
assign axr1 = axr0;
# l+ E: I+ o& q- Y( f: {( L' h% {- N [: Q: O2 h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 N5 Y: n# u7 U" C6 U3 Gstatic void McASPI2SConfigure(void)9 W" D& P( P; y' P/ N
{
( _% I- {& i* t5 Z- m0 \7 Z9 v1 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 o4 h: R6 ?, }$ v5 z9 B) X- `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 ~! f2 T) o, q" U/ W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' e" d' k: _+ Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 _& A' E( t* [. j! K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; E1 f% C7 d6 @" z: k0 A iMCASP_RX_MODE_DMA);6 Y( ]- h% K- H1 w \5 Y0 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* b" w0 K) |, ?7 }. ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 C* b+ v# l6 o+ u; ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & X) Q0 b$ p7 ]+ ?0 A! F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- ~' i3 j1 O N* g, k4 ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 [% e! ^6 Y: m) K; TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ s- E7 ]% w. P/ b# q8 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. {- r1 m4 ?( e0 j/ G: [/ ]% {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * }+ [* i- w' q$ V' ~$ v6 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 B9 B% e, ~5 ^ i
0x00, 0xFF); /* configure the clock for transmitter */4 L4 j- e+ l7 ^$ B v5 z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( j, L p# V: O- aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , }0 ^5 g# C0 O# J }. _; B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: @1 S5 f: U- ~! [! c9 r N
0x00, 0xFF);9 D8 Y' H5 p2 g6 n! P
8 ~/ c% |% C) B# n5 @& H- R/* Enable synchronization of RX and TX sections */ $ d3 d1 s0 w8 i0 A/ A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- y5 D* [2 \. ]1 Q2 G `) E; g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 y& X/ D2 j" v8 i( d) m/ ~- fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 v) l5 F, `, |5 X3 b** Set the serializers, Currently only one serializer is set as/ A; h) e% C# v; ?, `6 }7 B, d& t. F6 D2 O7 R
** transmitter and one serializer as receiver.
2 P* `. ]! j9 {6 T5 g+ m: Q*/; m5 p7 P$ C9 J$ g! z$ f2 H& ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" U) R. \/ E# M( L5 I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 K3 y1 A7 `+ P+ L+ F
** Configure the McASP pins . n& a$ b" F& r) X1 U0 u
** Input - Frame Sync, Clock and Serializer Rx; c+ c' T0 _2 H# H- n
** Output - Serializer Tx is connected to the input of the codec
+ a" g0 K7 H6 `; } N7 p8 v; C*/; C" R6 ]1 F) I7 g; n" g. x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' [1 f# i9 |& lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 X* f: f& m. V& a9 zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ W0 G) @: Y( ^- X9 @' M
| MCASP_PIN_ACLKX
$ Z. T/ R# |2 c% X# u. ]0 j, s| MCASP_PIN_AHCLKX- W6 ~7 R7 T8 p7 i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 k$ n) f* u; W; I2 G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; M8 X+ q4 x8 F! h8 X5 F| MCASP_TX_CLKFAIL 8 b. F1 {* L, T6 a+ b: A& p
| MCASP_TX_SYNCERROR
' F; e* j- z) d+ h. l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 h1 O$ j, _( B( d2 {| MCASP_RX_CLKFAIL
% U' o B; Z8 ?8 X4 [7 ^| MCASP_RX_SYNCERROR * ]0 f3 B# A+ _" p1 r8 F. h
| MCASP_RX_OVERRUN);$ l/ i4 v, S9 V5 `; C$ N
} static void I2SDataTxRxActivate(void)
% P+ [! G3 N# Q' u5 `{8 F; B6 @2 X5 B2 H
/* Start the clocks */# `; e. T3 D8 ~! J, s) F! q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); C3 M, J* m/ p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( i7 ?1 g( p5 x1 x* g" l4 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
g1 l/ k6 }( p0 g: f2 xEDMA3_TRIG_MODE_EVENT);
; E0 V' Q: P F1 a+ LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 d) `" x7 U4 O4 k# Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( t5 I% {- v y+ {+ g" S6 l) `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# k T& `1 O8 D0 N+ \6 KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. M6 f- E1 [) m9 p; Z- l& S! F% F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 g9 w4 t8 A" R5 f8 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; B: f3 ~& e- T. V- GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 _" _8 W3 W; t: K
}
: n6 C6 d4 t N& e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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