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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 B% c- u2 M3 d6 a, R/ |input mcasp_ahclkx,3 ] d4 N8 R4 p2 k+ I+ @6 J
input mcasp_aclkx,+ i1 X! C9 N a# y& ~2 g& |
input axr0,0 b6 x- ]7 z( |% P1 D4 R
, W) B3 c5 `% ~/ `output mcasp_afsr,
! a# p, [% `2 N* a6 |1 Goutput mcasp_ahclkr,7 ^+ q' d5 l+ n: N1 ]4 y9 P" b
output mcasp_aclkr,& o! \0 Z8 a' g9 E; k( u. t
output axr1,
( f6 z: T: N b3 b9 j5 H+ l assign mcasp_afsr = mcasp_afsx;% l7 n7 Q7 U: F: h: f! r# b
assign mcasp_aclkr = mcasp_aclkx;- X' a2 B0 x4 r7 s- a$ J
assign mcasp_ahclkr = mcasp_ahclkx;% ?2 z0 p ^# ~" D
assign axr1 = axr0; / g8 p5 S" ]$ x) N& Z
' ]$ L3 O% V8 R# \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " g! B4 P. Y+ H: d& M1 A
static void McASPI2SConfigure(void)
: p! s1 G& B; `1 x" }# o. H6 Z: E{
6 m4 U* U' q+ ^0 Q0 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ t- G/ f7 f2 p+ rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& _2 `, ]; S I+ l: ] J4 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 ?% r% c' }+ k" {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) N# i; Q x( GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' n: l4 R; Z* C& W/ DMCASP_RX_MODE_DMA);
& @0 V6 E, e1 q) QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! _8 i* ^6 t* [/ @& x3 ~. y+ z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 L2 J$ h0 r- z# y/ c; TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
p/ F9 c( J/ M* C7 @8 F$ I' y: rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 K* G1 d* `: F! q" C- uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 D! [. P' y% Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% j. M% j4 ]8 T7 F& x0 t0 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ i& Z# r# N5 ~, L+ x0 NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; i# e0 S' A g& X9 K% l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 g0 c: X' Y6 Q1 s6 b6 q7 q
0x00, 0xFF); /* configure the clock for transmitter */
: r* k, ]' a" Q, I6 nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 M/ `9 ~* z3 G" q p0 fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 e4 r; g8 f9 m6 t, [: u% s8 \: WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 ~( [8 r# G. n
0x00, 0xFF);
3 v( p, k6 B P2 b" }! ^/ |# k+ Z, V* p: }9 w% }& x0 @
/* Enable synchronization of RX and TX sections */ * [/ l2 J N8 U( V p; I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ _% l5 f* R1 }- aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ g `; {2 g7 C% }( ?& M4 `2 a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 g4 o2 H$ N+ @+ H6 c** Set the serializers, Currently only one serializer is set as
( i7 T' T( E2 B: a, N( q2 M** transmitter and one serializer as receiver.
5 B* [# N" L: e! j' L' f*/
) }1 U. \5 ~* `, Z1 f6 {% lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 f$ D3 O) K, ~' a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. ~+ {4 ~" T1 P& \' a
** Configure the McASP pins " d! j$ k# y* _+ t+ ?. _ y
** Input - Frame Sync, Clock and Serializer Rx
: y) |! ^ p: y) o** Output - Serializer Tx is connected to the input of the codec
+ g& S: F, T& v* ~2 A+ K& F*/& Z7 K' W; f9 x d5 i% Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ M$ ]% b2 j# [. ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ H3 G" B6 a$ Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX y- J4 V) [0 S4 a! K* M: @
| MCASP_PIN_ACLKX
8 i$ g5 W3 Q( ~) g @7 r| MCASP_PIN_AHCLKX% i" }+ b9 o7 a5 g% \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
t" u8 c- ]0 P# zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& Y0 `9 c: B$ c- q6 X6 Y| MCASP_TX_CLKFAIL 4 ]2 H5 c6 f4 U( m8 a! M- N
| MCASP_TX_SYNCERROR
8 [. m' W* A7 F- S" S: N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 D2 e+ b3 m ^. P1 _
| MCASP_RX_CLKFAIL
0 B7 l# F& s( a5 Z, J1 y; K! _| MCASP_RX_SYNCERROR
: O, _2 x; }5 R8 m+ R| MCASP_RX_OVERRUN);" v5 V4 T0 y+ C; _; K5 Q( h* }% [
} static void I2SDataTxRxActivate(void)
3 v! F* q; c ?* V6 W v) M{# P3 M, M; |) |9 z9 D9 E/ B. ~% {
/* Start the clocks */
% w0 n* G5 X% l) N' H5 Q4 { `) VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- C! _8 n7 Q) h ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 b/ p" K4 C. }+ R+ O/ X, L% `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& N: v6 \ l: e5 s8 M
EDMA3_TRIG_MODE_EVENT);
# k2 P* m Z8 N9 S4 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 o( @8 I [: qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- g C! a# J* Q I- D5 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 r, N0 O X' J$ ]+ g% eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ Z2 D1 j0 x! c! [. W0 e8 d+ {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 ^/ V0 m, T3 K/ P, _/ j& S9 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 ^1 J, @; k6 w1 U) {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- H9 B H. H6 Z( }} 3 @! O$ u. p- d9 O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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