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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," j3 f2 U0 X# r! W' [! l" w# |
input mcasp_ahclkx,5 Y7 \0 \% g: S3 W6 [
input mcasp_aclkx,
, B! y+ M1 j3 p/ T) I) h1 [input axr0,
4 A( Q2 j6 V9 k7 @5 l0 k- _. C' _; L/ i+ `& X: l% a* d
output mcasp_afsr,
5 _4 p) ^$ U0 L* r6 T youtput mcasp_ahclkr,5 T8 B9 s' y9 e8 o/ T! r- u6 r
output mcasp_aclkr,1 t0 s+ C- z6 d4 [2 L6 a; p$ E
output axr1,- U/ U4 v7 d, u4 B; y
assign mcasp_afsr = mcasp_afsx;
]# R2 h- @- Yassign mcasp_aclkr = mcasp_aclkx;
0 |( U4 `! {. X. Lassign mcasp_ahclkr = mcasp_ahclkx;! b/ T5 g* S( a
assign axr1 = axr0;
# ?7 l) V5 D! f- V' P. T2 l$ q, e4 G( G2 U" e2 [7 a+ b5 `+ x% G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % ], P8 ]% J& r" L7 ~
static void McASPI2SConfigure(void)
, y" V* Y" E" a2 n. H" j{
' }7 i( W8 k# b: ]* GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: w8 N; p6 m; g3 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% f) {8 {5 ]" o) e) @, MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! w% k% o* |: O4 r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: {4 k5 e/ f) a) W6 `5 ]/ C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, V; V, X( [, B- t( R( H; r% @ a# `MCASP_RX_MODE_DMA);! ?8 x2 c- R& K% T" y% H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) l$ D8 \& t N- R# Q; U2 A# }4 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) ^( Y# t6 \: x- UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : Q+ p0 I. T4 `! e: |. Q4 `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" `! Y- i7 c: a0 r; GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & E. w0 E4 Z8 A* b* T5 L, }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- u$ t7 e3 @; i- Q& c- r" ?7 eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 A$ z5 o% c1 i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 M* G0 `2 j5 k/ E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 G* C2 u5 ~" h( c# k
0x00, 0xFF); /* configure the clock for transmitter */) q4 ?8 T5 f- p+ ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 ?, c) W9 e& _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* I! e6 s" l+ |8 x, _. FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 a* O" k8 O6 H4 p: I/ ` n- b0x00, 0xFF);
& s r: D" i5 y+ n. m2 C% e, a/ F4 J9 Z; x; K- [, _1 p ^3 S1 m
/* Enable synchronization of RX and TX sections */
# A0 N, @$ J. ]. VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 ?- a/ e, q( RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# y' e! c* j5 {" q! t8 vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( B9 M3 Z% t- d' e, `; b( R
** Set the serializers, Currently only one serializer is set as
" d6 G( r5 c% b# f$ `& N** transmitter and one serializer as receiver.
- a5 |& f0 `) C8 k0 p! E*/$ x1 k$ P4 G! m0 N) k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# M/ C9 N3 x3 [- m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 |; N, Y) \' p1 C4 s
** Configure the McASP pins
/ f) r9 k/ F4 E: y( Y' C** Input - Frame Sync, Clock and Serializer Rx9 m: d1 m& s; U6 L6 U
** Output - Serializer Tx is connected to the input of the codec
" G; F7 m4 Z$ J5 u* }/ J8 E5 ^*/
3 H! T2 [- I9 Q1 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# `8 ^3 J# q! |) D! K6 x; }% e8 B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 @) o* W/ P0 {" u" CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 B+ m+ p8 F! l. I% @
| MCASP_PIN_ACLKX
# \% X1 h& q# w( C| MCASP_PIN_AHCLKX
! G6 B) s h. H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. V! q8 j: R& v4 L- DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, d% t% U- j( L! U" }& Q| MCASP_TX_CLKFAIL 2 }+ J; s( B/ r% P5 y" x
| MCASP_TX_SYNCERROR
! _+ d# x$ n# U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' E) j/ `0 G1 A9 _* p& v
| MCASP_RX_CLKFAIL6 F# Q d* C& N: ]! a: z
| MCASP_RX_SYNCERROR / _' g+ h, ]& k0 [) O# G5 W5 o/ }
| MCASP_RX_OVERRUN);0 v# l# \2 L* S; o$ m- F0 d! J
} static void I2SDataTxRxActivate(void)
5 `" h- @- H2 R/ ~{
( ~: x% w# d2 Z8 K; t2 R* ~/* Start the clocks */
$ p. L6 f. `( a$ j6 z# xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) G0 Y% L% Q, y% D; f8 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- x5 E) f+ H k4 [3 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' K/ X' o5 T# O+ c! W
EDMA3_TRIG_MODE_EVENT);8 M3 V% X& U6 `/ ]2 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# R( q O# I# D& J! P7 q& aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 @3 Y x: J; y' _8 c: O9 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 q4 c; i% D: [7 m6 R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 ]1 A$ G: Y# N+ x8 G0 E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% \ I- V4 ^+ M T" RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
t, i- \6 T0 ~# P' `2 jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 d( E. e* n9 @5 O7 s! ^. O A
}
5 L9 X; P: o! @. Z. N# ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 \8 n8 o0 V; a. z' t; O
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