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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 v* Z0 {6 s9 V) xinput mcasp_ahclkx,
3 a7 n* r8 n+ X3 X6 Q: X _; A- Uinput mcasp_aclkx,
: k5 j4 Y5 r/ E) m ?% Cinput axr0,
# Y1 ^7 x k7 w, k% Q* g
( Z% Y, J+ o' n5 J& loutput mcasp_afsr,+ ^# w5 Y! ^6 B
output mcasp_ahclkr,
, N; z. q2 w `- e% M. soutput mcasp_aclkr,9 W. O+ k- T: M- i$ {* s9 y
output axr1,, M/ F: p E1 R: y: H3 c2 O4 j; U* r
assign mcasp_afsr = mcasp_afsx;6 D! n2 o9 d* y& K' \* a
assign mcasp_aclkr = mcasp_aclkx;
: Z% e0 C$ r. l5 N: |assign mcasp_ahclkr = mcasp_ahclkx;0 l) Z/ P' K# K2 x Z7 N
assign axr1 = axr0;
d" k* R' @) J0 k; q
" I5 l- s; L$ X6 L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 C9 ^3 z9 a: ^( s
static void McASPI2SConfigure(void)
y; k/ ^2 G! V- J1 x2 L: G{
+ y |# I7 y9 E8 _& E- N+ m/ d. c% y- BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# {' i! A$ _% z: b( \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 s% @; ~7 `% V$ ~, y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& `: ]1 Q v4 dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' s7 c, `$ L, F( xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ R4 y V1 d$ H! I6 w; ?, `
MCASP_RX_MODE_DMA);6 S6 r0 F3 |/ O. l5 g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# e. g) m6 D3 W4 ]( E! BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ |* P5 P8 E/ L! _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, n- H6 z5 W2 c/ ^, F/ uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 S7 M w& b2 x$ B0 g8 OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % T7 C* h* [& C! N* R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. k; H( L/ b/ [. K! Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 f/ ^# \3 a! M0 K) @* s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- J' K! m' ^" o0 r9 N+ Y% WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 Z4 i: ?( |* @: k4 N: E
0x00, 0xFF); /* configure the clock for transmitter */# a8 y- y! O' V4 w. C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 d; J' D" ^$ z7 j9 _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + n5 ?; z- l) V9 P* O) J! p% E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 Y6 C1 M. S+ i; v
0x00, 0xFF);
) m b# e/ _; |9 I( y. L: F& A d2 T. W4 u F3 \
/* Enable synchronization of RX and TX sections */
' m! P) q8 R. R6 W: y/ m6 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 o0 j+ x4 @: _9 d; x6 }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: }$ r2 u, D1 Q3 M: NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, J. n5 a$ g1 P" l* q** Set the serializers, Currently only one serializer is set as
/ G! |" Z/ o: I$ y" U P: D** transmitter and one serializer as receiver.5 M3 E7 p5 U; ~$ Y
*/1 I4 U: z# E" G- F$ Y2 g/ Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ m H; @. p n0 R" J3 F3 MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 m# J6 Q1 o+ w& F- ^
** Configure the McASP pins . y: j! {) C }0 c. H7 u, w2 j
** Input - Frame Sync, Clock and Serializer Rx
! \, c2 N% [8 | x0 ]! g9 P** Output - Serializer Tx is connected to the input of the codec 0 U/ l) S. X' |. e# |9 z
*/
% d- j* {8 l7 }, a# T! zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- |" _6 N4 h( F) wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 v9 ?. o0 R' k' l BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 S3 P, D+ } o2 H7 x2 `
| MCASP_PIN_ACLKX
& \5 l/ V! Y0 W/ L" _/ m) M| MCASP_PIN_AHCLKX' L* E7 f3 @6 }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ p4 d& m3 `9 a1 q; [4 h+ D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( h0 K" @4 H* X: N& {7 Y
| MCASP_TX_CLKFAIL
: i6 O1 X: U( C2 r1 i R3 b2 p| MCASP_TX_SYNCERROR! F2 ]8 l% \* O/ [8 o' s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) b' L! I% C1 x, m+ h! ^4 ?1 J& n
| MCASP_RX_CLKFAIL
7 W0 r, I# d: D# i- V3 T| MCASP_RX_SYNCERROR 8 h8 ~# q3 |8 s
| MCASP_RX_OVERRUN);3 m4 c+ g. {4 q; h- ]
} static void I2SDataTxRxActivate(void)
. g5 u3 s5 z& b: v9 z& u{( ] V4 ?/ U. N' l+ n5 T
/* Start the clocks */
2 |, v; M; d' c( `* I, TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 `6 Q; o- e# EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 u+ `5 K. E6 m7 b7 {6 t# J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 v7 z2 U* L8 m8 |+ n* l
EDMA3_TRIG_MODE_EVENT);
) t k8 ^. ^) n9 T8 A5 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; u$ ^, [2 q5 ]+ F' y7 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 n0 u- G$ W7 F- L; g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 ~0 J9 \5 I; u5 h, k1 Y$ J! ?1 D4 _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" P/ _7 {9 g& K+ Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. |2 q* w$ h% |( f7 o, H( R( W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( _7 u& d7 d! D5 U' w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! }, _) [, v/ ]& }9 L8 S& a
}
# ^2 b+ D/ F3 F. h: O& R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 q5 g4 w4 B$ \/ b1 q2 M
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