|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 z! ?% w3 R6 O. R8 Y% P- einput mcasp_ahclkx,
0 b, D3 `# P( @8 c: b* j1 sinput mcasp_aclkx,; E) D+ @3 V" M% i6 Y$ N
input axr0,
$ h% @! t ], o- ?$ A( P! F! Y) e9 t* ]5 Q, e: a- j
output mcasp_afsr,0 T1 o# O' H7 N: x w
output mcasp_ahclkr, U4 P& J; D) ^# C2 a- v
output mcasp_aclkr,7 t2 n: ]( u; m% x( f
output axr1,
# `5 X# }3 e* r assign mcasp_afsr = mcasp_afsx;
: J: M. B# E8 j2 G) c; y% oassign mcasp_aclkr = mcasp_aclkx;
& b: f( W3 `/ s g! C" Nassign mcasp_ahclkr = mcasp_ahclkx;
- t" E$ U1 k5 T8 Aassign axr1 = axr0;
: X7 ]6 q* x+ D9 D3 W/ D; c" \: [( a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 z0 ~4 ?9 ]8 K4 \9 \# P
static void McASPI2SConfigure(void)4 E' \- @: q' W* ]1 u' N
{
- T6 Z1 o3 o3 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ D" y; J8 U, i7 s% y1 WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' b+ S( e3 d% y6 ^+ R( LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 W; [. n k+ j5 p( n/ u1 pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! Z1 u. p3 b H1 o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 C" a& q5 ?# t7 p
MCASP_RX_MODE_DMA);3 d( v" {) H/ C2 @! z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: u/ y C4 D; X8 D: C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* x( e% f- v0 j [# @. z5 Z$ Z1 _" m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
g) p- n# h# S! I3 [; iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: Q( P$ v6 z6 t: J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : K; q7 d3 L1 q8 |1 x+ Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' a( r; {; ? @+ o& \( ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) k$ Z! e, ?# o5 s% t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! S% S0 u7 V& H- o% O, V T6 XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ M6 }" I6 ~3 L0 Y4 U1 f
0x00, 0xFF); /* configure the clock for transmitter */
3 G6 q2 K" {' x) p) t: c6 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ [ ~) }6 d7 |" L8 J3 A3 j$ N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " P% B7 n( f% m7 r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: _3 e9 C' E6 ~2 x( x. M& @0x00, 0xFF);
1 q4 _) V# o- Z/ X0 a5 _5 K* e; M5 O8 @8 z- `; F- h$ Y
/* Enable synchronization of RX and TX sections */ ; I( v- j9 h# s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 c0 I, i+ Q- k5 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. p: H9 Y% q; D5 XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** e- P: E& e5 A5 Z
** Set the serializers, Currently only one serializer is set as5 o* Y! }, g) A8 X7 @: J7 y
** transmitter and one serializer as receiver.
$ i1 V4 Z+ y. V9 h( \) E! U" M*/: o. u0 k: ?2 A! W3 S3 N- K% [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 M$ b5 P* R$ U( {+ j+ k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 @+ ?" V2 @. ?( z4 n N9 p+ @** Configure the McASP pins ; k6 D8 t# [3 t/ c
** Input - Frame Sync, Clock and Serializer Rx* Z( b9 o. {& ]+ B% g8 {7 x7 w9 y
** Output - Serializer Tx is connected to the input of the codec - h: W0 Y3 g: t U1 A! T* Z0 H1 K
*/
% {! {( q3 T( @* {* `/ EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ a+ B. C; }! I4 s# t+ _' {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 t3 U7 n" l& j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- I8 ~/ x+ d7 H5 d+ m) c/ v6 Y| MCASP_PIN_ACLKX
: h" n( g. O5 |0 m2 B$ Y3 X) G| MCASP_PIN_AHCLKX
" D' x4 x! D1 f) Q6 }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& R# {% _9 i% F% a0 m! C5 ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 @$ [% A5 Z6 D( Q9 i9 J* r
| MCASP_TX_CLKFAIL ; V0 ~; Q0 P1 g5 U% e# A
| MCASP_TX_SYNCERROR
+ F3 |$ U8 C6 O r3 M0 y% I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
~6 ]9 T$ Q0 e0 E; B! D| MCASP_RX_CLKFAIL) o/ |) G+ }, ]
| MCASP_RX_SYNCERROR " W( B L+ i X: v( U
| MCASP_RX_OVERRUN);
7 ^8 J# N: f, z4 w7 |} static void I2SDataTxRxActivate(void)
+ o2 n9 T$ u( Y: H6 P0 p{
, E+ L' U3 o* r. ]( G2 z/* Start the clocks */6 H- A+ J) ^1 @7 k4 ]- q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, m) c3 e" l& r! K8 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' O( w M1 _: d+ X* ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ o( N- V" E2 u. P) Q
EDMA3_TRIG_MODE_EVENT);, V0 {6 M6 f! }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 g# n9 ?+ H( N4 Z4 n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 _2 N" M B6 Y# k `, I$ c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, r" R2 f- w7 c. G' U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 j9 \7 D7 Y. h/ q5 U! J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' k; v: S: M9 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: q+ U! c1 t8 D2 R k% n EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) O D- \; y8 \}
% [, P, n# h+ K! P* m9 J, c, E/ a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
: w( c L A, r2 W! ^' | |