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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 u. i3 s$ q" O$ o) E) @, f+ H% Qinput mcasp_ahclkx,8 z- l1 q, g: C. Z! p1 x8 p* r
input mcasp_aclkx,- N7 p8 L+ Z2 p' x6 O. U. U
input axr0,- T7 y, b- j/ L% I+ p
9 f$ |1 Q9 C0 Q; L& O2 \7 Q
output mcasp_afsr,
, o8 \) ~ G' v4 F( K* J7 aoutput mcasp_ahclkr,
r/ d- T9 O7 P7 f. W3 Eoutput mcasp_aclkr,
* z3 B7 g% N/ V# P* ^5 M2 Goutput axr1,7 I2 [3 k c% _( D& K1 H
assign mcasp_afsr = mcasp_afsx;9 _! L+ {+ N) S2 h0 N# a8 Q4 A
assign mcasp_aclkr = mcasp_aclkx;
2 w9 V0 H R7 e, ^3 |% y" N' m) Zassign mcasp_ahclkr = mcasp_ahclkx;- H8 s) ]7 S7 ?0 H& m
assign axr1 = axr0; 9 j$ _$ a5 t; T0 A) h" M
& t, S$ q! R1 e5 E4 s7 [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& c5 w0 M6 R# ^5 tstatic void McASPI2SConfigure(void)
' p8 M% D. V7 n f4 u{! A' u$ H4 m2 p: e2 a3 A+ M( D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 I2 I7 M3 ]& Q% D6 D1 q4 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" Z) U& T: n# S! H8 l; m' O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: g v0 T3 C3 _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) L$ N8 X7 o0 Z# ~0 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, W# u. u" ~2 }MCASP_RX_MODE_DMA);! D% V6 K. P8 A: k5 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 ]5 I( n& G+ @$ L! k$ W5 k, h. I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. I6 w; a, C7 e, j2 q- WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' \; {% C+ @% |6 W5 x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% e' n0 r: L, C$ d& G* l- oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- p X% j/ }8 {& M, Z7 [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# T, p' j$ z& `" t+ wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- X, K2 I4 j5 C' A+ i$ Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ }* A M& w/ B' n: PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 m% C+ D( m& G2 x/ g0x00, 0xFF); /* configure the clock for transmitter */
9 r* a; I) c8 ~9 b1 r9 @$ UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; G- t X, t# r; t1 }# sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; C- t. _. S" I0 P$ `: ]- @( `1 {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; ^8 k) I2 k( O# v- p, X0 ~8 @) o
0x00, 0xFF);. V+ e; Y! M2 Q$ n
: f; V8 U/ ]. _2 d/* Enable synchronization of RX and TX sections */ 8 ]7 G' X3 f6 a6 q: x$ C& K2 X* N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 [& m) N- d: Z- Y$ W/ V8 P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, O* F- C) x9 U% {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- G. r% ]1 U' Y7 D1 ?! e** Set the serializers, Currently only one serializer is set as
1 l6 T- a* u/ E** transmitter and one serializer as receiver.
- z# c2 f J/ l*/ v: J) ^3 q, \/ r6 F; K) o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- f5 E2 K# K) H1 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 C+ z* Q& E9 G9 x
** Configure the McASP pins / Q8 V' h" y- x7 F
** Input - Frame Sync, Clock and Serializer Rx
- ^. Q) w( J' V3 L7 {( R** Output - Serializer Tx is connected to the input of the codec $ L- s1 i! ~9 p( R ^2 n9 ]
*/
7 q7 L' b, s& j9 T' B" [3 l- yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) g3 F; k3 S+ r/ `/ n! n) O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! n3 m( g# y$ i$ t/ E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 f& P: W% w1 y
| MCASP_PIN_ACLKX7 y/ j. o" n" x5 H! P: _
| MCASP_PIN_AHCLKX
- T) m2 u5 O+ B% g% d# ]( \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ K4 _$ q& V0 p# R2 LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( q% p8 e3 L9 `# u) C8 l! K) e) z2 [
| MCASP_TX_CLKFAIL ! f2 ]( G6 y" |) [1 j* m
| MCASP_TX_SYNCERROR& M/ V6 @& B0 R A4 |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 U+ y% b6 f. ]9 f5 V| MCASP_RX_CLKFAIL$ P/ H* p+ E% G% W* _
| MCASP_RX_SYNCERROR 0 j& c& ^& U9 v6 i( ^3 c* \
| MCASP_RX_OVERRUN);
- R3 y, K# [; }8 E6 k} static void I2SDataTxRxActivate(void)
( B9 D, P U! t{
/ C7 i: N1 K4 z1 B! `/* Start the clocks */5 f& L$ Z$ Q1 }& t7 s7 P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 ]2 s4 B9 p @3 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) Y+ L& }# F% Y& b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& b6 ?5 s% g0 {1 b ~/ A
EDMA3_TRIG_MODE_EVENT);
' \' O/ {" G2 D) V' xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # L, I$ g7 q9 N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; }/ u9 k( ^- }& I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' F8 ~9 ?+ ]: I I% D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! C& \- m4 _6 T: O& C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, E4 \/ V& M: ~( g! I/ m- Z4 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' q x4 _6 m9 {+ hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 R ^# [5 T; w: A4 s
}
/ j5 t7 u& m! P& V/ B& p- E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 B; ` o' K1 `
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