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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," h; u# C/ W) a' `! f
input mcasp_ahclkx,
' d7 b% D3 ?, Finput mcasp_aclkx,( z$ ?2 V8 C* w8 _# \% V* u
input axr0," z n. k; }+ W
6 r) |5 Q& |% h& u$ Toutput mcasp_afsr,: d7 }/ _6 _& F7 B) D v4 e
output mcasp_ahclkr,
# U# \. ]. y" [" M6 h: L u) Q5 s Boutput mcasp_aclkr,& S; U! Z- j' {* Z2 j' ~
output axr1,' l0 c) I. r* g$ d1 @1 x) Z
assign mcasp_afsr = mcasp_afsx;4 G7 @* n* Z. L' d6 z2 @: A2 T. o
assign mcasp_aclkr = mcasp_aclkx;7 p2 a: v+ z( G: ?/ T* M
assign mcasp_ahclkr = mcasp_ahclkx;5 ]; W- X2 x* F3 }& v+ x- D
assign axr1 = axr0; ]' F# G# X- u9 [
* N0 p7 ^& J1 c: |$ E4 u# ?8 `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , t8 T# U0 b4 }
static void McASPI2SConfigure(void)% _! Y6 ^& o1 S1 ^ c( R8 ]
{
. L5 t! Q3 E sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: X* e- e& K, n5 WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- T1 P; J: ^( ]# e' s6 ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); ~- k p1 q+ h- C' M( g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. I: F- D# b: t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. x: W1 c% `6 R
MCASP_RX_MODE_DMA);
% J7 d# ^: z4 o' `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 r+ ?0 \# D5 I) gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# J( i# c7 ~" u9 U! {1 B/ S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % _: s* P- d3 O/ b. p, B3 I* k, ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- f1 k* ^5 _7 E' O2 Z7 T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 b4 O7 v' p& w; @7 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' U6 Q1 R: ~7 I) E) [* z$ q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% y) u6 C- V# f3 c+ O7 C: e) ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 {5 R( h2 `, q: G3 @) u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 j! N+ L3 _4 I3 H5 d/ x
0x00, 0xFF); /* configure the clock for transmitter */
; K2 A, z. j( T4 O! @& cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 C* u! j; v& R" t" qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 B+ G# [" a5 z ~( y7 V0 K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% {* j5 j) q" w1 m0 E
0x00, 0xFF);: x6 C: }3 I7 f9 m+ F3 W8 ~
f$ a. m# c0 g* t/* Enable synchronization of RX and TX sections */
# |- O$ `& y( RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 ~: P. p4 \' a2 Q$ B* j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% T8 p( m( b+ m$ ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ p4 P& e+ `: Z y# d% T9 `. w** Set the serializers, Currently only one serializer is set as
' t' B, d) v5 H& Z- N** transmitter and one serializer as receiver.
8 }) o/ O- [0 O! a*/
) M1 J& C |5 \# v/ CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# {7 s4 {: e$ `1 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 G7 i& H+ F/ P/ c! y, z V: A
** Configure the McASP pins " ]' v2 k i( i& X
** Input - Frame Sync, Clock and Serializer Rx) E7 a& d4 ?0 B2 t3 Q
** Output - Serializer Tx is connected to the input of the codec : v; l5 I5 D' J9 B7 W" E7 d
*/! b- a& z, }. G$ K% I# P3 y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 Z& {; Q f. r9 M+ _4 V5 {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& A) R5 Q) O1 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( X! `2 H1 c' \5 o9 F6 ?( `| MCASP_PIN_ACLKX
- ?6 R$ {6 H1 ~! i, j8 u| MCASP_PIN_AHCLKX1 P# [4 c4 m& i" {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 x/ U" Z4 y2 ], C& Y- c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 p) G9 \/ \; \+ I3 i
| MCASP_TX_CLKFAIL
& R5 s. n9 j4 P3 c| MCASP_TX_SYNCERROR
" t% G4 \" P2 p. B4 Z3 O" v0 f$ {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ D% H1 ^. S% t# c: E- D+ l+ l- W2 X| MCASP_RX_CLKFAIL4 _, K; c; _( |0 L
| MCASP_RX_SYNCERROR - |* `$ a9 ]/ ~" U5 S% M
| MCASP_RX_OVERRUN);
" c8 m" b; t1 j; _} static void I2SDataTxRxActivate(void)
2 R; M6 v! v$ @1 f: q: X6 ]% _{" n0 c, l3 U; ~+ _7 F) q$ J! _# A
/* Start the clocks */
! O4 P; {' k. s6 ]: p( GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 u0 Z1 v* F8 l/ w8 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 T1 O- F. @0 P0 }$ q. jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; g" v( M/ l) z% h7 ZEDMA3_TRIG_MODE_EVENT);' l; V7 C' e, Y) x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' B1 x1 Y7 u/ h* ~3 K; n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( y* z8 {, ^$ l, W9 ?1 X% yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* \! P, r( a& B/ e8 `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 {. _4 D- E! N* i! Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& h0 {( L o& F% c4 X% _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 e$ d/ }; \# `& W, _" ]4 v: cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ b# w6 R8 m5 o" a
}
5 p1 H. y+ @7 T" L; t, Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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