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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 ^1 V3 F8 {" `5 g5 ainput mcasp_ahclkx,% V3 M0 {5 C9 `8 D5 }) S
input mcasp_aclkx, [( r( o, k6 P- T
input axr0,
- c6 R: O* W3 H' @/ L
5 I9 s+ ]& G( A7 c1 Y9 Aoutput mcasp_afsr,4 z1 c; C. ?; V% ]1 ]) {+ K/ A
output mcasp_ahclkr,9 W+ ^2 x* s7 `' t) m7 ?7 d, E
output mcasp_aclkr,
' r# p# @9 C, Poutput axr1,
, L! V8 z# ~3 x& ^& t E4 y: P assign mcasp_afsr = mcasp_afsx;" K2 X/ R; s* W. G$ s8 p
assign mcasp_aclkr = mcasp_aclkx;
+ K' U: _' v$ {+ J; X1 U7 P' f# ?. nassign mcasp_ahclkr = mcasp_ahclkx;
& [' s; }* r: X6 v- E8 Gassign axr1 = axr0; 7 l4 j2 @8 i: B: N$ n4 M
% n8 V; k8 \! c( m4 F, |2 s" F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 y3 S* ?5 b( _; ~
static void McASPI2SConfigure(void) j! C& S {) D
{* m6 Z# r8 V/ }$ o. L2 H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" @- t p2 h1 b) @, w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- E0 v( s: s2 v7 j' a& e }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( Y3 H* N; h' n( m6 w5 lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ D: f5 x8 b+ P7 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 W/ n) j% V7 y7 H3 O" K+ `MCASP_RX_MODE_DMA);* E9 w q$ V& w! B2 Q8 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! n/ a" p" X' O3 r; m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) f% {. r$ A) u; Z/ XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
\& x" E. J7 \' fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% Q! ~5 F' G6 v y {9 x. i# G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 ?/ n6 h9 K, q% ], V# ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! ]0 q8 e- I/ V: D( s! Z5 Z; eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 u: x5 Z$ G3 [7 j; V! T, u( M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 T* `9 ~! ]% a/ F: ^/ MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 S f6 k. M; {) k, ~( i, v0x00, 0xFF); /* configure the clock for transmitter */+ x+ _" `3 T- Y# u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); L" _) V7 ?8 {6 I0 U. y7 R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) H; t0 u) u" u1 |% K" W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 p9 w5 i0 }, I: I8 @9 [
0x00, 0xFF);& t. X, Q. L; Q* U7 a
# A3 X4 q+ l) _9 ?/ M j/* Enable synchronization of RX and TX sections */ 1 d, V* P8 m# U9 F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. e8 p& G; |9 n9 |& c8 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 \; k' G. h% C H5 g+ I# Q WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' B& z# V' t) ] d! D2 G+ f, [
** Set the serializers, Currently only one serializer is set as# k' I: Q9 c9 d$ D0 q
** transmitter and one serializer as receiver.: p( Z/ a C7 h1 R H F
*/
M. Q% c4 {% n2 y8 U3 D$ T, QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 P7 O8 b& a* T! T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- e0 ]4 b4 Q: _- g2 G$ o
** Configure the McASP pins 1 ^$ [, g5 [7 S9 k3 l
** Input - Frame Sync, Clock and Serializer Rx
+ e% w4 V0 ]' a( [$ [4 B** Output - Serializer Tx is connected to the input of the codec 6 R9 W+ K( h$ a/ a/ p* {
*/
, |2 D( }: x- AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ |* X) ]* L2 G1 k* H- RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& u0 k* k2 I7 J7 N& ^6 {+ I& d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 X2 l& Y7 O0 _3 [# d0 b. X7 w8 j| MCASP_PIN_ACLKX2 {; O8 D" Q7 j+ G' T2 X
| MCASP_PIN_AHCLKX
3 U. r/ u g8 R! V) \% y; N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* c. g* q0 l4 Z7 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - X- u& b: m7 A" N
| MCASP_TX_CLKFAIL
0 u0 p. b' [6 q8 L8 G# y) F0 i| MCASP_TX_SYNCERROR
3 Y0 w$ [3 m/ X; {9 E k8 I: j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 o; a: n: Y+ u* O
| MCASP_RX_CLKFAIL
- K2 v' D% r ^! p% W| MCASP_RX_SYNCERROR I( E: g* |- {5 X) l
| MCASP_RX_OVERRUN);
- J7 t8 z0 Q+ f8 R% U* j& G} static void I2SDataTxRxActivate(void)+ |" G3 X, ?6 ]+ h8 I% j
{/ ]2 b1 d E7 Y/ h
/* Start the clocks */( j, L" _, T. k( M' h% }' X: U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ r S2 Y" O7 q# k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( Q$ d7 \) Q5 f; i* m" W) |" h, A2 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 L! M5 Y% P6 L+ T0 E
EDMA3_TRIG_MODE_EVENT);; u9 V0 `# m! e' \/ [$ x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . ^! Y/ e: F B* x7 b ~, a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' J& k9 c- f( _' `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* A2 _* T1 B% w( n Q1 X5 q& P! ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. K1 S+ a% h V7 }) i: t0 Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& q& o. C+ v' V- `8 v9 d8 E4 cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 B3 s# K: a/ F4 u2 a" q" C, X* ~4 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! ]. d& ]1 z0 c1 T}
; J$ `6 r5 J( e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) D ^% ]8 l( {5 s
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