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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 ^3 K7 k. q8 g3 u# l! G F
input mcasp_ahclkx,. l) y1 j; e; Z S! {4 @
input mcasp_aclkx,7 t2 _* V) w/ q
input axr0,; \0 I# q, o8 Z* y, ]6 d
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output mcasp_afsr,
% p& c+ I. L7 Q5 B. h" K# Z. Q @output mcasp_ahclkr,- S- h- N2 D- j) a
output mcasp_aclkr,
+ {. ?1 I+ t* T9 p- Joutput axr1,5 I" Q3 W" e/ D
assign mcasp_afsr = mcasp_afsx;/ m# l6 O6 k9 [8 ]! L8 J, t3 j
assign mcasp_aclkr = mcasp_aclkx;$ }# w; S0 G! x( @! Y' }" P
assign mcasp_ahclkr = mcasp_ahclkx;0 `3 C( k1 f0 b
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" v4 } }( k5 [9 zstatic void McASPI2SConfigure(void)
8 n" K7 I- R1 |* l{2 p4 h( y1 H5 O& ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; z! n2 |& Y1 w- u3 O. g4 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; y& O% X) j% t/ aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 e" m2 U. ]9 T6 _+ [2 I' G7 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 s/ G. C, G9 {+ k6 f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 K0 B; y Y' ]/ U# ^8 `/ wMCASP_RX_MODE_DMA);
, z* m3 Z4 l8 j1 e* CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 g! y/ g8 ?6 m. M" o) QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" i& l S4 M& T) Z6 I" ]' L/ a. R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * O& B8 P6 n' U4 Q1 Q1 l% d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 k, c* D5 \7 a, ?+ e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 v. J" w# W8 W! M: D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) T6 n' ]; R+ G; R1 c) pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 l+ d& i- {) \) S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 Y" l* @7 G8 ?8 M/ S+ n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) s! L1 k5 R7 s% V' n& P# I) b5 m0x00, 0xFF); /* configure the clock for transmitter */
# P1 A, D; z* ^# S/ m& y5 ]2 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 |3 k: i. S" e+ XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' f2 e- ?. y" f- cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 T4 J N5 a; q/ c/ x0x00, 0xFF);
' e( J0 f& j @8 j4 m4 T* | n! l8 T% Y
/* Enable synchronization of RX and TX sections */ 5 R. G6 o8 W* M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 G2 M3 ^& o" w5 G1 ^+ dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. w" @4 w0 `& j. rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 L2 K" D, G( D; g** Set the serializers, Currently only one serializer is set as
W& h& _! t( Y7 w8 R** transmitter and one serializer as receiver.
, _+ i }. j" [, l0 w*/
: Y. w" {& l$ f1 R, kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. R+ H. q+ t6 L6 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 i3 }& o. D1 ^5 k) V
** Configure the McASP pins
* `6 @% e0 u9 o4 \0 [8 Q2 c( j2 o** Input - Frame Sync, Clock and Serializer Rx
6 N" N- H8 Y3 G! y** Output - Serializer Tx is connected to the input of the codec & h+ y& P$ N0 K0 i$ Z
*/
2 z4 `0 ?2 E8 H4 A) ^$ tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 h: t1 }: e" X: |, ^# X8 }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 @( j8 I" Z7 U& i X" b" S+ _6 UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! u" z( P! T! U5 q| MCASP_PIN_ACLKX3 H5 K" W- I# X6 } q" Z% Q- b. k
| MCASP_PIN_AHCLKX
$ L& h" ]1 V+ {3 @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# {4 t+ x# A0 j b6 P3 YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 T1 y+ k/ \6 C1 B4 {5 t| MCASP_TX_CLKFAIL
( f6 E, K- a$ A| MCASP_TX_SYNCERROR `3 A8 i6 v9 T; {, ]7 n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& S: M, `) T4 E/ E& w8 ?| MCASP_RX_CLKFAIL
# ^* x3 O9 z. Q0 b* [| MCASP_RX_SYNCERROR
& O- g: Q* I0 F6 l2 v| MCASP_RX_OVERRUN);
; a! R) b o. o% @- d% ?) M. A} static void I2SDataTxRxActivate(void)
0 a& Y/ e7 k% p; o, z{
7 t) k, I9 }1 y/* Start the clocks */) |! {" q: V1 h7 P0 ~; [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" Z$ e9 ]. N$ t- b- f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- C* T4 x7 f; bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 C7 D) x0 Q/ o+ G( |' |; `- ZEDMA3_TRIG_MODE_EVENT);
% R: @2 W" F$ z( kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( `2 I: p0 _; w3 Q& s. G; dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. p( w" C! b- [* B% mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 o1 T$ J6 j: | b3 rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) ~0 @+ x. `! v9 e. q4 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 S( t0 \- c" R; EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 |. O2 ]$ @$ y! F e0 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: \ U" _4 m) ~( C* e}
/ b) ~+ c" w; \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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