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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) T: N3 ]2 R' R, J$ @# Y: K6 E' z4 m
input mcasp_ahclkx,
6 p" M" N* O/ j1 w1 a Q3 zinput mcasp_aclkx,
1 Y$ C# z+ M( s( k3 [9 @input axr0,2 O1 B, A. d# C; a3 x
# R) ^, d9 x& c; A8 M0 toutput mcasp_afsr,
( W! {( D: Z. c' p0 Aoutput mcasp_ahclkr,
2 ?- n9 _3 ^0 ]* O+ Poutput mcasp_aclkr,% \9 R3 Z$ f. L: u( ]4 V
output axr1, ?4 G5 t* t. t5 ?9 g
assign mcasp_afsr = mcasp_afsx;
& j* w' A& x# Vassign mcasp_aclkr = mcasp_aclkx;
9 M7 @8 ?0 w/ I- Sassign mcasp_ahclkr = mcasp_ahclkx;
$ f3 ?8 F! t: r- ?; Q, w8 j# Vassign axr1 = axr0; 8 Y( d7 k5 F0 ^1 o! I
/ x6 R5 T" t6 {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 J6 i, ?0 d9 M$ T& V0 A1 |3 v- y
static void McASPI2SConfigure(void)
; q. ~( E' p3 j( e j{1 z+ I4 _6 m+ [- B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- v) F5 L) h; U j0 B/ S0 sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. v9 P& f0 _/ I( f& I1 o% DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 j0 G& ^/ Z; q* d5 ?' rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! [ v Y# s! h6 B" _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 i# D6 k3 x" S9 c& T
MCASP_RX_MODE_DMA);6 M/ H) D# X: w1 \& V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, o8 \+ l- f3 `+ Q2 }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 v7 O9 I, {: K! r' aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 O5 o" Q7 Z5 U9 [$ o( k) q' U/ N' aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, E! W& ^2 e: ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % x* r, D8 Q' g/ R2 D: X2 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 X' C4 b7 ?. n+ N6 {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& z* ^0 R% u, f( bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ n6 r8 ?6 A$ K+ ?2 u8 ~* hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ ? n+ p7 j0 G, u, h, H+ U" J0x00, 0xFF); /* configure the clock for transmitter */
# F* t- D0 S l3 pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 o: w% W; `0 P! s) ]5 d9 bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 j S: A+ w7 Q/ T( i4 G3 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( i0 K1 s& P7 o. g1 L0x00, 0xFF);; L/ {0 ?3 \" _1 w6 ^3 k4 e/ j8 Z; X
, R2 R3 g* b8 X5 h4 z! @# L2 h" f' g
/* Enable synchronization of RX and TX sections */
) |6 m& H! N9 d! Q8 Q; aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 i" [( c( V* T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 A1 d1 j9 x+ [5 [0 N/ fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, F4 ]2 U( G" p, |/ U: r% ?+ U% G
** Set the serializers, Currently only one serializer is set as$ ?5 N2 S u/ l" r$ e
** transmitter and one serializer as receiver.
0 M, L5 ^* g7 i*/
5 }6 C% X1 @1 a# C. JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 h7 j# I, j" f2 [& `& e1 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ c; G' J& A% J3 E1 A
** Configure the McASP pins
: G* p- }( Z, L" q" I! f+ {% p: v** Input - Frame Sync, Clock and Serializer Rx( @# V* ? j! B/ g
** Output - Serializer Tx is connected to the input of the codec $ q( u1 ?- s8 _% R Y
*/1 { _, l; o9 A1 n$ V/ ~% Q: h( R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; }7 [9 ]* L& G" \3 cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 R; W6 [7 X! J2 n1 zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- m( B" q$ W% w$ X5 l. D| MCASP_PIN_ACLKX
! I# H* j; I) q: j% E( w! L- l| MCASP_PIN_AHCLKX
- F7 @% W0 f5 G( U& A6 Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& m: H4 K1 w9 e9 `3 Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' U4 f1 d, m' B ]! L: p) A# e' s
| MCASP_TX_CLKFAIL , Y9 z9 @! l! z8 L( D9 J
| MCASP_TX_SYNCERROR
/ j+ o, T7 Y3 _5 {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) r1 s8 |3 h c# M7 U! ]# ?| MCASP_RX_CLKFAIL
0 j$ u1 j. k; D0 S @| MCASP_RX_SYNCERROR 5 Z! J! q( c7 f9 z6 i7 w8 {; i
| MCASP_RX_OVERRUN);
. t/ G! k2 ?! i( |} static void I2SDataTxRxActivate(void), A7 p, D* l, A7 `8 Y
{
+ |% l$ n) k! p# K6 W% N/* Start the clocks */; }" m4 s1 H5 [; I/ l; }9 `/ M Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: c$ n4 Q! o9 _! H$ x: q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% b! b7 u1 N5 @9 w+ U0 T# wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 X, o3 ^4 Q7 Z' N5 q. L! o; h0 s, SEDMA3_TRIG_MODE_EVENT);
; J; B: }. z" U! y/ _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 @) U, C' S5 G" @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" y4 z2 e2 \: l1 _! x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! Y6 N4 d( Y h0 A1 z1 a E( e4 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 e3 f+ N" x y7 z2 Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: o1 J, S; B! `" B d4 M+ N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* e8 z) v5 W" ~& a& Q* r5 U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 _' z7 p. r# U} 6 ?3 Y: Q+ Q9 k8 S7 ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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