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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" {' \" ] ^0 l5 A2 S8 E* ^) _input mcasp_ahclkx,# _# a1 i+ L6 N; R( W r
input mcasp_aclkx,; s/ Y3 f3 N1 |/ P# S% O
input axr0,/ I e5 \' F) W* S
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output mcasp_afsr,# J7 o! w8 N. G# @$ Q$ c- { P
output mcasp_ahclkr,
2 w8 L' t* O1 `8 Koutput mcasp_aclkr,
( R2 t6 F0 K) `6 Qoutput axr1,
5 U7 x6 G0 [: n9 }: A- \ assign mcasp_afsr = mcasp_afsx;
* x7 \4 c6 N" F. }% ^1 fassign mcasp_aclkr = mcasp_aclkx;
, m5 |& B) k) \) w j: s$ ]assign mcasp_ahclkr = mcasp_ahclkx;; j8 W }2 ^5 E
assign axr1 = axr0; / V: G- b7 _! {% h( L, U2 x- d
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " |5 ?% l/ T. z8 z( \& I
static void McASPI2SConfigure(void)
1 {5 r e/ \( b& O% D2 v+ x0 r- f, ~3 g{
6 h5 f/ R& B3 V: AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& n8 R/ w/ C6 Y! C3 s! f) K6 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 p$ g" Q1 n3 @# O4 L% W6 Z. w ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 w5 L# M+ c2 R: ]( C0 m; ~8 j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! f* Q; a3 \0 z% d9 L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( D2 @# Z% H! FMCASP_RX_MODE_DMA);0 S0 Y, |1 c/ R# \4 |5 W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 U7 g* B& P9 U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" S3 E, ]8 z# b# X" { ?$ v2 a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 }" V7 |/ b! F$ i4 [! c# G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 h5 ]: ]5 s, R4 M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / }4 k2 O/ A" J, x+ z9 |5 W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ ~ v+ _: M4 E' O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 U5 q5 f e" z3 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 l6 }8 o+ h' _& S: S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 l& R9 U+ [8 X" T4 d
0x00, 0xFF); /* configure the clock for transmitter */' B1 V+ V& i& H' i3 e0 ]$ N6 L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- @. g4 F% z# @ y: w* F' }7 m8 yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ w6 D) ^0 Y9 _. o- ], }5 ~# c' `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( z6 T7 o3 V8 b; N
0x00, 0xFF);
4 ?( |0 c' [; z7 c& \
2 y# i* V: {- [/ U% f' D/* Enable synchronization of RX and TX sections */ 3 ` P. a: Q( z+ }. Z* L, o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. M( L( U% I( |% v. F1 l( Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. }' }( m: e ?2 mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, D+ ?3 ?1 H* R3 x7 G8 ~! |! c o
** Set the serializers, Currently only one serializer is set as ]6 }* a' I( S6 [) c& C( n9 k
** transmitter and one serializer as receiver.' o/ G, l3 R- y3 F
*/8 E% V Y& \. q u2 N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 i% M \1 {( P j5 m. J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: g# j) N7 T Z2 W( w( k6 L+ S5 `
** Configure the McASP pins
: J. t+ g. P% G** Input - Frame Sync, Clock and Serializer Rx
5 Z# O( K& F( T! _$ S* _** Output - Serializer Tx is connected to the input of the codec
+ F( {/ ~' W# A*/" g/ |) X0 W. i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! i ]! m b+ N* X5 c0 q8 {- W# {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 m; c3 \: ^0 i6 J' B3 oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ H! M) `! c! \1 \" ~
| MCASP_PIN_ACLKX
8 y, ?9 C- [4 A# i' R| MCASP_PIN_AHCLKX
) y* U. n+ r! _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 J* o+ U, _1 |3 T# y: H4 wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - u' h {/ a9 R/ P& H, {
| MCASP_TX_CLKFAIL
& Q: e1 h, K! \+ q/ |! ^| MCASP_TX_SYNCERROR
$ v) S% S6 G: O+ {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 v7 X6 P& i5 O8 n e
| MCASP_RX_CLKFAIL9 O3 l5 h- M9 r* k& I9 Y
| MCASP_RX_SYNCERROR
3 r$ l/ n/ z* l9 G- e) @8 H| MCASP_RX_OVERRUN);
5 z5 P! \+ k& C, x+ L} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
3 I" d& L* f% W4 N* CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 |( d) D" x3 W/ C7 A# OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: A1 r% @* ?: r' k, d% Y9 ~ A9 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% n; `, B3 Z* K8 j# x# r' ?" BEDMA3_TRIG_MODE_EVENT);
- e, G6 ~& h9 K; O2 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 f& C' D. O( W- y- p0 W! \+ u+ d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ _ @+ Q5 a9 |8 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" n+ s+ F4 ]& ?& ^1 b5 T2 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% v. h" Y: a# ?1 f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 [, P# Y* ]# u1 o& e% {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- F5 i. z$ u& N# Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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3 i; S, W7 {* f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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