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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 @$ u, U" q& y3 Y: v! q. linput mcasp_ahclkx,
, u; X, |$ h; p5 S$ ~5 {9 Oinput mcasp_aclkx,! s' b O# S$ I8 M
input axr0,9 m: i6 x0 N! J' U& {4 i" Z) H! P9 u6 t. r
, P3 M9 Q& F3 boutput mcasp_afsr,
, d$ @0 n. Y3 Qoutput mcasp_ahclkr," n2 D: ~& g' c# d5 G( i* l' S
output mcasp_aclkr,- `, p3 a$ q e# Y D) l
output axr1,
# D8 z9 C' e% A' e assign mcasp_afsr = mcasp_afsx;; I; B7 q- v1 H
assign mcasp_aclkr = mcasp_aclkx;
7 ~' j2 O' O% r; D: C; {assign mcasp_ahclkr = mcasp_ahclkx;) v5 L' q5 Q7 t" q, S' U( v
assign axr1 = axr0; , j: `- `( r# j% X6 u
' F w. | W- e) |" c5 a5 A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ N: g: S& O/ N" w- Pstatic void McASPI2SConfigure(void)2 f7 r, |: U) r) B, y0 C0 p% q
{
G* Z3 C6 z8 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ D$ C/ B; [; |) |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// n9 Y1 J6 h6 B- I1 p1 t3 }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- V. Y9 y& L4 L$ d( l, Y- X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* b( w. O' P Z& A! d6 w9 S' m5 z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( m) d0 ?6 i- ]0 e$ a* hMCASP_RX_MODE_DMA);* n# T6 d1 O. D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 l5 w( r' D6 L. _( J3 N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 e# y ~1 w% M) i5 k' L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, V1 N! B/ ?, sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ b: `& A; N! [" c; { O# r+ i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, l2 F9 c6 K$ l# q- hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ q8 Q, ], i" b: x- ~: ]+ G7 `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 m' I; t6 o' K( K" J8 f; X5 qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 F" F/ d2 A }/ H4 I1 V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 O" H1 m2 u) o$ p. [
0x00, 0xFF); /* configure the clock for transmitter */# U( c! w0 W- l& @9 I. [" n: ?1 x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 V) _( X1 Y4 {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' n* X. q/ [5 R* B, C3 [( [" a/ c* ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 g! ~8 Z( E4 O0 l( k, ]
0x00, 0xFF);4 M3 z8 R$ P* v D6 Q
' n. ]2 z) I: z1 c
/* Enable synchronization of RX and TX sections */
! \/ M1 E( A( y& \- }7 ~, rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" j9 E) V7 y" Y& U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 p j: {" ?: p' TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 S/ g1 B% V* \- a8 F! W8 D' v
** Set the serializers, Currently only one serializer is set as
5 b. ]1 l$ X4 h( { l# q: O** transmitter and one serializer as receiver.
7 Q$ d3 k; J9 {! }*/
$ j, a* E2 `" B/ G6 y# HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 ^3 [/ B9 Q# I1 s# H6 ]- F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' d5 h- n8 K6 t" g** Configure the McASP pins
8 v; K3 h8 [7 Q9 o** Input - Frame Sync, Clock and Serializer Rx
; |4 b1 i0 _, b8 c, ^** Output - Serializer Tx is connected to the input of the codec 4 i C+ p( r9 K) F2 O: r
*/2 j2 Y1 i+ L, Z/ x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ R3 X$ \6 U" ^' @- BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" u, j0 D& R( s0 j; [; x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ s) ]- C2 `5 H& N2 R| MCASP_PIN_ACLKX$ _) V' E) s! W: u# Z# k5 `7 g7 C
| MCASP_PIN_AHCLKX
5 ~5 ^* e+ P1 p/ ~( n/ J: t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( T* k7 y* w w/ B. m/ R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; R# _* @% x! n3 S w8 C5 `| MCASP_TX_CLKFAIL $ E0 C' ]% ]: }
| MCASP_TX_SYNCERROR
3 j- u4 Z* ^6 B! v+ o- V5 V, v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, z5 o: ?3 h: o| MCASP_RX_CLKFAIL
) T( z+ g+ G7 C. j. p| MCASP_RX_SYNCERROR & ~; Q+ U' `5 a# a* Y; n: N, U g
| MCASP_RX_OVERRUN);! c3 U b: w; d( m
} static void I2SDataTxRxActivate(void)+ h6 C; o6 b3 o9 j4 P
{, _, N1 V3 }* h' |& b7 U
/* Start the clocks */& u: W) c; E$ T* b3 B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* F" s* q) w8 B* A7 v# |% i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; B& h9 T) P, D/ s$ N3 Z7 e" t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ Z- L. m, H2 Y. N0 FEDMA3_TRIG_MODE_EVENT);
7 f# P, i% R1 U' z( x# OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
U: i y& m( y; k! a4 ^% hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ ?! J5 K8 k# x: wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 R' Z* {$ A! v4 o ?6 h3 kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# A# S p' w4 E% k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; O$ n% W9 c4 V- a4 j2 v& R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ Z- n- Z( b' i5 }) ?- B2 DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; s9 Q5 {( ?" L! _' T% w} % S3 K7 t% Z: g- P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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