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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 Z. n. e L8 d2 x8 Jinput mcasp_ahclkx,
+ V3 z, f" K- ]3 U% ?6 V# c; Q3 A. Kinput mcasp_aclkx,
; ~& K+ L) O, \3 m4 binput axr0,9 A+ f; q2 H+ g8 K) m/ T
2 H K2 C. t1 g7 B$ }output mcasp_afsr,/ _- v) S6 ?# x& k' Q# [
output mcasp_ahclkr,
/ k0 a5 l& C0 F/ F. Joutput mcasp_aclkr,
8 f3 r+ |' c k# p; {) o, y: }% G/ Zoutput axr1,
2 {9 i- W- {$ ?6 c8 Q assign mcasp_afsr = mcasp_afsx;% y& { R& i5 e
assign mcasp_aclkr = mcasp_aclkx;4 w5 S8 H* d+ o' l! |
assign mcasp_ahclkr = mcasp_ahclkx;
! _3 r* ]0 f& n$ A) s p8 v/ Gassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 a3 V: w- d% Q, ]0 _6 K, Z8 G
static void McASPI2SConfigure(void)% Y; ]) H3 h. [6 j2 t* C! G
{
; W. D8 Z, k/ w# u& xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* v: u4 R6 K! k( i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) }" L# O' K9 L& A4 y( H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; i3 L. A- G' X! S, Z8 NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) u% S- z% X: \' J1 Z1 vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- o; b; l- a$ g' t; U/ s6 y) C0 ^MCASP_RX_MODE_DMA);
0 v8 A, ~- C( g- z3 {3 mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ m: O0 _) v' N' x" [& A5 ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# B5 j$ h! O) B% w, d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # @. F( l/ _* h7 {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! O* \" T: f( iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : P7 K" n1 b. S6 d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- @( @2 g9 R) w. b- C) k4 pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 M$ q0 ~8 y: W# A3 P9 f6 E& Q# J3 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 V* U" O k9 g4 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 I3 C, U9 I$ b+ _' t0 i* j0x00, 0xFF); /* configure the clock for transmitter */
8 H" V t* a1 _4 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" N6 s7 n5 Y. m# B6 {: ^0 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# e( ~1 V( U- W7 k/ _2 `9 gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 }5 A& W& y* q7 g% V
0x00, 0xFF);) E9 c9 J. I3 q$ v
* L# U$ S o2 Y/ f+ }' r- F) V/* Enable synchronization of RX and TX sections */ 2 L( K. {- |. e) j9 U6 M8 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ D: ~/ m; o. BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& `% K: _1 O6 Q3 H4 w; W# nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; Z9 T1 L' D3 Q, \2 G$ B% T, y
** Set the serializers, Currently only one serializer is set as" l; J7 ~- @2 [6 C' x" z
** transmitter and one serializer as receiver.
; a0 f7 f2 I- H7 Y8 m*/$ K* m0 y* d, n) L3 p3 m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 ~5 S' k6 X* A$ g: L+ FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ }9 Y. e. Q* I7 k+ t7 y1 @** Configure the McASP pins
/ p9 {. }' M' l' p2 n6 v** Input - Frame Sync, Clock and Serializer Rx& n: X. z5 P: Q4 \7 u% I
** Output - Serializer Tx is connected to the input of the codec * S3 _ P8 X, K% I9 B+ g
*/
" @( W) |" c# \3 I. CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' q% y8 Z) V: d1 M% G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 _; W$ y( a; s! ~* fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 E% b, D! r+ k7 H7 T( Q- M7 x
| MCASP_PIN_ACLKX1 y M1 z0 o; D0 k2 {
| MCASP_PIN_AHCLKX
4 C6 O1 \6 I& y, p# u* u1 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: T- q2 J( i6 t' H- s9 c" l$ tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 r7 y5 ]# p% i: E( H4 a| MCASP_TX_CLKFAIL
6 P6 e* s S+ q) U) C| MCASP_TX_SYNCERROR. s% B' m. `: x. z# {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 \4 ]8 c; A# x8 S* k$ || MCASP_RX_CLKFAIL
- A$ v6 W; c1 v3 J. ~" s| MCASP_RX_SYNCERROR
/ L3 x) B9 b9 u+ e& S| MCASP_RX_OVERRUN);9 N( a& ]7 P; S5 a1 W0 e7 Z8 f
} static void I2SDataTxRxActivate(void)
: s( H' X# E7 K9 B3 w5 V$ L$ ?{& F) B8 }: l" c$ S4 x2 V
/* Start the clocks */
- q& f2 N4 E4 q E; q' U9 jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 G( V- P: g+ I2 W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* _4 A3 K) T5 x7 O3 _* i5 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& A6 E5 f0 D5 h" y4 F4 J
EDMA3_TRIG_MODE_EVENT);
8 v! c- P+ Q3 z( a1 _8 |2 ?7 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % _8 _3 | Q! |. [. e3 A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 g5 G! X" `7 ^, O2 K \" X( Z1 e" aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 h) X6 @1 J/ J' F: YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 L; \# g% @# c s; Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) d' ?, V! q v6 `! sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. h! e) x0 z, N4 ~1 a8 oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" I5 a* {, x; g& C* ] d; _* i$ P- Z
}
& P w) `% X% b, y" x% V" d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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