MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
) d- R  `2 d  P4 C2 O6 F+ E  Linput axr0,
, b8 N  N' Y! B4 v" o
$ k! Z& B* Y' a5 m7 Y8 H2 o1 B& w/ soutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
" z  R3 R) Z9 @6 I* F) ^, m* Eoutput axr1,
7 N: g4 h8 S! t. C: ^3 e1 y# t

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

; u$ _6 g3 p3 T9 N: ?2 g

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
1 u! W! ^6 f: W& {$ _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, g6 H% k4 Z$ L# @( K2 FMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
) h) V% }; z! Y2 p) RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ~$ O6 a0 ~7 l0 _* B5 |2 pMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 }/ ~" |* n6 ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
  z1 w6 u6 s" X# @$ WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
+ m2 e8 h/ a% zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 O- K3 E9 }+ o1 l" T7 {6 k7 {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& ]' m) J7 F7 `' \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& K: `6 t2 @, V  D# |6 R) w0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 W1 i& ^% p, N, }- K; E6 L. {6 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ d" Z6 g3 ?; N$ @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
7 `$ _. K* L/ F/ }*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. R; ^- m* k* l" dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
  I% S# H9 {. w, M3 }: [0 L3 F- _** Input - Frame Sync, Clock and Serializer Rx
) p  P) l0 V5 |2 m8 X( p, @/ D** Output - Serializer Tx is connected to the input of the codec
3 |1 L) _- Y/ @# o5 t/ J0 x) n*/
+ `& x2 _4 r2 K! YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 Z  w7 Y9 R6 c0 v# bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 P. d( M; c9 y; [9 E$ W" P| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
0 X+ g' x. V- r6 |, Z" l' k4 Q$ T2 M| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 n. }: N6 Y4 E! Y| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
; A3 Y7 Y3 q! N" D2 W}

static void I2SDataTxRxActivate(void)
3 C% v% k4 ~" v0 n{
/* Start the clocks */
! K' I$ r0 [' VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& p) G! K+ e4 S9 \" eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 x( e: ]( Z( y* Q6 AEDMA3_TRIG_MODE_EVENT);
& e5 M# ?/ \5 n1 t4 w, X  V% m, {& qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
  n- H2 D# w3 b* B) [1 GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
5 q7 d& f  x0 y: u2 h; f0 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
$ W& ]2 s$ V+ Y/ K8 cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; I$ q/ o- F- A4 x: V3 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 p6 I) P9 v# h2 T  D}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.