|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 p( u: |- z4 r; M+ e2 G: Z5 finput mcasp_ahclkx,' c6 k6 e+ d3 F" Z1 D
input mcasp_aclkx,
$ x4 _( o9 o1 r9 L: Oinput axr0,. Q& C1 f: {6 _7 ?: O9 k
, F2 T$ x# V5 P: w
output mcasp_afsr,7 u& ^' ?' T- Z
output mcasp_ahclkr,
" ^( d* J b$ m3 i6 b* Routput mcasp_aclkr,
4 {7 e' h* O, G8 y, Boutput axr1, f( E5 Z4 I3 o0 Y6 ^
assign mcasp_afsr = mcasp_afsx;% Q7 u: J2 q M; w
assign mcasp_aclkr = mcasp_aclkx;
" Y- G% g/ w, }! [6 Y; a$ fassign mcasp_ahclkr = mcasp_ahclkx;! `9 Y8 v: M+ L3 G* t
assign axr1 = axr0;
$ n* s2 D( c& i- @5 d2 i1 y$ T% `! ^, ` o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 @, G, i- h' j+ Y0 I& h& d$ fstatic void McASPI2SConfigure(void)8 c$ ~+ b8 @/ G% t' O
{
) F/ T- L' f" ]6 g( Z i) A( VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# _8 k, X3 D+ t; yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' K* k; B* G, W6 e9 o) o/ N' k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' u% A Y8 v) `$ l! i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* q1 p1 u9 e! a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 O0 S& a/ O, b* \1 g1 Q3 X
MCASP_RX_MODE_DMA);- u$ W2 Z3 p M, C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# p4 M9 C& s$ }. U8 n' U( r# \2 {% xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ V: T5 \3 }' @5 c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 g: g" I1 }$ A4 C' XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# C7 p4 c7 x1 r9 h- p, KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) ^9 f1 t0 Y7 o) _2 V6 O b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 j$ s$ I- ^7 z8 iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( @0 Y# A" o! k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: F/ f9 v9 H. i: t0 a* o) {7 ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; Q2 W9 S9 [: I. k9 j0x00, 0xFF); /* configure the clock for transmitter */" B, ]6 y4 P# x1 o7 r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 X- ]- L7 u* R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ |4 Q# s. @8 _7 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. n9 V& A' b; A# v- o
0x00, 0xFF);( k+ k: K9 U' M8 [( b! {! H2 A$ v b& e
4 \0 B9 q4 a* Q. J$ C3 ^/* Enable synchronization of RX and TX sections */ # Y0 g! z3 `7 R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- @6 u/ f3 r9 g" M# A% X# }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; ]" i0 m4 g3 Z/ e3 a3 A8 hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 I; J Y1 A+ c1 [/ _
** Set the serializers, Currently only one serializer is set as
: b/ n& v( w1 V: g8 n) N) O" e** transmitter and one serializer as receiver.5 y, y. s2 s# K& n
*/% M* j: R; l* q% b' j% h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ z$ O" t% h ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 _$ O4 P5 ?/ w" M+ I
** Configure the McASP pins 8 O- O1 M2 _8 a3 F1 V# v6 P
** Input - Frame Sync, Clock and Serializer Rx
, S- s) y6 n# N; ~( |6 ?& Z T** Output - Serializer Tx is connected to the input of the codec / Q: D/ v8 |$ ^; \7 x2 U6 o
*/: L: c4 z' @: r+ E8 D1 N: I( j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. }/ z% L! J) d3 t- ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 L3 G8 P3 Y% r% _, HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 c% q1 I% i" b* `; [: R" q% x- || MCASP_PIN_ACLKX
5 L2 m+ p( [8 {5 v G| MCASP_PIN_AHCLKX
; S8 t8 F1 t% z( d' n0 }+ l$ M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 E, a/ l; e% r4 \# M( r- ^. e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% v# L ` l: n( e6 D| MCASP_TX_CLKFAIL
0 {; ~; y2 N+ {$ M# ?0 r) W% u| MCASP_TX_SYNCERROR
; Y8 z' I ~9 v# r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- }: K( V3 ]! @1 N3 D# f| MCASP_RX_CLKFAIL( i! u! |; E0 m! l
| MCASP_RX_SYNCERROR
- K: `; ~3 p' A, d| MCASP_RX_OVERRUN);& ]% Q% I# v) X* O: h- C
} static void I2SDataTxRxActivate(void)5 f9 x8 E+ {) Q% [- w3 h% Z
{
: B2 j; M F6 ?) h9 P! \8 B+ I/* Start the clocks */
. X! [ R- H3 \$ ~$ eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- `$ Y' f9 I( k5 A' y4 B+ b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 \! i Q% O1 ?; n3 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) N+ J' E) T; s) a0 ]
EDMA3_TRIG_MODE_EVENT);# ?7 W. {; m; f4 x& z9 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 G. c- D2 o. EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) P% E2 z' f3 c! ?+ |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! ] |5 y; h! @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% l% U) a9 M3 e* |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# z, Y! Y* [. l) u+ a; tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
y- ?+ ]7 L* _; G2 O7 xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 y6 z& g% e5 F' i! | z
} , I+ w. F' \/ W) x5 y: R1 I |6 w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
% `/ h; [0 ~4 Y9 b- @2 e |