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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, k$ | Z( m* O. c- \
input mcasp_ahclkx,7 B. d' Y# m0 u# M8 L
input mcasp_aclkx,
2 x1 E4 j2 G' @9 V$ Cinput axr0,
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$ x, Q8 `" G" ~3 N! u" o7 k6 koutput mcasp_afsr,) M- o+ |% o5 R3 R3 R4 m
output mcasp_ahclkr,& e9 e* d) U- w4 b
output mcasp_aclkr,) |6 O; z- m) R$ f" u$ I
output axr1,
2 x9 o$ j/ N5 R- P assign mcasp_afsr = mcasp_afsx;3 v. y. E8 B: P( |2 X6 x8 Z0 x
assign mcasp_aclkr = mcasp_aclkx;
$ m2 _# E7 P6 u& o0 D( k9 Rassign mcasp_ahclkr = mcasp_ahclkx;5 j! y6 N! l: W3 K! j6 T
assign axr1 = axr0;
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( k' @3 c. C. R2 f: [; v+ F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 |) B; P% t# p$ c1 Z! lstatic void McASPI2SConfigure(void)
. q- x5 ?& D4 n) l) j" |& \; h{3 S- w, N3 X9 p% w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 a( u* o5 ?) L0 p5 N4 d ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) b! }. v8 D* O: mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' G3 R% K5 ~$ [0 CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* K& J% z) B1 F; N6 z# v5 K" G H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 d) `8 e* B+ i t# |MCASP_RX_MODE_DMA);/ J0 h- ?. T8 w$ H {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, A% c9 B% ?) F+ y: x% t0 D+ P' e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" Q F0 }9 ^: ^6 H! _# Y: v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * a8 r$ s; s' Y$ p* [- G9 a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 g. v3 N h2 K1 R) \8 O6 }9 J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' c5 ^" H) ~6 }' H k) H: {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# T( Q$ m3 ?: T6 E/ N7 l8 e GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 D% @! c" i0 O! S4 Z/ u* I0 \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! g7 l9 ~3 @8 a m. `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" x6 A% C D* I1 A0x00, 0xFF); /* configure the clock for transmitter */
9 Y/ H" ^% i6 B7 B4 z' t+ `' W& O LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ K! k. G% ^0 c3 J7 o7 yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * C8 v! y( N% Q7 f8 M# @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. _, ?" b% V+ d4 C' i2 ?0x00, 0xFF);
2 @6 r0 G$ m0 }' {, \5 f& b" \5 q# v" A, v/ _ P/ M% [
/* Enable synchronization of RX and TX sections */ : H' c F, h) n: ~$ I5 k' D+ f6 A0 T9 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" h9 U- ]* D% O" s6 B: o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* F# j3 e" \& \+ E& ?8 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 S. L" j6 s+ S( J7 m2 m** Set the serializers, Currently only one serializer is set as9 O$ }7 m: F- U4 B
** transmitter and one serializer as receiver.8 G* C; \9 {9 x- p3 `: k' u2 P3 t0 R
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 |7 w \0 q O- g: I8 TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. W5 X( J2 d: c$ \, q4 j! r
** Configure the McASP pins
# I8 n/ J: m3 f: T' Y** Input - Frame Sync, Clock and Serializer Rx3 `% _+ o0 G2 q. c2 n
** Output - Serializer Tx is connected to the input of the codec 8 n7 C# w! f, m8 d) D/ x
*/
0 I; Y: {; k( k' T7 E# E& wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( z2 j: |1 }! \( fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& f2 @$ ^4 H% |- h" E7 @8 l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ p( `1 G& ?, B; r' |; W; p| MCASP_PIN_ACLKX
+ p3 [) t9 h7 L# i! g" S( K8 X& G| MCASP_PIN_AHCLKX
0 C5 y7 J$ j* _* P, Z$ U( u* \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ l. x& [/ D3 pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( `" u& J6 V9 ]0 X/ ^# V6 O| MCASP_TX_CLKFAIL
$ E% S5 w% B4 F" v+ T. J| MCASP_TX_SYNCERROR
1 e" x# F9 ~4 M$ s$ v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, y9 T) |+ h. n* C: z7 j| MCASP_RX_CLKFAIL2 l- f' a% m6 B) k3 m
| MCASP_RX_SYNCERROR
& {) I4 a5 D7 \ J| MCASP_RX_OVERRUN);
# f% e4 g* g* I# w: s} static void I2SDataTxRxActivate(void)9 `( N' v2 A8 G' Z- f" w
{/ h E/ @; ^3 C( V
/* Start the clocks */
7 r/ h7 c- E; v' n" iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' T) m% H8 W( R# Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! r, x. h+ ]$ p* q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 q% }- i1 f. c
EDMA3_TRIG_MODE_EVENT);
, C% B/ }/ j) w8 O0 U4 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * `9 P! Z1 V% M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ }0 F1 M4 x: w5 }# g& e- sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ m8 H, |$ v% m6 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 d" k* j+ c; Y3 ]/ w G xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) x( G, o x$ K9 @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 H: H7 b$ j' H3 X" pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 A8 {# |9 ?! c$ `2 z8 ~8 h2 \}
4 b% C- y! ~- O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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