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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 u' T# C4 L n8 h; s! g
input mcasp_ahclkx,, r& g' g, c/ v1 s3 b8 O$ Q
input mcasp_aclkx,% Q- ]0 R( D3 k& R0 @6 m" Y8 ]
input axr0,
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output mcasp_afsr,/ b5 n" V) x" s
output mcasp_ahclkr,$ \; h2 w. [0 `2 s( U3 c
output mcasp_aclkr,( {- L8 d5 e: [% x8 ~2 L. V4 X$ v
output axr1,
: h& B6 z, I0 I assign mcasp_afsr = mcasp_afsx;. e' E" W- n) a* {$ A# N
assign mcasp_aclkr = mcasp_aclkx;/ R0 q4 O$ J) b) z
assign mcasp_ahclkr = mcasp_ahclkx;
/ V4 l& N _8 Z2 q: _2 hassign axr1 = axr0;
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# k' s! @: A8 t" K; {0 t* O: U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: x# n- o7 N' z; q# L2 Zstatic void McASPI2SConfigure(void)
6 ^3 |- [& r9 ]! K, N2 E, M% y# R( [{
3 }3 J2 ]: V( EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 b2 w; F0 [# MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' {. s. Y0 K L& n3 l1 CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 F, T& Z* m" i( Y# \4 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# ^& h) U9 I- o. b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, E% B+ E7 B" K7 C
MCASP_RX_MODE_DMA);
- _' S& M3 N7 _4 i& q; qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, O0 C S7 q( OMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ C0 g: Z2 @ V7 Y0 H% X3 }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 u6 E, a9 n+ A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( y S: b, x8 V( ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & B& _1 _8 n' j- N, |% [/ [- g1 j$ H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 L9 Y3 t6 ?1 w* ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 S; _( u1 @& A7 T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- g; L+ h6 J/ SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! U* _4 m Q: f9 B( A3 m
0x00, 0xFF); /* configure the clock for transmitter */8 u' C2 Z) O5 l6 q/ h$ [7 [& d- s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( J: L5 y, C1 T0 k5 v, h" f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - u* ~* u0 g# U1 j' R# N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ M# ]( v: K, P5 n/ I- v8 b0x00, 0xFF);
! ^ i: G/ P' t. K* q
. w5 v$ U9 K$ N( v* k7 g/* Enable synchronization of RX and TX sections */
8 l7 n: ~% n' l( F8 b6 ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- m1 ]0 u1 F: t& o8 vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 `7 t! |% @" F! D: d) x1 W1 n+ D5 x' fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 Q1 @1 A5 J9 m! t* P3 T: x** Set the serializers, Currently only one serializer is set as
G2 k5 I/ C' v4 _" N; D** transmitter and one serializer as receiver.
- @) v0 C. h/ D( a! g5 r$ R*/
% B. p3 }5 Q. g. t3 jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 }4 r. V; U$ x' D, L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 U E: w3 e" i5 [. n5 |** Configure the McASP pins
9 P- X/ L w7 [. l** Input - Frame Sync, Clock and Serializer Rx# g% k D& a: y+ B
** Output - Serializer Tx is connected to the input of the codec
& Z1 R) e9 Y1 S2 i4 L6 s6 A2 S% X! N*/
; G- @0 }: O: n7 I3 x V1 ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% M2 m' q. {9 l1 LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" ~" ?" _8 H! Z8 m+ Y, B' UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" w3 j& [& S7 l! N$ A- T+ `
| MCASP_PIN_ACLKX
0 N9 `7 t% s) a: f- c& H$ @8 b: f| MCASP_PIN_AHCLKX; O$ @* _4 w8 A3 S6 _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" ?$ x6 y6 l) p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& P+ ]8 h+ S1 o& e/ X8 A5 u0 t- {| MCASP_TX_CLKFAIL
?' r8 s8 S/ G& Q| MCASP_TX_SYNCERROR
4 K1 w6 d* F) }1 z8 _5 x4 ^6 ~: e2 |* I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - k( n$ t4 C0 S& V
| MCASP_RX_CLKFAIL
5 D1 s$ T4 H* [9 P8 Q| MCASP_RX_SYNCERROR
1 P1 N, a2 U+ E" }| MCASP_RX_OVERRUN);
' y' n$ j% y. X2 v6 e, n+ x} static void I2SDataTxRxActivate(void)
8 ?4 s6 B: a3 C7 V; c! P{
F! o* T M( b' g3 t5 g/* Start the clocks */
0 r, h$ L) W( ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. _! `" t3 _8 g, U8 V8 D5 B9 _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 R- Y2 f+ ^ B7 r* v9 i. _% N4 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 A9 O: S9 L9 V6 MEDMA3_TRIG_MODE_EVENT);1 t/ B+ f' w w6 b) G1 l, L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : |0 J, }3 S/ n7 b( ^+ p f* [% |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, i$ _8 l8 w/ }- ~3 h Z( K& ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 A, Z. @0 h1 j- W' Q9 K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ h1 m) H8 ^! f4 a+ n% ^* {! Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# I+ r/ b2 {6 i* {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 y% S5 E6 R( @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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