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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) j2 K1 F; t$ h4 i' P ~9 r3 e2 Pinput mcasp_ahclkx,. l( b: B3 Y+ X6 A3 l; n
input mcasp_aclkx,' b2 G# t' }8 Q# o) [/ ]$ q
input axr0,/ }8 F8 \8 g/ u9 G
& z \) x7 V( w- q9 }
output mcasp_afsr,% j/ w) N$ R1 C2 Q+ V
output mcasp_ahclkr,/ `: p1 i) t1 Y/ g
output mcasp_aclkr,6 B& g3 A- P" ]) I, m2 R/ `
output axr1,8 K2 d7 F& ?$ \4 G. ^+ Z& o' D+ J
assign mcasp_afsr = mcasp_afsx;' v( r, @2 {; _# k3 j* Z
assign mcasp_aclkr = mcasp_aclkx;
" G. h5 A1 H- cassign mcasp_ahclkr = mcasp_ahclkx;/ {, |% T! b. v
assign axr1 = axr0; ' K5 }$ D) H+ O: a/ G: n3 l4 Z+ x' H
3 @0 c+ ]# I9 U, Q% m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! ^$ }1 F" S) M+ c
static void McASPI2SConfigure(void)
' x9 Q, u' C4 r2 \{
, }, G6 b6 ]7 |7 U. eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! [1 w/ t% n' h% d, v" K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ M& e! X, L3 V8 Y* l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# R. T! [( V+ B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( X( p' P) `, r+ a1 jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% t s/ I) m8 `1 t3 h& HMCASP_RX_MODE_DMA);& c3 V5 E0 B, K1 F+ O0 O% F. s k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 q8 y- V/ g% X% ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ y7 R' y0 M$ s% {( n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 s8 L6 g9 t, N6 F5 w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" j# d$ y u7 G* ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 c: c# y8 V! N& t4 T2 w2 R" O$ R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* b* V* c' z' x0 `; k" P) P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. G4 k7 {# J u$ ^% W( B0 YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 }8 }* q0 E( l8 I8 |/ H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 y* ]: g, p: {
0x00, 0xFF); /* configure the clock for transmitter */8 l) j! \- S. B7 @+ l% w* m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: u, o- w) W* P) r7 xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " Y4 G: j* a. j' A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 S; D7 s5 v% x1 \
0x00, 0xFF);! E4 t! i6 Y& C; v9 V
6 D) L" X, c" T. I; o, c/* Enable synchronization of RX and TX sections */ ; x* m5 h+ T0 J3 x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 z% U- h; ]0 nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 a$ m# M2 ]# s* d! i' OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 {2 A! P: n$ C6 l
** Set the serializers, Currently only one serializer is set as& G" v/ g- `% J/ X/ f- n
** transmitter and one serializer as receiver.+ p# I& t- i# P. r- I# J. P
*/2 t2 P# u7 |% T$ X# r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ K2 m) p2 N9 l, u Y5 O' E3 C9 S iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 N3 k. m, V; E. b- P+ V** Configure the McASP pins ! p7 t9 @# N$ ]9 A: O# U( P( m& d
** Input - Frame Sync, Clock and Serializer Rx
% G/ z9 B# f$ A** Output - Serializer Tx is connected to the input of the codec
0 p3 _0 r( b0 H*/
. M, t( }7 e" ~. \4 \- WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: N- x; ?3 Z: H( l% N- w" _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# `8 a0 c: Y2 D& P+ j; z! bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" G3 `+ c) E1 }0 F8 i) M" ~( S| MCASP_PIN_ACLKX
. V0 I6 l5 W4 h3 h; }6 r3 b| MCASP_PIN_AHCLKX" ^# |7 A; N6 J- ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 Z2 l! D9 ~9 V w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 D3 O8 K. f+ p
| MCASP_TX_CLKFAIL " O7 a4 B; @5 b, c9 ?, D
| MCASP_TX_SYNCERROR5 \. a0 |0 R3 C& a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 c1 Z, @2 m* }* m| MCASP_RX_CLKFAIL1 E4 g( V. x: u v" |+ l
| MCASP_RX_SYNCERROR
9 q5 C# t) G- m4 g' H| MCASP_RX_OVERRUN);5 c3 b2 }: U* ]. {$ Z+ c& @
} static void I2SDataTxRxActivate(void)
$ N: d3 B' t2 \' G: b{+ H$ k. u, E+ Y% ]/ b
/* Start the clocks */0 S$ N% N9 T8 b B! i F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; L4 f7 O8 L4 Z& {% t( z- ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" J2 k' v1 T3 o4 k2 d5 u" cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; O3 C7 V; s# f: v
EDMA3_TRIG_MODE_EVENT);
# q6 g. l: ~+ X& @% O+ n# LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 }2 A s b D% A- C( Q( t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# U9 ^/ f, j, f' e9 o6 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; [8 r* O$ h: u4 \- L/ Q( zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! |- D9 j- h K0 rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" n" d. t! H8 V& m8 l9 }* ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" q C' z! T. ~$ B5 TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) |4 a+ m. d5 n& X
}
3 ~- ?& j" P" y$ @, v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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