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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' H: \/ C& }. T. \( s* `& }/ D
input mcasp_ahclkx,
# T" f D, R; k( J% r. linput mcasp_aclkx," o( X+ S6 c6 \& H* E0 V/ e
input axr0,
1 u! c/ ~: w% {( D1 N$ Z) Z* U! `4 @* k2 m9 s9 w& {
output mcasp_afsr,
/ W G8 b- a$ B/ routput mcasp_ahclkr,
: V2 R j# D$ s' h' Ooutput mcasp_aclkr,, b- R. c! `6 `* p! K) b3 O# N& E
output axr1,- W2 @8 _) N: n7 G
assign mcasp_afsr = mcasp_afsx;$ o4 x/ T$ t4 [
assign mcasp_aclkr = mcasp_aclkx;
" V0 }% [. }; @( e$ X% ?' wassign mcasp_ahclkr = mcasp_ahclkx;4 v5 w& Q; }$ E, o: b- W% [$ l/ E1 V
assign axr1 = axr0;
) J2 U! P3 t5 ?5 E% D1 \- @( G0 z. C' M1 Y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% |# \- Q% J Z+ b' Vstatic void McASPI2SConfigure(void)3 s% H% B& o9 K
{- f8 b6 o& M6 S; H$ _. x: W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 e0 Z, X, P7 B6 _9 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! l0 X4 x% P2 Q% B& e* kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; {: O8 x; ~+ k6 x; e, Q, s8 ^: sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( E! e: d. v' P2 c2 }; z3 `0 Q) N. UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," v1 n7 \5 j' @: P
MCASP_RX_MODE_DMA);
3 C) X; P( ^6 r+ w8 M" g" ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( G+ X* |0 l9 ?$ k7 [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ S! A% L! l" L+ Q$ u3 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 M+ a! w" P# t" i" M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ K) Y! Q) |: V, |9 k; `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 ^3 t( q& }& ?0 s3 `' C- U/ i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// J [4 d) ^. Q7 I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& J# i3 u0 B, V/ @1 y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- G! l, C( ]8 y+ h1 P% pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 R' j2 \5 g$ e0x00, 0xFF); /* configure the clock for transmitter */+ [7 L- k1 M( v0 V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ {" m0 [% T: B% A* F1 k* L5 u! o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " m1 p& O9 G' z+ T4 h2 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& W: G8 L5 n4 r0 T% p: u( A0x00, 0xFF);! T+ W/ Y: U; Y1 {' x7 Y9 V$ o
6 X2 O$ I$ p5 P7 r s; W! e
/* Enable synchronization of RX and TX sections */
4 y# |+ b7 i8 m; y- Z. U/ @+ mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 s' } u4 x! I; _& t# J, kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# I. E" L, I- ~ o0 ^( [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% Q. ?1 Q/ X V0 P* J** Set the serializers, Currently only one serializer is set as2 m# H8 U2 D# o9 R- s8 p; F
** transmitter and one serializer as receiver.5 f& n0 q. w% }5 r4 a
*/; B& F1 c" d, O1 j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# M; h$ `7 k0 @2 z2 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 S h5 R6 l7 }9 z0 J5 P
** Configure the McASP pins " T% C4 f- m2 ?/ ?
** Input - Frame Sync, Clock and Serializer Rx, T. x2 b0 f3 {9 ^# u, b
** Output - Serializer Tx is connected to the input of the codec : z, X' c- d+ d3 {: E. a8 h
*/
# z8 F) ?; ^8 @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. w4 H' S% T" l2 C9 a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 U; R2 V* e! D/ h5 DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ [. R: ]: S6 q* _, g9 e, [6 p
| MCASP_PIN_ACLKX
3 d; j+ S, R% L. @| MCASP_PIN_AHCLKX
/ W7 W$ ~! ]6 c: _4 @7 B$ S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' ~; M' I5 m) l, c. _* c4 y! tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # [* `- q+ M5 S# ^" M$ P
| MCASP_TX_CLKFAIL 8 q6 F0 j7 K7 L0 O9 {1 G) H, L
| MCASP_TX_SYNCERROR* Q2 ]- q/ N2 L3 x9 w; g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 S/ a& |9 ?, [7 _% l; X5 j: G; o
| MCASP_RX_CLKFAIL
! i. ^* y$ Y- E" f| MCASP_RX_SYNCERROR
) [! g! Y- Z$ C8 t8 G5 s| MCASP_RX_OVERRUN);
) o( n9 l, M. }) E} static void I2SDataTxRxActivate(void)
# a9 c d% C c; j4 W, J1 C4 K{' u% t. z9 o' X! Y0 v
/* Start the clocks */
+ i- ?( {0 R8 J8 p4 vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 x6 n9 T8 m2 [8 r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, \4 }2 W/ t+ h2 P7 r( Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 V T8 {+ b ?/ w$ H7 H3 m
EDMA3_TRIG_MODE_EVENT);
- ]8 X2 ?) S; t" r# q* g% TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . A: R, s1 x; N2 T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 d* b `1 @& @& f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 @/ K& N9 {" ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 |2 d' {% a/ N% v- e. Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, X& x# Y$ @9 f( SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 `* v7 \+ a; u$ g/ k' \; pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- K, c2 [6 m$ s, ^
} + s! p4 V( \) K) y4 h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " _" L) Z) g1 z
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