MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
- W2 x, R5 F" \5 I8 H! yinput mcasp_ahclkx,
$ h! y& ?/ B8 q' |input mcasp_aclkx,
! z) s( ^2 z& _8 X4 y) B. ^2 k- minput axr0,

output mcasp_afsr,
output mcasp_ahclkr,
# m" L! L7 P) I% p( Houtput mcasp_aclkr,
output axr1,
* i) B* k9 @, Z

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
1 D* d9 a/ L- ?3 B  Yassign mcasp_ahclkr = mcasp_ahclkx;
9 m7 j- X3 \. x* \. i; }, B4 `+ Oassign axr1 = axr0;

3 O7 Y9 j0 c0 p# `- F- o

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

1 y; w% M2 v9 _

static void McASPI2SConfigure(void)
% t2 O+ ?; Y( v$ q5 F" M{
5 ^7 k$ I- {4 P6 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ S# _9 d, C8 p7 Q) ]McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
9 `* `+ J+ r- B0 y- c6 rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
  S! t, a$ L( Z7 ~/ e2 z6 w1 ?MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 e7 F4 |3 _3 p2 K& W3 ?MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* }+ W. z9 e0 K& T5 d4 p- vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; Y# \0 R" \/ }0 x6 s2 g  d) UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
# G5 }/ J7 c; ]* E  |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

2 v# {6 _0 v  X) J( Q  B3 Y! @/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
- h) `4 \% {# @. Q; j% xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' E0 O* L, H9 g  \; b& \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
2 m1 N' T$ Z$ ^- X** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; [6 d' w( |. v6 rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
5 J: ~4 h$ v( @: m, e** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
4 f/ P6 t+ P6 U* N8 z1 p: a! Q** Output - Serializer Tx is connected to the input of the codec
*/
' }# f: d4 @7 W4 M) M5 VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 U4 B) J$ \/ N* E9 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
# G  H) ]3 J+ W| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
! V+ Z* N: F4 Z0 M2 R9 z$ k3 CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, A# w$ C9 D! j  P/ j  J) z| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, X- s) F3 p9 A) H% _- Y4 k| MCASP_RX_CLKFAIL
) s1 o0 U, _, {| MCASP_RX_SYNCERROR
& H/ a) ?( A8 P; j/ E| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
- T( W% y. ^3 @1 P# q/* Start the clocks */
5 ^, I  G0 e1 K6 t; eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 ]% ^  ^7 t- r9 OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
2 g3 m# j6 G, R7 v2 P: ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
( A3 {* e9 N6 n& zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
# F3 |: [2 U2 `5 Z6 kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 F7 a/ h& B) H$ K}

! x- L* @5 x, p8 a$ o

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

( `) W) Z) N" D& g