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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* W2 v, ` \1 d w' f j5 H9 rinput mcasp_ahclkx," p9 O+ {* L. T
input mcasp_aclkx, c Q9 @6 \/ S9 X0 J) K, f3 u
input axr0,, g! l& j5 W: }4 g* {
) Y/ O: ]8 \" V8 w( E6 g5 `
output mcasp_afsr,
; W- M! N" t3 j3 p) Foutput mcasp_ahclkr,
3 b( P4 Y9 _: `9 u+ ~2 }output mcasp_aclkr,
# m4 d- g. K/ h poutput axr1,5 A4 M0 b+ N) s1 o; K
assign mcasp_afsr = mcasp_afsx;
& L% A" X3 m: jassign mcasp_aclkr = mcasp_aclkx;
: U4 ]- l# Y; `3 Z+ H _assign mcasp_ahclkr = mcasp_ahclkx;/ T0 t" u. C, Q5 L
assign axr1 = axr0; ; R C) G# y3 @$ @, T7 o6 O4 w
; f; |3 L, y4 Y9 g! p1 x& l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( B! d; C' O3 I; s# t, X) Z( xstatic void McASPI2SConfigure(void)
7 S, n @7 O# e+ `. Q{- ]% p$ m/ |) p" e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- a! @5 n7 n7 [& Y- HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( x3 y8 R( l' N" |( P) x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& M0 g6 g' Y/ h& V+ I- kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* ~9 h$ R, e' g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' j+ b9 P' u9 c* KMCASP_RX_MODE_DMA);" X$ @/ Q( _$ l9 e: C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, N2 ]2 m3 D" b( o4 L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
@5 v f# k6 S/ c: ^, j. YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 y5 z: [+ v: |" [7 p' W+ e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ Y2 w+ {3 J) l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& l- N- d7 R0 m( HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; O! ?( S3 }8 Q# p! q' q% O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 T6 [/ |& r v* rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) ]% ?+ K; Z, O! R% S2 e) N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 G# R6 g) }8 C
0x00, 0xFF); /* configure the clock for transmitter */+ ^$ G$ }. Y# ~; \, z9 A" l/ b5 ?1 E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& I( Z+ S% G( K4 b- n# ]' J: yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 e0 F- g( w7 ?) |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 ], L& o! N1 o9 c- d8 M
0x00, 0xFF);
( r+ b# e; r/ Y7 T$ P+ N8 D. W+ d
1 O' \/ ^' h. F& y, ~/* Enable synchronization of RX and TX sections */ 3 [, z) T" P/ ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ c; l% {1 Z& U5 IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( r! O$ v; x N" G3 E9 @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( B" g X# q1 }8 F" C- _2 e** Set the serializers, Currently only one serializer is set as
9 f0 Y& o" X9 {6 U+ A5 a4 ~** transmitter and one serializer as receiver.) s9 h9 I* P3 G9 J7 j1 K7 E# p% ?& Y
*/* h7 r3 z) n9 `& [& k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
W z6 K. ^% w; F- K/ LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 K% a0 m7 O# S9 k
** Configure the McASP pins
) v" Z9 b' M& }4 b** Input - Frame Sync, Clock and Serializer Rx1 z1 z, n2 `: a+ G% @! n6 ]( ]
** Output - Serializer Tx is connected to the input of the codec ?' X3 T/ c/ w, k- c" N
*/
0 H) c, H- H: X) r" b6 y- YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 o/ A9 \5 o. X7 N6 {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- H6 a; K# l0 e8 \, z# v% EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! U# ?0 p5 Y% a| MCASP_PIN_ACLKX M! ~4 O9 i2 h
| MCASP_PIN_AHCLKX
' D p$ p/ U% S& l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 _$ m: h/ `6 }$ b. xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ a! r' p( S) `9 H| MCASP_TX_CLKFAIL 8 _, }4 X' w" S3 _4 b# N, v
| MCASP_TX_SYNCERROR
6 d6 N+ b/ X- W" i6 c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) i' j' u0 y# A9 R| MCASP_RX_CLKFAIL
& G# t0 E. g8 ~# I| MCASP_RX_SYNCERROR 4 z1 y* ?0 Q) X( ?3 [8 a4 {; Z
| MCASP_RX_OVERRUN);
: q( ^/ N" C3 @ l. f} static void I2SDataTxRxActivate(void)
+ i, @4 [5 k" L6 L9 t; `3 v* s{( R4 j+ ^! p+ U/ h! `
/* Start the clocks */
; D- g" ~6 s& }7 B+ W7 s PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 G: X! a( P$ S0 }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: J2 G9 ?2 ~$ M6 o. v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 B6 |/ x: k& n1 ] o* @' _: `. NEDMA3_TRIG_MODE_EVENT);
0 N1 _, b, o- C+ _" _5 s: k" {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 U6 O( p. u: i/ [1 Z( V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 ]" C" |4 u% A, m1 M$ qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" ~+ X8 B) T5 N# X1 e y0 \1 C$ [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 C& l* ]. u+ N( V! S1 n8 e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 y2 x! N6 _3 O( H& Z# b8 Q+ p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" q; B/ }3 O( W c$ q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" T* G/ f# w) R V) r% j7 u} ^1 v$ s" C# ^8 `4 @' J }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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