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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 k" x' P/ U1 ^/ I' E
input mcasp_ahclkx,
' g1 H: S, s% _4 ~$ e( Xinput mcasp_aclkx,
O& N2 j. Q: i+ V) Minput axr0,
% Y) `+ o- [$ p9 S4 t ]1 O5 W: S2 U& N I0 y! B; D
output mcasp_afsr,. ]& k9 r# _" v3 k6 L+ C& W
output mcasp_ahclkr," w7 g) ~0 \0 E: Y
output mcasp_aclkr,
- }9 E; H) }+ T9 `2 f; P+ Routput axr1,
& K" u" _( V3 ^3 k6 @+ _ assign mcasp_afsr = mcasp_afsx;6 n" L4 B; k' u$ J! b% ?% R
assign mcasp_aclkr = mcasp_aclkx;
: @* a& e& D" f6 }assign mcasp_ahclkr = mcasp_ahclkx;7 p- r& j9 |; g6 {
assign axr1 = axr0; 1 G4 o9 b2 g" o- i9 u
- C* _' g! R% \1 M0 [* l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 I" \* T8 L$ j$ C5 L4 A2 wstatic void McASPI2SConfigure(void)" a# c2 n, t+ U6 @
{1 }" p; |. d. {: \7 s
McASPRxReset(SOC_MCASP_0_CTRL_REGS); T* v I% t+ V5 s' s: B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. Q; G P' M: J. Q; o0 ~1 c+ n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 ^1 t1 w" l' i7 O$ ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. I5 ], l% ~( z* \+ _3 ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* k7 h) J9 p8 T" c; _& h
MCASP_RX_MODE_DMA);
1 u, n1 {( J. B/ g) D9 r' u: f! ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 m* u: j! m# U8 T0 C8 z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' u. W( E+ j% E4 ?( o2 [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " m, d9 E% U9 s- n& O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 g& T: t7 z9 H# }0 }6 e! aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ Q: c* t, ~8 _" k L6 gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 x( k2 [, x2 a7 \' l3 Y, a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 o. ?* R( M9 w4 v0 I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 R- T/ C: f) t3 y, h/ {- aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. m: s) I3 z$ l: U, I7 x0x00, 0xFF); /* configure the clock for transmitter */- W9 l, }' ?* I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) a% k8 }) {% c. o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & o2 k5 G8 x8 ^. N( M4 j. N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 V+ Q$ s2 H: F/ J2 Y3 S, _7 \0x00, 0xFF);
! N2 k' q: \6 [" @( i( Y8 ]& M
' Y, F) l; Q9 Y7 E. X0 l3 m( x/ v7 f/* Enable synchronization of RX and TX sections */
4 @. ] G2 q8 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' q1 r% Q2 \: f) W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ S; s( Z5 U) y6 d3 B% K1 c# W6 J9 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' n9 ^8 Y) M5 x2 k/ L" ?& i( f4 Q
** Set the serializers, Currently only one serializer is set as
) ~$ m1 Q; x; p; ?5 ~) |6 h! h" Q9 S** transmitter and one serializer as receiver.
* o* Q# T; s) m" x( C7 }; F* U* m3 W*/
1 h* g1 B, c- L [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 r0 X3 _9 G$ n/ lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ r- a4 \2 K' l, w2 j3 R' e
** Configure the McASP pins
8 `+ x' f4 p% C' S$ o% k" e** Input - Frame Sync, Clock and Serializer Rx6 p+ F, ]9 {; N! M( _
** Output - Serializer Tx is connected to the input of the codec $ t; ^6 @% \! _! x& J, F; ]6 O
*/9 C1 Y& {7 O1 ^' e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 n5 }* g6 Q+ P3 `5 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 K# X1 o1 _; A# ~# {# _+ SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# c+ k i# H+ k' q
| MCASP_PIN_ACLKX0 @4 B. E0 S- k5 T- m' X! h
| MCASP_PIN_AHCLKX" {+ |. n# Q3 {+ }0 \! U- j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 }* d1 w, n4 M* j' V6 p5 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / W: h6 G4 k) i' @; s' w( Y
| MCASP_TX_CLKFAIL
R; t3 Y8 j- k$ j( C| MCASP_TX_SYNCERROR
5 }- J: h+ f- d* I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( T4 j# `9 G; }4 m| MCASP_RX_CLKFAIL" v$ i3 a: o3 J+ L/ G9 v
| MCASP_RX_SYNCERROR % R' F) g |. [# z$ h
| MCASP_RX_OVERRUN);
' `8 [, P5 y9 _0 g; g' \4 a0 o( Y$ R} static void I2SDataTxRxActivate(void)
7 b* P/ @! `6 Q" `6 S* F F{. r" K* G0 T/ y& J% J& u
/* Start the clocks */
% s1 @2 K; f! c' {& RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) @: V. b8 \0 X* L: D: M6 D5 v) a* QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 a! m1 J7 J$ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' t! N! P7 X" J' d$ r
EDMA3_TRIG_MODE_EVENT);
8 U' D. g, q- j" A8 Y. j' l6 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) Y: n4 ?8 P. B5 v1 d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) b/ B9 m8 ~3 G; j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; J3 k+ O' }, z2 u/ L9 D6 b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 F; g1 W/ g F, w8 V3 dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" n, F: s a2 f! c. x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 t$ j1 U& r2 ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 Z- ~& k- N! s$ \4 D} - }4 C3 ]- q! T2 d$ }1 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( E- W' T. U% M, l/ B+ Z
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