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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 ^5 ^1 T2 \7 {3 Rinput mcasp_ahclkx,+ j" K5 f+ N c: q9 N7 x5 F
input mcasp_aclkx,
/ Z3 O1 u" x6 a; b7 Z4 x! I, Ginput axr0,6 M, @: h. w4 }8 H. O p6 \0 C
; b1 K/ e" j- a/ I4 [
output mcasp_afsr,0 t# ]0 q) h3 l$ B; E
output mcasp_ahclkr,
+ m& ]: E2 a# j- T* A& Xoutput mcasp_aclkr,* ^) Y, W: _- h0 P$ _! A4 _" N |
output axr1,+ r1 Y; S1 d$ T0 L
assign mcasp_afsr = mcasp_afsx;
# s! D* o1 h* O' | @$ r, _assign mcasp_aclkr = mcasp_aclkx;
" d& c# H5 j4 w& n& |6 jassign mcasp_ahclkr = mcasp_ahclkx;
# X, S. V7 U( w; G! J# k( }$ Bassign axr1 = axr0;
& i6 V, B3 s( @! }7 s
$ {1 q- q* N0 n3 `* q' j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' z" @& `5 Y1 e( x: Wstatic void McASPI2SConfigure(void)
2 `7 G% Z9 y/ w7 c{8 f* S3 Z) R& d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. B% q" {% x$ E- h, u8 J, A; QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 K% |* X. L: {6 u0 Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ b0 _1 t# x: y3 L N9 [7 y# OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 F8 ]' B! f" k; C. }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) ]. ^( M& t* p, ?* |% n# {# }* ]
MCASP_RX_MODE_DMA);
, [% z. c8 Z& v. ?( H) iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 \* g& _, Y. Q; f! K& F+ ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 P: M2 D I- a* U( k7 f7 n& RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# z; Y- X$ f& K0 O" e5 hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
L! f2 w6 L, a. n- h# `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( r# z9 ]' ~+ p1 w* ]2 T8 l) sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 i6 o. E7 @) y {: _" v9 t {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) [7 m0 A; r \, t* ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 Q: p$ N0 |9 w: GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. s8 M7 S' ^+ v( b9 P
0x00, 0xFF); /* configure the clock for transmitter */, W8 n) N3 S4 A6 i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 U" L* p; {+ a& P0 U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 @7 P/ v8 m: N9 \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! Q# y8 Z+ B3 U# E
0x00, 0xFF);6 K+ ^; \% ~) R# `: G9 q
5 p. [9 t5 z/ Y. o! E5 t% u/* Enable synchronization of RX and TX sections */ & y# ]/ N4 O2 R$ T. A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. n$ p7 f% u3 y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, Z$ n2 `. p; z3 i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. x) C+ l9 p' ~ z
** Set the serializers, Currently only one serializer is set as
1 [* a; k8 q9 _& e m& ]4 e" o+ P) a** transmitter and one serializer as receiver.
) E g7 j/ G; b3 ~& I" u. O*/
) ]7 y2 H p; t3 T2 g+ w8 f2 n4 d4 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 v* N6 q& U! R' U }! d) VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 \: I( g u/ j- W- w+ \# |' ?& }** Configure the McASP pins
$ k0 r* l' [% _5 ?6 @** Input - Frame Sync, Clock and Serializer Rx
/ @! ~3 ?, H& J2 b/ [- o/ @8 X** Output - Serializer Tx is connected to the input of the codec
- P q9 ~+ }# }5 I/ c+ d2 f( y# t*// C& ~; M$ x% `& h7 ~% N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& K) X* D6 l2 S; A$ R% {$ J1 a8 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' q8 U; N$ F; j, m' U6 U0 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 v) M L. F8 ?$ N# w4 P
| MCASP_PIN_ACLKX
( m! h1 g8 t' z| MCASP_PIN_AHCLKX" C: P! r0 Q, Z j6 i5 H% a% c% F. G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 u9 ~8 h, M h0 v2 n+ _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # {. z- B. h( d+ e! m
| MCASP_TX_CLKFAIL ! ?) H( O2 k: q; \
| MCASP_TX_SYNCERROR; U( P2 X$ u- Q2 ^* R. g$ m! [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 J" ^ j% J# {& i% k| MCASP_RX_CLKFAIL$ x q7 n+ K+ h3 o
| MCASP_RX_SYNCERROR 7 r2 B9 S; s* t: v: \6 `4 M% ]4 k" S
| MCASP_RX_OVERRUN);5 S0 t# T, J4 w* ]% C
} static void I2SDataTxRxActivate(void)
) ]) e2 l: ^, U+ N" D/ U{
- o* ^; e; x+ D! K% S2 B/* Start the clocks */: T+ k( W f6 i) l% d9 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ T7 G; V. @( v+ Y4 G! dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 g' Q1 N b7 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% e" D5 F. _) v6 ~/ G) mEDMA3_TRIG_MODE_EVENT);
$ n: y' r: {/ e' X" Z# i/ TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 ?5 }* ~9 p! j6 v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- Y- W" q, x; l- S" hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% [9 l; L7 s0 X7 f. wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. J$ r( \" |+ D7 w: y$ U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ \) v1 @8 }6 |0 x! W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- D; ^& r0 v/ T4 t! c) ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) {" [4 ]. W. f$ T
} ! j, L' g4 n/ z! f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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