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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# g6 M$ N' I" ?% E9 |input mcasp_ahclkx,5 M/ C: {$ w0 F ^3 A/ y1 S h, V
input mcasp_aclkx,; B0 z+ n( H) _9 L9 i5 h
input axr0,) k$ U% V! W3 i* x5 m
4 z& \) [/ [3 ]% o; \
output mcasp_afsr,
5 y; ~: T$ Z8 f* m3 M/ Coutput mcasp_ahclkr,
5 w4 I% P+ f$ _output mcasp_aclkr,+ m/ |5 j" V0 u' R
output axr1,4 F3 Q9 v8 w( k9 ?2 f+ \
assign mcasp_afsr = mcasp_afsx;
8 Q$ ~ I( W' k% H4 m/ ]& }assign mcasp_aclkr = mcasp_aclkx;
- \) _, J* O0 s% w7 dassign mcasp_ahclkr = mcasp_ahclkx;
! y$ F6 [8 }* z: I4 Hassign axr1 = axr0; 8 a! ?1 C% r5 N3 A
. T2 p8 e; T q3 P) `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " o% t, M3 v4 Y9 g) I
static void McASPI2SConfigure(void)4 @, V5 |0 T7 k1 E1 x% q9 J7 v
{6 H8 `9 ]2 t, Q! U* Q( X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 c' u' q, s0 F S, `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 s5 R& D6 x; O! d1 t3 h: l, J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& @7 ` x/ w- m7 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( o- Q+ w! P# m, k+ h" qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' O) q! D0 r' a1 y2 S2 xMCASP_RX_MODE_DMA);% R# P, x3 y6 E) w* t- {$ J( q) I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 g9 O: w- v7 A- W: uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: O) J7 r3 i% ]0 ~( X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* n8 M6 c/ s% v) L7 V' ]9 UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( F) N7 Y7 ~- ]6 u- y/ F G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( ^% n# Q6 u6 Y& m+ {4 K! YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 l7 c! t# u1 W0 I' v- }+ ~3 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 q* r6 f+ J7 k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % N. l! v! D1 B% t; ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* T* r: W0 m9 P( R3 q6 e0x00, 0xFF); /* configure the clock for transmitter */$ Y# c# i1 J/ Z! K9 f# j, i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- x% O9 s' C& t8 K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) `! ]+ w/ B1 z8 k+ B, s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: F# r* Q" ` d% S3 j0x00, 0xFF);
& l) \' r' Q! o s$ y* Y- Y6 [" Q4 M
! `# ?/ Y4 @' i) @; W/* Enable synchronization of RX and TX sections */
0 C* \9 z9 ^* F3 gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 w7 i0 D! e A: f1 { b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. \ _( C; n- z5 C, j" }: V, R! Z% ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ C1 _ p/ ^- P+ a
** Set the serializers, Currently only one serializer is set as
_. S/ z1 f8 E% C** transmitter and one serializer as receiver.! }7 N( `9 E! C$ ^- Q2 H, y
*/
; l$ ^; }2 s; Z+ C5 O& jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. Z& h5 G; I0 I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. N" Y) i2 m6 _! g0 k8 T& f** Configure the McASP pins 3 |+ x! m5 |$ m* W7 F, R; K
** Input - Frame Sync, Clock and Serializer Rx
F( v+ q* w9 ^( C, H** Output - Serializer Tx is connected to the input of the codec
" R! i S: q3 o Z% b# N*/
7 i. J7 B7 `; H3 c& zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 s; K, t& }) I7 D- A2 [" `4 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* R: D- N; P0 t7 S* g8 T1 Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ d. N) P6 E; [; E& {9 W$ [
| MCASP_PIN_ACLKX
9 M) e. {, ?% |+ {5 \| MCASP_PIN_AHCLKX
7 |+ W2 N, f( g8 t3 ]* x9 x: I# w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, u0 m# @# {. L- S6 x# o$ r' x" `7 |# E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & J( ?6 i: z$ F
| MCASP_TX_CLKFAIL
9 ?" ?& ^7 _' E- Q2 E0 h| MCASP_TX_SYNCERROR/ j1 a- f4 x0 o9 g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 [7 g4 Z- n. F/ l3 T% [, S8 C
| MCASP_RX_CLKFAIL
7 n0 `% p5 U4 Q. g$ V# o/ [| MCASP_RX_SYNCERROR
2 l# G+ f7 g7 e5 p0 C| MCASP_RX_OVERRUN);
: ^# B" b5 r! _( _& a} static void I2SDataTxRxActivate(void)7 d6 `, y2 S9 ^! F$ j+ `
{
7 [8 L# e3 q u/* Start the clocks */
( a( E- y( ~, N' VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% w$ Y* n# K& SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 V6 B6 S9 r7 i" i$ wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 P7 {7 O7 C+ o
EDMA3_TRIG_MODE_EVENT);
" w9 L+ }/ ?# R* F: }5 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) _& U$ U# U% m" `: h/ G) w. UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* T' H) h5 A8 [" z% p) y: C2 P1 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- k. J1 y4 Z6 |( F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 N, | j6 |' `& j+ d1 \& G- S3 C3 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ f4 t$ p. ?4 l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 b* l6 n& S# t& P& A1 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 c- N$ w& o/ V0 W6 T
} 0 W" z, H6 P- Y" _5 Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 s1 Q9 S' a6 z4 z2 x. L }
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