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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! K( u- b# {8 P# vinput mcasp_ahclkx,
5 t" V8 l# j* s* z5 k* p1 b/ Yinput mcasp_aclkx,+ e6 A7 t( v8 d, V
input axr0,
w7 Z8 {$ i# M' H! G8 o8 Q% X) I; Z- j- _
output mcasp_afsr,$ G6 S3 F8 s$ D, H8 C( p) j
output mcasp_ahclkr,
5 I, O" Q, \/ t4 g a& y( r) _% Qoutput mcasp_aclkr,9 i9 I( `0 ^/ P1 P) R8 f
output axr1,, L- x; i6 H( `
assign mcasp_afsr = mcasp_afsx;" z) D8 I1 N- V+ F7 s
assign mcasp_aclkr = mcasp_aclkx;6 }8 ^6 T8 m# } Z/ [( D
assign mcasp_ahclkr = mcasp_ahclkx;
7 U5 }5 K: S; I1 ~0 b2 |3 S3 sassign axr1 = axr0;
6 [- g0 ^# _: y7 g4 u7 }0 _+ p6 |% F, H0 D% {; Z( J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; X6 K z( t" E5 E- jstatic void McASPI2SConfigure(void)
1 K6 P; a/ N+ | ~4 q4 u* J/ W, i{% m. T2 l1 ]7 u: W2 l1 b! a: j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 d K5 e" C0 ^ T3 A# SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ `, r% {: P& @" L3 v8 _. Y& B/ }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' f6 F6 s0 X+ P5 D6 H; \8 A$ OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ i+ Z% V* j6 t* }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% Z1 |% P" x& d* A( fMCASP_RX_MODE_DMA);* @! E4 l7 P0 W! g3 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 N- g+ x, S J0 g9 u) g6 s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 O3 G( x3 }. L9 v: N% T! T2 l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * p* d5 G* V2 B) P! u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! l/ R z1 [0 P7 i" C- H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' C0 L2 [: l& i0 n% Q8 P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 V4 }' T& m G PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, O: c7 `# f( r0 MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ b2 f$ q: O* F& V6 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 i7 R4 s- P, ~ `( Q/ x: \# w
0x00, 0xFF); /* configure the clock for transmitter */$ Q- i6 d9 v7 [. c& N# ?5 T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% e" Q. t, ]& `+ p U* pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . J1 K' p# o5 e0 q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: u8 |9 H4 e$ @; A8 J, V4 n0x00, 0xFF);8 k, Z I3 Y- x+ U: K- Z2 Y, L
3 x: ?0 `' Z% v4 ]
/* Enable synchronization of RX and TX sections */ 1 J$ a: T+ h, O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 e" z4 d/ e% Z" \0 w! e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ d: q1 @& M' b! m# UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' u3 N2 ~* q* [' f** Set the serializers, Currently only one serializer is set as
3 [% f8 G- T8 Z$ E0 u( f6 z4 m** transmitter and one serializer as receiver.
6 E2 N& z4 W! L G; C9 a*/
. f8 h9 C3 q1 q8 vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% R& \: D+ X% j: F2 {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' u2 [. A& M1 W** Configure the McASP pins & |; L) |# S+ c( d) k6 l5 b
** Input - Frame Sync, Clock and Serializer Rx2 \" z C( t1 \ L) |6 Y
** Output - Serializer Tx is connected to the input of the codec ) F7 t9 F5 l7 M+ \% Y
*/
( @" `; ^! J3 x* o- AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, O4 ]2 _( v6 S b CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; w/ R* m+ O( h. ?5 aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% R9 {9 E( g4 ]! g* T1 s
| MCASP_PIN_ACLKX
. y. ?6 N9 G1 t# \) s| MCASP_PIN_AHCLKX: x2 q, U& y2 E/ h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ M! {3 G. w; X% d3 o' N- q) J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! r% |5 h4 c( k0 E$ p
| MCASP_TX_CLKFAIL
+ K* g( V0 e( r0 O: d: v8 t| MCASP_TX_SYNCERROR
& B6 g" h1 ?% h1 r: [( ~$ f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. Z: G* ]$ J2 J+ Q* h| MCASP_RX_CLKFAIL
/ |9 I1 u" B) y4 v5 _! J% `| MCASP_RX_SYNCERROR 7 u9 u2 g7 F, M8 z; c% n
| MCASP_RX_OVERRUN);
3 k; ^, a O- F. m6 K: b& j6 e9 n} static void I2SDataTxRxActivate(void)
6 _5 j- i7 X: s$ l" F5 c& U7 S{
; p* I$ E4 e9 S1 \% |/* Start the clocks */
1 |1 Z; h& q. M" VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! }" w4 k$ l% T0 M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 W6 X) e- f. _: M' e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 B7 U. b5 Y! Y" h4 REDMA3_TRIG_MODE_EVENT);* o ] t* N! T; F ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ y2 L7 ]6 N! S9 W7 UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 l; `; c, J& C, e# J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 z/ k+ h- E2 h3 R% o$ W+ c, _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) D' ]3 H! \* I E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 H+ B* _( A0 ~9 x3 G: ?+ D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# B5 H+ G) J6 m T7 `# ?; f- r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 T' S% `, B& p- ?/ x! G2 U; f; n}
! o+ Q2 T' |( w- {. b9 |8 G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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