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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; e: s5 U( D) \- |) Yinput mcasp_ahclkx,; E4 _1 w6 ]* `* y; W
input mcasp_aclkx,
7 |% {7 v5 q0 d5 Finput axr0,4 Y+ V N' g2 n! S! g
6 ^* o, @6 @, Joutput mcasp_afsr,: z- r9 k$ _/ s+ |7 X
output mcasp_ahclkr,$ h' \1 W; f: B0 t' o Z9 |/ E
output mcasp_aclkr,
8 a( K& c& W: n$ O0 J; ]output axr1,
+ A/ M; ]8 N* X% T; h assign mcasp_afsr = mcasp_afsx;
- O0 Q& S' w3 q+ ]" Jassign mcasp_aclkr = mcasp_aclkx;8 X( s. O9 W3 c, g& R- e$ m
assign mcasp_ahclkr = mcasp_ahclkx;7 V% [& s& B4 d( }+ [' a' E& H+ R. c
assign axr1 = axr0;
8 z5 {; k/ e( P
! M5 D/ F6 ^1 k9 }8 b1 ]$ a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 `' K1 a2 j# istatic void McASPI2SConfigure(void)) s; g" L6 W! y8 u- l& B9 ?
{3 @1 r3 a* o7 w! F( `, D) c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" e# `; g; y4 {# @6 X, A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' Q; y, s- Y; g+ t; fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 v' {" H) W A4 O# kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 H# W/ r, u, {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
f8 P# L' K* z$ ?MCASP_RX_MODE_DMA);
2 [+ W" T' n( a, C: dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 [- N0 _. b% D3 A- z; G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, K5 R" r$ Q- @ u" W P" oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * G) k) }4 U5 L$ Z& h+ U% I& m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ N% O: Y! ?7 q! N# cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: O; W6 ?7 H g; m3 @* cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 {! }; g9 i! ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& L: f J( Y5 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: ?, f$ J& W" }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 F+ n" |; s: w3 Q! V
0x00, 0xFF); /* configure the clock for transmitter */
9 S$ ]' X$ r- C* L8 L. ?& yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 C L# N4 K& T# [) Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ _( E6 v3 h/ K) c* jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 M0 `6 r. k# }0x00, 0xFF);/ l% Z, [# }: ~3 c! ?7 I5 j e
0 k1 }4 w% C2 x7 E7 W
/* Enable synchronization of RX and TX sections */ 9 E, t# N8 |, c1 A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// t5 ~0 b, x" B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, s8 F( o, m9 X; v0 WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ y5 b6 i0 R7 n( g! Z `
** Set the serializers, Currently only one serializer is set as
0 H" C6 V6 @, X: Q. z' {* I; z** transmitter and one serializer as receiver.
+ [6 R% w: n9 [8 V; p2 v- }# o/ Y* W v*/
Q: i6 G) B' n. U# U. ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) R' v+ r; ?$ i, Y) VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- k% o$ q: f) k+ `/ _ ]
** Configure the McASP pins , _# d- \& m0 k$ w
** Input - Frame Sync, Clock and Serializer Rx# A- I( E+ N6 E7 {: M/ R
** Output - Serializer Tx is connected to the input of the codec % p3 G5 L5 H! o1 g; j
*/8 ]1 j5 Q2 P6 b6 G L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 m$ [+ b0 Y6 w& Z4 \8 P) uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: r) D4 I% K ?6 ~) X- F3 Z3 gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! n4 a9 o# q k$ p" A
| MCASP_PIN_ACLKX9 [: p6 p. q# d P3 L5 Z# G
| MCASP_PIN_AHCLKX
, s n, z r+ s4 h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: ^0 o" @6 h: G9 N' C$ T' P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 ^' q E/ E \" K| MCASP_TX_CLKFAIL , _" Q" T1 R+ T3 Y4 i, ~& q7 j
| MCASP_TX_SYNCERROR
3 I% @% ]1 W& X# ^8 j0 H% i6 R' P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " L& c, Z! I, R t. d7 z g1 y
| MCASP_RX_CLKFAIL
+ ]" f' n6 t! ?1 A| MCASP_RX_SYNCERROR , M( I9 ^; W8 X5 g6 C$ E
| MCASP_RX_OVERRUN);
6 A- E; f$ Q4 X h4 Y, H( Y} static void I2SDataTxRxActivate(void)6 z- u0 {+ U' n
{0 I0 i% Q" p7 e+ g y5 x
/* Start the clocks */4 }# }' W( m# ]7 @6 Q+ W6 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# ~; ^) f' F: Z) s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ I9 b/ M5 [* X2 l! z6 i& ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 X* a) l! r" N; G# j) q, s# d; f
EDMA3_TRIG_MODE_EVENT);" y" H+ g4 e) H+ Y7 `! ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 t# X/ r$ w. Y. f4 @- \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 g0 r+ T$ Y; e% w$ q8 M- aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 S- [* k* L0 C: k7 A& kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! K" P" [4 z4 q. {* ^! c4 J/ h% A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* E1 Z$ X T: c6 i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: Y$ `4 s+ b3 d" D5 ?7 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS); T# u( H5 _9 G' }
}
5 T; W- Z3 G* V' j7 V6 |2 h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 P4 d; K4 i) l9 P. N$ L
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