MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
" t4 ^: `0 p$ v+ ?! k% sinput mcasp_ahclkx,
input mcasp_aclkx,
1 l% m( y. a" S. \& Binput axr0,

. @/ Z* r% [% uoutput mcasp_afsr,
- t  h7 x1 i. ~& u( [8 Toutput mcasp_ahclkr,
output mcasp_aclkr,
; }6 S- K$ A9 A  soutput axr1,
: c) t7 y: v4 H/ B. [6 A

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

, P1 W: o6 `# J& Y$ d3 a; k

static void McASPI2SConfigure(void)
# H% C0 A; P! R" j' b! h" w{
2 L3 \  f6 g3 x$ _( R* X( r8 c& qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 e8 }7 R% U5 }4 YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
/ C9 H' J. c. e) nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
, v8 c# W6 K0 A3 h( e9 @% \8 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
  S( v6 u+ f) ?# wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
2 E, j; D. k3 o& uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! h8 o6 R& x; f; E' zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
8 \) [) j5 B9 s5 v4 f5 j8 G+ ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) o3 c9 H4 ~, }. J3 b0 t6 EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ H& u5 a" E* g+ |+ l/ d! [# L0x00, 0xFF);
! r' m: I; c/ D( [6 E
' V  l4 G; l' M8 C/* Enable synchronization of RX and TX sections */
) @2 C+ O9 m/ w$ W' q0 V8 e3 PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
. Z. f$ R& G" [; `# A+ o& W6 M6 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' Y% V: \% {/ O* k3 M% LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
! }' h- n0 }; a: Z) I** Set the serializers, Currently only one serializer is set as
/ l4 d5 C; W7 u- ~1 Z7 c** transmitter and one serializer as receiver.
*/
; D* _& Y. q8 v0 L0 _; |# n, B7 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
2 @# q1 U& P0 y$ Z1 }+ ]9 X9 X! V** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 U3 B2 W. l  `% t7 C: r4 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& T9 e" p/ ~) ]! zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
/ e4 [+ u' b0 R2 a+ e| MCASP_PIN_AHCLKX
6 g( ~$ q3 `$ a5 k* S2 e5 D8 C| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
7 D, {; q; i$ ^6 cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 x8 g8 `9 E9 m: b7 [' I  j5 G| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- H, ?* @9 d% Z| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
, u' t) Z8 c8 k5 \{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ U1 D. S7 q. }8 ?1 X# z- GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" r- U/ K* H- d) o% }' c$ dEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ W) J4 O+ q6 u3 q. S/ \, q7 zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
  W2 D2 Y9 [. r1 O! U4 CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. G2 g* _) e/ T# tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' B* T( R3 k+ A% H. z}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.