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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( V0 j w! b$ o- G- A; E
input mcasp_ahclkx,; }7 u" }2 e8 S% u! W3 [
input mcasp_aclkx,* }: F) Q% w( m. g
input axr0,4 P' b8 x6 r( E
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output mcasp_afsr,# }2 w% E1 O& A! ]7 T
output mcasp_ahclkr,
8 K/ `* ]" H: xoutput mcasp_aclkr,5 V Z- G0 J+ P& H$ Z8 p1 g" f
output axr1,
; O0 b+ M3 h# {" Z assign mcasp_afsr = mcasp_afsx;3 u2 S8 N- F& t( O/ U; ^4 { b
assign mcasp_aclkr = mcasp_aclkx;* l: E" J3 y, U
assign mcasp_ahclkr = mcasp_ahclkx;5 F5 `$ e4 o, j+ W$ P; d
assign axr1 = axr0;
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0 Q+ G3 E+ g" x8 S4 U5 X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& V; E, Q9 l2 r$ H/ Pstatic void McASPI2SConfigure(void)
3 ]2 G8 F- {0 {2 H{& C9 V9 } B. B/ I0 P, p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 L G, b( C; o; A9 z5 @ E) z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' P( ]. w* Z- W- U$ UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" C1 I2 o! f0 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" n+ \& s' y `1 y' A' aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) V" b* e6 i( nMCASP_RX_MODE_DMA);
. q* K7 {8 D$ P1 S( }0 F- tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 a, a# E8 N# ?% w n& T( w$ G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' }- G( x% f3 n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! ]6 `+ s% u, d4 _- G! G! c! o- U3 I9 _# `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 r* G" ^# O* K& r7 r0 L' |& yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 N# o' B$ |4 [( S5 [: k% M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ v7 a! _0 F$ |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 N' O6 A& R; [5 ]4 pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! V7 N2 H; D: ], [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ v' K, D% G/ `" H
0x00, 0xFF); /* configure the clock for transmitter */ p- I* |/ v+ X; j9 o/ P6 \; O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, ~5 D- a; J3 l4 U6 s: SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 v6 F. q# u& r: n# R1 ?# [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 p/ }$ y) i& u6 F+ L* Q$ R9 k0x00, 0xFF);
; }5 n- S# A/ |. m! f# C# o
3 S6 C( ^9 A" G; W5 G/* Enable synchronization of RX and TX sections */
/ ^& p+ }/ d4 V" X" XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" \2 h# M1 k# n: ?; I3 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 W: F% |5 J4 z" CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, [2 w: @6 [5 Y, W N* R+ T** Set the serializers, Currently only one serializer is set as
9 t0 n! B" ?) k& X$ K5 f** transmitter and one serializer as receiver.8 S) j4 ?/ }+ ~! I8 X' d) p
*/
( u% I# B# t9 N9 Q' D$ G$ v" cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. t5 }9 P4 y5 t( ?8 Z" |, F0 A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 ]% G$ F Q* O** Configure the McASP pins ; c. A3 \2 n# Y0 [- p) c* j
** Input - Frame Sync, Clock and Serializer Rx$ _2 j# G- X# F1 h v8 d. l5 W, v
** Output - Serializer Tx is connected to the input of the codec 2 {1 A/ b( X9 z8 B1 f
*/5 G5 E+ p/ R# u, A. f6 i. e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, I# E3 o0 E% t2 ^% S2 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ v6 n2 E; v! N/ o+ d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. u& {: }) `: z+ C! D: p- m
| MCASP_PIN_ACLKX; y: J2 {1 d/ M, S( ]! T
| MCASP_PIN_AHCLKX+ j9 R3 X! d5 ]& W7 {8 Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 O) X) `: _8 e' l0 B$ VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
j0 v9 K; ]9 r5 E: o| MCASP_TX_CLKFAIL
. |" g& d6 x* {4 P; u: ~8 C| MCASP_TX_SYNCERROR
% Q( j1 o# R6 S+ S6 C) W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 D1 O; S6 I9 C. P* S" P7 t, ]| MCASP_RX_CLKFAIL' \ k/ [6 x3 R) a( U, K& O4 U7 z( C
| MCASP_RX_SYNCERROR
2 `# `$ _* H2 z; v5 W| MCASP_RX_OVERRUN);
% e: S2 h. l' X- ^% i: w9 \} static void I2SDataTxRxActivate(void)9 u( X+ [9 B* Z9 f3 B" _
{
- C1 L+ t6 u) i1 M0 d2 K/* Start the clocks */
4 S$ X; G. Z( t, @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! Z/ F$ [1 t- X! z8 |8 F( Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" y) Q* W0 Y6 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 r& R. p/ D) b: LEDMA3_TRIG_MODE_EVENT);
" A5 N" H8 e+ x2 I+ i# UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, w5 Y) r' J8 w, Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 y' ~4 t- \$ n5 j$ sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
y8 X- K6 E3 e6 o4 c, [/ }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# Q9 ^; {( ]& w% d; h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 v7 d* p6 Y/ c# x% `) w+ z: n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; x+ Y: j: \' W, e+ w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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: e" L/ @: N# y5 b$ ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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