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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, x8 X7 {8 E2 Z6 jinput mcasp_ahclkx,
' \) R( i# U9 P0 N0 P% iinput mcasp_aclkx,; a9 \- C# {6 z( d. Y* h
input axr0,
3 ~3 H+ ~$ q* R2 k c a
# {7 s5 _0 n+ C; s7 c' koutput mcasp_afsr,
' [: n: n. b* Coutput mcasp_ahclkr,
" x3 x+ F. r* F6 Youtput mcasp_aclkr,8 R! m3 |1 _' s. l/ H& I/ Z, S% m
output axr1,
! p1 d0 L0 ]+ p assign mcasp_afsr = mcasp_afsx;
( i0 e2 i8 [9 @0 S" [assign mcasp_aclkr = mcasp_aclkx;
l' d8 o8 t7 P- {& b! Y; V9 Massign mcasp_ahclkr = mcasp_ahclkx;8 B7 e/ ?4 m* W* Y0 M! S# N
assign axr1 = axr0;
0 k& c' v. c! |- W* Z9 s. ]' t, p9 `7 W( J+ O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' [: d0 Y+ m* m5 r# Z
static void McASPI2SConfigure(void)
: ^- Y; @2 ?+ }7 F$ E/ r9 K9 U, J{
( b& {) M G4 |6 h" z! OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 U) F* F$ ]" }/ Y5 vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 z$ t3 O5 j3 { S7 U! x' yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 q- r7 y. Y- BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
g8 ?5 w( t, J1 gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. ~% D7 ~6 Z8 n5 ^- c) c1 t, y
MCASP_RX_MODE_DMA);% ?/ L$ N' k/ b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 v: N* f! v* f+ J- |$ PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ y4 g1 A! J( c. ^' z6 c/ K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; S) b+ F% ~% l6 F9 H Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 l5 e' X$ y& W* M$ k- ?& S9 P0 n/ B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , w+ F/ N* Y9 b' e$ i! L6 ]& b# p! s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. c( y* i% f3 F7 w, s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 g& l4 y4 l6 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 o( W* o, r5 N* TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 H2 K+ Y2 Q5 {6 W" e% i0x00, 0xFF); /* configure the clock for transmitter */5 V8 o' Q: Z- R- w- t3 h7 H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- R, B ]+ K) c8 j9 V$ l, Q+ m7 t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& ^/ f' {, b5 K5 h1 |: ~& i8 I9 t/ g' jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 ?+ H% n' ~7 A% G4 Y* C0x00, 0xFF);2 c6 V0 O7 [% V6 C- T
7 ^* b8 ` h# f/ i( x5 W3 [
/* Enable synchronization of RX and TX sections */
# W' x' G3 R( d* D; S% c: G# JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 m* q x& ~7 h) b- }' t' K9 u! Q: v3 _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% F1 l; m; i+ [( W7 R# V/ _! LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 H4 I+ W5 g( t9 o** Set the serializers, Currently only one serializer is set as
0 w0 E+ m6 C% ^$ U4 h1 c** transmitter and one serializer as receiver.
. k* s# T& k+ U7 W& p/ S; G*/
! ?3 L! M* v. n) |/ QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 g' s% a' F" E$ R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 C$ K2 G A1 Z" u' u1 G: C5 n
** Configure the McASP pins
$ [+ B1 C/ T# E j, d** Input - Frame Sync, Clock and Serializer Rx+ h) _* c. w% U! b
** Output - Serializer Tx is connected to the input of the codec
7 D- Y3 ~7 K0 i) F*/
* c7 |3 \ r( w" V) TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% B* r1 @& ]/ g) p3 a5 e- oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: T( H9 X7 _1 j( `2 bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 e3 C4 U; B: t, i$ N& _
| MCASP_PIN_ACLKX
" _+ F8 b. ], x) |5 e) c| MCASP_PIN_AHCLKX- S+ P& ?" H, A5 w- f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 @8 t' M9 ?0 ~& H' D) {: y4 M Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( l) |) x6 U7 V# ]| MCASP_TX_CLKFAIL
0 C1 V c+ D# ]| MCASP_TX_SYNCERROR
/ {1 Q$ g5 P& ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ e6 `! d; X! e: R| MCASP_RX_CLKFAIL
8 W% Z/ g0 {; l- U) P9 v0 H5 n| MCASP_RX_SYNCERROR . ?# K" k3 b% y. K) `0 G
| MCASP_RX_OVERRUN);
- E. l% e' i% x* G7 s} static void I2SDataTxRxActivate(void)) g/ U; N( m. {$ y8 s' Q
{
8 B a. t6 B$ D6 d. {/* Start the clocks */
1 J$ G) r z: Q* kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; z& i8 `3 y$ T1 |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: z/ Y" I( g8 v% q$ a1 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) R1 E8 }$ T7 P& r3 hEDMA3_TRIG_MODE_EVENT);
q; Y2 C9 A' E* Y$ @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 ~3 q* T' s* I8 r4 W$ d8 J ]8 _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( x7 s0 r- w& D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ U8 ?2 I$ ?5 M: z* ~) S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ J5 ]6 V6 l8 e, C" D& I& r! u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* j/ b8 I9 [+ X; l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, q% h) w2 w1 F- }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 r3 b0 V" V6 F7 q' Y% }} , _* @% e' v% h6 h; T( N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : C1 ]: ?6 L' O. v/ ?
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