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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- w: M) y6 |" u) S8 a: r
input mcasp_ahclkx,( F8 w$ L/ d4 J! M0 l
input mcasp_aclkx,! y& @+ R' e0 v& q
input axr0,
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. k( C8 l4 k* H; {; m6 g5 joutput mcasp_afsr,
- T( u2 r/ F1 n: j$ ?( Doutput mcasp_ahclkr,, q1 S. h, o0 I
output mcasp_aclkr,
6 G U3 R7 G$ Q" F9 w0 loutput axr1," h4 i3 l! u* r) H3 \% q1 V
assign mcasp_afsr = mcasp_afsx;9 w/ R! ?1 d* l5 \' W
assign mcasp_aclkr = mcasp_aclkx;6 E" F; R' s N8 s+ L: z+ r
assign mcasp_ahclkr = mcasp_ahclkx;- t/ p4 A* x! t1 u ]0 k! B( H
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 ?7 R- e1 W X
static void McASPI2SConfigure(void)9 z% L/ E6 G! D5 y( s3 G. A1 _$ V& L
{( L2 ^6 V# B1 a" D$ \) w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% o r9 c }/ I5 o2 _' E& j( GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. l1 l; s4 \& P9 fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 w8 l3 Q& j& i, `. M3 B$ W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' H6 Y2 J. \& X& B* J/ ` D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ m) |3 [7 p4 _. q' X% xMCASP_RX_MODE_DMA);
7 z% {( j; @' o% VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 Z$ s% @" ^! VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# y9 p2 o H @' @( e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( y& n, W/ j# D1 n5 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( ?6 @! Q5 z {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 r, J. K& [0 \0 Y2 p3 k" j9 s, g) uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ ^1 |9 t2 b- U2 XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, i$ _1 K% V" kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 v( k5 f- t* W" j8 ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: P. B% [+ L. j) |9 A% P& J
0x00, 0xFF); /* configure the clock for transmitter */4 D1 A1 z' J3 _& n5 I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( w7 b8 Q/ m" U( x8 d7 u: eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
Q% p4 |* e2 ?3 `& s# Z' cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 l# C3 m/ v* r3 y6 U& {8 t0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
$ G- K7 w3 [5 o5 W ~% x) PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( y! L* u2 W& L; c" x: ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( ^* N; e- f: d- CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 l6 ^! d$ {' ^4 i** Set the serializers, Currently only one serializer is set as
' z5 d: u" |$ A% ^) H& i** transmitter and one serializer as receiver.
4 Z) D2 i% y$ x*// [( G) p- M- T) F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 v9 b, T# \7 R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ C& C( r/ X7 \** Configure the McASP pins
8 W. a7 P6 _7 N( P$ p1 l1 @0 J' p** Input - Frame Sync, Clock and Serializer Rx' I/ b; u. l( }7 H' J5 x4 w9 s
** Output - Serializer Tx is connected to the input of the codec
: U$ z8 P# b3 D7 A3 h# z*/
- I' T6 j! V/ G/ i1 l1 F: e* W8 `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 q/ o. Y& C$ H: a2 H" D$ Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, o/ i$ B; y- m4 E- ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* r* ]+ O# x& v| MCASP_PIN_ACLKX4 q8 W% X: o# ?9 H! a
| MCASP_PIN_AHCLKX+ S/ w2 H; }1 j/ h% w r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 B6 U- y |. c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ L( S: T6 S# }) c6 I" ~
| MCASP_TX_CLKFAIL
6 g) N$ u0 l+ U! U# u| MCASP_TX_SYNCERROR6 J, b) l# D) G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # O% _1 V; k9 I
| MCASP_RX_CLKFAIL
- D# O, Z. Z! [/ j" u| MCASP_RX_SYNCERROR - z1 O: O: k( G' W, E0 \" a
| MCASP_RX_OVERRUN);/ K! R0 L3 Y% ]% Y8 O; k( ~1 [
} static void I2SDataTxRxActivate(void)1 w6 A) S* u, s) g1 Z! U" p# T
{
( p; z) @& `$ H/* Start the clocks */
: Z" W3 A9 [" L! [& l" H3 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ I% `! N* T, I8 {+ T! ^. P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: {3 q2 x) b P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ V- s1 K7 Z! @0 ^# C
EDMA3_TRIG_MODE_EVENT);
; q2 o _# C2 W4 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ G9 d, P1 K( A* K- P3 V9 {8 L& HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! l! o5 `2 E" E7 ^5 _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) `) ?- x/ k( K! [/ ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. M4 x% d, h3 W* E" e5 B ^" }3 Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 h( I' v% H2 a: \5 m# W" Q5 s' w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) a( B+ w4 z# iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* c) y) Z" A3 Q& d5 V( D, ]
} ; E ^5 y( G6 V e5 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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