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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, E' j) V" H6 Y5 ]. }
input mcasp_ahclkx,5 m# R: h: W9 c. N5 x) F' C
input mcasp_aclkx,
- v' s2 t- k5 f" t& }" m2 W$ sinput axr0,; y4 r# U0 k# h& b) U, @ e; F
2 w4 x3 Q$ H- s, b& P' H( N5 ]output mcasp_afsr,
0 Q* Q$ E ~: Z1 |output mcasp_ahclkr,0 t% w* \5 }, x$ h$ C3 t
output mcasp_aclkr, q2 h0 R' c5 g) S4 X3 Y1 |" X
output axr1,
% {1 T2 t2 \* Z" |. B' E5 Z assign mcasp_afsr = mcasp_afsx;
# J# e! y2 F' j# bassign mcasp_aclkr = mcasp_aclkx;- a( ?' l7 V" o" p
assign mcasp_ahclkr = mcasp_ahclkx;
# }1 x& O6 r! {6 G# l. eassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; Q+ I" D& Z: Y/ |
static void McASPI2SConfigure(void)3 I4 j0 }( C) y. A4 S8 e) \
{
( I, w; p6 ^- a7 H7 ]$ g1 v$ bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 E) P9 M+ y- K. N, f$ yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ {9 A9 q' Y' s5 g" M. GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. F& P! A" J) y; N o1 y% t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; i' `/ t' x* `: `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, T0 v7 ~9 x- Q% ~! f
MCASP_RX_MODE_DMA);
9 o2 L7 X/ c$ M* G9 E: n0 gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 q' n3 F6 t4 rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% m+ H% O# y( c7 S2 ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " z' m' C' l; \0 c- Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 b2 u* f: z# @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 t. G' ]# r# I8 g" A) P- CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 O3 }8 n0 d5 VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 k* e& c) ~) N+ O: H! _2 e! g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ t4 [1 z3 g- j0 w2 kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& L2 Q2 _3 ^9 e8 q
0x00, 0xFF); /* configure the clock for transmitter */$ z" K1 p0 P6 v6 w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- R/ _* e2 R0 A. R& o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 g6 |& I( T8 r' E, ^4 Q$ E3 _- C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& v, l+ v: N2 @5 f0x00, 0xFF);
3 ~0 |- r; h2 e% O) w0 w. c( u8 a% O' Y' `" @# }
/* Enable synchronization of RX and TX sections */ Q. i& e; g% f1 b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 L5 r" m) u( Q f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. F& z3 Z$ F5 M& e' d; ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 W5 l( q' r% t1 [8 k! W2 O
** Set the serializers, Currently only one serializer is set as. m7 d' r( @0 T; R, q; n
** transmitter and one serializer as receiver.3 E0 [$ w$ k/ z# N+ W3 Y2 |4 z2 S+ a
*/4 o" S9 Q1 [3 c6 W) s- b8 O# P7 q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& k2 C6 H" e/ u. w$ t7 rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, C' l! ]. x% d$ p** Configure the McASP pins
7 t' u% c9 {) m** Input - Frame Sync, Clock and Serializer Rx
" Z1 E1 w! h* [4 k** Output - Serializer Tx is connected to the input of the codec ' t9 Q5 S5 U( Q I
*/
5 T. F6 _/ v" P' K. XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. d. ?/ x& y% J/ _& N: y3 F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 f6 l/ C, l/ v* U5 n. R6 h+ d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( F4 l3 d$ R/ A2 d+ X| MCASP_PIN_ACLKX3 z9 b- C, J' p+ _
| MCASP_PIN_AHCLKX
+ a1 v6 g; {5 n0 R/ T7 L2 B, U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 T# {+ G- z% b4 c( sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; N+ {( S" e: S4 q1 ~* h| MCASP_TX_CLKFAIL 2 _" u/ y# `* c( r% F& g; T
| MCASP_TX_SYNCERROR- ~7 _. m5 `/ O0 v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 _ g: m! w' R' _/ Q5 u, u2 L2 f: N! m
| MCASP_RX_CLKFAIL& M, J0 q: g6 s* C
| MCASP_RX_SYNCERROR
7 s% J; h8 {1 R* ~ l- Z0 i) || MCASP_RX_OVERRUN);
. k( G9 }: ?4 Q( A3 t5 Y0 e/ W( L} static void I2SDataTxRxActivate(void)+ Y- d) c! G ?7 l$ t2 H# M& @
{
. ~4 |+ m) Z; T2 x/* Start the clocks */; h) v2 `) p' [* |& s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: Q! \6 c( Y% N7 Z' a, L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 L {- x% I# k9 \, F& }9 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 f# a1 M f5 L; ~7 g% r5 ]" aEDMA3_TRIG_MODE_EVENT);% z) @6 q# A2 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ ]" s$ P; N5 QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 H3 F% C& _/ m5 M: `( C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* H+ ?/ ?( i2 e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% `4 M; @+ c/ [1 s$ ?0 L0 cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 T) J( b. {% S! g4 V$ X7 X, V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 i. d5 i$ t( ?7 a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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5 W1 J3 v' \5 w- w/ u& }4 T& _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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