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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% {# ?4 G3 t* Y7 R% L! N8 qinput mcasp_ahclkx,; f8 @% X8 n5 U8 s& e
input mcasp_aclkx,
0 b B8 J/ Z2 k/ Minput axr0,
3 B3 H; |& ^# H8 T( ~, H! m. _2 J8 S0 l
output mcasp_afsr,
3 Q0 _0 y: i O; T# Foutput mcasp_ahclkr,
8 W/ P$ i* D- C0 F) Q2 u7 c! H! T" Uoutput mcasp_aclkr,2 g1 U; c( E8 R3 [, l t* n
output axr1,0 a, g4 j# `4 C! H: f% u
assign mcasp_afsr = mcasp_afsx;% E% [0 Z. [9 n1 k2 g
assign mcasp_aclkr = mcasp_aclkx;! y+ L4 @. H# J3 i
assign mcasp_ahclkr = mcasp_ahclkx;, @6 Z' `3 f1 J! N9 ~+ ~. D7 o
assign axr1 = axr0;
+ k! [$ S$ O- e; s6 b. A5 ~
; F- c9 E8 v) Y. O* d/ s' D- G) |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 I; h( u: V$ B* Pstatic void McASPI2SConfigure(void)
3 v" Q: r1 t( U: k1 d% f{
1 g# z/ P w: I \1 |McASPRxReset(SOC_MCASP_0_CTRL_REGS);# j$ W/ w! K0 ?, p1 `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' j+ \2 ^: Z- _& w- s+ N( cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' F$ {9 g: w9 l5 \/ D/ g( Y* e# HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. g3 @& i5 q0 I/ y' UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; ?! V$ y. p8 c9 YMCASP_RX_MODE_DMA);
" M+ s* {# m7 P% AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ _( i* O$ v/ a. dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! c& [* n; S- f n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, h) R) i5 k& s* t! }8 WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, z) x1 b2 y6 G3 H, ?( O6 ` r5 B0 k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * f# q g' F: [6 F% t* |9 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) g6 m& ? C' H9 n1 `$ z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; u, u V' g6 H/ p, W \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) ^; U/ T- Q/ a7 J9 J' u7 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) H5 U& d F7 P t# z, F2 N0x00, 0xFF); /* configure the clock for transmitter */& \! a3 n1 F( O( H$ ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 a) V/ | C9 o* I0 GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 W: P. c l2 p7 k/ |, ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 K/ P3 {6 k# C* m0 S
0x00, 0xFF);! D! W% k; G4 K/ Z0 t
- \( u+ W: Q. ~8 n/* Enable synchronization of RX and TX sections */ * w i4 E2 [" X* W3 |: C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% g" l; n: X J7 K4 D n! v2 |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( `: M3 x G. `2 n6 h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ V% S8 Q; J. l; z) X& M; k8 H
** Set the serializers, Currently only one serializer is set as% _6 M& e; a) x3 U4 `1 Z' b
** transmitter and one serializer as receiver.4 f9 K: M! A- k1 o V3 U* ]
*/
2 J' \' ^! f" w# w: vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: R4 `' T0 K* H8 F6 {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( a' w# n: p, a$ J** Configure the McASP pins
6 a6 B6 k; C) r; |** Input - Frame Sync, Clock and Serializer Rx
) c% n6 p9 p" [, V& S** Output - Serializer Tx is connected to the input of the codec
4 M$ d# p- A3 t% H*/
$ w! G3 v+ Z3 k7 Z- k6 L0 ?# HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ k$ k1 Y, Y8 _, O! aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" ?, p, G6 G* n- Q ^& K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ J0 `. A+ t0 G. k0 C' u+ J2 B| MCASP_PIN_ACLKX
) _( b: @4 x6 || MCASP_PIN_AHCLKX; D: \+ a! B2 a0 R# @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' {& D; Y$ A* S1 \4 V5 s5 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 Q, G5 S: ?5 t| MCASP_TX_CLKFAIL
( i5 W; P7 f/ [, P/ _2 F X| MCASP_TX_SYNCERROR
( m- Y. @& x8 P+ c B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 n7 l8 w7 O6 e& u| MCASP_RX_CLKFAIL
0 n" L# q0 P; l| MCASP_RX_SYNCERROR " n& F$ }" ]( W$ Y- x& _6 K# o
| MCASP_RX_OVERRUN);; {, b. \% t$ F) w, M6 z( j
} static void I2SDataTxRxActivate(void). ?* e. M/ ^7 n0 e* u
{4 s3 c2 H( A! j, m. o
/* Start the clocks */9 x, V5 ?" E! m5 a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ h% \8 Q4 E; \; Z0 d9 }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 c. t& O; W% I3 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
O6 O e+ ^/ jEDMA3_TRIG_MODE_EVENT);
4 d7 p% J2 {" Y! P" c6 | x- N4 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 L) H3 a$ t( m4 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 }# B# W, g/ L8 r4 L* s8 B3 N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 L4 q1 }* E/ }! S+ l- r4 f9 E. `4 w2 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' ?) Z# f3 [% D- y- Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ S- b+ Z. S2 S3 l- z/ n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ f. P9 |0 n2 bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS); N6 P- s3 B/ X7 n1 i) K' q3 M6 ~
}
* R! T* k* C: H, `1 V3 F: o: O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 F' M4 z( ~7 r/ p% X
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