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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# R& T5 A, X) E0 iinput mcasp_ahclkx,
3 R/ C( o& I o6 a4 zinput mcasp_aclkx,
% t( p* B& k0 \/ y; q1 Ninput axr0,% \' i( s& v8 {- b+ g
' S! c3 w( g: ]( L/ v e
output mcasp_afsr,- r O. x, u: |: W
output mcasp_ahclkr,
: ~- h; s& [) s( Qoutput mcasp_aclkr,- Y# X7 ]$ H% B6 Z2 B9 M
output axr1,
" z' V3 t$ c! ]4 T: D assign mcasp_afsr = mcasp_afsx;
! P3 v+ |6 U# K2 @. J; z3 C' xassign mcasp_aclkr = mcasp_aclkx;
4 I8 @" L2 W: t. Hassign mcasp_ahclkr = mcasp_ahclkx;, [3 c# |, N8 t! b; p. N8 s; N
assign axr1 = axr0; 3 R/ O% d2 B" ?% b+ E
6 P; t) u) D& u0 p. A- _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 a6 b3 ~4 }/ b& cstatic void McASPI2SConfigure(void)
% P9 r% m) d- [& r' I{
x5 e) _! c4 N4 r* ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
j6 f7 i/ ?" ^5 M3 t; HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- V6 Z; d# f2 ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 C- b" p' q0 v: L. G) `) k" W* t4 Q* z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' E* {9 V, Q' y' T8 \9 W1 }! p6 B1 j* }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# H x8 F% ~( X1 h
MCASP_RX_MODE_DMA);* r, d4 C8 E/ I& g+ a& b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" B# @/ C9 Q8 K8 ~: s, AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 W1 C$ c1 N, |( I$ Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # P* [+ X( H3 v' |9 \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ F+ i! Y4 U( B& E q/ f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 `2 E8 e! q- F; g6 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. r+ _' x4 Y! U% v) {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& z7 ?% A" t, s8 `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ E7 l+ T! |7 c* H$ D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* O5 k* K6 x7 ]1 M P. p% Z2 x0x00, 0xFF); /* configure the clock for transmitter */, g- \. o( ^. H: {) Q! f( |, _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" i' B# z% w5 _3 Q8 h- ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 @' D0 W# s, b6 s1 P7 ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- c6 e [+ X! Q- C0x00, 0xFF);
" t3 C# S5 c/ Z8 z! _; e% ]; d
8 A) i7 w; `- Q* _* z/* Enable synchronization of RX and TX sections */ 0 q2 h" z( D# w. N3 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: V+ I% Y4 A" C6 W( s) f& DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" V: N& F+ _" s; |$ P) x. S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
A1 z3 P7 R& V1 y% U3 w8 g) N** Set the serializers, Currently only one serializer is set as# L2 n8 P4 A" O- ^
** transmitter and one serializer as receiver.
0 P5 z' `. Y( P: A: m*/2 I, O6 `3 t% i6 k8 l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 o* _9 C. `" z/ j2 ^, ?: l1 n$ w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- O5 I) O' I8 C, ]3 x; g9 u** Configure the McASP pins
3 @0 J D! _ B** Input - Frame Sync, Clock and Serializer Rx7 Y" ?' h: A9 @9 M
** Output - Serializer Tx is connected to the input of the codec
{/ y5 L4 N9 m*/2 Z/ T9 K- h0 W* r# x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' I, W: X0 ~) g4 |3 p2 x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) W* E% l( J. c( I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: G7 U* Y F' N, B& u# z| MCASP_PIN_ACLKX
z" m1 U6 ~) w4 X8 T9 R: q P5 X| MCASP_PIN_AHCLKX
* Q- c6 k( q1 i! H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; m: G+ S& q4 oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, P, c9 u9 h$ p* E% I| MCASP_TX_CLKFAIL
) n) }+ g# _$ j3 A1 y+ s% R2 P| MCASP_TX_SYNCERROR* U! m5 I/ h$ l1 _0 d- a6 ~/ q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % n' u$ _1 }( s" d
| MCASP_RX_CLKFAIL9 y2 T7 x. r( Q7 g' y: e( y J
| MCASP_RX_SYNCERROR 1 ^" t( |; p# r4 [
| MCASP_RX_OVERRUN);
B3 Q3 z9 w5 j' ~4 @} static void I2SDataTxRxActivate(void)! C0 x3 L, s9 l- e
{* x6 ~4 c0 W J; \0 G' H
/* Start the clocks */
) f. p1 x+ H7 R/ k% D. h9 ?" xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 }! X7 L1 A' n8 e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; Y# c6 C9 u/ O1 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; X4 h- [% v# l) n5 ?' h5 u5 q9 m: HEDMA3_TRIG_MODE_EVENT);* t6 ]: l; _; I) y2 R& ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! o' u# U- ~3 M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 e* i6 i ~' Y7 W) i0 \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 @, B* W1 {) W% \& r6 \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! D( J" F& W ~! Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 K# C3 p) r: c2 Q- mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; D' W; U7 o$ q; S" M/ n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 s5 j: Y a( n3 X, q. o O n" m+ y; M} - u, B. Q- Y8 ^2 F% K0 C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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