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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ Z0 ?2 J2 W* o5 K( M6 l: g
input mcasp_ahclkx,
" m/ B$ U4 e0 u c/ `& b; Uinput mcasp_aclkx,
, x$ i! M: @: k$ G+ kinput axr0,7 @- p! t6 l% \6 r- G! ~6 f! h
2 V( q. }# P" s( P' W4 \# soutput mcasp_afsr,
* G/ x+ E: K: |: o2 Ooutput mcasp_ahclkr,: |1 i' i. Q# s3 H3 V& ^1 {
output mcasp_aclkr," l) Y7 `6 z. h
output axr1,3 O' M( W0 e: H, r- P. R- M2 _
assign mcasp_afsr = mcasp_afsx;+ o* w( L- t6 M3 v: ~
assign mcasp_aclkr = mcasp_aclkx;
7 f1 M, J1 q/ Y. e0 Cassign mcasp_ahclkr = mcasp_ahclkx;
* W; |; y; a, g' X5 _% }. Y3 Z! {assign axr1 = axr0; % i) ?3 R9 `* ?3 v' D5 X
: E* G1 D* y# ]9 G. A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 A7 M( U, T' j/ B3 X
static void McASPI2SConfigure(void). }, n5 s$ I* J2 I4 v
{
% E* }0 _6 Q0 J/ p# [McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 |% V" t+ P- k2 \8 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% p' x9 n, X0 p+ Y" Q, e" e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 R0 b/ s& z2 g% Y4 l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, j# M) G1 ?) m6 N9 aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* l( D+ K/ Y" w: D4 x
MCASP_RX_MODE_DMA);
5 O+ V& T3 S8 K4 V/ V! C1 CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 o) P& x3 _$ ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: N4 D8 H% F: JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; a1 h/ k: m4 {/ N6 i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% a1 l* w, `! X% |5 q& I, ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / a! U: k' l) Q9 L: c5 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: g' C! z1 f6 ^7 e# }) A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 Q; J) k% ~7 jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 C2 B. j& `' _" V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- B4 |! k& D. s) f! H; b4 H0 u0 H0x00, 0xFF); /* configure the clock for transmitter */
1 h8 N- r1 V' `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- V, f3 k5 @# ] Q! yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( u6 P' ^8 O# D! q8 H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 r \) b, d v5 r+ U0x00, 0xFF);/ Y- \# z( ]5 G
7 n2 p8 r' p0 i, N! a0 b
/* Enable synchronization of RX and TX sections */
5 p( p8 y8 }' c+ h3 SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% g" l8 G/ N! T7 J9 p) _$ C- IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' \2 g) T- r/ _+ [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ N' c, L7 M1 C1 ~) t
** Set the serializers, Currently only one serializer is set as
/ n7 E6 w/ m G v9 r* {! G' n** transmitter and one serializer as receiver.
! Z' Y* v: j1 j6 b. C6 N. Y. O# W*/; M. N0 ], |" {# W. B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 y4 b) m# t1 S ]& t- j: z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% a3 a2 k! g' ~3 c1 I1 {9 C2 [% K** Configure the McASP pins ) N: ^0 Z2 x3 F2 X4 ^ I# K' N
** Input - Frame Sync, Clock and Serializer Rx1 W5 ^) k0 O5 V- _0 T9 o3 }% o
** Output - Serializer Tx is connected to the input of the codec
. ^, ~) @7 K' S*/* y/ u" o3 H( W3 H! { V: ]7 I* _( F/ m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 b, |1 k4 \5 a) _; A! @ ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 }8 G, m* e9 \0 ]; PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 l1 e. Q1 ]4 A% e$ ]
| MCASP_PIN_ACLKX
- X, Z# O4 Q; Z9 ^| MCASP_PIN_AHCLKX
9 B" q! ~. Z0 S" h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ H' E: D' [6 L$ xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 H: w9 |8 @" X5 X, s& v# L| MCASP_TX_CLKFAIL 8 i/ }% t1 F8 Q0 O
| MCASP_TX_SYNCERROR7 @% m1 Z/ H! b$ E# ?* k- O/ ]: ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 ~* N, f( s* b3 u| MCASP_RX_CLKFAIL
* f% y+ q# W5 t- L% [- W| MCASP_RX_SYNCERROR
5 O" h/ r; s0 P, B% e0 M; W x| MCASP_RX_OVERRUN);1 y: `4 Q) v! [' J9 Q
} static void I2SDataTxRxActivate(void)
' u5 A& F' J' B1 F' i( a1 f- S{
: x: O* E" E7 U9 W/* Start the clocks */
, C, ^, C% E( I& I; k- L; OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. p. r- a* E: {1 b) r1 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; F3 I* r" f, n ]0 u+ p5 C' vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: Y; ]5 m' g$ g. F6 i1 z R
EDMA3_TRIG_MODE_EVENT);& } x# s- \! N; u+ Y; l4 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 T. I( O- C( p7 V, a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 q/ j% T+ ~; E' \" kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ d$ J# t8 T$ _: c# QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# M3 i T/ E9 s) E7 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ b6 q: \8 Z9 q, }- Z* }5 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& S! D- `8 R) j, Q SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 I5 r! N0 }5 y* F4 f3 {5 `7 l} * K# b6 F& Q, l! A# u6 U% L4 y( F1 G8 w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - p# y9 u! }, k. u9 }+ }
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