|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 R P6 H/ b) e- R0 q$ h
input mcasp_ahclkx,- K/ P% n% W9 d0 \% [/ C
input mcasp_aclkx,3 Q( P: F0 e2 F& F& E7 Y* u
input axr0,
6 P/ m1 \( W' ?
% s% Q8 ?; N; x5 N, H" Z2 Goutput mcasp_afsr,2 w3 u' s" j# m& k
output mcasp_ahclkr,
: ?5 m" c; E! L0 T) ^/ koutput mcasp_aclkr,4 g7 I( F: l8 W
output axr1,+ U6 f- A) r* R, \. y
assign mcasp_afsr = mcasp_afsx;
8 x: H: d9 r* c" c* r. W: hassign mcasp_aclkr = mcasp_aclkx;
& j3 X0 x* X# F# wassign mcasp_ahclkr = mcasp_ahclkx;
3 `. {# L, K* {assign axr1 = axr0; . Z! H. p0 r0 h/ E( K
( Y h- L3 B% ~$ g4 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 {" \! ~9 N. [3 X
static void McASPI2SConfigure(void)' I6 A7 y7 `5 P
{. y: O! U: u! U' p# H) x3 g) e6 z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 |% ?: Y f8 v' ]# A: t+ wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& S! I- I$ H. `; m2 {8 b( v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. R1 h9 _6 t6 eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* x: p% h n7 l! ^: ~. HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 j# ^, h C6 mMCASP_RX_MODE_DMA);) ]5 ~! U% _% j, f1 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" W1 J4 ?' K7 h$ a1 g' H3 XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 k; x/ y; H4 y, r0 H' j+ G! tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / j8 L; W' _ \, F2 J: |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" q9 m$ G* {. o4 \) h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) V# H4 E- o6 Y4 ^# tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* d- ~, d8 ~2 `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 j( x. M8 b7 \ C( Q2 KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' v1 V# P* y8 X" `) ^) D- K) k4 ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& N# `7 @, @( t* `3 ~
0x00, 0xFF); /* configure the clock for transmitter */
. O! L6 ]4 u9 u9 u* z1 BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 p( K3 ?5 I% {7 P- }; p1 n% m" zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ o' @: E* S# G' r* r3 bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ _3 K6 ^+ c/ \ r2 x0x00, 0xFF);& |9 u: L9 r Z8 p
/ F( n$ H4 t s) N
/* Enable synchronization of RX and TX sections */
( d, m2 }: f; IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 B7 A# U% O% j0 A2 SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 x. c/ _5 V8 I/ ?1 J# |' }' l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 [/ Y4 H4 p; a8 U** Set the serializers, Currently only one serializer is set as
1 c, J5 q& M! T* Q2 S# {** transmitter and one serializer as receiver.
& e% O" x1 X$ R4 u$ n0 n+ \*/
& ]3 j( ~" }# }2 C* d9 KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 Y/ s& i4 H, K# u6 m: ~6 o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, ?* l( ^$ T2 s1 }* Y** Configure the McASP pins
/ I: K Q z1 Y& c( p** Input - Frame Sync, Clock and Serializer Rx
; [& u n# v% `: Z** Output - Serializer Tx is connected to the input of the codec ; ?) P* j: K$ P) Z
*/# W& I# C' E9 t G% P, K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* U3 M1 S: K1 \3 J) S; o2 D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 W$ q% S$ g8 g& o. z4 C* Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& j: H: T+ ?7 A6 P| MCASP_PIN_ACLKX. E X8 r2 s/ t& Z
| MCASP_PIN_AHCLKX
G$ ]1 n- Q# @7 `( J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 \: n- v" M6 ~: J0 }9 ~" xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & @( I: {. | H: w% ~4 l, r
| MCASP_TX_CLKFAIL
! p2 z) Z0 v/ ], K) e| MCASP_TX_SYNCERROR* p4 ` Y# ^) `" o3 f3 w6 D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * E K+ ?' `( J) {" K K- V
| MCASP_RX_CLKFAIL
$ s$ S! H. L( g4 C% e/ F# Q* ]| MCASP_RX_SYNCERROR 9 O3 L7 v8 n1 G- T Y& r
| MCASP_RX_OVERRUN);
! |5 p! Y4 U7 I$ b} static void I2SDataTxRxActivate(void), f. S4 f. w2 Y$ _2 {
{/ M$ i9 m9 p7 R7 I0 q
/* Start the clocks */
/ ^7 X% w4 c4 R, g3 l- L6 oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# S, a: _* T# m4 j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 G. e& Q- v8 f2 w7 j% |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* ~" @. G$ J: t
EDMA3_TRIG_MODE_EVENT);
( G% D$ w, o4 C0 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% f' b7 `8 S& V7 J/ f9 F# _) F6 {5 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' e k8 b+ D) w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); P6 _! c7 F E4 J/ T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& i% t9 @4 `- j, O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" q; d1 s$ v: h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. u( `* x0 @2 y. ~. a2 gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( }8 k- S' J* A" V3 f% ^} " W0 \0 q: R/ w3 f7 @" b3 M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 k# n" c/ z$ M) v9 X |