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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! k. p: e3 z2 d, F
input mcasp_ahclkx,( h Y& X8 ~; J- A# y
input mcasp_aclkx,
; r0 M* T6 C0 o9 a6 _( r! Xinput axr0,2 P+ a8 M1 K6 b" o8 G
3 q) [; N4 Q' d% A# v% A- w/ _output mcasp_afsr,
! J- I/ @5 I' T* Ooutput mcasp_ahclkr,, D- n6 l* M" }
output mcasp_aclkr,3 f$ P/ r3 {: N6 W1 ]2 Z
output axr1,
9 d. s7 a- S; D assign mcasp_afsr = mcasp_afsx;9 k3 B r7 D; N3 ?$ v
assign mcasp_aclkr = mcasp_aclkx;
* g" v) {% t. U5 sassign mcasp_ahclkr = mcasp_ahclkx;! B Y' t) v2 ~4 P" T M: @
assign axr1 = axr0; # w, h1 N+ ?; X8 l9 G+ L
" e" B' T \2 `: M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 q9 m+ u6 s' [# K. d3 l
static void McASPI2SConfigure(void)4 K* P& B$ z; |( O: U! u
{
0 u4 Y' D( v' J; y0 a/ K9 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* c0 l* ~% k3 H- }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 q# ?4 e2 f1 n& x1 T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 S3 s& {0 `# X* w; v, `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ q: M$ d3 d1 V5 J% }. c* U( pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 b5 \3 f/ Q- b `2 `/ fMCASP_RX_MODE_DMA);% t" c$ ^3 m% i$ w& Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 X; Z4 r8 F- t$ |* }6 MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ g" y( t# l% F% L) e$ AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, y8 `+ \7 g. h: Q) K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. v" f& J- }6 U3 d; O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! c) m) i1 [7 B1 O0 ~4 S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. b% P* m5 B% H, GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 P |9 @1 }, @% C8 @" U' Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 u9 W3 m/ `7 k% t0 W: J: N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) X% \/ x: q( G2 u9 \5 o4 e' p6 i
0x00, 0xFF); /* configure the clock for transmitter */
+ O F/ J( l# g) L( N; w+ @1 ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! n6 [4 m1 e0 @, q( Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 S! S6 T8 {: c5 X8 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 F. V% C5 }4 f8 N3 i
0x00, 0xFF);8 J3 k5 [# j2 A1 P5 M) @/ C" t
& h/ ~9 E8 B* j3 A% M/* Enable synchronization of RX and TX sections */
( h- D! i* ?7 j3 M! y/ WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" b$ d/ x3 X1 b; Q% \0 `# h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 W5 H$ Q# n2 L( _* K; s1 l: S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! ~0 E0 G9 d% t& |** Set the serializers, Currently only one serializer is set as
4 s- o* b. c& ]** transmitter and one serializer as receiver.' `0 k* w( l: \# \
*/4 p/ \: l7 H) P* U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" S$ ^' N. e( {. _% p4 S% v# z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ n1 P( W/ R0 E/ G' t6 I** Configure the McASP pins 8 r* k/ Z" [3 _
** Input - Frame Sync, Clock and Serializer Rx6 c' z5 B2 h y. S( |/ B) T9 ~
** Output - Serializer Tx is connected to the input of the codec 8 ~. Q) G: V0 Q: Z i" K: I. n, t
*/" N) t, [2 K8 Y0 M. s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 z2 Q6 J' i; m5 F# E& Q* YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ r l# v8 O& b3 s5 T( ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: Y, @2 @& w$ O" V- N: a" W! A8 U
| MCASP_PIN_ACLKX y. `' p8 x% h+ b& K& c5 `
| MCASP_PIN_AHCLKX5 u- S2 R" ]5 s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 f; i- t: C( ^) U hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 S, m; k& C# ]| MCASP_TX_CLKFAIL * P0 ~6 v2 {) i( {7 G
| MCASP_TX_SYNCERROR- P( A; U J" C& X9 C: w( ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* _ C9 {4 i4 B% _7 y| MCASP_RX_CLKFAIL$ q( Y9 _. N: Z
| MCASP_RX_SYNCERROR # J! z- a% g- y& [
| MCASP_RX_OVERRUN);
6 r: q0 H9 r+ x& h" u6 M} static void I2SDataTxRxActivate(void)% r8 X6 P! z7 F4 ?
{
6 `$ e1 v- a+ N+ T1 s* Q/* Start the clocks */
8 o0 E7 d! g# J* RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; H! ^% i9 }& S' G( b- ]' B* i: x& zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. S+ r: z/ ^" @8 \6 f VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 f9 H& ~: J6 o
EDMA3_TRIG_MODE_EVENT);
: J& U1 A# N( V$ \# ]) U$ V, _0 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 Z( |3 [3 r* X6 j! J0 L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ d* y; {$ N5 z" v; i4 Z. s0 s6 @8 s3 r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); v5 J1 G" g9 v9 u; J" A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% X( I9 G) A" x* }- H9 P6 |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 L% n$ { x) N$ a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- p% k% R) |1 s5 ]- B- N7 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 B" i" c, X; J6 ^
}
' \5 ]$ v ^% `9 E7 i9 O9 E6 h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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