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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- `0 d2 w' w* c* S! f, d$ ?2 ?input mcasp_ahclkx,/ p/ S2 f o# ^8 k9 J
input mcasp_aclkx,
, ]) c" ]; }. B' K. {input axr0,
, v( ?1 q2 @$ o' g& p) F/ Y8 J, ?
output mcasp_afsr,
& h- Y0 K9 e0 k. J7 x& ]6 Xoutput mcasp_ahclkr,
% J5 W8 M1 {. n Houtput mcasp_aclkr,6 B$ {; [& C" `. e8 ~
output axr1,
r* _: M, c8 J& s$ \9 N8 c assign mcasp_afsr = mcasp_afsx;
' R! d2 {; [ R) r$ ?& Massign mcasp_aclkr = mcasp_aclkx;
) B* M; ?) J6 [! s) M' h" Yassign mcasp_ahclkr = mcasp_ahclkx;
: x0 V6 ]( b" X1 `) V# uassign axr1 = axr0; 3 _6 ~4 c2 ], V! ^( \: q' M
5 N/ Y6 j& x2 u# E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 c! a$ K" Y3 }- n4 D. ~2 p X& N
static void McASPI2SConfigure(void)2 L8 |% m; ^! p: C" b# ^
{) x0 h6 K2 v4 U4 u5 J1 C) R! _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 c5 H$ x9 I6 w- [" b/ yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 \1 {, Z4 T% z* v/ L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# s0 h3 f' w5 p" x. J4 J7 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* P) L: B; `; w% S- b, G/ yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 @5 S9 w+ T: v4 EMCASP_RX_MODE_DMA);) Q. f! X5 v5 f3 m" T$ [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, p* x: b3 u$ A/ ^* B2 `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% j0 ?8 \9 `- x) K1 @2 AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , e ` @9 S7 L' D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- S) X5 u3 a% A) { X" R* AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ y! @4 X$ K, f! m1 VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 |/ q5 m1 p( b7 k' Y" ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 o# E( w2 w+ L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- D, q9 t, F& o. D. hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# ~1 X1 R. u5 _" ?" c! ^
0x00, 0xFF); /* configure the clock for transmitter */
, {) J3 L; n7 [/ V" I2 S3 fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# _% K8 M+ U8 M9 e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); {' O, K1 I0 L! y7 U' C" s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 u) X ^$ Z- H% U; X
0x00, 0xFF);' `5 g) G9 z; O3 S; d m8 K
4 h( O+ V# H) q0 g+ r
/* Enable synchronization of RX and TX sections */ 4 c$ }5 e$ z J2 K: T; |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" w4 a1 U( Y( ]- d+ S% k9 z4 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" o: [$ C& l+ K5 Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 E+ [" f- G9 _7 p! p8 X# y. z
** Set the serializers, Currently only one serializer is set as
. L8 @8 S4 ~$ Y+ P+ l+ b** transmitter and one serializer as receiver.3 [, e: m3 R" n% u4 k% L3 d d0 G2 ~
*/
9 G- A. m5 I- M% L8 UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 J( T g3 B) i2 \3 m" NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- f1 ` A7 j* L, v5 i** Configure the McASP pins 0 r1 K1 _7 B; Z6 U7 ^- M8 i
** Input - Frame Sync, Clock and Serializer Rx
2 }0 A1 t. g( e( B** Output - Serializer Tx is connected to the input of the codec
' f* ~3 P7 W9 P) Q7 j*/6 u* |# F1 C z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" j" q( x0 j: Z+ o, C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 D; j" j4 ]9 J1 T* [# xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% [2 a/ u _) q# t2 h0 I1 O3 P7 G
| MCASP_PIN_ACLKX8 D6 S3 E+ h; r9 x
| MCASP_PIN_AHCLKX
% ?$ I; D4 a6 K8 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ T+ Z H: M) m- qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 }' E+ x( J8 c$ {3 Z| MCASP_TX_CLKFAIL ! P3 E8 L8 o2 n$ H
| MCASP_TX_SYNCERROR' {! a+ G7 X0 X% Q7 y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 v3 L+ ]' X1 K7 D+ f* t) a, U| MCASP_RX_CLKFAIL1 ~ w' p8 v" c5 a1 P8 I8 s( G
| MCASP_RX_SYNCERROR 6 }5 K' U/ L" Y% U( @, ^2 Z
| MCASP_RX_OVERRUN);
" s+ k, {; F+ i" D& x& I6 F} static void I2SDataTxRxActivate(void)
?5 ~% o) a$ S. K t0 ^9 J{+ L/ G o- R3 V. J
/* Start the clocks */
$ `1 r$ {9 H9 i' \% IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 K6 c5 o% c, S. T0 j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* D5 J9 w+ k2 ]) Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! A% n6 i* m( h7 s J: u8 ~$ dEDMA3_TRIG_MODE_EVENT);
5 i% h/ H% F5 t# o( ~0 I- DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 m4 }) L. L6 ?5 p1 E- h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' P, x( Y! q" b* ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 N0 v) m' ^# o# {+ ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 C$ A' H) @$ Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) X! u! C, c; M- X8 Y* E* ?5 GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ y2 @( {+ {$ q- IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 R& p0 u# C7 f8 j; j- B9 m' W
} : n; \" f5 n" K% E/ B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 s% }" r" g g' J; b8 J. Z6 x
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