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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& @& J/ ~/ f! j" f: p& D
input mcasp_ahclkx,7 a! S7 a+ m- I& P, E* R
input mcasp_aclkx,
5 ~2 w& r- S! U7 S2 u/ minput axr0,
" v1 I# {+ o4 D" S" @$ k% o& ?& _) V3 v$ _" L/ g
output mcasp_afsr,
9 M7 _ [* m5 boutput mcasp_ahclkr,
, z" |" b# x) W: F$ Uoutput mcasp_aclkr,
& d3 p! k2 ^" M! W5 N7 p4 K& uoutput axr1,' m' K9 }% W# n5 V- U5 c/ Q8 Z
assign mcasp_afsr = mcasp_afsx;
' ~( S1 P ]; J0 W4 s2 y; ?assign mcasp_aclkr = mcasp_aclkx;
7 `( v# @. T- u/ }assign mcasp_ahclkr = mcasp_ahclkx;
9 W6 S( a; s& q1 _7 ]assign axr1 = axr0;
- J" u, Z* C; r2 @( z- g$ c7 w5 C" y
) T8 } |; g7 S, F# C5 }9 X; W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . y- m8 A9 q1 V# u1 ~: U
static void McASPI2SConfigure(void) w8 t1 M. i/ t4 ~; o0 t2 y/ f
{
0 B" ^' t5 d. p" Y, FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( \7 t, w/ B% t% \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ P1 t% o5 k* p4 V. l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% Y' o# n) C& ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
r& u- ]6 _0 qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 [' R" o1 g0 A) oMCASP_RX_MODE_DMA);* s/ z" r. L( ~/ L( g2 T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, W4 a' e3 W& L' A z. z* i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ r C* U; O: q1 TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 A( H. F3 A& e2 d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- n+ ?9 C1 T# t1 i q# l; Z5 [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + ^0 s3 n9 R% [1 T" V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 M. p7 z1 S! uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 K5 S& \* Z( \4 ?9 V) KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " b, \3 i/ {& b& u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
f- H4 i4 q3 ^. c' S" L, H* B0x00, 0xFF); /* configure the clock for transmitter */
r( F* ^) u: T, X( }, aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' x, K+ u5 a6 l+ y( g1 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 _1 x1 v" e/ P7 Y0 ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 e6 K4 q. D! I* e3 F% p" {6 S
0x00, 0xFF);
) m& D$ l; \. O. {, ?4 p5 b8 P3 w
/* Enable synchronization of RX and TX sections */ # I+ M- n* r3 b( L" L) L! a* r( I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, }; N1 \* w7 Z, @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! a4 Y& m+ _4 E; ^) HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 u+ B) f6 Z3 l" Z** Set the serializers, Currently only one serializer is set as
8 S( @2 Z/ d, R# {3 P** transmitter and one serializer as receiver.
) h( b! [& Z5 z7 j*/6 o! Q2 k, n) o& l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; s- d! q; z( r9 ]8 Q dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( H( y3 U( Z2 z& |
** Configure the McASP pins
/ B* \. Q9 L3 O- k$ d** Input - Frame Sync, Clock and Serializer Rx
2 p, L( s" t6 `** Output - Serializer Tx is connected to the input of the codec
; b* s$ s, a% d4 Z; s$ L*/: [; b, i `( D0 w1 d" [8 d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ x2 y/ {& @. }/ @/ S* c' ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 z1 {& I0 |. P: uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: T. \( H$ h6 A7 n( P& e* I+ H) b
| MCASP_PIN_ACLKX" d% w [1 a, Y+ z
| MCASP_PIN_AHCLKX
9 W* ~7 ?* K( H8 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 ^/ x) q( G* [& h/ x9 T9 t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- c. O( ~% B0 f1 ]! O, Z| MCASP_TX_CLKFAIL g1 a5 j7 {$ Y( i- j7 u; Y! `% r
| MCASP_TX_SYNCERROR
9 _$ n6 ^ X& F3 f& A8 ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& p5 F; Z7 M8 V| MCASP_RX_CLKFAIL
/ F; m. c& P4 v1 t4 e" l% p| MCASP_RX_SYNCERROR
( B; v$ W- z$ C# O% b" Z) z! F| MCASP_RX_OVERRUN);7 j) L' g7 W8 h" I
} static void I2SDataTxRxActivate(void). c8 V3 w. \# p& N% y# P
{
- z$ [$ Y6 S5 Y! M; H, `, _/* Start the clocks */& D( Z" U: _1 i6 s- G* }, B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) N0 m9 f- l, V! ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 c+ H8 ~' p# I YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- g' A: t- u. \, V' m& }1 J
EDMA3_TRIG_MODE_EVENT);
6 M4 @/ ]$ v% m) ?5 R- ~, LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 N# T, E, W) {' qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 t4 J5 j* A8 W8 m. NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ S" B1 o* m+ X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 \' X8 }) ]( Z! [- h0 ?: ~! @% S3 D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 O) N9 i( z% z! G1 g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 h9 L1 m; @" Q& c. G; B/ g/ dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" l3 A4 h: A& \- n$ H# x} / g* a8 t, v' b l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 {1 \" w u5 j2 B
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