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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 ^+ z( M( X# A! `9 F) ~
input mcasp_ahclkx,9 M( _: s# f& g8 S: P
input mcasp_aclkx,
4 s8 C/ @3 s6 i7 f5 K9 Yinput axr0,. H: ]1 M4 l- V' s$ J5 z: s5 O
& M/ H" m9 x+ [- Houtput mcasp_afsr,
$ W8 ?" V8 K2 moutput mcasp_ahclkr,
- Q6 n# c7 {/ L) E& a B6 Routput mcasp_aclkr,8 W6 E' U# x1 O1 j ~
output axr1,
2 A: U j6 r1 k. t6 B" y assign mcasp_afsr = mcasp_afsx;
: O ^9 |% u. f5 A! r. Rassign mcasp_aclkr = mcasp_aclkx;! s2 T0 O# x! o" \* K
assign mcasp_ahclkr = mcasp_ahclkx;
& O$ f& \% b, [8 n8 E# `8 Tassign axr1 = axr0; 8 y3 C1 j& ]% G0 R
1 V. `. G; i: o2 `) n; b; e. e/ [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) X, j" X# A+ L! ]8 nstatic void McASPI2SConfigure(void)
* V7 f; v. O- ^. U( M; X{
+ E, x. V1 b1 A/ R, U; ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' }5 ?1 E/ Y- `! ]9 f! G& HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// {3 D( L, [5 p$ v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: o8 B j& S: k0 d5 hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# w6 G' Q- x3 J' T/ K2 S0 \4 ?; BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- w- _8 A8 g. U" t# DMCASP_RX_MODE_DMA);! ^5 H: W) r3 K3 p2 S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( ], U) C: ?9 t" ?7 p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 s$ p1 B4 ?9 B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! v: h5 D: C b$ i4 R* M* t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# u. v, i/ Z2 e$ fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; A0 Z5 y% s7 B* s2 ]! g2 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 s# A4 d2 i, v/ ~# P9 }' b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( \. r3 W/ z w4 q6 o# f3 c% N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 ^. w- q; _: s2 gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& }7 k2 Z2 @3 ^* y/ U0 M( G$ g
0x00, 0xFF); /* configure the clock for transmitter */
# h: h K3 @9 z5 F/ c5 n( m7 `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ x. ^: z0 b) a) z4 a/ }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 M: C8 E4 G% L" a3 m9 [4 WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- n0 e9 r+ h4 R9 @
0x00, 0xFF);, m* [ V; I/ S7 l+ r
) O3 N0 @" X# r4 n! F! s1 [7 O( A
/* Enable synchronization of RX and TX sections */
* W; F/ ]# {, J( _7 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! x2 X0 X6 G7 e/ fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* F/ m) q5 f: J! M/ N* U+ l; KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, x( n: F9 ^8 ?) D5 G
** Set the serializers, Currently only one serializer is set as( c# f4 g% v9 P5 b$ i& S, g0 L9 \+ Z! T
** transmitter and one serializer as receiver.
4 o, u% i D7 a8 k: `! k/ g*/ _ l6 x* o: I4 k7 x! C& K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 `* Q( {3 k! R/ a$ |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 v( T* O" z& [/ f** Configure the McASP pins
" \7 j4 g, q, C' t3 |9 ^! s** Input - Frame Sync, Clock and Serializer Rx
+ T6 F5 e; n$ f* z8 x** Output - Serializer Tx is connected to the input of the codec 3 q7 x' i9 A2 P3 j. l3 Y$ U7 U6 c" j
*// a' q' O$ y: f: D: A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, F; I% d6 N0 [4 n6 L' KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 o$ p; k4 H4 F( z2 Z! u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 I' B7 Y7 t: k. m| MCASP_PIN_ACLKX9 ?% v9 S Q' p/ \6 I6 T& X
| MCASP_PIN_AHCLKX9 Y5 [2 P: @5 R6 \3 A5 c9 M9 S0 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
q9 i1 h1 B; }, a0 |) n* DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # p; W C' A8 }
| MCASP_TX_CLKFAIL ; C1 o& f' ]( G
| MCASP_TX_SYNCERROR
n; D2 ?+ o( ~( u( i) ^1 p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 m8 m( H9 h8 r! W9 h! `
| MCASP_RX_CLKFAIL
: ]* n. T; \# K! a+ S4 U) I| MCASP_RX_SYNCERROR
; Q+ j n& m% W1 s5 d" S| MCASP_RX_OVERRUN);
; {, h h/ Q) |2 F$ r4 j} static void I2SDataTxRxActivate(void)
6 {0 j3 ^# A. R6 F! Q& @{
: J( d" {7 G! G7 q- F/ F/* Start the clocks */
3 D6 E5 Z5 [ f- V) H& L' wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- Q) K. `: _$ T0 A0 Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& z( b6 D& o* |1 l6 U" Y. CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 e9 h( G* z2 v% S- }. h' ?
EDMA3_TRIG_MODE_EVENT);8 i$ b D6 K- X: L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / N m6 _$ l$ H6 k- d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 t" X( Y$ K* IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. _5 ^6 `5 S" | P w* O' J) G9 r0 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, `+ X, u$ g8 W( `3 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// i1 T q( Z; U- g" m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 v% g/ |0 N# R# a" s4 K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ e- M t& h0 i" M$ F; h: D6 C}
6 Q' j6 U Q# v* _" G, G$ O$ O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % ^6 c! d8 F: C" `4 }. @
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