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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- T/ m' ?) a2 p' |7 tinput mcasp_ahclkx,
& T' n5 r0 R; J+ F8 {# [input mcasp_aclkx,
! F$ E8 h) j5 d6 p" O3 z. vinput axr0,2 ^1 |; v0 y4 N2 N% y1 N, ~3 f
2 S+ q! }& F# V) a* `
output mcasp_afsr,
5 s# k2 h: e8 goutput mcasp_ahclkr,1 ]! C$ l$ c! {# @* R. n9 g/ F
output mcasp_aclkr,
, p9 m5 x! K4 `$ O2 Koutput axr1,# F1 X3 }- J6 ^
assign mcasp_afsr = mcasp_afsx;
2 _. ?, \( U+ A' Zassign mcasp_aclkr = mcasp_aclkx;2 I) k6 q* w' D# Q' Z! A4 ^* R+ p
assign mcasp_ahclkr = mcasp_ahclkx;
5 v* E0 x5 t/ X$ B: j' Z8 n3 uassign axr1 = axr0;
* y$ r3 P* a9 u$ b) |; v
1 p! o1 B8 \ B* ]6 j8 `# ?& \- g+ n' u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 }" f n1 p; N, g
static void McASPI2SConfigure(void)
6 k6 r& f4 c* H$ ^3 L{/ W9 e# l m# k# c) S' W1 h- M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 q6 Y; }: k, d# Z6 @ S* b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 ]1 y, t: y3 K" n7 vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) P! N9 c2 v2 P, c3 J, x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 c1 y( R. b: n; `$ B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 B' Q, [! a/ ]MCASP_RX_MODE_DMA); A% A" \# u1 z: }' l) ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 u6 s2 s5 Y7 J# Z4 b2 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 o( k* B/ M8 L2 m& NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . S' g9 g( p! X% X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); h7 Y, L$ W& G) g" x" v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 i2 Q( M& J, n& IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 s8 z/ ]2 i. U) m. w, A; D! W2 jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 O0 H, s) o+ v% e6 A' ]) ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 W* P! V+ Z" Z2 {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 @2 E9 p0 ?. M0 T: l# b
0x00, 0xFF); /* configure the clock for transmitter */
" I3 A2 L& S3 V6 j' I) T# I3 ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 p+ d* J: C6 ^) m- u1 Y. ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& V7 w, Y3 r" ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 v% T& d% `7 c5 t4 I! W1 u0x00, 0xFF);8 H/ H! }8 K; W3 a" a/ P- u
6 [( q e+ `; q4 Q1 P7 m/* Enable synchronization of RX and TX sections */
! P% D. @( F/ M: V0 Q" A, h/ kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; g% C7 d' H, P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- f2 v5 ^8 [& m! I0 b# S* s, F. LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, D; W T: f4 P v% l6 |% [** Set the serializers, Currently only one serializer is set as' m$ H/ |5 y D: A5 m
** transmitter and one serializer as receiver.
4 V) }" W" M ]*/0 |* V- D& P' }9 I( R% R& k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' v' e$ G# S% s: t7 ~; S1 P+ P$ e4 cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 ~# c1 m a* a6 U0 Q** Configure the McASP pins 3 S+ w% l# o: X9 E
** Input - Frame Sync, Clock and Serializer Rx# P' `# C$ [) W1 t* c. J9 M
** Output - Serializer Tx is connected to the input of the codec
) N; E8 |% U3 c0 E*/
; w9 x* ~1 m/ p5 \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 ?. W6 a* m) }9 `1 V: O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); G9 i& }* A/ X6 \7 r; y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& a0 G0 x- M( w+ Z0 v$ P0 t| MCASP_PIN_ACLKX
$ |& D( h5 t1 D( m) K7 v| MCASP_PIN_AHCLKX
, G1 c( Z3 n. P% U* k+ [- l- m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ Z/ D i5 g4 Q% K2 HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * K, o, c' H9 m
| MCASP_TX_CLKFAIL
! a* }, l U2 l( r5 v| MCASP_TX_SYNCERROR e- t; v1 |# n' f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' e" s$ F: a0 _ E3 G: t| MCASP_RX_CLKFAIL
! e7 b. K4 y1 c: |' i: a' ~| MCASP_RX_SYNCERROR F# L/ o$ L0 ~$ S- F7 r
| MCASP_RX_OVERRUN);9 X- F* W; ~. \4 W% C' S ^
} static void I2SDataTxRxActivate(void)0 w, r; ^8 O/ G+ w
{
2 d& o2 I4 W4 z5 l/* Start the clocks */- M" K1 c! @6 L" A) ?0 y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ \0 ]1 T7 [7 F+ l! g( I" D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- {5 I- S- N+ z# K- AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 |8 v! V+ h$ m5 X' z
EDMA3_TRIG_MODE_EVENT);! V4 s9 M7 T" m+ j: I* p/ Q; O) \9 U0 e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 d8 N0 D* P3 x+ @& t3 fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 r7 `% a, N' C" o4 P! M4 ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) E& t. j& s& y' o% h6 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 ^+ w% Q+ U0 G' M$ |% Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 v1 I1 G+ L. o ~+ M7 l, G T% T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ |- B. L, u; Y9 L6 _; H5 F" a* r+ d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; Z3 y4 S$ P7 ~$ O} 1 v( m+ g8 H7 _ J7 R0 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 x& C6 O! \! w; d3 \1 A
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