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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 @# j# }: Z' L2 [6 x4 b% Z
input mcasp_ahclkx,
; A3 F" W$ m" p7 P9 }' M% k9 Minput mcasp_aclkx,* |6 _6 _1 a4 B6 C: x( P* Y; G
input axr0,
$ ^: A1 b0 n+ ?: j6 P% h
1 ^6 C1 }1 l# i; w I f; woutput mcasp_afsr,5 M' b: A* [$ C: \
output mcasp_ahclkr,
2 X! j0 Z& F- B& O) I+ F0 ^output mcasp_aclkr,! D& \! b. y, \0 h! ]5 p* H
output axr1,
( @6 H8 [8 s I; }/ z7 o2 n assign mcasp_afsr = mcasp_afsx;
/ C& r6 H) \1 |4 _8 v0 Z9 oassign mcasp_aclkr = mcasp_aclkx;
, }- J, j' G1 ^- x- jassign mcasp_ahclkr = mcasp_ahclkx;
5 }2 z) t, Z6 ~9 a( K+ K. j- p: hassign axr1 = axr0; + m1 E- M8 i! l! L( C
: b: F! n( ^# b, O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; F! G1 D' \1 ~& q( ~7 J g
static void McASPI2SConfigure(void)
! N4 w g$ x* O9 r: z: n; [7 v{
! E% k; n9 v) e$ B% N q8 y; uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- ?9 h; Z- e1 U+ }' X6 ?% d- BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* y) D2 U" n) A) [' a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& N- t g: f8 V' B% aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* A% c8 r1 f" _/ o* pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( N8 j @; q( B" ?
MCASP_RX_MODE_DMA);$ M4 k' A7 l' T; c& q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 ^1 q: y& y0 O: J7 w2 V5 |1 Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
s* M* D; m2 ~! Y XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 U# T) [! Z7 n3 Y. t- ^9 M* E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ i" U3 Q* z7 O I* c' H" D& k7 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 V) V( `0 Q2 D# f7 Y8 ~) BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ t5 K; C6 C" q. [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# D' i3 x$ O0 r K: B; r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 q" O3 x6 m; w9 T, TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: g/ @5 K8 ^% M6 ^3 y D3 [
0x00, 0xFF); /* configure the clock for transmitter */3 G. l+ Q+ _1 v8 l: V6 \2 ]5 {0 M1 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: _1 J; [1 s/ X: s9 h/ \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; _/ M8 C) R# NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" j, m+ S" y) F; u+ B4 E# o0x00, 0xFF);
3 M/ S* _2 `& W$ S1 l0 C/ [. |: ?. v5 h% U5 R( l5 i
/* Enable synchronization of RX and TX sections */ + k4 R8 H; a g# h* b. A# c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' H, i7 k9 o8 ^0 J) G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: G2 a/ Z3 S% v: n7 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ N/ n1 ]$ W# m! \- h8 j
** Set the serializers, Currently only one serializer is set as+ Z/ u0 Y: r; P# J7 _0 V$ v
** transmitter and one serializer as receiver.: b" F! }' n6 s( J
*/! R: R6 \) s& ]) X# j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ z( z N# m" e$ M2 R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* L3 s1 C. w" m f
** Configure the McASP pins
. i& N3 a5 t, }" O6 q** Input - Frame Sync, Clock and Serializer Rx
7 J6 U7 U% W# e3 K( T** Output - Serializer Tx is connected to the input of the codec + @) ]& y& O5 M& i
*/# B9 e: B4 @0 D4 U9 i8 |8 N, s$ [ h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- Z) D( _3 \# U. wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! j I4 i# f( M7 v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! r( s, ~. b( N# ]$ s* Q3 t. B| MCASP_PIN_ACLKX
. r# w5 Y- f$ h* J1 _| MCASP_PIN_AHCLKX( M' d$ O" @( @0 ?6 N' A9 o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; l: }3 y0 u. K: C; } ?5 f5 n" k qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& m( e# j9 Q S4 H% ?: w( N| MCASP_TX_CLKFAIL
" ~' D& ~8 h- U| MCASP_TX_SYNCERROR
7 y+ ~3 u3 |% f* M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 ?) i# u; n2 c+ C| MCASP_RX_CLKFAIL
) Q" A$ n. K M/ x4 v+ u6 U| MCASP_RX_SYNCERROR
; ]6 ^# H; Q; l2 N* w* _* G| MCASP_RX_OVERRUN);
+ ^# `; s8 W2 x" z4 V} static void I2SDataTxRxActivate(void)$ g5 d) D- b# x
{
4 Y, r" O' k9 D% d, `4 K4 |3 U/* Start the clocks */
! J- V2 r( @1 e( L/ h$ H' cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
G- Q& D5 X+ KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* x) K: ^6 ?9 x$ n2 {+ ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 ~! A9 Y; t) G7 o1 _1 l. x3 ]' d
EDMA3_TRIG_MODE_EVENT);! _7 G( X* I& U4 X9 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; o5 s, u9 ]+ R% F, q$ |7 \0 P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& [) S3 t2 `& M2 p7 O, U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* m- t" t8 A. p0 |5 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; g1 L- ^- M6 `# N" Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 {7 ?0 I: X* i" z/ M# n4 zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" W9 A8 h" v# J# K3 t; fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, _* C' t8 H0 _4 Z' P1 e! R
}
5 q/ Z4 W# l# J7 d( w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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