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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ P0 v$ D, x3 {; g" ~5 v$ ?: R% C
input mcasp_ahclkx,! h% F3 g9 n( a+ J7 Y) Z$ f* J
input mcasp_aclkx,
# I3 M% S* _; Zinput axr0,5 e8 {! _- F1 p3 j0 O7 {! T
/ D" s- a# A a+ z$ f# ?
output mcasp_afsr,
3 H) i+ l: R2 c3 c0 W; y$ }output mcasp_ahclkr,& L+ N( k5 C d
output mcasp_aclkr,
+ m: J; n, g6 C1 _output axr1,; \) b4 ?" Z8 M/ d' J: [% `
assign mcasp_afsr = mcasp_afsx;
2 t( v/ v3 i2 Gassign mcasp_aclkr = mcasp_aclkx;& I. a% m! @/ m# j6 f3 C
assign mcasp_ahclkr = mcasp_ahclkx;: l" K, V F' D) y# O# S7 P: b
assign axr1 = axr0;
% m; B2 c. S5 M* {" h s( `3 }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 \: N2 P' I2 n' y- Z* R
static void McASPI2SConfigure(void)- M. L* ^7 ~$ n
{6 l3 E) K! g6 e3 Y# ~- j+ E& w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) x$ A+ g& s2 q+ u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- x3 x0 m2 y$ O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# e b5 E1 A& J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' M+ }9 d% X9 p9 t$ |3 D# l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," {: Y% N3 i- X2 o( n% i! J; p
MCASP_RX_MODE_DMA);
, _: }. V: G$ F" R" g. dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! O4 y: R! u- R$ PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, P0 a( j. j$ D1 F3 X1 {: F- I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 W0 M7 w+ }6 D& m7 u% q& Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 W, s8 [6 k, f# E5 f. @6 v8 y( f9 E; qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + t1 h- E; s3 A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 S& k- e! ]8 [- s" {7 w+ E6 m7 Y# XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 p2 v2 j4 L" T1 W# [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' x8 E4 h1 P. {4 d/ dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 q! w/ i/ v* P& `* n
0x00, 0xFF); /* configure the clock for transmitter */, e% f1 e( \1 I7 [9 b; R$ A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! [9 H/ K# Z/ H# U0 A0 g* QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: }" I, O/ G J& ?: eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 V9 F+ U. U# N! A8 B0x00, 0xFF);8 @! W7 u# {0 Y
+ K! A2 ?+ p' d" U: m% |3 w1 Y/* Enable synchronization of RX and TX sections */ 4 ~! A# Y4 C- Q% |) R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. I( d, }/ ^+ R0 d' iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% {4 E. E. e( ~. \9 n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 N7 I5 ?1 @# w8 S8 f+ R9 ^** Set the serializers, Currently only one serializer is set as, i4 _+ k& E: l ?. d! ~% ^
** transmitter and one serializer as receiver.
% I# U& G, c6 d: O8 w*/( t% l5 b. }. W, S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 g0 P1 W& N tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& T( n6 o3 C% y% [, L( B9 O3 ~
** Configure the McASP pins
. p4 M/ V$ y2 D/ K f** Input - Frame Sync, Clock and Serializer Rx
% Q4 w6 b, s; Q; P% x4 H** Output - Serializer Tx is connected to the input of the codec % w' I2 [5 Y) c% X1 m/ d
*/: c, ?2 `: Q) Y& Y, \, ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); }1 O$ G4 I1 W; Q1 O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 j' f7 a4 {, ~9 g: y+ WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. C8 A+ m+ ?3 k2 }; K& c, l| MCASP_PIN_ACLKX5 D7 ~9 G+ t4 p: D# p# O
| MCASP_PIN_AHCLKX
) s s6 M/ a$ ` R( J8 V: N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& ^& a- s/ c8 u e0 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 {& y- }. X, |3 g5 H
| MCASP_TX_CLKFAIL , I, h: L7 U/ Y F8 Z" M
| MCASP_TX_SYNCERROR
4 {" J) S$ Z# ?9 l+ [" _0 k' C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! U$ g2 b3 Z, ^- N- G) m; `! [7 u
| MCASP_RX_CLKFAIL& {! L0 b3 Z* @* _- b8 p) o
| MCASP_RX_SYNCERROR 5 L5 a3 a' Y3 W A
| MCASP_RX_OVERRUN);4 j, ^. f( n1 D3 N7 E
} static void I2SDataTxRxActivate(void)9 {4 I M8 p) H
{
, p; q8 j1 k3 h, g9 J$ |! M7 p/* Start the clocks */2 c) j) z( { [% c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# r) q! T9 X# L& j3 D6 }" j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) L& v: F) _) H, C) }6 Q. J$ i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. k1 E: j0 K) q& N5 |: Z5 WEDMA3_TRIG_MODE_EVENT);
5 P- a) @! r, H; j+ ~2 [; u- LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ I- B4 Q0 m+ X- a* {* NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 k4 H& s* D2 |. u0 E6 UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: u/ i$ e2 f# X6 i/ V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. t D$ d/ M, n4 n0 b5 x3 F# E6 I0 x' E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 l, T; A# r% n" P7 N. I4 n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& Z0 `9 ]2 }( k# k4 V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) k1 ~3 x5 E! C& ?7 `. {) p( e
}
$ W8 o+ Y8 w& w% M+ X" c' R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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