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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 E7 ?7 U& V( U* D0 x( z1 i
input mcasp_ahclkx,
! m# g! o0 v9 Y- oinput mcasp_aclkx,; k0 c0 x9 n- ^& _- C
input axr0,
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output mcasp_afsr,' r% }" M8 V# B3 R( |
output mcasp_ahclkr,
1 L9 |9 d* l% Foutput mcasp_aclkr,
D* S5 Y0 X5 R; _output axr1,# e1 `" K, E" R; X+ U6 c) a, L5 F, x8 ~
assign mcasp_afsr = mcasp_afsx;: e8 D. |3 h3 u- }; o+ l4 r& }# i
assign mcasp_aclkr = mcasp_aclkx;
: O: M$ U) z% g# e6 Cassign mcasp_ahclkr = mcasp_ahclkx;1 n0 D. f& J R* v
assign axr1 = axr0; / z$ v0 h0 H* _% t6 k4 y6 o& D% c
/ z, H+ G" S) Z; K; q! \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 l I" s2 I. o, Mstatic void McASPI2SConfigure(void)
/ S% m# n' x: M- U+ R# ?{
$ ?- f8 X) w" @9 T- `; wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
W" X) T$ s6 g6 B8 h" IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; |9 z! s: K. L" c: xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 w T+ V" v: A# O; m% z( V) `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# ?) }# P5 |. J% U4 R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ [1 h2 @( u+ k2 }5 \
MCASP_RX_MODE_DMA);
) o1 j% @- _6 x$ w: s% LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- o- h+ @+ s6 G% lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 I7 O& g6 u. c2 x# k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! e! _+ `. p/ ?5 T1 b. Y/ Y7 WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 ]0 }2 J1 S6 {1 f7 T' |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( j" D, d/ i7 B% B7 k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; K& I- |% F) B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 N& _- Q! A! o8 A3 s4 V3 C& {# fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
k) C, D7 I, B- j$ I5 l7 CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. b+ _& L$ B8 g+ a; y, a
0x00, 0xFF); /* configure the clock for transmitter */8 |( ]" ]5 m9 l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 o* L6 S% n3 \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * _+ R& h% ?2 J+ n$ }5 J& K: g* k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ U4 p$ P2 w- I( n" Z4 I5 I4 X0 g$ W
0x00, 0xFF);
8 N, J8 a' X4 H6 l: ]# \8 `% b9 E( y& ^
/* Enable synchronization of RX and TX sections */
: D* [( H2 @3 {1 ^' QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% p' V" }7 X z2 a: h, j$ g4 r- B& `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 r/ {. q: x/ u; |) W: y* m4 q; Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 H6 m { c& g7 E, M/ V2 ]
** Set the serializers, Currently only one serializer is set as
+ F* o& F5 C, T/ ~$ ~$ s** transmitter and one serializer as receiver.! j, E2 A/ k* b) A4 b% a
*/: f* A w: i: r+ T) U* B/ H# r- Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, L3 G X8 ^) L8 R$ hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 N% P) b# j# E. G% X** Configure the McASP pins
; _$ E/ I6 d5 `** Input - Frame Sync, Clock and Serializer Rx9 C& C3 Y8 }: w/ D4 P
** Output - Serializer Tx is connected to the input of the codec
- h2 M" n- D P4 Q0 R1 K p/ e8 Z& n*/
1 {* k4 u* A0 K0 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 p& ~6 I8 {2 v) A% IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 d3 `1 G' l+ @+ g9 Q6 d& T1 U' }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, @' O+ P% Z" K. y& [8 B| MCASP_PIN_ACLKX
# m7 S6 p9 c0 H| MCASP_PIN_AHCLKX) Q5 j$ t% r$ ?* Q9 T8 F' N$ z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 u& f4 G- {# i, i1 V2 d D; |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , g1 X+ E+ ^; n; Z3 E
| MCASP_TX_CLKFAIL . K0 X8 E5 h' D0 ]1 P a2 x% K, a8 f
| MCASP_TX_SYNCERROR
2 Q4 C- b7 g0 ]* }6 t8 X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : `2 |, |. d- L! z U- q
| MCASP_RX_CLKFAIL
Y/ [8 z2 S u+ B( Z; z2 {* E| MCASP_RX_SYNCERROR
2 w t- e* g' [ c6 _. Q7 A" a| MCASP_RX_OVERRUN);" E. k" r. l2 R! m
} static void I2SDataTxRxActivate(void)% x1 R; ^8 W" l# G8 R4 W0 Z
{
2 ]" q( {/ [" @6 p/* Start the clocks */
8 q! M# K7 I# u3 NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: P) A- v% S& g9 K3 a% q4 E5 F5 o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# \. Y" \ K' o0 z( D* J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# ], r" ^& U# }* q! f1 v
EDMA3_TRIG_MODE_EVENT);
7 I0 q3 u1 d0 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( Q" F' g' F8 M+ K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 o: p9 s% T& j# [ YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, `( O7 i- c# B& w& A; d. mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 o' v/ F3 k( Q$ a f# Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) Y! K" L" l+ [* {9 Z8 h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ _% ]3 ?. m/ k) @0 o) a0 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 q b2 [5 T9 E% N
} & v/ l& q6 v: V+ C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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