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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 I V8 y) K4 `0 v6 i
input mcasp_ahclkx,
# ~0 y, h1 _" Z% n$ ]& Linput mcasp_aclkx,
8 |, ]7 A2 a; g' I; `3 Jinput axr0,2 ~; `9 j3 z! U: O6 z2 o) j6 |2 U
8 s5 y( O3 I% s# A6 t- ooutput mcasp_afsr,
H1 @4 x% U8 [output mcasp_ahclkr,: C3 f' `! s1 X6 m7 O! w
output mcasp_aclkr,4 c1 i: t g( D( }9 U
output axr1,
; z( c, [6 T& x; Q- O6 o5 \5 |0 k6 b assign mcasp_afsr = mcasp_afsx;
9 C! v2 J. W1 S8 a/ N0 r8 Oassign mcasp_aclkr = mcasp_aclkx;: m+ h- D9 o7 N" R+ k$ {
assign mcasp_ahclkr = mcasp_ahclkx;& R0 d! E. J1 I# u7 f+ G$ r) E, \. k
assign axr1 = axr0; ( H& }; n4 b4 Y) o% M
% U1 t3 y3 p, Q% t- ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " _/ i$ U" i/ p8 k3 i0 F
static void McASPI2SConfigure(void) X1 |/ n3 J5 y5 w7 |6 J9 S
{9 S' W* A: ~; _6 Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ f5 R a. b8 l8 n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 e& G' l* L: XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) X( K* J0 W- }1 ~2 c( F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 r8 |( [3 y/ a0 fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, X. V* \4 p* I" ^: J6 z9 u
MCASP_RX_MODE_DMA);
( U$ s+ [/ E( q2 T: t$ O8 y! FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- W) J- a5 k. W1 G kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( K& t; p0 l/ o$ h2 _1 ^3 _6 c4 sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 ]6 O" U) k6 S" p, YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; u4 N$ C: }6 s) G# PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * m0 o1 C: W9 P9 D# d$ G- K3 e7 i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- g/ @4 H. \) A5 n0 U- T& t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" Q9 m4 P. ^5 t0 G2 fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" l/ Q6 c ] N9 F$ C5 V$ F$ l4 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. ^# S# [9 D% V9 T
0x00, 0xFF); /* configure the clock for transmitter */
2 ~; R, H9 y# U, A' Y; DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- ~# N% {5 U5 C. ~& `7 Q: n" P& w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! N' g$ l4 h2 | T, f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) A* L- b. c5 f7 [0x00, 0xFF);
, x& ~6 q2 w# K6 O b O4 b9 d( h% i* l4 t' X1 W
/* Enable synchronization of RX and TX sections */
* a4 x, Y5 D' h6 P/ T6 C8 `1 J6 u& dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- X e, y/ \+ V8 V: L2 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* { V# g3 Q% P. q$ n C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# B6 L* v+ N R0 H: y3 I
** Set the serializers, Currently only one serializer is set as
+ Y* K, F! W" @: I) P: |** transmitter and one serializer as receiver.# n7 n8 \ ?0 v' s. z
*/2 a* \; `+ E) l, O$ ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 \7 G2 M+ O5 x: M+ Y) R8 AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% `6 f* n& N; K, C# n; Q% Y** Configure the McASP pins
$ [# ?& }0 b" L1 g Y** Input - Frame Sync, Clock and Serializer Rx. i* h$ o1 |- Z6 U( ?, Y
** Output - Serializer Tx is connected to the input of the codec
8 O* N: Q/ i1 p' }; u2 k* S*/
( g# `+ e& Z+ X8 E; ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" {' t1 G' k+ l2 G- u# Y. lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 _/ D* j! e8 D& i7 u! wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" \9 e. N% F& [5 o4 [1 ~
| MCASP_PIN_ACLKX
, q* D3 m5 `0 `2 h| MCASP_PIN_AHCLKX
0 z7 k. Q9 O- s5 t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. N* J3 }: Q0 N/ W2 f% F3 i0 _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 h! [' H R4 ~9 z
| MCASP_TX_CLKFAIL
% m8 ^% e m) ?# y v- Y5 E/ [5 W| MCASP_TX_SYNCERROR+ z6 b# L$ V$ v7 W+ G! O! F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 B, V/ X$ T/ e( P7 j8 e9 _0 e
| MCASP_RX_CLKFAIL+ C b+ ?% ?9 k0 }( V+ K8 n
| MCASP_RX_SYNCERROR
8 E+ p; D# X, p- `# k| MCASP_RX_OVERRUN);
+ n$ `( V0 D& K+ T} static void I2SDataTxRxActivate(void)
% `; w) b G& y/ U4 S8 s{
9 @7 q) n8 l9 @1 T; m& c/* Start the clocks */
* X1 H, r" b3 U/ Y6 RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% s- L: Y. B0 l) Q( a" @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ j' v) N* w/ Y' ?0 B2 f, REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 Y. E- Y/ q: x/ U5 C# kEDMA3_TRIG_MODE_EVENT);
# v+ w0 S- o7 {' bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( k) [. {8 f4 f* \3 ]! S+ kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 p1 b& ]) @ U& O. a5 Z0 s8 m4 O0 e uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* T/ w: ]2 W* E! W9 g6 k. \# tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* M) }9 ]' P9 y9 `. `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 J% ?0 D3 s+ O! ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 ~, b9 Y3 e/ J$ c+ d" p- y8 H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 k# [3 C' e) p; ~' d% T
} 1 I F ^4 X/ S; a) }2 h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 o7 S% v, j; [- O/ J1 e
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