|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, g6 R. x1 \& L6 V, }
input mcasp_ahclkx,
, i' x( s) O+ r8 L2 f3 U) x! B( Cinput mcasp_aclkx," g* I6 j) B, P% y2 D3 d
input axr0,
, h9 W; H6 ?; B5 a" u! D X# \/ k" |
output mcasp_afsr,
' w1 ]6 }$ l/ ^! V' m' v8 V; Boutput mcasp_ahclkr,8 B( o. Q4 l* v9 E/ i( S
output mcasp_aclkr,9 W2 d, V" d, L' X
output axr1,2 k' z% ?8 h) C4 _: g2 [
assign mcasp_afsr = mcasp_afsx;
5 M7 K1 U d, ~assign mcasp_aclkr = mcasp_aclkx;' Y, x; ?" t2 _- z
assign mcasp_ahclkr = mcasp_ahclkx;
0 N* R' [+ E3 W% n$ passign axr1 = axr0; & k- i! |& ?) @- U2 c9 r, a- ~1 |
\. P9 ^3 Q% f8 v+ _3 ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : E+ x; x# }) b
static void McASPI2SConfigure(void)
+ X; d5 h8 O1 E4 I. S! F{
% O# S+ h; O6 M% H/ h8 K% oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% c. R# _2 K1 a" o1 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% [2 X1 c8 E2 N% ]- K8 W0 WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# f1 d) {" ?# p% yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* f$ T9 G2 s0 K8 X, H: f5 uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ K7 x6 Y5 v$ U, N+ uMCASP_RX_MODE_DMA);4 A3 a- Y% f$ q) q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" D2 | y1 v4 x0 G4 J0 J4 SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 _+ W& k5 q. \: ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ {4 ?- t3 o- l u$ V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ ]. I' S v* E& q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 w, A& X4 j$ b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* \* ?* w3 f3 F v* z- x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 b$ `$ k @: ^, I4 w: p+ s; i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 @# n. S, @/ F7 x/ E G6 IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 r: {& z" j; d' e$ p) Q6 Y. }' @0x00, 0xFF); /* configure the clock for transmitter */
5 H! l# w$ d5 r8 hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 N; x/ \( @ M" \( |; p9 XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , U+ l1 B9 n6 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 l/ |0 {7 {# ?
0x00, 0xFF);
6 x# A- {) K) R! F
: X! k: X8 p8 m/ B* E/* Enable synchronization of RX and TX sections */ / D, L/ } u& Q# D5 Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 M' J# `5 f" I5 J. o* W& hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! z1 N) P4 S4 | H& {# p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% C5 ^1 a6 P; W** Set the serializers, Currently only one serializer is set as$ |* W6 Q3 T& M" H/ }/ |
** transmitter and one serializer as receiver.' d+ x1 S; r0 F" f0 F6 \! _, ]
*/- q% }1 P0 w7 u; k/ [" J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, G1 N" p0 J- a5 d3 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 V5 O7 R. g8 x H** Configure the McASP pins
. q4 J/ ~/ N6 ]5 u8 {** Input - Frame Sync, Clock and Serializer Rx
0 B3 F0 a* x: d# e( @& ^* x** Output - Serializer Tx is connected to the input of the codec 4 G4 S2 U& p+ g: {& D; a: d
*/
/ \1 _& m2 i- D: I8 ^ _* J7 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; h! J! N, [% k, z5 ?+ r) X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 Z3 m4 h1 U3 t6 j8 A) eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: N1 t( W) {! a/ J' K3 D| MCASP_PIN_ACLKX
( D; L/ @* M7 R$ G& P| MCASP_PIN_AHCLKX
5 S; K$ Y& N, U7 H$ S$ }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 Z" d$ s" R! q8 n6 |! s. n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& y# u& ?5 l& g& y% k6 `. P- y| MCASP_TX_CLKFAIL
6 g5 o+ {! s R| MCASP_TX_SYNCERROR
- [6 R' j/ S' J7 h: s& ]; \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
`# z, p5 E' H' H& P| MCASP_RX_CLKFAIL
" k$ u6 J7 U6 U. { v% G| MCASP_RX_SYNCERROR
% V& {4 x1 Z3 F- a2 Q# O( j| MCASP_RX_OVERRUN);$ q8 x8 H, ]! Q% s
} static void I2SDataTxRxActivate(void)
: o' q& o4 x; e/ Q w( D4 s{6 h/ m& H5 t4 W9 v2 }! b$ X) n
/* Start the clocks */
1 B ~/ ?8 A% h% d& W6 F3 V7 BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* x* s: U( d8 P0 n* hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: T! |- b" v8 h N5 l2 \; x# D: TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% O* G& C3 V1 ]0 P& b+ D( I( b0 {EDMA3_TRIG_MODE_EVENT);+ q4 N# a- z- k/ }4 m/ x# a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; ^4 @9 P+ ?/ l& T$ Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 R% ]4 U8 D8 k6 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- U( x6 J0 A$ o: j# E7 |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 H9 ]- X0 V) w' Y- t1 d% Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- s( _# O+ V& g/ ?) t9 g6 h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( K) m, `* w2 ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: b& J/ s2 z6 m* J+ R7 H
} ' p% e9 }5 t. S8 \1 {; t$ g" O {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - K' D0 b7 X m! D* r9 ^5 w9 Y, f
|