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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 }: P1 ?/ g, }3 i* _
input mcasp_ahclkx,
% _+ n2 b) X% L$ ?! h. V5 \- [input mcasp_aclkx,& ]" C9 m3 }( f6 `) U
input axr0,
. H) d. u0 e9 o9 B* @& A
+ G9 _' _9 y8 s' E$ N. noutput mcasp_afsr,+ \% b1 O' N# h# @# c W& x
output mcasp_ahclkr,* [2 I. N3 }8 W; i; R* K
output mcasp_aclkr,
9 K, E9 A) \% M% noutput axr1,+ |+ H; K* [$ ~2 n2 R
assign mcasp_afsr = mcasp_afsx;
7 q4 }6 z# k, y" M2 Passign mcasp_aclkr = mcasp_aclkx;, ]# V0 U! r1 r% Y
assign mcasp_ahclkr = mcasp_ahclkx;
8 O" a9 y$ b6 ~) X! V- A6 nassign axr1 = axr0; 4 F0 q: V/ J. z+ S; y5 @
3 s4 ]) B$ G. R8 ]* v, v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( E) A& _ [* l8 J8 N1 K3 u# fstatic void McASPI2SConfigure(void)) i" f! M8 ~ L- h9 e7 D
{
; _* T& F- M, T1 b8 A' xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ t8 p6 \3 D5 r. x( o, t+ nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 a- x( Y% A/ U; V/ MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; U; `; A7 E3 c( D ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. G4 j g; {6 v; W0 P7 S5 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* x/ [2 O4 a( h, f; j8 F$ u# a" ~MCASP_RX_MODE_DMA);4 p1 [) s1 ]& |% W9 n% A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, G T; I$ a, R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, q0 E$ S: Z0 D4 F1 O9 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 O5 ^# `* X8 U" @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* g. G$ Q+ i* c8 a" ^0 P, LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, m* N. V' _% }- \( W4 |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 b2 l' m! |! d5 W {9 Y- I4 Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 @ X, x- O& n. I& Z" K& F0 x. tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! a- L8 e& J8 A, VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, k# e; @. H3 r$ C. p% e5 Q2 r
0x00, 0xFF); /* configure the clock for transmitter */, m, X8 P) n- y! A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 b; S. p6 \2 Z4 r3 ?5 zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 z- d2 m7 m9 z! ^4 N4 ]; \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 z+ j. N# { `! D0 K
0x00, 0xFF);2 E( {6 O% m9 a$ R% A, f( b- W
( u' i1 \3 z \% i
/* Enable synchronization of RX and TX sections */
4 r# R9 h6 |' I! oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 U+ ~' ^; ~6 D) |# ]+ }+ Y$ R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. S( z5 ? C% p6 eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# E" N* u6 C1 w% m0 J! N** Set the serializers, Currently only one serializer is set as
% E. n8 ^( G9 P** transmitter and one serializer as receiver.
' V* K7 I2 Y' ?*/
+ I% ~9 c9 }6 d: S& q4 kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( x+ @% v9 ^. k8 j2 [+ E, ~5 x! g6 C6 fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" p7 l+ s9 x8 O5 k/ Q0 W+ `
** Configure the McASP pins
; f: P$ A2 W( @** Input - Frame Sync, Clock and Serializer Rx
4 F V6 o/ A* F# U/ P, a1 T+ b** Output - Serializer Tx is connected to the input of the codec . W4 x3 B$ x* _8 M
*/; h/ L1 }# l- S B! F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" T) S* Q- k! L- I6 ^7 sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% J3 ~' a% Z( w5 E# V" DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( U: D/ V3 a2 q2 }( l0 R| MCASP_PIN_ACLKX
) r; y# f! @8 V3 e: h" ^4 q0 R| MCASP_PIN_AHCLKX3 i7 i2 Q. r' Q0 z5 U( R% p n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% k7 K+ j; M' s0 t+ LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 q6 |) g! t/ c( r: l# U& C| MCASP_TX_CLKFAIL 5 G+ b% E, r, I4 ?+ m/ F7 k
| MCASP_TX_SYNCERROR) W' X7 v' S5 p& q7 l- `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 C: W3 r# v9 I+ t| MCASP_RX_CLKFAIL
5 @7 O: s; S8 A& C* [4 R$ || MCASP_RX_SYNCERROR
- j( x* Z0 u$ Y( X8 }| MCASP_RX_OVERRUN);
# L/ P3 ~* v( i; h$ X! P( {, j} static void I2SDataTxRxActivate(void)
: [! d% a; L3 Q. g4 {( T{2 Q9 \+ r2 @* C' `# N
/* Start the clocks */
; c5 a( G( i( e- w! jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 W( K, u! c1 E! ~; E! @5 r: }$ l. ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; W; B4 q- V- K; L4 G8 w- sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 V* r- {. D" n" w; W
EDMA3_TRIG_MODE_EVENT);" M' {' X* I: `, [" O/ [7 }- I9 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) ]' i9 M- z, y1 r+ ^1 o7 x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" a0 B' d: j; R3 \2 vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( r7 x' ?5 v0 K0 xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) F. F7 [9 n( C1 m. g9 rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 Y7 u0 m6 F! a$ L, H) p! SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 N1 J B2 e; }, t2 U( C# q) `# J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- N+ F) H! r! Z6 q* P* Y} + Y r. J/ t0 `# N- e9 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # `6 R; A# v) R5 R
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