MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
" \% Z9 N3 @" Z" h' qinput mcasp_ahclkx,
input mcasp_aclkx,
$ ?5 u# D+ F! J" j1 tinput axr0,
. @" S. [5 q" ~
output mcasp_afsr,
' j2 W6 s- A/ N' }output mcasp_ahclkr,
output mcasp_aclkr,
1 \* X* ^6 l# Loutput axr1,
# a4 A$ F5 K6 M! s+ C

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
8 z! q! P7 ]% q4 N1 Wassign mcasp_ahclkr = mcasp_ahclkx;
; P: `) j: l, zassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

3 H7 N% i( ?1 f4 Z6 J# l2 T

static void McASPI2SConfigure(void)
: M& e& ?& ]- {{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
  }( t9 u7 J4 y; A: ?0 ^7 sMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
' Z# l0 S, b) {6 {0 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 T% m2 F4 q5 `+ _8 e  y0 \0 XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
# l7 N0 q+ E6 Z/ wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
6 I7 l( Q- q$ d8 |  ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 R$ d. v$ f9 i' Q" z/ w3 e# NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: M5 c7 a* ~5 I5 gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 I7 V' N6 S% Y, o, D3 QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# g$ v  O) k) |0 B3 N/ }: hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 d0 E0 F+ `( B2 _6 a0x00, 0xFF);

/* configure the clock for transmitter */
1 v0 i9 ]' ~9 g, xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 e( ]; v$ c; P% {% p. h6 O& o8 U8 bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: S' J% O) Y' a. k$ A0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
9 U' o$ k' @4 K  B+ G- q* fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
# ^  j9 x. q8 C8 M9 h2 @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. x9 u1 n% g+ G+ uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
/ V$ p( h# M: s9 E5 N9 u' X9 D& X** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
8 |' x3 K8 _% h" a2 D: s9 n, S/ V- y*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
2 A% N1 P; ^2 E: S2 \** Input - Frame Sync, Clock and Serializer Rx
# I1 o* I( X1 k0 n** Output - Serializer Tx is connected to the input of the codec
*/
. |; E! A8 w2 m3 W1 n5 v# |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! T$ K5 l) ~0 o, z5 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& ]$ G' [6 D5 n  HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
# U( |$ q! P9 o: v. _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- a6 q8 s7 i( y7 Z| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
9 z% e. J  Z% C- ]6 P. }| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
7 e" N" Y1 g6 R' ]| MCASP_RX_OVERRUN);
4 W. j. z  t! W, w8 y; Y, ]4 }5 R}

static void I2SDataTxRxActivate(void)
; L" B$ I# y: _: g# O' p{
/* Start the clocks */
* O: \: _2 W2 {, g7 S5 f/ @) W0 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% s7 t1 _  s# @6 ~" wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! J3 D' u( A+ }6 T+ KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
" q4 e1 _2 O/ R/ _0 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: R% O% z/ s# q' pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
7 N( `/ u+ d5 H) EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

2 N, h  N2 c6 Y; q7 P

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

1 w- T& S, G! S0 ^3 y