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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 y8 Q" l1 z; Y9 o, l ninput mcasp_ahclkx,+ W+ H6 Y7 I) ]+ I- s5 y
input mcasp_aclkx,
0 r# b- ]/ Y5 t3 }9 einput axr0,
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output mcasp_afsr,
0 S |1 } v( Xoutput mcasp_ahclkr,: g( j, N+ W3 f- M) [5 l$ L
output mcasp_aclkr,3 k. ~# t* Q" y2 r0 a
output axr1," j* L9 P% m5 h
assign mcasp_afsr = mcasp_afsx;. Q' i5 @9 M7 }4 u6 _
assign mcasp_aclkr = mcasp_aclkx;. B, g+ q* z9 {! x+ K# j, b
assign mcasp_ahclkr = mcasp_ahclkx;
' `7 }9 `0 }# H2 oassign axr1 = axr0;
; u* c7 Y/ U( w
5 Y( e+ L( ?$ k( _0 ~9 j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 f: E% X- }; o M* H
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: m4 a. s9 M L+ G8 ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" U7 p5 W( \" }% D. @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 c. W9 k4 i7 ^& i6 ]5 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% b3 L8 {/ [# z- g8 {- t- M: mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) Y; w9 Z- M( M4 D
MCASP_RX_MODE_DMA);
( E/ f- f; f! w) J- r zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 _: m- x, {' RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
F0 }! O* \ `+ ?7 f* H2 iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 \6 {& Z. ~2 M" y0 P1 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 ]% {# o4 h: x2 T+ B" p' m1 G! }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. v# ?& q. B z2 L/ A* X* BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ @. g2 ^6 C1 y( {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 J' C- _' E1 T9 G/ d* j( B' O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: C$ |6 a- y) s4 ~# l$ |% LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! p) F% o0 K5 p# e! u3 m: I# [! T; x5 R0x00, 0xFF); /* configure the clock for transmitter */
, s5 S5 Z+ m8 t+ q6 pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 S7 }9 j) N5 Q" S) ^/ [( v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; }7 n0 O3 V/ v, x- x* k# Y( R% _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 A( V Z) f9 B
0x00, 0xFF);% M1 C9 ^- {) R6 g9 M$ a* n1 x
( t$ {0 L$ s5 _ C
/* Enable synchronization of RX and TX sections */ - V% m t# O8 e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 {: @2 q0 M: fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! V0 Z+ [" u. u! \7 ~! E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 p0 ?" t+ y+ J5 a0 Y+ n8 {8 ^
** Set the serializers, Currently only one serializer is set as" y2 g1 C$ ?% V+ e$ u
** transmitter and one serializer as receiver.
3 E2 N* f" l8 }3 |* P*/
J' n% u1 m: U" ]* o# f* ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 ~2 s- A& C. l: L9 p% AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 E4 x( Z' Y9 w2 n6 O2 z. w+ e3 s** Configure the McASP pins $ P" I9 W( o! L; B. m* [1 m% R
** Input - Frame Sync, Clock and Serializer Rx; m3 j# @5 ^4 u
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- i- i; }# @/ k# m0 P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. a& @9 o' d, L, e- E5 R" a; N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" U9 A* A& O7 ?) m, E
| MCASP_PIN_ACLKX$ r+ P6 R' L. M$ x) G
| MCASP_PIN_AHCLKX% C# o# k5 k! j/ ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' |8 I2 ?& c" N# F5 @+ V: k& f3 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 N5 o7 z: \, w8 T8 Q
| MCASP_TX_CLKFAIL . N% I8 P$ v6 m
| MCASP_TX_SYNCERROR
' c$ i% x. Y/ G/ O) W9 j! v2 O6 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# z. b6 [. P! V2 c* X# R* b| MCASP_RX_CLKFAIL
9 T5 v6 P& c4 `; i/ m; M5 j' ?| MCASP_RX_SYNCERROR
1 {- g$ s/ `4 E' E, l| MCASP_RX_OVERRUN);
; D' v1 {0 n* m7 x} static void I2SDataTxRxActivate(void)% B& F$ S, P4 D8 s4 N' a# `4 U4 O5 u
{
: [0 b k8 B' Q/* Start the clocks */
+ g! P4 I% K) ]; K8 DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* U$ z9 c$ B+ z; a1 tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& g* @9 O$ N7 N7 o* I& l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 _ ^8 h5 q5 ?( Z5 k" y R. i5 XEDMA3_TRIG_MODE_EVENT);. h& b+ R7 N/ \0 F' w4 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) q. N; q! B1 @6 C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 T' C. |' w) [' V) b uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, s' N/ t# s6 k7 i, f- bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 Q* q3 h4 [0 R, k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! Y/ u4 V$ |0 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ T2 Z8 c) b: M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( ]' }6 Y( x- R7 q/ ]+ A) p
}
1 p: ?2 l) d ?/ \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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