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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," E% v4 n* g8 _" `
input mcasp_ahclkx,
+ r! y I0 G1 a) A* f- ~9 B6 L. Xinput mcasp_aclkx,
5 |( N0 u' p. r8 d" ~2 H, |" ]input axr0,% _# j$ H; n" K! j+ [5 p! P
: Y: R2 U' Z& e. t5 `& j3 m1 `
output mcasp_afsr,
' D; x( c+ n) M3 x2 F3 moutput mcasp_ahclkr,. r( V/ U7 b; ^
output mcasp_aclkr,
5 A. e1 Y* V0 T4 \0 Youtput axr1,
, A! |& T3 ~/ f- N) A3 V9 D assign mcasp_afsr = mcasp_afsx;: _+ ]0 H; x! J! A
assign mcasp_aclkr = mcasp_aclkx;
- s" D5 t7 T- Yassign mcasp_ahclkr = mcasp_ahclkx;; [" G/ [0 ^ @; J0 J
assign axr1 = axr0;
; i( {3 D& a4 |4 P) l( q' V; n
) N0 |' M9 [- s) F/ _& q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( [3 k( G+ {( T9 s1 G. @static void McASPI2SConfigure(void)
: w. W5 n7 M; p) }: i! y" r/ @{
# r9 k; }3 x/ x0 g. m2 Y+ oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. E0 T' m3 s' O, g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ {& R0 x, y: \# D: Z4 T+ M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 z2 g H3 _4 ]0 q% z* KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# P; P1 y, Z* N8 X. vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- Z1 u) N4 m2 }
MCASP_RX_MODE_DMA);
" z% ^4 q% l: [8 S! Y% b6 ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 M; ^1 ]3 X7 i/ V: A( m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// ]7 W0 Y7 G2 g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . Y( y) e7 l$ C% x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 u1 v6 ^1 A& a& W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, ]) Y* C0 v4 R! @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ P% D; L/ N2 R u4 n4 EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 w, l% ]# J; ^# R! P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 ^7 q5 t5 E7 g. U- D. L$ |& ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: R" {2 L# M% o; n( X! `0x00, 0xFF); /* configure the clock for transmitter */
' o4 \ J5 q6 E# o; \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 p, H; E2 ?0 Y, P# n: @ g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 Q- x8 f9 |+ A6 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, T6 Z: ^% m3 N* q
0x00, 0xFF);( G) m7 \8 K, Z& E$ u; ^
# g& u$ Y. f# m, T# D
/* Enable synchronization of RX and TX sections */
8 J4 c6 M1 H3 {5 A1 `0 j/ a0 `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, q3 C$ {) Z: f4 \& w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! ]# @; ?, u- j' Z1 j& `& X8 s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ n4 ~" o0 {$ K6 m& w) C** Set the serializers, Currently only one serializer is set as
) _+ b1 T, V7 ~8 l- t** transmitter and one serializer as receiver.6 u m: j/ N7 N. k6 d
*/
) H, f, t3 u( b' k. d3 UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 e! ]5 M8 w" e4 j2 A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' y+ {7 s. @/ I$ @
** Configure the McASP pins % N7 i/ ~4 S4 p9 u, ~
** Input - Frame Sync, Clock and Serializer Rx
: _, ^- k; ]5 b0 q9 H9 g** Output - Serializer Tx is connected to the input of the codec 9 ~! v2 W4 t7 E
*/
0 r8 e7 w) p; RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 f) T2 \& Y2 N4 a9 G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 e2 l6 V$ ^1 k5 G% LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! O, c- t: P) k, q& O
| MCASP_PIN_ACLKX
, Z+ p; i' }+ H- e5 ?| MCASP_PIN_AHCLKX
9 R k$ H: W5 ?, U. n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: T% W% M: Z& l- q! i9 M; N2 ~! E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 |3 F( f" u% o: e3 W, {| MCASP_TX_CLKFAIL : S2 W2 C, |+ u) Q9 x4 ~* [
| MCASP_TX_SYNCERROR! J/ W3 [/ ?2 e/ {7 i! q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) _- V' n. I$ L9 }2 X
| MCASP_RX_CLKFAIL P- W F: Z3 @0 ]2 r
| MCASP_RX_SYNCERROR " F$ @' x4 s8 f m1 {2 P% @1 w
| MCASP_RX_OVERRUN);% o, e# q4 D I# e3 g
} static void I2SDataTxRxActivate(void)6 A, N# A" w- O+ x% O
{
; ?7 i0 o+ {2 ~. Q/* Start the clocks */. J. h( f4 D: q, r0 O- {' y/ ^+ P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ X# T/ x! l5 Q. F Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 ]9 c& [) k. L8 C1 |: s. S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 @: {1 }5 V7 Z# `, {; zEDMA3_TRIG_MODE_EVENT);/ H. D. W2 g8 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / S& i: `8 @: x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 A9 G K I, j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ r3 v$ [& v$ X0 X. @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 Z' K2 b2 n: N: T: R! ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& H# C& W; [7 x3 p0 \1 a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 S5 C* k( H2 ^4 o5 V8 m6 a: \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# J3 x1 A u, q% y) D
}
: n- n* |% _# C' E+ N% t/ e2 L1 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , z6 e/ d4 [- @) { _
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