|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 T) v ^& D; J$ X
input mcasp_ahclkx,
& U7 {( F1 G8 \ Q8 {6 Z+ C# Binput mcasp_aclkx,, @. @( O2 l: ^& Q# d, h
input axr0,
* @9 B: b1 @+ P# d! W
# K+ P K/ F3 O5 H; `2 z7 aoutput mcasp_afsr,2 G: q4 Q0 ]# [& r2 T! L
output mcasp_ahclkr,
/ B' D/ p- g m/ Zoutput mcasp_aclkr,+ @; F' }5 Y8 V
output axr1,
% [3 B2 N6 D3 ^- h$ C, v0 g) ?9 A5 e assign mcasp_afsr = mcasp_afsx;& A/ l$ ^7 R0 T4 Z, X
assign mcasp_aclkr = mcasp_aclkx;
# N& n( g% ~% G. iassign mcasp_ahclkr = mcasp_ahclkx;
7 I( ^; `+ [3 v! Eassign axr1 = axr0; ) y1 J$ l3 T9 S; f$ G
: x! O# h: q I3 h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : a/ D: t, G3 {
static void McASPI2SConfigure(void)& E2 [) Z8 f, a; y) ~( B
{. {( D) L- P/ J/ I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ l) r8 g) E8 J' s! l7 Z, y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// E' N5 ]. c/ H7 ]2 Z; [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. L9 T) Q- x, ^0 J. h6 i1 k. x T- N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" t: ?) Q, _* D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 P/ d; p( N9 x! I3 H9 Z; V: o
MCASP_RX_MODE_DMA);( l7 O; \- j% y* D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! a. {) R( V1 r! |6 [, t5 h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. W( u. [( B1 OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; {8 ^4 ~3 R0 x5 r. W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& w( J1 q2 V' u4 M y3 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 H0 O6 {: ?0 c7 ]( v6 g& B+ K/ p3 cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" @' D- }$ R5 A& U$ v' [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 p/ h4 I2 k3 ^; N5 v! OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' U$ i. v0 h& b c$ a- \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; O( U7 B* J, Y" Q3 l$ ~9 i
0x00, 0xFF); /* configure the clock for transmitter */
6 c e; L. ?! A, }7 {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. K- I8 c8 b! E( M$ R- t+ r: N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " ]& }9 ^( A. O6 k q) ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, x9 ~0 V4 s$ {% u9 z" z. ]
0x00, 0xFF);( P& w b' I% j/ l
- F5 j0 Z3 g8 r( n7 S/* Enable synchronization of RX and TX sections */
4 A" W% k4 J# K' vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ i- u( O( ]" E3 _% \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 V8 N4 i# z+ X7 S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% V/ {% V( r/ M* Q
** Set the serializers, Currently only one serializer is set as
# ?' Z7 [" T3 W** transmitter and one serializer as receiver.' o# e& i) i. Y3 d8 [! ]! I
*/' P. b5 {: N- _' ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: I" U7 ]# E. e, t3 x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 A% a0 f; a- U! l* d* p
** Configure the McASP pins 9 n$ R- ]5 V: L! e# m0 ^8 I
** Input - Frame Sync, Clock and Serializer Rx
) ?" w n8 F, Y _** Output - Serializer Tx is connected to the input of the codec
7 i' F& H) ?& A1 q*/- P0 {, H; a% Z& w3 t* B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 B; d- k% T E" T" I$ i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! ]1 g3 @- z9 C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 H, `8 T. m: Y5 n& X" R9 {| MCASP_PIN_ACLKX# q) J, E, b5 \, m, }2 f D% Q$ f1 _
| MCASP_PIN_AHCLKX
+ Y9 c3 h2 y: ~/ [/ {" O1 P+ {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// t9 u* _1 Q) C" N' {! |3 }/ z1 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 B0 d5 u. _' K2 e! ?
| MCASP_TX_CLKFAIL 8 R# }; R9 ]' R7 ?! Y V v2 |
| MCASP_TX_SYNCERROR
/ k1 E) I0 U( c" F5 ]5 k( @9 q4 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
w/ z( |6 V) I6 }( n \| MCASP_RX_CLKFAIL
& F9 J! c) V+ g/ z* m3 |; t" D| MCASP_RX_SYNCERROR
2 j9 j7 o% v# W4 F- j| MCASP_RX_OVERRUN);9 A0 r+ ~ n$ U7 F
} static void I2SDataTxRxActivate(void)0 M4 J a0 H( E
{
; N2 D& @3 H: G Q4 o* K4 s/* Start the clocks */: V; `% y. X4 {, ~( a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: S# F& K: g2 s4 e5 M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) y" Z' e5 ^6 S: Z" J- o9 `6 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ N t# K; S( G8 l. |% H: u8 s
EDMA3_TRIG_MODE_EVENT);
/ {9 }7 i0 b" f2 Y) pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) ^" v5 I: ?( [% aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 F2 q" O- u1 l, y9 Y* |+ _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: b& |& n" ~ H7 m* KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" \ a! H# J$ T. X/ k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# b! C7 o$ l+ l0 }2 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' u) M( A# n* R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ h% d( A, R0 W' \' C
}
! O. e6 u. b4 N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- q6 a# _4 L3 a5 @: f+ } |