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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 ~( X" V( D4 f2 x q8 r$ e9 s
input mcasp_ahclkx,8 K+ q: @) Q* o! A- }9 U
input mcasp_aclkx,& X) c' H9 E/ ?4 ?3 k& I: n5 N8 r7 C
input axr0,
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* J1 J4 l# ] i8 i& F: x6 T( @output mcasp_afsr," ~5 }6 {" t; y W- K( J
output mcasp_ahclkr,& K& u# {/ y! I& Z' ~# P
output mcasp_aclkr,
* C+ {- h9 ^& R5 i! z" E' {; foutput axr1,5 x7 J) x+ T! ]2 u: E4 M! C5 S9 g
assign mcasp_afsr = mcasp_afsx;
7 v- T2 b8 U: s' X+ a7 Y! ^assign mcasp_aclkr = mcasp_aclkx;+ z- w/ ]' F- ~
assign mcasp_ahclkr = mcasp_ahclkx;
/ D6 E6 ^, R6 r S% \8 ?assign axr1 = axr0;
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; n* s8 H/ c) u4 i# T; y2 T4 }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 U: A1 Z& L1 O
static void McASPI2SConfigure(void)* g* u$ m+ U/ Q* @; J5 q' j
{
' v! U( A. g; c1 J; OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' v$ x: R$ ~6 ?! q0 WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; N3 ?6 y* G& n( G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ K* d+ t6 h: {# x. G# J2 MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& r6 A1 J k; U7 y& ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# l# F/ c3 T' `/ m' u; M/ K. U; @MCASP_RX_MODE_DMA);
# i7 \) {4 Y' zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 }4 S# I. a& Z: Y1 o9 j2 C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ Z) U5 F* q1 o0 fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , g9 r8 l$ @3 B W- E1 M2 \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* L& k9 n- b6 m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' `9 P, {* X8 b9 o- D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! V5 T; w. P1 L: |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 U: ?+ D8 H+ Z' k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 f5 X. U: C5 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. ?9 X0 r+ z0 ~) q+ J
0x00, 0xFF); /* configure the clock for transmitter */4 Y7 W* h; @, b; L, v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
I& P! W0 ?: j* [4 iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 {6 s1 R. B9 {4 |3 Z1 ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ p" D" n0 o) K+ B R+ `
0x00, 0xFF);6 r( N- o m$ P9 m4 |9 q" \
) U! p# C1 \/ W& w5 h/* Enable synchronization of RX and TX sections */
4 E8 B: }1 P: K) \- hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 Y+ i: Q/ d) I/ ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* ]9 `: }6 R) R l; b4 h. U) \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. _4 W* X) [9 U0 }** Set the serializers, Currently only one serializer is set as$ [: C& n6 ?( t) M
** transmitter and one serializer as receiver.
& l4 Z3 m3 X5 I! f9 L*/
( S2 b6 ?& v$ }0 j! ? d0 C% p- tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, h8 ]" N8 n( H; V/ q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
f4 M3 E9 G% m** Configure the McASP pins & G3 D3 g6 @2 j& w! ]5 {8 l* O
** Input - Frame Sync, Clock and Serializer Rx5 W! x/ O: j4 H9 G9 D
** Output - Serializer Tx is connected to the input of the codec
5 h1 `0 D3 [7 P [% }2 @*/
' z+ u6 `2 T, _% y3 m" f6 b. V9 yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' S0 }$ k2 x; i, t% w( I- DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ x/ C( c9 ^+ k; r2 ~6 ^! w0 l* K" n% {8 T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* }# ?- ]" w$ c$ @9 u: x1 x| MCASP_PIN_ACLKX
T" M" \; _& y9 B7 X" J| MCASP_PIN_AHCLKX
2 Z* r o) z% R; g& z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 I. p8 A, q/ F1 z# FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ p8 G5 i9 W$ t7 s| MCASP_TX_CLKFAIL + |% o* x" k$ x
| MCASP_TX_SYNCERROR0 z @0 z O! t; p4 I5 F3 I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 M5 V+ f \- P6 x; r: {6 h
| MCASP_RX_CLKFAIL: h- Y: F" O( W% H0 ^) a( V% Q
| MCASP_RX_SYNCERROR
* q9 o2 A& I' b# L/ K) o| MCASP_RX_OVERRUN);$ S: }! Q' R/ K0 A$ Q* T; s$ W, _& I
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
4 o0 y ~9 D2 h4 Q7 `; [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); s8 H" F [8 g2 Q& k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, \* c( Q8 t1 V# x$ ]7 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% U8 v) J, k: N2 V2 [% |EDMA3_TRIG_MODE_EVENT);% e c. E& ]4 ?/ ]1 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' _6 ]) D+ p! m @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 A% X6 Y2 Q3 \" a wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# C$ X& ~6 J+ V C9 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* S, R* ~$ S3 \5 e; _8 L% p, \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" r( F5 l! a0 l, I* h' }; B4 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 d( m9 K; R9 P: \% M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" `3 d- V. X6 G1 ~& z2 w4 p8 x
}
' L7 o1 j2 M3 S" g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - c o h/ L( c' B4 d" J
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