MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
8 B9 s, j9 o" Z# ^6 f  Z7 v' Cinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
1 }5 H: I( |4 S! m9 s4 A8 y% i0 _! }
/ L5 b( @- |7 o1 w; q( |" c) Doutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
: `( v; Y* x' e1 ~) S: `- }output axr1,
+ F; `" g; M- J% z4 G+ C

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
' n4 _; H, b! t# a! p+ cassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
" t- N9 v9 I! AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
' E$ _5 t0 \  K+ q* s+ z( OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" [5 U% @' p, K- v3 G7 U/ P& ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
8 A4 z9 G7 W/ W9 q: k6 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 A% s/ S  u; l9 ]MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ g* q5 @7 Y( U" }2 CMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* o, U3 Q1 W: ?" R2 @/ KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" a) z* a2 }* s9 e( P. I/ eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* T) }7 A5 S  u% W9 cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! }  X+ s, y7 r9 CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
2 s$ [$ A+ J2 M- I8 J4 Y3 P7 m2 z* @; cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 B- s+ U$ c; C0 I; L* c6 rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* u8 u! A; @; K/ V% L, LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

4 h9 B6 t" |. H  S% ~/* Enable synchronization of RX and TX sections */
8 A( L2 U8 P; G' [! E$ b; PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
1 ]) P/ O$ ~3 e( C9 B*/
1 s' d/ L5 [" d; uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 Z3 z9 P2 N- W+ \% i$ y1 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
9 q2 K" K8 u) n; [8 x. `** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
' o+ S# f; S  }' B9 g*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' w+ `: ~9 W: y0 |2 l" B  W9 U" _' oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
# p0 P5 M  I4 G" g! T| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 s: _4 q+ ?) {| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
, E! Y' L! H3 [: s, |9 E. _) f| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
$ I7 P* V, L8 |$ l}

static void I2SDataTxRxActivate(void)
9 i, t3 l/ V! \: A4 G4 W5 j# h{
/* Start the clocks */
9 C* u$ W8 R. [0 iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, l3 T6 X/ T; V# c# e! V9 rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
- h3 L6 G" O! \! Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
2 L6 g! U; I- p9 s3 A9 m* w* {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! G. x9 f% B* A  X* @# D% DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' U( ]1 K4 Y- m/ L( A* n}

% j  v8 p( ]  J- k: Y

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

5 L' Y/ b  b1 G