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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 `8 a5 a; Q% x9 N
input mcasp_ahclkx,1 r. f/ i9 a. Z& T1 Y
input mcasp_aclkx,
, } T3 M) x; ^; M! n* ^input axr0,
9 p( e% `& A/ d7 Q9 U/ g( s8 p8 ?0 {' r+ f+ a- ?* p- v% ?$ d
output mcasp_afsr,
8 E! q* T# f+ y3 l7 m2 H* z9 O+ ioutput mcasp_ahclkr,
! C" H: H' ], doutput mcasp_aclkr," ~/ R6 [! X( w( x, F) ^
output axr1,$ l0 s( ]. e0 v9 v0 ~
assign mcasp_afsr = mcasp_afsx;
7 Z! C# b7 D% r, v+ f3 jassign mcasp_aclkr = mcasp_aclkx;
" r4 H1 |( B0 W" _% U, Gassign mcasp_ahclkr = mcasp_ahclkx;% p$ Q! w, K- J$ B! d
assign axr1 = axr0; $ D, u4 |/ [% I/ Y
9 U9 t1 k2 }9 Z6 h' c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : A# y: L' c2 l
static void McASPI2SConfigure(void)
' ?3 L. Y5 G+ G) p0 f- H{ G9 y( G6 x, E( N, L8 o2 `3 ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 y& Z0 O7 v8 a/ r, G. g% a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% G2 `0 B* ~9 e* f2 @* qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); @9 M- N" T, A: _8 S$ @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 j5 i* q+ W6 L E- Y! K- S* [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
y& H) ]# V# M" p! h WMCASP_RX_MODE_DMA);& q0 x9 i5 [2 ^5 ]; L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! x0 L+ y+ l2 I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ Z* X' g; y& k) [) `' }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 J+ l" f' g8 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 W V0 C" ^8 H" \* I8 ]( _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" m5 @- D* H8 i! I& n& D; u5 |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// S6 r' J( @/ a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 \) {+ Y: h. m" v7 U7 B1 |3 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 S J+ J8 o+ G) B% U; X3 d2 z: G( E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ v2 k) E L8 \# G2 w0x00, 0xFF); /* configure the clock for transmitter */* [/ D% C$ j2 O2 Y/ }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) T4 o2 l/ O2 s3 fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' Z4 S/ A; {: @4 R' w3 E$ f% K4 b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- R5 q S0 v8 i
0x00, 0xFF);
; z# Q) i4 J+ n! X, ?! j0 I; D7 t7 R( X2 j2 n0 i9 c+ W; D; F! T
/* Enable synchronization of RX and TX sections */ % G9 Y8 l) e$ d2 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) l. S6 ?! u" e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& K, w6 |4 M; w' S' |' F9 Z9 ^/ j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 y" i1 X$ G3 E! j* p** Set the serializers, Currently only one serializer is set as7 x X4 ?/ B! u% W
** transmitter and one serializer as receiver.
k9 Y9 E. V2 }3 |7 i R*/6 u! A6 k* l6 Y" G W. {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 {% [) _7 y6 E! j8 i* d1 J8 |4 g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( r4 y+ H' Q; c' }** Configure the McASP pins
, Z. S/ b7 S% m** Input - Frame Sync, Clock and Serializer Rx8 U7 k; R0 v1 L( y
** Output - Serializer Tx is connected to the input of the codec
% ^6 `9 u# m8 f* l3 H- v6 e, Z*/
9 }% e" A: u5 g2 `% x9 q2 u: HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ x+ ?3 }3 x' c2 A, m# lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); K5 }) F1 d Z% C) G6 H3 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
q- R: i- z: m1 L3 g| MCASP_PIN_ACLKX8 V& H7 u/ p y- @: f
| MCASP_PIN_AHCLKX
! G9 u/ a) v" r+ Y6 D7 f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 d. n4 g" V; f+ ^% pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 v( t: M9 t8 A m| MCASP_TX_CLKFAIL 7 |8 ~2 c! y$ }
| MCASP_TX_SYNCERROR5 X0 c- d. A+ V; v; Z. J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! n: _8 u( o( }# o$ V$ U* \
| MCASP_RX_CLKFAIL1 t6 @2 O9 ~$ ^5 A% `6 S1 W/ q% {
| MCASP_RX_SYNCERROR . n2 _+ p. Y* z @% U
| MCASP_RX_OVERRUN);
6 v. j# l% J/ Z+ N} static void I2SDataTxRxActivate(void)
4 H, k" E5 z# Z7 f( p! g! o! t{
\1 o+ Z" k4 e" C/* Start the clocks */- e# `! R* V" N9 k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 A3 G" v$ @" d- ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' }5 N9 V: s4 j y7 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- ?% I9 c4 o' m& E" ?
EDMA3_TRIG_MODE_EVENT);
% s1 Z0 @# g7 P/ t( gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . p" v$ [" a$ F' ]( s( V) e* M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" P) z( I# p% n! j. H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, L/ V8 G1 j& ^9 ^0 K& F& V# vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% i& @! H; w+ }$ s* v1 J1 \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- d* i8 v, o- ]( k, P* OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 C! \7 r3 G$ d; W2 s) C6 LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& t: U% k! ^8 R) U5 E' F& m) f
}
& G6 w& j8 u0 z, D, ?7 n/ R) [. O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . [" H0 F" X* v- v- ~6 G) M' _
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