MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
5 O+ A& ~  f; I+ ?' Yinput mcasp_aclkx,
input axr0,

0 v% \8 r- d# I& n+ b( \output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
) t- v" f, I- h! g/ k( cassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

0 {) ?+ l0 O8 Q% \- P
3 y' ]  p5 }5 c9 y

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
3 e: k. Y; F" P# i) EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
6 E, E5 a" h* [- Z0 wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
% w% W3 L2 X0 Q" f* UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 s' v5 f! q) f/ t$ x* ^# iMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 @& c0 R6 C: bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 i- u) L; A( A% e- IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& q' [' O1 z: B( l. b' j- t& `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
/ n3 v% _+ x7 ]! y2 G& m5 kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" U2 N1 y/ p$ R" @0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

9 q4 q; d' I9 _. P$ Z/* Enable synchronization of RX and TX sections */
; n$ ?0 g1 G5 F2 @" a) ?# mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
: o4 ]  q: G: ~8 s$ vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 y- y8 O6 T5 m3 I% V3 _* dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
) i2 ~  R4 F) U*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
' \* Q+ C" S0 O8 k* ]** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
9 ~+ G$ x) M/ P3 [0 |' J  Z/ p** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# {7 h1 z# P; T# VMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
1 X/ B1 k& B" D( K# S- U4 u5 I| MCASP_PIN_AHCLKX
  S# Z  \: C- Z0 E1 E8 g% d' [7 k| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
: i& y, }( J1 v4 ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 Z% ~" [. O) ~. D/ r| MCASP_TX_CLKFAIL
9 w% P  l  t0 M. C. y| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
, L- k( z" K" W9 m( F- R$ l| MCASP_RX_SYNCERROR
2 T) D& l, }( w. H' `7 |  J3 {| MCASP_RX_OVERRUN);
" E2 j+ y8 Y( ?( O}

static void I2SDataTxRxActivate(void)
2 V0 I1 D5 N1 j. k: f. W+ p{
% m! h- U3 H+ e; }/* Start the clocks */
" V' v5 n, L# T/ j' BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
* A0 {5 L. [6 k4 |" r8 {! p$ HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% B/ W* G1 w: `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
' ]: x. T7 B" @( s8 K$ s/ pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! w% l# X! t, g4 B& L4 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
! d1 Z# w/ d( u! A9 ?- Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
2 A# G" V2 \$ ?; C5 N0 UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 o( Q+ H4 w( E+ F2 PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

7 o' C% s% ~; T0 U% ]% ^) ~. n

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

8 Y6 G& I5 d: V3 Z' r