|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
k! L6 J; i% l- p( p( g8 |& linput mcasp_ahclkx,# p1 C$ {0 _$ ~! d7 o
input mcasp_aclkx,
^) k+ Q1 P, X( n7 G0 e3 hinput axr0,1 o: l/ Q$ w0 x, K, W
8 K: p4 l5 \% E9 zoutput mcasp_afsr,3 A `: D5 x0 ?# t W
output mcasp_ahclkr,* Z/ d$ A. F1 `4 B* Q7 }+ A
output mcasp_aclkr,
3 x: }% P6 n2 \) Soutput axr1,, P8 y: U2 K. J; ^, y# l
assign mcasp_afsr = mcasp_afsx;2 b& @& G" w/ K' i; I
assign mcasp_aclkr = mcasp_aclkx;1 y: l! M/ G) l; `5 T
assign mcasp_ahclkr = mcasp_ahclkx;
5 Y9 W: G: y ?; W- aassign axr1 = axr0; ' c9 Q" A, i3 @0 P. F
0 Q; t* S4 {8 b/ R. u P' W, L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , m% u+ ~, _. \' G/ A
static void McASPI2SConfigure(void); t$ ^- @/ k9 e ~1 h8 N
{8 o E& s! a% D( W) C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- j' O, g+ q9 Z; W) t: y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' [3 N/ x/ z) H5 I! w7 k. vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 @$ v6 d& Y7 T% B" h; E$ }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 y3 L: v4 o) J* x/ l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 m7 U: O% u& O5 \ rMCASP_RX_MODE_DMA); Z+ G O1 d. ?/ z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 n0 \8 z3 |9 |7 i, h* ~0 L0 q6 `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 J" W/ H/ X4 t, E# U7 y: u& x' @* `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 E: e+ V" D8 c) R b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: f: L# g/ O% f. v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: Y, C [" Y2 |/ _: NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 M# {% }5 }- w4 E3 ^- }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
g. d6 [4 T: } BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + i! c! c; d' J" q& o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: R$ o7 @% i' a: n: V; ^' N y0x00, 0xFF); /* configure the clock for transmitter */
( i9 s2 X( p1 N% Q4 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( l. |9 _" l1 N0 q% {! x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 t2 G% g I/ V* L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 q8 P% I% ?' j# A4 P/ \7 A0x00, 0xFF);, K6 g% c3 w7 C% z$ m
, {% r+ ~( W1 S# U
/* Enable synchronization of RX and TX sections */
" T( P9 G3 \2 Z1 U5 o }; uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( D& L w: O5 N9 n) P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( k [, a4 v7 c+ T& ^4 |/ ^3 h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ U- {3 j6 W* z2 E" Z; ]$ _** Set the serializers, Currently only one serializer is set as2 [+ o8 ]' ^- W4 h. D# E
** transmitter and one serializer as receiver.. l' y+ b( J' N7 U- H- H w
*/+ G8 e! L. d5 G, ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& P A. \: \. h5 G6 A5 mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- U. v. a2 }: j1 A) a; F$ ] w# p O
** Configure the McASP pins
& l/ r j5 Q( W7 I** Input - Frame Sync, Clock and Serializer Rx6 H, E% a$ n+ [8 _
** Output - Serializer Tx is connected to the input of the codec 0 ?, q) ` I' E. |
*/
( {8 t) ]' g jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 D* R8 y& Q3 \# Y& Y" Z1 ?4 K x- IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. h" u0 n/ ?' w8 R3 LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( F( g, }5 k, |5 Q: P$ f* c& V
| MCASP_PIN_ACLKX r' c" N& Z% Q+ o) ]' ?+ ~- C
| MCASP_PIN_AHCLKX2 i: [" m. A h2 b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 Z9 ?$ d3 Y `9 D h! I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 P% ~) [) d) p' n| MCASP_TX_CLKFAIL ! }, N* Q1 y- E* }7 }
| MCASP_TX_SYNCERROR
+ p3 }( `4 A; w4 f% Z# N5 g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 M. X! Y- x" |: @8 }
| MCASP_RX_CLKFAIL
* ^! z: C. _; U/ a z3 `| MCASP_RX_SYNCERROR
0 w8 I7 y7 j7 @' h| MCASP_RX_OVERRUN);$ u" j s O3 Y$ h
} static void I2SDataTxRxActivate(void)
3 {: t/ D0 ^/ @& `2 g1 e" @{0 n/ b% Z# M4 K, N D7 R
/* Start the clocks */7 G5 P3 F- X, g5 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& e+ b7 E; H1 ]9 DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 q7 K% U. P% x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ ^# ~% K [) b4 w4 ~EDMA3_TRIG_MODE_EVENT);& g; r5 n5 n, w7 e. {" T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& Z; [) C, I9 [, vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& s2 M/ {% N( y# C3 N- }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. v* k. P1 W' ~- i% }' y- _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" t6 a& q7 i1 A* f+ G: g! v8 h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& h- ?1 [) x6 N! }0 G# EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ N1 n1 d) S7 K3 ]' Q( e0 Y% y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 [6 i% D2 V6 J5 \$ e3 i; q}
& l* f8 R0 d" I/ P Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
. D9 \% H$ b$ f2 x% O& ^! J2 K |