MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
/ G; h) T. L3 L' ~/ U- k. `: Kinput mcasp_aclkx,
input axr0,

output mcasp_afsr,
: U1 I; n4 r* Noutput mcasp_ahclkr,
output mcasp_aclkr,
  n7 C# c2 C* Q5 q9 n' doutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
+ S5 i  c5 |' |; t1 u* GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ ^4 G& A4 P/ m2 n5 c8 xMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# ?( o- o1 [; x4 ]! P$ U, m% Y9 UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 U- l5 h. U: g2 f( UMCASP_RX_MODE_DMA);
! r$ V9 Y7 B. k6 u! tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ h. H* R& s, `. K# H5 M4 yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. U4 }8 O8 o5 _) @& FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 N* W: A0 a% [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) G( Q6 q: j8 s) TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
2 Z2 Q  o0 f& cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 y$ U- T+ Y7 w5 lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 P. P! U  {) W. f$ x3 Y- V. sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

0 c3 A1 i: S/ `$ G. y/* Enable synchronization of RX and TX sections */
, [( j* A  L9 T: h6 J' _' E4 q+ oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
: n4 x/ s2 D* q: n! o, x! a9 y6 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' ]9 N. {2 v; V! T3 j7 L0 z% lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
  ]0 u. W% d5 L- T7 ]& z7 f( J** Set the serializers, Currently only one serializer is set as
- z7 \  @' R9 F. t8 t- |** transmitter and one serializer as receiver.
. d* ^: f: ^  s5 D. B( F' X/ h0 b*/
- w: U0 x7 g7 f5 q, B8 B9 o% OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 J5 s# ]% k0 I5 z4 l* EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
( O( f) h, }+ Y9 O** Configure the McASP pins
0 |5 M# [, j4 `; M** Input - Frame Sync, Clock and Serializer Rx
5 u# Y$ g& T: E- ?1 f; v5 \** Output - Serializer Tx is connected to the input of the codec
9 w3 g' @/ f; I& t! F( U5 H*/
: ?) W- M+ b* {! O6 f! O! tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% V0 C$ m7 M3 x4 K1 ?| MCASP_PIN_ACLKX
: z5 D; L$ g& b0 t| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
4 c" ^8 l+ l3 L3 G4 W/ `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
8 Z* Q! @) H! U* M& Y2 _| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- w" o& a1 Y: i( S- X: d| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
! h) q- j4 `6 F9 B, h7 g2 S5 t0 c| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 b; R' ]; u4 h2 Q: a: YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
. z$ ~" C- H5 _$ R4 }% Q: YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, s; R- M: A" q3 R' VEDMA3_TRIG_MODE_EVENT);
8 a2 }. B4 l  S7 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 j( @) e; m6 `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
# ]& k  Y4 P# g  F% kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 B" ]9 O( b5 O2 {( ]7 d9 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.