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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
z4 Q l% V8 X) I/ Zinput mcasp_ahclkx,( S- r' j" T, N
input mcasp_aclkx,. N6 p1 V/ e. t. A) f
input axr0,9 P, k6 K9 V3 @7 q6 O6 [3 W
' x: j* Y. n! aoutput mcasp_afsr,
$ Q9 N9 B9 O1 L3 Koutput mcasp_ahclkr,4 j; a' F! J. p
output mcasp_aclkr,
; \7 y9 }! u0 ooutput axr1,( C. C0 s! i0 Z8 @( Q( `2 R U$ m
assign mcasp_afsr = mcasp_afsx;
% J% a# Z" W0 ^assign mcasp_aclkr = mcasp_aclkx;' q' ?( [* V0 V7 _( Q k
assign mcasp_ahclkr = mcasp_ahclkx;2 b, A6 N g" y3 f
assign axr1 = axr0; : C% Y' G; N9 K1 d, e9 G+ |( R! V
3 y. H) u* O. Z; E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( n$ \& a, q' w7 A
static void McASPI2SConfigure(void)
1 _' V; S: L8 A{7 C% R3 {, C6 d3 T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 ~$ [- |4 h N% T0 ]+ a7 k3 o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! Y5 r4 s6 C: p& A% m* eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" Z5 l- q- _8 d$ V7 a1 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 W5 R. O% Z3 H% f+ I9 ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," [+ W4 t+ l; @" v7 ?3 B
MCASP_RX_MODE_DMA);
% }0 q2 Y* y; J. i4 e0 r1 K/ tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# p! [' y2 x3 T( R; b6 d) l9 iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 H) ^ ?/ \; I( f2 U% O2 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; ~: u9 p8 W+ c9 i0 X% |0 WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 ~; R# q0 K- s4 B. }! b% |# DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # A* U. { `0 w7 p; h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ D6 g- V6 S# x% w7 r3 pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, l+ a9 g( X1 FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# w/ S% ?: R; D7 D, N" u& VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 [0 }, U1 }- U. `7 z
0x00, 0xFF); /* configure the clock for transmitter */
/ Q, h3 Q& g6 ^# ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- q) @0 L5 c; M9 D" ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
X' I; n% B6 l7 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," v8 t+ y; @" x) o9 q
0x00, 0xFF);+ c/ V& X: @: s: \
) ~! L+ h3 ~* |) |6 U& _
/* Enable synchronization of RX and TX sections */ 0 G7 b4 p+ I/ H5 ^- Q; h1 q9 w2 [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 R, ]5 ?) q5 Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ K/ w0 i' D0 b4 z: r! x) {; i! J( V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
i m! v( i# E% I** Set the serializers, Currently only one serializer is set as
: Q8 d8 T6 p! h F0 k6 s** transmitter and one serializer as receiver.) B/ F) V4 R# w. t& y
*/+ J1 T$ |: ^6 h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% {0 t8 k$ Y1 N7 _/ n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* `+ o+ n9 S& |3 l& J
** Configure the McASP pins $ d4 H7 Q: ]& e4 {4 B
** Input - Frame Sync, Clock and Serializer Rx
' o% u) ?/ b$ B. @** Output - Serializer Tx is connected to the input of the codec # ^# Y @# ~# C7 q% Z
*/
: {0 W U% Q2 i1 @9 r T; @7 CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 T" Y, A1 b* w* r. X: ^4 K J+ h+ `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 B: x) d8 X2 t7 F" u" u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" q5 T! c2 {4 M7 q! X: S| MCASP_PIN_ACLKX
# P: ^- n4 b; i0 `# |1 k7 c* J| MCASP_PIN_AHCLKX h2 n: {, a/ r! V. w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; U9 { x1 Y1 ]' ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 }/ l U0 J; U" [! {, }
| MCASP_TX_CLKFAIL - C# M: V* d+ s7 H7 X5 ^" V- ^9 A
| MCASP_TX_SYNCERROR
7 o8 n* f- a: E" i; s4 {+ z. I% u4 e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* a, a. A: I9 b- A| MCASP_RX_CLKFAIL8 ]( I; @ Q+ K1 m7 g
| MCASP_RX_SYNCERROR
, W3 M3 W7 b# W+ ^& l| MCASP_RX_OVERRUN);, H3 S+ K+ O* {+ Q9 u# ?
} static void I2SDataTxRxActivate(void)$ h7 ]2 N s3 x4 J8 ^7 \
{
' S: ~' |, H# z/* Start the clocks */4 X5 P* _2 U$ Y0 @/ G& M% D6 C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! p1 P9 R; R3 O8 j' @: Q) R# G/ [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ p6 d$ U* h6 Z& e& ?& X3 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# {7 ?4 A. f ~: S
EDMA3_TRIG_MODE_EVENT);9 t* f- m4 h0 P4 F) o7 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 R+ V$ t2 m$ Z5 H+ ]1 x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 i6 H: x3 z- M! TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. i' ^& c+ b7 n) U- z# O8 F$ }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, e, @9 t* u6 N7 x- T' ?/ I4 _6 @: Y! Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! Z) [* s# |4 V$ U; }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 k- I8 x9 }2 K- V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; M6 I7 E3 _& c K
}
/ C9 s* \9 ~4 _' j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 M# h/ P1 ^6 R% {1 A: U% G0 {
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