MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
) U% ]0 C% j9 L0 \. Yinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
6 ?1 e0 b! G1 m% r3 l. N1 D$ x
output mcasp_afsr,
. r& d! ^: |& houtput mcasp_ahclkr,
  I6 Y& s& b' q0 o: Soutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
# f# o9 I4 Y" U' I! Kassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
8 r$ u- R. I; y7 |  m, B0 h{
# ~6 @: I2 ~) |7 g+ mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! z/ E$ L$ k% p- f; Y9 H& g( XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
1 L2 D0 {3 B1 D) w) {; |% V6 c. q% fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* k& T& j) k4 G* u& [MCASP_RX_MODE_DMA);
  ]& t' @/ A% R6 h0 `7 y" Z1 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& v2 L, k; e" q# k) y. oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
- V  w& P+ h" _/ LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 ~* \& ?+ @1 y; P8 o5 s1 NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. n; m- }6 M, I; ^0 D0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( \0 Y2 Z0 a" F) Z( t. P6 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
/ |# |. o! L5 W5 P4 a" ?# F
  M: _) B  w& j( t$ w; u% G6 a/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
" A! N* T) F: eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 C5 x) X! |: n: X, oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" O9 |5 c  j* C9 M0 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
1 p* g% b0 V5 I* o' h' u** Configure the McASP pins
1 F' e5 }# q( [$ |& ^** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
3 }* K/ ^. Y3 K- B4 z' F- Y  A*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 V- G6 D/ R0 w" M  T1 DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% k1 N0 `7 K9 X& u' [| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
5 B! {/ w$ ^( ]; u* K| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
- a+ `5 Z0 [( NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 l- t2 o% Z# l& v; c| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
" _, Z+ h. {8 B8 N  N$ G9 o. G| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
) Z) G; a1 R9 c4 Y0 W| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
" L$ G% A* a7 ?% M; v( v}

static void I2SDataTxRxActivate(void)
# e( S# @+ Z  G5 H0 w- t{
/* Start the clocks */
5 N/ ]" ?5 c8 {1 u- k; [. x% ]. LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
4 e# A7 r  i+ Y+ N+ Q8 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ y6 X, V! C4 ^3 \# R- rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' D: G3 e2 c3 \3 t8 K7 EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) |' }+ ~; u; U+ J6 q}

8 m, p2 t" W4 Y

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

. ^1 k1 H- }- _* P$ D