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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ N* s! c/ b+ k1 s6 m' xinput mcasp_ahclkx,
5 i! e! N6 W( g, c2 Tinput mcasp_aclkx,
0 b+ d& ~* G7 o* R6 b0 b1 Ainput axr0,8 |) `/ z6 G7 D
+ v0 K. T; X( T0 o5 z, Q( Q1 |: noutput mcasp_afsr,
! b# H) I8 J* Noutput mcasp_ahclkr,
0 d4 w9 b6 E5 ?$ K4 M! J5 L/ x1 coutput mcasp_aclkr,6 L4 x3 P2 l: {: G
output axr1,' ^+ M" R9 }4 |( d4 m
assign mcasp_afsr = mcasp_afsx;1 \- e9 s7 ~* h0 w
assign mcasp_aclkr = mcasp_aclkx;
6 W- {5 ?, F) n" Dassign mcasp_ahclkr = mcasp_ahclkx;
+ c) p$ [; w h ^assign axr1 = axr0;
: n! y4 `6 B8 E' K+ ?; t5 j- w) G- ?/ t! O9 P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 v2 n; e' Q' f! g) b, U* Nstatic void McASPI2SConfigure(void)' E( B6 l' D+ t( c9 ]2 s
{
; Q4 l v! m: S. d; z7 t; T- `McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 B% _# w$ Y3 Q5 W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 i2 ? _& @' |( @( kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 ~6 H, r1 c8 f. D- sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. N7 _4 c( l& oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' ?6 Y/ g) f) L0 E
MCASP_RX_MODE_DMA);
" z" l& g' w) a. v9 g$ J. _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ W# i$ I5 S( q' z: r' O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- m- N- s9 x& o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 Z8 g* _- W1 M- X/ B4 @8 RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); X% d! K" ^& x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # {- _9 T, ~" L6 E0 \; n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 E2 b+ z7 b0 O* T* E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); \5 n1 c3 W/ m& `0 f% g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 ~* N3 j5 g- W- l, q) o7 H) ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 o6 @, [) l: y6 E9 B; G0x00, 0xFF); /* configure the clock for transmitter */* d0 \$ p4 U' i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' }+ H, r1 m- U$ u8 \4 _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 g# k/ g, q/ m4 q/ O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' b5 o2 t$ Z* H5 C3 W! M
0x00, 0xFF); H! E# a8 Y% l7 c9 W& n
* K/ _1 d- h/ n# j/ ^
/* Enable synchronization of RX and TX sections */
" G/ z4 ]; V5 T, x! MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 t- v' l) C: v6 W. [1 J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, K; N9 C+ [* I5 _, h2 e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 m. s, S- Y9 ^! i. ]9 x% e/ }: \** Set the serializers, Currently only one serializer is set as( }* _3 [0 E6 P9 F; n% U$ V, S
** transmitter and one serializer as receiver.
; f7 Q- a7 ^8 u7 J. _. G2 p3 {& m2 E*/
' F' j$ A6 g( c3 ~/ sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 @4 r m0 j7 k' E- H0 h6 BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ n. k- n+ v5 s& [" `! u7 z' j+ @
** Configure the McASP pins
2 {2 O% \3 y( d0 S( v c3 ?** Input - Frame Sync, Clock and Serializer Rx/ \, J& }) \' a
** Output - Serializer Tx is connected to the input of the codec
6 L% R5 M# h# X4 J' }*/
3 \, s$ \" r8 R# W- dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, `0 U$ o: B N3 s3 \' T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, ]- ~/ y9 i# g* U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: Z6 [, H$ ]' S7 `# s, y5 N
| MCASP_PIN_ACLKX/ I7 E: W# H( [+ t0 \4 u' Y
| MCASP_PIN_AHCLKX1 [. H* T$ M- n* ~8 i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; i, z2 o& {# j/ V+ a9 J5 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + u- v1 G" Z9 w0 d3 ~. g3 y. W3 J
| MCASP_TX_CLKFAIL & t% q7 p- Z* M6 e6 f0 P
| MCASP_TX_SYNCERROR# d+ v: @3 w/ Y$ @7 _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
R5 W4 j5 L$ n4 }$ w| MCASP_RX_CLKFAIL1 ^3 ?7 X& x" z2 U1 o+ u
| MCASP_RX_SYNCERROR
$ Z9 W$ U+ }5 [% C! `" f' k' ?7 M7 I| MCASP_RX_OVERRUN);
' D/ o G2 Z* k& C; f} static void I2SDataTxRxActivate(void)9 b% J( A( z; W2 K- N
{
" x+ b( F5 i& T+ L/* Start the clocks */
; s$ _0 r4 J1 AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ \9 Y3 E6 c0 g+ r" M' l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 S$ e/ m) I$ s7 M+ M1 F. q2 t q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; d$ O" |! _4 z8 e' @EDMA3_TRIG_MODE_EVENT);
& {) ~* g0 L1 J NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * f9 U; }9 H* q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& y/ Q# Q1 c/ v" ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" @2 v- r5 f4 V2 w" S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 C; t K* L# s% Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, _- J% D+ N4 u" D" P2 lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 b5 T9 T# b5 [5 { L0 ^: M4 nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ ^. T( Y; V; Z- k" I) v! A8 y
}
+ i% _* \5 t8 y2 ?. J7 R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 J$ ~, H" |7 B: d4 n
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