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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' b" q1 q. y& r( u6 x
input mcasp_ahclkx,
5 f) s: e. s6 V* ?0 d. Jinput mcasp_aclkx,; j5 @* s% ?' G: ?& q
input axr0,2 t5 b* S* K! X1 X: v2 R [
# H/ N S: V- q O( f
output mcasp_afsr,
+ }) O) p/ r+ S5 ~* L; Woutput mcasp_ahclkr,
3 |" ~5 f. j1 c* Youtput mcasp_aclkr,+ B* b' Y# F4 d3 }' x
output axr1,
* G( |6 W g5 Y$ U" w: Y assign mcasp_afsr = mcasp_afsx;7 w2 y# W7 G `6 }* H- H
assign mcasp_aclkr = mcasp_aclkx;
) l, C+ L+ {, J3 t: Q$ |: D% |! s2 r( aassign mcasp_ahclkr = mcasp_ahclkx;
x4 m, f; }$ p, Iassign axr1 = axr0;
8 }4 a. v6 C% H! R
' ^; y3 B# H2 W+ f: V5 V d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! ^+ W# t& o, N' p* w( ]! l
static void McASPI2SConfigure(void)- j" x) c3 z9 p5 c$ {
{* [. _: n& F2 z, z
McASPRxReset(SOC_MCASP_0_CTRL_REGS); C* q1 [. C% h0 {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) H( Q! E; M* R9 ?- N% b3 ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 ^0 r7 k% t% E/ b3 k( E0 W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" [/ f) r* f) ?8 q1 s; C7 \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: [! N* E+ z: iMCASP_RX_MODE_DMA);
/ n2 H/ x. X/ E g& C( u. N* ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 l* J# T; _: M& r2 _9 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; ^9 S/ D9 k6 c) y4 Z$ |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / r% l4 i7 m5 v: a2 K! W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 \$ t9 _; A- g5 e2 ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( b3 T! q! Q, f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 o* r) s; { y" @# r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. y. X. [7 t7 t' y3 Q. ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 B; v9 o5 a4 u9 x& A v6 v% VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 N* d! K2 I6 s. Q1 a( Z. L% B% P0x00, 0xFF); /* configure the clock for transmitter */7 b, t& F; I: i; H* R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 f( `0 }9 u+ i. ]) z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , s/ F2 O& l' a( L- N6 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* [# K7 k$ y; b' L/ D0 W' v9 n3 K
0x00, 0xFF);
G8 ~% l" x, a1 h" _* K6 V+ l. `/ {/ \( }7 I
/* Enable synchronization of RX and TX sections */
c @3 v% h& x3 M, MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 ?6 s, b' K& c8 j3 F# u" ?* C) vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ y V9 a) }8 r c! g* M- IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ `% J$ g7 V" M" |4 `/ [1 }7 U
** Set the serializers, Currently only one serializer is set as
1 a6 b! x- T+ N0 }# R** transmitter and one serializer as receiver.7 A( l5 ^ n3 X; x( ?7 d6 E
*/
2 a" L: X# B- M4 x8 N7 F% GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 p+ Z9 m& p" l4 v- { i1 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 E' T) o- K! c, D* r** Configure the McASP pins 9 |5 w- \6 ^/ X/ n' M
** Input - Frame Sync, Clock and Serializer Rx
6 t. J/ b: I( [% J6 r: T** Output - Serializer Tx is connected to the input of the codec
! B$ C2 H. R" Q. e2 f*/
3 ~" [0 K \2 \% ~1 EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 a) Q/ o7 b8 u2 e( N- e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* V; c* c" Q& B6 c9 s7 I) LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 d. ?/ J! F4 s" s% E6 i2 J( P
| MCASP_PIN_ACLKX
) a/ R4 o2 {1 k, t( W& d: n| MCASP_PIN_AHCLKX* m7 B* I3 \* p, \5 z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: n8 x' \- W* G/ EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 }: J. q; [5 P& K# b3 @+ Q# o% B
| MCASP_TX_CLKFAIL
4 y0 x/ x: \1 G% s" `9 Q| MCASP_TX_SYNCERROR
+ v2 Y5 \7 r/ u7 h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 X& b% e# I/ i5 g
| MCASP_RX_CLKFAIL$ k9 Y: ^ U5 r' |) P; N% G
| MCASP_RX_SYNCERROR
1 Z% q2 ?" o, l* `% K- }, R# q| MCASP_RX_OVERRUN);" {8 Z2 J# j; U, {: k: V# r
} static void I2SDataTxRxActivate(void)5 `; A C9 |2 u( `
{# m" |! v8 d( Z8 w" b" b2 ?
/* Start the clocks */
( J6 w- o, |4 ^+ w1 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- J; i, r- X& |' qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& i0 v! Z4 R. E8 q/ W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! e) c; a' O: r5 X0 a3 L. e3 k
EDMA3_TRIG_MODE_EVENT);
2 g5 Y0 l- t& e; ]( u% `. t( SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , l* Q0 q* i, s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 S" P5 \$ Q6 i+ d" e' n, YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! r$ v5 `( C! E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' e( Y0 ?8 w. V% C8 v" Q* Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* T- ?# F$ W, T0 p FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" ]0 U! d( t5 wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- P; L% L s4 a$ F
} - P* A: D7 P/ U3 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 o0 Z! m- O8 Z5 v2 }# h
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