我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 Z* x8 d. @2 O% d8 V- b& L% A8 l& n2 x
input mcasp_ahclkx,
9 B+ L: e% N' {4 ?) w/ I' Minput mcasp_aclkx,6 h5 k1 L6 }5 `7 {! Y( I" N5 Y
input axr0,# Y- ?+ l" Q" I* U
& }) z8 c9 _0 Y' k" U7 h8 d+ e+ f
output mcasp_afsr,! @! i* ]/ [7 q2 [, R- V( V
output mcasp_ahclkr,8 M; b6 q: c5 H: G3 A' @5 S
output mcasp_aclkr,- c7 _/ L/ c, m' k z4 D3 u
output axr1,0 {2 x- M2 g& y5 u# |4 z
assign mcasp_afsr = mcasp_afsx;
/ m& [4 I# ]8 `2 j! xassign mcasp_aclkr = mcasp_aclkx;
# G1 U& Q2 r9 Q* \assign mcasp_ahclkr = mcasp_ahclkx;
" }; C) U$ r2 x4 Z: I/ I+ Bassign axr1 = axr0;
% T' |8 D* B0 l0 s( O8 ?$ ?) ^; Y% T* I9 Z6 {( b; {! l A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + v! {7 Z2 {/ [) ]- I
static void McASPI2SConfigure(void) Y* u4 C' ?' B$ |' B0 a
{
4 r2 |/ }, U X( _McASPRxReset(SOC_MCASP_0_CTRL_REGS);! p. G9 w2 d/ O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 H6 }2 `- I# _/ _# m5 Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( W9 ~6 W- I9 {5 \$ j) y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 K. N! O8 I8 O% oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 w9 H3 z8 \! a: a
MCASP_RX_MODE_DMA);
9 I) U, @4 @/ E* s8 WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 G. W, y6 R& r2 z" M9 ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% \& y9 Z2 U/ P* U Y, ~% n3 g u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 z y# T* R* m6 {) c4 ~! R6 YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- u/ l5 P4 G( K7 `: z( n% J; FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : m0 m2 ] \7 y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: l4 S4 q8 l- }. l* v8 a8 ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 J5 X! I( ~3 s8 ^. h- w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 G; U5 [+ x8 h, v0 z0 L! d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 {& l9 Y" ]% q% L" h% ]) B
0x00, 0xFF); /* configure the clock for transmitter */
8 A7 D4 Y0 C7 |6 N. m- R- @, Y, U1 VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 \4 ?1 V; _1 TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. l2 F- `! `% g: M4 IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
j( t$ w8 @3 [& R- ~2 \. o0x00, 0xFF);) u1 U4 S9 [. D9 O$ _3 g# t! W
! X# m- c; R4 K6 m/* Enable synchronization of RX and TX sections */ ) `3 U; E! ?! Q( K! H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" X+ ]* O% z6 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 m, o `% m3 g, x4 s; j: E* H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: r M0 `/ v, I4 O% l
** Set the serializers, Currently only one serializer is set as5 I3 x* J/ @( ]/ ?6 \5 v! [
** transmitter and one serializer as receiver.4 X: N5 _9 q+ Q& `3 }/ `
*/
& c0 Y0 Q. S0 Y% c8 o8 i/ O5 o( r2 }& HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 l& x/ { m3 \9 L) |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 |6 K& a! O& k: P9 x" \
** Configure the McASP pins 2 W. R( g# d, |
** Input - Frame Sync, Clock and Serializer Rx
7 a$ B1 z) R) H# z5 G3 m1 p: j9 c** Output - Serializer Tx is connected to the input of the codec
9 V5 G# _+ ~. L! l$ ^3 V. S8 C3 ~*/
' u; f0 }+ h' A1 v4 r/ R$ |& q6 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- {0 R: o- {* L8 r% I; t0 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" L, T1 s9 f6 x1 Z$ {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: w4 g) U6 z, `$ E% K: b+ j
| MCASP_PIN_ACLKX; n5 z- _, l; \) I6 U4 A' @
| MCASP_PIN_AHCLKX9 Q6 p- j8 e! n( [) Q* f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 n& R3 R, B+ Q7 H1 r' K# q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) b8 Q* M" z9 _; o4 C5 n
| MCASP_TX_CLKFAIL % O7 _. ~- W, P* w* s( j3 z3 `4 \
| MCASP_TX_SYNCERROR2 q+ A) w9 a$ F. b+ E- T# A9 z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " E- C& n6 `: h: S' _
| MCASP_RX_CLKFAIL- l W! G9 i/ a# h* ~
| MCASP_RX_SYNCERROR
/ y' ~9 _0 M) u, I4 H' P- k| MCASP_RX_OVERRUN);" s& y6 c* b$ p4 i: E
} static void I2SDataTxRxActivate(void)
3 s1 T {: t! ]& y{
* e, u. u: O; y, l/* Start the clocks */* y1 ?* s: U" f( p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 }; [' c# J+ b. p K2 H, }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( }7 C/ F: m7 |5 A" B jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 |; Q9 E& p; GEDMA3_TRIG_MODE_EVENT);# b: g" p8 g! _1 e' `% a2 V, }" v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " V. x4 {9 g' V+ G( A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- W3 k6 l" `+ D- p7 v! {* KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! l% |5 F5 H9 A. }2 y+ L4 V3 f5 W$ `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ N' `* {7 \: Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ E g# }" \- X/ p& {( x( {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- t2 _$ p6 P, X( r- G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 e& C& r) @. z
} 9 L' W- H8 O6 y/ m3 g7 X$ H5 ?6 k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 M/ Q! L$ `* [& t, p4 k/ R
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