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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, Q7 o* k: [3 A
input mcasp_ahclkx,
: t$ A |$ H* `' f- T6 W1 R3 g6 Winput mcasp_aclkx,: u( N* _! J3 `% \2 e# D4 o. W
input axr0,6 `- c( h9 ~* V6 |, I
- u3 p/ l2 t/ A, ~output mcasp_afsr,
: m) \" p' I3 S7 K) e% P" X7 m; [output mcasp_ahclkr,
, W3 Z K+ V7 {$ f( soutput mcasp_aclkr,
: o: K7 G3 E' h. b1 Noutput axr1,3 j6 q" O6 y5 T0 M U
assign mcasp_afsr = mcasp_afsx;
Z( ?0 n% x- ~) x; {/ R4 gassign mcasp_aclkr = mcasp_aclkx;7 J! m$ H* a( X( x6 W# {
assign mcasp_ahclkr = mcasp_ahclkx;
: A4 r# e2 i7 @2 E Nassign axr1 = axr0;
$ }" |( C0 y$ b) [+ o' l" w
' ]" ^) N2 a8 S; \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 T- {% R4 v( \ e" r2 Ustatic void McASPI2SConfigure(void)
" d' @7 J& l" @& m{
& b8 \7 N+ R+ W$ x/ e: `McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 s& t: v- S C! E5 ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: |# o; o. r$ }) ]( d8 s [: ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 G3 z6 }0 @ l' ?) D) N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 q7 z, [6 _" _- l" I6 a- r/ CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& w% j, j1 \# o5 _, U! ]1 IMCASP_RX_MODE_DMA);
. v( V. |1 \9 A* cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& J$ l. M; a' e" t" J" {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; }0 V7 g8 a' U2 b% ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . v4 C- w& M( z5 g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' ?- L% Q+ Y) x5 |) q: J! f% WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 F" x9 } i# \3 _5 ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" d, F$ _4 ^$ J: M+ Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( }6 R& S- K: h2 Q5 T5 L! ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' s0 J: d' _& C0 a8 o4 s& e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% x$ k( F# Z" i0 a% o
0x00, 0xFF); /* configure the clock for transmitter */
* d7 u3 w" Z: GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 E+ b! u* R7 _) W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; u* Z- f2 y! r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 i% Z( ^* C& W7 |- N$ V l0x00, 0xFF);0 f$ b+ Y$ {; Y w2 V
1 X+ V/ P2 n: w
/* Enable synchronization of RX and TX sections */
$ U, H( h$ b. s1 _ T* t& bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 ~/ b c1 F% Z9 C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ M7 m; X9 u) H/ o' C0 wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 f0 u4 ?4 ~+ d( H5 A4 _** Set the serializers, Currently only one serializer is set as! L& Y. I" f* n: f
** transmitter and one serializer as receiver.
+ j4 f9 q! ]& { F: \" R*/1 R0 _7 W2 z/ W8 J* E+ r2 R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 S- m1 r0 Q1 \) Y3 Q$ b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) G& g0 `* w" x& \
** Configure the McASP pins
- I5 i9 u2 x, R o: o& w8 d** Input - Frame Sync, Clock and Serializer Rx2 l7 }4 W" x& I- C' `3 P
** Output - Serializer Tx is connected to the input of the codec 8 O0 j- |1 ?6 S9 s& u! J& _
*/- }& o$ q( g. T3 e8 S$ y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
|' E W Z/ L# C3 z* \7 Y; ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# w z6 x. o+ N& B. g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 h4 O$ }# |4 d; u4 B6 U| MCASP_PIN_ACLKX. C `/ ~: n0 ]
| MCASP_PIN_AHCLKX3 [9 [3 ?# X7 R6 O0 ]( A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 G M2 _" ]8 j x5 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' R2 j8 m/ h% a# |" n4 F1 _/ l/ ^8 R
| MCASP_TX_CLKFAIL
5 }/ V) r [' \8 x% v| MCASP_TX_SYNCERROR
) _8 c$ I3 v' A4 }4 p+ Y9 d0 o7 L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; v7 {7 `$ n$ b% i) ?| MCASP_RX_CLKFAIL, H7 _$ s0 A3 T6 K" p
| MCASP_RX_SYNCERROR - h: ], G9 M& |; h
| MCASP_RX_OVERRUN);
) ^' I: l6 a0 G6 k" s! @ N} static void I2SDataTxRxActivate(void)
& U( M: t- L. [4 F& i. V. [{' j* v9 G$ }- n. o G0 k' I. V
/* Start the clocks */
" M5 i( k2 a6 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% i* [8 }3 t5 V& R. Z0 x0 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 ]/ I7 ? b' V9 T3 u- BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* |) |7 v; n6 n3 x% F3 `
EDMA3_TRIG_MODE_EVENT);* E( v( N1 k! u2 o! i$ _3 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" t$ {8 J# p6 ?7 [! _# kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 i, ?2 a9 W' r# p2 }, q7 S& l( p' nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" Q' o6 d) f3 EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 n i* F+ i5 T+ ]% hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( J; x8 h* @+ g ?, e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( G/ h. |1 K+ Q7 \6 x& A2 B. ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 s% h3 ?4 n6 Y) w# z) H; l
}
; m, J- z+ [( @( x: `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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