MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
! D4 g! a5 U" Ginput mcasp_aclkx,
1 G/ n9 v3 F, ^input axr0,
2 n2 E7 x: p  Z+ V6 ^
output mcasp_afsr,
# u9 p, |8 Z3 G: e5 ^/ ~5 Y  ^output mcasp_ahclkr,
/ m1 E# j" x. B) a9 @output mcasp_aclkr,
  Q, j  X& _! M+ }# {output axr1,
" K. S$ |* P- G0 c

assign mcasp_afsr = mcasp_afsx;
2 L7 v' r9 @: c2 Kassign mcasp_aclkr = mcasp_aclkx;
0 M; R( G) _$ F# m$ K/ N* L4 ^, ?assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
+ C- M) I# h8 O9 F3 v# n2 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# Q' N/ E8 I- r& u* vMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 H! j: j4 i2 t( c! D, D. o# I* v( fMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 \8 Y7 j4 E) @( B  n; p7 iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' O- U- k! m" y; f& f1 u+ ?: DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ A& ~% h1 R+ o  ~& |% lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 ?& u  U! ~& L, u$ C# nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
7 s% o. X) J& Q: V! p** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
3 v, t( a" A/ q& {! f** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
' X( u) A) o3 n0 Q) V# j*/
& y: V& C4 w# j; |: ~' kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 D0 S9 H' m8 M  {" q2 l, i) l4 JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 Q7 p3 d. _4 w/ e4 M( g| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
* w, s! |- S- g6 f| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
* A2 m" Y3 G% A& J+ x9 f4 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
- h. D% N4 O/ @! j2 P7 || MCASP_TX_SYNCERROR
9 w* W6 P, {. g0 U+ I% l1 [| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
5 p, C% Q, e0 H" g; Q! ^| MCASP_RX_OVERRUN);
4 W* O$ d/ U/ e+ }- q# P$ Q9 @9 y}

static void I2SDataTxRxActivate(void)
{
3 ]+ s8 X- F, ^9 H/* Start the clocks */
* ^4 j0 {4 Y7 hMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 u  e! W, T; N+ D: m, i4 j) U! o" OEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: b. [' ?4 a; p/ FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
" a, p1 o( @' [" j! ]" vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 c+ c/ H" b' b' [* t$ s( eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
& D1 Y9 i9 X9 Z7 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& B  g0 Q  {/ b+ A! U6 H: G; vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. ^. z/ p/ T, m/ [( j}

/ {: G6 T1 @) y; }

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.