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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# x/ s8 Y" e& U' Y! y; N/ Z
input mcasp_ahclkx,
8 C0 X9 B8 g! T M1 ^/ z; w( }input mcasp_aclkx,
# S9 O8 f' i" {$ yinput axr0,
1 U8 d$ `" y$ N/ } Z% U& m) N
$ Z9 V8 T4 O$ Y6 eoutput mcasp_afsr,
: W8 P X( B. J6 [4 Loutput mcasp_ahclkr,
' k# v/ R5 r' ^output mcasp_aclkr,
8 K$ R1 |1 N7 g8 y' poutput axr1,% ~3 w( M5 W! J; P; y, H7 U6 M
assign mcasp_afsr = mcasp_afsx;9 d5 ^8 V6 Q, n4 i4 U4 l3 S
assign mcasp_aclkr = mcasp_aclkx; a }2 f& j6 U% h) j9 m; r
assign mcasp_ahclkr = mcasp_ahclkx;
7 D; x. P+ i3 b1 Iassign axr1 = axr0;
2 h, m7 X/ N: p% M# B O3 r9 V' E$ f: e' T! r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- { k7 p, r" p0 Ostatic void McASPI2SConfigure(void)% H' y4 w" i1 }! ^1 T
{6 P0 N& w1 @& w; S! l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 Y2 G& i& S- w' i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( K% E3 ^1 z& a1 S, d4 ] R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ w5 P* b& Q$ [% W2 g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 m2 V' l) \' t$ W" a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# q7 {1 B; Z9 N. q5 q X5 \% R7 X- K
MCASP_RX_MODE_DMA);
; S0 I( z7 U2 O, fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. K! z% b! ?8 e8 f- J+ SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// D6 i Q) |# U1 |$ K1 Z( n& D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- z8 y' M: j# O3 l5 Z; p* a/ \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& ?8 s! g) D9 `! r4 ]6 }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' `8 j1 s9 d; i1 qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 }( i* ~! b! u# [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% `# u0 `# ?7 Y8 a QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ P& `) Q9 i7 g% n$ S3 aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 c9 h1 k4 g; i# J
0x00, 0xFF); /* configure the clock for transmitter */4 { S# k. O: E9 g! i7 o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 U+ a5 p) \! n: d" F, q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ R5 s5 [+ |9 C8 r/ F, Z) J: `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' R, \; X9 d1 j
0x00, 0xFF);9 |* u1 `) U- d8 L; c
/ r0 \2 V9 K$ K0 F! j {6 H/* Enable synchronization of RX and TX sections */
2 j. ^" j0 H( I" L) sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ r, }+ s' A$ D, E9 c8 ^$ fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( l% A- @) a* M! S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' l) q9 E/ D7 q+ t) n1 ^
** Set the serializers, Currently only one serializer is set as% v0 t( d3 k5 r6 E. A4 r
** transmitter and one serializer as receiver.& c u0 w# Z5 Z. `# I& B% t+ z
*/1 b# g' b: }6 D4 u6 J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); Y- r) i" g1 h" \% d+ m9 |0 L" {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 R! v( [7 j3 E9 z$ g
** Configure the McASP pins 3 I, b" q0 Q% h/ D- f1 J
** Input - Frame Sync, Clock and Serializer Rx
& r: r W- X8 M3 {' p2 q v5 G! j" ~** Output - Serializer Tx is connected to the input of the codec ( e* Z- ~0 E1 [0 e! l- M6 T: I3 @
*/
8 P- Y7 l3 s$ A. g; X% \/ xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: H9 c! P' A8 ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 L, {8 P2 I. d; n% @6 O; r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ P3 {' p. }! C( {" b
| MCASP_PIN_ACLKX6 D! G9 |) w- h
| MCASP_PIN_AHCLKX A2 O- q k/ L# G5 l+ c m7 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) l9 w7 u& U! MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 Z& y, U! |; l( U0 V
| MCASP_TX_CLKFAIL 8 `8 r" ^- M5 j
| MCASP_TX_SYNCERROR+ u' f3 h/ f+ T+ X! h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% @3 g; {; G: C; K' }| MCASP_RX_CLKFAIL; K) K0 h O2 q/ } M
| MCASP_RX_SYNCERROR
4 j) J( G1 ?5 l. C( E2 z" b! W6 f| MCASP_RX_OVERRUN);: c/ H/ }& g- u2 E# Q
} static void I2SDataTxRxActivate(void)4 e; \& C8 ]: G7 M- G5 q
{
+ k1 j D5 H' v k5 z, R# v/* Start the clocks */
* \$ E8 _; s6 ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: x2 D4 p( R0 X7 S! x& p& x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* U6 S; x' m) b, h! {- ^/ g. t; P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! [, `9 ] g, y
EDMA3_TRIG_MODE_EVENT);
* _- `7 j- w) t9 g1 t1 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % t1 @, E- i/ S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" B% c* ^& ^5 ]0 E. C* C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* {- f0 k1 Q: q4 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 N$ U( Q( c( q) M8 w$ ]( r c# Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 c5 F b2 `" m5 A jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' P+ E( u! q; E3 a- @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 D9 |2 Q6 j, x+ w& F- Z, X
} - |5 q: D, `+ t% D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* ?/ a+ K4 H2 I& H( `4 F1 v6 p% ~ |