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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% i, `* h" j0 ~$ ]% tinput mcasp_ahclkx,
' O& n2 U$ l# P6 w( Y+ I3 I) Dinput mcasp_aclkx,# W& ~8 m- m9 D1 N* _3 i
input axr0,5 t9 s% G) }+ z1 b W# d% B3 Y
5 p, W; t4 p) x# Q
output mcasp_afsr,
k+ G ~* T' [* Y3 ?output mcasp_ahclkr,0 N; u/ t& k. T( ^; I# U. g+ k
output mcasp_aclkr,% G7 b: K1 E! Y0 |9 \, H
output axr1,7 a: H! j7 n* j
assign mcasp_afsr = mcasp_afsx;8 D8 u4 P0 C9 D. ?
assign mcasp_aclkr = mcasp_aclkx;% T9 d& m; K" j
assign mcasp_ahclkr = mcasp_ahclkx;
. o, H. \2 d, c, p8 D& p: lassign axr1 = axr0; 9 t. b ]9 b3 h; I% X$ ^" s3 c. {
( U Y1 C, N& z; n+ e, n$ |9 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
a% e3 z0 w/ I: H4 d0 Gstatic void McASPI2SConfigure(void)
. W6 p( u8 D8 q& J4 S{
% {' K* Z' {" L# }McASPRxReset(SOC_MCASP_0_CTRL_REGS);( a1 q8 z9 h' J$ C% ?6 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 o9 a0 i6 U8 o7 W; J; X. g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 q H1 X- f. n. U4 r5 CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 U! w6 s" G: U. O2 W YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ E) |* N/ q J6 S: ]- j3 Q3 [
MCASP_RX_MODE_DMA);5 u& F( w5 Q9 w9 Z- e! U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 i0 ]; O4 y' ^1 Y1 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' M* A! h* y5 m/ t, F$ L$ v% i; v# |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ V3 \6 t7 M& h" m$ e3 Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* u" {6 g6 J; I* \3 C3 y* dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 z4 R( @: q" J; s( L8 ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. r- T) e) w1 D& {( bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& r9 ~5 m* i: [- {' qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! a8 E' u* ^0 z, R, U7 v5 j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" q2 s/ l j+ J5 S8 W9 e0x00, 0xFF); /* configure the clock for transmitter */
" A. B0 u% g; U7 i# P2 @6 lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 p g; f- a7 |% L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 Q; l. r' I1 ]: ?: B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 L3 e: j- L; X9 Z- @! p0x00, 0xFF);; q9 e6 T$ G$ _, K
/ M( M( D0 [% b2 Y& X/* Enable synchronization of RX and TX sections */
# x% n2 \ s% m* c" a. Q! aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" z- C1 O6 q( ]9 m" s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- C, |- y- r- i3 w5 i7 g8 [$ pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 S+ Y8 u: b5 V% i0 h7 w; q** Set the serializers, Currently only one serializer is set as
' V7 Q. b$ P: _4 p7 i/ K) M, E** transmitter and one serializer as receiver.
; G$ M1 y# z4 y) b0 j3 G*/
6 {5 t% t' N) t- D. T' BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 F% _5 N0 W r! c- X" e& q+ m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- p: J$ ?+ `6 ~' r& `, k+ l6 @
** Configure the McASP pins ! i% B% u0 J. \, C ~
** Input - Frame Sync, Clock and Serializer Rx
: `% s1 U: a8 L9 ~8 \** Output - Serializer Tx is connected to the input of the codec
9 p3 d6 i/ ]) W9 C6 c% j3 u*/! S4 P9 ]% b; w! u, ]7 Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 Z9 ?) D; l& J) Y0 e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ A& `: y5 h/ SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ @. r# y. z& _% A3 W/ }6 ^| MCASP_PIN_ACLKX2 B* S0 {! X* Q* \+ Y6 ?; _2 g
| MCASP_PIN_AHCLKX
0 L7 h* N$ z- s$ k0 q9 ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 ^4 w8 z4 D A' ^) W9 S0 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 i6 c/ o+ e$ B| MCASP_TX_CLKFAIL 8 a% d6 k/ h/ W1 u3 S2 W& y2 Y
| MCASP_TX_SYNCERROR
9 A; S9 u% l; a6 O, Z" A5 \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: p4 B& L/ h: q$ @1 m8 c# s L/ E| MCASP_RX_CLKFAIL9 m& I6 g) g0 `3 Z! w
| MCASP_RX_SYNCERROR
. A1 l, r7 S2 f# |4 D' k2 _: @| MCASP_RX_OVERRUN);1 o" q8 P. U- K; D6 f+ V4 ]% L
} static void I2SDataTxRxActivate(void) S( }) N& M% o# w
{, J- a$ u/ M$ @1 f) r$ z2 C6 F
/* Start the clocks */: H3 K! q+ ~1 d1 q+ x6 P" H+ P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 z3 }2 v, X/ h' T: zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) s4 n! `+ P1 Y3 Y, V0 Z# eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* Z a; T6 ^. E% t
EDMA3_TRIG_MODE_EVENT);$ _9 c, s4 ^# [/ j& Q2 F: v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . d- w" k4 g# O$ N7 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 C% c: ~0 v4 r8 h( AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 r2 ^4 ]0 F0 x* G+ cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( Y4 u( K2 L" z* g5 t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ c( y$ T; m% C* U6 n) TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! g z: N4 E* ~% R: g: _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 o% |0 g, ~, W# D
} $ u4 |) U$ m6 Y) _: l3 l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 { Z8 ~2 F4 u t {& n# J
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