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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. I3 { {* P3 B% M; c- z( A7 F% u
input mcasp_ahclkx,
1 l7 ?# X7 R- u; V( v0 X yinput mcasp_aclkx,; v4 H, T) x1 ?+ j; v( ? u0 x- G: u
input axr0,
) c! |# y# x- v7 _+ K9 M' [! Z/ M- x& B a8 d8 ]' t
output mcasp_afsr,9 ?0 Y; y/ W9 n) D! N
output mcasp_ahclkr,; B/ ~' e, E1 X0 K( y
output mcasp_aclkr," R- l# u* M' w1 f7 X) P
output axr1,6 ?! ?: w! O" [* b- P
assign mcasp_afsr = mcasp_afsx;, d; t; S8 E' p7 c
assign mcasp_aclkr = mcasp_aclkx;
/ ^5 R* k- i- U; U5 |& Nassign mcasp_ahclkr = mcasp_ahclkx;
2 I: g/ A' w' n" f+ w1 A+ p2 ~% \! h `assign axr1 = axr0;
& g2 h& A. `( M
) H' Y6 r; K; B( \, w& q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 m; f" W% a1 E# }$ zstatic void McASPI2SConfigure(void), R0 [' u6 n/ n( R/ b, a9 f
{; ]6 v! [2 \% f' J6 G2 ?) X( @! y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 w5 R. \7 V% I: ?7 [1 }( KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ F# j8 g# }$ Q8 A. z) {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! }. Z" `$ g: K9 @# LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 ^3 `, D; f: N' c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ ]2 B' y6 e& p" A9 q
MCASP_RX_MODE_DMA);2 `2 K V% r1 l( Z; Z( C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) O( ?3 g6 ~" z- t, Y* Z0 fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 q* n. O+ `7 z7 y% @. BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 b( N9 s9 E( s2 V+ R! b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 { M8 m) k o! J+ w8 C0 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( p/ C' m/ e7 u3 y$ q. b @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 ~/ U3 z( }' @8 p( V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- _8 @, q) f& x+ t. H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. m8 o4 U+ \. m0 oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 O; Q* y2 n. }( W" Y/ z4 I4 Y a) t0x00, 0xFF); /* configure the clock for transmitter */
7 i$ M1 `6 \: Y w# g% ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: `: e, p# Q& L! g. u& w9 g- z) d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % R% Y; D( K# Z3 W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, P+ T' Q" b- n9 {
0x00, 0xFF);
: _2 F- @' W: |( E' V9 u, _! }8 e# [7 X, c9 \7 _
/* Enable synchronization of RX and TX sections */
: P& J" p% ~/ T2 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; E' Y: D0 t c w% ?2 EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( w0 d% H2 G7 {8 Z& N5 u' @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 q1 L* h1 w' i* m! }** Set the serializers, Currently only one serializer is set as+ r, t0 \9 T& f6 r* b4 L
** transmitter and one serializer as receiver.
$ v8 }$ K5 L" F# U) h0 q*/
7 x, S, D& {7 G: UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 g& N4 l' |. [, |3 ^8 t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, L/ G" ~$ l% o+ y9 T& v** Configure the McASP pins
0 }) R8 O% b, O0 p2 }** Input - Frame Sync, Clock and Serializer Rx4 g3 O5 I2 q. x9 t6 v/ o& u1 r
** Output - Serializer Tx is connected to the input of the codec
( T. I/ j! U: i+ `$ B- T*/( n/ s) P: G$ k% o8 y, X( r8 m% |- q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( O. D! U2 ]6 d0 e4 m; |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 O$ k3 l! Y) m! t2 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 W/ }1 C2 F4 c" K& A" J
| MCASP_PIN_ACLKX5 B+ {: }! |3 I6 W3 R" n
| MCASP_PIN_AHCLKX2 y" t, m3 ?8 T! s# K+ {7 ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) g8 }2 G5 q% _* o6 O7 cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ S6 }/ u1 i" K9 h| MCASP_TX_CLKFAIL 3 t4 F2 A' h% z* [& n- K
| MCASP_TX_SYNCERROR
. P+ L6 ~8 ]3 [7 L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 K5 `$ } g2 q" t6 K| MCASP_RX_CLKFAIL
6 Y- z2 n6 c2 ?4 I9 ~" J7 x8 c| MCASP_RX_SYNCERROR 8 C: R/ B* t9 \/ @2 ~( W3 b% j
| MCASP_RX_OVERRUN);$ S! A5 v& X( v" h& Y2 F2 J. a
} static void I2SDataTxRxActivate(void): o: J0 _- }' P% F- q3 b
{0 F6 E& S( ~7 a I+ R
/* Start the clocks */6 L6 c# F% y1 [: P. P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ ] D/ M" B" _: h5 l+ @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) p1 p' q, s+ G; `3 ^, N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 i2 q9 F3 i0 P o' f( T
EDMA3_TRIG_MODE_EVENT);
/ U4 I v( ~: B" UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
}3 |4 K, ?8 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ P; q* @4 D0 J8 b2 p4 ^! @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 ]5 C- u3 i4 D0 i) D( L( ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& |+ J4 B/ n% |$ `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ `/ }9 S4 w9 R0 w/ ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: H1 N: _- X' CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 c9 I( y( y0 ]2 w0 w+ T7 X}
# X2 C6 C* B3 y/ j+ f0 G3 G4 r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 S$ E) G, M8 h" K5 z* c
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