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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," a1 s3 L8 N3 }6 U- V8 R6 ^. }
input mcasp_ahclkx,
[; d& Q0 d6 b* g( u" Hinput mcasp_aclkx,% a& D% ~3 r4 g- i& l
input axr0,
( t$ B/ O! J# q" b# @0 `
$ _8 w3 z: ]: a2 K1 noutput mcasp_afsr,
) k& e! a& B6 G6 t$ N koutput mcasp_ahclkr,8 U1 [' e; p* C$ B$ [- g
output mcasp_aclkr,8 {! \6 h2 C4 `& b1 l
output axr1,* \( q% j. a2 y
assign mcasp_afsr = mcasp_afsx;
( m% j1 N# j8 L4 n8 r% h- s6 \& lassign mcasp_aclkr = mcasp_aclkx;, r5 Y0 ~, H+ S2 e9 j4 c
assign mcasp_ahclkr = mcasp_ahclkx;+ j+ X. k7 I7 `8 S
assign axr1 = axr0;
I0 ]9 u% O1 R0 C7 s. t
3 E% ~! [6 g3 s4 ~8 }6 C" u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: q6 C! Z/ S" Ystatic void McASPI2SConfigure(void)
! G% { T' O4 R{
4 L# u U* y; j( i& GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ x& G: Y9 u; D; @7 [+ Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 {1 V: c F& R5 ^& U. s3 L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# y* b$ K6 x2 a2 K! ?' t. K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 M! X, k, [; y( \7 l& U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* @2 `1 L7 l2 P5 w" }# FMCASP_RX_MODE_DMA); [/ r: K6 k2 Y* M) f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) ]. d K. m' {) j6 W( c. SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 F" p6 V+ G0 h) q8 h& AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' k) I5 y" L% c; k! J2 O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, K! b, A( R P1 X2 R: q1 j) \) n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# N+ Q% o2 N _9 }$ cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ ?% _2 Q+ p, X% Q) x2 ~8 B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- l/ V0 ~* G+ r9 CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % q8 _) F" J8 ]4 [7 o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; L$ F/ B. J; @0x00, 0xFF); /* configure the clock for transmitter */3 F8 Q: h( U: p% E. K* o, X$ w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 L K0 V2 ~8 n. R' k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 ?. _3 z: ]1 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ i n* M! |* R) `0x00, 0xFF);7 W% b( m' l2 D' j' d% N- R- H
% {7 D$ y9 l; W9 o
/* Enable synchronization of RX and TX sections */ " C8 o# z1 z& z3 `* i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 p3 q1 H7 [7 Q; T V4 }# P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 U2 m" I" O0 E" f+ Z* sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% y: ]7 M B# O** Set the serializers, Currently only one serializer is set as
9 Y" b; L7 e+ X+ z/ E, x** transmitter and one serializer as receiver.- T# D5 ?- h* N% `% s" S
*/
. O. q- H9 D' n8 c: qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! ]1 K/ Z1 Y* I# T: S5 WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* O3 T- u: `5 E% E: U3 r1 ?& M
** Configure the McASP pins
y z& I9 S5 k) r** Input - Frame Sync, Clock and Serializer Rx0 y, G* f$ q, \8 i" b! k
** Output - Serializer Tx is connected to the input of the codec
6 }# j3 I# c% P" J* L*/0 C# V; N& y+ y, q# f6 x3 ~0 g% \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ R7 h" X0 O2 ]+ ~$ i' _* x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) K# M8 K% z Z: U1 Y( l2 h( IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 i/ `! F$ c5 H* |0 F+ D| MCASP_PIN_ACLKX
. v3 Z* i# h* u7 d| MCASP_PIN_AHCLKX
# l% H2 ~- b# D: l2 ~- q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) r. b8 |6 n1 @& H) BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 I" H- d5 S9 } p
| MCASP_TX_CLKFAIL
7 h/ r% l/ o/ D4 P| MCASP_TX_SYNCERROR4 |( H9 b4 h2 s) g5 ]: I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* n: y7 i3 _# V| MCASP_RX_CLKFAIL7 z# r" u' p1 O6 E2 g6 @7 t# G
| MCASP_RX_SYNCERROR
+ [9 a, A5 i! I3 X% k| MCASP_RX_OVERRUN);
* ~0 A. O" w) ~: s} static void I2SDataTxRxActivate(void)
" T/ ?; \& k8 m/ t{! ]; F. A' K& @- x1 b' h% ]6 Y
/* Start the clocks */3 J& s3 m0 R: l2 a5 A( P' c! r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 q- t7 g) O$ i8 ^. C5 M; H/ V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 U; d4 Q0 ], ?& L6 J GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% c1 [; v0 x) h3 ]) P! DEDMA3_TRIG_MODE_EVENT);- L* F8 k4 P# w+ F0 g4 x& o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; {, |; }. v t4 q! Q$ U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- I! Q) W( b/ `5 Y8 B; RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' f( D- x( G* U- @/ [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- R7 S e4 V+ M; t/ E! S: {. d) g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% H2 M; q6 c7 P8 N' S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( X- P+ ?2 o2 D zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
w( [ y1 K4 b- A4 {" @4 \; p}
2 ^+ | K7 l' P5 E. q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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