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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 ?' S9 ^5 i, |* k; ^6 y& ` D
input mcasp_ahclkx,: L( j V9 t( K) q% V. x8 F
input mcasp_aclkx,6 X; \ B; h8 [1 c g
input axr0,
- o* i5 e1 D. ^$ z
. o7 r: d) r1 c# [output mcasp_afsr,- u2 c/ {( F4 Y$ b
output mcasp_ahclkr,
8 b: ~ v* E' F" c) L+ Eoutput mcasp_aclkr,
: Z$ k# ]9 h; s, poutput axr1,
3 G5 q, e6 h6 g: G# t7 j assign mcasp_afsr = mcasp_afsx;
9 j; i8 x' p0 { Jassign mcasp_aclkr = mcasp_aclkx;
& ~8 U3 t+ m- Bassign mcasp_ahclkr = mcasp_ahclkx;
/ L/ |. t+ h) d, o8 l! uassign axr1 = axr0; * w+ b( m" W7 ]" n' v+ E0 @
# A) X4 x7 @8 A! i6 @+ X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 d& ]; M! u* t; a9 F
static void McASPI2SConfigure(void)1 v/ j8 f' O. p& B$ Q' `
{
; M: k( m% m7 _2 @: iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- E- j$ a6 k3 E& {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ g% ~2 r. U* l6 [/ O9 J7 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 d* @$ n$ g4 J4 I8 S! m( I6 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ Z/ F, a p( P1 l; M) q+ f+ v0 s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: ~5 j7 B) I q" A2 `' T S' |7 G' ?MCASP_RX_MODE_DMA);4 p3 Z4 L; R0 t) B5 L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," D( A) t, [6 {6 j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& y7 `+ J' @9 _. Q2 ?6 C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 u, y3 t9 O9 y' A9 u$ [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" v; J# c$ M; ^, N$ D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, O3 d8 f; k9 h0 q) S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
x) x' D, E; _" O7 c( @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% n* t; h5 o5 Y8 K( k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - ?; ^/ D" M) M7 S3 S& s/ p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. Z3 I: w# @5 t. k# Y1 q# _0x00, 0xFF); /* configure the clock for transmitter */$ t2 ~. n) a, d; z! m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 H6 t8 G3 S/ g- ]; Q+ Y8 |" jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 z5 @7 q5 S' j& {7 O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 {; _8 p5 J! o t; g7 {$ H& ?0x00, 0xFF);. q7 f0 {: c, V( G
& r( [: n3 c4 j/* Enable synchronization of RX and TX sections */
( r5 R0 P. {7 a+ |3 ?0 d: k: aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- q6 F$ c4 s! Y) X% w- j$ Y% c' `2 \% C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 n1 T5 c3 I, r0 M) E" a6 b! F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 Y# g2 O3 L4 k9 _' u** Set the serializers, Currently only one serializer is set as
' k& N# T9 u, j. L+ C** transmitter and one serializer as receiver.( P* [% P- N6 J) v
*/9 I. ]0 K% A% Y; j! Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ V' b q8 V, U5 TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 @2 }9 F3 |- q3 U* }7 g, ]' ^2 G** Configure the McASP pins ; g7 Z( \$ _% I' E% `
** Input - Frame Sync, Clock and Serializer Rx
+ K& r' W# D, q, i- g& ?. B** Output - Serializer Tx is connected to the input of the codec $ o9 c# \ S! v
*/
) S0 h- \+ p, `4 d! xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 I. }# a! r" U! \ [# s$ s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. j; ?/ x. n5 q( ^0 Y; b, KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
b) u1 t; X+ n( N- n* C, u. K| MCASP_PIN_ACLKX
: w+ F% _, h7 E. C3 t8 s| MCASP_PIN_AHCLKX( G$ i6 U8 u" Q( v$ o; B j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- N; Y% ^& z" A6 s) ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
b6 @6 V+ D" v( L O Q| MCASP_TX_CLKFAIL : m" w+ |0 g. d( n" _
| MCASP_TX_SYNCERROR
7 s' l. X, h5 ?/ q Y4 z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ G4 E2 Z" A1 q' K' _. w* r1 D| MCASP_RX_CLKFAIL5 T% H! v* F- L
| MCASP_RX_SYNCERROR
# t4 a+ Y, |8 t0 W| MCASP_RX_OVERRUN);
( L3 I% O* p3 A0 [( _9 r$ M} static void I2SDataTxRxActivate(void)
6 Q: l, c! q3 a6 J6 @{
( c" W1 l4 l: E/* Start the clocks */
+ r; o1 S0 s6 z7 f+ S4 m0 PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ \( P. M" E/ Q* M3 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 e) \3 i2 E! x" x. \5 f0 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 k2 v8 z" a0 W0 dEDMA3_TRIG_MODE_EVENT);
: ~( { n4 V: p8 q5 r) oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ D; P* X8 T# ~0 @, x% i8 T' S; \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 C, M, _6 t- H7 U- _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" n9 \4 i ?% \0 w/ [0 S- M5 X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 e; N+ r: j2 C5 y3 b* ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 x: _: G T+ {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; |" o' W3 ^ KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- l$ j' f, n) n} $ M5 f. g# l' z% @4 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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