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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ m6 N F0 ?( q: f4 g
input mcasp_ahclkx,9 G' S* S- e7 x, h }
input mcasp_aclkx,# G7 `& z" d3 W5 {
input axr0,
4 T* a, o5 T$ S) q7 y% T8 P1 a- y o5 D+ ]& ~
output mcasp_afsr,
" ^* B, `3 x) ?3 H% C# Z! koutput mcasp_ahclkr,. f, x" g6 B4 {2 }7 S" P
output mcasp_aclkr,9 Y) T4 y" Y8 }' V8 @! Q" X1 D( i6 N
output axr1,/ }! J: f+ V+ P3 {# s2 g- b
assign mcasp_afsr = mcasp_afsx;) q6 `2 b( P7 c ?3 L
assign mcasp_aclkr = mcasp_aclkx;8 \/ Z; W3 [+ I( e9 O# \# J
assign mcasp_ahclkr = mcasp_ahclkx;2 y7 ^" `4 N% j4 y2 L# x6 ]
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . ^ g) ~7 X# y4 x9 H/ |6 m7 W$ D6 G
static void McASPI2SConfigure(void)1 m8 _1 Y" t( F: _
{: c0 u0 g. @% ~6 U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 U" t9 D% V$ r! F: \$ y. f/ b& h9 YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% I$ P6 S7 X! a0 D) v5 QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ H* D5 a7 p% V! M* u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( B0 p, R, O" g. W+ iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) T# M, {. | j7 {6 [3 [4 E
MCASP_RX_MODE_DMA);4 T: I7 |5 p. E, `0 ?8 j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, v- w# Q9 _5 d/ O }* F9 p# s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 U6 u: b, b! B A" Z7 k: f! F+ T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# o$ F8 F% q" YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 }! W8 U- ~! ^3 W2 q* mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; X$ R; K4 l2 R6 Z3 ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" s; g! b( b! I+ M- s4 b4 g! eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 Z& Q. a& t2 T! z( E) y- hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& _' D' j2 M& @ `' h& V% Z% GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* a& N7 k8 a# |# [0x00, 0xFF); /* configure the clock for transmitter */
& J$ {' b/ M! ]. H2 |6 QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 e, ?/ w+ s9 w8 R1 Y1 G9 [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! \7 ^) i' T f4 Z" ?6 V! G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 ~' o! `8 A; S; ]$ f* H0x00, 0xFF);
4 Q( u; B" Y0 V
) {) B" n2 Y5 C, v$ q4 Z2 W/* Enable synchronization of RX and TX sections */ 2 v/ A3 ^/ I7 Z% A: m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 J: s+ O* M5 A; d5 i( JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ [# G }6 z: d: m, L# B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 H! f7 I4 i0 ]' ^, u# Z" n# K** Set the serializers, Currently only one serializer is set as
; l( W2 T+ O8 m1 F1 m# o1 c; `1 x/ S** transmitter and one serializer as receiver." d+ X! H" l/ k9 R8 s9 a
*/" G5 N1 u) O6 k# Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 Z2 _$ k. |0 G3 x5 s7 y3 i/ mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. O. B {: ^9 c. F/ J+ z
** Configure the McASP pins 6 Z, x/ N/ H( `* y
** Input - Frame Sync, Clock and Serializer Rx
0 w/ l+ @. V& ~+ T. t8 s** Output - Serializer Tx is connected to the input of the codec
1 T t; p" b, E' v' W*/
# [% B O5 r5 _0 e- uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% i" R0 D: r& f( }4 R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) T, u/ v+ Y7 V5 D( T% AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ c2 |. _3 D/ `" S9 ]
| MCASP_PIN_ACLKX
8 e6 O/ y* y8 ~ ~, j3 m8 I( J| MCASP_PIN_AHCLKX% v; E; p4 X2 W$ v0 r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# P t3 u. C8 y/ a& ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 L: E7 d$ B/ s: v& o6 d5 }| MCASP_TX_CLKFAIL
' R2 x$ f9 E, `1 ~| MCASP_TX_SYNCERROR4 Y) ^( n+ x' K; H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 V# }* E1 _# I- C7 a+ M# F4 j| MCASP_RX_CLKFAIL' h! K" F# ^3 e8 A: r4 E9 T
| MCASP_RX_SYNCERROR
5 j/ n, z2 N! N8 D| MCASP_RX_OVERRUN);
# t, ]: S* @& X1 s5 d} static void I2SDataTxRxActivate(void)
$ j% m% T: A; l# E0 k{
* x, r8 G' y! z, G9 B) J5 i h/* Start the clocks */$ e4 k7 M; L2 P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 k) K r+ S0 P l% ]! r- b% fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% [# i6 [3 h6 k2 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 j* Y, [8 z' V; w
EDMA3_TRIG_MODE_EVENT);/ X# H/ q) W d" f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 a* P& Y; q' K1 |: R0 U7 vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 W: o6 O3 Z8 aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ d% H8 R- D7 d' I d! Y7 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 Y& c) F6 J+ s0 t; @# @+ d" r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 f0 l4 h3 N: z/ m- _, y* g: C6 |3 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% Z, a$ t. P/ _3 f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& K) q# j. Q& p}
9 J, s: H; {$ X D! y1 [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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