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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" c1 m0 |( q% ?7 Dinput mcasp_ahclkx, z0 n6 N4 h F
input mcasp_aclkx,; \. G" w- D) z u
input axr0,
' @9 k m& k [+ [$ w# V
R. T0 L: ` V7 v* youtput mcasp_afsr,+ J* _3 O8 ]4 P% B# M- e1 F4 ]
output mcasp_ahclkr,! q. A* O. a5 d4 r$ ^( E1 X
output mcasp_aclkr,/ n# L0 K8 x& B4 h4 i* |' }
output axr1,
2 o' {0 F% {5 i assign mcasp_afsr = mcasp_afsx;
' P) M: Y% J' h5 T, {) J8 `assign mcasp_aclkr = mcasp_aclkx;6 m" ^; b4 q* J9 Z
assign mcasp_ahclkr = mcasp_ahclkx;
& h5 V+ Y% z2 r. L2 S: l: G" @( ?assign axr1 = axr0; ! N9 e# z- C1 y6 s3 L
3 T3 c4 Z3 z8 a# X- I ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 G! T! e3 Y' Z/ w. m
static void McASPI2SConfigure(void)' r1 I1 ], `# m( G: _# y
{, j4 ~ g' n' T5 m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 N. ?' |5 _! h, }& l' ?8 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 r+ W2 D5 |, R1 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* n6 w' m( ]' X$ D4 A# PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, V6 o5 x x9 P# r; `4 E% a1 B/ }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 ^6 E$ U5 j2 p" t& o) \) P+ GMCASP_RX_MODE_DMA);" O8 r. c8 _* A, P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! X y- R& w' i$ T' h9 R, \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: b7 b& O: c, S" @5 r mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 x- e* b6 j0 ?/ [. y) p* gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" j6 `! x% r+ I( ~1 w6 N+ } i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* I- W/ W. `. t7 }, |" t+ RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; l! u6 ], X5 o" G8 S' }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 P1 S4 w' b! s# X( s# y% F0 SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- P" t4 i# J7 U CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, {' m1 w" H8 R- n% ^
0x00, 0xFF); /* configure the clock for transmitter */' f R: c X% t. N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! y; ~* ^' {$ i! o3 } N6 j7 mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 O! O/ z' x/ A$ p3 r0 YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% d/ p1 l) a6 Q8 ]7 K# b+ o
0x00, 0xFF);
6 U$ [' p g6 z8 g/ f, S! o: x1 A: N4 u' p/ ~! K* L
/* Enable synchronization of RX and TX sections */ & m$ [) `5 s) k9 U7 X8 Z7 c$ B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" i1 s3 k% c0 K3 V$ J. o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 y. a' c# E0 \+ u* WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: \* M0 z7 h' u, k** Set the serializers, Currently only one serializer is set as$ Y. Y9 r" E6 d% {9 ]8 u: W
** transmitter and one serializer as receiver.
& C5 [! I, O$ m- q, L*/
# q- t H/ ~* B1 EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 W% J! s7 R- W7 k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 ^4 C6 y$ n6 w O8 C
** Configure the McASP pins 7 F! F/ v e3 L3 I: ?5 ^
** Input - Frame Sync, Clock and Serializer Rx
% i/ b* h+ N; c0 n: g** Output - Serializer Tx is connected to the input of the codec , [( C3 ?) b# v
*/
6 r; w9 s* i0 K2 a9 t* ]8 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ G. ]" Y8 h: W% T. bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; U5 v" D+ M: W" {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ F7 l8 ?% c' l% H3 K| MCASP_PIN_ACLKX
# E' g; [0 c A Q1 |+ K+ G( {! k| MCASP_PIN_AHCLKX& \/ n4 ~* {, Z. S% z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 t4 K( X% m3 D4 q# g" sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- z6 B3 w% u' Z! C) [" s L| MCASP_TX_CLKFAIL
0 o; \4 S9 }! M| MCASP_TX_SYNCERROR- J! r5 `- A7 S+ R. N2 {1 k* C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ R4 V3 {& Y! m| MCASP_RX_CLKFAIL
9 P! h. G/ W" o) b N3 z| MCASP_RX_SYNCERROR
* f" d: n+ f9 ] |; V+ T| MCASP_RX_OVERRUN);: W) j$ u$ o" d* [& `" r
} static void I2SDataTxRxActivate(void)0 T, C! Q# u! J
{
9 `: A) f8 e" y& c% p) C; K/* Start the clocks */. L; W+ ?6 x3 s. |" a# \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% _. R5 ^' T. J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ E I3 _4 {. ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, f: F6 h% ~- ~0 i/ c; f
EDMA3_TRIG_MODE_EVENT);$ h" t' s. \2 h. |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) Q3 a# z' h* Z# Q' Y# NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" G" t; [% k( n: }' m6 y0 d7 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. M2 r3 Z( C- a. |! R- v9 `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) q( p$ ^+ [# f4 m1 ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 Y2 g" G: W' F" W8 B- j* Z$ K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 v; N+ U- x5 K: [* hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ C( Q- w0 o# y P7 i8 o3 I1 ~}
/ I M6 F ?, ^- |; y8 r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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