|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 o' c c8 ~" U" D6 I
input mcasp_ahclkx,
" J! n1 ?/ ^( U2 Z! w: binput mcasp_aclkx,
' |* F+ J8 ^' W" F( b2 v- winput axr0,
& o/ y. w- I5 @. _. }# M, x
3 n! n7 r# M( V) _output mcasp_afsr,
1 v$ h# Q7 t6 ~: {6 S' n) Goutput mcasp_ahclkr,
$ e% S4 m$ ?. Voutput mcasp_aclkr,9 F1 Z) ]$ D1 ^- u$ e/ s3 G' ~* Z
output axr1,$ W$ q! [6 I8 D
assign mcasp_afsr = mcasp_afsx;
: x$ p. e& t, M( {1 G6 Qassign mcasp_aclkr = mcasp_aclkx;! E. H6 ^# F: A
assign mcasp_ahclkr = mcasp_ahclkx;
% p2 e, ? `, r+ t7 X9 z& Vassign axr1 = axr0; - l. b% Y2 N% x( D1 U
, ~0 {: s, M2 w) A( `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( R3 Y4 `/ x- W3 s; ^6 G5 tstatic void McASPI2SConfigure(void)6 m) B6 `* C$ |! J$ c3 {! d6 N& R
{
/ r U: U0 f" [* X1 ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 s% \) F2 j m7 G6 ?$ r" p) s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 a v; Y4 G2 R* ]3 I, z$ [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 W* M, P; Y& ~) v3 _; GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 a! @- ~- \2 F9 y" i, p4 {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ |- {- k, ]' c% jMCASP_RX_MODE_DMA);$ }2 M' V) H' f) P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) `9 @7 K" h3 C" l8 V4 {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// {$ Y- C# J: \2 U! I! Z! _ p8 I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 |5 d0 p& |0 o- n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% _5 v Z% m: [( x6 t+ y, GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 {+ s8 ~. Z. T" O1 P4 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ J0 ?' s: V7 n" V! ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
`8 o- J; z0 y: s" B" G! Z/ @9 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . P' {/ B2 q4 Z% o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ k: H! Z) B! L* d, f0x00, 0xFF); /* configure the clock for transmitter */
4 |- K$ u# U8 I- j$ pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 H! t& X3 I9 v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- s, C4 C% |0 \4 @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( G% a. l6 M5 W# k1 e0x00, 0xFF);" M* g5 e% y' Y1 f
, I+ q8 m; {4 C) K9 |/* Enable synchronization of RX and TX sections */
. A6 l6 ?# J gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; ?3 F/ g2 M- S4 hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ o# U$ m# J" Y7 O7 Q- q7 b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 a1 p2 g) J- D( J3 }2 c2 Y** Set the serializers, Currently only one serializer is set as
- L( N; L I% U' g% S+ }! @1 G** transmitter and one serializer as receiver.( J" `& z: u2 d
*/) }5 L& ~6 m* v c! e) w5 A; x' Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 t8 R+ h4 @3 M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- M& q; ~ X: p2 N# V3 f** Configure the McASP pins
. }, j# l" G, h- s( e** Input - Frame Sync, Clock and Serializer Rx
' _! J$ K% \! H% w- H+ B** Output - Serializer Tx is connected to the input of the codec
; y$ p( _, _8 \" O; J: Z*/
: B9 y5 G) c& x7 k/ f& |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. [* I+ T2 y4 @6 i! H0 s, A: k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 r6 V% X+ v1 @# o9 C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; D; c Q3 B) q- w& H
| MCASP_PIN_ACLKX
3 O. f* n* R1 D6 `) _| MCASP_PIN_AHCLKX% X% j; r, f' f' L1 o( O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 @1 U. w5 j. Q4 p) aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 L/ t" m+ N- @+ m| MCASP_TX_CLKFAIL * s" R% \8 w; [( f- u4 C9 i# y* W
| MCASP_TX_SYNCERROR2 A/ X, {5 y% M' L6 k1 M1 C# V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 O5 E5 u; \! o: D: f' O9 \! N) ]& O- J| MCASP_RX_CLKFAIL1 _4 A! G2 W: x( x: e
| MCASP_RX_SYNCERROR 2 c- T7 I* z& k% u
| MCASP_RX_OVERRUN);# Y2 b8 M T0 G5 |
} static void I2SDataTxRxActivate(void), U, L9 b) B1 q3 V# m3 g1 K
{' d: G- m" ^4 j8 ?: |& s
/* Start the clocks */
0 I! ], D" \) H$ d5 uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& z9 ^7 a# p* h2 `. k' P( oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' `$ Z, A. v# J+ \* i2 ~% K; e1 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 B( x* p1 w7 p2 T/ j* IEDMA3_TRIG_MODE_EVENT);
8 o" _4 v% q2 E0 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # ?( V' `: m; f( u7 p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& `+ z i* y( D" v/ F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* m! J" M/ u* Q# e6 T" j; l4 j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% l- @& M6 {/ ~5 c2 I+ ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 t# T4 j; }, _* o& h# D4 k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
U' ]# l4 y! }* E& y# r$ B! CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; |) U( Q/ }; v, X V$ _
}
3 K3 U8 N% i! d. u& _, S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : _1 C& F; J+ b/ k G
|