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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ {! l9 _/ L! L! binput mcasp_ahclkx," ?. m4 |4 V4 \, W
input mcasp_aclkx,
, B' W% P( @ d& m# sinput axr0,
* g) N$ r3 K8 P8 Z4 z# ~5 _- @5 L
output mcasp_afsr,& h1 t, a) C; Y' |- @% a
output mcasp_ahclkr,
& i+ B J7 n* I1 f1 n" Youtput mcasp_aclkr,
% z, r- @2 P9 e2 s; Xoutput axr1,
+ U' v/ @2 e" | assign mcasp_afsr = mcasp_afsx;* d- q A; N1 [
assign mcasp_aclkr = mcasp_aclkx;
7 w+ m" d+ O. }' Kassign mcasp_ahclkr = mcasp_ahclkx;
+ h8 U' W, m" l# G6 h' Vassign axr1 = axr0; . S0 i Y/ U2 M! W, D$ T
6 X0 D0 o9 s, f3 b5 W6 \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* D2 J% p" k5 k M3 Y1 f5 p: tstatic void McASPI2SConfigure(void); v; J" s" y/ g Z) a i( Y4 n
{6 f1 q# J3 ~" j% ]( `1 A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ N: U: _5 ]0 I% `. t% W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- s% O- d" {9 k4 X# H/ A5 Q+ {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( M1 @. K% Y( t6 M; a" J" d) D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// ?$ Z9 D+ q3 @% A* S: A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* V, w' W) \ z: G/ @4 z1 [MCASP_RX_MODE_DMA);: ~2 F( K6 v7 Z* T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 N7 B9 N$ Q7 \7 d( oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( L2 x" p, W& S/ f+ r$ FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 T- ~% V8 s3 `6 y( T8 q |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 X4 v. m& b$ rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' {7 z- U5 a9 i' u# [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ `' h, I1 o mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: t+ c/ S S/ ~! H% U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 L: h! m6 X8 ?) T6 c4 J2 [- ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 M+ c$ {8 @6 h" R x0x00, 0xFF); /* configure the clock for transmitter */. D$ t) S4 f8 d. I5 o* N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 J) I) o, E/ R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 b3 J0 @9 p. ~% a% [3 B0 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! T; N' I0 x8 i$ u4 h* Z5 a& ]' ^9 u0x00, 0xFF);' s& m0 q' I) ~: D" u' w& _
+ v) h. {) ]6 E& T9 p! P6 g. F/* Enable synchronization of RX and TX sections */
' P' Y8 q$ ^5 w/ s- pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ i' ~; O8 m9 o/ N7 C4 f! \* l6 K+ h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ S Y% E. q T1 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, {- H5 i( r9 s** Set the serializers, Currently only one serializer is set as
* u6 O3 Y' [9 Z8 i& ]: k** transmitter and one serializer as receiver.
9 _1 V& w* h3 X* }- \*/7 X& d$ ?) T/ \* B7 Q! ~6 E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% A7 ^! W' f+ i9 W+ XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, g$ T; ?& U7 B' |1 k8 f** Configure the McASP pins
" E- ^. H' n" O+ J** Input - Frame Sync, Clock and Serializer Rx$ o* ?, k! x! c5 ]6 D) u5 X
** Output - Serializer Tx is connected to the input of the codec 4 n% j r4 S3 n8 H; l$ q9 |; F* o
*/
* `' h1 |% U1 T# WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( j+ T6 c! e2 O/ I5 ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( G2 Y' J2 h2 E+ {" p* L5 ]0 q& yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' S$ ?% _& ]$ F6 w( R
| MCASP_PIN_ACLKX4 K0 y# ~/ M$ H- S9 k' _7 h
| MCASP_PIN_AHCLKX" f( U1 i1 ]# |' l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; E- d q' J1 j6 P: X DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 t0 K. V9 j- ~' n
| MCASP_TX_CLKFAIL
/ f9 I4 s) g4 x- f% k9 R+ ]2 m! {% S) J| MCASP_TX_SYNCERROR
+ W! T: |: L+ d# a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % i: I3 Y/ n$ }
| MCASP_RX_CLKFAIL! Y8 }( a3 ?: K$ t. B) ^
| MCASP_RX_SYNCERROR % r' O0 u& y9 p" P6 _) @
| MCASP_RX_OVERRUN);" v: S! W- Y- {) g, L- v( D
} static void I2SDataTxRxActivate(void)
s9 r6 s* n5 X; W0 b' ?{- z/ D5 z! O6 C4 U# L# ^7 ?
/* Start the clocks */
' t# x9 g( ]( @. B# A0 iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' B, u6 g7 x- D" ]& w- P2 q3 H6 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# v9 m& j/ v: [% K. ~: Z, GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ M# S$ c( J3 V' Y4 d; i# aEDMA3_TRIG_MODE_EVENT);
1 J4 v: o/ Q( O! Q: A3 x4 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& A& g' r$ I5 TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ y N W: U% ^' sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 D' V* ~0 b. LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 a& H. Q# I" p7 i2 r, M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ P2 p' ]8 l7 U9 ~3 Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; a7 O+ p. I; z( |. V1 I7 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 E9 J H5 e2 w$ r+ I* u X0 ?
} : f( ~8 U& C( w: ~7 ~( ]9 m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : M. n9 U5 f) E5 H' q4 m+ e
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