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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 a. B$ C, ?+ d! F5 Pinput mcasp_ahclkx,( t3 u: j. K& l( |8 _2 [1 Q& U0 k q
input mcasp_aclkx,
' t' f! T, v; h- C. X& D2 oinput axr0,
* B( A5 e Y* y2 r9 g8 i5 b8 d$ N3 Y. Z0 f
output mcasp_afsr,5 `/ O. U. c9 v1 d
output mcasp_ahclkr,! D, w) w. A1 P3 @# R- G
output mcasp_aclkr,
3 B( R" E3 [+ C: f$ ?output axr1,
+ r1 P7 F' Q9 |$ R# G% l. `. x assign mcasp_afsr = mcasp_afsx;! W1 w" {0 a5 n( k
assign mcasp_aclkr = mcasp_aclkx;
, d! s/ v/ r) R( r! u+ n" X% \assign mcasp_ahclkr = mcasp_ahclkx;
; Y/ L. [+ Z9 O2 S7 q- iassign axr1 = axr0;
, o6 ~0 ~7 ^/ y( U/ \6 V5 E( t8 W' `. G6 e/ ]# \( z4 `3 x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 u- _5 i0 K, q
static void McASPI2SConfigure(void)5 t; J* b& n w. P% p
{
6 ~4 X# W8 U9 w" g3 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 X3 t3 G/ [& RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* a6 J% c D1 n" ]: qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ f$ q9 Y* l, q2 d" KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ V( M/ \; T* f0 {, iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: R3 ^: S7 e7 S# Z# k+ J- r3 l5 P ~
MCASP_RX_MODE_DMA);
: C7 j3 [! F$ i+ ]* g6 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, d: E5 d/ i# x1 H9 f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- v* W' X7 B: r; e: E) R( J3 H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; R6 l1 m) y0 b4 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; i' V) R- U( u+ [. u* M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& [/ S$ d1 N- V( MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ Q9 M) A2 |. m9 U. B" ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 g7 w) ]( c, [- Q( w" b. b, S DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" F+ |. g# c1 U: a! r# B+ @6 e8 z* ?% QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 w. T, z* K1 V9 ]0x00, 0xFF); /* configure the clock for transmitter */ L5 U* Y* E& p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* _; l5 c% N9 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; i5 E( o C7 E" K3 K8 \5 v4 l/ VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, I3 P5 V' }, R0 k) G9 F
0x00, 0xFF);2 g1 h. f, N) ^" B& r' v) u ?
+ L; O0 @) a v4 e H7 m. i
/* Enable synchronization of RX and TX sections */
7 {% z: l4 o3 ^4 l* YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; X; j: }" Q& L$ F! a8 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 m3 e, ^' h' @ s4 `6 G) T( q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" _! o( W, M4 F* A& h G# o1 m** Set the serializers, Currently only one serializer is set as8 g9 o* }/ p. t8 ~( _( D
** transmitter and one serializer as receiver.9 B0 U* j7 g$ @6 N0 |
*/
; B" r: K9 t, w ]! O8 @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); x( O3 w! R- }$ ^( @* S! ^1 i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: l B$ T* p& l$ r5 \" l) k p3 w/ f** Configure the McASP pins
% g* E5 Q, n! S% u% F: X# O** Input - Frame Sync, Clock and Serializer Rx4 E' B; @4 A% g& y7 ?
** Output - Serializer Tx is connected to the input of the codec
4 ~5 K" a5 z2 ~: T- a*/) Y2 k! A* }2 V5 J2 J# e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 e/ b7 { F8 SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' F9 B" k( @2 O+ }" M9 |, D2 @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 \! E9 M' A+ N" y4 I/ Z% m9 t
| MCASP_PIN_ACLKX" P, p. X! H" \
| MCASP_PIN_AHCLKX y: o* v* b7 B! L. V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ G& T; |# V, f9 f* k( v) m4 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 g5 e3 a+ ?- d2 U
| MCASP_TX_CLKFAIL
+ M$ t8 b# x) e; e| MCASP_TX_SYNCERROR7 Q( O2 ]& s6 I0 h9 Z4 i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 z' e a; n5 c' Q
| MCASP_RX_CLKFAIL
' A8 ^9 ~2 I6 _" G| MCASP_RX_SYNCERROR
) T( q E$ n* ^9 ?6 O. e| MCASP_RX_OVERRUN);! I7 d9 `6 I- ?0 |
} static void I2SDataTxRxActivate(void)4 x( N* Q2 X! y4 s, W/ g
{1 i% Q- }: `- g/ F# w" B( E8 l+ M
/* Start the clocks */! M; v0 `7 u, G B) h7 k; k% |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; G6 W4 l+ a6 a+ a& N0 OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" S. C1 t$ ^4 w- G2 T( n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ d+ [7 Y, t, ~) F
EDMA3_TRIG_MODE_EVENT);
4 C# C. Z! G9 I: n* [6 R8 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 \+ k+ K6 |: G1 P) g+ P `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: S N! F! K9 b$ D z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ | @1 A$ d; k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& u0 p4 I8 @6 b9 ?' |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" O) m+ ~( H/ a* }+ |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! \6 w3 T2 B5 [* g3 @1 A5 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# p; y& Z8 v" p7 k2 w# b; J, c: a}
' j% T$ ]6 h" K1 d0 |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 S# @! D, |+ ?; W9 {# k" D2 ^
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