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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ y& j; H& D9 T' l0 qinput mcasp_ahclkx,
# A) u/ Y! I% yinput mcasp_aclkx,
& Y/ P ~# T6 m5 Q! ?6 Sinput axr0,
. i8 w- l5 M; k& f6 L2 C2 Q+ ~ H+ {" m4 E. ]+ t
output mcasp_afsr,
* G4 e( g. R( k7 X( T3 \output mcasp_ahclkr,4 f! C3 d; V' }3 Z% p8 a
output mcasp_aclkr,; u3 [ {" h9 j5 t# [) v' T2 a
output axr1,3 I0 B9 X+ _& g1 X$ M
assign mcasp_afsr = mcasp_afsx;
" B1 o; M) R4 Nassign mcasp_aclkr = mcasp_aclkx;
# e7 v5 r* n# A3 `assign mcasp_ahclkr = mcasp_ahclkx;
0 W4 M. L( t+ }- i0 w( |assign axr1 = axr0;
* b) F/ e+ F9 Y: T
: K. g, l5 t3 c' S9 j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 W* P _# {6 l$ k/ cstatic void McASPI2SConfigure(void)
% B$ v' w+ n) s0 `/ X' i{
% t5 A! t# L9 W# Y6 I: H1 q. \4 uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 D0 m( K0 r; w7 a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 v5 h& _& T* P8 h# c9 v' E2 P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- }9 O6 _0 o j8 I2 n y4 A1 v5 k9 OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& B# u; X. o8 n$ `! |- q6 ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 w' T) {1 d9 C: ]MCASP_RX_MODE_DMA);! c2 T$ Q& F# V- p9 m! H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," I) Y* J4 _4 S/ J8 C4 q3 a# P0 T/ b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* r0 ~. {* D6 x) j* r. E! T ^8 M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 r3 B* v" k; s D( m) @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 i' E3 a! `( o4 |; ?) v8 b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + d) {, y. n1 L$ y9 _% o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 ?' Y, K- ~" u5 R( k# T" ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ X9 l/ K3 P! GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) {4 s8 B3 |+ u& j" I uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' {' ]! n3 K: D0x00, 0xFF); /* configure the clock for transmitter */, E/ b$ o- e8 b& v0 W+ x) H0 e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& i) T5 b( P, `! GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 x0 b& n G) s7 s# X8 g& DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ p' }$ |, f, d% I7 g
0x00, 0xFF);
" i9 @8 }9 n0 J) p
: }0 T* s( U" [/* Enable synchronization of RX and TX sections */
* ]' Y7 S+ V: V0 X3 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ n* s; u) r2 `: w0 E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); H5 ~! h+ H L- V8 n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 g% E& L2 A0 z. V3 N( w9 C1 f
** Set the serializers, Currently only one serializer is set as
$ T* Y7 l8 Z6 W" l0 G. c** transmitter and one serializer as receiver.+ i+ c$ N* r9 o& [6 l
*/
7 u$ e( k* W' }+ N, s/ n4 A2 JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; F6 a6 P! Y2 x9 n' S% _, n8 a- L7 kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** _4 H1 V9 C$ D
** Configure the McASP pins
2 h; C. W7 c M" h( O1 q** Input - Frame Sync, Clock and Serializer Rx
0 B% p U( g, c/ J4 I" N2 ]1 r** Output - Serializer Tx is connected to the input of the codec - e9 r+ N3 R. v& E8 @4 q
*/
8 o, H. X( Y. `; OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 p6 I0 e/ V- ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" G$ A% g8 y( ^+ v n) v. |6 | LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. c0 y" x& K g9 y| MCASP_PIN_ACLKX; N5 q6 @1 J+ y1 d7 J
| MCASP_PIN_AHCLKX; Y( a" c/ P) J2 D0 I( a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 k/ H" q% ? y# E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 }! O8 I( x6 j+ G| MCASP_TX_CLKFAIL . C2 j4 B5 j. d6 v6 c3 y2 K
| MCASP_TX_SYNCERROR
$ s B' T/ ]) g, A) x4 U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 G9 z+ p# Z( T| MCASP_RX_CLKFAIL
. b7 O. x: }0 L0 l; M L! E| MCASP_RX_SYNCERROR " G! {) H8 e' I2 @. ^, P* V
| MCASP_RX_OVERRUN);# R% }8 b# |1 V% x* ^3 G% D
} static void I2SDataTxRxActivate(void)
$ \5 v- d0 O4 ~! h7 m{' c' E( f, ~( W' H
/* Start the clocks */' @6 P4 \7 s: N3 b5 Z# `+ d" a; u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 ?8 q( V4 ^$ Z i/ v( p9 [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 a# Z( p, a$ ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ K2 |; z% w- Z( d8 T, DEDMA3_TRIG_MODE_EVENT);
- P( Q: M( {( J: t+ v: VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' p( A) ?# n* ~0 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% d" n. y7 L/ R9 t* i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 I) q! D+ Z, N) Q. x6 C% {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- D* z6 g# V* r0 k5 Z/ h& awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" _0 z5 B5 S" r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- W. p0 ~) a# _. X' Q+ u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 @7 C4 R. P L9 F- w}
* l: J, s, o9 |0 `! s9 m4 z% I; g" M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 p/ s9 e6 m2 r
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