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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* |) V6 q9 X( v: s- _input mcasp_ahclkx,- X' _3 K8 \8 X: U* ]
input mcasp_aclkx,
) n' V2 l5 v# ]+ _input axr0,2 Z1 U% b( r t' {
3 g' u. v( S. d7 houtput mcasp_afsr,
% c0 |( [5 l" Goutput mcasp_ahclkr,0 g. U- s' s7 ?* H
output mcasp_aclkr,
* T& l8 i+ }! c/ ^, j% M! i" boutput axr1,
6 _- _6 q" w8 g1 K9 `: P) o- h$ E assign mcasp_afsr = mcasp_afsx;- x( L0 _5 N6 ^, g# A5 s6 |, P- R- u
assign mcasp_aclkr = mcasp_aclkx;1 N; F. {1 }7 {: e9 c7 D
assign mcasp_ahclkr = mcasp_ahclkx;* J3 d& [7 x7 a" n
assign axr1 = axr0; 7 h% O2 K* K7 I' `8 C; e
# S, J( W: m' x* n( f9 |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! Y9 B% m) ~! U; s0 e
static void McASPI2SConfigure(void)
' ~6 k- X7 b3 ~1 g{5 L9 _6 K" n, K( p& H# }; w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& r" ^! d6 x, z p9 U6 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: {& l8 T" |4 U9 D) f: J& yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. b# _8 q; h o% HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" w2 `+ ?, B. D2 H2 r; k# ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& N/ j0 ]% l5 h/ S8 t/ ~: wMCASP_RX_MODE_DMA);4 v* W2 L! H) Y# n C: j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- ^2 R4 b* X) i' D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( C/ s+ q7 c3 P9 [! J8 V3 ^% I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% ~& I$ n7 i8 v3 }7 J2 K: WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- Q5 ? R2 t1 g7 }: x* O& s1 fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* Q/ G$ i7 ~7 i+ tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, J) X+ ~7 R$ l6 F4 P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ v6 I4 F; k4 z1 tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . B. I& v: r$ L) c0 Q5 F5 K- _! }. g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% T! m: A4 h% V2 F/ h. Y
0x00, 0xFF); /* configure the clock for transmitter */; K" z4 A3 h5 V7 H# |* u8 M7 O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 _7 S! I$ [# |8 @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, |$ W+ Z& s. A# r' `% hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; t2 }& u- B+ W' [: e0x00, 0xFF);
, _( O- X" X v& k, O) [ s& q: q( E- S/ G" y1 D% k2 J3 L
/* Enable synchronization of RX and TX sections */ 1 Y# k7 c u2 Q: c( i+ d( T. m, R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' T0 \, A6 Q7 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 J* U5 B: J' [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ ~% y: x- d3 o3 ^. I/ d3 F6 d** Set the serializers, Currently only one serializer is set as! ^9 I* q4 e0 G9 s2 M6 `$ w8 _3 |
** transmitter and one serializer as receiver.
( c+ P5 {3 ~3 A% F*/& p! s+ g$ A8 h& ]3 M* A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 Q5 z7 x$ x: u% CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ ~( S1 ?9 o( U; J% }** Configure the McASP pins . M( [) f; m, t$ ~# }% q) O# G5 a! H
** Input - Frame Sync, Clock and Serializer Rx, P' c# d- F/ @7 Q% q
** Output - Serializer Tx is connected to the input of the codec 6 H& v$ c8 y! _* j3 U5 J
*/ E$ w0 p6 p0 m- J) K. L, i& I0 e3 B- h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; r# {5 P. @) n: Y# T1 E8 ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 R* j, Q8 e' L8 w4 t, J- D# XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 C5 m( H: p) i: q! w
| MCASP_PIN_ACLKX5 y; {* V( I8 r( K4 L
| MCASP_PIN_AHCLKX" v3 S5 E* n1 j9 F. i% e8 C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, g; \. [9 p5 c( W7 H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- K/ [( M( }& u| MCASP_TX_CLKFAIL
) |9 g3 ?. g7 w7 e8 X. e| MCASP_TX_SYNCERROR
8 d( x2 P" I" Z/ }) z; X6 `9 T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 n }% x" D- S# I! O5 Y% T
| MCASP_RX_CLKFAIL' z# [( B- B/ u5 L
| MCASP_RX_SYNCERROR ) t9 ?5 |0 X( z% ^5 R' _2 W/ Z
| MCASP_RX_OVERRUN);% p. U; w- X1 k2 k" i6 i3 e
} static void I2SDataTxRxActivate(void)
' J7 C8 {2 Y& c4 I' O$ a' C{
# Z* d( t& O ]3 Z/ ]/* Start the clocks */
4 R2 ]# t* Q3 u7 J7 _7 T/ X, l, OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 I- e& a. s) g/ jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) L# D: g' @" y+ L, QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 J3 X* y) C. P9 {5 @: D4 F* h7 Q
EDMA3_TRIG_MODE_EVENT);
( Y( U, J: W9 L. ]8 D# uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % P! M, p5 f# X$ L6 `. {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 v: K+ a- h: R) d/ E5 \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); w* i' D: Z' o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 W* l4 g; b1 ~3 I7 w4 u* p+ |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: [3 ?$ b; v( K7 I4 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* y5 W2 n0 W& f: R4 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, p. J9 @1 I& q0 U @+ e
} % r4 N0 [7 W4 q# m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; O9 E' k& \: D
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