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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* y5 {, M) H5 B3 I! h) Q" x
input mcasp_ahclkx,
1 p6 Q1 L4 ^+ ]0 X) A* v b: Minput mcasp_aclkx,7 }0 H& C4 X) l
input axr0,. J* P3 O$ r: _: @+ h
* v1 C. c- i& t; ]- }0 u+ L
output mcasp_afsr,
, y4 {2 ?. c4 R" H4 u8 G; [' N2 Woutput mcasp_ahclkr,9 }7 a' I0 Z( S- }% {6 y) q
output mcasp_aclkr,
- r, {9 O. h- _" L* {. `output axr1,( e3 x9 y' t2 k4 r
assign mcasp_afsr = mcasp_afsx;
/ F& p' s2 g H) m- R' _' m- Wassign mcasp_aclkr = mcasp_aclkx;5 T% S3 ]. [/ t+ t2 q
assign mcasp_ahclkr = mcasp_ahclkx;' P5 b4 i, L3 H& [! t1 n2 H
assign axr1 = axr0; ; a: l+ V. ~+ E& g9 S8 V; J, {
0 n$ H5 J! {' R3 q3 `2 e+ k2 r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 E0 e5 i/ s: l# m) \) U: b
static void McASPI2SConfigure(void)
( h% R! Q& W6 f( G- q% E{
( X7 ?) M X( w V6 Y# _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( ^8 z6 K, I* b2 U# ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, r$ |$ z/ M5 R6 eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% `, w2 J$ @) g6 _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 b- e0 {. Y9 d pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% i6 v7 r) u2 f2 U3 Q7 |
MCASP_RX_MODE_DMA);
6 M( Z4 X, n6 ]* EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. o" [. u* \/ y+ Y3 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 p8 h! z: B% b, @2 R$ F: `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( I# ]3 O' V4 o1 _2 W# lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 ]' b5 y0 M. C2 O$ q, YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) _, F: @! Z/ _' {) o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# i6 j: o& g& M6 J. b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ r' z% _! c, i5 M% r. b6 _, _ K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 N3 P: q0 [ ?2 f( F7 E, I2 t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 |; [$ I3 C: c5 H& l
0x00, 0xFF); /* configure the clock for transmitter */9 | p0 F$ a' O( e8 X+ z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# x7 P' R* |1 |. nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! v- A0 X8 j4 C* [5 B- F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% {8 r; \/ ]8 k9 z! u0x00, 0xFF);
$ r# P" p6 A" r. K; W$ b( P8 N4 r+ H/ X0 } d F- |
/* Enable synchronization of RX and TX sections */
# R% f& S: }1 `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( _1 @% ~, H' A+ F" h0 ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; q& e2 g/ y: u: ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 A0 k) r% X$ @- D7 u- q
** Set the serializers, Currently only one serializer is set as
( N9 x' Y) j! P Z' B' c/ z3 _# b# ^/ W** transmitter and one serializer as receiver.1 G# w; r( Z" V: Z H
*/6 C9 V" |8 M) c/ [1 [6 u7 F/ d; u4 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" w& T. J R5 y1 x0 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 B4 }8 S( {; |$ s W4 y4 r1 C1 r3 F
** Configure the McASP pins
2 N- d7 }6 [) w9 }5 Y1 g3 f( X** Input - Frame Sync, Clock and Serializer Rx9 J+ y9 P# |0 n: m, U1 k) y. R5 S+ x
** Output - Serializer Tx is connected to the input of the codec $ H( O+ R1 W, w6 }! @, q: b
*/4 p* n2 `; j" O8 Y4 Z y+ U0 O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); A9 a h. N) C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 j A( m, t6 ?& M2 f- k- t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- ^ K1 _/ P. T8 D
| MCASP_PIN_ACLKX
[6 O. d5 ]7 Y, f4 W, G$ `| MCASP_PIN_AHCLKX, c( s& B# e5 @; V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
C+ e2 N5 n: Z& N: r, k$ @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * G9 m0 H9 ~. F: F c
| MCASP_TX_CLKFAIL & C# K4 v( a2 F$ E* J) g
| MCASP_TX_SYNCERROR
( m+ a9 v/ z9 \. P: B$ i. l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 r- @7 A0 W! l) p| MCASP_RX_CLKFAIL: c; J' V; i7 c0 l( E* r' m+ t! B
| MCASP_RX_SYNCERROR
' M0 l! a9 P' j/ Y' s0 \8 @8 w| MCASP_RX_OVERRUN);: L! t8 L6 @- x
} static void I2SDataTxRxActivate(void)
: Y2 i: \' F; P" q* M% T{
# [# B- \5 A* ~/* Start the clocks */
) b/ K$ P I5 ^' F# BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
l. T: B' W! R' L; m$ cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: ]. W& S, Q0 f" O, C) \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" d* t9 @7 V& r7 V& d4 q3 `EDMA3_TRIG_MODE_EVENT);
+ h4 p- f; y3 w, CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % K7 q) ?( [, b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# t a2 y! @$ P" a* H% E/ z e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 q1 ^ q1 E% @. W# HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 M5 B9 `$ {/ f4 m9 a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 ] Y5 f" C7 P! \" m/ A% P; m" b; JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' q4 Y$ |+ u. ^. n4 T# IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. V/ L; O1 p/ G0 D}
* P2 m0 `1 j& a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 _2 M3 y6 p* L; |( p
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