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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 q# W: W' o% s, M# E: p* i( ?
input mcasp_ahclkx,
m; \1 T& j. r- ?, a" k7 m+ D4 minput mcasp_aclkx,
0 H$ q$ q% m/ {/ e# {8 ]5 Zinput axr0,! d' p. U- h' i( L8 k, C8 V
: Y' \6 O- R- v% ~$ ^6 l2 o! R. y- v
output mcasp_afsr,) B# v* Q c% ~; u ?
output mcasp_ahclkr,8 t# `$ @+ N' P5 t7 d1 r
output mcasp_aclkr,
. D9 Q0 T1 r, I4 x- i2 J9 Toutput axr1,
5 i4 S; F0 c: D. v% G- t assign mcasp_afsr = mcasp_afsx;' \+ r5 H/ K* R5 ~& h3 o
assign mcasp_aclkr = mcasp_aclkx;
" X* n4 q5 W$ j8 a9 eassign mcasp_ahclkr = mcasp_ahclkx;
, t2 q+ y1 K/ }. F) V9 \- xassign axr1 = axr0;
/ ~+ y* X6 j, i) `: G. e: s
* {$ ?0 x3 H3 i; h9 J1 ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& o8 W5 x5 l- v; |static void McASPI2SConfigure(void)/ {/ ?+ V' J$ ?
{
/ L/ \% v x) j4 jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 I5 P3 T2 u3 T: @( T7 X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( D* C4 k7 ^* n& j3 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. [+ L+ {6 r9 s6 ^/ C. k; C7 X, u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ Z- B3 x% d q1 i* m: w6 }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% m' D* ~1 e4 Z% I
MCASP_RX_MODE_DMA);% r+ Z- _+ \/ s% o M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ _+ D, S+ J7 x! I0 Z. wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ E. _. ]+ i+ u" _: O( n) QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. o' Z& D- w& Z3 @( u/ m; g8 s! TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 ?' f4 L! I Z( {; NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; H/ A+ B0 o* Y" T/ i5 |7 s" R! ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 v* o/ [/ @5 JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. \) {" ]) s$ y2 y @# y: PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 e. x) `) L9 y2 v: K! |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
f6 L( Z' X& x( B0x00, 0xFF); /* configure the clock for transmitter */
9 j) Y6 v& G! a( S0 C5 [8 cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& p* k2 U& L P$ K, PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# Q: a3 a) a. }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' G1 X% K1 Z2 C+ s* a2 X4 ?( S
0x00, 0xFF);
, J2 G7 e9 g/ X* C# Q# }6 U, X
1 p; E9 _- c! X- X. y0 `/* Enable synchronization of RX and TX sections */ 5 Y% F7 k5 F2 y: X: y. p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ I0 I9 W4 `# `# b) \& XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 }/ j8 B2 Y! y) ]! LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' L( s+ q6 ^8 T ]1 t
** Set the serializers, Currently only one serializer is set as
- Y3 Z1 _0 }1 n8 w4 L5 O. I7 \** transmitter and one serializer as receiver.
. J) m& m2 `/ a1 F* z*/9 L' [* R. b/ \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 e( R; \# V3 Z1 xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% w, B( _$ y3 p# m* A+ V/ V% A' h
** Configure the McASP pins & g3 }5 w) d4 F! [ {3 V
** Input - Frame Sync, Clock and Serializer Rx
, E; p7 D7 z6 O8 t# E3 x, ~, n** Output - Serializer Tx is connected to the input of the codec
- ^7 b$ i8 d4 ^; A$ o+ ]% _& P*/2 U6 m: j: }4 R- R" G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! I- d7 H9 d0 k+ Y4 n3 [! x1 U% k! HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: C- [( o6 L, c) e8 B' FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ i. M# s$ K. k; O- i
| MCASP_PIN_ACLKX/ d- o9 P4 S) \: l
| MCASP_PIN_AHCLKX7 u4 u8 F* B1 R$ P& U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 f0 ~4 `/ d8 z9 [# TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! D& R- Q& b( Y/ X| MCASP_TX_CLKFAIL 8 J) M4 \" B8 g1 @1 L; x
| MCASP_TX_SYNCERROR8 B, U* s9 D$ U6 S, G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % l0 q9 ~5 t8 D- o
| MCASP_RX_CLKFAIL
- T" B& {) X; o| MCASP_RX_SYNCERROR
. q$ [$ W b. j' H" a/ F) r! Z| MCASP_RX_OVERRUN);
( c! N- I" M' C2 \5 L} static void I2SDataTxRxActivate(void)4 Y, y$ C5 o9 p" c+ X9 R
{
. v/ o/ H" {) X9 K. o' o/* Start the clocks */
( U7 |$ O! ], y9 ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: z- l! n: ]8 o; |9 o- R+ F7 I3 r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 G9 Q1 v& Z: z! L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 e9 @" P% Z) i- x. U2 TEDMA3_TRIG_MODE_EVENT);! [* t9 F5 X: \ O7 W' J& V3 S2 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 F# J1 S# m6 _1 m3 ?+ p: cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) s& n2 q1 `& O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 u% K8 R$ v5 B f+ T( L' d cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
d9 I; s: n6 j u2 swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ }) Y9 ?% T# J, r# R4 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, B6 P" Q) d# |) W7 [" L1 j4 w+ yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% Q% |! f9 y/ E3 |" i} - \0 e7 {2 S' P; K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * D. m# ?, a3 D, u3 g
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