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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* K6 P2 N H- [input mcasp_ahclkx,
& J) y$ m; P! v8 F8 V4 m( [+ i% Iinput mcasp_aclkx,
/ I- [6 m* a8 [3 A- Dinput axr0,7 v; b3 _ Z& m/ D
$ X3 Q) e7 r; x/ R- {output mcasp_afsr,3 ^ t7 E( Z# y @ ]
output mcasp_ahclkr,! Q) g6 \' d2 f( x7 `5 c7 k
output mcasp_aclkr,
$ |8 r7 g, b4 R" I1 X2 u+ noutput axr1,+ H: }2 e0 n2 ]9 u. }7 ]3 N; ~! S
assign mcasp_afsr = mcasp_afsx;% _* r9 y2 e( {
assign mcasp_aclkr = mcasp_aclkx;
" B( D5 X" Y7 {3 Eassign mcasp_ahclkr = mcasp_ahclkx;
1 `6 J% F n7 M9 a) [ P5 h6 w( Cassign axr1 = axr0; # @7 d1 Y/ | o! S
% Q, ], }& X s- ~+ t& t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. z$ c7 I/ C* o) E2 istatic void McASPI2SConfigure(void). }; }# e) c% }* }1 G$ y" {3 T. v
{0 N+ K0 w3 X! f: s- r8 n+ Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* O4 l& Y8 w) r1 o2 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 R* J ^3 }8 T; M% ?- g1 l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 }( ~4 g; z& M' X5 o: \* d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 J# ]& Z4 G5 T; a% M1 i3 f* DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- n! _4 i5 y1 q/ j" H) ]5 JMCASP_RX_MODE_DMA);" Z! ?% U' v! g; L) @8 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 W) J% Z* `) w+ w' c1 b' D$ \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- B% u# E9 J4 }4 s4 O7 I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 w" U; B N% o' e- q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); |' P. [+ ?, z2 Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) t3 X# q$ N6 G. H9 L- vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
o, Z4 i, x o X- PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ ?( ^8 B5 ]" r) T+ U' m0 a% HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 p" ]1 I- F3 z2 j9 u1 Q1 T1 tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* a1 D' r! g! [2 A2 ~0x00, 0xFF); /* configure the clock for transmitter */
) Q0 B7 I$ |( N( K+ r" MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ G" e4 |: A" N3 H; P, L' d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 }+ b2 N) k/ y. e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 b, t- n/ v ?, v0x00, 0xFF);$ p( ^; t5 H4 v, @2 g* d7 o
* ~7 t' N9 T3 }1 G
/* Enable synchronization of RX and TX sections */
" E% I! i* r3 g0 f1 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! _. \: M+ M: a0 m. @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 v3 G3 V% O' Z# l1 v" cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: G! L# r6 }. s* M* R g6 i) P1 ?% v** Set the serializers, Currently only one serializer is set as) G \ N2 s- d
** transmitter and one serializer as receiver.
3 C, x Y i0 l( h% Z*/7 K8 J) w% S3 Z8 ~& }# i5 N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 \% i8 L6 m. F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 {3 [7 }6 L/ E3 h0 |** Configure the McASP pins
- [0 d3 _7 g' g6 _( ~1 D$ |; D* o# G** Input - Frame Sync, Clock and Serializer Rx3 x1 d+ o |0 e4 _" Y2 t
** Output - Serializer Tx is connected to the input of the codec
0 h$ p0 ^+ `& ^! E/ h" }*/
4 R" u( H* ~! s! W" R! x' S; U! dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; v. N& d% z8 h# ]9 R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 ]4 L, f4 t6 N7 X+ t# ] a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- y# e" S" r! ?6 B B0 b' G| MCASP_PIN_ACLKX
0 `! H/ n5 w# c. S5 l| MCASP_PIN_AHCLKX
M* P( F! ~1 S, l e9 p# F, n; X m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 n0 Y/ [) H! h* l O8 U3 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 P1 [0 v/ Y ~
| MCASP_TX_CLKFAIL
: C* z; \/ a$ v5 U2 e: O1 r| MCASP_TX_SYNCERROR) w' n2 g) H/ L, x* l& L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" d" _. C& ^" \! e0 z4 \* A| MCASP_RX_CLKFAIL; V7 r3 G# Q1 h3 T
| MCASP_RX_SYNCERROR 3 s( \5 j$ l& k
| MCASP_RX_OVERRUN);
" I9 m) Q" [, M" L- A8 a7 [* M1 `# b} static void I2SDataTxRxActivate(void)
t% M7 u( j( z' a{
6 W% d! k' Q7 f+ j7 y9 H/* Start the clocks */
4 c6 \5 @' h- aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: x, Z5 f6 d2 P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// s* j6 S4 i! \( B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 {1 k: F: s" [EDMA3_TRIG_MODE_EVENT);
' g) x) F; V8 a/ iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 R4 s( ?* F' F, t4 |" p0 i: g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( ^2 t5 n& n' x8 U! k2 Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" s/ |# K" H5 G3 ^; U0 w N7 P4 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( q; \4 v5 q: S" O, g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* a x; l: q' V! P2 e) i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 T# K9 D' z. I0 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: R- G9 S& E- q q' W* T}
- Y- ?+ X' l8 s. F: L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - M. e# S6 e1 j1 r
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