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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, @ B5 {3 e1 D! p
input mcasp_ahclkx,
: J- T z5 m7 d# c T+ P/ V+ Einput mcasp_aclkx,- H! W; U" w* Y0 t/ \ z
input axr0,
" J. Y% L; m: H, p# Z/ B( d2 b' x* W- k) t2 V
output mcasp_afsr,, i" H8 t) m4 O: o* I
output mcasp_ahclkr,' D; W' z$ j. Z/ h+ r
output mcasp_aclkr," z4 R3 o( i7 x H9 I+ w3 G
output axr1,
( v; o7 V) g8 J/ a assign mcasp_afsr = mcasp_afsx;6 H) U% O3 ] b j6 k- Z1 ^5 r
assign mcasp_aclkr = mcasp_aclkx;6 A0 p) a/ L6 S6 n. b! U
assign mcasp_ahclkr = mcasp_ahclkx;% P& Y# z/ Z z* ~/ G" e+ c1 n, x
assign axr1 = axr0;
* b! B7 p5 a( G
% _: Y$ m, N* `9 d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 ~/ u# @9 i) E* B
static void McASPI2SConfigure(void)
& n' y8 M' f# {& u6 O8 ?) _{
$ M! b+ e& I, ~ [' b1 @McASPRxReset(SOC_MCASP_0_CTRL_REGS);% Y: _) k0 ^: B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 P) R+ D( f6 U9 @1 u' F9 r% g5 |; m) CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; M6 p, l" \+ o: A/ rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 ^3 k! H0 @$ F9 H( [& E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! R4 R$ m* }: M, U7 U5 M( {+ {1 c) ?
MCASP_RX_MODE_DMA);: K l4 g P l( F8 O# m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 i( q+ l. v9 l" g* T1 r0 v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 ]- X, W$ j; S5 i+ m* RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; s( Q G& R' q' p* ], {9 x: W% F% O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! {/ F6 z/ ]9 a7 Z5 {* V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ l9 b7 D4 E6 XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 l' c8 h& g6 T/ B7 q/ s4 `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 a; p% x! B* P- H' ]) P% C" ]2 T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( A% p/ F0 z4 b# ]) N' S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 Y1 ^' Q6 {- l( P
0x00, 0xFF); /* configure the clock for transmitter */
7 x, l7 y' {0 ~! h+ S8 G: TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. w* h5 u5 Q7 |8 k& S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 L ?* n1 r2 @9 U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 W7 z* i8 { Z# ] `0 U
0x00, 0xFF);
: a" U- a% U. P+ d" ]
9 [+ J2 ?; |" Q4 h. z, g' G2 o. F/* Enable synchronization of RX and TX sections */ 7 z: P! w* @2 y; T" U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( Q# Q! x* U/ Z* P- @3 y7 q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, |) I: J- X2 S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 `# r7 z: r A. Y6 k** Set the serializers, Currently only one serializer is set as X8 T4 B/ X' s) E3 K+ F/ W
** transmitter and one serializer as receiver./ }6 O% [1 V# P2 i4 L( j& L$ o# B8 }
*/3 }+ a0 C# E2 j5 k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# H, s9 s0 o6 ?) wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ R- h7 w( b; @2 R** Configure the McASP pins
- s7 {! H# R" S% U** Input - Frame Sync, Clock and Serializer Rx; X+ t* u2 g2 }. Z( o) w& K
** Output - Serializer Tx is connected to the input of the codec
. f: s& M% P: @2 @/ |$ _$ W8 m7 j& P*/
; \: z8 \* u9 f+ r, n. [ E) V* oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! I' S8 u. t N# C, T) y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, W, M* E, {3 I8 r2 F! k& i/ e6 @7 f7 t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& w. @7 G; z) H( ]9 }' g| MCASP_PIN_ACLKX
; A% i# l( H. E7 a0 [# b, I/ Q| MCASP_PIN_AHCLKX6 U9 z. Y: p- G) K& @- d4 U- m. o1 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 p+ u) u+ ]% ?8 \5 lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 X: Q* O% ?# m2 U
| MCASP_TX_CLKFAIL # T7 N& q- `+ R5 j% l
| MCASP_TX_SYNCERROR1 p5 S: i# T! X+ m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . K4 v: }0 l( d
| MCASP_RX_CLKFAIL' V7 e' g$ T+ q3 t, ?
| MCASP_RX_SYNCERROR
Q" b v$ Y! J; n/ T| MCASP_RX_OVERRUN);
9 d, C7 g9 |+ j* t. y} static void I2SDataTxRxActivate(void)1 g, v& ~9 E8 M' A$ S- t! X
{6 l1 ~; X$ E# Y7 Z2 v
/* Start the clocks */" e/ N+ N! V) \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ {% X& q% @/ K* uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: n; l4 X1 |+ W. U) DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 u0 a+ [0 Q$ {/ [, i; _) w, w) PEDMA3_TRIG_MODE_EVENT);. g4 }9 [0 E6 p/ z# Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, n5 s: Q. P- _+ @0 w. {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: L: e" Z+ p5 L! @- ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& F3 P9 q. g1 ^$ n( Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: r- {5 L8 @! n1 T5 a/ I2 {# b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ N' M2 T( E8 n4 Z* |4 PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 b2 \& l7 q: i1 N; {2 x9 H. VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: v; n) B+ h$ L: N3 Q `) _0 U6 P
}
, a" S4 z9 D3 }( o) T" G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 l# ~5 ?% f3 B$ g
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