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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 \2 D0 e5 l$ B# _ M% c5 B* ^" ?8 vinput mcasp_ahclkx,
% w( X8 U* {' d; f! l. I/ l" ^0 tinput mcasp_aclkx,: j- z7 B- F/ {$ v
input axr0,
6 _5 O& c* f5 R1 v
0 Z# k$ P2 w2 d6 O& p( _output mcasp_afsr,
; r, d, `& g0 \7 G. C$ Aoutput mcasp_ahclkr,
# {$ t4 c: U t3 \& U% [/ _- ^output mcasp_aclkr,
; G. S2 ?" }' }7 E" p7 {; Coutput axr1,
) S8 t( p( i3 s$ ^7 P0 [' g assign mcasp_afsr = mcasp_afsx; b, A: }) M: U1 z# E( m' H/ `: x
assign mcasp_aclkr = mcasp_aclkx;
" A/ L' K* f) V% I7 W) Bassign mcasp_ahclkr = mcasp_ahclkx;* ?" E+ N3 ]1 M3 n$ ^ X5 B6 H5 ?
assign axr1 = axr0; " F4 u. G; s q6 s/ ]# Z' J8 e
) a+ C4 u- o H: L p5 X, F2 S$ h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 k g0 X: Y" |8 H
static void McASPI2SConfigure(void)
E' k' |* c- _' b1 E; X{
! ~" N; E/ r% LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" L$ y* x9 g7 @2 Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% B2 |( A6 }- d+ \$ ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: @! L+ t, ?" l# f& S# [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 | t( X- N% r5 H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; T' s! e2 t' Y8 k8 X/ P4 v' d5 d
MCASP_RX_MODE_DMA);
$ j' n* d8 L5 Y7 X9 N7 u, H* JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 w& U5 `! l; |% \( @* H4 @" G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 x# R4 k+ Y7 S4 m7 o0 M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' e! j" Q a: ^, D5 t' c: R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* r3 p. m3 _! N9 c4 c6 N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 M4 n6 S8 a8 H( g: g! ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 t# P3 S( j; R9 @/ w+ r& |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* }( }/ s( f0 f* M+ Y, ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # v7 \& O6 d1 [) U9 X( ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, {8 [: b( O+ s
0x00, 0xFF); /* configure the clock for transmitter */
; F! x+ G( N& @5 x" k+ w6 SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ Y* X, V+ f1 U& \* Z1 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( D7 S; |' k& _$ n/ a) vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* r5 |4 [. E: @8 n; d0x00, 0xFF);
/ S, t* \2 u+ q H; q6 E0 `- v* b" d) Y7 S
/* Enable synchronization of RX and TX sections */ O, v4 Z3 S t" y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& O/ ?# e1 ?# n& s" H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" x! x, P$ a( ~( \* D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. @: f% Y% j: I( @
** Set the serializers, Currently only one serializer is set as7 ~( K* M+ M0 \; Y u) V U
** transmitter and one serializer as receiver.
1 m# {" `6 n% s*/
- H( ]) v$ l5 u& VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; T2 t2 ?: k# n0 ^1 M. ?0 z3 |+ }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ L" @9 O5 g4 z3 [5 Z8 ~
** Configure the McASP pins 7 ~* Y9 P. n3 |9 C2 t
** Input - Frame Sync, Clock and Serializer Rx
' V# W, s! h4 e9 v** Output - Serializer Tx is connected to the input of the codec
8 n$ {6 k; T: K; m5 ~7 U; E0 T' G*/# m. J5 ]7 C) A( ]5 c" B, L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 V# }/ H- F+ y( ~5 S, P" S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* K" I0 |9 R$ V- @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 v1 k' ?/ L2 y) \6 x
| MCASP_PIN_ACLKX
. n& ~& Q+ Q9 h% y' w9 M6 S' `| MCASP_PIN_AHCLKX
7 y& W# z! ?: u% \) a1 P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& l" M) _0 c' |. m0 ?" U* I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 I6 B) z1 c+ ~1 L( U! z- L$ d| MCASP_TX_CLKFAIL 2 v+ ?+ l# B6 T7 X
| MCASP_TX_SYNCERROR
0 C2 v5 v, D* k1 l5 \2 @4 S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; W) Q7 u v) s) R' K| MCASP_RX_CLKFAIL
8 y1 k- t4 ]* a( R. s5 v| MCASP_RX_SYNCERROR
/ j h3 S2 X2 C| MCASP_RX_OVERRUN);
9 M. y/ G. q! F! U `: F* v} static void I2SDataTxRxActivate(void)3 |% }' o A. [! s+ s3 B0 G
{
$ ~! g0 c$ W3 T! Y% Y+ L# o/* Start the clocks */% ?% `% R5 l* g* L7 v5 k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ M% P6 f& f3 T, d& HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 `6 j' ~$ c; J: y" Z# P. Y6 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* B6 @6 y5 R A$ V# W/ i4 CEDMA3_TRIG_MODE_EVENT);
4 r0 F* J; e' sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& S) d+ N* t' l. s/ {9 H) J, BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 B, M x* S5 U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. v# K* V" z8 S& W! O8 J/ JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 D- i; v* C- F# Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 \. ?5 }6 @0 D8 @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# Z/ p) e' h. k+ I, }+ v+ e) wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 i6 Z" W. V* I7 F& ?
}
& f P# F* w- h" h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 ]( l2 B9 w. p
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