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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( l9 |. ?0 G" c$ B7 e- }
input mcasp_ahclkx,1 b( y/ {8 j$ m! R0 r: G
input mcasp_aclkx,
. B# K( Y2 i- Dinput axr0,1 z- `8 c( `0 I" i# X( p$ n& \7 i/ I
; k: l) I* z( Z' g* E3 L- N" \& Boutput mcasp_afsr,
4 k/ j. p# f6 x$ ]output mcasp_ahclkr, o/ k7 u9 x9 p- Q4 F0 Z
output mcasp_aclkr,
& s7 V) H3 g0 x- ioutput axr1,
+ C4 B! C7 e' s assign mcasp_afsr = mcasp_afsx;5 m2 O( R" d( ~
assign mcasp_aclkr = mcasp_aclkx;
' R. g$ a* @* o1 dassign mcasp_ahclkr = mcasp_ahclkx;' k/ V; h- X, ]) Y/ g7 v& w; H
assign axr1 = axr0; # G& E h. `1 \' |. W/ E( `8 M
1 m: i2 m$ z' U3 ^: I$ {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 A# P; ]' w, U" N' n. n. D$ }9 ~
static void McASPI2SConfigure(void)" L& R# j9 K$ Z7 C" M
{
1 Z$ ^* h' u& r" R, a z# _ \8 RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& u5 f' O. i9 ~+ W6 c& c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// S) Q; i! m( U& R4 `" Q' J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" D* f& W' ?. x |$ y3 ?! ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 l& ~+ R" v5 B7 K |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. t7 z7 K3 Y2 e. B z2 _, _5 }. L; cMCASP_RX_MODE_DMA);7 E* I5 d3 J' i# {6 E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% Q/ V: \1 M4 @% L; \$ m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 n# L; R W% r+ o. fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 O* p. c E- @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# Y% c. ]8 W. C! Z! m( U. I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 t O: E9 n& K. G" z/ zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, E0 [, f+ Z5 {/ H; ^/ M9 }3 m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 i4 V. Y0 ]& LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* P% D* g& _( _ Y9 R; F2 NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
i6 @ R* L9 ^* a; E0x00, 0xFF); /* configure the clock for transmitter */ X* \4 D) p8 X5 g; r1 G) h; Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ t. Z4 G, L7 q6 \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 l! ^4 B \) Y& C0 n" p% h% P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 {/ q' c+ ]' r+ i" _0 O! j; G
0x00, 0xFF);. A) I$ p+ \3 ]% Q0 ~
) s4 O( z' j- R! t. p
/* Enable synchronization of RX and TX sections */ 6 z; y2 Y4 W; v* f. _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ |; f' @$ _4 f ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; x/ V C) i9 G" ~3 W" xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* {' Q. `: \3 O2 ?* D
** Set the serializers, Currently only one serializer is set as/ p. P) E- j& L' n3 k
** transmitter and one serializer as receiver. A. K1 S6 ~: F6 U/ J
*/
: R" O/ T& d3 d9 \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
U* t, |4 a9 B1 ~& z( K/ bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- N) F( d5 X8 O% ]
** Configure the McASP pins + c! `1 t8 E$ E) s8 C& c" G+ _
** Input - Frame Sync, Clock and Serializer Rx1 w( P1 d0 x. G8 Q& t, I+ D% W
** Output - Serializer Tx is connected to the input of the codec
. \2 S0 j9 b$ m/ N) s*/( v4 `; _: T2 L2 u8 ?0 |6 ^, R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 T" p5 N2 J) l! L8 d& t. u3 q* YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& a, @. J1 A8 Q& W" y& G: W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( O% ]8 v& E4 J( N7 M# w4 o* L
| MCASP_PIN_ACLKX2 Y# l( b9 a/ ?! F
| MCASP_PIN_AHCLKX
* O% e( q; P8 i# |& \8 B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 c& s- _5 ^5 E6 ~4 B' _: ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, k: l/ K4 E; e2 U0 Y| MCASP_TX_CLKFAIL
! P1 \- I- `; V) u4 }4 s| MCASP_TX_SYNCERROR' e% @5 b+ E5 j; @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ F' `3 |5 A: u
| MCASP_RX_CLKFAIL& y- l l( h' s; r1 \* v m
| MCASP_RX_SYNCERROR
: R* [9 p" c5 n* J| MCASP_RX_OVERRUN);
$ a' y8 o3 D8 z6 O4 T3 _} static void I2SDataTxRxActivate(void)
) H$ Q7 E" P4 y2 b' Z/ e2 e9 C- a$ H{2 M7 ^, I5 a1 ^" u, _7 I
/* Start the clocks *// Z* J& |$ M+ y& q2 R% i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 }6 G& \) Q7 m$ x8 o. A" H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' d3 q) f2 J3 k9 [7 B [8 m. n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' A) R3 m! q( h6 o7 o; x, C- nEDMA3_TRIG_MODE_EVENT);$ F* U) {* t! U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) v% q' m( {3 i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* [- u8 e* l' W/ Q# A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 r$ ]" ^9 X$ [2 E; \! bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 x% {# [- v$ M- D: ?0 j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 y2 s, M1 v6 }3 fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, b& w/ b4 @) S$ z2 g$ {2 GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 x7 H$ T' ~* v8 V% y
}
$ j1 a6 ]2 ^( }' U9 j0 p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / Y% }0 Y* G7 m0 w
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