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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ ~/ } y* a B4 E, V( Y B+ sinput mcasp_ahclkx,
% y$ k- ^, c- E2 E A; \input mcasp_aclkx,# `6 r! U z+ D& s
input axr0,+ H0 F4 T! _/ z) O$ B3 u, M
6 W1 \6 Y, c6 `1 r1 I5 _$ Soutput mcasp_afsr,5 q6 y& d( W* h9 l; |0 T+ i
output mcasp_ahclkr,- }$ c$ s6 D* H! ~0 f. }
output mcasp_aclkr,
, Y# Z0 a9 ~+ A2 B2 {output axr1,, o, f: T1 j$ W( I
assign mcasp_afsr = mcasp_afsx;- G! h# }- R. T$ M, V
assign mcasp_aclkr = mcasp_aclkx;6 p/ ]7 D3 H2 o" y" `
assign mcasp_ahclkr = mcasp_ahclkx;
$ F6 m6 d& T& z2 hassign axr1 = axr0; 7 e M6 i0 g, P, s
& a! h6 J5 n2 _/ ]* ?7 B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' H2 K& n- b5 N% Q/ ]static void McASPI2SConfigure(void)
, i1 q" S, B5 ^( k( Y$ ^{% ^) U$ O4 J2 N( E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- i1 I+ r! S+ r0 q1 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& l5 {2 |3 G' }, y2 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" f% b& e+ q2 X7 c6 ^6 [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 M( Q1 M" Z# ~6 s3 x1 n' O6 ?+ t$ G7 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 p' l' |1 _. y6 D0 {- b. f3 C
MCASP_RX_MODE_DMA);
. X( g2 N1 S% i0 F1 _( h6 hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& d2 z6 }5 G/ N( x) d' tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, l6 ^* Z5 U5 ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, t' e; Z4 [. y$ M+ L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; x! H' E: Y, A7 [7 ?1 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 z5 D9 [; t$ B3 H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" k) G) g3 ]' ~; ^4 aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 j6 p. P0 n5 i9 q7 K; qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " t; f' ^7 i( T/ Q( ~6 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& B$ h0 {8 L$ _+ c1 Z
0x00, 0xFF); /* configure the clock for transmitter */8 p$ E, |6 B7 c1 ? V. M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. M: |: Z. f+ `4 i% rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 {2 T: M$ w/ E+ J) T* {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, w8 `5 n& W, ]# [8 ^; w7 p7 {
0x00, 0xFF);$ s7 m5 y8 P1 u2 I. H2 J. D/ e/ T |
6 ?+ V; |. S* e3 }" Q8 Z/* Enable synchronization of RX and TX sections */ 1 a( E( ~7 u1 T, W- G6 ^0 X( ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 F$ i7 ]7 [* X( j; v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ e+ F; y2 m% @! C* M6 b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; j! d" O# A: K; o** Set the serializers, Currently only one serializer is set as
2 S( Z: \1 G" @7 D% k** transmitter and one serializer as receiver.
! h5 T: z# p" [9 T( g" o/ a2 W*/- V. t8 S' L) \! U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ d5 M! @' P2 z. U( n/ O3 N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& r+ ~. F. R! {" G" o( W. O$ E
** Configure the McASP pins
J/ W- x5 O1 i1 u# h* g** Input - Frame Sync, Clock and Serializer Rx
6 X7 \7 ?# `/ Q2 X! S& z** Output - Serializer Tx is connected to the input of the codec " I) Z& b" {. m. g5 {8 C& M
*/
2 u! r" v, U2 M# A& Z" L8 }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- k4 Z7 O1 {; T4 ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, ~ P# l" i! Y+ @+ c0 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# z5 r( x. F- g' v2 l X| MCASP_PIN_ACLKX3 \' _' u; r3 N
| MCASP_PIN_AHCLKX% E0 V- f& O U% U' A4 R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" x4 E; o/ ]/ k7 `" g: R1 DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 A; J$ M& c) w1 u B. v| MCASP_TX_CLKFAIL
( y T1 j$ G% u# A| MCASP_TX_SYNCERROR
# I6 ~0 Q8 |& R9 }( @8 A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# p3 h( E8 I: i0 ]| MCASP_RX_CLKFAIL
) f' x0 c$ z! Z* {| MCASP_RX_SYNCERROR
2 b) a" [# B* `5 P| MCASP_RX_OVERRUN);, v/ ^! k# K/ m- o% k \
} static void I2SDataTxRxActivate(void)
. P5 \/ M9 m. n. U8 K7 R- [9 ]{
9 H3 c4 E6 _, d* @3 R/* Start the clocks */7 `8 n7 U& X' U! F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 [4 h. V) `5 ?# S5 o6 H& s( nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# L# v' o+ ]2 _7 r4 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 ^! j4 Z& o" b% }5 Z2 nEDMA3_TRIG_MODE_EVENT);
: Q8 L; j4 u- o5 h" OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ d9 ]. ^0 {% J" E+ A0 e, ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 A4 |1 X! e) }( j' m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 ]" i% R: E: z9 i8 m0 IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 [& F6 Z+ q9 ]8 j1 N# o) a& ]! |( }/ O- owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 s; M3 `2 S: k$ M- uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) O/ Q( ~+ `. v$ ]2 g( }0 E4 @7 J' P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 e4 R$ @# N$ x. U3 ~- F% d
}
# j6 b: z8 f* l3 L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 T# c; j* [! _8 b6 A- E
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