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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
m0 J3 u, x6 o/ |9 `input mcasp_ahclkx,: N8 {2 ^& J8 p U
input mcasp_aclkx,
/ |) w5 L8 ]0 K$ v6 o; Rinput axr0,
! F8 m% U: u2 `8 w; H7 h* S8 q: `$ j$ F% {5 F: A
output mcasp_afsr,# I! A' A1 V- z) k Y
output mcasp_ahclkr, }1 Q& O& r1 K1 t
output mcasp_aclkr,
6 g4 ^2 F& g" c+ youtput axr1,
$ K% A' K- ?7 L0 d! i* z5 d4 y assign mcasp_afsr = mcasp_afsx;
/ B8 [) H4 m" Q" e5 massign mcasp_aclkr = mcasp_aclkx;
& s9 `1 t' r' d+ z9 ?6 Passign mcasp_ahclkr = mcasp_ahclkx;1 V; }& G% b" h' R3 ^
assign axr1 = axr0;
) z6 j+ R8 j) Z$ i4 ]7 U
p9 `- L, o2 |* C8 `# n# G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 i5 d$ x' w& @# O( L
static void McASPI2SConfigure(void)
, h* V( p1 @5 S: ~{, v1 Z7 @4 w5 o( F2 i8 a$ o. ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 k* p$ S# \7 T) j7 a, A [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 M% L4 y! M4 i8 x; H! H- g5 CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); {0 S4 ]" Z3 O- \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// e3 T x: p3 t# h. w# g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% J" K v* N% k4 V+ V& W
MCASP_RX_MODE_DMA);
5 \& m/ `5 c3 s# ~9 BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 t% i9 j$ Q2 D0 N5 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* r4 _& Y, G Y, i& t+ K8 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ T; G! J% B, ?7 p, hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 d* X6 ~) E$ JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% t. A |7 C3 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" _# y' W6 B/ t& D6 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! t4 Z. R$ ^4 p4 d9 Q3 }0 wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 u0 r: I0 R# I6 i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* B2 R t% r# q* u/ S
0x00, 0xFF); /* configure the clock for transmitter */
5 j2 B5 V$ k2 e& R+ I/ DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 K1 E* x8 B; k) I1 x. b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- T1 {7 J& A' `, ^! AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- M" ~5 K/ z! Q$ R8 Z! [' M3 u
0x00, 0xFF);
; ]. z% z; L% |; O% U+ _# }2 F7 H! F9 ~8 e' ` Q5 C
/* Enable synchronization of RX and TX sections */ , @6 F6 j" B5 a, I# b7 o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. S0 X4 A4 Z+ y- G& \" I' L1 B) H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# r: I2 g7 q; g; Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% E& L7 J# e. C! T7 m' h** Set the serializers, Currently only one serializer is set as
$ c- P W/ ]2 ~% b/ ?! q2 P! R$ U** transmitter and one serializer as receiver.
& P+ p" z5 Z. R0 _4 L9 s: I% z3 s*/% K, f* S$ H6 g) T% v" O: C& p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( s) |$ Z* y5 H: e- }* R: sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 u4 U6 |$ A( u$ b0 {7 v: S** Configure the McASP pins
/ t. m5 x6 a! B. c4 q q) B$ e/ H4 g9 t** Input - Frame Sync, Clock and Serializer Rx" [' z z( J9 O2 o
** Output - Serializer Tx is connected to the input of the codec / B% a0 u6 F8 |( P& E
*/
5 m: g9 o# P9 X. v( k& OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; E/ t" d2 ^# d8 Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 e9 e$ v0 [9 G2 P) p! B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( P2 I' Q4 R: U& m3 ^! i| MCASP_PIN_ACLKX7 L% B: D# }7 A% M9 x! ~
| MCASP_PIN_AHCLKX
" G+ @7 l5 A" ]: y2 p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 \% |5 v, X/ p, yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ j" x* F* {( g/ Q: ?4 e# A| MCASP_TX_CLKFAIL
4 l- h5 r7 L7 C! ?| MCASP_TX_SYNCERROR! _' L; H. ^( o6 U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ P& @' K0 o9 H- ~| MCASP_RX_CLKFAIL
: t+ H+ W2 V/ u [! L( e| MCASP_RX_SYNCERROR " K, ?2 a! @) W$ H
| MCASP_RX_OVERRUN);' b* k3 l4 \" d4 T
} static void I2SDataTxRxActivate(void)
2 ]! K- B8 U3 \- e/ D: P U{
- G7 p4 Y% b' |* P. S6 C& o/* Start the clocks */
& o0 ^* U" y8 U: Q" O8 Q* {8 W% e1 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ A$ m! O! t8 m; U6 k5 r( CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, Z E$ X& R- H2 Q) r+ e# R# dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
G' R8 [' E! H6 QEDMA3_TRIG_MODE_EVENT);3 q5 J" q: ?; J% a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : Y/ C. P1 u. A; D
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 O2 i0 w5 l4 ^* n; l0 l+ v- M6 P1 l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ w1 M* M3 r2 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( p. r4 p0 ~/ i0 G. y- Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; L5 Z( I2 I% I9 {. x, f% h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 m( n% N+ u/ x$ ?: S6 Q3 e( q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" ^- m( f: q1 `/ c- N
} ( E! [# I) S3 D' G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! Z, m* z, @, U7 L j. }
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