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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, N% L$ l" C2 Q6 |9 u+ l( u {
input mcasp_ahclkx,
. q9 j U( k: Winput mcasp_aclkx,
8 G+ k) D! ?. v! A1 q: r/ Zinput axr0,
3 E D0 x4 l+ `, v- y+ v; h0 a1 Z9 k; w& x0 l* N% {% ~
output mcasp_afsr,3 @- W+ U* s- h% z3 M
output mcasp_ahclkr,
3 ? Z* U" i3 @8 ooutput mcasp_aclkr,) P/ H- P% P$ q6 X
output axr1,
6 F7 g* O+ F: n- i2 M8 S assign mcasp_afsr = mcasp_afsx;5 g- O: n; t1 O: _) }* H6 j
assign mcasp_aclkr = mcasp_aclkx;
_8 B: L& L9 c' j: N6 C0 A: W z; ^, Passign mcasp_ahclkr = mcasp_ahclkx;$ a' @# e2 j, j5 |; {6 p
assign axr1 = axr0;
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/ h% Y0 @" e# s% _* h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) `: L" D" m0 i+ U4 _* S" ?
static void McASPI2SConfigure(void)
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8 `* J7 z( d, VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* e3 K: `0 S$ ]& y. G* _" U7 b1 v, Y$ aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 n, Q) @/ D, |- s* s7 aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 g4 N& t0 v( Q! }. e7 O3 i" g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. x) X5 g" o0 i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 I) _2 T1 V2 g; jMCASP_RX_MODE_DMA); }. l/ @" ]# W$ Y: Q) y8 g$ r- A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# Q/ z( t6 n3 }/ h; y0 V& M7 g2 k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( n) R7 D2 H- b' n m. [5 qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - v- O3 h. Q, T- q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 R- h# I- e' a+ c$ Z7 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# V0 ?. P7 o% fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 Y" ^$ [, Y, @7 `, bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 I: K; Y; R4 ]6 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ N }' N% n3 m3 r- r- RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% O, |" P0 v8 @6 W% t8 ]# k
0x00, 0xFF); /* configure the clock for transmitter */+ M8 i5 Q9 k( M/ Z8 h, e0 @* `0 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, C' n6 k' }% S: GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' o: h! R, a& i5 }2 iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 e% j+ T" U! r; g; @7 a* D& W! g
0x00, 0xFF);; e6 j' }& N Q
$ y; |- E) O, n0 `* i) Q
/* Enable synchronization of RX and TX sections */ - O: H! U- w% X" Y2 h1 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- K0 z& n4 I, r* \+ _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. j7 _8 Y" L7 l! o. q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ J1 a/ @) M3 Z$ ?+ K+ `8 ]** Set the serializers, Currently only one serializer is set as6 w! @9 K3 S2 b6 U. [
** transmitter and one serializer as receiver.
5 c- A8 g& P5 H: I' @# W0 G5 N*/
5 L$ t* W! n# [: G! I( {3 ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: |, U# N4 K0 g) c' _: s) ]1 {* U1 Z1 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 w* s4 L8 k9 V** Configure the McASP pins 2 j. j6 ?% b/ t8 D' q% {
** Input - Frame Sync, Clock and Serializer Rx5 I% S3 {. H9 {
** Output - Serializer Tx is connected to the input of the codec
8 {, M4 ?1 L$ w e6 ]0 w*/. i6 c# O0 R# U0 X3 D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: V; M0 K [' ]" R0 I2 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- I( n' x k; }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 R7 u. z# h" b4 G( z2 ^7 I
| MCASP_PIN_ACLKX
) y4 q: B# X! s5 P| MCASP_PIN_AHCLKX
0 y3 u# n6 x! s; y+ ~$ z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( E8 c0 D0 x1 qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; `( B$ M7 j/ E$ L8 R$ ^" d4 f| MCASP_TX_CLKFAIL ! n. ]3 A+ ]6 _
| MCASP_TX_SYNCERROR- K. J0 R- \3 R1 q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . |5 G8 h B' A# m6 l1 J$ }
| MCASP_RX_CLKFAIL% r$ h3 \5 M3 A! A3 |, a. K. V
| MCASP_RX_SYNCERROR 7 L# c4 W9 r. \; }( b Q
| MCASP_RX_OVERRUN);6 L. c8 g+ n* `
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */1 \7 U7 z$ s6 H" m$ x" a# ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: O: e! w$ T2 m, D+ e. s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: Y' Z- `' h: o8 L$ z; X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) N* `/ D. j/ ~9 S- F6 E7 W( b9 B. j
EDMA3_TRIG_MODE_EVENT);
9 Z* t S, P9 k: o9 X6 {/ pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / X3 k4 `6 }6 R7 ~5 V `( B( k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, D7 Z% q2 r. HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) e1 m: u. s$ i4 G4 Q7 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ y6 N3 r; v' y7 ?( O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% v8 V$ X, {5 r6 n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ `3 k$ X2 I# `- G: I. s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) w: u/ H1 P2 E! w! u7 U
}
5 Y/ I" n* u) j. L/ P" F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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