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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" w6 ^$ M0 }* n2 K/ T: Linput mcasp_ahclkx,9 }+ K; \/ L0 m! H. K& y
input mcasp_aclkx,. x6 T0 p9 l( C% D
input axr0,1 Y% Z! ^ u0 y1 {/ Y; O
% A5 G% [% v# [9 P3 {# {. f7 Loutput mcasp_afsr,
3 r4 l Y5 A3 j% d0 Q6 ?1 Ioutput mcasp_ahclkr,
$ M; h8 u5 B7 i }4 e7 a1 Routput mcasp_aclkr,0 h/ [( ~# _& ?6 ?
output axr1,8 x; b1 l' c; m: ?7 m* J! v
assign mcasp_afsr = mcasp_afsx;+ U2 S+ K r$ _2 J& ~/ G
assign mcasp_aclkr = mcasp_aclkx;
' ?4 Y& @$ ?) ~6 m wassign mcasp_ahclkr = mcasp_ahclkx;2 {! ^7 m2 P2 q6 T/ S0 {
assign axr1 = axr0;
4 L1 y" r- i7 g
! Z) e' Q7 a3 e* V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" y1 l6 a8 i* L$ C- l( `7 H+ u0 {static void McASPI2SConfigure(void)
! H6 k% ]) @0 F* z; \. c) ?{0 \( f. s& e! T; E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! e; q% j" \0 y1 QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' X2 D% d! V/ k1 O& n% w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" }4 w) e; q2 B2 c z! m2 V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 O: A* f! o/ H8 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: t- w7 B4 M, W% U1 w' n
MCASP_RX_MODE_DMA);
- a- D7 \, U8 P: p" PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; A* m$ c2 V; o( }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) R* u! p5 R. w3 K$ `! J" y& rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % z" \" l6 H9 _" x# _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* I. g, t d0 J" lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 p2 B4 t5 @9 Z; j7 u$ JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// W7 s" X4 D5 E" g1 a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 o( e8 y0 B9 d w5 n0 v0 c% SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' R& {, z4 Y* K- [$ M( \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 E9 k8 C% X1 [1 k
0x00, 0xFF); /* configure the clock for transmitter */" ^. q1 f+ D/ I2 ` M/ M0 ~$ B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& E9 X& F9 C( \, k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) U( m, u q5 ^$ g; xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 T* n5 I6 h# s5 p4 c, p4 r+ v6 s0x00, 0xFF);
0 Y1 B- j6 k. N/ }/ @2 I" z
/ L: U+ w8 V* T3 b* j- E/* Enable synchronization of RX and TX sections */
! J1 m+ o" M# h3 Q2 ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 q3 A S* j6 c# }9 b3 I9 XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 I# R. Z( O/ y. e" f" B- r* y# wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 {0 M* f* v8 M+ N% p
** Set the serializers, Currently only one serializer is set as! T* Y% }: r: s+ m' v' _/ o/ ]
** transmitter and one serializer as receiver.
2 i) f1 t( f! Q2 y# f*/& n- ^8 ~. b' O# C0 h8 `6 ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 c" H" |# y4 N v9 T! TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# t5 J, \8 _0 @. d4 C** Configure the McASP pins
( V) K/ m5 L- @2 ~& M5 J1 h** Input - Frame Sync, Clock and Serializer Rx
' u+ \- K' a' b8 [** Output - Serializer Tx is connected to the input of the codec " ?3 z1 ~; D6 I* c' ]( |2 r5 e
*/
% v( x. i1 H- h9 C$ ]% j7 F# `' uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: ^/ ]5 s( @8 k& z& {" Z6 [% ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 C6 K& l3 f$ D' K* q# K$ T; sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) m1 t _* v9 [, p
| MCASP_PIN_ACLKX. D( v W. X9 a; o& l) O" [
| MCASP_PIN_AHCLKX
! u& S" h3 f1 g% O5 Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ L4 ]& \4 r7 F: E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # @0 ?" _& L5 H$ Q) {
| MCASP_TX_CLKFAIL 7 z, s( ]" j. Y# U
| MCASP_TX_SYNCERROR0 [% m/ i6 P; s% H2 T+ F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) Z: n- I* t j' m$ }- C/ q
| MCASP_RX_CLKFAIL9 b0 Z& X. k r" `
| MCASP_RX_SYNCERROR
; B1 {5 B s" u' Y! v3 T5 @| MCASP_RX_OVERRUN);
; c! u/ I9 A* i" M; ~$ a} static void I2SDataTxRxActivate(void)
$ w" J9 d G3 D/ B, J7 K{
# a; h: J2 ~6 x8 M2 H6 p. j7 O4 J* H/* Start the clocks */& f, \- j0 e8 V; s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 R& T# F! t: `4 R1 ]8 S& J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 f* ?+ c& c1 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" y$ i( o/ }+ r# f9 t8 FEDMA3_TRIG_MODE_EVENT);
~$ P f. `$ n9 ~. }6 _3 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) W: `: j2 i$ P2 r4 g7 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& ?$ M' T2 m) x1 X/ I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ f# f b4 P! r, \. R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" v+ v0 t1 K+ ?5 V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; ?0 f, P X0 q! _; E/ TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% ~, Z7 d' ]) ^- t2 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 K2 j+ A# ~5 S7 P
} + C) `' \$ Z! q/ n1 n0 _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. a1 k8 \2 C" w2 }9 C! Q" h
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