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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% w. \/ {) |4 J, b3 _" l5 R9 F
input mcasp_ahclkx,. z- W& Y! f1 }1 s' R- S
input mcasp_aclkx,
- k$ u9 z% Q0 ^: Zinput axr0,; J. Y! ?( l7 E& w+ a& u" e8 t* n
! e" J. a: J4 o/ N0 _% S' voutput mcasp_afsr,( P/ x" n: c2 a2 n) E
output mcasp_ahclkr,
4 [! L# B0 H' ^6 a4 j- doutput mcasp_aclkr,
: v7 l2 @$ {' w' ]output axr1,8 t1 D2 I! m$ W- H _2 K6 U
assign mcasp_afsr = mcasp_afsx;& r6 [ V. u, s9 l5 y9 }" M
assign mcasp_aclkr = mcasp_aclkx;
" }0 x% H% ~: Jassign mcasp_ahclkr = mcasp_ahclkx;
3 c1 ]( P1 ?: z) A# B- `0 v+ cassign axr1 = axr0; C- k" }3 T5 W, b% O+ B
/ A- P! r) L9 @4 y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 P. c# M# q' H/ m+ [, V
static void McASPI2SConfigure(void)
0 N2 U/ ^* U3 F7 V$ b{
) H9 U7 ^ v$ O$ R( _! CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 \- A4 d( z0 k2 G7 M; oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# A$ M- d5 i( a3 M# t- \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& N Y, D% N, a+ IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ ]. e$ k7 d5 X, T( p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- {; q" w# L1 V. a
MCASP_RX_MODE_DMA);3 D1 x7 F- c7 |, r0 j% ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 ]" j2 B1 M& BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# y8 T5 L/ q* ^$ w0 J) WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 G2 h/ B6 C x( D+ E# C2 g. g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 Q$ p$ W- q( QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 E& c {1 N0 s9 L; [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 v0 F5 _; B) u& u A, M5 ]- GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; S* b) |/ B7 @% o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ d5 D+ |% ]& b' e6 A( f" ^6 [2 f: GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 U; b( A6 \0 _% T( D# z, I0x00, 0xFF); /* configure the clock for transmitter */
) N: P/ w5 I/ n3 x) O$ ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* [" o" K- T& p, e* i% vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: p# ]' S: Y: K& ]. z# FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 C" Z) B9 J6 B, V5 z
0x00, 0xFF);
$ I" h& d+ w, P- r0 a1 K6 S) A8 C' h6 S" U1 @5 o
/* Enable synchronization of RX and TX sections */
2 t* R* g+ V# j" B4 A Z4 DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# m) h! `3 E. F$ ~3 m. M6 C7 E9 J5 ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. Z2 k2 C2 ^" [7 r; {2 R+ H }2 N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 d# H _- t V* w) K' _1 b
** Set the serializers, Currently only one serializer is set as
; J5 D2 Y6 e, i1 v7 ]** transmitter and one serializer as receiver.- |0 [% q" h% T
*/! ^% M6 Y0 `5 T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 f/ l0 b7 z ^0 |( Q1 O, `! Z$ w( SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 a6 d7 z. ^; }1 s9 b* H( c** Configure the McASP pins ! ^ a4 O- o+ l3 c& ]( q# y- {
** Input - Frame Sync, Clock and Serializer Rx1 k# K& P$ A! a( n% G1 }
** Output - Serializer Tx is connected to the input of the codec
\. Z* P2 H; r*/: Q' m% E: H! V1 D$ i5 x. J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 c2 `2 z$ h$ L/ x& c4 A1 WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 B# O. ]6 ]7 c& d; r& O( c* a5 @1 k# ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 }6 N: O5 i. c3 \% k& d| MCASP_PIN_ACLKX
9 W- c/ f& z* w" B3 ~| MCASP_PIN_AHCLKX
! h/ G( q4 t1 W3 l$ {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% i8 R4 _5 c2 N5 g0 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 S+ C2 B7 R3 U4 r
| MCASP_TX_CLKFAIL 8 M- n6 a4 o M
| MCASP_TX_SYNCERROR* J5 c! }6 `: J7 ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 I T' }! C7 e0 m| MCASP_RX_CLKFAIL
4 f" n/ Z( }9 [| MCASP_RX_SYNCERROR
$ L+ E% j- i4 N& O7 h, s3 `| MCASP_RX_OVERRUN);
( C3 t7 p$ E' p, ^& h7 \9 Y* |} static void I2SDataTxRxActivate(void)& g$ k) h( ?/ e4 i9 \+ b1 u; H
{( D9 A+ z$ D+ O' a8 A
/* Start the clocks */5 Y* f$ j, w( x/ F! [) r; u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ h1 }( L/ S& e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( N* o. a# z5 |& S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* |' n" f+ w) {) b
EDMA3_TRIG_MODE_EVENT);
) Z# ]0 |& j2 a) d/ y! } ?7 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' o& V8 p) T- E+ N: z9 y& a! s$ yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! ]" | S: M, k6 b& O3 D4 ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: T6 z; u) i, m1 V/ r& a3 L) }' c RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 M A8 ]' i( W C- d, O7 T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" r* e R- i; H$ l, E8 z- ~. g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& ?, E: @" n {) k, B g. E9 I# r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 ]3 G% g* y6 p4 L' ^1 S5 E( H
}
1 U3 }, r7 W" F/ \7 u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! J" f* w v0 N6 t1 q: i; _. u
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