MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
* W, Y6 H3 T9 }( \# Ginput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

. V! l* S2 X7 X6 m! |- K  n% Loutput mcasp_afsr,
6 K1 @. b/ ^& ~4 |2 [5 ?  P$ }output mcasp_ahclkr,
output mcasp_aclkr,
) {9 n2 p7 c" `9 y- M) g# Ioutput axr1,

assign mcasp_afsr = mcasp_afsx;
! t: y% ?/ S& Fassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

' D! A. @" G; Q: K. Y; }  e2 B

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
4 t/ L; T+ F, z5 f: f; Z- pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
. c0 @4 t, H7 I) nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 k4 [/ e7 v/ N3 V. v: n% {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
! ~4 M7 W  S3 E6 F/ N' X9 J4 ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 k; j0 ^3 t8 [9 E; f* D, Z. jMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
. P' T! V% _" k( W$ AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% k7 [9 R6 C0 P3 Z6 K0 {, oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
$ ^* O4 Y7 U# g! X, e' Y" ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
+ z+ L, ?+ B. ^, L  L0 U* D7 w! F
5 _) h" R/ w' P" W: \  v, M/* Enable synchronization of RX and TX sections */
0 I4 l% i9 {; V* u) C* qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ z& Z; ?; A& E* K5 H( y  MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
! G7 c6 O6 X/ }% G7 ?0 w** Set the serializers, Currently only one serializer is set as
8 a/ k! Z$ X  [$ e8 @** transmitter and one serializer as receiver.
7 K& C9 G+ z2 ^) z*/
" ]% ]7 M) k+ U# X' x, MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
  p" }( k" s$ T( e6 \& v; y$ i; o/ fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
7 ], U5 Y1 q4 i** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
' a' w0 f6 B+ `! m& j** Output - Serializer Tx is connected to the input of the codec
*/
+ w% ]' I# b5 GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 L9 p  @7 W1 EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* K! S" V% i- D- q8 F| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
9 K& E9 [9 j2 I* _8 ]2 n| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- L: ~& H4 W" q4 S| MCASP_RX_CLKFAIL
+ S/ v7 x- U* F) y8 t| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
- r* W8 j' J' k( E" K% h{
: D/ c  P! `, [/* Start the clocks */
3 j" \1 M3 {/ c  l) v. O6 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- d" T2 D4 r( L4 ~8 ~* zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
9 N5 @- P$ {4 ?5 K4 x: aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 {' S& p6 X3 ^EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
" |" k1 E5 H7 \- E. t% ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
  j) k  i% n; uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
( ~+ m0 p" J4 P8 s3 ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
" a2 M& |1 `3 K$ N' sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* i# t3 E, P7 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.