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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! A7 D; @1 A9 R7 ^ F
input mcasp_ahclkx,' c; }& H, |" n/ ?2 `# _
input mcasp_aclkx,
8 I( {& ?/ |" Z' x# y qinput axr0,
, `! @* d! ~8 T' {- Z/ \& B1 K/ }
( e) y# z' c1 o: I) v, Soutput mcasp_afsr,
9 K; L9 {( o' C& L5 n" G" b0 p" Koutput mcasp_ahclkr,' _- [, C) B* b! r. s( ?& ?4 L
output mcasp_aclkr,- T. _ h% C. @
output axr1,
2 z& W# N- R3 u) c- ]0 p assign mcasp_afsr = mcasp_afsx;2 ?" \* I5 L5 n2 f* L! O* s7 s
assign mcasp_aclkr = mcasp_aclkx;
& V# c# d, A) b- I" h: B ^assign mcasp_ahclkr = mcasp_ahclkx;6 u& p. ^9 M( j" J1 B7 h D- {! M
assign axr1 = axr0;
. z: y. Q$ p" B0 B2 E
4 F' r7 T. s9 B; A# J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / J2 o) ?- c/ j% u: u3 A
static void McASPI2SConfigure(void)$ h' }: m1 `! ^6 Y5 {/ p4 J7 s9 v
{, F7 c% a. i: q3 F) T) c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 |, x2 K2 u, s1 C$ p7 MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# Y4 O+ [' s9 ^% D9 b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 Q" U: k9 u, s2 d2 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. d' q# w: T/ \; b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 W) K8 H/ j, o9 D8 J- BMCASP_RX_MODE_DMA);
. s4 c F! a$ O# n; N: A" SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# P8 X( T7 W% W9 A. ]" b4 Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- {' W. Z: o8 h1 R+ Y! `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 N9 ^$ D! \! C, R6 ?# k) Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) S4 n+ j3 C" u* V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / g% q. U: {% U0 N0 Y9 s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 z" |! ?: v; S( k; l9 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 p, Q' t: [8 |9 u, AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 X% ]7 D* w; U) nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 G- ~$ t) R) `: e' @
0x00, 0xFF); /* configure the clock for transmitter */
! Z- a4 Q) P6 ~7 ~7 Z- EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% P- E, t) d+ Q# kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: u2 H& F0 U: W- W" bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ ?2 s- | L2 h* n0 q
0x00, 0xFF);" i: z, T" E2 l9 |7 m2 j; O
- {6 C+ a. }, w# v3 s5 p/* Enable synchronization of RX and TX sections */ ; D0 p; b. L" B- H) j7 |- P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# x' U) V) M6 `2 r! g5 w+ W& |4 D+ uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) |0 z; ]. V/ ]5 F) J, Z T' [# N1 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 g; Q& `& o9 U% b3 s& Y! m** Set the serializers, Currently only one serializer is set as
% i7 V9 c8 K1 V0 o7 @** transmitter and one serializer as receiver.
5 H# A1 D& L7 I# }/ G# \4 O*/
, @( ]) u+ V: ?" t" l6 BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 c7 B! W Q- \% ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) x: I' [! E& n4 h3 y* r** Configure the McASP pins
3 `- }9 F9 ^' R** Input - Frame Sync, Clock and Serializer Rx4 G( a0 ]: |& i3 @( n# x C
** Output - Serializer Tx is connected to the input of the codec
( ^( W3 R3 F( S E8 l2 q5 |*/
, g: n: f1 i4 [3 ^$ L$ |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 P0 y6 o5 S, x# u J* |# u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 P; D& B: V% w3 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, X! h, c+ C& M| MCASP_PIN_ACLKX# ~% | T! D6 K, x
| MCASP_PIN_AHCLKX
6 B5 X7 C9 i! p, V6 X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' | F1 G: N7 e: n* Z4 O& JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 e9 \# q/ a/ C+ ^8 z' Y| MCASP_TX_CLKFAIL
. O7 t- `; h! t| MCASP_TX_SYNCERROR1 y& s# R5 {+ }! F' u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& S }- P9 ]7 u4 j1 y9 Y$ l| MCASP_RX_CLKFAIL
( S4 n' p2 i3 T4 A i2 J# y| MCASP_RX_SYNCERROR
: B0 U+ K1 {* V+ h( t1 c| MCASP_RX_OVERRUN);
. x& c8 a, B* h$ |} static void I2SDataTxRxActivate(void)
5 d7 `1 o# t F8 z6 p, Y{7 X& p+ ~6 S5 T- R
/* Start the clocks */
7 u: Z* B7 z3 xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 G/ a- B0 ]% Z4 V2 oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ a+ H/ }. k+ x5 |2 T% D1 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. A5 A" T2 s j( v( W$ S
EDMA3_TRIG_MODE_EVENT);0 i. n! O9 g& ^' x4 N( \0 S0 O. E4 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % H; f/ j4 X8 [! @% ^# B4 G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& n, D, E5 `7 K4 l$ IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ _9 ]) c, v0 j" @) F, D% @- QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# |, ~8 L z; {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! C3 w, Y! |: R1 a( k! T. Y$ M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% l$ p" s, |1 W5 D9 r4 nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, h; B# P+ f/ I, z, I2 o}
2 f4 }# `/ W3 C) p# p! H, |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 p" P: i( S" Q9 y
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