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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, N+ E( R* b: R3 q. T! Y
input mcasp_ahclkx,7 u6 ~$ J! L0 @5 Q- c, u
input mcasp_aclkx," O& I( |. [& R/ d
input axr0," J$ e8 C# Z8 |# J) T) J2 P4 ?+ L
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output mcasp_afsr,/ q( @5 K2 u. t. _; R5 Z4 E: h& L9 v, F
output mcasp_ahclkr,! @, U! {. P) |. p2 S1 I
output mcasp_aclkr,( T+ R$ w: j+ `/ n" q
output axr1,# l" n% ~( H5 e
assign mcasp_afsr = mcasp_afsx;
9 O5 N y; Y0 t0 ]assign mcasp_aclkr = mcasp_aclkx;, \, a' V* ^" H( \
assign mcasp_ahclkr = mcasp_ahclkx; f; Y$ I+ K. B4 f/ u
assign axr1 = axr0;
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$ Q$ q! v6 ~1 v1 q( W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 r. C2 w/ R6 K% x' I5 rstatic void McASPI2SConfigure(void)
8 y1 ?% q& u# r5 h, v4 m2 P{
( |. b, g E3 M0 P" D! LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 I' i' j! w& Q+ U- q2 `: c9 H4 M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% d" J& a# ]: P$ DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 t# h) j7 V) p1 I/ G Z. S& CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 a; b. \: U/ O7 X# D4 O% ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 }; l* I6 i9 E6 s8 j4 ~
MCASP_RX_MODE_DMA);
* h* T; z* ?1 ^3 n" UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 o9 e' E0 B p% W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 F/ v( p5 K( E* ^9 O4 P- ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; M7 Z4 S' `' d' m% {: p: XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% [' m" Z# x2 U' Z* iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 v% h+ l. Z& o. U4 |7 `1 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, z4 r, J: `, _* {2 @/ w+ {0 F! ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); D i& E% W0 }9 q- d( r0 h; U. y1 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# C9 M" N- X5 d% {6 b2 M7 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 c! ^8 h! e0 N: b) I
0x00, 0xFF); /* configure the clock for transmitter */& p! H" Q( m) R9 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ f. Z! G/ O! R8 _( @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, f9 X0 ~7 J2 v8 DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' h g2 t- f1 Q0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ # U/ [9 X# j- o& l" s6 R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- \2 C% w/ v, n" x) E6 k Y$ uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; p8 z6 r2 o+ N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ M# K1 O2 O/ `2 w1 s2 s
** Set the serializers, Currently only one serializer is set as
7 T4 O7 {0 }4 C7 ]3 E( d$ l** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 ~$ d# I; X' Z7 q, ]7 e4 k* [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) Z$ l/ R [, w3 k3 R3 D7 b** Configure the McASP pins 2 S$ ?2 p& h, c* `3 p8 s
** Input - Frame Sync, Clock and Serializer Rx9 t# U- d+ }4 N7 Z
** Output - Serializer Tx is connected to the input of the codec
4 x* G9 }& _8 H. N*/9 p. \9 ?6 v/ A5 r ^5 |/ \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' W; y: X" Q3 s! A( m9 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 h7 [3 q" j/ EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 Z6 I' C6 @) j4 r' r| MCASP_PIN_ACLKX) I9 a* }1 u1 t' Q x# _/ G
| MCASP_PIN_AHCLKX2 i: F2 R5 K8 }* V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: m# J& G' R4 `2 M/ q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # C( b+ G, M- Z. r/ K+ Z$ K
| MCASP_TX_CLKFAIL ) H: l$ T" B7 F, m1 Q
| MCASP_TX_SYNCERROR5 H( p. W& z9 l3 S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. `$ M0 _" f/ }* X" n. E| MCASP_RX_CLKFAIL
- y9 ^8 p @: Z| MCASP_RX_SYNCERROR 8 ]$ M/ e1 o8 Z& U9 |2 W5 n
| MCASP_RX_OVERRUN);
. y( n" d+ S x5 z4 ?# b/ E$ i$ b} static void I2SDataTxRxActivate(void) K' |9 u+ |; K/ Y3 l, n
{6 h f! y. j. c
/* Start the clocks */
7 e3 K& [! i) N! z7 V9 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 \& D2 l' ]* q4 G% }. @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& S( Y/ z% o4 Y4 J9 z5 h+ U, KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ o, ]* Y$ q8 E4 T8 d
EDMA3_TRIG_MODE_EVENT);6 I" }5 g; B7 g- ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 b, A* v- g; i+ r; x6 kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' Z) Z" d2 q9 b# U* F- aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; j0 z/ m* O& x9 t, oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 W. g( v6 s: U/ K# ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ A# P! V8 ]. W0 U. i2 l: W* yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 f7 S# q; {4 b8 L- t4 o2 f7 U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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" c4 V' ?1 B8 l9 B- M, u/ M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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