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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 Y3 T& P, R5 J! ]
input mcasp_ahclkx,7 E/ L! ~0 v4 u$ [
input mcasp_aclkx,
9 f. u* y& U1 n) a5 C4 ?input axr0,6 l% k: z: P" P+ x1 I
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output mcasp_afsr,$ ?: _6 ^/ [6 K7 {
output mcasp_ahclkr,
# B& V0 S6 }+ b# f- O/ T9 y+ eoutput mcasp_aclkr,' _: Q0 s0 @$ N9 ]* }8 k2 R
output axr1,
/ _' D! q8 K- l5 B$ F( n: ~0 g assign mcasp_afsr = mcasp_afsx;+ d1 L7 n0 X) Y+ q; O2 j
assign mcasp_aclkr = mcasp_aclkx;
j; t* |7 [( @- q$ \assign mcasp_ahclkr = mcasp_ahclkx;& T- s" R8 s; g! a% r) c0 j
assign axr1 = axr0; : a. j& v3 p9 \0 B; N1 v' c+ |
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% `( j }- i. |/ ~static void McASPI2SConfigure(void)
4 ^4 O1 I z+ Z' ^( z5 R{
7 F: Q- S1 s. V" W IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 G9 O* D$ H9 V) Z3 o. f( ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% ^* r8 m z: dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 x1 Y" |8 c' K& @* C6 U% JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ u( a8 ? \3 O' Q& uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 x* f, o+ f4 v, [+ M' t* Y
MCASP_RX_MODE_DMA);7 ^# u4 J# Y- g7 ]- _ c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 u9 ~" _! ~; {( j. w* JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- {1 l" ^, M2 K# M$ J0 bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : W7 @0 Y6 ?; ?6 }' J) X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ G5 _5 M1 J- H2 o F8 WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 O4 d+ B2 j; z% F3 [% L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) c* V* f; |1 n+ D" k* bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 m: w& e- P/ C7 h. x; o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& p. n0 Z7 b/ _8 m# h% NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& w) b/ V3 n( h2 m$ z. Q8 K7 G0x00, 0xFF); /* configure the clock for transmitter */- ~0 n: g0 w1 `4 i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# y! i, ~6 }# iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + c$ t; R. T/ P* N' N' z* |# S6 ?& r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) `; y1 O" A: S( Y' e
0x00, 0xFF);
8 Q/ W2 F- V- b3 o; Z4 v' T. Z$ e. d! \- A! k
/* Enable synchronization of RX and TX sections */ / s8 e4 {( D" R) s) \. E9 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 X0 }, k; r4 c4 J" G( G. }4 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- e/ s3 r- ~8 [) K: o6 c
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 a; s, p& V' A, u* C' k& Z
** Set the serializers, Currently only one serializer is set as( }9 M: |* O' n) l& [
** transmitter and one serializer as receiver.
0 n6 J, M1 L* D*/, r6 u3 X9 S; y- J8 `4 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ O8 F+ w' \" z) f1 ?- tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 M0 I/ u2 ~! U( U** Configure the McASP pins
6 w( I7 M0 Y9 O% o2 I( ?% i( N** Input - Frame Sync, Clock and Serializer Rx
# G( U$ k( A2 E) l3 ]. v** Output - Serializer Tx is connected to the input of the codec
- Z' l# @7 x9 k6 [! x*/
, m/ m3 W# A1 E& d/ ], ]' zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 X: j2 c* o6 k! Y: j" n% ?8 }/ g' K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# {1 {2 w T- W4 P% M* q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) T. ?4 M" Y: V# d| MCASP_PIN_ACLKX9 u9 E1 B3 _; j
| MCASP_PIN_AHCLKX
7 o, m. ?. |9 l: h+ [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# x; e7 @- H! k' V: C, A$ xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 W# O0 G, P( A; J& [3 p1 t| MCASP_TX_CLKFAIL 4 R2 F6 P2 ]% I) Y8 M0 x
| MCASP_TX_SYNCERROR
* p3 W/ f) k- a% T) Y0 H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / L! d6 v! U7 a( X6 U
| MCASP_RX_CLKFAIL* E* |* x" p9 [1 q* e& {3 E. d0 w
| MCASP_RX_SYNCERROR 1 U; E. g# l2 J; X
| MCASP_RX_OVERRUN);
7 c& v0 Y* z' ]4 q5 p. H} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
$ w9 V- g' F; D7 `5 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* a( h6 ?0 h0 U8 i+ }( y7 l6 @ P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" [4 \" L# Q* }/ ?5 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 w% m- k/ h8 g: s
EDMA3_TRIG_MODE_EVENT);8 ]' v6 ^+ z3 o7 k; ^. Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 i( G; L* c& t1 H% C! _, R+ tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* k0 |6 Q4 W9 ?' m7 r" F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 L$ }, T+ t% k2 xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 j, `; q: a6 Z- u- Z( u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
c3 `; _6 ^( X: X1 ?8 YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- {; g4 ?% x9 a- ~) i& j, R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 U" g8 Z. s2 t* v, P, l4 r} # I1 Z5 E" q: p+ d! J* }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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