|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
h& r6 d% W7 d+ A8 Q& Ginput mcasp_ahclkx,
( ^0 W9 r# H M- C( ?" E3 B5 P7 Jinput mcasp_aclkx,
; r3 d; N$ e; Zinput axr0,
# _+ }* q- H! @$ n, K6 Y5 _# w* b! N
output mcasp_afsr,
* S4 l! `$ t: k( m6 Aoutput mcasp_ahclkr,# `# c" Q6 _2 F# e7 u
output mcasp_aclkr,) ~- n- }" @* m: g
output axr1,& I, y: I/ O8 ?6 H% t: E
assign mcasp_afsr = mcasp_afsx;0 t/ C5 a( Z0 r2 \5 Z0 B
assign mcasp_aclkr = mcasp_aclkx;
% \" K, y v( D" z! T7 H: Oassign mcasp_ahclkr = mcasp_ahclkx;; y- i z9 P" H
assign axr1 = axr0;
5 T V L2 v5 P" n& M
! ?( }, K5 G! k& ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, z% @5 a: O4 v. h6 O- X& l# ]! Cstatic void McASPI2SConfigure(void)
# d! ^5 H! P* ]2 p! }{8 @9 i: {/ o5 Z6 M% O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 f1 h) k, }' K. L. Q7 J: a* P" I4 FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 A! R- B5 e9 ?; \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ \, K. f6 e# |/ Y8 C1 k8 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 B7 R4 t; N# Q: _& m! Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' I4 Q5 } g, d ~5 Q5 iMCASP_RX_MODE_DMA);
G* L9 A* b4 d+ rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! M. E$ O! k% yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% B2 z, t. O/ J( I; ?5 o4 s/ dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* z! P" C( L* i. A4 | d* nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) A/ b3 d' o9 H$ n0 \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ v5 o/ s" t( W" o# nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ S- U8 z# _: @' a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: P# U* R6 F* c7 f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 r/ [3 O; E$ h) p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 ]2 S6 G. v1 O7 e( C5 N. p0x00, 0xFF); /* configure the clock for transmitter */
: p- \7 }& p K0 [9 }6 VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ O% @. R. a$ M7 N5 k6 N4 ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( }' C/ @5 E w* ^5 \0 {! oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ `3 w2 d9 {* j' `
0x00, 0xFF);9 s2 g3 m3 L# I7 X! ]6 D+ A
* X# g* b& M! F4 p4 c+ P
/* Enable synchronization of RX and TX sections */
. A" }' z: |7 P) j% Y$ s/ j% c( ?' FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! I( O$ E; `. gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 F6 P0 U* y/ P& v- \4 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; L" f6 `+ J4 l
** Set the serializers, Currently only one serializer is set as
0 H I" J$ V8 m# C8 ~0 r9 \** transmitter and one serializer as receiver.1 m! q, X; ~8 J% F+ s& T; }. p3 Z
*/: U) O8 X8 L$ E, @) E& R/ A0 ^! b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
Q% s4 l, o, S; OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 o( g7 d5 _9 o' i0 W1 `** Configure the McASP pins
, i& r1 ]6 ]. P# j$ M7 t; Y! s** Input - Frame Sync, Clock and Serializer Rx6 n4 W) c. |# A( N) }* ]. O7 ?+ j* V
** Output - Serializer Tx is connected to the input of the codec & v* j& w$ e' k/ {
*/
% X, f) i; P2 c2 |5 }) U2 BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 ?6 a5 w2 G2 s9 x: }6 d' s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ R& Y4 J9 s$ s+ |/ D6 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& X3 g6 Z( V- f1 U
| MCASP_PIN_ACLKX
2 \2 D1 C% _% Z% a, l| MCASP_PIN_AHCLKX3 T5 O3 ]8 ^/ `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 o$ a9 R, ~$ Z- g a2 ^2 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 o, | y( e5 A" T. M" M0 o
| MCASP_TX_CLKFAIL
; t4 C. L# v' K/ g1 |1 Q) E4 R| MCASP_TX_SYNCERROR
+ c p0 W2 {# j8 p1 `8 h/ d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' o- N7 W% m2 r7 L7 B7 x* s8 M0 k5 n
| MCASP_RX_CLKFAIL
+ I; ?% P6 B6 l+ [4 E| MCASP_RX_SYNCERROR
+ z) r: F7 i# {% b! j7 h| MCASP_RX_OVERRUN);1 o3 q/ {. r4 S5 q# S& I* F
} static void I2SDataTxRxActivate(void)6 n9 b4 k' Q$ C# z7 N7 W
{
0 T+ u+ |$ Q$ ~; Y* F T2 g/* Start the clocks */! x% R" ^" C% b- f" {* G7 ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 d7 E. @' k7 Q) uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 L+ h) P& H3 N/ R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 ~. A) W: e+ k% Q. m& f
EDMA3_TRIG_MODE_EVENT);2 H! ]$ p" F2 O6 V9 Q4 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 p/ a: m6 \3 M! l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ x7 y' j# Q8 D7 G# |& N+ B/ v" IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 l o; v# ]8 S$ c6 A6 yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* {9 w& r( i Y: e1 a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! l6 \+ S) K+ \2 l8 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); N+ S& @' S) K1 u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 o0 m7 E% u$ k6 a# {
} . a' N' U( z& r( C, e! h$ O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
# J' Q4 C0 B4 j( V6 k4 G3 ^ |