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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- q0 ~! n) K$ R$ x7 {/ {; F
input mcasp_ahclkx, S' U9 v( m* h6 q/ q# j
input mcasp_aclkx,8 Z, l- }! H3 N0 E; ^1 A
input axr0,
1 y8 |* d; i+ L7 X+ m8 l: }) I) d$ U9 d: h+ h
output mcasp_afsr,0 R( G% O8 |1 Q+ Z7 T. }( n
output mcasp_ahclkr,; B J) ?! h( i! w( T
output mcasp_aclkr,2 L- {& ~5 [/ \7 z0 ?5 A! \- E
output axr1,
6 T i( j! g6 Y9 k' ? assign mcasp_afsr = mcasp_afsx;
! j2 a0 s8 w4 p) S. Aassign mcasp_aclkr = mcasp_aclkx;
" h9 y# E/ @2 [assign mcasp_ahclkr = mcasp_ahclkx;
5 y4 L' n+ n4 s) A# lassign axr1 = axr0;
! B) j: b7 @, x
& u6 H. @5 _1 S' x5 X: _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 i: j; E3 m) V/ e* A% ] h n
static void McASPI2SConfigure(void)
6 r# k: X& B$ b1 |{9 Z7 J3 Q: \( m) ]) r$ S! o* t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* h& C3 A. ?' }; H7 s4 y2 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- I0 S( S; j% r3 X$ C9 I0 hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 E4 e- V; [# l4 @6 c+ |' Z8 N' s9 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 b- a4 @7 d' F' Y: cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ ^/ l2 S. P- P. N
MCASP_RX_MODE_DMA);
, e2 W/ \* F @5 I0 O: @- jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, k! P% G |0 T2 {0 z9 \) K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& D+ t; D4 p' B) QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 {0 K0 F% ^/ R) i; a+ ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 N$ G* P/ @3 E3 Z9 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 o o6 F# P! Q+ P% V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 J' J' U5 T9 B. Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: t% F/ [ K2 R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' P0 B& H% W. J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) s p2 w; q, m* Z& j0x00, 0xFF); /* configure the clock for transmitter */( b$ t6 B4 u! X6 A& P7 D# m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# N/ n- C. f- l9 O' }1 w7 j; P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( F* n6 s7 P! H, C' W! vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% _! G9 s0 u" O
0x00, 0xFF);* A$ z; p5 U" ^& ]2 ?: B
$ F# r" l- e+ k" O+ Q# s/* Enable synchronization of RX and TX sections */ 1 l: O6 \9 T/ Z' V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 c [- I1 q* e* `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 v; m$ O* L/ a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 W$ e& x* B) U* }7 O** Set the serializers, Currently only one serializer is set as
; @1 x5 E) ^" S4 ] G** transmitter and one serializer as receiver.* }& H3 I+ g) _6 L" T3 |; b) l
*/, U( b3 M6 w: P( [. [0 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 G% j% \4 X, P3 [9 e8 I+ gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 i0 Z) k3 d# \: C) a2 n; W2 q$ v
** Configure the McASP pins
% c/ ~$ j! e' }3 D0 X# P' E** Input - Frame Sync, Clock and Serializer Rx
5 _! V3 Z7 q5 |# R3 E** Output - Serializer Tx is connected to the input of the codec
8 R* p+ f. G" z4 b. n( W1 H x*/
/ v/ n1 |& ?/ y: |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) B1 ~8 w+ |$ a/ J6 G! D, jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 U% v- W, R9 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; A) g' [; ?: \& B| MCASP_PIN_ACLKX
, ?" b7 X& c/ D4 a$ m| MCASP_PIN_AHCLKX( u) ~, g x0 D9 U. {* k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( H0 [( Z( {1 GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " }/ y @: h7 l: H; a' k
| MCASP_TX_CLKFAIL $ u' H+ K4 X& _6 R/ Q
| MCASP_TX_SYNCERROR6 O6 ^% u5 e: }! ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 ]! W4 y% n, Z, a
| MCASP_RX_CLKFAIL
! D# s E6 P% |3 O2 ^$ b- Z( f| MCASP_RX_SYNCERROR
" M; f6 j! k6 d4 [6 J$ P* m2 || MCASP_RX_OVERRUN);
/ D$ R. v3 l7 R/ x( Y} static void I2SDataTxRxActivate(void)5 B ]$ O3 {' c
{% ~# C N l& Z% y$ D' t, x
/* Start the clocks */1 P' ?. G6 E# q7 |( @8 O' _8 P2 |" }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, S& ?$ K% W& H& [0 h3 }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& y3 ?. {( ~& |5 P/ t" \8 s, G, M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( D' b. \ w8 R9 `9 M+ P7 o" O
EDMA3_TRIG_MODE_EVENT);# Q* ~' ]) `! R9 x( l- t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# I9 }3 J8 q* M+ I8 ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: [( b- F' H' ~/ P. _1 d( ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 l7 B1 g7 D- n- o2 @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' @" \& \2 j* v* ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* d' S L+ |: J& D( w9 B. s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. m3 G+ E7 m1 y* g0 V2 X; c; mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! {3 h9 d3 B4 p7 ~$ {& C: N}
- B, b( f3 X; v) M W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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