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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% R: [8 ?8 |" X: @, e3 oinput mcasp_ahclkx,0 T, W1 d: B$ ?% s5 `
input mcasp_aclkx,9 h3 v C: ^. p! N B3 V7 i
input axr0,
! K5 j* Q0 H& q1 z X4 p! N3 ~, E2 ~
output mcasp_afsr,. [9 Y, k5 ^2 F Z
output mcasp_ahclkr,
0 B2 G8 ~5 e8 {1 b" Y& X" o' W4 Routput mcasp_aclkr,
. {# g; ]# q/ Uoutput axr1,, |1 x- d; C2 C
assign mcasp_afsr = mcasp_afsx;4 K' \4 i( o" N
assign mcasp_aclkr = mcasp_aclkx;
( p6 e& t4 y0 [3 J; massign mcasp_ahclkr = mcasp_ahclkx;
% j( G t# S. \0 _+ Z& {assign axr1 = axr0; o/ J, F( a. ^: J& K6 v! y* p
! ^, X( S- [; ]+ a* ?+ ~# e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 s, Y0 n7 Y& _: G6 C6 ?static void McASPI2SConfigure(void)
1 N) H' R; U5 f* U4 b{
4 R. k$ N x$ k& i1 O* J8 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 K) W0 _& i: U N/ d( w& k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# p. q/ l4 `3 T; rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. W, k3 p; ?2 N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 M7 [: e$ U3 p* }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, c8 ^5 U+ u# O6 W
MCASP_RX_MODE_DMA);
6 h* f+ A! [: k/ s0 |, bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 t, e$ p7 \; {$ y9 {* e9 G3 f) k$ WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: B, p7 A) r4 `: ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# X$ ]7 L8 l0 m! c& q# FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. k! N- c' ?2 Y4 ~- y9 ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 V4 x0 F3 B! M& Q8 N- `7 y& gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 B6 J1 P' L9 B! S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% j5 ]* L, b* C0 S0 ?4 f1 VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : m# k. E% x4 C) j4 Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ ]1 v z! M' I7 k( r0 |( \6 o0x00, 0xFF); /* configure the clock for transmitter */
9 E! f' c! H7 ^% AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: V5 u& ?7 |8 d" x n mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 ?9 E: k" L6 V' h3 gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 ]& S1 ?0 `# d/ P/ n: w
0x00, 0xFF);
: R" T/ W" U5 s5 ~) g/ @4 f0 { ]* d! }- c% {. @0 \' }
/* Enable synchronization of RX and TX sections */
$ w; u; o9 b4 D2 I) e( n" }, v6 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 N8 h# O. {) c1 z+ xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' y; O# w$ k" E3 }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 ]/ [. h8 G& e+ |1 ], c- G** Set the serializers, Currently only one serializer is set as* ?# F8 x$ t/ e c! x: S/ J
** transmitter and one serializer as receiver.
! W# u$ X3 A4 D9 {- {% c( V*/9 {) w+ W% C( {) q( Q4 N. c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 r6 n' \% n2 ]( n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ V7 {# l" g- w$ s) k
** Configure the McASP pins % W" B2 o) x. ^
** Input - Frame Sync, Clock and Serializer Rx. S/ W: A" |" X/ }
** Output - Serializer Tx is connected to the input of the codec
9 t5 E5 _4 T8 R. S4 P; R' H3 e*/7 d5 W) L `9 m* [; s9 _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" a, M9 W X/ @1 H- DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 q3 ]- t% S2 R& a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) k: Q& y* k7 [9 h4 x$ s- F5 E. b| MCASP_PIN_ACLKX, h# [' R7 o5 i
| MCASP_PIN_AHCLKX
h/ l$ Y( A/ z" @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! S* e2 b+ a! @/ q% i# JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ l+ V8 T6 G; X& u; _
| MCASP_TX_CLKFAIL
_; {- b. j' M0 D6 K% N| MCASP_TX_SYNCERROR
5 `( s* J" ~8 x8 X3 d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 R% w$ K, r7 N3 f) t| MCASP_RX_CLKFAIL
5 x' W- f7 Z0 G+ p7 R| MCASP_RX_SYNCERROR
, H" t+ p i& G* n8 N) G| MCASP_RX_OVERRUN);
3 q; a' @6 t0 \( V& u} static void I2SDataTxRxActivate(void)
! g8 G/ w3 M& D/ M3 h{
' I% E* ^6 d1 L1 x/* Start the clocks */
- X* g/ H# J! o6 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. c' R) _- r; O( |" R8 k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( d5 ?& @4 r: b5 X3 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, I4 J( J- u( s; ^
EDMA3_TRIG_MODE_EVENT);: D, P, T+ I! H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ N& j6 C O) Q }# d* _2 zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* }, ?, f. X0 }& H+ P' }% e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ }. _3 O' M3 ~8 j8 k$ \9 \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. D* h0 ^5 D) u9 z$ Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 J& ]8 n1 _* X- R& W9 [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: X. i5 Q: H" d. [1 d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 N. ^2 v' A: v& d' M2 q: {4 l, b( m
}
( ~9 t) z: c b+ f4 g- X* R! t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 ]7 F1 f4 z4 ]. ?( L/ Y
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