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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 U. V3 x% f. f+ jinput mcasp_ahclkx,# ? P( s; V N2 y0 N
input mcasp_aclkx,
8 ^( w1 V# {2 \" G4 f- ]input axr0,' j$ ~ H; l. k0 u' j
2 k8 F9 G; e) I$ x6 N9 toutput mcasp_afsr,
0 d8 j( ~8 W* m* o9 K* ?% V5 Moutput mcasp_ahclkr,
& X% U7 t& T: I; ?: Noutput mcasp_aclkr,$ {3 {. D) v3 a" X
output axr1,1 V. f, r! t0 M1 P2 o
assign mcasp_afsr = mcasp_afsx;# h4 b1 x+ _" p, n6 N+ ], y
assign mcasp_aclkr = mcasp_aclkx;
$ f) S e6 ]$ j* I( S1 E( L5 z% A+ o; _assign mcasp_ahclkr = mcasp_ahclkx;
# n1 [/ l# Z! P( _' p( r7 ]% u( yassign axr1 = axr0; $ H7 I0 I7 N' s( u4 h- o/ @0 y
+ n' X3 I ~5 m: G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) Q4 A9 P0 B2 |% [3 g4 P
static void McASPI2SConfigure(void)
# o8 x+ S5 \& s& R+ w8 \' l{
1 {8 j6 B2 m5 f4 C9 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* S3 k/ I; J- SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 ]) _. _5 q; {- A/ q h7 O% zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) u% w0 k+ m2 t' y0 s5 C2 q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ p2 P% Q& o. r( {4 |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# \. `0 }/ x6 _' ~
MCASP_RX_MODE_DMA);
, _4 S% p+ E- T4 ?# q" X6 W+ D* yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 M3 F4 f) G: p) W; n* h% LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 w: o" x u2 ?( n3 G7 T9 M" H# ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; k m( H' t! \; l0 M0 h) X. UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 D6 r0 z0 x; L3 ^6 j+ Q8 fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ n( F; j& b Y5 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 C8 ]7 N# u* Y0 u2 S; q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) g# g6 @; I! }( C& C- jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% t q7 |% j" iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ G7 s* c/ ~3 y+ k. { o# U B0x00, 0xFF); /* configure the clock for transmitter */
. A L" U: h, o/ W3 JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( i4 J) @1 H1 ^: s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, s, k% @5 f" @, R4 S( L% DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: y/ r x4 f/ z. N
0x00, 0xFF);2 P @% D$ `3 N
9 w+ U h) ]% ~. n3 D
/* Enable synchronization of RX and TX sections */ , j3 W; v! N* W% h) d9 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" _2 v2 E, ^1 R) a4 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 B) y7 M* |) L5 l8 ~) K. c2 c$ oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 ]9 p; S( i' {2 k& H/ I9 E7 u
** Set the serializers, Currently only one serializer is set as) |: x+ [6 D" L8 L
** transmitter and one serializer as receiver.
: O9 v2 D5 r2 G5 r( i*/
0 q9 y/ w1 i4 f6 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ G6 s3 q: i) g6 {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ k- V1 z# x& q$ H** Configure the McASP pins * ^5 ~4 c( } s: s* M1 z- [
** Input - Frame Sync, Clock and Serializer Rx
. @5 q$ e1 K! t! x- }9 u** Output - Serializer Tx is connected to the input of the codec # H1 ~% ~) H( e6 u
*// C* x8 A$ ?/ W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' F1 s G# F7 Z, O/ {% o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# P4 H- X( \* j3 g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 D+ b: [+ I7 l
| MCASP_PIN_ACLKX
9 g/ r0 h6 o4 ?: x0 K7 |/ _. c| MCASP_PIN_AHCLKX
% ~4 P* Y0 m; f. R- M& V' e' k- _: o| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) c" ~# B+ X/ P+ w" p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% C2 N% l+ c% a6 L& }| MCASP_TX_CLKFAIL
, \% m; {# G; i' N| MCASP_TX_SYNCERROR! w6 P8 {, K6 t Q5 F% ~" k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! k, P6 B9 A! e# X% K! N
| MCASP_RX_CLKFAIL, ]$ v- {, T' L
| MCASP_RX_SYNCERROR / _5 i# q' N1 l: W, b! [
| MCASP_RX_OVERRUN);, ` e' t. R( W# ~( ^% z. U/ X0 r
} static void I2SDataTxRxActivate(void)
) g$ d H) |* f3 Q* {{
- }# h* d8 I( p# T( Z5 A/* Start the clocks */3 |+ b' V; j6 F% I" X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ y1 x+ ~" D! t/ V$ f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 K! H' K2 G/ x3 J" J7 f% x* N* t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# G7 e) Q% {; `- ^ p
EDMA3_TRIG_MODE_EVENT);
8 H' Q% [7 q3 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 i. @. |' b+ B2 C3 N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ r9 M+ ~7 B- w9 s8 Z; C6 E3 R3 ^) i0 FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 \+ Y3 m; h4 j) S5 \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ y$ W1 H, ~; o! B F5 e6 H1 D: Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' Y6 \7 e9 m2 s3 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* ]7 L: o7 E, @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! P3 `# ^. V; h}
3 m2 j( V7 H1 x0 N2 I m' Q( G1 ^9 D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 n# P% q/ c# q+ z5 I
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