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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 w) E+ G' ^ T7 e& ~% K$ tinput mcasp_ahclkx,! q8 ~. N% c& N
input mcasp_aclkx,7 x/ i- U. b! |$ c L% ?3 F
input axr0,
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output mcasp_afsr,- V( W, d( `8 [: u# V, ?! f+ T
output mcasp_ahclkr,1 ]4 k+ u2 R/ v) ^
output mcasp_aclkr,
4 h, ^. J8 [7 ^6 ~0 {8 I. a" voutput axr1,; [# X9 E1 ?' r' u$ T
assign mcasp_afsr = mcasp_afsx;
% ]( U/ a4 C, z dassign mcasp_aclkr = mcasp_aclkx;% E; z: g) l& @9 u6 J% I! \
assign mcasp_ahclkr = mcasp_ahclkx;2 g- e: Q# S- I2 Z+ n2 f
assign axr1 = axr0; : Q- T( I5 m7 L8 \$ H8 i$ C
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - t1 y4 f8 E$ G* t8 K$ w! l* @1 u
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 M: `. w6 C/ x1 T8 O! w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& i; f+ c T6 D8 ]% o1 S% [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 L" B( p( b5 J4 W, k; }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 r3 o( G: b3 I) ^: K7 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ h! `. ?' r9 N4 z! |" G- P4 T& _
MCASP_RX_MODE_DMA); z! W, q& v7 e+ f( t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ \; W) n7 q% Y/ y" yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. C' N0 J0 ]+ S# U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) Y/ {$ _0 n/ {5 c* Q9 {3 [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" A. b0 F! E) j7 V3 {) ^& J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 r+ w4 ^# u7 e: J1 PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; b0 e$ E* [1 r! s5 pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* O% k w% V' ~& |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 s1 _4 d6 Y+ _! I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 G8 L8 l$ i3 O7 Q0x00, 0xFF); /* configure the clock for transmitter */: a- Q6 E% r) R+ t# `: B# i1 y+ o0 E; `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' l3 _7 a8 \) H# b% [2 u* ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' g/ ?9 Z' V# H/ zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! w+ n% q$ t* d: M6 e) H
0x00, 0xFF);
% G+ r: `0 J9 F4 C1 b
$ L% N: q1 b, V/* Enable synchronization of RX and TX sections */ ! s6 C3 t9 ]0 X- u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 f+ M9 q$ l( }. m1 m& h( v7 `4 H0 zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 \" [$ F6 T7 h8 m5 D$ eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** t$ y5 R0 B; o
** Set the serializers, Currently only one serializer is set as9 I- @9 x2 J# F! t( e4 h9 ^; }3 z
** transmitter and one serializer as receiver.
! N# K+ t* r% I/ U1 Q, Z*/
) \& g ?! h/ h0 z3 Y9 cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, B, F2 w8 O( p# {9 W1 u6 t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 s1 r/ ?) O9 U' s** Configure the McASP pins & v% k2 Q8 v' o5 a* B' R( I
** Input - Frame Sync, Clock and Serializer Rx
3 W; U: [0 Y) R% o2 f" e9 _** Output - Serializer Tx is connected to the input of the codec ) I' g+ Z# z+ t! \, N+ e$ J ^4 H
*/ }9 z1 {( D+ T8 A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& u2 k x" E$ T: Q+ l* @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( g+ R$ ^0 d5 Y3 y) GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ X) ^+ z6 ?: j6 H| MCASP_PIN_ACLKX
! p1 s+ j" T0 U6 b* ?- U| MCASP_PIN_AHCLKX1 C6 y; G0 y6 l1 ~* C. }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# E4 J( d# o# l5 ^9 ?/ C! h- sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , X# q; l1 {3 P' p# X2 p; _
| MCASP_TX_CLKFAIL * ^2 m8 w: G& |* ]2 a
| MCASP_TX_SYNCERROR( T2 U: {7 ~0 x! M1 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 m/ v y: b% F0 l/ t, e2 X| MCASP_RX_CLKFAIL
0 _. w2 j3 [$ ?* T| MCASP_RX_SYNCERROR
+ j5 |) i7 E# {' |! f- K& {* d) K| MCASP_RX_OVERRUN);
. d8 s, h( m4 z3 C9 y; N5 _5 i6 m} static void I2SDataTxRxActivate(void)3 J" z/ v' m! f7 `, n; a$ f
{' r! d# B# p- U% k: x, P
/* Start the clocks */
3 z. B1 J7 z8 x7 L8 L7 \& tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 u* O( B+ G/ p' x" c. {: ?6 F7 ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; M/ n8 Y; b2 M: o9 `6 g" r; DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ t, P2 y- v: l
EDMA3_TRIG_MODE_EVENT);
4 k1 a. C e4 h% Y! F& Q1 n: i% A& EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 t0 R6 n1 ]0 x! l8 n9 |" A0 L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 v& h. [2 w3 H: EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 G& o7 E4 ]- {( B# g. j& |$ iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- a; ~3 n% Q- a5 ^1 N# [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 j( _6 X- h" c/ S1 t) oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; C. K* e- a1 J: o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 w5 u) M0 |0 ?; Z
} 9 Z% J# {1 ?* ]% b3 m0 _6 A9 v% g# ~: o: n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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