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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ \- h2 u& B b1 H/ Z1 yinput mcasp_ahclkx,
9 V7 f8 _( {: m8 G" a' ^ q8 Oinput mcasp_aclkx,
( s' V; A5 m5 Y1 m' d. \input axr0,
7 G% ?; i) m0 w$ Z8 c: P' k9 z: O0 o) }- T$ d0 K
output mcasp_afsr,7 w6 B- r A5 s$ @, S
output mcasp_ahclkr,
( g+ K5 D2 D- s. x# ?/ e9 @: X4 doutput mcasp_aclkr,+ G8 r. r7 E0 F) A) i, T: T, y
output axr1,
% p3 L" {; k, D7 \ assign mcasp_afsr = mcasp_afsx;: W. q& b F* L: p- x6 @
assign mcasp_aclkr = mcasp_aclkx;
. t0 ]3 U$ u+ ^7 D% p: u; gassign mcasp_ahclkr = mcasp_ahclkx;9 ?4 X2 n; o+ o* V# B
assign axr1 = axr0;
; g+ u0 p2 S4 {- D" \* z$ U9 K6 p7 P- p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, L9 d) h6 g! K" B8 l" J3 @* Fstatic void McASPI2SConfigure(void)5 P- ]/ F4 Q$ l
{
# L/ a0 `2 m; `5 FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 B% d A( t' q; }/ YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ [$ J5 U. w* r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# k% D0 e) Z9 [2 ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 ]% l3 B' G9 U7 NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 x! H% E8 N" K. ^MCASP_RX_MODE_DMA);
! ?( \7 M- }5 `1 G# l0 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 ?, |2 R8 k* Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ |9 x8 Z5 ]1 G+ L. M/ V+ g: f% ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% M. B8 f- Z. j3 ?' O oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, a* a* L7 U$ p" f. n7 z0 H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 |$ B4 g# i9 b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// \$ S. L! K# ?2 [% ]8 [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- U; c, {) J! ?; N, iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & d! W( M6 Y+ G. l1 J/ S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. \9 _1 \2 e5 |6 y) m/ L8 q+ @0x00, 0xFF); /* configure the clock for transmitter */" I e* F9 [( q j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); a, O5 ^7 I1 ?0 Q8 B+ x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - ^; j p. B6 F3 t/ [' H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- Y: c* m( y' r- Y9 @: T) }, V6 k0x00, 0xFF);0 b6 A* A2 _ o* L0 X5 ^# F
" B5 F7 ]1 P. }' \( `8 w0 ]/* Enable synchronization of RX and TX sections */ 2 U. f6 ]0 Z5 a( w# H% |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
[3 g8 B8 W8 B2 y# g" OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 I0 R1 ]/ g: s, d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 o) z; D8 \9 k2 }( Y8 X W** Set the serializers, Currently only one serializer is set as
- W$ L" `" \/ A8 N7 V# |# s** transmitter and one serializer as receiver.
: E( h/ b7 |% n1 [*/3 A3 g" p! b; w, k7 w, l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( L, B" n2 e4 H, n, A0 Y8 d! b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& M" u- O( t% f. b% T4 f
** Configure the McASP pins - V; P Q5 O- f. u/ R, K
** Input - Frame Sync, Clock and Serializer Rx/ o t% {1 X$ Y) {
** Output - Serializer Tx is connected to the input of the codec 1 z% z/ f2 w, @ k2 k. o7 G
*/
6 E( F4 Y& f+ A3 F3 Q$ i8 c4 i& @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 U4 I* V) B' L0 S' x# i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 ~4 E( e" Z% JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: b. e3 c& b# J5 p, A| MCASP_PIN_ACLKX
4 @5 J& M) M& W, _7 h9 J| MCASP_PIN_AHCLKX
- M% \+ S5 K& |, p% `& S9 B& Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, S) t' Y1 v" l; X9 H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - _" _, V# j4 E! ~: C
| MCASP_TX_CLKFAIL 8 U2 N1 Q9 p% R8 g
| MCASP_TX_SYNCERROR
3 O/ e1 Z. ?, S$ C1 I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ U9 Q+ U# y' }2 _| MCASP_RX_CLKFAIL- Q1 e/ N) x' B p4 r
| MCASP_RX_SYNCERROR
1 K) W0 {! n E4 N1 v, n. d, A| MCASP_RX_OVERRUN);
; @, V3 X) f, i} static void I2SDataTxRxActivate(void)
0 ~! o& J5 h ?{. S* b3 g1 A+ J* h7 s1 @
/* Start the clocks */6 P* Y i- `4 h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# @% R, j9 G: D, j" h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, ~* K& ~7 N' p. n6 c! H2 H7 f6 P: KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ q, l) `, C3 S' S/ y4 I. Z2 LEDMA3_TRIG_MODE_EVENT);+ |. s) l# I8 D( P8 a1 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' Z9 ?+ d% ^" H: K3 ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ u! `4 V/ c& k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 G+ F) G1 B2 f) r3 R/ j* M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- L* m5 K/ M3 I7 t5 j: R! uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 c5 W& ~0 x( k) _' MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& w" }# [2 k9 ]2 c* s4 o* L& Y; w$ Y Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! d) ]- ` b3 C9 H ^" w
}
$ u1 |4 D* |' R6 d/ X" V* }8 K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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