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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, f" c! j( X/ K9 T# e0 [2 j6 J0 hinput mcasp_ahclkx,
% B- X7 s) E. b4 v& l2 f+ Yinput mcasp_aclkx,
6 R) k) l3 {1 Q( Q$ k Minput axr0,$ j' \3 B5 }5 d/ |' D* T$ L. t
" k1 m5 V! f" ]& Routput mcasp_afsr,1 q4 U Z! D7 O+ A9 [
output mcasp_ahclkr,2 D) h' g+ u; p2 M) _
output mcasp_aclkr,0 g# m# {. w/ P
output axr1,
+ t' Y2 ^2 m# ~ assign mcasp_afsr = mcasp_afsx;& p2 z: }3 M$ i* s. N. G; ~
assign mcasp_aclkr = mcasp_aclkx;
% g; i" p: F2 M' passign mcasp_ahclkr = mcasp_ahclkx;6 B9 r- z C2 f1 e4 H' O' ^
assign axr1 = axr0; 9 B0 ~1 A. x- S; I7 L7 i5 B% Q
7 P, \2 I1 m5 R5 L; c( \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 V, x4 K0 O9 Z; Cstatic void McASPI2SConfigure(void)7 ~- u- A5 b% p0 j6 y. \( N
{- O! W, j8 q2 ]& J+ Y" \" _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ c( b- M0 D- B5 }* r# IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' B# J# P3 a& c: V Z$ v$ @; F* I& {* n+ y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' R- s: {6 K, _ c4 N0 xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 c; g$ {3 p, c9 P& X9 V7 P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 E. X7 {% q/ C) R. R. ~
MCASP_RX_MODE_DMA);
9 X2 o; v/ _( ^# [1 o9 R7 ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ P. e# I% G/ k5 V" e( i; n; F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' G3 Y; B" `: n: I7 ]' O: ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 G: _& g# ~* l& C! w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% Q* a+ b, w& x4 P/ [5 X2 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( D& U* B- a( ~9 u" R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: G+ p7 `( K5 q+ N+ Z- n! uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 P# S6 z: z. m+ J) L6 n8 PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) N9 }) ^6 h9 |: B% r5 B8 C4 k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! v; Y, v$ C- H, n% z. q) ~
0x00, 0xFF); /* configure the clock for transmitter */
9 T; k3 W) w" O7 G* gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ z& u5 o- A, `6 K. g7 B# @3 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 U5 D+ ~9 D% b+ v/ ^, w' H1 f) IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 f1 b( Y9 ?- y0x00, 0xFF);6 d! W8 t$ F# {# P4 u3 e* v
" l) J/ [- Y: _/ m8 |6 F- N" J; }/* Enable synchronization of RX and TX sections */
5 I1 w# ~& c% z; W6 h. rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* | @' ~8 D+ O% b+ j' @3 p3 KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' f6 a9 L* P F" P- }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" |5 {/ g+ I. ?! l. D* l
** Set the serializers, Currently only one serializer is set as
( w% \: X9 q* t7 t, o** transmitter and one serializer as receiver.
/ d! Y- q! @7 ^# I*/7 V/ f4 n% h2 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: K7 F; u7 }( [1 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' W9 p2 F" a+ u% Z** Configure the McASP pins
7 l: T7 [. ]* A2 b** Input - Frame Sync, Clock and Serializer Rx
$ f& J/ z7 T6 o9 [0 t* ~9 I8 _: o% m+ u** Output - Serializer Tx is connected to the input of the codec
0 u7 J$ T- z) T; r% v*/* d) Z4 V; t* L) @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 T! M3 Z/ ?/ o, u, X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; K+ x/ U7 B% w# J1 ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 N8 B z. ~5 T3 N N
| MCASP_PIN_ACLKX; J4 G) y2 F0 q0 j, J' ^% K5 Z* e
| MCASP_PIN_AHCLKX
3 `0 N+ ^ b# G" E- x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 L6 E6 O3 [& g0 z- `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 Y$ a# t; f2 B+ m8 W- V
| MCASP_TX_CLKFAIL : ]0 o0 ?" i% A+ m5 H
| MCASP_TX_SYNCERROR8 U" M" r- V$ O0 n' d N. C O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % n2 ^& p p0 u5 z8 f% s
| MCASP_RX_CLKFAIL
# v3 Y" Q, ?+ U3 H; a| MCASP_RX_SYNCERROR
3 x2 B% w4 w2 T$ S| MCASP_RX_OVERRUN);8 j( ?% I0 g" A0 e7 Z3 L
} static void I2SDataTxRxActivate(void)
; Y4 c P( Z8 o% B' D6 b6 h{
' m. c: |1 }; J/* Start the clocks */
: T9 f1 F3 G3 n) Q; C% Z' E6 R, FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 Y8 H% m0 e# H4 N" q* L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 u! G* S* g* a% t- UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 A6 g6 M4 C( B* e
EDMA3_TRIG_MODE_EVENT);
: e. }, C# k3 B, {; ~5 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 Y; R) t, u0 x1 U. \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 g4 p' D' D+ F: Z$ z+ C! m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 [% h9 @* J! d2 D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ R( |- F, V7 {* J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. U* t" q7 [, h, \4 \! ^( f. P/ j! EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# f1 `& _0 m$ a2 K! [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" X! e w3 L; S8 R1 D% A; C}
! {6 ?# d' }" S- u6 Y. N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 N) {% c2 Q% D* g! r, y' `6 ]
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