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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, M! F7 w% E* f* \: _
input mcasp_ahclkx,: d# a5 D# l% c1 n9 L/ V$ ^+ U, P
input mcasp_aclkx,
0 X& V+ K7 z4 [ E3 b, Finput axr0,
; _1 ?% P: i, m* z4 }8 o, k2 ]
( L; \6 s$ a7 ^6 S5 Q9 `output mcasp_afsr,* ?, P v8 p% d+ c6 z
output mcasp_ahclkr,& R# @, z/ x- m ^2 N
output mcasp_aclkr,4 c& X, m7 _3 l7 R1 }
output axr1,+ c5 ~4 T3 ]& V" _0 t
assign mcasp_afsr = mcasp_afsx;; l. x& u7 }( r- P( F
assign mcasp_aclkr = mcasp_aclkx;
: B6 _2 X/ e0 M) _1 kassign mcasp_ahclkr = mcasp_ahclkx;& q% ?. _8 _1 C$ ~) m h. L
assign axr1 = axr0; $ Y9 k# l* y' g
1 B; }0 I3 L6 E2 S1 @, v$ F+ S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 |! ?; u, Q% h. E9 }0 s
static void McASPI2SConfigure(void)/ ~ I( H% O' N$ l- p) O. f
{
% M! {: o6 @" C" ~; ^& {' ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 I8 K- T8 d4 cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. s- r, X1 x( w# w9 w3 JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* d0 l/ c8 E3 U- b, H9 C: ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 g7 |4 }9 n+ A) x1 ~- a* b. \7 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ z" q* f# I2 E1 M7 f) \MCASP_RX_MODE_DMA);
2 V6 u, G7 ]' F/ C/ w# |* m6 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. z7 v$ W- J6 f6 b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 V5 d8 i1 T. h* v, FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 s1 J9 y9 t2 w, x% c; }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 w; ^: o' Z# l- X3 F- H+ h( A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - h6 F4 M4 c& a Y! Q6 W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 m4 d. e' q( n1 y$ l6 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; `4 {2 y- \) {, z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & F) T% C, Z3 m! b/ E" }, K, B' x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 N: g: r6 m: N0x00, 0xFF); /* configure the clock for transmitter */
: f8 Z* m5 @1 G8 fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ A* ~ O" U: _3 P+ v+ d p( e' MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! P( ~3 o( } M8 ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' w9 g: l* h! n! H% h+ @1 f
0x00, 0xFF);4 k8 f+ ?( {7 I$ I2 T! f
6 [$ Y) C) e, v/* Enable synchronization of RX and TX sections */ - Q Z, _* P4 c6 e: C3 V$ `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' l/ _7 b, j* h* `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 P' ~) k g- \$ _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 O* x5 @$ f# v8 U& h; _' W
** Set the serializers, Currently only one serializer is set as- g |& u4 R/ K h7 S
** transmitter and one serializer as receiver.
9 ]- w8 X2 U4 F! y, v3 a( W" M*/+ m) N( ?) Y- o0 `1 {, R q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) u( u5 Z9 K9 A: ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 ?. y- h: U, z) e' f, p* N1 ]** Configure the McASP pins
, L8 g5 p0 h% N8 `" f** Input - Frame Sync, Clock and Serializer Rx
; E) e1 v+ f1 N5 E; \** Output - Serializer Tx is connected to the input of the codec ; Y! w5 `8 l/ | ?
*/
' c' |- Y$ o; |$ O, r m1 wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; R j1 o' |9 z4 ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 l! d2 u+ k( v: o0 s& x2 Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 [. z* s$ s; S; y) I* g| MCASP_PIN_ACLKX, o' l' r% l/ V3 J- C8 x
| MCASP_PIN_AHCLKX
7 ~/ F) T9 w v5 j4 x5 r8 b. e! |! L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ P3 y+ z4 l! V2 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " Q m- ^6 d4 e& Q" s
| MCASP_TX_CLKFAIL
- x7 H- ?1 ^) |3 U5 v: W4 T| MCASP_TX_SYNCERROR
6 B8 @4 `) r# F, I4 H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! M# u8 I! `8 x6 N: |
| MCASP_RX_CLKFAIL
- X5 _$ p8 y* @4 k6 M+ t| MCASP_RX_SYNCERROR 7 Y, |; ~1 b* s6 N& P' Q( Z
| MCASP_RX_OVERRUN);
' D: `9 W1 i' I. E, z} static void I2SDataTxRxActivate(void)
" r" @2 I F6 Y [7 L& j" J{
3 D6 l8 W K, L/* Start the clocks */2 N4 k* V9 _/ p4 e0 p/ h( s+ ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ _- E7 g" m$ l$ t m% ^5 H( f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! y1 ^ ^ N* ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! B4 I, b8 J8 L* ], a1 ]EDMA3_TRIG_MODE_EVENT);7 t7 m# a$ F! f) p2 K* K: v/ e# |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 L5 O# R+ t$ U, s$ a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% ?" D& z3 Q: R6 V$ K5 r' X2 J$ d0 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ B ^9 d5 m) E8 g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. M* D8 k4 e( g9 n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 ~5 `7 {/ q+ ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 o! N" m0 P! z. W2 Y) z3 S- jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 \7 S/ ^1 }; [7 y& J1 Y}
3 Y* }% K6 U7 t S u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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