MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
$ {$ z0 X/ {0 n' t$ c0 [  _3 ?input mcasp_aclkx,
0 [* l5 G, S1 X2 A1 Finput axr0,
8 l3 m( _! O9 o1 q1 m
7 a6 q- F. ]0 Soutput mcasp_afsr,
6 F  y2 `* @0 ]output mcasp_ahclkr,
0 {+ f8 H0 j3 |) C. qoutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
5 ^, K- ~2 H% Y2 f4 N  `  ]6 i+ nassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

7 h( z! h" C; p: `) m2 e
6 ^6 R+ w$ Y0 F% y: q7 }4 R- m

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
( y: Y5 ]9 w0 `" PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! s! e! F+ Q3 K5 bMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, ~7 B3 h4 C$ X, s" \% H" E6 U, L$ oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, \; o6 O( f( v  d+ A  o, r5 O, BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 v. ]' \9 g6 y9 R7 ~! _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
0 U0 c1 I# \% V6 @: n% ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* X" _' ^+ u5 P2 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
/ A5 o/ V% k  j1 i" k
0 b0 C0 q- @! f  I3 }/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
! m% H  {: `9 q' G; ]- q% R5 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
4 A: ~, ^- E! l& c8 K# x0 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
3 J% P# z. d7 z+ o: T. N! @8 J2 ~' Z** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
8 F* Q8 x2 e8 [** Output - Serializer Tx is connected to the input of the codec
*/
$ b1 e9 I9 M7 VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 T: w; A" d3 _! ~+ aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' Z3 _* o8 {: J( ^* t+ }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
6 L& l1 i; B* y| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
* \' [# j8 P% s4 O, nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
+ R0 K5 [# F7 N8 \  v* n; p  z| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
& Q# w% N( O, e( B) H| MCASP_RX_SYNCERROR
) B7 \0 D$ }$ y* I8 ~  F| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
% Q' p. t. q3 }7 x9 U{
1 T9 C* J: M6 [" g! C2 ~/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 a5 m, O9 u/ mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
5 y5 H9 v* ?# C. iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
0 i0 G4 X1 r6 r$ _9 K0 n) DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
) r( O8 Z$ d7 D0 ]. ^  xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% e) o# C% q: [" _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
& Z) v  p( ]9 y' X6 y6 i  w8 _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

' I' ]) d5 y- _$ R; J