|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 n$ V: M; d7 I4 g( Y" J3 o" cinput mcasp_ahclkx,
! ^% d9 v8 Y+ \input mcasp_aclkx,
9 R7 v. F% F4 G% `0 `$ tinput axr0,
- d0 m' Y) _1 ^" J' Z$ V3 q
S9 z- h8 m* C$ c( Foutput mcasp_afsr,
" k% f1 f! U* S" U+ g, @' t& Voutput mcasp_ahclkr,+ W, o/ M. a4 B0 x1 k
output mcasp_aclkr,
% T& C2 L2 ?, r! _1 L( [output axr1,
: w. N3 s8 Z4 W5 O7 ^3 {) M assign mcasp_afsr = mcasp_afsx;
# b$ J( D2 B& M: X1 w* U4 H3 massign mcasp_aclkr = mcasp_aclkx;' U* J+ d0 K7 Y8 o# d
assign mcasp_ahclkr = mcasp_ahclkx;
X; @0 a0 }' q- Cassign axr1 = axr0;
8 j, Q) Z- {/ S" n3 D6 L1 s6 K) c' H9 H# X0 G7 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * p+ G+ E7 `. ^
static void McASPI2SConfigure(void)
5 e4 V0 |7 \6 v4 i{
9 a* |% b( b0 [. K3 qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* ~: b4 @. t/ J$ H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 U p% k1 n! A& a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# K& r+ x( }! W, c& Z* t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 F+ I: E, U: H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 b" v% a7 C r, O
MCASP_RX_MODE_DMA);/ r c7 r5 R/ \' t+ [3 _* Y4 \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( |: B# R1 P+ f C# _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, G" t" ?6 [" a2 NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: p$ v9 E) u9 s' k5 S9 u, E% kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 Q" ]+ p9 S; O5 e- M5 Y. X" R6 |& QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , w8 @, M9 z! G( p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ K3 t9 L [1 F( BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
v. h, G( |5 I! J, ~+ @2 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 _' B q5 V+ {, f# l8 z6 o+ o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, ^9 v" Q/ O2 d- E* E9 k0x00, 0xFF); /* configure the clock for transmitter */
$ G4 i: c, D, }: G7 G: HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: B" q C0 m" \+ j) {6 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( Z2 M8 M# [4 d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 W9 r/ o0 d* R0 U5 w3 s0x00, 0xFF);! B/ i3 }1 N6 ?8 Y7 ^) u
. k- L: O7 o0 g1 p' V, @/ W% }/* Enable synchronization of RX and TX sections */
; d# @$ T9 y" S* q2 kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% r4 n- {# |8 N M; }# qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' I* L5 g. \- |5 ]6 J! l- UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: O5 H- g$ U- b6 ]* k2 e. v
** Set the serializers, Currently only one serializer is set as
& O; k4 z* T; N) I4 W9 n' F** transmitter and one serializer as receiver.+ x4 |8 N, V( F" b) s7 p
*/2 s0 j# v" y2 N# Z+ U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 O) s9 K4 V$ M# }: }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ ]. [7 r( f7 x** Configure the McASP pins
& {( X/ o1 o, w- ]0 W: ~** Input - Frame Sync, Clock and Serializer Rx
9 P6 |! _5 d( p$ i+ E** Output - Serializer Tx is connected to the input of the codec
0 | J: j m; x% _! |*/- f' `1 Y/ I7 \3 R, W/ i; T, X4 j+ F" o+ x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ g# g& k! i" ~3 O, G1 d) T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 r8 s6 {5 C% K8 {) O. XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 F! F9 W# P, B& R| MCASP_PIN_ACLKX
' `: C; K5 r% b| MCASP_PIN_AHCLKX
! @; ~5 h0 h5 u: F# B- ?0 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ p6 V0 _; y" Y3 P: w" qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 c8 U! C. @- f) f* {0 [| MCASP_TX_CLKFAIL # q: K( V2 l6 c
| MCASP_TX_SYNCERROR
7 e: C4 m3 p2 j" E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * A8 ?# C" Q& h# l" J# ~' f
| MCASP_RX_CLKFAIL
' q b8 J& Z6 B8 S; g1 m| MCASP_RX_SYNCERROR
% _2 u7 u5 G' U9 E! Z| MCASP_RX_OVERRUN);8 P' i; b; i. [% k3 r; F
} static void I2SDataTxRxActivate(void)$ A9 W- U! {5 o% q0 [
{
: Y3 [3 M7 h" U$ t/* Start the clocks */
9 i0 i9 D, X7 C+ m3 O3 oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 v6 p4 M0 k$ d6 U+ X- ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& L+ t+ F* P! C' j( |: o7 h3 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 }4 [& A/ x- D/ a
EDMA3_TRIG_MODE_EVENT);
: H0 y; Z, w; f1 s5 J# HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ S" f' g, u9 m1 q K1 B+ J3 J N3 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) @- W' k1 [3 @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 _' d6 H8 p1 w* D: f0 u3 AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! s; e' x6 n2 i7 }. D' Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 B9 A8 c5 s* X5 m. d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 L( m& g5 G2 f+ S5 N5 q0 G; C2 F! IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. j# U: N9 c* I7 V/ l0 x& A. n
} 0 S' Q2 S3 }% R) k7 s6 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + X2 M* }# @% x* {0 A0 u+ a
|