|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 i6 j7 A5 u* o ?+ _( Ginput mcasp_ahclkx,
" Z0 t6 ^2 u. m' E# Z0 l' |input mcasp_aclkx,3 x8 M6 X. z! a" G3 j# p
input axr0,
" A' a# }3 x7 g# c2 y* z) V( w$ x+ R" t' k, |+ a
output mcasp_afsr,$ s! V2 `2 Z" F y p' P1 d
output mcasp_ahclkr,) Z' [3 ]( s" N/ Y! T, k. Z$ A5 P
output mcasp_aclkr,
$ F1 `# U, m" K6 Soutput axr1,2 Q: L- V% A6 M6 a- ~' o/ w
assign mcasp_afsr = mcasp_afsx;* ~& {. _0 S& ^( F$ D
assign mcasp_aclkr = mcasp_aclkx;, S1 _4 [6 L ^1 w1 _; z, Z
assign mcasp_ahclkr = mcasp_ahclkx;
, s9 G/ W: E. k# ^assign axr1 = axr0; : x2 p; ?3 R$ |4 E; P
& a H- _1 z! w# N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # Y1 U7 x1 b+ m2 x1 }3 K
static void McASPI2SConfigure(void)' [( c1 B) v4 ? {, g2 c
{9 u1 _, \8 a; ^$ P/ r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 ?+ n' |) N tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 @3 d' I$ a, Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ }' i( K6 T# s/ f1 c* r* i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: ~6 q t7 h- i7 V- d ]6 L" m( hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 Q4 S$ b& l' s+ {) z8 \) J
MCASP_RX_MODE_DMA);
/ w; d' R4 n @! o. y/ h+ ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; ~& V8 b# [5 `) R1 [: }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 N* t' G1 q! I$ x" F) c, oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 Y, C5 p3 F) Q' \0 i9 v1 n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, T: G, U# U. v" {/ pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# }- z8 Z3 I2 u1 r; vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 k6 w/ M& u+ Y$ {. H0 E( l1 }2 Z! D3 k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" U8 ^) r. F8 VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 a/ O1 r, w- a& s4 |8 aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ J6 d( ~, @& {. Y: S0 c4 _# `0x00, 0xFF); /* configure the clock for transmitter */
, O6 b4 z, x9 e4 |" VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' H1 p0 W, t' e/ qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; ~5 E4 ?+ j& O. O0 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" _: l/ Q2 c T7 j7 ~1 n# V0x00, 0xFF);! p$ X; c2 t! f! X4 F
" \9 X9 n2 ~2 m8 z6 w3 c/* Enable synchronization of RX and TX sections */ 7 ~ ^. y! N7 Z4 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 j$ y+ Q0 w, S, N& p! I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 k2 w p# \+ HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 C6 r; s0 L" S** Set the serializers, Currently only one serializer is set as3 K0 c" N$ j% X2 `
** transmitter and one serializer as receiver.: b6 J/ S4 @+ G! W" X0 e/ P1 U6 w* _
*/
* p! G) H6 o; K2 J$ DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. m4 o: w- `1 y3 T* j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 C# ~% h, g2 z** Configure the McASP pins : ?! T' p) J; m' D9 K5 F7 [
** Input - Frame Sync, Clock and Serializer Rx
. n& y7 o. J& Q6 T** Output - Serializer Tx is connected to the input of the codec 2 \& B' u" A+ {* |! T
*/! D6 q, u; z6 k/ l+ ]1 ?/ n% F" X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* z R4 \ l, u4 H ?$ uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: h% Z0 {* n/ ?4 v$ v: uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& _/ r* O. C# C, d: Y" Q& l7 o7 Q6 H
| MCASP_PIN_ACLKX
4 y& n, i" m2 \3 [" M4 S| MCASP_PIN_AHCLKX
) p: z' Q6 Z' z2 V4 R/ p3 K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' \6 t2 R. h" [' [/ k6 E( U9 Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * O S# U' I% R- `, U6 p
| MCASP_TX_CLKFAIL : d9 g4 _) d. M- h
| MCASP_TX_SYNCERROR0 X2 X" F3 a1 U( \ U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % w7 N& u2 p" [7 b# F
| MCASP_RX_CLKFAIL: G# \5 v2 o- Q1 ^$ `8 p
| MCASP_RX_SYNCERROR * V1 |, P7 H1 v- v5 O9 M
| MCASP_RX_OVERRUN);. Q6 \# f6 A% I. ]
} static void I2SDataTxRxActivate(void)4 D/ D: z* m8 M1 n& n. k
{
" K# h$ H H% E7 {6 S/* Start the clocks */$ h) Z* s. a$ N) D; r& q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); _4 K5 p' B7 r; M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* p* c! t! K$ h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% i$ ]6 H' `6 q0 X p
EDMA3_TRIG_MODE_EVENT);
/ t% U% P. A) h3 pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" x8 T: L6 C6 ?0 eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- U* C& j4 ]/ ?# hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 S6 e7 [6 b; ^! g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; y7 c/ m n& r: n) |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% k# d5 o/ g+ J& b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ @" I/ v0 Q- t( Q) T2 ]. [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* o, Z( s! r* k, Z1 P& E9 {}
$ z. r( u" p) m# L: C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
9 ?& [8 a; m; a3 x0 b |