|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' q; L* U& H, K/ l- U. g, \input mcasp_ahclkx,
k2 a* ]6 a/ v4 y4 N7 Winput mcasp_aclkx,2 B+ Y7 z: Z% k2 B4 F; w O- h
input axr0,) j; _' Q% s3 D% X
q0 Q" F$ \, a' q& youtput mcasp_afsr,: W) f# R8 r/ N. g8 r: t8 V; x
output mcasp_ahclkr,+ s+ Z" y) a4 X# M, H2 Q8 {" L
output mcasp_aclkr,
& ]- T) Z% Q* _output axr1,: m4 L% y: I! n; ]. O( Q
assign mcasp_afsr = mcasp_afsx;6 n, T9 U8 c: N* x* n, j; _
assign mcasp_aclkr = mcasp_aclkx;
" Q* ~' L" u3 |9 [1 \assign mcasp_ahclkr = mcasp_ahclkx;! w- o5 h9 M L# O, P: ]
assign axr1 = axr0; - E& A& s! b8 R4 w0 M3 g
5 @; Y r) U Z) ~4 o& M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 I" [9 y& l0 D1 C4 u
static void McASPI2SConfigure(void)& h2 U+ Z% \8 j
{5 |7 \! H: C1 `5 B7 D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 G6 x* ?+ \ y" D( Q: P. I0 uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, i7 g H& C( S* y% sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 c1 ?- \6 D; s7 b: _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- c) [# R7 y1 y5 s; g* WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ `; d6 b! P G/ p2 N, Z
MCASP_RX_MODE_DMA);
8 a, t- _; q1 o9 `% K r0 u" KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* T0 k: M* i! h( k) }$ GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" [; ]7 h2 g% N4 D# SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; X& Y- w4 a9 z1 P$ F& a! w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- n" W' S8 \3 ~6 G [3 uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
v. ~) g) S6 s/ `0 HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 j* g' f, @, e, A1 h* t2 K. ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 |+ ~3 j! [1 }5 Z) Z" ^7 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- ^6 E \! S* D! X" f1 hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 B& J- @4 h8 c7 Y* C. I& T3 D( l
0x00, 0xFF); /* configure the clock for transmitter */
2 y& _+ L8 I# ]+ \- _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, B: P/ z* U/ v; f, e2 Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' X1 F: c& w, }- ?8 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 B. N3 }& M7 N2 a
0x00, 0xFF);, W5 X* q$ q6 J- F0 m
W/ B) |' N ?* U
/* Enable synchronization of RX and TX sections */ 2 M- N7 Y3 f( L4 ]. _8 M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 z$ U2 }, L( D& n3 r$ w7 _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 b2 q* w$ T5 p5 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 r' |9 U7 M8 d/ J$ B, `, E
** Set the serializers, Currently only one serializer is set as% n3 l8 K i x+ ^ T @5 P
** transmitter and one serializer as receiver.6 b5 W' W1 R9 S
*/# X" R2 A3 f v# q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 W) _& @, w0 k- n% z. k6 Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 ^6 o B, b% S6 @0 R
** Configure the McASP pins
5 a" G0 ^& S) Y1 ^9 h# ~** Input - Frame Sync, Clock and Serializer Rx
; V) v& J- h3 h- B ?7 v5 Z% ?5 O** Output - Serializer Tx is connected to the input of the codec
. B. Y# e; g3 v*/
G. _) w* j' v1 y$ m0 j, @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; |# g; u: N4 ?# `5 D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 F# n/ q2 X& B; K" q6 tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ q X0 ~+ b' @3 A
| MCASP_PIN_ACLKX
% ^- g- z( }$ a5 z) C! h! v7 u( P| MCASP_PIN_AHCLKX. u' d0 \/ y7 `+ q% e& p- E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# B9 L/ u5 E$ f5 ?! z+ H# c! eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # V& |' j6 |7 @' g: P$ e ?4 \
| MCASP_TX_CLKFAIL / {: T" Z$ f- |1 S. a" S
| MCASP_TX_SYNCERROR% [9 B$ |* ^8 ^- Y; O! {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + d: N1 f# x- X5 J' L
| MCASP_RX_CLKFAIL% i. G# _- I M/ W
| MCASP_RX_SYNCERROR 3 Y) K1 g* A; _1 d
| MCASP_RX_OVERRUN);# M. v7 Q* s) v$ K/ n
} static void I2SDataTxRxActivate(void)
6 q) w: ~2 h- N{/ u' Q8 s$ r+ j8 b
/* Start the clocks */- q4 Q A7 \& h7 s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& D/ _2 b4 i8 I$ z4 |7 w# J( M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( ^" k, E. T# L" U3 t. \/ }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 I6 C' f5 O6 m0 b" Q/ \
EDMA3_TRIG_MODE_EVENT);
8 m8 l2 R: K7 K9 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . O, y1 G. J3 o3 r, H" ?1 `3 y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 S. I/ c2 ]- V9 _% t, UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 J+ e% \ Z! k% w7 V4 |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 `+ a0 p/ F0 E+ K& V" Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 M4 F& p; A( p1 |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 o5 B8 f8 `9 A$ ?8 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' g7 M$ e: v" X} . `- J7 E0 z& K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 ?0 g$ D( N1 c4 y7 G2 M* {
|