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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 {. D H- ?4 W' {" ?input mcasp_ahclkx,$ x! ~/ w. c F
input mcasp_aclkx,6 F$ `/ F" ~- x$ e4 E* X
input axr0,: G; L# G0 e; G! z& L; ~' e
1 V# z6 \7 d; Y" V9 P5 @$ f4 O
output mcasp_afsr,' Z. i7 _# M6 ?* w
output mcasp_ahclkr,
; H) f: h5 K( M8 L4 Youtput mcasp_aclkr,1 e5 G$ E9 k& n* i' }
output axr1, ?7 w$ u% T" U h& ^1 p- f
assign mcasp_afsr = mcasp_afsx;2 K3 b. O, m3 |
assign mcasp_aclkr = mcasp_aclkx;
/ e4 _( f' f9 P- s, p! W! Q6 aassign mcasp_ahclkr = mcasp_ahclkx;& z$ s& q f) ^+ f1 @
assign axr1 = axr0; 1 \$ d; u) J/ q1 t* \
9 W$ x( P9 D8 B% D' f- y% {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : ?! s7 a$ W" o9 n
static void McASPI2SConfigure(void)
" f; h3 |& I8 Y{
) r: E0 ~, _5 vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' q+ @# S. ^/ W! B5 j9 f0 FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# d- ]5 m. V' V& \4 W( A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' r: {1 H& P+ w" C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 r- G6 R& j8 o `7 h$ X+ e, nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 E" E# b8 ~* T" I
MCASP_RX_MODE_DMA);
. f1 ~* E9 F" |+ x& j3 H% pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 y$ W; ~2 X( Q& ]# j& R, z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. ?* d8 L( t8 y% x* A H( P: A" V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 f5 e& Y3 i3 I8 ]. `* C" w7 KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( x8 w( x! I2 d! d; d3 U8 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 r( ~* d) \3 i% b+ Z% mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 ?4 W% @( E$ O J0 [1 `0 _1 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: n- C/ G, \! B5 \! tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
K& X; f+ ~' q3 C6 XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 Y) j0 ?4 Z+ H. m& Y2 O7 Z% `. M0x00, 0xFF); /* configure the clock for transmitter */
* J( f8 u( e. D7 J. e; {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 S; p( ?# X6 n' f# x1 p2 c* G: k! [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / S/ ]3 p: {% Z' D! q( I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: ?$ { }" `$ W9 _$ @7 {, m( R
0x00, 0xFF);
" m% m* s! t8 N* C/ ]. k3 f- O R6 y
/* Enable synchronization of RX and TX sections */
! o0 E, I, c( _2 L0 {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 L$ }' z' X" R+ u! b% j" `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 p* o4 s% Q5 |9 `$ LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ u) Z( W, c5 `** Set the serializers, Currently only one serializer is set as3 E! h; w* c0 Y/ I( z
** transmitter and one serializer as receiver.; I+ X- c( L: v: p
*/: q% a* ^. ^- ]# Y! g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 t( M( i2 d4 J0 y) [* l+ \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 h/ Z" {2 n# }) {* `( p% s** Configure the McASP pins " d; w- ` m& ^& p2 Q7 W0 W" C$ ^
** Input - Frame Sync, Clock and Serializer Rx
- y$ `8 R2 v+ V. g** Output - Serializer Tx is connected to the input of the codec
7 t. F* @" W, W6 W' T/ ] x8 Z*/
, I( r% `( n- g1 U; tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% ~ w, b2 t6 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 ~) l2 d: h1 k& |' w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! l; j: B3 ~# u G$ A) e g| MCASP_PIN_ACLKX! {1 ~4 ]2 L0 h' n1 r
| MCASP_PIN_AHCLKX
7 E- B4 Z K! N: k. v, \- i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 z$ z' Z; p9 ^% X2 L ]% k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ]$ M' e8 Z. F' R2 A" I
| MCASP_TX_CLKFAIL
$ _. x1 e2 g+ l- C: A# e4 W+ T| MCASP_TX_SYNCERROR& w- g& B5 B* ~3 }9 J- v( B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ U3 [+ |! J+ L1 k: j0 ?9 q" J| MCASP_RX_CLKFAIL1 z/ Q1 S2 y5 U, E6 l
| MCASP_RX_SYNCERROR / u& f: Y5 ?& i+ a s/ M- y" Q
| MCASP_RX_OVERRUN);9 [! W+ e: F7 N7 w5 i! s
} static void I2SDataTxRxActivate(void); z7 d% p( k& [0 P" S) c2 w( {
{
+ R# W1 J) U _' Z* A! F7 d/* Start the clocks */8 i: |2 K& W% d: j6 D5 c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' I+ Q- ~0 S2 L. Y) }- I6 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 C2 a5 m8 X6 U, fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 a: P) I9 k8 ?2 z+ Y7 w
EDMA3_TRIG_MODE_EVENT);
: g8 n/ g7 V; e# H$ s3 c( bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! Z1 U) I* O! r; j( s# I0 gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 N; }% S, Q* E3 nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) J+ O( e# F, @5 T) [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! ]& w$ S" c, x6 ?% c, ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' X& m* m7 S" D' d5 t, Q% o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# L- J. y( B+ q% `9 MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' w- v9 d1 y5 j1 u} ' V, [6 l! ?4 Y6 C" L( G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 Z6 y: P/ T) M) G q2 D- e1 k5 r. Y
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