我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 j$ S7 `$ \& D" [4 G
input mcasp_ahclkx,
, M7 A" E- {6 B( @input mcasp_aclkx,
5 ?3 D5 t5 c2 `2 C, L9 v, o tinput axr0,7 E, r: ~7 S2 `8 r$ k
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output mcasp_afsr,
, H/ H8 [, Q6 m; p( j% coutput mcasp_ahclkr,. N8 e# U7 \" y; N6 X# K
output mcasp_aclkr,: X) n( Z4 l8 M: S* f; l! V
output axr1,
' v5 u4 t$ [" T$ d9 ~0 A- w assign mcasp_afsr = mcasp_afsx;- P% G8 q5 W- c0 O
assign mcasp_aclkr = mcasp_aclkx;, Y5 N6 E7 X; f: r$ P! n
assign mcasp_ahclkr = mcasp_ahclkx;7 M/ ~+ U) b( I' _. G; x
assign axr1 = axr0; 4 a0 B: |/ J+ J; T
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' i. n% |2 x1 O5 N
static void McASPI2SConfigure(void) v/ c- R* `' l- m9 S7 Z% ^
{
+ s; z) j9 g1 m5 FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 l4 Z2 N$ Z. R; j4 w/ MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 b; u- }+ E6 v/ R- U+ n, B3 fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
m. b9 u6 y& G/ U9 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# x0 M9 ~' ~9 D5 Y7 Y; r7 h1 V8 r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ j0 ?* D% x5 F( ZMCASP_RX_MODE_DMA);+ M; Y; W7 j" A# @2 X* Q0 Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ g+ f& {& b7 b! K: ^3 a$ J4 U( X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" |8 u. p/ ~& U1 Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 Q: }3 \2 f4 X5 E, Z4 U% j5 Q" g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 Q* m1 J1 r1 TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 v. ?# E) a+ zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 ]9 d7 N y0 q( C, p" H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# O3 ^7 Z! u, C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* H W5 B0 f* I: H: t0 lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 a7 Q! q* Q/ a7 ]# j$ g& g# y0x00, 0xFF); /* configure the clock for transmitter */* V" Y- j) R8 l4 W; n. j9 s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 ]& Q. a/ S5 k+ f) W- T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 F/ D+ D6 S. n5 m3 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* @4 ^* }3 F- s0 p1 T" M: [, V
0x00, 0xFF);" s* |# g% Y/ _5 @& Y* D ]2 `
% M9 O+ |% ^5 p+ X0 p7 ^
/* Enable synchronization of RX and TX sections */ / j6 m; c2 w7 K* e9 K' F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& z0 }. W2 i/ F( ~" r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 H6 c" m( w y) i" s7 O& t% v' P% x3 U( |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 c/ q3 c2 D! V8 l/ W' `
** Set the serializers, Currently only one serializer is set as& w2 ~* P. |( y
** transmitter and one serializer as receiver.
# z. V. [1 f0 H% ^. z4 X*/
* l" K9 p+ y! q/ T8 W: k( r/ UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. k: K5 P I! p+ `& F% U# Y# v$ H: XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( L+ I/ x- v4 Y** Configure the McASP pins
" o5 u9 X, _1 E' p/ t** Input - Frame Sync, Clock and Serializer Rx+ S3 e' Y$ ]* d/ S, _
** Output - Serializer Tx is connected to the input of the codec : Z4 m- ?" Q$ \! q8 U: Y& e2 p! s3 e# x" |
*/- \ q: |% v+ r% K' G0 y; B* }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ i' f$ F0 V x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% {) Y9 h( r1 F1 c0 _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' Q9 L+ S& w* \% T) S- O% z
| MCASP_PIN_ACLKX
: Z7 I, V `! Z& {" \$ v# t| MCASP_PIN_AHCLKX7 u5 U4 e8 X5 [3 j- T9 |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 @- ^8 u" i. ]+ K$ F' K, RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , p3 i" O0 P7 E v6 R, g; L K
| MCASP_TX_CLKFAIL
3 d1 x) H& V" A/ j| MCASP_TX_SYNCERROR, O% }2 n' R9 {+ D: s& P, M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : C5 T3 B" G: X+ N
| MCASP_RX_CLKFAIL- [, @+ X6 q& T8 ]2 f: x, _
| MCASP_RX_SYNCERROR 0 p ~% p9 [: `7 X/ y1 v/ u- p
| MCASP_RX_OVERRUN);
2 E L2 V% D- S} static void I2SDataTxRxActivate(void)0 b+ \( d# X- n# E- |' o
{
' n) U7 i! R' s# N g! y/* Start the clocks */6 B" b! o# b( t7 f9 b, d. F, p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; E) T" _0 d( L) x0 L( L- hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! q! G2 V4 d0 P$ Y- t% YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ I7 d: k* F5 I
EDMA3_TRIG_MODE_EVENT);" H! N% T. I0 x/ H( N0 Y. e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 S7 }7 K% L$ {/ P/ Y: k) w0 }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. E3 E7 g" Y. [& ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 H' b$ {6 L8 K0 M; |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 W1 E2 X7 _, ^4 q- z5 Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( g1 d2 U: |: _' Y# GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# n g) I8 a1 jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 P! W% G/ j4 F) {8 R+ s}
/ ?% k5 v6 Z) n9 s# o5 ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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