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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. I& g3 w% z7 `6 [
input mcasp_ahclkx,
1 y* p; ?0 o+ X5 f0 Y* j% r! xinput mcasp_aclkx,! b2 T) s8 C( }& i' a6 w
input axr0,
0 K3 q5 T9 S) p5 _( V; o' y- t( z$ N1 K. ~5 L. D: M4 ]5 C, q9 R* p
output mcasp_afsr,( A6 k/ m. K! y8 u4 T" v) h( y) f
output mcasp_ahclkr, B/ J" e2 s7 v6 I3 b) ^' O% H$ m2 i
output mcasp_aclkr,8 V" N! l% _7 q- e7 b0 ~% {
output axr1,1 W) P) M+ E0 v
assign mcasp_afsr = mcasp_afsx;/ e. }' x4 K4 t. T4 q1 X
assign mcasp_aclkr = mcasp_aclkx;6 ]6 D) D) X; X+ n) I; [3 C. g
assign mcasp_ahclkr = mcasp_ahclkx;
. @2 e# A+ G6 k z: eassign axr1 = axr0; " P0 f, j8 I5 \3 G: h
# L# I% q- M) U) N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 E9 \9 @" c# u' bstatic void McASPI2SConfigure(void); k( P7 j9 i7 Z. {2 q
{
. E6 |" Y- d1 j; }3 l# A% fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 c( O5 f% R6 o5 P. Z, @0 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* [5 @$ @2 A/ y+ |. q2 M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* c! P4 o" t- a1 o! j6 A! nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" R, ]' o, |7 {, EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! y/ I: u* E0 A4 MMCASP_RX_MODE_DMA);
5 i0 ]" X8 Q6 p$ i6 A6 tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 P/ X; Q7 y, u' SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& h$ T' a1 J1 n, V( V4 z" AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . F' Q6 ]3 M$ J* t8 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 q2 q# l7 @* c2 w2 _. EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) v& o" Q- {. b aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 O) L4 w9 T7 XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 ?! H2 N& e2 a4 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; }# g* ~! s# d+ J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 h1 e; Y; S# D! n5 {
0x00, 0xFF); /* configure the clock for transmitter */
0 p, m4 ?' h* V0 @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# ]) S- V9 o# ^7 f) g1 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( ?0 p) R: V" k, `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ R+ ^& d0 z% E$ ^$ H0x00, 0xFF);
* y7 T, i5 \# D7 R0 v4 y: q g* m* R) _. I* [7 Q% y/ V
/* Enable synchronization of RX and TX sections */ 0 T. `* e+ i3 u9 m! \5 B' R R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 |4 X1 `8 n% G! bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 A; _8 l; K) z8 f6 E! D& g8 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 ^, e6 e; K# x. ~** Set the serializers, Currently only one serializer is set as: \& {2 G( P) ~4 K
** transmitter and one serializer as receiver.
" T4 N1 r# N$ C% ^0 q% T! T$ v*/4 ] Z* T8 j$ i- x- k' S0 q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! p) p0 j* m# _+ J4 q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" D( g# A2 {, e a" T: @ s& x** Configure the McASP pins / \* U: u* i( k1 v: a+ Z* g
** Input - Frame Sync, Clock and Serializer Rx* m: W& N; D" D5 h
** Output - Serializer Tx is connected to the input of the codec
( E5 v: F3 s: e*/
% i) e) G' ?" vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 |# ~' U# A& g" D# K- Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, r2 f8 z: o, c8 {; F$ M8 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! F9 f4 l# e# \1 Z| MCASP_PIN_ACLKX+ n) q& Q* X @" Z7 ~. u
| MCASP_PIN_AHCLKX
- Z$ U" X. D+ F% r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- h" C; N) u& |. y% n$ [' k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; I" g& ]) G9 j, ]0 X
| MCASP_TX_CLKFAIL . w6 \/ i, ~0 V1 m* n1 y
| MCASP_TX_SYNCERROR. V* ^% y- J$ K" g. O( Z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ R( ^9 j" T. j. S0 H| MCASP_RX_CLKFAIL2 O5 O0 s7 w2 A6 d3 x2 T. |( ~
| MCASP_RX_SYNCERROR q) E, n& j9 z6 L3 z4 [7 u/ R5 A
| MCASP_RX_OVERRUN);3 t1 e' P" }: {: D# v: t
} static void I2SDataTxRxActivate(void)
5 f7 J0 D. C% X# b{
, m% K" }2 A+ X/* Start the clocks */ [; x. h* g, m. W( R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! Y k, b5 `# w7 @. C0 g+ x( t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' ?) ~) ^/ a. p- n+ F3 W: G4 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, O/ R: G& X! m* T
EDMA3_TRIG_MODE_EVENT);
: U2 t' ]' x9 s8 K4 J: [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; {# y9 s6 C8 S3 |- ]6 w0 \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 a" O" V7 u+ V w2 ~9 d# G7 EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, D9 l8 T3 r: R: e G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- }8 `8 h5 _+ W$ |3 Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 `; `* H, d' [" C, V/ Q% ?* n4 v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! ~7 d! f$ }4 P/ L' m, G4 i1 c/ ]. bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: k# `" I- }! _; }% y4 ~: ?( d* R}
2 L6 X6 P+ \' ~8 r( E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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