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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 X" O& C* w% w, T; W/ x3 Z5 a+ t
input mcasp_ahclkx,
7 G' ^9 _# E/ M0 m2 e% Z, Finput mcasp_aclkx,( i2 i7 M3 a& U$ i# Y4 c+ k- B2 z
input axr0,
, t: w2 j1 C7 N. @
% Z8 I! h, F, g/ t1 Q$ ~output mcasp_afsr,
6 s$ W- g( s$ O. G: a2 |output mcasp_ahclkr," j+ U1 L$ q; R( V9 F# G0 t }
output mcasp_aclkr,0 E- q+ h7 v6 d4 w0 p7 D
output axr1,- L7 ]- M. C D) x/ G' Y
assign mcasp_afsr = mcasp_afsx;
" [: m. ]1 N: B6 nassign mcasp_aclkr = mcasp_aclkx;
! t2 x* b& L9 [# l) rassign mcasp_ahclkr = mcasp_ahclkx;
, v! Z8 E7 U! R! j/ xassign axr1 = axr0;
9 d( n9 j' d' y+ n! `" J
% {# Z" R% {, h5 M9 E; E2 f/ J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( U. G- ^6 a' _6 ~2 y0 ]" I, X
static void McASPI2SConfigure(void)
% P8 R4 T& Q' s# R# c; H E# `{; O O* T$ l+ {, a* B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! b8 D: l% z) a: ]* L& p* P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ Q; a" s' w w2 N- d7 B. DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 ?1 a) v m; x: Z V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 W& o* p3 g. q6 `7 ?+ z/ C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& K |4 B2 W( W+ g& M, j7 S1 \
MCASP_RX_MODE_DMA);
$ Z+ I$ b5 `" u2 R' XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- d) O) Z3 P3 P/ S; R0 v1 H n+ FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ z; j: U! { T5 U* J9 c9 @- N5 d0 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 G; S. e9 V4 H+ Q2 {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! X9 b4 @+ L. R9 |5 ~8 oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; H- P2 B; d. LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( N' w) _) K6 @, C! b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 q9 V0 k: M) C0 n$ q! u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 I7 L/ {9 e. DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. d5 T W0 B: D. v0x00, 0xFF); /* configure the clock for transmitter */, b! O% X4 t/ O: N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 o9 a& \" p2 i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* V- g0 f0 Z bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
R7 l) M! C2 Q0x00, 0xFF);
* L- S8 c1 @" E, ?. I2 I' U; G% S {6 N8 v
/* Enable synchronization of RX and TX sections */ 7 L9 M# R8 {4 G9 \. H8 V: X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; i* U1 y5 E. K8 I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- d. Z& q3 b4 H5 |8 Y5 tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 n! _+ j$ ^* Z2 u6 N% O; r** Set the serializers, Currently only one serializer is set as
" a! g+ k0 Q- M9 ]; z+ _ O** transmitter and one serializer as receiver.# v( g5 P j8 u" u* r5 f& ]9 ~
*/4 C% S' [4 y; }7 a& Z3 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% X u y1 |" x, I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 L% g( q0 G/ Q7 |; i
** Configure the McASP pins " O, h3 k: V: r
** Input - Frame Sync, Clock and Serializer Rx
8 ?" S4 p( l( `/ i** Output - Serializer Tx is connected to the input of the codec O, d3 U2 [& Y/ `! r0 a+ O3 |
*/8 K$ u7 X4 g) _( e# b6 L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 P) r. h( c1 u2 ^% i" _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ X0 a! b4 }* T6 V2 N+ B5 z5 D6 ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" J" [# I1 t$ w7 Y, i+ }* e
| MCASP_PIN_ACLKX
! G F4 A+ u/ _; J4 y| MCASP_PIN_AHCLKX
4 e8 @) f, \, z" w! D/ d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
R9 e" E1 L1 OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
B* H) M: `/ C4 n| MCASP_TX_CLKFAIL . {2 g; j$ X4 D8 b* t
| MCASP_TX_SYNCERROR' u" Q0 r) V/ B% `* ~ f' x$ L; J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 {1 o; z. F X3 w
| MCASP_RX_CLKFAIL
( e: y, |0 ^: ?* n| MCASP_RX_SYNCERROR
$ X" P) a" P; u# _, j) c| MCASP_RX_OVERRUN);
+ \7 c) j8 H, l8 t& W9 D: _/ j9 `8 F} static void I2SDataTxRxActivate(void)
6 q5 D4 \6 n6 M/ I1 p2 r- o{9 _2 _% z1 p y8 k& n
/* Start the clocks */
6 M5 X9 X1 a5 k# |# ^* QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& c0 S& Z$ z6 p. I4 Y# EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; ?8 A. z4 Q- M& s8 m A% E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 l; y$ |3 l8 R! D) OEDMA3_TRIG_MODE_EVENT);/ J+ x# k) d) _' \9 y% B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% n' L3 d- C' IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ A0 o* K1 R+ A1 `7 t( fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 O' q+ Y, U$ `* V7 ?" O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ D* m4 c7 t9 V1 X# m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( h1 \: r5 b* T1 a" i0 Y- pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 f6 p! Z$ F1 P8 F! x& W; eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 D; C# S7 \0 K u
}
( X& {& b* c! t8 z; U; S* I A; H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + G$ q Z" x6 _$ g3 f
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