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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" V6 i4 f4 l6 p( O2 u& R. {/ Jinput mcasp_ahclkx," Z' l) Y0 N7 g# X( L1 S' U C. p6 y
input mcasp_aclkx,. ?" E: F8 N& O/ T" ? j
input axr0,
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# l! v" w6 O9 I; F0 _ J. o1 z# e! ooutput mcasp_afsr,. t0 c u3 n2 R& d3 N) c
output mcasp_ahclkr," s! |& Z/ P3 q4 B8 R1 E
output mcasp_aclkr,
$ o+ P# n: k( u4 e& U# i) coutput axr1,/ ?% Q9 J. ~! x8 w$ d! P5 O
assign mcasp_afsr = mcasp_afsx;; j* e+ o$ N2 L& N
assign mcasp_aclkr = mcasp_aclkx;, g! m/ p0 z/ [; y6 t
assign mcasp_ahclkr = mcasp_ahclkx;
2 T8 @* q; U/ J# passign axr1 = axr0; * y! S- e/ f5 Y- ?( A
p8 m8 p) E7 Q6 T3 P4 w- _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 | j! ~$ H5 T# [( s
static void McASPI2SConfigure(void)5 `+ c/ ~# `" l& x6 x# p& z
{5 L7 r2 i& X e$ [1 C9 o$ {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 Z# v7 u- T! S, j& h6 c" d5 NMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 B+ y; v' b7 _1 z9 {& p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! y- V3 @, g; ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 }" M. n1 n0 O# ^4 F* }/ s3 I7 a9 U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 U' v# P5 P7 iMCASP_RX_MODE_DMA);: q1 k+ T/ H! [( O7 ?3 O- \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, i+ L) }/ R& q" G) p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 ^. K0 a/ J+ @8 d% ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + G1 R6 j# v2 v, [; o- i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 T T$ F$ g# s' L% o1 z& L6 q# O. gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( D p; J: y6 m; [5 w& UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 Z ^% G. B# c) Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 N/ R) v% I8 J. R0 jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 ~" |, T- _2 i/ {& y% n3 K5 h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* g& t0 W7 ^$ O( X) s9 W4 R0x00, 0xFF); /* configure the clock for transmitter */
' s: t! R7 x2 l, Q' H' i: c# S. kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ u* n: Y! F5 V7 O; }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ X7 m6 p- i, [9 ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! o! s/ y7 Q4 F$ w/ b0 a; I
0x00, 0xFF); v t3 |' M* O4 J" a
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/* Enable synchronization of RX and TX sections */
' t0 X6 W4 n0 i& ^" j+ i0 rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* g3 G& J, Q8 }& e2 z+ W5 {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. |8 V1 Q9 `+ E" ^: l) T( |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ w; ?2 s0 }# l** Set the serializers, Currently only one serializer is set as
/ F( _& [& M$ s9 T) g** transmitter and one serializer as receiver.
4 U: } ` Q4 n( l" F; ^*/3 J3 m w7 P. ~6 y+ q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# m3 ]7 S3 z+ m9 L# ^3 _4 KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 ^* o& y0 T4 F/ O+ ]
** Configure the McASP pins
: z& l8 `5 _9 c** Input - Frame Sync, Clock and Serializer Rx+ O: B$ V) X. @3 ]/ j7 `9 t) I& {6 W
** Output - Serializer Tx is connected to the input of the codec
4 {7 K; D' H6 L2 s*/
# H4 {2 w. V( e4 ^ _% fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& k5 @9 ?- p+ `, P/ C( O# R% Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- D; ^# x' A" r5 vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! k# K6 \% }% J% p| MCASP_PIN_ACLKX
4 i6 X. b, Z; y/ O A9 x5 A| MCASP_PIN_AHCLKX
& B% V' L4 d, m* N1 h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( ^1 ?% _' O2 I1 I+ Y8 t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( Y# y K. ~3 Y. T+ f( z. f5 x5 V
| MCASP_TX_CLKFAIL 0 ^0 V) a! {: Y
| MCASP_TX_SYNCERROR
. u9 b/ f+ O: w5 _# B$ n$ Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR y3 g* d2 `7 D& k" ?5 p
| MCASP_RX_CLKFAIL# R9 t. A2 b' j8 w/ i8 U/ w8 {
| MCASP_RX_SYNCERROR
- _* k( Y6 A" n| MCASP_RX_OVERRUN);
w9 \; W0 h; U7 b} static void I2SDataTxRxActivate(void)
: C8 k2 `: d! b6 q{) [5 ^) m; P/ [: D9 k- _
/* Start the clocks */" n+ z7 I, j% a9 _$ f( _# i/ m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; C5 @( ?8 g+ @8 \3 g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 x! `# w. s7 \( `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 n7 g" `4 G. E- L
EDMA3_TRIG_MODE_EVENT);6 s$ {) B/ C0 i$ o! g, ]* J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . U. o1 G# K1 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" m X, M+ _! @- B2 E8 a4 X1 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. z3 B1 L Z* h! _7 r' b1 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 M; g; D1 e3 m/ z1 s( V/ d i& j& _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! v/ @2 ?1 q& s5 h( b, cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- o. q0 ]: I- u+ U% E9 D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% R3 t3 y ~1 E p
}
' q) f( H9 o) o: w4 J* }' m0 W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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