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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# v8 {( J, a! u$ _5 j' ?
input mcasp_ahclkx,
6 [& O! H$ L7 O! q" finput mcasp_aclkx,
) ?( V t( h4 p0 C0 Yinput axr0,; {( ^% A* y4 n# \
5 Q: v1 o# G& ?" v
output mcasp_afsr,2 b5 w: N- e6 h J1 ]/ N
output mcasp_ahclkr,0 O/ M1 F+ W, S" }" B
output mcasp_aclkr,9 K3 O$ C* U- s7 O- ^' k: T
output axr1,
8 r$ e% V! A7 Q r: A. X assign mcasp_afsr = mcasp_afsx;6 i* h s) T3 S3 Z
assign mcasp_aclkr = mcasp_aclkx;
, o8 W( e3 c$ {1 _3 {assign mcasp_ahclkr = mcasp_ahclkx;4 s" |( }) h) @
assign axr1 = axr0; 7 d. D: n; V( V
& E! u0 \4 J4 f. z0 j6 w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 ~" x! D+ b; |! astatic void McASPI2SConfigure(void)
/ M8 r6 w" G! H7 F: N: m7 R, t; q{
* q/ @* ]" I5 i4 e' l: W( Z" v! n, eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ O% U6 V' `: y8 _5 p3 v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 P/ L$ q3 @5 J* p. M" B% jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( H7 t7 U: U* {2 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 N: _ X! [8 k% E, J; B3 ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 k' Q6 \ m7 {" P. t4 q. k2 E+ h
MCASP_RX_MODE_DMA);1 j) k0 X7 W2 l. u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
d: g3 I- V% C+ n3 P2 EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 h! b5 l0 d6 uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: ^/ e) k! ?, E5 p, b3 x+ b, gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 J# B% T- g9 E2 q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 B* x9 @$ R6 F4 S6 P K* pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: v5 ^9 i d) o: S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ j1 t4 d, Y2 V; M0 E+ J! b' LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 l, [$ f' {& s7 v) A9 s2 k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ | o& y' i: d2 e+ a
0x00, 0xFF); /* configure the clock for transmitter */3 A0 D/ v) g4 k5 c! O$ A Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ x8 j- Q# [4 W5 c- J& i2 O1 uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . V& p9 K1 o, c) G1 _; I& @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
E7 p, t+ r, M+ F E4 s5 M+ v( h0x00, 0xFF);% a9 L1 S* V7 r. K9 W; F* D) W+ E3 B
& u. d5 {3 M' e6 S/* Enable synchronization of RX and TX sections */
3 `1 \! _- d1 E% L% r) y" XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 w8 C6 O9 T, W' P$ w. |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" ?2 g; ?0 F4 h; |$ {! s5 D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 `% I0 A0 f' M3 n/ b
** Set the serializers, Currently only one serializer is set as
# B' Q& ]/ K( N7 k n** transmitter and one serializer as receiver.
5 q" Z j3 ]' E8 M; b*/2 R! t' D% ?( w8 ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' n2 G. A: J+ T, F7 t7 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! ~5 K4 i7 J" }$ _3 P) l
** Configure the McASP pins n% o1 M: } u# o+ o P
** Input - Frame Sync, Clock and Serializer Rx) S6 {3 e" }$ h9 s
** Output - Serializer Tx is connected to the input of the codec : ~3 ]9 ]* A; t+ n
*/
7 e3 Z' b- P8 f$ Y* Y; PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" M/ E9 C0 \. y" W4 w. zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ F) v' X, X. P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 N# _/ Z3 h. p2 F% L" U
| MCASP_PIN_ACLKX. H3 ]* T: _+ m$ a) ~6 T
| MCASP_PIN_AHCLKX
C5 b, a: i4 C F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 L# {0 _2 [- B6 p# V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 c! d4 k+ q; i5 `1 q4 p' o& r6 O
| MCASP_TX_CLKFAIL
7 m% D' K7 J$ u P0 F| MCASP_TX_SYNCERROR
8 o$ u( J5 u0 O5 z+ w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 B1 }. d. Y8 ^* b1 f' c| MCASP_RX_CLKFAIL8 K7 K, r; @ g
| MCASP_RX_SYNCERROR
0 X1 V* K- Z+ o| MCASP_RX_OVERRUN);
+ D; n% \7 \. x/ Z} static void I2SDataTxRxActivate(void)2 c( z8 d* a* m7 S; P$ N
{
5 l' ~( Y3 k: J! U: i" [! B ~2 n9 t/* Start the clocks */
n# l' O* X0 S+ |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 V7 u. a3 k& F$ Y2 k; B# ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, i) j/ B' v% V+ Y4 a5 E( Q0 g6 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 V/ p7 o. \: S, T% H- G
EDMA3_TRIG_MODE_EVENT);9 k" t' ]/ n5 F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * J9 m O6 @7 K$ a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: z) j( Y4 @4 v- r* B) KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 ?% r, W4 @+ Z. }1 h {- {7 u+ H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# o. `4 m' O! q& c5 i8 U% gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 O L* E6 d( s4 l4 \% C1 \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& _1 c+ m* m) Y6 {/ h- ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 J" [8 B- u. C7 _/ s6 S
} ) }- M. S( F; l, s& [5 h3 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 c# G* [7 t0 v* d. v) p& o4 A
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