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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, n, o# D: F% n3 \
input mcasp_ahclkx,. R' E* z1 U( d5 K
input mcasp_aclkx,% E5 S" \" t4 G* M9 f& a: d, J( X) I
input axr0,. B9 b; I' r* M- ^& \$ W# K! B M
3 R& U! B! \% G8 L* J, C# ?output mcasp_afsr,
! s0 e( ~7 S, B/ D7 _6 _, Uoutput mcasp_ahclkr,
+ o9 O1 T3 J: S+ ]% |. t% H5 Eoutput mcasp_aclkr,
1 Z, e' u5 d) ~, ioutput axr1,9 T! W/ m! F7 G+ Y h3 E
assign mcasp_afsr = mcasp_afsx;
; W* s$ C4 H; G) Q! R: Passign mcasp_aclkr = mcasp_aclkx;
3 C' V# Q( R4 passign mcasp_ahclkr = mcasp_ahclkx;
: U! z! O% t/ i \assign axr1 = axr0;
# W9 m3 x3 w9 R/ I6 S/ t6 d% l9 |3 m: Z1 P& L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " \7 H/ i$ H/ h
static void McASPI2SConfigure(void), Y7 J( \- t5 h+ ~; a
{
# s5 f) z, m) _- ^% ]6 Q* kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: H" i9 T* J1 {& Q5 hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) ? O `% l- S4 I; }, w: k& BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ E/ x0 E% |7 J0 A2 g n& VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 {0 ~! `! A; g: i% t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- C$ `/ E# U& J& n. M% F
MCASP_RX_MODE_DMA);
g5 N! {' l+ O- k' h# D! w5 mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* h% L3 w: q) }8 FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( L" E0 q# P' o- R! \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 r! q1 y) H' ?+ yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ f h, Y6 T4 v: n# k' p* q4 U G. Z- N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- O8 g# z, O4 W4 m, A+ j/ iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ i& K9 F: c6 UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 p. ]* |7 f2 M1 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 K4 q% W7 C" xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 I! v: n9 v( t& d O0 C0x00, 0xFF); /* configure the clock for transmitter */
: ]9 B! }# k( I/ d8 ]* QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 R8 E5 Z) j) N- A6 ?1 {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 O" g0 ^6 k E' hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! ?7 q% C) U! k9 A+ v
0x00, 0xFF);
7 c; o" @9 R. W( J
9 q. ]) Q8 d8 U% L3 e w' n/* Enable synchronization of RX and TX sections */ ) {' b* C8 f" H! P8 S& [# M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ I) b8 ~" l1 C7 a! J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, r. q* ]5 E) A3 W. uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# W# F; n) w- ?$ A7 k' N. K** Set the serializers, Currently only one serializer is set as
; \" y( Z& Z* k9 f- J: H** transmitter and one serializer as receiver.
. w- c3 Q/ j Q1 a) v*/6 x# n5 f2 O6 v4 L( R* n, d3 J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 L9 z+ a0 i. C* Q1 ^1 |3 v; t7 xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 }" g3 @' N+ H: N4 o
** Configure the McASP pins ' l# S2 R0 @" U( n
** Input - Frame Sync, Clock and Serializer Rx4 g; g1 m. l; c$ ^! o
** Output - Serializer Tx is connected to the input of the codec : f9 b4 y( i. e. E7 _
*/
4 d- E: r0 J' n& T% ` CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ U* n& ^& M) [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# e/ [! V" F5 J+ v) F) jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% @4 r* [# t% g. u. G, s| MCASP_PIN_ACLKX
7 F% O% F8 {2 c. h* K6 F| MCASP_PIN_AHCLKX
j/ X, K6 [- x0 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& c( V' k" I4 N% }2 e0 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 M8 m1 h3 V+ [( l* z2 |
| MCASP_TX_CLKFAIL
0 h0 ]% [1 X8 m' O5 H" i4 g# r3 J7 || MCASP_TX_SYNCERROR. t! ?: h0 X+ i' M( \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ k s7 q& P6 M! C, s/ E' c: c
| MCASP_RX_CLKFAIL
2 ^1 }& h( e5 o2 ^% c| MCASP_RX_SYNCERROR 5 r# O7 L+ o" ] O) k( Y
| MCASP_RX_OVERRUN);0 S0 E7 H* g) |5 X
} static void I2SDataTxRxActivate(void)
5 s |' }) |3 s8 J P{
% {- \: C# R2 q) a( g% ^/* Start the clocks */
* D# S9 ~5 e. W! ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- O8 `- s& z" |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 Q$ ] I! q: n3 d% z& cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; Y* v- r3 j' m- b: f+ \% b* k- [: a" ]EDMA3_TRIG_MODE_EVENT);0 N7 P/ X7 G I: t2 S: b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & x% C9 `7 h3 F1 c, G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 Y8 x @$ `# k1 _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) l4 X) G! A5 p7 G7 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ `9 E0 u0 N4 }" Z. Z& c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 k7 t+ J2 g' [) u+ ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 M+ D) y5 e! O% ~5 d: G) ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" D0 W3 R- F9 P" D g- D+ ~6 \} 0 y+ w9 g+ @3 J" o B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & I1 C9 L/ W! N2 H
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