|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 v6 Q. K2 Y( b+ a ?- {/ iinput mcasp_ahclkx,
8 R% s" h8 x; j' V5 Y2 ^input mcasp_aclkx,; { h9 s% S }: E# A7 k. j& y
input axr0,
/ b2 f" p+ s8 {& h1 U: ?$ c9 i: N4 g1 x! a
output mcasp_afsr,: I2 r) k6 @" A& h
output mcasp_ahclkr,- X5 T( {& r8 i: o
output mcasp_aclkr,5 l. W$ m0 w, U! V9 L
output axr1,
4 c* I( c; n. N7 d( j H" R$ h assign mcasp_afsr = mcasp_afsx;
2 g% t- [2 e1 T: v# d0 passign mcasp_aclkr = mcasp_aclkx;2 X& U7 P }3 C8 T
assign mcasp_ahclkr = mcasp_ahclkx;
; ~( @3 i1 g# ?4 T5 g3 s- Yassign axr1 = axr0;
2 n, l( E9 H. E& r, t2 ^
4 F5 V; R/ G! g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 b" G& P& R4 s! @ Qstatic void McASPI2SConfigure(void)
# r, N1 Z) u. \6 b7 n{
+ r& }% l* }4 w6 w ?# W/ iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- c6 O3 q- ]( Q, s1 U/ b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' \7 R, R# {, T: }9 SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
H% v; f, G9 G9 O9 `2 N4 jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 b: B6 \+ U/ t! S/ [+ fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. t% ?4 F- ^+ l
MCASP_RX_MODE_DMA);' j$ v2 i6 ~* j- ~$ C, f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, j2 d: m n% Z" l$ v$ rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, s) G* L; s, P) R' R4 l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) P! u3 H* }; K- r/ X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) c l3 j1 }0 L; v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; y( [. Y% ^+ p1 `" D4 lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; A$ s' E( o9 _ b8 I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ n/ c2 S# Z" t- d( Q6 qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * x* H9 M9 Q9 z; B' O2 K2 q. T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! J5 ?: f4 a) C3 o
0x00, 0xFF); /* configure the clock for transmitter */% e/ C2 E" P+ H" l( l' ]: h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 h8 s% W1 S) V# n( x$ ~7 k6 o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 z h1 j$ X7 Y( V) O; k c+ PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 U* A0 C" w4 N$ W: J* _) u, I0x00, 0xFF);! Z4 m1 M' n# r0 ~/ X
4 g" P. x( g3 J, {% f# D p& i$ Z
/* Enable synchronization of RX and TX sections */
$ A [' o. T3 k0 H9 m+ |2 B( }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. v% ^ ]$ R( i% W2 H4 l; z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; w7 [2 Q: Q2 h* a: lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 \8 M) X; O9 n) w! s** Set the serializers, Currently only one serializer is set as
; @* l1 h5 O& n I8 h: l** transmitter and one serializer as receiver. n( f/ z4 ], `/ ] ?
*/2 W0 H9 J' Z4 E) _6 A1 y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 j! C6 { c+ n [7 \" f6 }7 [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 P; K, U( j4 t8 L; A: V! h [** Configure the McASP pins " \5 K' F! ^3 O4 T, v; N! l$ I% N1 f% }
** Input - Frame Sync, Clock and Serializer Rx
% x) h- ?, {. x# J: S' f2 z( ~** Output - Serializer Tx is connected to the input of the codec
( S- g; E. ?: T4 R% c$ s% r* `' B*/
( h' m; b% Z( Y" ^+ f! fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ H: c$ `1 s, g6 o. X! TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" j8 X2 t; h0 D1 T, a8 x. a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* n4 N2 g% M( e6 }
| MCASP_PIN_ACLKX
2 t3 o- O( a* T2 D* u/ t% M" o| MCASP_PIN_AHCLKX
3 \8 A( b$ i8 i9 D+ E5 X9 }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ x5 h. r' o4 h8 q/ b# hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, [" u$ D: A% w8 S/ w| MCASP_TX_CLKFAIL + c7 M- ~( _' w& |/ p0 i
| MCASP_TX_SYNCERROR a! ]% y8 h$ L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 v' s8 b8 r+ X8 S
| MCASP_RX_CLKFAIL ^. r7 A; ~+ J+ o( s4 A
| MCASP_RX_SYNCERROR : _8 G, u! Q0 N/ _) P3 P3 L! [
| MCASP_RX_OVERRUN);
+ F% D( O* {0 }4 r/ p} static void I2SDataTxRxActivate(void)
9 h& ~+ Y9 {9 c4 S! u) {{& \$ p$ T7 S0 \$ p7 E
/* Start the clocks *// s+ p' m8 K% l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ F2 }1 G. ]: x) ~2 b/ [1 ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' A- N( ^5 \! y0 D. v. z8 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 B6 M! T( n" v3 J$ ^0 oEDMA3_TRIG_MODE_EVENT);+ N3 Y- ?$ c. s0 A, L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) X# O6 V9 m0 z" B0 x/ b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" {3 q2 I8 ~+ R4 j! C; R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ V7 i( V1 P4 I, i& G. UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- S3 k: u) w' O" R0 R& z6 Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( v) U3 I2 J5 F- R* ]2 f& ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 O/ Y" q% q9 x3 W- l0 Z& ~* ?6 ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( [" E S9 u, [# C9 N& b
} ! Q3 s; ]& O5 W2 S! e$ J( {, g+ d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 Q# [9 l: }! Q# O4 ^6 |0 b, y7 `5 |
|