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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% \$ @5 k, X& r2 r0 w9 e
input mcasp_ahclkx,2 E9 M7 J! {5 b, {* K5 t
input mcasp_aclkx,8 `, m8 o5 h9 R. J3 Z) L
input axr0,
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output mcasp_afsr,
' k+ t- i/ r: z0 j: p6 }$ Toutput mcasp_ahclkr,9 J1 U( B4 @* P% [% n. F3 I
output mcasp_aclkr,
2 ^8 o* _7 Q' R# a7 {! a1 toutput axr1,& o5 T: R! d9 \1 A
assign mcasp_afsr = mcasp_afsx;9 G( @* e2 _; b/ Q
assign mcasp_aclkr = mcasp_aclkx;( ~4 i0 @5 b' p
assign mcasp_ahclkr = mcasp_ahclkx;
$ w3 m( N- N' e3 B# R' Q, Oassign axr1 = axr0;
- T3 c+ \ I; s. F9 I& O0 A$ d) {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 q1 @8 |, P) i2 {" h8 C6 r Istatic void McASPI2SConfigure(void)7 d) \* u6 `; A) c
{" G( U: T9 n5 z, a5 b ~7 D! ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' b7 g9 U8 Q ]5 W$ @( s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' }/ k3 o* W! b2 J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 b* M# b4 S2 ~, O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- G o' W& } n3 N* d1 K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: N$ q% H* Q# g$ P# ` T4 C
MCASP_RX_MODE_DMA);
: N( _& `* b. J) }+ g( h& S2 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: Q2 K# s6 V7 ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; h% z8 I: o7 ^. ^& W' yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 {' S# j, ?, Y) L6 ~6 O$ BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 ^; v _5 H6 `6 R0 _* f1 I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! Q4 e) V) D8 p$ [8 pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) [' p# u5 B4 z8 i+ m8 y* gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) W$ e. m; I# @% O% V6 p z3 A, I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' Z# ?" Z' T9 L+ O7 F# ]* mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: t- i2 B& c" Q& n5 K- c+ q
0x00, 0xFF); /* configure the clock for transmitter */
4 t L6 A* M) Y; ~. N0 N- pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ ~3 g) e' `( qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 N6 L5 M- I1 s, R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 M. W& \. }! H4 j5 c0 @4 c4 O! e0x00, 0xFF);
8 N* y, r1 l' I r) i, v2 v/ ] a, i" j% g( o, F5 o; E9 H
/* Enable synchronization of RX and TX sections */
h( u& b% H# }+ a% r( s) M* gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 I. Z ]9 _( N! e* l, u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ a b6 P' A1 A* kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 ^0 }0 [! \2 t** Set the serializers, Currently only one serializer is set as) Q! ]& Z7 G3 R8 j: @& x
** transmitter and one serializer as receiver.# v( U) C( a- z. m
*/
* @0 t/ _$ Z+ c1 o" X6 _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ e% \# }4 f! r# wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 t! H% C; f, S7 ^( o1 d" u& i** Configure the McASP pins
! q7 ?5 l; n4 H- ]( o, o2 ~** Input - Frame Sync, Clock and Serializer Rx1 O+ g. I$ [, s" d4 a
** Output - Serializer Tx is connected to the input of the codec
7 S4 x; u& c; P/ K- D*/9 L5 E5 N. o# U R/ T2 j' M. O9 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 y+ d. O/ q. r# R; i8 q* e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& N4 [* B" E" w- p8 h+ J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 F6 L: h: K* ~$ m+ Y& x W# R% F
| MCASP_PIN_ACLKX
4 L3 E; S% d% i1 V2 E; R| MCASP_PIN_AHCLKX
1 L0 ~7 t d% a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 ~$ F3 i( Y7 u( Z% D% z7 X+ N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' h4 H2 B; c* j2 J z
| MCASP_TX_CLKFAIL ! C: X1 f: e; X) P) Z
| MCASP_TX_SYNCERROR& C* L; M7 U- B! u6 x6 T4 Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % A% P; x) w9 F3 m6 O1 G
| MCASP_RX_CLKFAIL
3 \3 E! E$ a# v7 L2 i0 f: T9 A| MCASP_RX_SYNCERROR
$ j& V( p& G$ V% `* H5 e: C| MCASP_RX_OVERRUN);
w1 Z N v7 p: _3 J5 E7 D- Y" ~" F} static void I2SDataTxRxActivate(void)
9 a% S3 u# C# E{
8 P5 n" h' O0 Z$ S+ l/* Start the clocks */! m+ V6 ~; {+ p2 x3 U+ C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; q* P! N8 U! g! X( z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* e, R- {% j; D) NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 Q: y; i c- {4 h, \1 Z4 Y
EDMA3_TRIG_MODE_EVENT);
: r G9 J+ U# J& Z r6 _ M- O, |8 ?7 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. T9 M1 w I0 W. T+ MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, N# U7 T/ q( B8 b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# Q* s$ S& h2 ]; O5 E I8 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 A R; V) m; ]$ m" }4 V' v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- e i# g# n3 t' E* \1 ^& v4 XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: D/ V( }% q+ Q+ c) [3 s3 d. T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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* `6 M& B' { F2 K$ F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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