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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, z! X2 p4 C _, Q) ~8 v
input mcasp_ahclkx,* W' S% F1 R8 F8 y
input mcasp_aclkx,) q7 }/ F* O$ ^- V: C
input axr0,
9 J" ^- F9 G: r$ A
. |4 h# ~5 c4 v2 R6 Routput mcasp_afsr,# Z& L7 M) R6 X; G! g2 @ ^
output mcasp_ahclkr,
: g, ?( s& V" routput mcasp_aclkr,; f S! S# l# r6 V& \
output axr1,- t( k+ k' V& v, b5 c6 e
assign mcasp_afsr = mcasp_afsx;& j7 }5 t& J1 e8 b0 q
assign mcasp_aclkr = mcasp_aclkx;# b1 ^0 p% Q! L8 `3 D
assign mcasp_ahclkr = mcasp_ahclkx;
( Y5 R1 X m& nassign axr1 = axr0; , y- |( J0 P- |' {" J) n3 T
+ e5 y5 w# s) ]8 |: u+ E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) I p% @) f: e( [9 r+ M+ A
static void McASPI2SConfigure(void)* ?" ]/ H8 G) S- S7 d) ^
{
) I; l0 Z+ ]' S2 F) U6 c' LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% F/ R8 h# Y" N; u3 a: K a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; _/ K: ] m" f$ FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* {2 C7 `! L# f: g5 g6 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' ]) K g' M9 ~' E6 G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. G. ~2 i! y8 M1 Y! Z2 BMCASP_RX_MODE_DMA);# m0 r( D( M7 w: T3 M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& r* H( A; @: k5 }: Y' W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' w7 G, q' d. ~+ \7 ^7 [1 O& ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* E2 ?1 M7 c2 q) {5 bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 m, J' ]+ R, o+ q) ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( W2 T( I% g4 o# \5 {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* Y) L1 N ?- q5 l2 v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 Y- U0 s3 d; J' W8 Y6 {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ ?! b0 ]7 v2 T h+ z7 }% f# pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 ]7 I8 j+ L0 K1 K' t. H$ W0x00, 0xFF); /* configure the clock for transmitter */
+ [$ B# u( L0 T" X4 iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ o4 S; {# {6 sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, J4 C$ j- |' J7 Q }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& b1 o& N# l6 e, t7 k9 i$ R% {
0x00, 0xFF);
4 F) |- @5 M. z8 B" M
" m' _& K9 |* o% C) O- U/* Enable synchronization of RX and TX sections */
# P& V0 r% P0 }0 n: y3 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ D, @) z0 i1 _7 p1 B: A7 K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' ?9 s! b5 e% g$ L9 o$ H, y# MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* y ?/ w7 }- b7 p1 {3 z0 V
** Set the serializers, Currently only one serializer is set as
9 ^$ V$ _ G3 i% t** transmitter and one serializer as receiver.
, ^) G1 L7 H: `, e*// W v6 G- A- [% }% x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! _% A& h) w% n2 t0 FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# M& j/ j3 W" F' k8 g. g** Configure the McASP pins
) ]! d' p" H4 J8 h9 h* a** Input - Frame Sync, Clock and Serializer Rx; t0 }9 n5 D* z
** Output - Serializer Tx is connected to the input of the codec
+ Y* x8 @1 `+ G6 Q6 {( x9 ?& T*/; a0 Y7 X3 G& p# s% ~5 _& N: v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 S* O' N! S0 h kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 { F: l3 B/ D1 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; _2 m4 c6 g& M4 _5 Y/ A# Y6 o! \& [| MCASP_PIN_ACLKX) d" ~( d! ?$ T( Q
| MCASP_PIN_AHCLKX, Y* l& T+ V; x0 V; I$ g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 M9 y/ P( V7 l1 _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / h' x9 n9 g H3 \3 O8 J
| MCASP_TX_CLKFAIL
4 H8 q. b6 Q- F2 u2 \; `: G& @1 t| MCASP_TX_SYNCERROR) ~7 Y% z! \. ?* `% ^' Z# R V. f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 R9 ^+ Z# V- @) `! O4 c
| MCASP_RX_CLKFAIL
8 C/ t9 A# ` K# F0 a9 D| MCASP_RX_SYNCERROR 7 \& e* |" U; j: z5 P* ^+ w# M
| MCASP_RX_OVERRUN);
0 S2 g, V: J" W7 c} static void I2SDataTxRxActivate(void)8 Q+ X+ S# b' j6 Z9 v. g
{. h4 H/ J% q! V8 F
/* Start the clocks */6 P- z' `8 ?6 j o- F2 f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. W' X+ S5 p- d4 a% D1 r) m3 u/ @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 r$ X) H$ L) K- H: U" a- IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% L% V6 V2 x/ {# PEDMA3_TRIG_MODE_EVENT);
5 r- [% @. c+ Z3 @' r& oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ f9 V C$ H: O8 [, D; w; ]+ `, VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& s7 ^) Q& Z. c4 HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 ?" ], f$ M( E* D, S- c# E& gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 C7 F9 e+ U6 G' c4 b5 @3 r: J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 i X/ f# ]% o- Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ ~1 y* H3 J1 {6 |% lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 { Z, h, _* U1 P7 I}
& m3 e/ t/ U9 ]' d7 g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # e/ h1 o( H8 `! P" Z. t3 e
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