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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- T# \& d" O+ D" G2 g; Dinput mcasp_ahclkx,
( X5 b* O$ D# j% ?5 einput mcasp_aclkx,# q5 n5 k* G; J, H
input axr0,& ]( N* ^) B5 d9 g( y. l( \ E
; ~, ?' f: S7 F! U" youtput mcasp_afsr,$ c, m7 p& h7 \% q' @
output mcasp_ahclkr,
" b+ F8 Q1 f! Xoutput mcasp_aclkr,' V. u I- g" B& Z& n% A
output axr1,8 _1 i I* y8 f5 i$ ?9 E
assign mcasp_afsr = mcasp_afsx;, Y0 ^- Z; n# ^/ d9 \
assign mcasp_aclkr = mcasp_aclkx;
2 j8 q' e! J& T" bassign mcasp_ahclkr = mcasp_ahclkx;! D8 o9 d- z8 x3 L% t
assign axr1 = axr0;
+ m q. e; ]8 p3 N
* a/ o, N) G l5 c* ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- w8 U( U& `& ? V+ ]8 Estatic void McASPI2SConfigure(void)# s" @7 U6 z( `/ _# x; }5 H0 U, n4 n
{0 Q1 F$ i9 n+ {- r0 n* p1 Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 x- } m5 F/ A9 R8 H! k h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; C7 C3 w- ^+ n% I* M! EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ P9 L: w$ M- K6 s& IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ h$ W& h7 y; _+ n \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. t' f% z, h* U( j `* U. u1 a7 W( AMCASP_RX_MODE_DMA);$ U4 W4 s5 R9 B; [' F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 I" C8 N6 p [4 g3 a- P' n( t6 z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& ^5 {5 T, t. X5 \" g/ W. d+ U2 J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * U7 w9 v* m7 r# S! L% W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' e& Y1 E2 k7 s4 b! E$ x; _; OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! l" f7 G. t2 F3 j& N/ m4 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 l9 r7 g7 E$ n" P: \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ H! o" U9 c" D L/ d1 {- u' t3 A! A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 L/ a3 d/ S- x; x3 s: PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 o! j& x" S* H Z0 Q8 `
0x00, 0xFF); /* configure the clock for transmitter */
) d8 J' @6 m0 I' X2 `+ xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 m1 ]) X, i4 f/ Q! `6 r E, sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! I) d% n: A8 z ^& m! _/ l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 K* }. x# e: ~! o
0x00, 0xFF);% ^( B. H. q& I- f" i
3 X+ U8 k; x4 A v, p/* Enable synchronization of RX and TX sections */
( h4 ~* k% Q+ {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- I+ w4 ^! B! M9 M+ U/ p" h% b+ `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' P D) A1 N [/ p" O& n3 Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% U& R) P( ?4 O: S" E8 W. z** Set the serializers, Currently only one serializer is set as, o1 o4 m$ O; c8 Y9 s
** transmitter and one serializer as receiver.
* d! i# E% z& h*/
2 f0 t7 ]* i$ k+ ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 P) `. c6 J. h5 y8 QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 `) i- ]8 f/ U3 O
** Configure the McASP pins 4 ?6 s0 f7 S9 i9 \( ^4 }! W& U
** Input - Frame Sync, Clock and Serializer Rx
8 B5 [" k. ^' b$ n1 C** Output - Serializer Tx is connected to the input of the codec 1 A. J0 h5 p4 S; I
*/
) Q* D' k$ k3 z# h$ |/ D- MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 s# k% l- i \9 X0 L) q& W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ K4 N% w) g) O$ X. l# V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# c1 i- l( b* g; f" g
| MCASP_PIN_ACLKX
3 ] M9 Q. s6 E| MCASP_PIN_AHCLKX
. w8 x$ l ^/ h2 Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- o Q) |! d$ z4 X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % N% U7 M: ^: }9 F0 J! `
| MCASP_TX_CLKFAIL
0 U7 G5 c2 u( G2 D$ R| MCASP_TX_SYNCERROR
8 s/ @! A& v% f( T- L$ S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 T0 l5 `. Z6 I4 k
| MCASP_RX_CLKFAIL
0 g' w5 ~ \! {7 T| MCASP_RX_SYNCERROR : F; ]. j- \3 R" j% @+ Q v
| MCASP_RX_OVERRUN); X; W: I" l( r
} static void I2SDataTxRxActivate(void)
$ a) e& y8 w* M4 G{) \! z1 [4 `* V+ }: K# M, q
/* Start the clocks */" `" Q+ C& T/ h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 P+ q6 f& p1 h P. o1 K2 K( WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- L+ w$ y' i5 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' w" l0 k, c. k0 a( n, a2 i
EDMA3_TRIG_MODE_EVENT);3 a& Z* |7 ]8 R( s% ], n# w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 H" S0 ]" _; O" z$ B( ^0 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 _5 I" q$ @# K# ^9 z+ C3 JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) F4 w/ R% ?- P, L% h/ l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 c) l; p( n p# O9 r; {5 d) awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ k0 ]! W( j* I" |: b' A* ]; ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 L: y2 Q9 k5 v6 k* s: VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ h# X ~9 z* x: q}
5 p7 V4 ^% B- B+ x* A. q( J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . a6 [7 O$ y! m9 u7 k
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