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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, I! a- M. F7 o9 e1 t# D% q7 L# S
input mcasp_ahclkx,- l" F# N- _+ n* C+ W* N. N0 i
input mcasp_aclkx,
3 p3 |% q9 R: k2 _2 pinput axr0,: E- \" \8 u, i; l6 s* |+ Z6 e
c8 N) m& y6 Boutput mcasp_afsr,
. o8 @7 ^! t2 T/ [' ] C" Q2 F/ m8 [0 doutput mcasp_ahclkr,
* K+ a$ M: h* D+ |7 ?2 f4 s& }output mcasp_aclkr,8 E$ ?4 A9 S0 r
output axr1,6 ]9 Q8 p4 b) o+ X0 `4 s
assign mcasp_afsr = mcasp_afsx;! X+ I* ]9 d9 R Q( J* D7 y+ W. }
assign mcasp_aclkr = mcasp_aclkx;
0 l# ]* X: G4 x" q9 s1 Sassign mcasp_ahclkr = mcasp_ahclkx;# Q2 |: i- s0 h" Z: s' V7 }+ Q
assign axr1 = axr0; - Q0 f v2 t5 K1 I" G' @. R
6 J" s) q$ N: U3 j! p& R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ q. \( w& E4 p) l2 N2 dstatic void McASPI2SConfigure(void)2 p6 {3 w2 v: R
{4 s! A: V2 C4 r$ U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: t7 m; o7 x/ o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 b9 o7 z- n/ j5 E" `* E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 h1 K7 `3 ^$ B4 s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' S0 H0 v; m M; G' d( H% @ e. \. M, @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; R7 @7 x: M4 B9 L$ o/ t
MCASP_RX_MODE_DMA);1 i" B9 N; _9 k9 V: z" F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* y- R. x. F+ ?( p, W1 i" e8 O' UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 b# |$ s% p4 z: d6 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % U( {4 `5 |8 `( I8 e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. j+ a& j* n2 _8 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 X6 H) @) k4 b# [. e9 a! mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# }- z _; s7 O" G1 @* N8 rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, n8 C" i0 u1 p1 C+ t2 a6 MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + d. |- v# x4 J# b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- C7 V$ a. g; s9 F0x00, 0xFF); /* configure the clock for transmitter */0 B" k; [7 F y" `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! D# c$ l0 j& W) u! n7 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# w, v8 i9 [ r- SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 u9 ?2 D- `* b
0x00, 0xFF);" m! n7 o4 D* R* e
( E# d1 ?$ D! A8 _% S& Y# ~/* Enable synchronization of RX and TX sections */
7 P2 t* B/ j! k, ^. IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! B7 Z2 Y/ e6 |* U* m# x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ E# }# U& q3 h2 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ \* f0 T ]& [- G5 O
** Set the serializers, Currently only one serializer is set as. Z+ E# m% Y5 ]+ w, R; Z" L, _& n
** transmitter and one serializer as receiver.
2 P) D6 n& ]+ e7 N*/
( M" X3 \" Z' V7 z X! L! o6 G' H; J' SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 a$ r# H# M, s( f% U+ qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% r* `% e. Q% c2 {) N$ O- j** Configure the McASP pins
( L8 {6 E# w0 E( t0 r5 L** Input - Frame Sync, Clock and Serializer Rx+ e A8 p" g+ u z8 T. Q
** Output - Serializer Tx is connected to the input of the codec 8 T, c1 M1 }* m# N& `- ~- v
*/
4 M6 r) F# x' d0 k {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" z: h% {' {/ H8 D' `3 S( r/ nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 z2 M0 b! G" m- ]- [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( W# Q$ G2 z; {) [* w5 r, u* ^# j" }5 b| MCASP_PIN_ACLKX2 b: k0 q0 ^1 k0 o9 d( D
| MCASP_PIN_AHCLKX
! n4 z1 e3 ^& O; p/ o9 y" a+ Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& `9 E- m6 u' j. z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ @ r7 w2 m ^| MCASP_TX_CLKFAIL X0 `0 _( b, H5 S
| MCASP_TX_SYNCERROR6 O/ G+ a' j# P/ k! `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : m3 }& E) P8 X- `/ x8 l% `
| MCASP_RX_CLKFAIL
- n& d- V* F$ j% G- z| MCASP_RX_SYNCERROR
6 h( S, z6 Z( b# o% x9 B# O; M| MCASP_RX_OVERRUN);
0 q; B- N, |" [3 J0 @3 l8 `. D+ P} static void I2SDataTxRxActivate(void)
: W2 G7 o P: I. f1 `8 I7 M{
5 Q: C4 U( ~( B }/* Start the clocks */: Z2 T- e% ^" @( R* B6 R% F5 D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 h2 V/ X# H% X; J9 v9 i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; ~9 F$ b: G, _$ }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ T3 x7 ]7 R! k& H
EDMA3_TRIG_MODE_EVENT);( N$ ?# z/ p% T& q9 g8 k0 G! d6 v% k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) M) |% I5 v* P3 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. z6 B1 i/ \4 |. S9 S% w! _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ l7 \$ h3 y8 o5 s7 [* p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; }5 K% N5 Q1 k/ v6 Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ r9 Z" o( r; ]9 K" _. C! w8 wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 D2 w6 F) r/ F# o% d: GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% L: r" g5 `- A3 K# M# A7 o6 U: o} 1 ^6 r, B0 e7 ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. i: y, r0 j- q, \2 ]% p3 h
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