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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& A& v8 Y# _3 M
input mcasp_ahclkx,7 u2 [, r' @: q* O9 h, B
input mcasp_aclkx,
- e' }6 |9 k2 d, p3 N5 iinput axr0,
5 j G5 P3 L( Z
: X2 N3 q* e- o; L/ @3 w( Y; Coutput mcasp_afsr,! q: i- s# J; _7 i" S
output mcasp_ahclkr,
6 I( a% E6 i; g7 Aoutput mcasp_aclkr,& M! q, @# p$ t
output axr1,/ x) I/ t# z4 O0 z: A5 X) H
assign mcasp_afsr = mcasp_afsx;
" ?, V/ x9 _. {+ H0 e1 u( rassign mcasp_aclkr = mcasp_aclkx;: ]! v' t0 ^5 ?, \/ h+ ?, `% M
assign mcasp_ahclkr = mcasp_ahclkx;
1 A/ o) s6 |, n- S9 @assign axr1 = axr0;
! e3 b* h7 N( T/ }; \' c% [
( E5 E; X' [8 f% R5 c0 A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 W. v* L; n' {+ w2 A' I' ` x
static void McASPI2SConfigure(void)
8 O& u, o0 \# W& w: z, K{
1 z7 s- G4 e, H0 H: }& P! hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 p: a" i& U& ?9 R% z1 R; HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' h# L7 V8 P4 r/ q+ F% h7 k3 v9 EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! {3 n8 n# r1 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ a }( V! D& d" aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 j+ S+ R/ M3 w3 O( f+ K' |
MCASP_RX_MODE_DMA);
6 z- Y' X$ f& V2 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& C2 \3 n X. J1 l/ U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* t6 U2 i) \# |7 O! I# B. Q; {, Z6 _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 R' m, r+ I4 }* \; |. j! c* M) pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) U, J) c: | t& r. H* L! YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: g) H# n8 ?7 E( p9 YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 J' h; Q& p6 H* R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 D3 ^' C. ?' ~. q7 v3 j9 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 ^; q3 T0 L& g2 y2 y6 ^2 z& _, f4 ^- C4 uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( T* t+ `" I7 R" |! J% I; a
0x00, 0xFF); /* configure the clock for transmitter */
$ P, L' w2 c$ Y2 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 K3 t% z! w- l3 y) _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& A) w6 C7 P4 ?3 u; L! Y5 }; tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# W% e, S; e# J: r$ s0x00, 0xFF);) m0 x4 `# L+ h. m8 h9 \
% p6 Q' ?0 q' v2 w
/* Enable synchronization of RX and TX sections */ 1 p# {, Y, J2 u3 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 z! Q" c: c/ X& } WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ O% r8 A* p3 `! b7 H/ G$ ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" ?# p: { D) ]; i** Set the serializers, Currently only one serializer is set as
1 p" D1 q! z, Z' h" y: ]** transmitter and one serializer as receiver.
3 i% s9 F% P7 z- ]7 t- W5 l0 W) q*/$ b ~! L/ }5 a+ d, ~1 s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, u+ i7 c; {( p. p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 \1 Q& q0 } m6 g
** Configure the McASP pins o: H, X8 |+ V n
** Input - Frame Sync, Clock and Serializer Rx( @) ]4 _9 g8 u9 E
** Output - Serializer Tx is connected to the input of the codec 0 I* Q7 l. g3 }: J' z- e8 I# P
*/
: t! v# ~& b" x' D. UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ N2 J2 }+ }0 z4 M' N1 M0 Q" SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' S* k! c: X4 @5 R! b, C$ N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# f, u8 y2 g. K+ A# c6 ?2 D| MCASP_PIN_ACLKX
4 p) \0 G. c- p5 M5 T5 ?7 s| MCASP_PIN_AHCLKX
+ ^$ Y" A( I5 q) o( i, h j1 Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# k/ K5 q: s9 M/ s3 Z! }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 G- v0 p# W7 r! K" Q8 W% {6 \' F
| MCASP_TX_CLKFAIL + d% M" s6 ~( G- h6 m0 Y" d3 U
| MCASP_TX_SYNCERROR
! ]/ ^3 J9 B8 l9 Z0 k/ r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 c0 j- h- m- I1 X+ z- B* B2 w- ~
| MCASP_RX_CLKFAIL" P& O- g# @6 F( }* b
| MCASP_RX_SYNCERROR ( f- g; E( r8 ]5 U/ k
| MCASP_RX_OVERRUN);
* p7 \$ k% i7 E# X. [; E y6 r} static void I2SDataTxRxActivate(void), n( M3 g1 {3 x; k
{% k# s' o f5 u% s i
/* Start the clocks */5 c* q k, \; ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! p, u( ^5 Z K+ ?- F$ M2 V5 c" JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& H0 v+ ^6 p& t2 ?, J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; u# N ]- x" z8 ]5 e
EDMA3_TRIG_MODE_EVENT);4 X( Q7 Q$ N0 z }' ~) \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 V; V2 i1 j1 a f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. q$ r/ P8 `& J# K6 N) b# E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ C9 H% s7 @- U# H- o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* s% ~, E1 j1 R3 }+ u& V8 Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# U+ @, f) [. A* F! \* |$ P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 l4 ^' `! d0 J3 t, m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 k+ \! B- U. b, _5 ]}
4 [& c6 l. B" o1 D2 ~( J6 @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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