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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 b6 \! r% A5 {& x' F* dinput mcasp_ahclkx,3 ?5 W( \0 K; h1 i# [
input mcasp_aclkx,
) ]8 T" W" n- ~( i5 Finput axr0,) f& O% x' y: b8 _" s+ [
! i- d9 P- @. h9 m* q b! c3 c; m; joutput mcasp_afsr,3 P" ~6 g. o3 w8 ]4 m) g, h, @. }1 y
output mcasp_ahclkr,1 F2 J: Q4 u; J) s2 r0 m% D3 ]( E( E
output mcasp_aclkr,( A2 i, [: |; @0 e" ]2 [5 O
output axr1,$ |* N7 S& J; G: X% A0 h! l5 a
assign mcasp_afsr = mcasp_afsx;3 |4 C# y W" \5 L/ a
assign mcasp_aclkr = mcasp_aclkx;
* J1 ]: {* i) oassign mcasp_ahclkr = mcasp_ahclkx;" d/ j: N+ D1 U& z
assign axr1 = axr0; / x( M' \ x0 y
5 a+ X& ~5 {8 ^! L# Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . i( n D5 u2 g9 a/ y: Z( ~& }' r8 Z) t5 l
static void McASPI2SConfigure(void)
; n- L. B' ~* i2 Z9 t{
( c, ~' R" \* H! V {, d% U' LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- A- u# o1 J$ u2 `) M' e- ~7 B1 r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 [/ Y- y5 a$ o4 \6 E o. qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); f) I3 E5 l' N/ B9 N$ n3 g" Z$ i: u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( q# |8 c- Z$ @' Z% |1 J& ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' g4 z5 ~4 F" f8 l2 e1 Q
MCASP_RX_MODE_DMA);
% g: n4 m! |# Q; ?% l7 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 P4 Y" t3 T4 b6 M h H$ Q( Z8 z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) h5 @# @/ Y6 W, Q/ m: @) AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 q* A. M6 m5 G0 X7 mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# a8 K5 w- [' K ]4 T# n8 ?' ]5 N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 }' ?9 J1 k. G4 M) g4 g" XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, ?9 f" g; S9 x# G n+ ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ \. J2 w- o3 j; j, e2 v9 v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); o/ G; b6 y/ e. k7 N* ` F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 y3 h& {6 j# J0 K# K4 U* i$ R
0x00, 0xFF); /* configure the clock for transmitter */5 S$ K8 A) y0 B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, g' O. |7 d- d, A2 u8 X! DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - ` }6 |, u. o |4 x4 G. c8 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% e2 v% o; n( Y( t2 i: l) H! y
0x00, 0xFF);0 Q3 L/ X' d2 t! z9 F
: H7 J o+ g2 s7 X2 A8 i% Y6 V$ \/* Enable synchronization of RX and TX sections */ ! P7 D: h4 g7 {" o: H- k* _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ N2 i. J* h5 v6 I- wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- ~. F8 m* x- w6 J* T; y S1 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ i! r u) h" J
** Set the serializers, Currently only one serializer is set as0 M5 ~7 Y" `, x* M$ U5 K; t$ O
** transmitter and one serializer as receiver.
7 M8 c: I6 p2 [*/
. @- q% N( v! tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( i: m) U$ X% M1 V/ T8 O" }' f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! t& @/ _7 V1 i9 S0 b** Configure the McASP pins
3 _7 Q/ A3 b% S# r G# g** Input - Frame Sync, Clock and Serializer Rx
0 K1 m# b" Y4 y$ m# L! Q** Output - Serializer Tx is connected to the input of the codec , {$ \3 a% ^+ h) ?6 C7 Q) v$ H. G
*/
4 D. X3 V0 X& z5 G3 D# \: A: FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. ]$ f% P/ x8 P) f3 M, u) {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 @2 b9 i+ E) \6 q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, T/ b* T6 V# @, B' [$ ] Z2 B1 Z
| MCASP_PIN_ACLKX, j2 F7 e/ e- ^9 P0 P+ x M) Z
| MCASP_PIN_AHCLKX$ R2 T2 L6 H6 J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) R! |9 H* c0 T6 L( Z9 ^8 HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' h s7 c, B+ Q8 j& Z| MCASP_TX_CLKFAIL . O- |' R- t5 } v* b2 Z3 ^& k
| MCASP_TX_SYNCERROR
; x7 F6 L" i a( o" F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * t8 O: Q( t# S0 X* G+ s: s; g
| MCASP_RX_CLKFAIL$ Y+ ^1 d T0 _$ Z
| MCASP_RX_SYNCERROR
- o" t9 Q: j( ?4 Y+ s; T" d| MCASP_RX_OVERRUN);' t( }) x$ P) ]# V( T! v8 M
} static void I2SDataTxRxActivate(void)
7 V( U# }3 {% Y v5 }; J{
( K8 P$ z! L' P) w/* Start the clocks */5 z6 Z5 D* ~6 a/ |: b8 n* ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- u: k7 ]% z$ ]* d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) a( p4 j, b; @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ f, J' {/ k8 y& S/ ^, V0 VEDMA3_TRIG_MODE_EVENT);
& q. X4 x$ R& JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" C$ R. x- [4 p, UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 l! f' i6 ~- W+ m# `$ w: }& y+ @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 y& F$ r+ Q5 cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 r( {) P( f' |" |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" u7 |# S+ {3 O3 t0 h- n* d( ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* @4 [/ j( E. m; G9 }- g7 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' n) c) h- b2 c& T8 B4 w* [
}
# y4 z1 W, x0 W: ]: \# i9 c1 P+ b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ b+ }9 R8 a" I( M
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