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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# ^9 y$ f3 o: t u0 W5 j4 M
input mcasp_ahclkx,7 t1 S% r$ _: J# I: R$ ^4 V* P
input mcasp_aclkx,6 n. A( K* x- L+ I: o$ n i! d
input axr0,
7 z% {6 @0 q3 I0 X: K0 n Q1 F% y% `+ N) F
output mcasp_afsr,& I( ~' a8 T: G& `0 r
output mcasp_ahclkr,
! l, v9 ^1 w7 houtput mcasp_aclkr,
* q* M+ c# M- M, [output axr1,
/ G* B5 L, G- R* ~2 N- z assign mcasp_afsr = mcasp_afsx;. z2 b: N& D" \2 ^
assign mcasp_aclkr = mcasp_aclkx;
9 o- T) U) ^7 Q0 f- sassign mcasp_ahclkr = mcasp_ahclkx;
( b& S. H& H& o: z2 c' }assign axr1 = axr0;
5 }! U% K3 y9 {/ `( s6 j& |: z5 _# y* E1 J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ u2 V* |% ]2 M$ E' n% `
static void McASPI2SConfigure(void)
' k1 ~; Y' r9 ]9 W/ S{3 u* q0 F* J1 m& q# A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, _1 y/ t, J/ B# ?) U9 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* O( y' e4 G8 o9 N- EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: {( f6 N( z9 K2 ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' N* M) S2 o' L, `6 s# H2 a0 Q3 QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% s; i6 |7 ^& Y/ { qMCASP_RX_MODE_DMA);
. b( p( Z0 r" G& {+ zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( q. y: W- `- V7 l# o* g" f0 V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 N( i2 C6 [7 ~: ~- PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 R$ X9 z3 N/ C; I" pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' \8 Q' d8 b: jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ H* T8 C9 |% r+ Z2 A5 G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" G9 m# j, Q. |$ R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 }; W- ^( W8 F" S PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + J) I; l0 M: F# b7 m# d6 x. F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ m+ ?: D, ~" R, S0x00, 0xFF); /* configure the clock for transmitter */
/ `7 ?4 L; w; TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 S6 d4 l7 Z0 Y9 [7 t6 r. bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + U) A, y! ~. q6 j3 E' x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 a6 B' H. W, x# q8 U! }
0x00, 0xFF);
! W" U* ^2 K6 \6 g1 p
8 U) P7 U. m* @/* Enable synchronization of RX and TX sections */
6 t+ G3 u3 H+ c- L3 S3 DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 }) K7 C/ I2 J# o9 ]$ {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ n: c0 b! Z4 LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** R+ R5 Z; Y- x( k
** Set the serializers, Currently only one serializer is set as
- m# v9 K& k8 `5 X3 T" V' p. V** transmitter and one serializer as receiver.
( M8 z5 a0 X" f2 J*/1 ]9 D2 s: a# _% L1 o% a2 i4 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 r5 M4 e$ K/ d& j, X8 X0 Z- z& yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- u N+ ?# ^$ h; H: Z2 Z8 R6 l
** Configure the McASP pins 3 w% E/ I4 C* c7 m; e4 s5 i# V# S, a% K
** Input - Frame Sync, Clock and Serializer Rx" @- @1 m1 D* C# }% k! {
** Output - Serializer Tx is connected to the input of the codec ( X* G9 c: l/ g, q& l% M! [
*/
- w0 H0 K+ G) w2 A3 D5 _" |. J! }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- v8 }# }& H! E0 d+ A$ t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 b: j, N8 X& F* [. L8 O. @5 N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 D; m9 {7 a4 H: `5 o F# ^| MCASP_PIN_ACLKX( V' r9 W* u& U
| MCASP_PIN_AHCLKX0 {; a5 Q5 Z/ B# o& \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& K! a' V: @7 }% hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 |3 F1 ^7 h4 D& N$ B, Y3 Y| MCASP_TX_CLKFAIL
2 n" L9 \4 k6 r9 p/ s* I| MCASP_TX_SYNCERROR5 ^- H6 u2 K/ Q. E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, c3 Y0 B& \, @7 ^, r7 U4 K| MCASP_RX_CLKFAIL
, l/ F. s& y" a N# G! S| MCASP_RX_SYNCERROR
: p5 P. i3 V& |" k. L| MCASP_RX_OVERRUN);
+ e( z% O: R4 v; b} static void I2SDataTxRxActivate(void)" G/ l3 i4 i$ J1 E/ Q3 n5 R" Q
{' H$ Z+ D8 H4 W5 H! q
/* Start the clocks */
' l" V& g9 f$ P) E! x0 EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* k0 w2 I& q1 x6 X9 j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 y/ y$ U( T" x/ v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 `+ H# ^$ p+ V- T8 w) Z0 B. |% E
EDMA3_TRIG_MODE_EVENT);4 e& i, T! z' d* _, Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 J# o) e h# t1 Z- SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, {7 P) J7 V! Z8 j6 _7 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ _% c: A) x1 z& a+ [2 w! h% s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: u0 N- V' t6 i5 g5 A$ g% ` ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ g$ Q" i/ q( w2 J5 i% V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& ?. a! _- O# K2 H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; f$ {; L1 ~& P- H: e+ D} @7 k% k- S# S$ w7 D- I. b/ ]" u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 n% e/ u) q/ Q* v* @6 P0 A! `: h
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