|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: a, h5 ~: M; c3 w! Y) kinput mcasp_ahclkx,) }$ A4 i6 }. B
input mcasp_aclkx,- }/ g+ a% E* O/ { x( s. W
input axr0,% h- s0 p1 X& A( J3 T4 j
2 w0 w9 @# E$ ~7 J, ?( i7 {) L
output mcasp_afsr,
2 l8 K: {# Q% u$ a* ?4 e Coutput mcasp_ahclkr,9 u" {1 ?( b& E+ D
output mcasp_aclkr,6 c! |( }( P' J4 w" N+ b% ]
output axr1,
( ~8 @) y# d4 j. | assign mcasp_afsr = mcasp_afsx;
( v8 Y$ x3 R: ~, z& _; ?assign mcasp_aclkr = mcasp_aclkx;
' l3 l/ w+ l C& C: N& \4 P: K1 c! F: tassign mcasp_ahclkr = mcasp_ahclkx;
' W/ x& C) l/ k# tassign axr1 = axr0; 0 ]6 w% d7 Y9 d, D6 E
) [/ B" ` w# }' W. k- h( i, _2 o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : R6 @( O! y/ ~1 l- ]6 `! y
static void McASPI2SConfigure(void)2 b0 I* j" J8 P5 l2 `
{
6 p) P! T& j2 M* PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 @- @+ E* e NMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 \# j6 w# T: i: Q4 s9 A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 v8 N3 S7 g8 W2 `) D! m. [5 j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 {/ k: m& n# D' A. nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, k2 {- i. E' r1 J, T+ O5 {2 t
MCASP_RX_MODE_DMA);2 r" a1 M, X: r$ ?& Q7 M+ {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 N; R, v- m# j; a' c7 E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ _. h- s7 `2 [* ?- o! cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 a5 H" Q4 z9 B( C1 ^+ D$ a$ [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, \0 _4 K c7 r9 w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( Y- K- D$ f' k: p: K# J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 f! y5 K" P0 x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 _7 j' ]6 b+ ^& B6 u! L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 d: J& h- D" TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* F" s) b) {- i! @7 ~- d* ~0x00, 0xFF); /* configure the clock for transmitter */: V% ^; O `; x: b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 p$ A" ?) X2 J7 f# \$ f9 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 T1 c0 x9 K/ `+ CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% z3 c9 n* [6 ]$ [" ~: r) \0x00, 0xFF);
" b2 R% Q5 P; p9 _, m
. u+ j* x+ }+ m# w4 y4 w& x* J/* Enable synchronization of RX and TX sections */ 7 o+ j H9 N8 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 j* ~1 o3 p, S. q* DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ ~6 W& F& d- l# f0 Q, i6 ]# I9 b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: F1 H2 V, K, f9 F7 x: f1 S6 Q** Set the serializers, Currently only one serializer is set as
* a' `0 v0 ^( d1 b. L" o** transmitter and one serializer as receiver.
; ^& P3 p! Q3 M- G7 y8 n6 W*/ _ e/ G9 N0 Q% @/ M! ~5 e6 f5 Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, t! E& X) i! G" d8 `1 s9 q U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# Y0 ~. x; C T* _3 X** Configure the McASP pins
9 ]; Q5 b! x2 M7 i2 O+ S** Input - Frame Sync, Clock and Serializer Rx0 H/ H4 x3 ?7 ?1 u Q
** Output - Serializer Tx is connected to the input of the codec " u4 W! Z4 q* V0 H h1 r1 U/ ^8 Q9 X: ^
*/
& U$ M( k6 b/ {. L! F( z! P [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& \7 |0 U% g+ R1 ^; |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 x& P' N& S' i& u. }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' A. y9 R/ M, J9 q2 j1 l| MCASP_PIN_ACLKX# N) }1 K6 z8 `( U( ]& e$ y& @
| MCASP_PIN_AHCLKX
* R; I% C( w8 g* [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 r7 ~" f: _! Q% k1 t" o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 C, R) ]; w" }: k6 U
| MCASP_TX_CLKFAIL # R2 U. t2 S+ x
| MCASP_TX_SYNCERROR
' S) q- K7 \4 |! m0 P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR L; G3 ^! P' q" m3 d( P& S
| MCASP_RX_CLKFAIL
8 ~2 H5 ~; c3 j+ I* W| MCASP_RX_SYNCERROR 7 j) g# f3 ?+ k' I. z( r" {
| MCASP_RX_OVERRUN);! E2 Z* K; a1 D
} static void I2SDataTxRxActivate(void)# b) ^, E4 q$ p
{2 J8 [: u1 G7 {2 Y
/* Start the clocks */$ P+ S# [% W1 J* P- U+ F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 w6 n) P- d% e9 \6 P+ I1 P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* j: [" e. x0 ]& l' B, b+ \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 O1 R" o: D' M
EDMA3_TRIG_MODE_EVENT);. F. D+ u$ m, ~1 E/ L- K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! o8 V3 Y7 A: XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( b% [" T8 \1 `- e2 h% N( s2 X( A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 X6 J1 n: |& {2 {1 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& ^8 M7 v+ c* mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ r, e, V' \+ r2 Z# o+ K6 s; N; SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 X. e, k2 k$ ?! [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: }' C! T. s9 _ V5 l. o2 N# m
} + V& X, O7 c$ G; L% C3 }8 {, {9 L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 t! w3 H# d& ?2 u; N4 Z
|