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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," z9 k. K# i( {
input mcasp_ahclkx,
$ L2 z- V! u; I! q1 Q2 a. L3 H' Minput mcasp_aclkx,
9 \5 M) f" \, R$ Kinput axr0,9 `1 F$ ^( m, A/ `. {
% D) i ~0 U! l/ i. joutput mcasp_afsr,
8 z; M( j; c/ ?# b6 y) r6 Toutput mcasp_ahclkr,* g9 Q9 i# {" C/ Y
output mcasp_aclkr,
. b) n$ K" U! Poutput axr1,
$ i7 N. ~$ e N- \9 W( p assign mcasp_afsr = mcasp_afsx;
) J; R, b6 W' D+ }5 B& Xassign mcasp_aclkr = mcasp_aclkx;' e- d* E! U o) X8 j9 A
assign mcasp_ahclkr = mcasp_ahclkx;6 @. n; q; E* X- A3 P
assign axr1 = axr0; ) J' G$ g( G! ~9 i2 t
2 C7 D- H% P9 h+ P A& E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 S% k7 D* g. }2 T$ cstatic void McASPI2SConfigure(void)( B. G9 P' c [9 u
{0 S7 C8 B- U/ b! X8 m2 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 {/ M* t6 u9 t/ D/ wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% p0 q: a1 u; X8 P& z0 O3 SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: t$ P6 a! I4 D" O8 H4 K3 p; _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" K" c. P. ?( QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: I9 I1 s0 u. \9 z- X/ B# s, {
MCASP_RX_MODE_DMA);
' M1 ?* o% g2 u# m: {( ]( |8 S7 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 |% {9 v$ H! d* v( M0 O' r8 V3 JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% \: c0 _# N7 p4 C: kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' A; w M% V; CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 F5 c. E% |" |2 ?$ z* o$ }/ V; ]7 @. ?: Q: HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' }8 U: ^7 ? c2 c1 s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 |0 f0 q& V/ H) W5 z8 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& g- l: s& z- j# n1 c2 gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 f% k1 ]4 C2 E s. {3 R$ [' jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( F# L4 k& s: t# I# F; c0x00, 0xFF); /* configure the clock for transmitter */! z. g! Q, P. L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! V6 j; e0 |3 |' G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; i9 C/ Q- Q- j: H4 o2 i- OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 q8 k" t& e8 \$ n0 o) }0x00, 0xFF);- P$ E' v+ L# X: _9 `. A
8 Z! {1 R3 H9 ^2 o
/* Enable synchronization of RX and TX sections */ : i9 L- P7 M# {2 R1 q0 E* d' l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 N- L! K& W$ Z' |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. w- D6 w$ X8 g- OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; ?* t' ]4 l. `2 j' q3 v# f
** Set the serializers, Currently only one serializer is set as O6 o" Q' R' M) V
** transmitter and one serializer as receiver.$ T5 |1 l( O3 Z! I
*/: U6 l, B6 T7 h. `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 H) J. S' e) o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; g. O& F* T: I; V** Configure the McASP pins 5 h/ v, O* F) @* c9 w- l5 w, }$ `) A, u
** Input - Frame Sync, Clock and Serializer Rx
* ?; k% d4 N3 g7 d' r7 J: ?** Output - Serializer Tx is connected to the input of the codec 7 Y. g. C" }# M, ^7 z
*/) p/ p+ @0 B, f1 B& v2 R: Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# X) u! J9 }$ ] K! z1 Z: t% H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 q) k2 Z# r+ ^$ C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' O- \5 O: K" |. E| MCASP_PIN_ACLKX
* Y6 ^. `# ]/ I. D% I- ~| MCASP_PIN_AHCLKX4 i3 W; _6 {8 @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. N9 |8 n; x# ~: i' V, q! }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* R. j6 b4 n, j6 E| MCASP_TX_CLKFAIL
* ?' T1 ~1 i- e& M R$ l" T1 n# Z| MCASP_TX_SYNCERROR
* I K, E+ x7 M: Z( Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - |- }2 w1 x5 z: Y- x2 [
| MCASP_RX_CLKFAIL% Y J( b- F i0 t: q" F5 p
| MCASP_RX_SYNCERROR - M$ K1 Q6 J! R/ \2 O1 U
| MCASP_RX_OVERRUN);
1 E: }, S1 X Z2 j} static void I2SDataTxRxActivate(void)' h6 |" y/ `3 d# y
{9 F% x4 R) n( M, }4 i9 P( o
/* Start the clocks */
h4 ? u7 Z9 {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' z+ |* M, t5 ~2 F; @. W- NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. K, t! }' @! EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 a: ]; V& v3 p% z2 _EDMA3_TRIG_MODE_EVENT);* z8 y u& w) x7 K5 }; c4 B- Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 H- M$ j- q! s' `6 M$ uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ x1 f7 s, p$ b, }4 B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& c1 K" ~8 L1 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 W3 p6 `0 v0 P5 D; O, F8 K/ l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) B" I; `1 j) }9 A) T6 C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 M+ }& a/ l6 W' L: y% a* c3 L$ L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: P* X( J7 R3 @1 N( C
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3 ], I0 E* g* F# A6 M! H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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