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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" f, J# b5 O4 d8 ] ^2 E: uinput mcasp_ahclkx,
" ?/ g" R: z8 Q% G5 minput mcasp_aclkx,
9 t% |; X2 h$ Q% i3 Einput axr0,
6 g) o( ^1 ?0 {: ^( [+ P: t7 P% ^ s7 S |* _4 B) U
output mcasp_afsr,
+ y% K5 w8 x b/ Youtput mcasp_ahclkr,% p I5 _4 ?- l9 H
output mcasp_aclkr,
* d& A% ?9 [" coutput axr1,! p* S) l. y% U9 f2 @$ M
assign mcasp_afsr = mcasp_afsx;% C E4 Q' K3 A4 \; C9 G# M) b. i
assign mcasp_aclkr = mcasp_aclkx;' C* p3 E, i+ t5 G
assign mcasp_ahclkr = mcasp_ahclkx;. l$ f& O$ @7 P- Y5 t( z' K
assign axr1 = axr0;
+ C1 C8 S0 F( k$ ^: ~2 c2 q R! `" N, V, w' W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 H0 t6 w! p: I+ ?5 B+ N3 D
static void McASPI2SConfigure(void)
" z6 u% B& J, p# q; m9 t{
0 Q F% R; F! |5 \* {3 B4 e: UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( P, L M* k) W3 [8 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# p7 A. B& z, Y8 \6 ]) _, pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( q: r% Z, @2 F% Z, KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# @% X/ f/ E* D1 D7 MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, ]$ S% V& W. ~- X" X: A; ^ F
MCASP_RX_MODE_DMA);
5 _3 y5 ~0 l' Z9 S$ cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- }6 _+ F! u) h2 I+ l9 w* pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. c9 o/ {2 Q; C2 i8 I* J# jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
Z+ R5 C. l& hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. t% M2 d) o3 [4 r7 x+ }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - w1 a) }: c0 {% |6 B" A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. U d# F/ j/ L7 p1 S, vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) {" X& u" v, M; ~1 V5 }) B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 |( Q3 D2 F: f6 b; [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," v! [' Z; ]* P% z. T
0x00, 0xFF); /* configure the clock for transmitter */
( Z7 K0 h9 L }# ?4 ~. X( aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 q, M0 J8 D* ^- x- N+ H, VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 b2 n$ z" z r8 F" U* J# ?5 h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# n: C, F, C4 w! ]6 s: u
0x00, 0xFF);
; H+ J$ K0 O% l8 R3 B7 F$ E. a0 e
6 ?: L; F; i6 _# |% L2 \$ p4 c4 E/* Enable synchronization of RX and TX sections */ / a6 m( \7 e3 O% r( U( s ^$ ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ v+ k6 l- V% _ G. W# B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ @4 k/ N6 U6 _$ y! z+ qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- X+ I: H. W/ v9 k
** Set the serializers, Currently only one serializer is set as
5 N0 t7 H& _( g2 P, w" n** transmitter and one serializer as receiver.
5 Q4 m; E5 u- e/ y1 V8 x2 e$ M- c*/% z. E3 ? |* V j' }( s% z( m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
C! P, C' k% \, R/ l: W, s7 J7 xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 v' c& ]- h) |$ ~
** Configure the McASP pins ! R! J5 [8 g1 b" J8 {# n0 u
** Input - Frame Sync, Clock and Serializer Rx
% X7 b' ]( \' M0 @, w Q3 W** Output - Serializer Tx is connected to the input of the codec " A+ z. b) `- z ~" b% U) Q
*/
* R* b; b5 b+ _2 U6 B. o7 i, {. IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 ?1 C7 S8 H* V, v& NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( n7 L0 ~. Z/ C7 C1 t" A% U, h o# Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 b* Z" I- X1 k# I% k' b g+ @
| MCASP_PIN_ACLKX
3 z/ x) t& j- ~6 I" j$ `1 x| MCASP_PIN_AHCLKX
; y% Z$ y7 h# z9 H% N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 H) J$ [+ ?& R- |, \: z. |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! r7 b( [+ p/ c| MCASP_TX_CLKFAIL
6 s5 ~2 [, o) h/ y0 r& r. q& X| MCASP_TX_SYNCERROR
# p% Z& z% g3 X* v* z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . N/ a* t2 C6 q2 R
| MCASP_RX_CLKFAIL3 |& c9 ^' a0 ]! N& g) ?2 |
| MCASP_RX_SYNCERROR
; }' T$ v! W. d8 l5 Y/ h| MCASP_RX_OVERRUN);- d& _/ S- s \( t2 B E
} static void I2SDataTxRxActivate(void): p& E0 \& x6 o* k Z3 z X& k
{
- E# v) u; d' n8 I/* Start the clocks */* M+ ?5 _* S* D+ G6 _3 p7 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ {( o! ~+ Z3 ]" d% N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ q- n6 `' l+ Y6 ^; K, SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, s# l, W* l& }. l) ^: DEDMA3_TRIG_MODE_EVENT);8 R7 G& j* ^; c# S# o$ F7 X9 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # U' a- \0 M' C6 v9 d3 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) h2 ~' t, \! DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- Y2 m* N/ P7 I1 U( k9 H9 C! c# v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- K+ Q+ z1 y3 K1 T+ a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& X2 ^" Z7 t. cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. e; j& }7 Z+ I; [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 w3 M( O& U1 \
} 9 f, n, \( q# B# b1 H6 o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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