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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* x, \# y5 K6 Z5 X1 oinput mcasp_ahclkx,9 `+ S7 [' g0 v: ?- J# M
input mcasp_aclkx,% p' n' f3 z! h$ a7 P. r
input axr0,
& `( o# ?$ g+ j- l. O4 J+ {* r2 |! o. Z; P/ p
output mcasp_afsr,' `) j0 i' Y: |
output mcasp_ahclkr,0 ?2 N7 h) `6 ~3 v5 j
output mcasp_aclkr,
5 f0 D1 [, V+ u* S# l$ L" Foutput axr1," W @: N* m) U8 [! o# {! ^
assign mcasp_afsr = mcasp_afsx;! G1 ~( O! v* j/ M/ y# r7 P
assign mcasp_aclkr = mcasp_aclkx;
2 m0 i$ k+ |3 y* X7 |8 zassign mcasp_ahclkr = mcasp_ahclkx;" k/ J8 Z; C o
assign axr1 = axr0; ) a+ {! d. H3 O& v) _. h& B% o: E! N8 x
# T! w/ Z6 J9 f0 L6 u+ S9 _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; T, @1 k& s% R4 l# [
static void McASPI2SConfigure(void)9 d' N7 ^- K, B! R, C
{
- D! u1 Z# N! n2 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" w0 Z. P9 P. r: h. e2 C5 sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" t. f4 v7 m+ m b+ M& Y/ j- a4 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); Q c% |9 M# j0 V$ G3 Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// T) l7 a2 I. H6 c$ B2 q! u, G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 O: K' O+ i, M! t7 u
MCASP_RX_MODE_DMA);3 `0 M$ E. Y6 f# \/ z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: E- t" x, y4 f( n" ]$ i3 d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ C7 f/ J0 Y, ^- w4 @, Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & `$ f$ _# S* w. Z3 i9 N! D: `& b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 _2 c2 r$ D7 ?& Q; n" i; MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 I: X: N' ?" U" Q# t5 `# aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ w9 n/ O4 G' _0 P, C( UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; S8 H ^/ p5 ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- l9 |4 w8 s3 @5 g6 ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 A4 v* O6 \0 r8 h- T% u
0x00, 0xFF); /* configure the clock for transmitter */
4 Z4 y( _* F3 L# k/ }( tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 K$ u8 m. @ @7 C5 i5 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, J$ d; g, i# cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& b' j; z- S* b% g+ z
0x00, 0xFF);, c9 l$ }, g% I5 B( r. N7 X' n
- A. m, {6 d2 U/ C! _; _/* Enable synchronization of RX and TX sections */
; g$ E* L, m/ t' k/ _2 H0 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 u8 K: l1 h! d2 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% @- N9 Z) g* H% n/ L- R6 m5 Z) M* vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; Y( f6 x6 t1 |4 s7 h+ S( C9 M
** Set the serializers, Currently only one serializer is set as
& I; i4 t/ H4 |6 t) Y1 P* G; E** transmitter and one serializer as receiver.- x2 h ~7 [2 R. {7 b; E9 @
*/2 o+ k G, H2 `' Z' X g1 X, h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ c: V3 M, a+ h: ?3 q' \: N' J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% n3 W! P1 N) T5 h/ l5 I7 X6 ? d
** Configure the McASP pins
6 A1 l4 n3 @; ^2 {( H** Input - Frame Sync, Clock and Serializer Rx7 m4 Y2 r0 \$ K x7 n+ ~* u
** Output - Serializer Tx is connected to the input of the codec
; L, U2 r- a S+ f*// \ P `+ z% D; z0 k4 A8 G/ g% o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) X; N6 b; S+ T5 w# K0 M7 x) eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& i1 `# | o9 B# i* [" A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' b! N/ }# b$ O. `- L4 H3 U| MCASP_PIN_ACLKX
$ r6 s0 D) X: \- X| MCASP_PIN_AHCLKX
0 ~& v' X/ n# r8 o! B/ J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# C: r: z3 S3 m/ J3 n/ |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& Z2 j4 k+ c ?' i| MCASP_TX_CLKFAIL
; z! e3 f# f F n$ _| MCASP_TX_SYNCERROR
) f: b+ ^; [1 P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; k, t; i: B& r3 W; l
| MCASP_RX_CLKFAIL
r/ l4 [' {1 }: |/ f, d7 d| MCASP_RX_SYNCERROR 1 e8 V8 C$ {; N5 R$ K! l
| MCASP_RX_OVERRUN);) ~0 w8 b! W) M; ?/ U1 g- X, K
} static void I2SDataTxRxActivate(void)
# ^; v( V. v/ P2 x{
* I$ P: M. ]6 x$ D( J$ W( r+ K( Z/* Start the clocks */
5 b) o* Q& {' b$ O3 h; oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" \8 K+ A1 r. i7 ]2 \3 qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 }' G; t9 f5 S3 `4 N% ?# CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! I- b4 v4 V* q) rEDMA3_TRIG_MODE_EVENT);8 j4 U4 u$ r+ |& t3 {! R1 [: f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' t3 K0 J4 q5 C# zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% D7 D3 C2 p' M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ B) C. x: f7 w1 y* v0 ]! K# q; ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; |; L. E* Z9 s e/ K4 c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; C1 A- S/ c$ f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, i3 X2 |1 t* V% }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% K( K- P2 w# H, S
}
- [+ U4 I6 I! Q; P8 g1 _& I1 k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % o' o: {; `6 P! i
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