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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 Y, N- A' L* y( s' w3 ]$ xinput mcasp_ahclkx,
, F% ~; k& v% _& ^& t: h% pinput mcasp_aclkx, n% D+ @" ]: U- v
input axr0,3 _& g/ N- f$ V4 S4 x
) H7 q3 j+ r; B' z, ]- Zoutput mcasp_afsr,% I- F, S! X0 e8 R
output mcasp_ahclkr,
: ?7 t7 Y( I0 \( }; aoutput mcasp_aclkr,
9 m* T5 d1 i: Voutput axr1,6 }! b& F2 } L; Q2 I, k
assign mcasp_afsr = mcasp_afsx;
( t# {+ o& H- S- e0 Oassign mcasp_aclkr = mcasp_aclkx;
6 {" F/ v" A1 m) a% lassign mcasp_ahclkr = mcasp_ahclkx;
/ a# o0 R4 q2 K8 U, Vassign axr1 = axr0; 4 o4 G4 u; ?4 u6 e% B9 b
* ]' f' Z; n: ?& Y6 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
e4 ]$ j7 X, J! K, F' O% a3 P/ `static void McASPI2SConfigure(void)
% h; l4 k. V' @. y{
. W5 h! z# M5 P5 x5 a) HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 j! R9 O4 u- i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& Y, K$ t) k% u" _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. f6 u E7 t1 s1 g8 b3 }3 ]( w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& N! @! c9 V! k# I4 N8 [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! z( }# }& h# c
MCASP_RX_MODE_DMA);" i' t, ?: J: x) e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, i. P' k* V3 z( n0 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( r5 L9 D3 ~5 q9 ], eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ ^# i) }6 p% M1 Z3 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* G# J# {5 N3 {5 |- }1 H8 sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( s1 D% n) d$ i8 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- s, r+ d* G3 [' M. H8 ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% [2 _2 m: [4 x8 s, A2 `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * K2 D9 w$ _% o4 R# l' u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* V- v5 ~3 y( @7 F+ z1 D0x00, 0xFF); /* configure the clock for transmitter */2 h) [) d" S% V* l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! {9 u* b, B* q) ?2 Y6 ? fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + y% K- V/ \: M1 m) k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% A& d- K: ^/ J# o/ h( t) z& H0 j4 G0x00, 0xFF);! M9 f+ _" M# K9 J; y! N
/ S$ ~1 S. d. ]
/* Enable synchronization of RX and TX sections */ ) D( X1 J9 }, G+ G% n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. f3 L/ G! o1 {# L X4 n' bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; x6 R1 N2 Y! l& v2 pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 S9 q6 |4 g/ u: A; Z; v** Set the serializers, Currently only one serializer is set as
" {8 P( C4 n0 q$ t** transmitter and one serializer as receiver.
$ G4 | e* y1 N6 ^3 O) H4 w*/
3 J" G$ J% N- r0 ?, [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, U# F5 [- C9 | j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# p% m$ \4 a- F** Configure the McASP pins ~8 }* q: e9 q; v) W' X
** Input - Frame Sync, Clock and Serializer Rx" |, r/ w* h, d6 S( k- G
** Output - Serializer Tx is connected to the input of the codec
$ w+ \# c$ {, V5 ~( D- e*/* Z9 t4 z# }6 b; F7 l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 l# h9 M: Q8 w' L3 `3 yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: E- ]6 F w- ^' ?+ S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ r3 f; @" }$ |+ s% f u h| MCASP_PIN_ACLKX z# V7 f8 a0 x
| MCASP_PIN_AHCLKX
0 M6 @# O; U* c. @% U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; s- ^0 p* a2 rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( ^! D- L* b( {( q
| MCASP_TX_CLKFAIL ; V5 J) h% |1 B- d0 P4 L
| MCASP_TX_SYNCERROR
" ^/ p3 {0 C8 e- [$ d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' z1 ?2 u; ?( n8 t1 B2 ^" O X
| MCASP_RX_CLKFAIL/ Q- b6 k+ _- I! }+ h$ A- c
| MCASP_RX_SYNCERROR
8 Q, G* U$ ~$ ]& S5 P" B7 {| MCASP_RX_OVERRUN);0 o3 j1 S* R( o$ s) c g
} static void I2SDataTxRxActivate(void)
, N$ {0 }" _ \+ T{
% c9 S: e4 r4 J/ R' w/* Start the clocks */
# y6 e" y. q* q# S- E6 [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, I @, } Z1 o5 C9 }( o6 NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ m% n$ a! V8 t3 ?% c* T4 L' k* Y7 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, i( s4 F' T) C# t+ \9 Y
EDMA3_TRIG_MODE_EVENT);
$ R5 p: ^! b) G% i( y' u( s! zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 `( c7 J/ m: n; u/ y$ S6 S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# Z) M& K6 L6 O4 R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! I5 D. Q3 }' R* u. b1 [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 T" c/ x% F$ c- ]8 I% E" c. o. Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, o5 q$ i4 q+ J* \. s3 `1 s0 UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 H" [8 S( G0 u, q7 Y$ P! |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 m% m9 j" u4 r0 d) S} - z5 `$ q8 J$ o- Q) e" _( W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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