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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 d: ]; }) p" W: ]! t( u. M+ F" Hinput mcasp_ahclkx,2 y; k' ~1 G+ Q9 w9 [# U
input mcasp_aclkx," D. a- I3 a6 z. K! r2 V
input axr0,
l: ^0 m( k: M3 |3 y( s& u: }5 q9 x: }- L$ r7 H2 R- `
output mcasp_afsr,
3 L- i1 K& u6 R! woutput mcasp_ahclkr,5 d" S" A9 D r& ^
output mcasp_aclkr,, m6 U+ B4 N( R8 E
output axr1,
( }" S+ _. g" D/ ]) ?: C assign mcasp_afsr = mcasp_afsx;
/ H* ~0 Z3 B3 A4 k3 T4 Cassign mcasp_aclkr = mcasp_aclkx;
: {- X; e, n" J) u# `assign mcasp_ahclkr = mcasp_ahclkx;& C, b" X. D) p% U
assign axr1 = axr0;
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: l) f) a; @& ~$ L5 N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 @+ f7 O) P7 @
static void McASPI2SConfigure(void)
; K5 M! v% c* Z9 W! v{
' K4 e- W. V U8 V. [$ L4 p% m$ d! yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 G% p$ {8 a# p1 a3 \6 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 g! Y0 R0 N1 f; ?- _6 }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! M" t0 r. D- _8 \3 W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 n5 s3 K* c3 {- |2 i( Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 _2 H. T* R8 M
MCASP_RX_MODE_DMA);
: B6 i# U5 \* y5 l3 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' G5 z4 U9 t/ KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 {. v H) M0 z3 g9 P2 b1 F: J9 H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 f% O9 k( h; ^4 A" d, W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 }( G' c4 g7 q) u9 D" ^! v2 \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* J8 N3 S; J D% z0 [$ NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& V& f E0 U+ f2 }' O4 H" E$ X6 p# b/ }8 O6 jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& N" o9 B0 z' i0 bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & H L' O; r, Z% s% A4 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 u0 w7 K! r, K0 [0x00, 0xFF); /* configure the clock for transmitter */0 B: x/ v/ ^7 B( S) Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 Q* A/ Z& k7 O' {% [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" {7 b- b9 ~$ o% Y5 C8 v8 ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 c, y! I$ n, V7 v0x00, 0xFF);2 z! {4 D/ N/ L @# e$ z7 z, w
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/* Enable synchronization of RX and TX sections */
3 N' ~$ O8 |8 B! VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. j7 `3 j I! k; h- D2 {" k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" H# e8 a8 \2 K& E( h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 f% B$ q7 o* N7 a( C** Set the serializers, Currently only one serializer is set as. s; ~* b& m! ?! `1 c% j |
** transmitter and one serializer as receiver.7 n$ M3 e# i" K! K8 G, u( G6 Z
*/4 o# h( `( z& I8 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( r! \7 o+ Y- h
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& Z2 c& H6 L! K6 v$ E3 N
** Configure the McASP pins 2 M' _% {; B( ^9 r9 q2 h
** Input - Frame Sync, Clock and Serializer Rx% v6 e6 O7 y' ?- O
** Output - Serializer Tx is connected to the input of the codec 5 S/ G4 [, C' p* J$ A) c
*/5 j& ]9 y/ ~- j% z) b; J# m# R" l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 g3 F7 F, V4 _0 X; o9 a5 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; j F9 U) [% Q! T: v% [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 L, F& C9 G- C4 R7 i9 r| MCASP_PIN_ACLKX' Z6 \9 p9 @- R0 y* x% S4 |
| MCASP_PIN_AHCLKX2 k# G' n% w2 t# R2 s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* P" B5 e# c, x2 R" o! JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 N1 J1 C# S4 |) }3 q7 t: k }+ C
| MCASP_TX_CLKFAIL % n$ n7 s0 [. U( b* R
| MCASP_TX_SYNCERROR/ u9 l4 S1 s5 f' I" w0 o) A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & _4 f& s- {- q/ q& K
| MCASP_RX_CLKFAIL
/ Z h0 @2 ^" p| MCASP_RX_SYNCERROR
: b. g: l% `) ?4 r3 f6 j$ C% N) b| MCASP_RX_OVERRUN);$ J* a$ R- `0 d, T
} static void I2SDataTxRxActivate(void)
t6 Y+ c# ?& C+ q{) c& m& p1 o% r! J# p6 O
/* Start the clocks */, V7 f# }: v' v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ ?' W4 k. d7 Z# pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& k3 R. d* ~9 ?% l$ w+ N2 ^! {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 \1 {0 v3 H' k& H* ], @" G
EDMA3_TRIG_MODE_EVENT);
" M( T w, [, N1 R8 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 M7 ^" o! J r8 F& N6 y8 v# W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, z. o- \; w ^& ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 F/ P, X- j: D% \+ j- LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) j' ]2 k1 t$ zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 j: J& E# _7 q1 M( w/ r8 lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 W% U d" M( J5 R$ Q( g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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