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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 c; @8 }8 x; X* B# p$ e
input mcasp_ahclkx,$ r8 A6 c+ {, ^0 N, h3 p6 d
input mcasp_aclkx,: v( `6 m! s) q
input axr0,
0 j* J$ k& M! m) V& n; X5 B/ _! {2 e( Z" M% f
output mcasp_afsr,# c- T4 \- q0 d; J. ~! @7 b
output mcasp_ahclkr,
4 [5 q0 `2 k) {. R0 s: Koutput mcasp_aclkr,5 f5 ?; |5 f; P( H5 `. [8 h7 [
output axr1,& t2 Y. u- C# [. [: d
assign mcasp_afsr = mcasp_afsx;
$ `$ {( a# R/ G0 g6 t: gassign mcasp_aclkr = mcasp_aclkx;
5 Q) n p1 P* D; m. gassign mcasp_ahclkr = mcasp_ahclkx;, T- q! |( L: X& f" @0 ^ i
assign axr1 = axr0; ) j) g( Q/ Q7 z! C
# {3 H# F. m( q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( f* q$ |! U1 d( I4 w) ~
static void McASPI2SConfigure(void)6 s4 \' f+ k. C( s; d! J
{
. M+ M$ t* h# i; ~- s! g DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 Y, ]0 ^8 N2 {4 Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 k$ ~- }' }8 g, V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! }! T: V2 c# B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 ?! q, I/ o; C# @0 c( B4 _% r. J7 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 ~0 ]: l" l0 q" PMCASP_RX_MODE_DMA);
; q+ j% S+ c2 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& W' L" @; X9 Q1 A9 s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ R1 Y2 u" P( H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : B4 z/ k# d i3 X& U* M( y! q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. r2 @! c4 l- s, T8 ^7 r( p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 E1 o" Z& Y! E5 R# \$ ^7 u3 \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ U' `5 u1 }" [/ a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); I$ \5 [* s1 Q+ I% y% ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , n' _9 e) ?* h. S% j5 p9 f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ U! b9 t8 Q- r7 p; F
0x00, 0xFF); /* configure the clock for transmitter */2 ?* z% S6 W5 T# N" H5 o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" S4 I Z5 u% v, L$ l# e" H. v! m; g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / w0 p% r! H" ^2 v0 X8 \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ x& y/ O4 G2 r R: W0x00, 0xFF);
! g1 \0 T7 j: ?2 a z# ], y. x& [7 a/ {
/* Enable synchronization of RX and TX sections */
8 F& S( S. B CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 ?2 G6 Y! o$ h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); [; o! g2 t$ T1 T- }- y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 [: b3 z' N: `. |
** Set the serializers, Currently only one serializer is set as
3 }1 G3 D% Q7 O5 {! C6 `% x** transmitter and one serializer as receiver.
! Z* v; m) g2 G; M*/" K, \7 C' p5 S, I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 D+ m% m, H& N8 i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% @; G5 X# J9 v; M
** Configure the McASP pins ) I# I# F' H4 V4 \4 Y
** Input - Frame Sync, Clock and Serializer Rx
* l; c. w, [ Y9 g& F** Output - Serializer Tx is connected to the input of the codec & P8 L' T z7 c2 f+ M" }2 j7 c& Z
*/
" H9 X( N/ v2 O. c, X6 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, f4 M" F. w; | @ t$ ~2 k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 a; p4 \% v1 u& f: N, m1 u' F5 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# N! o; Z: \2 k' v4 d3 F" J) N
| MCASP_PIN_ACLKX5 ~6 _7 B2 W8 A5 W8 U+ j
| MCASP_PIN_AHCLKX
$ ~" g* l5 ^2 z: Q) n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! j" y- c/ e- @# H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 W% o$ Q& w) Z$ A
| MCASP_TX_CLKFAIL
( h& L: T& `- @& A. q| MCASP_TX_SYNCERROR
0 f$ ]6 Q+ v" o0 H/ Y, y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; O; V. E/ j8 o( i( n! u8 Y/ o| MCASP_RX_CLKFAIL; \8 y/ V5 S, ?" R: z! t4 u8 B
| MCASP_RX_SYNCERROR
4 a# q5 c' E) V| MCASP_RX_OVERRUN);
7 Q/ Y( [/ e1 t9 z7 s- o+ ~} static void I2SDataTxRxActivate(void)
4 I3 ?/ F. m2 T{
" t. e1 Q! N! ^* e ~3 H* ^) R/* Start the clocks */
5 D b9 F- \+ V. E( K9 qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ Q7 x+ x, V1 j' h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ g7 `, U* a* ]1 ^& g7 h& c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 D9 r- {8 X4 oEDMA3_TRIG_MODE_EVENT);/ Q: [3 {4 w3 L& z( B; J2 b' M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 o1 q6 G$ n: P' F, P+ F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& X; A2 V- _! ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" g+ S/ F6 t' ]1 a J4 e/ aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 a- {" d/ q& X/ f* z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, @0 r1 l0 K6 J- a; a5 t; c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 }2 M( w8 P4 o. h# g p0 ~' p$ KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ z' K( Q1 ^) L, @, D
}
/ I4 g5 K* N/ {" q9 }5 b+ h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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