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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 \' D' p1 e0 ?% v- B) g
input mcasp_ahclkx,( Q; H3 G7 O v+ y6 t
input mcasp_aclkx,1 K/ Y* s( v/ N8 A4 C9 s5 d
input axr0,
5 U4 g6 E& B2 ~5 V: f d6 {! N H7 {
output mcasp_afsr,# m" C8 C6 t" z5 D8 v3 P7 {
output mcasp_ahclkr,: o# Z# ~2 T, O' Y- O0 ]
output mcasp_aclkr,
, N5 X7 n# D3 Goutput axr1,& s0 A- G9 R7 g
assign mcasp_afsr = mcasp_afsx;7 r% {8 F' s0 R6 T$ n1 V
assign mcasp_aclkr = mcasp_aclkx;; n5 M% E* `% x9 H" ?8 v l3 {
assign mcasp_ahclkr = mcasp_ahclkx;
1 @8 R; P0 b2 r0 x5 H5 Aassign axr1 = axr0; " `+ |9 Y i) X1 i+ Y& L
* F0 i$ t. x/ ?% ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 x1 V+ r8 v3 m' v& qstatic void McASPI2SConfigure(void)
2 H% j) ~$ u$ f{
! Y$ L ^' U3 |# AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! S" n% G: L9 b; x9 B; |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( I! f% a* U; f" U" K% g# t1 O& mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; }! {) S9 h) P, a5 ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ L/ q9 j* T# ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# W5 g6 _+ b- Z: P Q( v, b
MCASP_RX_MODE_DMA);- u( o/ P1 f: S: f) P3 G9 j: S5 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 u" r+ U+ g# wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ z7 Z+ H8 v: s Y9 m% P3 V/ _% aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 \2 v& d+ p4 C, eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 d5 H. k7 I- m1 X1 l5 P+ n' F4 n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( m6 c3 @) R' d0 }& {0 R: I2 D- ~4 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ L$ c, _2 X$ e' M5 H2 c+ _. y+ y& |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; w$ B8 n' K% B! ^" mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 M% ]/ `7 ] v4 d) B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 Z+ x: g- X' v @/ |8 ~% q8 v0x00, 0xFF); /* configure the clock for transmitter */4 i, R! a H/ `& H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 a4 \4 @- u; g6 W0 T' x; jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' d, {& M( y/ I3 i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 o$ u5 k* ]( n& S8 Y0x00, 0xFF);; z8 N+ t! K8 q# Z! V5 j
* l/ p( K b% i `( R1 b: b& ? b
/* Enable synchronization of RX and TX sections */ : t+ [! k, q3 }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ G( S3 l7 A+ A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 n, Y4 r0 Z, |0 M& D- jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 b; z. F* m+ L" Y
** Set the serializers, Currently only one serializer is set as$ y H: y3 S8 W' A' q8 L: ?3 k
** transmitter and one serializer as receiver.
( A) p1 l X) c6 p*/# S5 Y; ]4 X8 R: a: ?, {+ P1 S( g* e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 E2 X5 X5 _1 }7 N8 Y7 }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: k' R# P4 C5 J3 Z
** Configure the McASP pins ! Q- Y) u! d. @9 Q
** Input - Frame Sync, Clock and Serializer Rx
( P3 ]2 m* X1 P6 Z/ m, D& p3 u** Output - Serializer Tx is connected to the input of the codec
f. f7 ~9 }! i2 n7 m. B0 A8 A*/
+ R4 p) {$ t# X( B9 F7 L$ fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ ]& c2 ^7 t3 w7 z# B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 u) S" E) J6 r3 {! o, ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 V& k7 ]. W; r/ R
| MCASP_PIN_ACLKX2 R& h0 U8 ~1 ]# N
| MCASP_PIN_AHCLKX5 h- ?9 H. z2 a q7 Q5 R* Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& J; ^- z$ q* I7 Y( [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* @( W8 d9 d7 [+ G% [$ A3 p( x$ Q `| MCASP_TX_CLKFAIL
! M' `# u! `) N6 O9 S8 }. D d| MCASP_TX_SYNCERROR/ r* X( H' B G0 o" j3 T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: Y+ }% N8 u; G$ I0 p| MCASP_RX_CLKFAIL; u0 X9 w# ~: Q; s# j: x; ]
| MCASP_RX_SYNCERROR
6 y8 `0 r# q" Q$ ]# q| MCASP_RX_OVERRUN);' P6 D4 d; W% N0 M* c
} static void I2SDataTxRxActivate(void)# u5 U. I% e! V! v: n
{
$ @+ e6 Y; S- c( t/* Start the clocks */
" y$ }8 k2 e/ H/ y4 _& }! u3 jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) _' z( y& E! R+ ~: u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 q+ g2 k+ ?* r9 t: CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ [: [$ r- X/ Y, j7 f
EDMA3_TRIG_MODE_EVENT);
" n4 [8 t7 R9 T. u3 A, O* e4 r" ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 J. V. i% Z0 W/ a' `# f( X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 x+ \; M4 n, A, zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ S5 n, `4 s/ R1 D% ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, }# z4 J$ t: m' G, B; {0 O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. n3 ]. D7 { A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 O% h+ \* \5 T" q' j) |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" v+ }8 q) U# w7 r5 t
} ! P% f& b+ |7 F- J( {0 G& T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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