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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* J4 o! F! l8 i2 Q& U; A
input mcasp_ahclkx,
' w. S* p7 t5 `( ~' ]# ginput mcasp_aclkx,
: V! [7 C' ? |3 |! i$ l! T+ r# ~9 g0 minput axr0," V2 s7 U0 b4 Y% W/ \* }
# I$ P. g' f) E: N7 Q5 n! boutput mcasp_afsr,
7 @0 R/ ]% H' woutput mcasp_ahclkr,
* J) a+ p7 ]1 K: v$ `* ~output mcasp_aclkr,/ B. t! l8 ?* v* O% y& y
output axr1,7 q2 `" j, ~9 Y- e
assign mcasp_afsr = mcasp_afsx;) ]& l) P- e. }6 W# Y2 _
assign mcasp_aclkr = mcasp_aclkx;
- @" M% y' ~/ H5 r) dassign mcasp_ahclkr = mcasp_ahclkx;' U- E+ l( J# A" R* v" K/ @; B
assign axr1 = axr0;
/ H1 s6 m" y4 k5 }6 p6 k, z5 u7 K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
Q0 a' A0 ], B1 b. E2 {* S dstatic void McASPI2SConfigure(void)4 ?+ }3 ]# R1 T. N
{
1 J' b- R% ?5 h% q( ^, @: KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- Y+ } v% d+ }, ]- x0 C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' V |" {+ B, ]/ d& Y5 TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 g. x% h P1 aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ i: Q2 t; ?& z; uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 @0 P5 D6 O4 }8 {MCASP_RX_MODE_DMA);
1 j# ~9 O' ^8 B6 ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& X0 s7 _: E) ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& S$ |4 ]: d) N9 h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' `2 A4 a- p& C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# j+ q! e: g7 U) T1 \& L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( Z3 u2 F% h4 U) i3 A7 n2 M# D/ FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 G2 D8 t6 C# W* \( V4 p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 \# }- Z& h2 r6 zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! r% b/ l0 U) R* V9 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- [( x; `4 ]: M# R
0x00, 0xFF); /* configure the clock for transmitter */
3 C3 M. N6 O- X6 |$ LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
K3 R9 h+ a) g1 f9 [; V; I, ]3 m5 XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, Z0 l8 F: m9 S3 u4 P6 I. UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 g _& _& ]; s) E7 o( E0x00, 0xFF);
8 ^0 D7 S: L g. J& T9 ?0 Y* w1 o3 r! A4 h' N
/* Enable synchronization of RX and TX sections */ # ~1 \5 }& O; S( k- m) |7 R8 Y {; b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. @" U+ T! P* ~0 g" Q0 H) R- d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, I: P: p/ O! K% v" a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& z1 w9 J1 G6 T- [% b; M
** Set the serializers, Currently only one serializer is set as' {: x) P" K/ f' E6 a: U. y
** transmitter and one serializer as receiver.
0 E9 d$ T4 A; V# Y: G) T6 t; d*/: }6 m. T" N: o. \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); c K5 `4 e( U2 u0 F/ W( m( p0 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ j( V! I2 Y: S* r j4 m: g
** Configure the McASP pins - v0 x6 { @2 ]7 j4 a$ Z- {+ w
** Input - Frame Sync, Clock and Serializer Rx
. o# Q! B' k1 x Y3 f5 q** Output - Serializer Tx is connected to the input of the codec
( Q0 z4 @$ z7 u& R*/
. b2 ^3 _+ v" r7 fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 x5 q8 k2 f8 ^* I5 UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" e4 L q; l: C$ f; W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" }5 {; \ s6 N; h0 {$ ^5 F
| MCASP_PIN_ACLKX
4 E/ m) i( X. P5 ] \) f% O P| MCASP_PIN_AHCLKX. ?: W' i6 W( @7 s: C: D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& y7 C5 G8 A9 ?( j+ {0 _% `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / @+ F3 h* m6 y4 @
| MCASP_TX_CLKFAIL
4 b7 {1 A& D% @( `0 X$ }6 \ `7 n| MCASP_TX_SYNCERROR
1 y& l# Z7 }: K7 Q+ j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( R5 \+ @9 `. \* `9 ~! T* Y
| MCASP_RX_CLKFAIL6 Z1 y: _! L0 q7 W% p; [
| MCASP_RX_SYNCERROR : K: @. U ^5 A% L
| MCASP_RX_OVERRUN);
; C: Z/ \ c7 r6 {! _ a' f5 B! e} static void I2SDataTxRxActivate(void)
$ ^8 G7 w" M* @4 F; |/ q{
4 g2 T* K' t8 x" w/* Start the clocks */ @; d$ N% g X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 b$ i$ \2 p9 L6 i. @/ ~2 \/ ~* f6 ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 C2 G* N+ |( l0 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 B6 ?2 H* J4 N- R g" p
EDMA3_TRIG_MODE_EVENT);% l1 l9 L3 V' u2 w; {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- g, b3 a, X8 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ n5 ^* D6 a& x& \8 r; FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! u" B+ ^, h- r2 \+ M0 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 P8 e% ~ c0 k) L9 d4 }1 F7 r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 g# @, e" }! l7 B0 y) t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: X5 g" m: |& k* r# z4 |. kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# f" n( R* @9 z \
}
6 F( M- |6 c4 z6 A& u" j7 U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 n4 S& L1 }* A8 }$ ]3 y. N2 `
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