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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, U) K' S% s9 [" ]' V2 F& w
input mcasp_ahclkx,: [/ `3 |8 G3 m4 Q7 o( u
input mcasp_aclkx,
% E: g' ~" ]/ e% g4 w9 Z' M; H7 V% Vinput axr0,
o; r: e# P" Q) D
5 I' ?- R6 o; s+ C. eoutput mcasp_afsr,
' ^+ I* l6 H6 H$ z) k. c6 @% }' eoutput mcasp_ahclkr,& w1 [/ p+ X( O
output mcasp_aclkr,( v( v( F: s$ Q3 W: L$ a+ @# F
output axr1,
* N) t8 |( Q' u9 b* b% d1 u9 F assign mcasp_afsr = mcasp_afsx;
" E$ |& U$ F0 f! m; V* F8 w8 `. iassign mcasp_aclkr = mcasp_aclkx;
, w* o/ b) \$ U0 K" p' yassign mcasp_ahclkr = mcasp_ahclkx;) B5 N( U: M- @
assign axr1 = axr0; 6 ?- j2 {: i2 ^
0 P5 L+ u: \) N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# C5 _% T: _$ zstatic void McASPI2SConfigure(void)
5 R: X3 E% z5 {7 X9 W{% y4 F7 x9 U+ y' `' `9 f5 O. X& R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" U5 U7 A- P2 [( L( |" @2 J* {! B% }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- b% F8 \3 A. k: `8 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- U: N S: b! F9 e1 d5 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! Y) q& }+ A3 d3 _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, ]2 \- `; z; h* k8 i1 \MCASP_RX_MODE_DMA);
$ Q- S& u3 d- a3 |6 c9 A( sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 n8 B# r4 l) C, X/ cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 \$ \8 r! f3 a2 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * v5 T d. u- e# ]& L& j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 L S d( O& R8 nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* N2 x6 ]) I- T0 K& P' o5 A5 pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ x I4 T! F0 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ |1 g* d# m) G! k$ o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 [) D0 w0 A# j: W& [# b) [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ t7 _! M( N5 J: P$ C
0x00, 0xFF); /* configure the clock for transmitter */5 n9 U$ z& l: u' w& b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 D; ?2 k: q' ]; }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 m2 |8 L( E; D$ i1 E a* T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. t# Y/ z9 Z7 z+ F8 o
0x00, 0xFF);
" t2 t; y% X) W$ K" J
& b, _% @2 [4 P. k: @/* Enable synchronization of RX and TX sections */
h H. o5 q; n( QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( x9 |0 w7 l" a9 c: o* Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 e. s( [" n* H/ b6 \. w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: d" w, e' k8 |5 F( j' d F** Set the serializers, Currently only one serializer is set as
7 R; {8 H }7 ^2 h; V** transmitter and one serializer as receiver.5 i0 d/ x* E" R H. \9 O! ]
*/
# e1 v( @7 f4 HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 w6 w$ _) `, M' cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 m, l: |, b+ q
** Configure the McASP pins
7 m7 ^7 E! k# @7 p% f" B** Input - Frame Sync, Clock and Serializer Rx
6 G+ J" S+ B. Y4 Y$ z** Output - Serializer Tx is connected to the input of the codec * o) h! B" d' a" ]- i8 X A$ H
*/4 g# p! S: X0 |) }7 R |, W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ J9 U6 [2 V( r+ SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ S/ [; {+ o, w5 b( h5 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; b% t" t S, Z U' m F- F3 Z: ^
| MCASP_PIN_ACLKX
$ M# b8 M/ M' C7 i| MCASP_PIN_AHCLKX
, M" @( [# j5 X% @; t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ q1 b9 h0 s' \% b! r9 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR O' ]- \# _9 _! c
| MCASP_TX_CLKFAIL
, t' o4 j, f7 Y| MCASP_TX_SYNCERROR G' }% w, x" ^' P$ e5 `4 C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 B7 v) {, s0 p" Q0 t' }| MCASP_RX_CLKFAIL
, V! H! w9 Y) ]* j5 S3 \" g3 R| MCASP_RX_SYNCERROR ) |; C7 |$ `! X2 {
| MCASP_RX_OVERRUN);
7 ?( T" {- n j" [4 w6 n3 g, r} static void I2SDataTxRxActivate(void): q6 b, B: d( m! x1 ?
{( A* z/ ^- b. A2 b
/* Start the clocks */
' v; z* |" c( \, }1 k" h/ ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! v% ^' I! m" G% ]% L7 l7 ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 C1 S/ {4 D+ r% ~) f- h0 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 J' d' H: V$ ` B5 x# M
EDMA3_TRIG_MODE_EVENT);2 D x! _ U3 L% ~0 E5 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 _5 W- ^8 K! r! c9 n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' O, K% z3 y& e- r' vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 q& [* @' Q4 E9 E& z: }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 T& q" k, o+ y1 k8 N+ ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 o7 b0 ]0 C2 U4 O( fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 z4 B2 C8 b* M) b e! i2 P$ _1 oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 ~6 {. j" B) |$ C
} " A3 ?9 d* ?: w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + L4 W# y* F5 c4 Z
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