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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% f% w- S- q& Y( X8 _input mcasp_ahclkx,
; n5 t) `' L5 [3 T" u4 R) ]* Hinput mcasp_aclkx,# J4 D, N1 B L: h! k! p7 S
input axr0,
/ F" O) y* T4 o' T4 x& h
# v1 |/ V7 T5 k5 h! S. ^output mcasp_afsr,6 Q2 l z# {1 o. ^
output mcasp_ahclkr,
+ _9 g+ b; f+ C joutput mcasp_aclkr,8 p: K e) R9 }) h8 f
output axr1,
. s5 A4 P( q$ C; Y assign mcasp_afsr = mcasp_afsx;
# d8 F8 h* M+ R5 H% k% B4 iassign mcasp_aclkr = mcasp_aclkx;
% G3 }$ j2 D' b7 Y9 Qassign mcasp_ahclkr = mcasp_ahclkx; h: x9 d6 i q9 y5 Y
assign axr1 = axr0;
9 t |4 M9 C; E# \3 W
6 A f2 J/ a& C6 {8 ~& P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, ~5 @8 e; L- f' R R6 Cstatic void McASPI2SConfigure(void)1 k/ N, f1 }8 X' y m4 d2 l
{
9 [0 E6 B3 s+ L7 a! QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* x6 V, V; w3 P; s. u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 _* n1 P/ X$ Y4 k& T+ HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. @: C, V- u4 C2 ]1 I4 mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 f9 N) w0 X' k Z- Z1 W' iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( i2 x( j' H" o0 i8 F* X' dMCASP_RX_MODE_DMA);
, t9 z! ~, Q9 X) oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' P& o. q3 u1 {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! ?5 r9 S4 j* _& @: _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 [/ c: c5 `2 B, K0 I; Y2 H5 R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" u: {. E7 E/ d9 z* n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- A. c5 K( t8 ~) d9 ]( u3 cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" {- c8 x8 @% T6 r7 E0 s8 |) |, D, [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 {% |$ \$ q" l3 lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( |% M3 V) |; I/ T* q0 _" I/ f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: H0 i/ d+ R6 x. ^$ j8 h# L! s4 }
0x00, 0xFF); /* configure the clock for transmitter */
- J4 @" A, B6 U5 \3 [0 Z, M/ SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( L: a( }- e9 M; j/ E+ G+ G! iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. W' e$ H0 L! Q8 c5 R2 q( AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 g2 v2 p4 B- S7 M5 N) r0x00, 0xFF);
9 q5 S" W3 {' e( C" m, R6 ?1 W1 h" Y: @2 K7 d
/* Enable synchronization of RX and TX sections */
* q9 M9 k& t- {* c6 ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( z( u0 t" v" |, |. ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, Q" ^' S- e) M$ D$ WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ s) h) r! G( T- _$ W# D8 R** Set the serializers, Currently only one serializer is set as
0 T( D2 I- k0 B' S# E** transmitter and one serializer as receiver.# o. c- Q' Y+ E# H# p0 F3 A
*/8 Z* p) R$ D: z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. @1 L! Y: \5 hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ E2 T \; c3 g6 V** Configure the McASP pins
. K2 A5 W/ x3 T** Input - Frame Sync, Clock and Serializer Rx1 W& |6 L5 Y. u
** Output - Serializer Tx is connected to the input of the codec ! Q+ j; X* P9 a! }3 ~9 \; r- b0 f, X, N
*/
( b3 G( w' i! U. d9 O' t' N% v2 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 d- v# `. g- n3 G+ D9 o% f- `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; ^1 r! [+ q# }5 C7 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ a4 L: u7 a/ E0 J
| MCASP_PIN_ACLKX
. R; A$ c# Q9 c, B5 [| MCASP_PIN_AHCLKX' u! ]$ s7 o, Q2 [0 |+ [8 n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. L8 |. u0 Y, W: G: A3 B9 oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 L0 w9 i) \2 r4 \" u- m| MCASP_TX_CLKFAIL 3 n% |2 W6 l+ v% {! [+ }
| MCASP_TX_SYNCERROR
9 o; x% b( a1 X. I. t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # h9 I2 m. Z- U3 i
| MCASP_RX_CLKFAIL0 u; w. n) L1 c! {! ?& `
| MCASP_RX_SYNCERROR
- \) H7 d. D* e6 s9 Q! T7 @" }5 I- H- e| MCASP_RX_OVERRUN);9 Q/ u; X: ~8 Z% A: c, \
} static void I2SDataTxRxActivate(void)
* E* ?* ^3 b* n8 `" P5 G0 K/ X{7 h4 t, b3 v9 Z' x7 ?4 z0 h6 M
/* Start the clocks *// c- x0 H t& {0 e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 C/ E- W$ Z. g$ l0 t) @+ CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- B5 o/ D4 q) F7 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 t1 N, Z' v' v$ {
EDMA3_TRIG_MODE_EVENT);
3 n- ^- Y1 [, b) g6 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, X- k0 J( u0 C$ q0 P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! B/ h- Z- y1 l) r* [& ~$ C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" y6 g2 ?& v% N2 v$ j: rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' J- X1 |' V, m: x3 K3 r. t/ ~) Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; A; {; |5 ]! X8 [; y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& Z& @* S" v1 ?, l8 o% l4 C @/ a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 s3 y6 A/ _& `1 N3 F} g; X4 _: `, f; _' p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & q; P4 k0 Q3 V, L- C
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