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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( P: ?/ `2 V ]* a& ~9 ?4 H
input mcasp_ahclkx,( [( v! H) G" B4 i5 d
input mcasp_aclkx,/ U. |3 F; J4 J7 q; c) F5 O
input axr0, I) W: Z& @% T) @ l9 E3 ?. h
7 o" r! ?: B# P& v+ S8 i* U1 S1 Uoutput mcasp_afsr,$ }+ y2 a" v1 q0 s# R& ?9 U$ V
output mcasp_ahclkr,
' l* _/ |; C5 [7 t7 I# xoutput mcasp_aclkr,1 _& P0 m% P" f7 B# w
output axr1,
! X2 K3 Y1 e/ ^7 M' y4 P$ f assign mcasp_afsr = mcasp_afsx;
) s" }# M- j7 B% l4 s vassign mcasp_aclkr = mcasp_aclkx;# _. y8 Z) \ O* w4 ?8 e( s
assign mcasp_ahclkr = mcasp_ahclkx;
* ^0 H4 N' V' Jassign axr1 = axr0; 3 F1 F) N0 ~" O, H
5 ~% O! c+ V. P: ], j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # X: Z$ o# e6 V- O7 K, R
static void McASPI2SConfigure(void)
8 V) \, ?2 a2 Y1 p7 n( U: @" l$ {{
6 p2 m1 W w. e3 ~3 @McASPRxReset(SOC_MCASP_0_CTRL_REGS);; f. ?: [) _# E: {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; A: m1 {. ` @* UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# I& Q5 C! A+ G* P9 |5 W0 R/ Q3 F5 c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. j2 e) u3 x# P% P9 j5 [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& m) T+ e9 B7 k6 x$ o9 e8 F
MCASP_RX_MODE_DMA);
w/ g: B# h2 T x6 U2 t. bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: w9 d- w+ ^. T4 E T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" c' C& m8 b4 h; lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 J8 M* s& x% O& g9 s8 \& QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! Y: b' r" q7 A' \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & `% ~7 g) r3 J0 S: S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 `) K4 R8 C$ M: D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 z( w. |& @; \: P% y! H/ i' s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " D; U6 ]" @- z- R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ z2 e T# q4 M0x00, 0xFF); /* configure the clock for transmitter */* U/ J, F" {2 N4 b0 t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* O+ [4 s/ n/ B- G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , ]1 H3 b( j* u0 f9 F+ B- B5 ]$ i+ q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 K* B' R% X3 ]3 w0x00, 0xFF); J) }& T. q# A) u# }
! Q' J( l; d+ U/ U) Z4 [# X: G/ @2 N
/* Enable synchronization of RX and TX sections */
/ V2 l( S" m' gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! _( a. Q5 \1 c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 r# J M5 e% o5 h3 Y( v: ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( O* L# Y e! C( N! y v5 V** Set the serializers, Currently only one serializer is set as( n/ z/ x9 k& J" x+ p# L: ?
** transmitter and one serializer as receiver.. Y9 x1 q% N5 ~$ c/ }" G. t
*/) |3 F1 X5 {- L2 L- @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; a, b3 P0 d H. A. Z' }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ w9 S$ E! Y' }** Configure the McASP pins % Y$ j1 [$ k) P: M7 O4 c* A( D6 v$ e
** Input - Frame Sync, Clock and Serializer Rx0 g3 n; M* _( B" z( D9 e" c( k
** Output - Serializer Tx is connected to the input of the codec . @5 M* D; P$ ^3 m U7 f" g, S
*/, D8 O, b, b; i& e9 N: y) j" ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% d- q- s' z9 l0 a+ A* bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* ]& p+ j o0 T8 c) WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 W5 ^/ l' v1 Q. M. j| MCASP_PIN_ACLKX4 n% ?, e4 p. h. g
| MCASP_PIN_AHCLKX6 R9 }* W- n, s S( R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ L0 N) ^: b* b/ I' n- [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& K# k* H2 J2 E, q/ I d9 D: U| MCASP_TX_CLKFAIL
. U$ d ~! _; U+ U) j) e| MCASP_TX_SYNCERROR" _: _1 T# s8 b+ v7 L4 x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! U4 Z* h+ v6 h: r5 P$ ?| MCASP_RX_CLKFAIL
6 e4 s: t, |7 [! O" O9 P| MCASP_RX_SYNCERROR
+ a* O5 P6 [* z; H- w# ]0 _! m! x| MCASP_RX_OVERRUN);) o' A) W" e9 I0 U, i3 n* T1 S
} static void I2SDataTxRxActivate(void)5 E( N9 B& a" X
{4 u) _& y6 m# w/ T: q
/* Start the clocks */( G0 ]+ g# ]. ^+ S, \$ r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, v2 x" p4 R4 V, {) w; \! }3 tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 d+ v) a4 G9 \2 z: B& J" eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 L8 l2 l4 o# D0 e1 {( p, x
EDMA3_TRIG_MODE_EVENT);
2 m6 E; x. {* M3 ^2 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ x7 B: { V& P6 U3 _( C& SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( O8 q; P* y( e0 MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 J1 _+ c& h+ n( e4 ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 |# K& ]8 b' d8 X( ]2 I$ n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
}3 a$ ?9 e3 j# x# G6 X) SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 L1 B6 J% r8 ~+ |( o$ N$ h9 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# a/ V$ {9 s; F5 m
} / P2 A' z% J) i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
6 |8 g: V0 B% {0 ^( x% e |