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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 g# M9 e* c4 A( N: Minput mcasp_ahclkx, g/ S9 z' V; R! w B4 z
input mcasp_aclkx,; G- `% V. @8 ~( Z
input axr0,1 ]- A ]/ a1 ~+ K& y1 x
) q1 a n& z7 L1 `
output mcasp_afsr,
+ i' h: K5 M. Ioutput mcasp_ahclkr,
6 p; |; ]" H* I9 P2 ioutput mcasp_aclkr,; R' ?1 ~ f+ @+ {5 J7 s/ G2 N
output axr1, {6 A' F+ E/ H8 Y w
assign mcasp_afsr = mcasp_afsx;* T- u0 D8 ]: Z" e6 k+ M7 m
assign mcasp_aclkr = mcasp_aclkx;
( B# R7 v+ }: n. xassign mcasp_ahclkr = mcasp_ahclkx;
- Y8 \* g! g' F; {assign axr1 = axr0;
* c! B( Y R5 C/ ^6 K" h* M N5 d3 c- \# o _& F/ Z6 I( q! |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 a1 A7 m3 t5 u* _static void McASPI2SConfigure(void)3 N$ I# {2 k/ B6 k7 b
{5 p4 ~8 R7 D7 y5 l) ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 j% Q0 ~( I) @. l5 z* [" a5 d0 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, \0 N0 l% e, S2 c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& b* O! h0 ~2 ~3 y# `1 pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 ?3 s1 |3 Y _2 ]; P: J) eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. m! y/ n4 h' S! T/ B: @
MCASP_RX_MODE_DMA);4 y+ D- X3 e4 H' H7 i$ n9 W2 Q7 y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 a9 @% H* }9 d# D) f0 _: n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" O" b1 a2 \/ y5 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 }, C' [- j: \3 O" hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* m+ k' ?/ g' N2 T% Z9 ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & X, D$ S. I* \! t' O. e9 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) K3 i% i' w; j2 r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& E+ @% O+ }' |4 U8 t" f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, L+ g0 T( `: V+ ^0 SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 S. z# n: h8 }. @; i# G( ^/ J0x00, 0xFF); /* configure the clock for transmitter */
7 v( B; ?& K: M, b5 e) uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; S/ h7 B" D' j9 V! |. I0 `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# q& M0 A. o6 M0 v+ J+ vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 P% ^* f: k( P: R2 b
0x00, 0xFF);
i z$ O) k; V' e3 d% c1 }/ x3 Z( t. u+ N
/* Enable synchronization of RX and TX sections */
$ X' f. E+ c, `7 L0 F' T- q( |8 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 m' f- ^( W: m( e+ [2 x1 \( {1 S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ q) D( j: ^8 [/ g) O% {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" h; e. @3 k0 O: p
** Set the serializers, Currently only one serializer is set as
( y2 a3 o7 Y7 x" k& F** transmitter and one serializer as receiver.
3 Z" A# K, G, O4 }4 [*/
5 m; r, ^* a' O; r$ ?3 ?/ r& h# qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 |$ C Y! N( s. A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 X6 q* \5 T/ ?** Configure the McASP pins
" X7 Q% s e" u; R** Input - Frame Sync, Clock and Serializer Rx6 G2 h' P3 r9 M) T/ S% M
** Output - Serializer Tx is connected to the input of the codec + ]+ t; J- |/ {$ v& z1 i' _
*/
! L L& Y \- X) l% r8 C& ^$ mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ t0 K9 s" l! ~, t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! M" d9 G. R) d2 w! t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 N4 } m5 I3 Y6 G
| MCASP_PIN_ACLKX: Q. O1 i& v8 Y5 D; c5 `2 I
| MCASP_PIN_AHCLKX& K$ A& m( q# S' R8 d' r% i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ n, A3 b1 M: Y$ q! v+ }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + E' I# K4 ?4 I6 _& a) O
| MCASP_TX_CLKFAIL % u9 r0 A4 S% ?* p3 t* ]
| MCASP_TX_SYNCERROR
: w0 H8 G/ v H+ |0 j+ H* s, H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 ^9 W! ]" e/ L& z$ ]: J2 c" T; B
| MCASP_RX_CLKFAIL8 a4 \; I- m# V* N! F6 r
| MCASP_RX_SYNCERROR ; F! t5 B/ u0 |2 U0 T
| MCASP_RX_OVERRUN);8 l B, d! B7 q* b
} static void I2SDataTxRxActivate(void)
' ^) L, q/ j' b# I{) v5 P- q8 a- Z3 ^, W
/* Start the clocks */
1 m/ A1 s I" c+ hMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 P5 u4 J: e7 k( p5 `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 P* r: w/ h- AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- {5 Z* v% H; d" M7 Y3 w7 DEDMA3_TRIG_MODE_EVENT);7 P/ o6 i: F% I/ V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / O6 ?( ]/ L* ^4 Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 B2 M; l4 \7 K; G0 [* l8 X$ d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 C* y1 g3 K$ u( m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ x' h: F% F+ n6 s" o/ @! o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 O* Z# w+ Z U7 QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 [/ H$ q# j# l8 v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. ?( }0 N9 u6 E/ A
}
, E; ?0 D6 l: R2 i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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