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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 q! t# j7 _! h, d
input mcasp_ahclkx,
! G0 N1 \' l2 a9 ^input mcasp_aclkx,
8 g5 l7 M( h W' `0 [input axr0,4 V1 H# d# c0 B2 J
1 n1 X+ x; k9 W) z& V
output mcasp_afsr,
) P B) {: c4 N" c" O% Z8 |- \output mcasp_ahclkr,
- u# c7 S2 J' K6 voutput mcasp_aclkr,1 x8 Y" q& _- _" N Z; n
output axr1,
+ P/ e4 n. V+ {: {$ w assign mcasp_afsr = mcasp_afsx; b7 q2 _, H; ^+ y$ F
assign mcasp_aclkr = mcasp_aclkx;; F, k" t7 n; D) s
assign mcasp_ahclkr = mcasp_ahclkx;
. i1 K2 U- F7 n/ @& i: K; x! b' massign axr1 = axr0; , n6 y6 _, j S0 [; n- j b
: ^* q9 E% K5 ~" p( G0 S& N" f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
F. o/ ?+ `3 D& V6 l \1 J3 V7 c9 lstatic void McASPI2SConfigure(void)
. s; {+ {/ F/ {+ n) n c{' p0 y! \( I9 Y* l' d* U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ D/ L$ T4 o3 \' e% Z" c7 jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) X( n5 n% E8 g9 i* w- B2 _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
N% D/ k5 H& x& G7 \" eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! ^0 q8 s5 p& M& v+ uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 _$ x3 m- l* G7 n1 I% Z# zMCASP_RX_MODE_DMA);
! e$ ^" q3 |5 s" \ w; R1 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ P: T! G! D2 J0 S* D0 CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 ]+ n% I4 j8 [1 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* T9 \. R* E; i- T$ c' r3 I: pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. f1 \: S6 D: F$ K' e/ K- \9 oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % X6 B) U5 g3 |, z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 l! A. _. |% M% C' wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) p- y+ X- w4 H7 ?0 {+ \1 |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( D7 k4 b# z: N/ m; Y8 rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 @, T5 F7 W( }: _- {5 ~# V V, U0x00, 0xFF); /* configure the clock for transmitter */
+ U4 ?' D$ q7 A: s: @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 C( E: v* Q% `. W" S8 ]; U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, A+ ?: S% I# b5 o: Y# UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 A1 j. J2 `* W2 c4 g8 p6 ?; o0x00, 0xFF);( f" q$ G0 R& e& f
5 v) L# }5 m/ G7 q3 E! K/* Enable synchronization of RX and TX sections */ ! I- K! r4 X( Z! Z4 ^1 m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ P( ?. J: ~3 H. [+ |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; }( z7 w" @' c' \5 h' ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, T7 f2 C7 p# p% N5 x' E: y** Set the serializers, Currently only one serializer is set as* ]; m# g/ V' v3 v! r0 b
** transmitter and one serializer as receiver. g2 Z4 ~7 A6 @
*/
$ M) L( a4 U" R4 M+ U$ S8 }* x& a; `- ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" B' e) E6 s% y: |$ Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 X! M; x" b) w* o3 [4 x' f( l: P$ r** Configure the McASP pins
6 u$ x3 x3 i* S" E2 R' e! F- {** Input - Frame Sync, Clock and Serializer Rx2 M$ s* l5 V& j7 a5 K( y" V
** Output - Serializer Tx is connected to the input of the codec 3 [) A* d' a; k
*/
; Z8 _$ ~: z/ l7 ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" `, i' l4 _' d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 h/ E/ {$ N( g0 i5 m0 w! QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. V& F j# V l! r2 o4 _0 [1 Z| MCASP_PIN_ACLKX
* N! R5 w$ ?7 D| MCASP_PIN_AHCLKX6 J. @) n+ z1 f. U1 R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 p+ Z x- r% eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . ^! t$ q4 k' b; d9 k; L8 T
| MCASP_TX_CLKFAIL
4 u- p& D. e6 ~& m; \# l/ K/ @8 f| MCASP_TX_SYNCERROR
% e0 R3 q# U8 b7 }. d* q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 B8 I, r5 r. J2 l
| MCASP_RX_CLKFAIL$ r# l2 u `3 y6 a- j9 s& T9 [
| MCASP_RX_SYNCERROR
% F& |- B8 u! \& i| MCASP_RX_OVERRUN);% F, Z& Z; J$ e' \
} static void I2SDataTxRxActivate(void)6 ~2 [% ?7 u" ]% \! V9 h# p
{5 o; F: l2 O" c, C. Y" f I. n
/* Start the clocks */& R: Y; O; _% h) R a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 r v% N/ Y! k$ n6 b1 s, p' QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; K! m) ~, }& C3 ?; P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# B, }8 v$ }/ W' x! I% Q) ^
EDMA3_TRIG_MODE_EVENT);
* T& }1 G+ S; U% C+ @& HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: O7 }8 s" _4 `* nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. b: H% k2 Z4 n( Y. V) u3 Z6 r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ N0 B, V: L8 ?) |5 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! m# C: |, b& D7 w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 [& }& Q I; F: C- }; r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# e' C8 m! c- Z5 |& X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: L+ H1 [3 v+ H0 Y' z* n
} 4 y+ e' n$ ^& M) m7 a1 }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 Z! Y$ y) r. _0 F8 A3 X8 \: R( B
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