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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 s( R* L3 Y# Z2 J# Finput mcasp_ahclkx,
k% r: o/ r6 d3 k* qinput mcasp_aclkx,1 m7 t5 E) T$ F! y' z8 P
input axr0,) ^7 a4 g9 J& S! z
2 p. N- @* f% S# s0 m* p; E
output mcasp_afsr,, U; ~6 r# S/ Y% s) s p
output mcasp_ahclkr,/ k3 u, i _# s+ ?) u3 v+ E
output mcasp_aclkr,
/ T! y9 }+ ^7 L: ^0 H6 h2 loutput axr1,, U+ E/ i& ]% ?+ a8 [
assign mcasp_afsr = mcasp_afsx;
2 c6 C3 l% N V7 M, u5 ?2 i: ~; kassign mcasp_aclkr = mcasp_aclkx;1 ?* C3 V0 g0 C/ ~6 e4 R5 _4 Z4 v, P
assign mcasp_ahclkr = mcasp_ahclkx;. \8 d6 c' U3 M4 F9 Q
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: }% n, `% k: zstatic void McASPI2SConfigure(void)
5 p# q( D6 {$ Q/ m+ y p) w{/ X3 T* v- t& P+ _ J& ]$ ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ q0 p2 r U# s5 t5 v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' G; o! o$ K1 P. Y# o$ r! M8 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) I0 R" q2 c0 e9 h! ^- }# l! s6 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% q$ s ~% B) jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# J( U, A) Z. q- R, P4 h3 R
MCASP_RX_MODE_DMA);& L" v2 J6 r0 y; s& D9 C0 t1 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 x" x/ m. p, n0 K8 u2 TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ r$ e2 N" Q" I1 g7 p u: J! EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 t; C# E4 [* ~0 z Y. I; J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ E6 [% G p1 m3 ^- q$ x" `- u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 D6 f) U" G3 PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# y% |; h. B& p) \. D" [* \% xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! q* k5 W- @/ B0 Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' _3 b- j$ E/ N! x! ~8 l3 t$ z! x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 y5 o- k u5 ~8 u0x00, 0xFF); /* configure the clock for transmitter */. \6 @! h( ~+ y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# j: r1 Y: ?) k1 z! t5 eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - y/ s, D, c$ V3 G8 n) P" P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% \' u* s) d5 L! e* w) q) \0x00, 0xFF);
/ R! b+ ]- v6 X0 l @3 m a O" E" x) X3 q( G
/* Enable synchronization of RX and TX sections */ 3 u" U1 i! H0 O$ n7 ?5 @5 Q3 e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* O' b# B% P2 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% ~8 Z% F9 x" G6 Y* W' KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 C' e1 r0 R$ P4 q" i3 D** Set the serializers, Currently only one serializer is set as
; R- o1 O* y4 [8 ~" D6 }7 Y' h** transmitter and one serializer as receiver.
- S* i6 u: K9 a( m) Z*/
- L- x' m- k. U6 x& J7 IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! W# v1 D2 Y# D6 D: J/ ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** S9 W- d. Z- m8 p& ?
** Configure the McASP pins # B1 X; ?' k" V2 ^# F
** Input - Frame Sync, Clock and Serializer Rx7 \& ^4 S/ g# S! l+ j
** Output - Serializer Tx is connected to the input of the codec - O/ x& ^2 m4 T0 W$ t
*/
( B. b* ?* {$ [9 J5 I2 nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ o: A' W8 X7 ]6 rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; G; i7 E D7 T* m- C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 n" x- Z" K7 r. _2 I) j
| MCASP_PIN_ACLKX
}9 F1 \" _ k. I2 Y7 l0 F# {% G| MCASP_PIN_AHCLKX+ o+ M- v6 O8 F& u+ I9 [/ b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- a' [1 d, X, X4 h/ D3 j0 ^3 _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; I% h7 \1 X5 f7 E. J# e) Z| MCASP_TX_CLKFAIL
; {( N* a0 ?8 x. c4 w| MCASP_TX_SYNCERROR" F0 v8 |4 q: D8 G% T& ~5 o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 c3 K( g9 B& O
| MCASP_RX_CLKFAIL
) v1 D% d# z/ ^ o/ P b| MCASP_RX_SYNCERROR 7 {+ s7 D) I" D2 Z" S4 @; A6 T' j
| MCASP_RX_OVERRUN);
- X! K# [9 `' [8 P7 ~6 @6 ?3 B1 [} static void I2SDataTxRxActivate(void)
# |1 w0 l7 x* C" P+ T1 `{3 y2 y7 J) l' B% H$ H7 T
/* Start the clocks */
% }! r& _; ~; I* J' Z% GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ e2 I+ [* G2 `' W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 T( W+ q N8 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ Y' Y( E8 Y/ j! B
EDMA3_TRIG_MODE_EVENT);
4 Q0 S9 z6 r3 a2 K9 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 e' h! Q j# s4 T2 R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& J2 T0 q* a% O2 }1 D. mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ T9 c, c O, V; m7 I0 |: t6 \: Y4 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# U7 B: W {) ^5 S7 x3 gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; V. q5 J5 ?9 f5 ], `, nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, F! D. i/ v. ?1 G& u( a3 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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& u& H- v4 L* W) _4 e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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