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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 j" s5 [% W/ c; }- J; w! |input mcasp_ahclkx,
8 v1 R& F4 y! l0 L3 G iinput mcasp_aclkx,8 V1 E8 |7 i4 ~+ }' L7 `- H
input axr0,( r9 B3 y5 X# M7 s" F: [
L" z6 e: R- C( U
output mcasp_afsr,& a- u) `4 r: ^$ B4 `" D/ W* L4 {
output mcasp_ahclkr,
* {" `, n$ j3 J" a9 \output mcasp_aclkr,8 a) B# B2 k) P5 b* o
output axr1,
( L& a8 b. z, d! u assign mcasp_afsr = mcasp_afsx;& q) ]4 x" y% `3 R6 r
assign mcasp_aclkr = mcasp_aclkx;& W0 f$ l2 }$ @ Y
assign mcasp_ahclkr = mcasp_ahclkx;$ [/ l! C/ ~/ s% H7 A9 S9 B3 I
assign axr1 = axr0; + h+ P5 D, F+ k/ c% x6 C- C
5 B- F5 U9 ?- ~7 ?6 m/ \1 Z$ g3 H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 f8 ?1 b9 f( Z3 p0 Z8 `
static void McASPI2SConfigure(void)! k0 N# k8 S- ^0 A8 M0 W: v
{
6 x9 w$ z9 g) H/ m1 o9 C2 DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ g4 R: D5 u! t+ O$ L: Y( Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; Y/ ` F. J" d, _' Q/ a3 S$ U/ xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) C4 R8 x5 n% O3 {8 H a6 C; a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, ]' N# A" D" @! J* c7 z- N" [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ |7 i! F7 @( t1 y: K4 W# j* I
MCASP_RX_MODE_DMA);8 o" Z. W9 T/ {, A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; G% S5 b& L6 K1 ?4 C- f; z/ mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 x5 l5 S+ w+ P$ e6 X+ R- @! n2 R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* l! A! w7 I9 L. N2 n z% TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ V# [ R& Z9 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 X8 `( E5 J8 y# _1 y0 r+ N# N( WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. D1 `6 \. z% b& Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); v( @# Y6 B+ j0 T3 }/ o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 s# k% [% x# KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 a, q' l2 Z0 z3 ]0x00, 0xFF); /* configure the clock for transmitter */
$ q6 x, @$ J+ b! KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, J/ X- s3 a6 `& H o9 m* j5 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , e: @4 ]/ C0 k* j6 \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% f. ~8 F+ \! G! K `
0x00, 0xFF);
& K9 h, u0 f4 c% ~4 v# k
. p3 ^6 \* `+ \7 L, N" L T1 u/* Enable synchronization of RX and TX sections */ ( L: D4 f; ~' }1 T* K0 p. ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" k- `; B% P$ D7 x6 k, vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* v. y t! P# J M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ A) Q k& Q9 Z1 h+ ~ [5 V( `** Set the serializers, Currently only one serializer is set as# C1 {3 m( S( b
** transmitter and one serializer as receiver.( S; ]3 O! q+ D" J, {4 `
*/$ D* p G z( V8 C- W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% y5 c" B4 t) }0 [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ R, U; ]; ? \/ `' N** Configure the McASP pins ( c8 v f1 K3 X* t, L
** Input - Frame Sync, Clock and Serializer Rx0 g8 T7 l9 Z) X
** Output - Serializer Tx is connected to the input of the codec
% K' c3 q5 u- S7 |8 q*/
: X& _6 E) u; S5 KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 K2 |- a' s& {# e5 E4 u7 ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 b, r) L5 m) m6 @$ s+ y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. `' Q7 `) z4 i) I) B; Z
| MCASP_PIN_ACLKX
; @" W& D* c; G& w. T* _| MCASP_PIN_AHCLKX
, C3 O0 f# K6 v! r; |& F) E8 j6 M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) J1 f8 L0 l/ D1 p+ \( b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 E+ |" m4 ]- J. k. }, _( k' e
| MCASP_TX_CLKFAIL % h! p0 T' Y) e/ C0 ]
| MCASP_TX_SYNCERROR0 D# q1 {# ?; u* Z. u2 p
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' |0 r. ~1 m4 W, F| MCASP_RX_CLKFAIL: i5 e+ N+ Q- L' I
| MCASP_RX_SYNCERROR ' \- i8 v% ?) A' }5 z3 W' h
| MCASP_RX_OVERRUN);5 u% ]3 c$ N, r1 O: h
} static void I2SDataTxRxActivate(void)' Z8 g3 O, L. {3 h& ?% m* x
{
5 K# D/ N7 z) M8 R J- I/* Start the clocks */5 T% t4 Y- w: A Y2 O$ }. ]( x3 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); q$ L/ N+ D/ t& K* y4 ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 ]; G( L* v- D; kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 V( h [2 J- m4 c" g* eEDMA3_TRIG_MODE_EVENT);' c4 o3 k6 z, Z. E$ ?( M* K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * A: r2 }5 P. I5 X6 Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 l- K6 d7 ?6 t, ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 c- @/ n' h( Q4 g2 I# O5 Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ K4 T0 g. G/ ^ v. W- Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 e5 @8 b7 c4 |# ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 _0 M7 E' B, f8 i; j( e5 j( ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) r1 P: F! D1 \5 J
} : @' ~1 o! j4 K' u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( Q/ q0 x! w R0 Q# g+ y
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