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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* U* k' R, @3 m7 ?, E* Q+ |input mcasp_ahclkx,
& U6 o: f% j: ]input mcasp_aclkx,! _# S9 R/ n R
input axr0,7 n3 c) ^4 c4 S
% U w+ p( q$ m# m
output mcasp_afsr,+ z9 w4 H+ u$ V. v) F
output mcasp_ahclkr,* p8 F, R# e9 V9 v
output mcasp_aclkr,; r( `( ]4 K; w4 H6 M
output axr1,; b/ \" k) |/ T* R$ K7 ~* Q$ R
assign mcasp_afsr = mcasp_afsx;$ s0 F0 h5 c, e2 ~% P' }
assign mcasp_aclkr = mcasp_aclkx;3 w; s- P; H7 L" n% b! L+ a! T% I
assign mcasp_ahclkr = mcasp_ahclkx;
( F" G* R6 O6 Z& z L5 K# rassign axr1 = axr0; & K& }4 p% O& b) M( F
7 E+ C2 w! a& m5 W4 b: j7 W$ e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! r1 B: V2 r U. y# Y( z
static void McASPI2SConfigure(void)6 ?0 p3 o+ J1 E7 @# {/ I- U9 Z
{
8 _6 x) W* W) p; Z1 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" q3 y$ ?! W2 t8 M, f& g" Y5 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( D( O' z) H2 S5 N1 r" C# S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) r4 y3 B# A* C D7 f9 Y! a8 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! W; D% o1 B/ ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& E5 H' h& v8 G1 d% v8 m% A' z
MCASP_RX_MODE_DMA);
. ]1 d; J" U: D3 G( O6 x$ OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) B( t4 [0 W$ q4 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 D* F4 G( {% E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" A/ h3 a3 p qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& s( m# T" _$ L a# f# M) }9 g- NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; O3 q: U4 G8 a* k0 b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) y4 h" _2 ?: A" o, h$ ?1 y7 h, m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 E) s3 p x- y* mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . Q( y4 y# j' D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, o) q: r. }% D0 \) q
0x00, 0xFF); /* configure the clock for transmitter */
' [0 ^$ z8 e, o$ K/ h8 j: r" t! @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 F4 j9 A( O$ D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 f V& y( d4 }8 a% d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* F# }, _- C2 l9 x. P9 h: w) c0x00, 0xFF);/ `! n' i) j/ m
7 F4 _' D' }- D8 v9 J) B
/* Enable synchronization of RX and TX sections */ ) k; Q$ |8 e& b- d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. }# ?+ G9 v* |+ y; \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ Y1 ?3 U' W0 p3 ]9 C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* B @2 T- h+ F8 M0 g
** Set the serializers, Currently only one serializer is set as: d: I: ^8 B! _0 Q1 _9 `4 j
** transmitter and one serializer as receiver.' N; M" J R5 A: e
*/8 P) B7 k( A6 }) p; C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 s: M3 T- s3 LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 ^5 ~6 S5 V5 b; m6 y \, Q: L** Configure the McASP pins # P$ I. k1 r8 X; V# O0 ]+ q
** Input - Frame Sync, Clock and Serializer Rx
& J3 W& w8 p0 S** Output - Serializer Tx is connected to the input of the codec
! Z) }% Z8 H) E; {*/" ~7 x4 O2 ?' [
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 C( S- g, Q2 @, d5 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 t; K; q0 @# i) z, V# t% s/ G; X2 GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 p$ M4 q* z" F8 Q' |
| MCASP_PIN_ACLKX
1 Y( M7 S7 q1 c9 Z) Y| MCASP_PIN_AHCLKX) K& ^4 s: t" z+ X6 ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 l. R$ E6 ~* }# M- N) l0 E! \2 kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 y; E& A5 A( S0 }" U| MCASP_TX_CLKFAIL 1 H: b3 O$ E" V3 G1 b1 A
| MCASP_TX_SYNCERROR2 y0 Y# d/ J# X U& ]+ D8 |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " {8 j* F2 x) x0 {6 K; j1 @+ f
| MCASP_RX_CLKFAIL6 \+ Z0 E# N" R. d/ q8 B
| MCASP_RX_SYNCERROR
; G/ c0 h1 j; x) g| MCASP_RX_OVERRUN);$ s9 H; G. C% h* ?: T; K+ {& Z
} static void I2SDataTxRxActivate(void) P! o, w+ m6 O A) \/ R# a7 A
{& [8 Q4 S- w. {* W
/* Start the clocks */
2 i6 z+ ?+ Q% v3 L6 d. O. EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) E4 W1 `! K) h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" e0 L0 r1 X1 K* d8 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 i& f- Y& J# o0 K) M: j, A
EDMA3_TRIG_MODE_EVENT);1 e- @7 }; \/ w$ W0 f5 V% i! ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, t3 m3 p1 a& d$ z- E SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& ^. c( K& _" a3 qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# w Q: E9 ?- G( C; ]0 _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" Y4 j8 r% ~& n& Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 x1 O4 ]( E' p; D, }9 y$ [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 v$ |: {: j3 k; I/ q* y; J: c# f# r8 u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 Y1 C: O `0 S8 z& ^} 4 ^4 B. s6 q; o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + _$ }; G, O/ \' m
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