MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
% x$ t! @7 T- Q" g  O& [input axr0,
6 X& C* u! Z/ m4 Y4 x/ @* [
* g$ I( s  r7 R% z5 c6 m. noutput mcasp_afsr,
output mcasp_ahclkr,
: b8 J! v2 s$ foutput mcasp_aclkr,
# x2 e7 W1 X7 U# i7 Woutput axr1,

assign mcasp_afsr = mcasp_afsx;
! r  U" {1 Y2 b' \assign mcasp_aclkr = mcasp_aclkx;
5 P: h7 B2 U. W5 P4 qassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

. C3 y; j2 N, S5 z) e
! ~: Z" b  w' Y* D9 ~. [3 w+ v+ A

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
. |7 f8 }0 I* x7 P) h( H+ }& vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, `+ C7 c; C  x) GMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
0 _# o% c/ F3 G- e& K. pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 G' k) }0 ^6 x8 ]1 l- {! b1 eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
* R$ P( M7 w. b$ C8 ]9 O% G3 w% wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) p. l+ g3 i  qMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) W! S8 v9 l! K- D8 _; B+ c* gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& U) T5 B% o9 Q1 ?# l0 sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" t, S' E. r6 p& M) O& o# |0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 b7 g6 z3 w! f; H2 s. xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- b6 P8 k3 ~+ j0 K0x00, 0xFF);
! }' B: q# Z! l: E/ |# E, F
/* Enable synchronization of RX and TX sections */
/ ]# {; Y. g# u8 E  k# NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 `* y) ~2 E3 n  I, T" G0 wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
3 y2 d  T% R& s1 X: ?# G6 O** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
) R# ^; N' U- j- E+ hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 x: \$ z! W" m8 O% A$ k8 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
3 N- o% w% r' f, d( k** Output - Serializer Tx is connected to the input of the codec
*/
9 g( I2 E. O5 G4 K5 dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, H% j* j: [' r9 D$ x$ ?% ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 ]  Q/ }4 i# q( D2 Q( t0 L| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 Z& \2 v. g# P. u* N: i| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
" X3 w: c, b- B0 g2 d! }| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
  V  P& [' m' i* o* c5 O| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
9 l! S/ }. I1 m{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ \. \. z5 Z2 rEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: r/ O2 g3 ^/ {& |% I9 fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
1 {( Y& N1 u, V4 QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
: }. L; x! }' OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

. J2 p2 `7 u/ s: V* h2 d