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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& a7 Z9 c* |# g; J) Yinput mcasp_ahclkx,
3 U. p4 c; ~0 c# ]& j* N! Oinput mcasp_aclkx,
/ y: K' J4 d. r( z) f9 einput axr0,% z# ?+ N" C- v: }" _
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output mcasp_afsr,
6 Y E! n, {) P7 R7 Aoutput mcasp_ahclkr,
8 x( `' i- D1 M( V) soutput mcasp_aclkr,
) {1 F1 Y1 u8 }+ Doutput axr1,) Z/ L4 N7 _" N1 o' E3 O
assign mcasp_afsr = mcasp_afsx;' b: L" J) z4 |8 B/ A8 H% M
assign mcasp_aclkr = mcasp_aclkx;" B5 {' G) c( ~/ d; h% ^
assign mcasp_ahclkr = mcasp_ahclkx;# e: T M; f6 }' x C$ w
assign axr1 = axr0;
( D2 R% `0 H. Y7 l4 a$ D& \% U! P5 N( e& u" V, @7 X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 O6 C1 q0 r$ l. n: v: H
static void McASPI2SConfigure(void)
. h. u# K; d% j; G{
# Z% H! `6 I6 m# F. K6 h8 k, o' r9 L ?8 vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ k- |* K n3 k1 f1 d' y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' \# E& U2 N) F( u8 W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 O. M* B- K5 k L" [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 F2 d1 q5 d- d5 E+ e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% s& Y3 Y0 W& z" {1 X- J- [/ `
MCASP_RX_MODE_DMA);
; Q7 t6 R1 x* ^) D9 l6 `) [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 R0 C4 \. S( o& ^% e& oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: `* t9 ?- N7 s. @) W4 y$ @* v! ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 k; q# c4 d) a' R& I' E+ \- r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 ]& H: b- h4 W" S- `! k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 G: ~7 D6 n% L; H& Z6 IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 n; V: T/ t% f1 I$ {2 X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- X3 k) Z: [0 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) Y1 n& y0 g3 ?; G; I( J* QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 S, [! H( ^1 p% g( ~: l! A7 ^0x00, 0xFF); /* configure the clock for transmitter */
3 z3 N3 z6 S+ E9 T5 {# DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 V/ [$ l5 @7 B9 J+ Q! G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' Y) P3 f( z6 Z9 t8 F f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 J1 w3 n& O+ a
0x00, 0xFF);
" u: m3 f7 F' e1 {2 e6 q& ?, V( ^" Z1 K( H7 I: v+ K
/* Enable synchronization of RX and TX sections */
" [+ d6 V. k' i! c, }- f! eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; ?( v0 G, H7 E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 n9 D W% c2 k: N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 D+ |4 ~6 U# d2 k. C
** Set the serializers, Currently only one serializer is set as
. ]9 p! b) u x R% Z** transmitter and one serializer as receiver.* b$ z% F# P( J- P2 w
*/, `5 }# _' v" b4 s& |' c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% U" G" m3 |% R% N+ `3 f( lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ k7 T1 t0 p. z8 y
** Configure the McASP pins 5 b8 L7 A* e& w0 x8 w0 a
** Input - Frame Sync, Clock and Serializer Rx9 {, \7 _- h1 {- o4 f9 n9 E
** Output - Serializer Tx is connected to the input of the codec 5 b* d3 x4 j% y
*/& i2 H* q4 i! j3 J) j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 Y: z X5 j, Y- K( F$ V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& y4 P0 n4 N" W7 ]! |4 G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ D3 W! o, {: C A6 q/ [+ w
| MCASP_PIN_ACLKX# T" J- B) C! q" N2 ~7 z
| MCASP_PIN_AHCLKX, c: c U q( m* ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# Z5 L; Q/ \1 Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 c+ Q u6 U. K/ j/ Y| MCASP_TX_CLKFAIL
; K: ?1 Y" z6 K! N+ C* S; ~$ g| MCASP_TX_SYNCERROR
1 J' @2 i1 L7 L3 P* T: |! m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& e _, `4 ]9 v1 o$ n| MCASP_RX_CLKFAIL1 K$ L# g9 E1 b' J9 M7 T
| MCASP_RX_SYNCERROR ( l' q& p7 M9 l0 f" K( y
| MCASP_RX_OVERRUN);# V* [2 D, n. E+ A- ~- z( I
} static void I2SDataTxRxActivate(void)
; Q, w" m4 _/ \/ v/ @{2 o+ m: k$ k0 v" G
/* Start the clocks */
/ c- j7 f1 e- l7 e4 iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ e4 Y; `7 K( h6 W2 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% |, A' g. ^$ p5 n' L+ D6 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' ]: i: h' w' dEDMA3_TRIG_MODE_EVENT);
/ J2 P3 n9 U& R& F6 Y( ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% u. Q1 b9 x9 N6 y. @. ^( [+ p0 OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 v; {) ]! C8 b3 x/ H" gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( a* R/ \" R1 }, h6 U% qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: @, ?6 X* y0 u5 A/ y ?" i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! E. T* ?$ l: o u" E: _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 Q* M7 d) C. ?' r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # y$ O' j. O% I/ |" ?+ L+ n) g0 x
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