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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 H6 r9 K0 k- n& S& i, sinput mcasp_ahclkx,
1 Q ^, K3 I+ ?' v# @2 r# S B7 X. `+ _input mcasp_aclkx,9 R/ Q5 @' m* m
input axr0,! u: X$ q) b" l# q2 _
) W% \6 M- t5 X7 k* V" j- boutput mcasp_afsr,5 m2 z1 j7 L7 }+ l# {$ O; ]# J; V
output mcasp_ahclkr,
" L8 u- ?% h; c5 `2 B1 joutput mcasp_aclkr,. R5 a7 l/ ?: m. d ]: k% v
output axr1,
9 F+ r1 N8 O/ Q7 M& _- v assign mcasp_afsr = mcasp_afsx;
* D/ y# W, z# O8 W- t- N8 Kassign mcasp_aclkr = mcasp_aclkx;
& E2 d/ ?2 q$ J0 @assign mcasp_ahclkr = mcasp_ahclkx;) ?; r! \' R3 Q. o
assign axr1 = axr0;
+ K% R, V. b% n% a
2 v9 E% ^8 I$ ~7 D+ V1 ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# o& Z/ x% N( ^7 ~- C* v8 bstatic void McASPI2SConfigure(void)6 K' |/ e! S: N0 B1 o4 ]
{
3 }8 O [1 K% M( HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! Q7 H/ @+ B+ e/ L; q4 a1 L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. i! p3 c" w9 p( c8 a \4 L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 D, M3 J( ]# I7 \' wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! U/ a# L: G/ ^1 j0 _- P6 }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 v: {7 y3 S8 _5 a& t% z* L* L
MCASP_RX_MODE_DMA);$ l1 g% ~4 A5 E* e3 Z8 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' w$ n9 t8 v2 m. |3 t3 I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. z( A9 C0 W$ L/ Y' y+ ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 [; L0 P! J' q' A) UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); U# c- q5 o. M9 V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
r) O: ^* Q) o0 {( _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 S( D4 I& F# \6 t3 M' R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% P- ~2 _: x9 h+ K' q7 e1 o2 {0 F9 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 B! ^* b4 e* [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; h. s, F/ T# K0 Y1 t' b
0x00, 0xFF); /* configure the clock for transmitter */
, [9 h1 }0 t9 M, w! ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: z: E6 s+ ~( ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - \0 Q! G. S1 E' y: |7 A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ O. R# c* U- ~7 a
0x00, 0xFF);
; z( i0 m6 i' V, V
0 C7 l/ V# Y8 |/* Enable synchronization of RX and TX sections */
" ^; b8 ^" Y( V D! bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 P0 H! w) b: F3 h: ?8 p0 E6 \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ i" X, p2 }7 x' A- [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; J' c1 s8 D- W( F6 L
** Set the serializers, Currently only one serializer is set as
* k" q: v5 r9 V$ i: b1 |2 [, z** transmitter and one serializer as receiver.4 l9 k2 z! O6 O# j4 T
*/* J/ C r7 @; H7 N6 A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ t& k! C) a) p1 s. k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ }# A" L8 p/ `& A. y" l7 ?
** Configure the McASP pins
* F; H9 y! m( s$ a) i% ~( A** Input - Frame Sync, Clock and Serializer Rx! V3 c+ q/ {$ m, i! a. V" w3 c2 v
** Output - Serializer Tx is connected to the input of the codec
( M& `1 l! M) [& R6 Q$ k*/
& }6 O, P* L U3 z" m* t. lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ d4 E3 J& m( w- ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- s2 b3 V% E% Z: x3 I4 A) uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& a2 E8 c, g% l9 T) K+ j4 X
| MCASP_PIN_ACLKX
g# k2 S5 V; a$ V8 o+ J" a| MCASP_PIN_AHCLKX
' t& h1 Q3 o8 B* o. o| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. a6 n; _. Z) X' r9 _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" d; L. O, V% s/ f9 W& O| MCASP_TX_CLKFAIL 3 z1 M- C' q% A+ j. U6 e# q) l
| MCASP_TX_SYNCERROR
- w( E$ b3 i3 o$ b! x! S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; f$ J. E1 X5 ~0 {| MCASP_RX_CLKFAIL
# i3 M0 ?9 t0 @ {| MCASP_RX_SYNCERROR + `1 }6 q( O% c0 Q g2 ]6 l
| MCASP_RX_OVERRUN);
; L, m0 o# q6 m7 Z" V* q} static void I2SDataTxRxActivate(void); t) V; d3 W$ B; Y) K
{
C# ~. L& E* o" V/* Start the clocks */* R% T6 M+ ~, B7 J" C# i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* r5 u5 y2 X" ^( m5 g" q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% B/ b2 w @' F: c/ {) K2 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# A Q4 I9 v2 _5 B2 }4 Y
EDMA3_TRIG_MODE_EVENT);* E5 P2 R1 ^; Q$ I; y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " x1 G0 ~; R+ n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 F* x% v8 y& Y1 j: ^5 c( C7 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 m R+ B9 G$ ^6 E) J ^$ v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) A$ M0 G9 T+ E$ E, N# I5 n1 k& c3 bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 v% J' r5 d" g8 |, O9 I; |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* T. ~; w4 a8 B0 N6 b2 N/ P8 lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( f9 S- H: `3 B* {; `
} " \$ O# A; z) \0 e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " A5 }; ^4 W4 Z) D0 J9 q* `/ C
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