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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ R6 [# h7 G! C% y% ^input mcasp_ahclkx,: W9 z$ T( k$ A+ T* ~
input mcasp_aclkx,& P3 d- R8 k6 F( u0 ?
input axr0,$ X' J- `% I, h% P% {0 f
- B8 G5 G/ `# J* M" d+ R/ {% goutput mcasp_afsr,
* a* r& Y! c) s- L' p% v* f1 koutput mcasp_ahclkr,
- ]6 o. j, a: K5 l0 j+ h* C- foutput mcasp_aclkr,+ w% z4 h5 ?9 g* w8 `
output axr1,
1 \. |6 S! j# x; a/ L assign mcasp_afsr = mcasp_afsx;% a# w0 b' `- S
assign mcasp_aclkr = mcasp_aclkx;2 S+ |& T7 @4 P+ `9 Y: q
assign mcasp_ahclkr = mcasp_ahclkx;
6 h9 h3 d$ w0 T6 K+ t- [3 u% Vassign axr1 = axr0; . a: W' _& Q' D& D j5 N% j
5 q4 W4 s4 C% }! U& _& ~6 I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, F* L! {" a" ^static void McASPI2SConfigure(void)
! L1 C* r& C8 m& \+ m: L& G2 k{0 Z v1 \" K# w( Z/ z5 i4 s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- W2 r, h! i2 ~# p( Y) VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 d+ u Y; V7 ]# J9 L1 H9 Z2 S* O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 W4 n. J1 l6 w6 F. X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 v l0 W9 X8 L: h# V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& X/ H5 U# H% @MCASP_RX_MODE_DMA);
6 c, E# l. T( |4 \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) | r. \% X2 p1 e9 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* b/ S/ L+ v: I% A( T4 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 E4 F: v- R2 T) f+ RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& i" b( o+ q4 }* [$ e0 P5 ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 e6 w$ D4 I6 c A! M4 J5 ~ V. I* s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 x. b. k9 K- u' x# ~' E. aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( m' [ W$ S2 k+ M4 ~( F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' M' Z( f m. s6 N/ W1 ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& \0 U" ?$ Z3 K
0x00, 0xFF); /* configure the clock for transmitter */0 u( C" N L( u! C `; q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& c) y e* Y3 J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 h% v# j) C) {. T1 ^+ \. UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. x& G X0 y+ u& x
0x00, 0xFF);
( P, a( H" g: `
' W3 C9 l% V9 }; W, Q/* Enable synchronization of RX and TX sections */ & K E: f/ t' E9 }* p9 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 b) F& X4 L( }3 PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
P( u e# a2 |! B5 lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 j" L7 j6 K* H/ Y5 s" q* v! g
** Set the serializers, Currently only one serializer is set as
S, R' F' x( N# d, y$ m2 f** transmitter and one serializer as receiver.
* h' I4 {- {! z7 x" j*/
3 t b% t7 e8 ]4 N) r2 pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' l8 I' s" @. a2 E+ ^+ {7 a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 D9 j0 Q6 F4 R2 p** Configure the McASP pins
( I& _3 b. [' T+ c- N** Input - Frame Sync, Clock and Serializer Rx# T$ c' |9 g u
** Output - Serializer Tx is connected to the input of the codec ( ~% ~3 ?; e7 ]
*/5 {1 @# B/ W# m$ v C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 O5 [8 w6 r; r$ A9 FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 J8 y+ \( D8 _! T* ?* \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 p% Z2 ]) t. w- ?, X/ h| MCASP_PIN_ACLKX
+ R' L8 C% G7 ?% n# q$ || MCASP_PIN_AHCLKX
; m+ {' X8 X# O- c* p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 M1 r% C; x- u; s, h( \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 J6 E6 _, c# |' D" u* b| MCASP_TX_CLKFAIL ' f; K L3 u3 _% i4 y( s$ a
| MCASP_TX_SYNCERROR
9 {4 g6 J8 F# s1 v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ [4 S. a& G! {1 C. n+ z" L3 L| MCASP_RX_CLKFAIL' N1 P8 S8 c$ |. S2 w6 ~! o
| MCASP_RX_SYNCERROR
2 Z& ^$ |' s, L9 A( D% `* ]! d| MCASP_RX_OVERRUN);& b, z7 x0 k. ?) L: E- y$ Z3 d
} static void I2SDataTxRxActivate(void)5 ]; Y& U0 H/ {% t6 U
{ m" N7 l: I, H" o, \4 s
/* Start the clocks */
) S2 w' K* m5 A7 i# w0 z6 VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
{5 y3 f5 I+ ^: F8 F/ W- iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. C5 `/ V. y$ v% [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 E* O1 v9 m) I1 Z
EDMA3_TRIG_MODE_EVENT);
8 |, x1 F, w' M4 d' F& @9 X# n& jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ t. J) ]* c6 U1 T4 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 c. O, L( Q' p! i! r, a5 ~6 X3 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 t0 F, U' e- ?( G4 k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// m; x8 v- n' [! z/ T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! d" Y7 p+ l; v ^- L% N& ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% J" o% j% O. G- ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" x5 h6 `0 D8 q% s0 |$ e0 z}
. V6 ?3 K; b$ ]# K F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' V! \7 S5 A4 }; e4 M4 {
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