|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 ?5 e# x0 s. `* Xinput mcasp_ahclkx,# I! [9 m z/ W/ r
input mcasp_aclkx,% M- n& {/ d3 L6 M; m( J
input axr0,1 z9 U+ e$ D% G w2 ?: K
2 m& j+ P4 G+ M/ woutput mcasp_afsr,
8 r0 r5 W! [7 @$ ^8 l- soutput mcasp_ahclkr,
( f2 ^' }' B& X( a4 l5 n7 Goutput mcasp_aclkr,
, ?& \# a. a( G' `* Qoutput axr1,! Q- E1 H( z; e0 n5 ]5 f# A7 Y
assign mcasp_afsr = mcasp_afsx;
( {% v, z8 s. tassign mcasp_aclkr = mcasp_aclkx;: E2 c/ F1 r+ i
assign mcasp_ahclkr = mcasp_ahclkx;9 r; R3 v; d/ A! Z3 O4 p0 Y n: u$ r
assign axr1 = axr0;
! }* f# O0 y& s- f6 f. N3 d$ B$ ~, V6 G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# i* o: Z# j! P! ~static void McASPI2SConfigure(void)
t0 R, |) |% z% {( M- z$ _- d3 W% d{ d `' {; E( q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 T3 D6 a0 U0 W! y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 }+ Z: e7 E7 w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& J s+ M# `+ _9 O" xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* V: \% I* T' m: r6 `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) n0 @, n+ G2 E5 e) S
MCASP_RX_MODE_DMA);0 S9 ~) ?1 [* g0 |# D, _& C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! q) r [8 R/ J" U7 M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ _0 V; z3 o0 p* T( i* Y9 @& gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% C4 t$ E/ n3 c _. zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 Q; X" H [8 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ l8 S' ?% u* g( z( r" d* H0 \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ ?# ^; X9 y3 W2 h8 M0 |$ n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# Z# W# D2 X$ ]) L7 m& e" GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; }; `2 p, O2 d, IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 ]0 | r Q. K; j M* h
0x00, 0xFF); /* configure the clock for transmitter */4 p0 K0 C8 w4 K2 \& G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 c+ X$ v4 J$ o2 p) S; V1 z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - T- `! w; S$ p7 k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 L/ C' \' D7 ]7 t7 w0x00, 0xFF);
0 J0 [& j/ |% _& Z* ^; I/ y
/ x9 Z- R0 j" \% ~# w5 d( F/* Enable synchronization of RX and TX sections */
5 M9 t# W2 ~ k0 K& p a @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 T- Q% I( b8 z1 |1 `0 v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 o: |! j% x' H2 m, q3 cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) f* K- F; h6 X1 W$ |. D- O
** Set the serializers, Currently only one serializer is set as6 h3 Z' v( t2 P) K+ A# O
** transmitter and one serializer as receiver.7 B0 z+ n# C1 U. \
*/
: [/ }* ^, y* e6 k: t1 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# O! g- ]* ?6 s( j0 t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 o/ d9 Q) k9 D6 l/ Y. a
** Configure the McASP pins
7 C* y" e/ p! [, y/ g** Input - Frame Sync, Clock and Serializer Rx+ B3 Y- C1 n3 G% R; @
** Output - Serializer Tx is connected to the input of the codec
: s* y L2 U- B# @: B*/
! j7 j) A1 k- ?3 E6 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 v8 k, ]* k( W w8 m$ kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& {+ Z6 ?. K; l5 C' ^9 b1 LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 `7 V' M+ b7 S9 S @5 Z| MCASP_PIN_ACLKX7 F4 r! l# z9 J# ^
| MCASP_PIN_AHCLKX
# }6 u- @8 F6 e% A/ O1 S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. K- u+ f+ ^' I2 Y. N. Y8 u. R6 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 k8 C9 |/ K9 G+ `" C5 {# H
| MCASP_TX_CLKFAIL
% s7 h9 ^) h7 n| MCASP_TX_SYNCERROR
& m# ~4 p( l! p1 c( E* }9 g% b: x" ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. w) X/ u2 J' H5 c8 I ]- S8 `5 _) `| MCASP_RX_CLKFAIL
8 f( Y2 \" I' C* _2 q) G| MCASP_RX_SYNCERROR
5 e2 Q" P% E. m( R5 @| MCASP_RX_OVERRUN);6 l+ u/ l& S/ }3 |0 _ K( s: o+ K) E
} static void I2SDataTxRxActivate(void). {# X) O3 Y. c" ~4 {
{! l9 |" d8 ^% ^, T f
/* Start the clocks */
( _$ h( _( d3 \/ rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ A! i5 I) H% B1 ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; |' ?/ b" ~! @/ _% g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# f5 C; ^: u) [& ^- p7 |5 U& E
EDMA3_TRIG_MODE_EVENT);% O# t$ `- t7 M% W/ Q9 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ a% j/ ~$ M6 q! ?6 _* iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( p% I+ P# \6 g; }* Y2 G4 ]0 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 E1 H$ j1 e% o. z! ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% D: u% X( [/ L' i v; _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ D" t6 s. T; J& a& J' uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 J4 d& ^% H8 {2 C8 G4 K; Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 l# W$ ?2 d+ y6 z) ~6 P- O
}
( [5 ]% b" N0 h5 n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
/ C" [/ ~3 K& ~! p, j3 b* L |