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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ W- K( @5 Y: Q# H I, Pinput mcasp_ahclkx,4 Q; c' b6 ~* B y
input mcasp_aclkx,4 j$ [5 P9 l1 ]; v$ R* E- \
input axr0,
' x& `& B) B1 u% D3 j* c4 R: T2 S) k+ B2 {, H* O9 y
output mcasp_afsr,
* q4 x' }% |! P d7 P* Xoutput mcasp_ahclkr,3 K$ D: J3 I1 n+ X' K0 y: j
output mcasp_aclkr,' w9 c8 V/ M% w6 e9 m# `7 ?& X3 P" u
output axr1, D" ?/ V9 ~* R" I" j" _
assign mcasp_afsr = mcasp_afsx;
$ K8 J, Q, x8 I& vassign mcasp_aclkr = mcasp_aclkx;
$ L( j& i% Z- p. T7 J( }3 Bassign mcasp_ahclkr = mcasp_ahclkx;
; v4 X* |9 \# v/ ^! {& A/ d3 \assign axr1 = axr0;
! L$ D I4 `) X& Y* Y% O
0 Y2 w8 n I/ o% c# W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- a3 e+ y# \( l bstatic void McASPI2SConfigure(void)7 O) p' y0 j# v" t9 p( O- ^- ?+ ~
{" U# t1 X) ?, g1 \3 _6 h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. q- \" _+ c9 ?' B6 ]! O( d5 OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, X d" C! K2 R6 l* J- S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 Q+ d& K1 e2 ]; w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( d0 x9 ^9 ?& \. U1 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 L1 Q" [" ^$ L0 p+ w" a& eMCASP_RX_MODE_DMA);" K7 R5 `$ v6 d R2 E1 {5 K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) |0 B: k; T' e8 ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 V- C, W2 s- ^3 l# [% x6 M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
m% h8 E# l' J6 g" ^6 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! b: q ~+ ]4 R7 j4 a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 j$ f$ ~" d0 p, D. D! M8 `. uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! e% V+ i* {# D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- d# ?$ D6 S2 x1 H2 n: }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" b3 Q- T8 t$ P, k# g! J% XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ t7 ?0 }$ K; [9 R) U; y7 x# d: R0x00, 0xFF); /* configure the clock for transmitter */# k1 K' E, ^. {' e# m6 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 _7 c8 i6 k: A9 g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 ?: d. f1 j- }! _( d7 C r+ I1 LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- p: e4 ^. r$ a3 e/ ]: V% ^0x00, 0xFF);; A" i9 K% s) { e* ?# [+ F
. I% B, ?5 O w2 t( P, i' s( |
/* Enable synchronization of RX and TX sections */ + f% N/ m# m! x2 u# N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( d7 ]3 \; J9 E. H" Q1 B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* q1 y5 h5 U2 m' E* |- Z/ @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ I V9 Z; S. M9 |" w/ j
** Set the serializers, Currently only one serializer is set as
* O8 N7 [9 F: i1 d** transmitter and one serializer as receiver.( l& ^8 z0 n' A% g
*/
' A2 @0 m6 {: G$ xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 b. ~% j# b* b ?: d, n& N8 Q% zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: x4 p# q1 m5 D
** Configure the McASP pins * Q) E& l! [( O9 @3 N) X
** Input - Frame Sync, Clock and Serializer Rx
, [; Q/ j7 j/ H$ P** Output - Serializer Tx is connected to the input of the codec * s% ?; W1 l# h+ m- ?" u; }0 N
*/
6 E7 R2 D. N4 U3 XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. U: u5 j& Q7 G! r( z) `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* t0 ^0 I" v) @7 i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# p u! o7 w7 R| MCASP_PIN_ACLKX# c2 I4 c3 j3 E
| MCASP_PIN_AHCLKX
- x$ A8 y/ S7 s; U, S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" U ]7 k2 V* {* z+ D! `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( w( Y) w$ g" L2 Z! }7 [& P4 U: O
| MCASP_TX_CLKFAIL
0 X9 z9 L* d1 W7 G7 _* e: i| MCASP_TX_SYNCERROR9 k z6 z/ D. x; L2 E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & I' I# q% E. t$ a
| MCASP_RX_CLKFAIL* |0 ~2 z% i/ J/ ?( z
| MCASP_RX_SYNCERROR 0 m# J7 q r8 v7 D1 {0 N) j9 s
| MCASP_RX_OVERRUN);2 [/ G" N% t* T* `% x5 B: [, W
} static void I2SDataTxRxActivate(void)
w3 C2 w8 S5 B8 O) g! j{! X1 X4 ~ U/ h8 D& d# }' _9 B* v
/* Start the clocks */ `6 J; T4 Z- s& e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 ^2 ]$ j! n, `& f! R$ |0 |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 r, c8 x9 W' T: q, @" J) y) m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) D: ~' ^0 ?8 E0 I' y3 HEDMA3_TRIG_MODE_EVENT);
! I L+ B) c) N1 A1 ~: T) rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 f9 G7 e% f# E- a1 N1 q( [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 J: S" m$ L% }5 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 N/ s7 w4 U/ t2 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 M/ V( |% K4 S+ Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
I* y& f8 m$ P* AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) I) @. @# c8 v0 E5 \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
o# p0 c( \" t) n} ; Z6 A! }# f6 h4 a- `- V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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