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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* m U* v- e* Z7 T
input mcasp_ahclkx,
9 Z) B, m5 h: @/ i0 l5 }input mcasp_aclkx,
$ d6 B+ k' S7 r& k* winput axr0,9 N6 L; w7 Q! |7 _9 ^" V; O
" w( ~( K: @# soutput mcasp_afsr,
9 i- v* @- _) C3 I3 Woutput mcasp_ahclkr,7 ]2 I' y V h, d) l/ }% i9 V
output mcasp_aclkr,
+ M5 h) V- N2 b4 @6 ^output axr1,3 V2 p8 ~+ H7 c6 I* k$ T
assign mcasp_afsr = mcasp_afsx;
* N1 n+ Q2 V, [) Y& Z0 O/ h! L2 d: `assign mcasp_aclkr = mcasp_aclkx;; i' B5 k4 Z" T; i2 f1 B' }
assign mcasp_ahclkr = mcasp_ahclkx;) u8 G& I+ F7 k8 q
assign axr1 = axr0; 3 Q0 V1 o8 v9 j) @% ^9 b* Z- D8 E
! J9 B. p4 F* x- H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! ?( c' W2 x; s4 C+ D0 Mstatic void McASPI2SConfigure(void)) G4 k( z% ^# o* ^6 ?5 u: i
{
X& D* Y: M% ]% J/ P# {McASPRxReset(SOC_MCASP_0_CTRL_REGS);* T# c; Q! O1 b0 @7 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 f: Z- X0 [6 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& t) A& p3 t P3 B- AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 _6 }# O$ I8 G3 s+ ^: K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) v; h5 z5 a B( e oMCASP_RX_MODE_DMA);6 j: f! P! s+ q- U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* g' j. `* J1 D3 ^( UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( n. w; B- \. ^ ~, k. ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 N% N& @6 Z! {% C# q2 |7 |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( C$ L5 K( U6 I9 o7 KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 ` c( D% H: h, F% ?9 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; H3 i$ w& p$ F- H# q: g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' \7 L; U& B) t1 k8 Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 v- _9 K/ B3 X/ O7 P& sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 c. Q+ D1 O7 @0x00, 0xFF); /* configure the clock for transmitter */0 Y8 `+ s, C$ j1 z4 |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ l) i3 e2 m9 }* C7 Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " x( D5 b( W* T) D; A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% h* \8 c* O0 _, I( a6 f3 o4 v( y% f2 w0x00, 0xFF);9 M$ \- c/ [4 K' U( y
! f6 t h% V1 r L2 B
/* Enable synchronization of RX and TX sections */ : j* D- }, M& ]7 [/ T& s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 n: l' \0 }7 W* \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 E1 v- o1 [" X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, A; ^, @, |; c ^; w
** Set the serializers, Currently only one serializer is set as4 k+ a$ q" O0 U# G. D! ^( n
** transmitter and one serializer as receiver.
: l6 [% Q/ J# ^; D1 `* d C*/
1 X; r l/ Y& n+ OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( F1 r: V+ [" T+ r4 z/ {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& X7 a. u. N/ m" `* n& ~6 I** Configure the McASP pins
; J. Z/ F) ^, U( ]3 }: \4 M** Input - Frame Sync, Clock and Serializer Rx# I( U+ ?' ]$ ]3 B- R
** Output - Serializer Tx is connected to the input of the codec 6 v' ` z7 s6 J4 x4 J# D/ @. H4 j
*/) R7 X6 q: D9 v+ Z7 r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 y+ o+ O8 _ |8 HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); |/ c4 b# o) K+ V+ @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ w: `6 \5 `% _2 ?4 D% `
| MCASP_PIN_ACLKX( J# u- r, [3 B# r. r: X
| MCASP_PIN_AHCLKX
; ?# b5 P8 n; W" W8 i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 E2 y0 ~& g9 ?* q7 tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 O, b8 C& E0 Z# w/ m3 D- t, ]
| MCASP_TX_CLKFAIL 6 ^0 l* E% M' j$ c
| MCASP_TX_SYNCERROR3 g; ]9 R/ v- U9 _% }/ k. P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; ~2 } a( f+ g& g| MCASP_RX_CLKFAIL
" V3 [) K5 Q1 J7 B; m| MCASP_RX_SYNCERROR + w/ O) j1 v$ {/ I0 C% k, B6 W
| MCASP_RX_OVERRUN);& c+ {, t- r8 H5 }# M
} static void I2SDataTxRxActivate(void), X, j% M$ B6 i: L9 e
{
+ c9 `3 u: o# u+ \/ V, V/* Start the clocks */: {: d! L) N- |0 K& J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. s' k: e7 U: N' S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# j8 |) K8 k& V; d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- }1 ~+ a3 p" m4 }
EDMA3_TRIG_MODE_EVENT);
* D+ J6 A( e/ V2 f5 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 \$ a/ l) _- ~6 h n3 x) v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. k; R d4 q( p0 W4 I2 j) K* [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 }3 X! C8 U" v6 _) X2 `+ Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ B6 T8 K2 ~% ^3 n; V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 y( I: V5 H4 m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 g: E4 R$ I3 G9 l- O1 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 p- T7 J0 {5 E. |
}
0 ?* j, N5 {* Z* Q+ J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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