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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# N0 y& F1 Y: @9 T3 V. R( f
input mcasp_ahclkx,0 y# H) J0 l* B0 ]* x( t$ J
input mcasp_aclkx,5 t3 \" U0 D9 U, D% _6 d5 q4 }7 i4 o
input axr0,( B% a. g1 l8 f* R8 g
1 A: S' U: _# j% _1 goutput mcasp_afsr,# t# R" v3 W4 |8 }. u# U. I
output mcasp_ahclkr,& w" K \& X( `+ K2 ^6 m
output mcasp_aclkr,5 N4 H" x* m+ M {9 K+ ~
output axr1,
2 I1 e2 q, B* t! a7 h7 p: c assign mcasp_afsr = mcasp_afsx;5 G/ [8 w# _* M: u, T* u
assign mcasp_aclkr = mcasp_aclkx;
: l0 s$ j" K. n+ g% xassign mcasp_ahclkr = mcasp_ahclkx;( R$ v: }8 m ~6 f2 K- q3 l
assign axr1 = axr0; * Q0 ~" U7 Q+ _ c
) c- z+ k8 ?% K7 z9 W3 N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " ]/ X9 I- {3 X! Q4 g
static void McASPI2SConfigure(void), G3 Z+ N' a, R7 g- Q; l$ q
{
" a+ \4 n8 G; }% ~" u. \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 _7 O( |% s2 B5 e; {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
[* C5 M( V3 r' WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% r( k- f x7 d" xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ _0 w% j$ ]* f) g; _2 w& h% G( WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- x& {' }% }' U' ?/ y( t
MCASP_RX_MODE_DMA);0 c, P* r6 [+ s4 G7 I1 i6 [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 Y4 F& J2 i4 _# f+ f& cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% R) X: B% q' e, h" c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& w* C5 n% @7 e& I1 _5 @7 ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! ^* X$ H7 H( v- W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 o5 E* L8 y2 X A0 e- G3 ~/ t* ~+ m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 |/ K6 `6 S2 l! Q2 S% f, B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 F4 [$ s# H: N& Q4 oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 e7 f9 d* Q; @2 f: }* BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ m+ E& k& N/ a) F7 L- R0x00, 0xFF); /* configure the clock for transmitter */# d9 h4 S+ U- ^! u }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ P5 E* ?) R# d. u6 V8 k$ j/ L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & Y, T; q0 ^7 {2 N4 X4 _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ ]0 S% k0 h1 e& q
0x00, 0xFF);2 [) K U$ _4 {" z5 U" A
! D) M. n+ t4 n7 O: o
/* Enable synchronization of RX and TX sections */
5 [+ E9 k' {* `5 \- r% o0 g( nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) t! _" F7 P4 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 g. K4 s/ W9 o- O0 ]% ~5 P/ eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ b) {0 D5 m1 }$ {9 s* }0 H9 o, a' h
** Set the serializers, Currently only one serializer is set as s+ I& H% L: D z# ]
** transmitter and one serializer as receiver.6 J& y& q4 L! k7 |; R- I2 v4 y- J* [
*/- z$ A) E9 J8 B1 W0 R/ _' V x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- N6 O* `" i/ }+ i' w' P+ Z5 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 B' {# Z+ g: r$ J- `** Configure the McASP pins
" W3 K1 e' m& u/ c** Input - Frame Sync, Clock and Serializer Rx
% h9 I& |" H+ A5 P& _** Output - Serializer Tx is connected to the input of the codec
! l5 U* G/ I, G; p4 ^' @0 f4 ^3 ^! [2 X*/* R C; x- o7 s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 B& A5 A& I' Y$ IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, m9 `6 T: L/ q( |. y; O. m" FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& _4 M, O$ e9 a5 f! P4 P$ J| MCASP_PIN_ACLKX1 Y3 N! w: k6 e& G4 `6 w
| MCASP_PIN_AHCLKX
+ ]) `9 Z+ ?6 R: ]7 p. J: @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% ]* P2 k/ Y; [% t3 I' s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 X( R- z% W( ?5 F( o! a+ o
| MCASP_TX_CLKFAIL
0 t& U @) p: z& D8 n, V3 j| MCASP_TX_SYNCERROR
4 h9 E' T. V- c6 I3 N2 r8 r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% R3 \% Z4 `9 G P s| MCASP_RX_CLKFAIL
% Z$ P! s8 U* g| MCASP_RX_SYNCERROR M; G( @! [# ~' ^/ w# T7 [
| MCASP_RX_OVERRUN);
* R |5 ? @6 {0 w+ j} static void I2SDataTxRxActivate(void)
; L5 [7 H! j/ p" V+ E) K2 I0 w{' N4 ` d1 e1 j& o; F# {% c
/* Start the clocks */, I$ U& J9 L4 t" Z1 @$ G5 C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# U: q. H' B0 Z( |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) i$ C/ W8 D; v% V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; T" |6 z( W, W5 I$ XEDMA3_TRIG_MODE_EVENT);, c. J, N, r! u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : {* p. y; m$ e) S5 J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ n! [7 J6 ~5 a: \& W: Z, y6 Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 o& w5 r5 s: t5 A9 f# a5 }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" z) P% i2 |5 f8 ?: I l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* i p6 S& P) O1 i% g' [1 v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); H$ j; ^/ h5 }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 z1 X: y8 y) {
}
' w' `9 H/ ~' R6 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 }. ?3 `6 A5 }, k! g
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