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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, w! R7 G; j$ D$ ]& Jinput mcasp_ahclkx,
+ L$ |9 [! |- binput mcasp_aclkx,
: {& q8 G6 e N$ w& ~3 l* j$ finput axr0,
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output mcasp_afsr,
% L( B9 x y3 ]* V- o9 w toutput mcasp_ahclkr,
' X: A1 o7 h9 Z, B0 Soutput mcasp_aclkr,. S1 l- f" `: P
output axr1,$ y( r# W- ?+ b6 d! \% k {
assign mcasp_afsr = mcasp_afsx;. f- h' ]* `2 d: {
assign mcasp_aclkr = mcasp_aclkx;2 g9 h1 d: O3 u
assign mcasp_ahclkr = mcasp_ahclkx;
' }6 T) E* H: z' [assign axr1 = axr0; " G; d! E9 o0 X4 g
+ P+ h: F3 @- a7 C$ t! x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 H" k% `2 H0 I( s) p8 M
static void McASPI2SConfigure(void). R, l' w4 U1 ~1 d- T; s% R; S4 n
{
0 H' l4 d0 @- l6 `6 Q" ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 P) Q! x/ {$ S. W7 hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ Z2 P% h) s# H, T7 O* mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- |7 M3 ^& i& F0 ~3 o0 }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" n/ v3 v2 O+ m, R; s1 Y. J9 g7 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ]/ ?* Z1 @% U# UMCASP_RX_MODE_DMA);
/ j- W' l$ H ~5 C; @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, E3 d0 u( g" ^0 E' [: m. m" x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- i) c9 V# D+ _2 L$ _% A! S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& [5 h2 e. {5 b ]% h+ Y5 _! bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 Z" \9 W) z2 M) m* i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 l8 S* W. [- W/ s0 \( EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 C5 |# _7 N+ GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 V& d# Q5 R4 b5 F2 Z& ]8 I% ?% |! dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. Q1 @- h9 o* F) W2 \' RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 i1 n# p2 ?5 c1 e* J& ^: t4 \: W7 m9 }
0x00, 0xFF); /* configure the clock for transmitter */' `" B, H: [) U, b! y1 d9 W7 Q7 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* }5 q) I/ d# L z# fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 f# A* ?: e" C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( \6 r5 k: S& c, U2 k
0x00, 0xFF);: Z! O9 K! m# B8 G3 |9 A# A8 H8 C
# m" c' ^2 K+ l8 T, _4 o3 }2 e
/* Enable synchronization of RX and TX sections */ , D9 m, ^* I9 n, A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ [( ?" S/ G! Z2 y/ A! u7 g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& x& Y" o1 o/ j) HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 v: ?+ `6 H- y( W' H+ o** Set the serializers, Currently only one serializer is set as
7 D" L @/ k2 E: y) }** transmitter and one serializer as receiver.! e. J/ i0 t0 D3 [+ d
*/
" b! Q; a( j- Z0 v% A' u/ r* Z/ YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 N' i* e% C- s$ HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& c/ A8 B& D% F0 i+ p0 m# P" z
** Configure the McASP pins
/ p/ I8 j& D+ }4 i- f. b5 L** Input - Frame Sync, Clock and Serializer Rx% Y' v |* ~6 Y7 J
** Output - Serializer Tx is connected to the input of the codec
& ^+ e7 N3 ~7 M" @% n2 Z! X- P: o*/3 F" y8 c0 F% _$ X) ]+ ^/ D6 t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 s7 F2 K: Y8 [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ E+ \, R H8 i* [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 H; K1 a/ F2 I0 _2 `6 o9 B- i| MCASP_PIN_ACLKX
9 Z1 D4 B: L* X/ B d/ ?3 u| MCASP_PIN_AHCLKX& R& b& L1 W" q5 d& ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; V; w4 {0 {9 o1 {; ^4 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' }+ b$ X. i, C* v- S/ }| MCASP_TX_CLKFAIL
4 Y3 s8 w" F! Z1 {8 H) z| MCASP_TX_SYNCERROR; L$ |* q7 \$ Q2 z& h2 j. G2 }% a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 k! b8 m0 G0 {0 O. ~' L$ M
| MCASP_RX_CLKFAIL4 ~/ X4 L; l1 G. W2 L
| MCASP_RX_SYNCERROR 5 m( G0 `1 a9 t1 C) S
| MCASP_RX_OVERRUN);
4 Q! Z; ?" t8 U4 o} static void I2SDataTxRxActivate(void)
t: ] V1 n! w2 H. ?{
( z% c Y7 X- @/* Start the clocks */
$ b$ a: Z" u; u) L, G, q Z+ v4 i3 p% nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 T' b- ]0 d( OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" m6 e7 G( ~) }" W a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; S1 l- H( d9 [! UEDMA3_TRIG_MODE_EVENT);
! p! S8 V% _* T, h& p/ ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; @+ d# D6 x# l+ ]: a" O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' D+ k0 t) F j" }( L+ I2 Q4 K0 Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ P' Y: Q6 R0 k( k2 D6 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. g2 c; j7 V5 x3 }6 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 W6 _7 ]" O1 F. a4 d7 l+ c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
^& [$ p9 C' X8 I8 i0 q: DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: e" E6 ]0 p" t6 a- V3 n
}
; M9 n- T6 A% U! ~! ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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