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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) n% E8 p' }, X& U7 X
input mcasp_ahclkx,
% y. G3 L/ K2 `input mcasp_aclkx,
+ H! V w i& `9 x( k$ ninput axr0,
h& ~, l& u, F+ j
: T3 Q+ }4 @/ |- D+ Y$ noutput mcasp_afsr,1 J' C8 Z6 T: o
output mcasp_ahclkr," h6 c- I; W) U& p; L t; b
output mcasp_aclkr,% N/ |# F" H2 h
output axr1,
# d/ S& d# ~8 \8 u* Y8 j: J assign mcasp_afsr = mcasp_afsx;
6 D7 E$ R- J' d. I2 E0 \: D) i. Sassign mcasp_aclkr = mcasp_aclkx;* m( Z, C* f+ F" i: e( I+ ]/ b
assign mcasp_ahclkr = mcasp_ahclkx;
3 `. d' t% h" h* e6 Gassign axr1 = axr0;
" D# P6 U) J4 A. B+ V; U# y. P
7 n$ \) x: D+ L* z8 V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( x% C) S4 h/ o9 x: L
static void McASPI2SConfigure(void)& q. U: f" D8 Z9 u! g
{! x) s: [6 Z7 l5 T& W& Y2 `% v2 ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS); Q/ ?+ T4 C- v& @1 _! V9 p/ } }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ B0 |% c9 c( L' g* Y. {+ d4 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( i7 T' N7 X* K/ d# v8 D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 c+ }2 T1 R% b$ X4 W$ B& eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* I6 L2 H0 q7 L
MCASP_RX_MODE_DMA);
; | k9 e5 j' ^+ AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 y5 b0 x% u/ BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% v6 k: {/ O- J a& r: |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& h' Z$ i$ p0 yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% Y$ h( t! t2 U i$ B1 ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ H2 X1 i6 O% l% L' fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 p# Y; d# p- l8 t s& i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); r0 X3 e" r! ]* e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 _: w* |. W/ V# O$ U& ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% g; u) H5 Z k9 U) R" L0x00, 0xFF); /* configure the clock for transmitter */7 C2 c$ a! ?" u- ]! x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! U/ w; S2 r* k& q! _+ m. c! DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! A, T# C6 K0 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 O% ]+ l% x( H; M8 Z' p- E
0x00, 0xFF);* o! n% H% \! m* B
" I% ^# A: w* X0 ?
/* Enable synchronization of RX and TX sections */ : q& [* K8 S C& V2 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 V! W2 G$ U3 q5 ?# G- CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( ]7 k, I# h1 X6 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# n) o$ ^" c" G7 g) a6 B
** Set the serializers, Currently only one serializer is set as i/ [2 ^; Y4 _, r6 ?. c
** transmitter and one serializer as receiver.$ k/ C1 j0 S. i, q' o) Q2 e- D
*/3 }' y4 V* R& W+ ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% P' a4 m S; I p2 N2 @- K/ kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ R% G$ f X- H, U% G' H; @** Configure the McASP pins 7 u, f1 S- R4 Q+ {: V) N) J
** Input - Frame Sync, Clock and Serializer Rx
0 I3 A( g. N* F6 `" N/ v** Output - Serializer Tx is connected to the input of the codec " u& E7 }0 h! Z( h
*/8 n% r/ _" K; u' n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 I# }% _; p" q! q ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, e% c/ @7 z4 B( BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' h/ W3 Q0 {" n, ^- l- P' x
| MCASP_PIN_ACLKX' e9 E' s1 }# x6 t! x1 k/ |: z
| MCASP_PIN_AHCLKX
" j! ~ b7 F8 g# ?4 g0 K% O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% b4 g3 P8 \$ z& Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, F/ \" K9 v" s, f1 u$ r| MCASP_TX_CLKFAIL
; O2 f0 B1 Y) U, r$ C| MCASP_TX_SYNCERROR
, D5 X; |/ v( {- ~* t4 n* S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ u4 @% J0 U& n8 _| MCASP_RX_CLKFAIL
7 }* h8 e0 z3 i& F/ ~2 x5 S| MCASP_RX_SYNCERROR
5 J" D, R$ W* ^' }7 {. x| MCASP_RX_OVERRUN);, {9 R* S: o% N' p* y
} static void I2SDataTxRxActivate(void)2 S9 k; \) j+ h. g5 }. ^
{
5 z) ^" d7 _, T/* Start the clocks */
0 j1 O8 C! p. H$ L0 b! VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 |: v5 z+ Y+ x) y" O# f- oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 F7 F7 t0 ?$ l M/ y( l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& c& @3 [. p5 }. a, d/ d$ O; X1 zEDMA3_TRIG_MODE_EVENT);) @' K6 b0 Q$ d$ r( M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # C! d/ U$ W2 I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
s" C! I1 H9 N. E) p" lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 |, |0 l* @+ K3 I" H/ yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' `* W! f, H5 @' i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, j: b; e5 e3 R% h7 e% N T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 A; K0 r# d( d) \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. L) S8 ~. t+ @
} % I. S3 v: A! H4 g; d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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