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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- D0 Y* v# e/ \/ a6 J8 ~/ H$ binput mcasp_ahclkx," K: ~6 ^ T. Z+ n
input mcasp_aclkx,7 b" H. N+ W1 Y$ U' ?
input axr0,5 U4 A8 D+ ^, ?9 B( D9 t/ J
2 }, S% k2 t6 E: Routput mcasp_afsr,
; w7 B( } ?7 qoutput mcasp_ahclkr,
- ]4 ?( j6 Q* O+ k" ooutput mcasp_aclkr,. J# J( e) g3 W/ @7 @
output axr1,% m3 a1 e% O) P" B
assign mcasp_afsr = mcasp_afsx;
0 v1 @& h# t. s5 _* o7 nassign mcasp_aclkr = mcasp_aclkx;) H' S- B4 }4 y4 i5 V
assign mcasp_ahclkr = mcasp_ahclkx;
9 ]) c' n/ J* b* r4 |. U- u7 x' rassign axr1 = axr0;
% v* c8 N8 x5 t" z
, ^7 ^6 \' v3 }5 d. I- h: }0 O9 ?# B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % |: K5 t) X- B& W" S* [+ k" x6 H& B
static void McASPI2SConfigure(void)8 j' ?, u( T' I- n7 y" S: k3 c% I, H6 ]2 Q
{0 u* Y+ s+ g- p, }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! I d6 L$ s. t" w2 V9 @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 \5 x! F0 H0 E8 N, Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# |( }% J. n; i3 p' oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 Q: T& L, f- w5 b. {1 E' N& @5 AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ |( \" `9 B! a+ ^
MCASP_RX_MODE_DMA);
5 i' _5 P: F0 QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, a& Y/ K. M4 H, |& ~7 C: R6 E! G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% U2 M' B7 v4 t! |" H: T: A# tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ I% H( y; Y2 z: j* z. SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 {; H7 ]1 {% l7 f+ c7 n) {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 E$ L# u6 L4 T& A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: J- x2 W9 b7 B$ m: n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: K, s9 z: H0 `4 @3 U- xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. x$ t$ `: J5 Q# s# s# u3 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 N# W4 Y' T5 o* V- O3 V0x00, 0xFF); /* configure the clock for transmitter */1 z" m5 l {0 @+ [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ @& {7 L E" g5 _1 V* i6 O) |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 r1 v8 J6 y( g C8 I. @" \1 f; NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 V& T9 v7 L" X+ U) g, g R
0x00, 0xFF);' Z3 l! [( ~% D- s8 R1 B. r
+ o- y# l( q% O* n/* Enable synchronization of RX and TX sections */ U4 k' B7 R$ N L& y9 n8 K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, r" E9 E: K+ \2 s3 B4 _/ X1 Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 ?: a5 |# [1 f u2 B/ i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 a- X6 C: m$ t; d! D
** Set the serializers, Currently only one serializer is set as
1 m0 W7 M1 M/ d7 p8 `2 @1 e** transmitter and one serializer as receiver.- z& [* G/ y4 z0 H
*/. B, M" A/ T; C5 B% _, U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( V0 d" g3 X6 w" u9 s b% AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 [$ K: c/ ^! B* Q3 U
** Configure the McASP pins
9 E% G% k; n- b) C: L** Input - Frame Sync, Clock and Serializer Rx
# {7 ?* \! b$ Z- ]" Z* C% l& K** Output - Serializer Tx is connected to the input of the codec / M7 S9 s N( y
*/. k, j) Q" w! r4 c# m& T) p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& h R) |) @$ C& _* R, PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* @% e- M0 A5 y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- V) J5 [4 `0 i, M' B! o* q
| MCASP_PIN_ACLKX8 p/ [2 d1 _1 ^1 W) |+ q* G
| MCASP_PIN_AHCLKX: l; D% I# I. j4 u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 u; f9 e! n* R) Z" O" ^# |! sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 L1 V; M* g \
| MCASP_TX_CLKFAIL
, h3 r U; H2 C& n9 {7 T# c| MCASP_TX_SYNCERROR8 `1 C- U1 W9 |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 W+ e' q' l n( V6 q| MCASP_RX_CLKFAIL7 T+ E5 v7 V4 e
| MCASP_RX_SYNCERROR 8 h L) g! e' v: F8 e7 K7 f# M
| MCASP_RX_OVERRUN);
/ b/ F3 z# [! D6 A# s* @} static void I2SDataTxRxActivate(void)
; |2 l5 R8 H" U0 F{
3 S, Y9 E# C5 f/ Y- Y5 G/* Start the clocks */
/ r: \) x" S4 y1 r3 B& bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 c# L. G$ d' l8 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# c9 e6 V& L* L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 Y( K0 e% E2 iEDMA3_TRIG_MODE_EVENT);- {+ p4 w/ F, [, k W: c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; P8 V m' U" p8 y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 j* g& d! R8 }% m1 S5 H5 jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 Q8 S3 c' z9 R8 j4 R+ P7 @ S! IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ Z1 h2 B2 Z D8 `& V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- n r! Y$ t# R" i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 q& a1 K& w; {) m- y! c- H& ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 x6 r( M6 I! Z' y2 W
} 8 e+ E* s4 x4 Y& F4 ~! B4 A7 w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * Q3 w1 Y( b; P: ?
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