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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, G6 x1 E5 J( h" ~0 E
input mcasp_ahclkx,
1 P; ]7 Q1 H/ m0 c& j9 c R% e+ @input mcasp_aclkx,* t/ `' ^5 j+ I8 l
input axr0,% `( d/ T0 f% o/ w& S
5 |1 a$ e/ h5 k$ N
output mcasp_afsr,+ ~- F) n( ]& K& v, `2 [% p6 Z- y
output mcasp_ahclkr,* g# C/ m+ s: R; _
output mcasp_aclkr,
8 b8 y' C- y' T5 A+ K: Loutput axr1,9 L e! ~5 w6 D. L0 \8 i0 D
assign mcasp_afsr = mcasp_afsx;* A7 m8 L. w- b6 H9 F& r; l7 M
assign mcasp_aclkr = mcasp_aclkx;
' g. M: f: m$ d( ]# Q1 l% Lassign mcasp_ahclkr = mcasp_ahclkx;
$ a+ o0 w; Q) k5 B# c2 ~" W# wassign axr1 = axr0; " z% S/ m, r8 F
9 s/ w7 l. l0 s) D, Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . j Z% \2 }) a; e* M
static void McASPI2SConfigure(void)0 Z7 M) R7 p* W4 ?
{3 }& \8 B6 q* ^( M# C& \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 p4 ]) [8 {1 s+ t% ^* d3 I% oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. ^" Y& r _' T, ^4 n3 C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# W& X W5 { D+ \! ^. i8 ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 L2 n9 x5 }- E# ^4 c. Y0 a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: m& x0 L; Z ]. n* iMCASP_RX_MODE_DMA);
8 i* g" x- t/ u7 k: M% Y7 N2 f- YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 O& |+ \. \- j7 \# z9 \9 LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- @6 `3 D$ S% h' e7 u* zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / `5 R7 P0 h" H# ]0 x1 r. `; ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* }7 y/ g9 h; i' ^3 y" \* qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' o9 m8 {2 Y. ?- {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 }' a, d4 O# R& A" S, B4 U! Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( c l" u0 f! E, [% G% z p5 oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 r/ y' F7 W5 y- r/ z# c/ o" uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: x3 b/ ?. j) _) {
0x00, 0xFF); /* configure the clock for transmitter */) t& d3 p9 p+ N- J" g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) k& h# g0 | ^# T: j: j; NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # k# n b" c- U3 ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 {+ L; v" G5 x1 e7 a0x00, 0xFF);. i* A! ]: Y J& v* s/ c+ M
* y' J& g, @* u9 t* x0 v
/* Enable synchronization of RX and TX sections */
" r7 Z( o5 s9 U, `8 w/ f$ | GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, L4 a. p+ \- W; u( a( {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: J% o g" i' z4 Q: HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: U# }+ o: e' T, @0 T** Set the serializers, Currently only one serializer is set as
& @5 x) q5 W M7 w** transmitter and one serializer as receiver.& @0 {! ]' p. R$ h5 ^0 @: Q7 h; T
*/% |, a2 G5 ]5 V% s, ]% S; \5 E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 K8 b8 \$ F+ V3 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ G% T( J5 j4 Y, c7 C
** Configure the McASP pins
I: W* u# j7 P8 B& ~# M8 p** Input - Frame Sync, Clock and Serializer Rx3 |' x' B! E# R. [. { X
** Output - Serializer Tx is connected to the input of the codec % a. V' Y5 i) {- y# k
*/2 @1 q. E) V3 j. R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 v6 R3 f* m* ^( q; N3 i' w BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' a( p" I0 c0 K9 ^6 D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
{' w. _) ]+ C! P) {( d| MCASP_PIN_ACLKX
, {- M: {8 a0 _3 [* x, `| MCASP_PIN_AHCLKX
( k8 e7 Q1 c3 G# w5 h' A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) d( }- V: ]! I( ~: W b `6 ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * d# \: K& f8 p
| MCASP_TX_CLKFAIL % `% g; `* a9 \+ y3 x1 n
| MCASP_TX_SYNCERROR8 _/ o5 @/ o7 B) |# ?; c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) t; \/ L# a3 w8 `| MCASP_RX_CLKFAIL
* ?+ H' E) g1 Y, f: T/ @| MCASP_RX_SYNCERROR . m, d9 J& l* _
| MCASP_RX_OVERRUN);$ W/ R4 @7 b4 r; I* _2 L1 o# r
} static void I2SDataTxRxActivate(void)" t7 o! O: ?- f' M+ {
{
9 n' P' j' N) m0 I/ m/* Start the clocks */% k: j) J2 [2 H9 y5 h. K! k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 c$ [; P) y& `5 o" OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 {. e( a1 G3 _% J! u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( W5 L( N# J+ a4 Q8 j
EDMA3_TRIG_MODE_EVENT);
/ s( g5 y/ F h( t" O7 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* C3 v |* m( Z- F; c/ YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 v7 }$ y# j% `' P" x0 `$ rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" n, K/ J) [; @0 g* q) m* Z- W7 q) GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
t3 ?' C4 X" U; U K7 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' }9 H. \& N: O |9 M+ J% I. sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 I# A+ D7 T+ N# R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, m- } ^9 l& q8 W}
' r3 o& k$ p+ ?) F t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + w! x- I) d" x B _* ~
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