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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 a b6 j% l/ k1 n
input mcasp_ahclkx,
) @) s+ X( [& g; p- c9 @) jinput mcasp_aclkx,
8 p6 e! [- U8 N9 `input axr0,
4 ]* k3 i3 s5 E7 o0 @; n% T3 l' s* Q: m& k# j8 ~9 s8 c- w! g
output mcasp_afsr,
6 A9 c8 U" g0 W) Xoutput mcasp_ahclkr,
4 P! u! \+ q. Ooutput mcasp_aclkr,! g, W% L( W* T# W. Q
output axr1,
0 o$ P1 s; L' o* k assign mcasp_afsr = mcasp_afsx;9 j3 J; [& o' U
assign mcasp_aclkr = mcasp_aclkx;! _) z3 }! ^3 \& ~2 l( Z4 Y
assign mcasp_ahclkr = mcasp_ahclkx;, T+ a" H5 u) W, N2 m$ m4 j! B4 I
assign axr1 = axr0;
5 ?% }5 d, n2 y' \) f2 J; y) a7 x7 ~3 V* y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 I9 E2 w2 L5 E/ o; } J2 T
static void McASPI2SConfigure(void)
- l2 \. r3 t- Y/ c7 W( W- Z( H& y{* L' { `4 v* m+ V1 n/ N( O9 S' x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( z. `& U3 M. A3 S' m+ \McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 t7 B' O3 Z4 r5 w9 d' `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 Q! n8 b; E' A, ]: m6 lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# w9 J3 J2 v1 C4 S Q9 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& p8 y# T/ D& OMCASP_RX_MODE_DMA);
, s5 }+ X$ i- }$ g1 D$ WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ L- B0 a$ S1 @& @. c/ m+ QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& K- J" K, Q8 l' r. L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & m% U* J. o9 ?) m" H0 w) l @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 ^+ K/ C9 J$ M. q5 D4 t& q) [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 }1 y6 M8 e8 W3 y1 P' Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( h2 _6 i& B2 D* [' d% A: x, L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& J" R) {7 V0 {& ?& d! i9 a, H# [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 @, x& @+ k k+ `0 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ h2 n6 v6 ^3 B s ~- j% R/ ?
0x00, 0xFF); /* configure the clock for transmitter */6 u3 n: {# D1 x3 }+ t4 ~ n) w# M9 s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* V7 l3 N6 l" t, G& h' R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! A. ?3 {1 T! r) V) m$ qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ P/ l+ B7 i) |/ C! e7 E- b( B( `1 N
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
* m% o2 [ k k* [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 J2 o6 u X7 U1 W' C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! A" w( \% k; F, |3 z( P) @( L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ d$ D6 Q, r$ r
** Set the serializers, Currently only one serializer is set as
* a# H- S7 w- V5 N2 A4 v# S: o** transmitter and one serializer as receiver.* K( k- d2 l( p$ J5 A; l
*/
. v% C7 m0 n; DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, H" K W1 y8 n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 U- t" S( z, A$ N* \, T
** Configure the McASP pins
: {+ }4 D1 Z) a4 D6 {** Input - Frame Sync, Clock and Serializer Rx1 {+ m5 f; K# f
** Output - Serializer Tx is connected to the input of the codec ; d! V8 ~: F# N4 P
*/: r4 t$ E: d5 s2 H/ w% C/ M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); D# U& ]3 l: o' O: W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& `' v) \5 B+ \" O- i; }- k! E% s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX Q1 n& q# e& b! F
| MCASP_PIN_ACLKX
}* k/ r% ]+ c/ Z+ m; N| MCASP_PIN_AHCLKX
: U9 y6 J0 }! p3 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* d! @) X" `) d) ^& ~4 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 l. u' g4 w P: l| MCASP_TX_CLKFAIL
7 t7 h- [& q* }; s| MCASP_TX_SYNCERROR$ Q$ I G. _2 ~7 b/ C6 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- N. i$ q c$ X. v! m7 C; A; D, g| MCASP_RX_CLKFAIL
4 @5 S* V" q1 }+ S2 _. Y/ P| MCASP_RX_SYNCERROR $ o; [" J! T5 i3 V A; y! ^% E
| MCASP_RX_OVERRUN);
1 d' k9 ~# m s0 c2 A} static void I2SDataTxRxActivate(void)
) V1 O7 @% O! j" Y{. ] D; X E8 V! d9 \% M4 O
/* Start the clocks */
2 q$ Y: m- t' ^' h7 l7 wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 L+ U8 F x( D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 w. r% P% O/ z$ B+ @( tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! I" a: R- |8 cEDMA3_TRIG_MODE_EVENT);7 v; G9 n; r) z) ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . G2 j4 k5 O: C7 n- n. S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// J+ u- _/ W5 b- Y, T2 C8 {3 n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 `. O4 b1 B, d5 B5 |' GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" f2 H8 ]' }. E- v# H& Q) z- k2 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% |! M) u5 C7 t: G* FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 {1 `2 s4 `4 ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 i" P0 U# i$ _; S9 h
}
$ }3 a* }( `6 G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / n2 P% y1 g+ O+ @# E5 L9 t- o9 X
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