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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( I% k( n$ B( i" W' linput mcasp_ahclkx,. a& U: H+ o8 i' U( x& X
input mcasp_aclkx,
. k$ e: r4 `1 a5 ]4 @2 X7 z( Kinput axr0,
+ v$ Y' V0 v7 ~! g- E6 S' o7 I7 {$ B8 L0 T9 n3 e# X
output mcasp_afsr,
" @; x$ ], a+ doutput mcasp_ahclkr, C( v( s3 B y& `, }
output mcasp_aclkr,
7 o; O/ b% S) u; j4 G" N( houtput axr1,- H4 V6 S: Q6 n: w# J1 z/ T+ S
assign mcasp_afsr = mcasp_afsx;
. U" J0 E- _9 I) E$ [. Passign mcasp_aclkr = mcasp_aclkx;- U2 k+ `. F; R7 ~" B
assign mcasp_ahclkr = mcasp_ahclkx;
d/ f% z& B7 J$ J* y* Aassign axr1 = axr0;
' x* L, D2 Y1 p% K7 Z$ R0 ]: [
8 q2 C0 X- Q2 C' z" P& X3 g2 e/ |) c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 Y9 n. p* l% p" c, f9 i
static void McASPI2SConfigure(void)9 K7 @ `# J- l( m
{. E- M. j. s1 E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# S: c% }. J% B. @$ u6 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& W; Z# u7 Y r6 N7 g3 T, q" U" T( \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 n. ?+ A% G, l/ n% J0 lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' c3 a* s. n4 M, k: r ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ n$ \9 I1 k" y" Z# X1 F8 V, AMCASP_RX_MODE_DMA);
, ^5 U- `) c6 m ~( RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; @" J; g% Q8 @$ Z4 `2 p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 Z- a3 {6 P; A" ?2 z4 v% j- y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 {5 l& z" K3 J4 I) d0 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 z: }! v0 r' h6 _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 E. Z! C- p: ~- N& s$ `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( N# |8 }( T- b4 t! F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 N6 F9 w! A* S7 Q0 E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); Z- \, w% Q5 H9 M$ X5 ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. y5 e# T Y: u* f8 g: g' Y" a/ ?
0x00, 0xFF); /* configure the clock for transmitter */0 w1 _- z6 A3 ~$ R' ?% e! J8 k e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 k2 [6 [) }6 V$ v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 |8 ]" I/ r1 g2 z* RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ N4 s2 b, y- E3 n! r0x00, 0xFF);9 F8 [; d6 T [4 B2 M5 ^* a8 E
( d5 m" a% q0 R) M8 V* y
/* Enable synchronization of RX and TX sections */
- e2 N. f' A: pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// t3 R$ h1 J- m2 B: o, A2 y) Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
N& ]4 |) I! A) yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- s+ [$ L" @; |2 o** Set the serializers, Currently only one serializer is set as, b5 }+ _+ I$ X& V9 j
** transmitter and one serializer as receiver.
. |- ~, {8 Y1 i- S*/8 q$ S5 d+ V3 `- ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 Y4 y4 H: @; j. @! zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 C4 B; s3 Y( Y6 k) A/ T
** Configure the McASP pins
3 Z ~; D4 G0 q" D/ ~$ D** Input - Frame Sync, Clock and Serializer Rx
! l3 Z. d+ o7 B** Output - Serializer Tx is connected to the input of the codec
/ n- T7 R0 X! k5 F/ L) m3 q7 D( ]*/. \; b5 q( F' ~6 S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 K8 D. ^1 X; q' s y) N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* |& x9 k! g1 k" kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" A: O- q- z2 i
| MCASP_PIN_ACLKX0 \) b6 I9 y, X' T4 ^! u4 V; d
| MCASP_PIN_AHCLKX
5 m6 l: o/ Z9 w8 O3 D/ x4 w+ G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ ^8 f) Q1 T0 s& @3 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 C9 z: r" _9 |6 b
| MCASP_TX_CLKFAIL , `) O6 A8 a; e* E/ m5 x& M+ [- H; i% @
| MCASP_TX_SYNCERROR
2 o/ A3 I" j0 z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 b- a; \3 s% Y" R1 v- ~| MCASP_RX_CLKFAIL
, P3 e+ u0 {) Q' G) c6 [5 h| MCASP_RX_SYNCERROR ' ?1 S, Q' `" m; L; B2 m
| MCASP_RX_OVERRUN);4 p7 ^# v& O7 b" \9 C/ h
} static void I2SDataTxRxActivate(void)
1 c7 G+ @& z" S4 z o+ N4 `{
8 F' B1 p9 N" p/* Start the clocks */# |+ ~( @* {7 l( f6 h# g6 q, ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 ^0 J4 y p" b& \. eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 y# Z1 q, Q6 s8 Z2 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 u G. u9 Q9 `+ W) vEDMA3_TRIG_MODE_EVENT);( v) \% M v$ `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
r: ~8 g' |* X; c5 _6 R! yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* H0 }2 i" |, H; Z- N3 dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 x% X7 w& b/ J) s; \/ A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ n" z O* D( ?) Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' P6 f" z5 w7 }0 o- |' ?0 }* aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% {0 U- M6 `5 X5 K0 y N3 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 x8 R! U3 d+ j! T) W
} " _- ~% ]. n) g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* V) @7 @# u- W# k5 {9 l/ t; ] |