|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. D8 g6 K! [+ u1 [input mcasp_ahclkx,
5 v4 @* Y' ?# cinput mcasp_aclkx,
& u. I3 |: J, Sinput axr0,1 _& q8 Q7 F) p7 J# q/ s
$ J' j' w% }; Q G5 D! Noutput mcasp_afsr,' ]# v+ Q" n; F7 x
output mcasp_ahclkr,
5 s6 T6 m: {" [% s) S# Goutput mcasp_aclkr,
3 m! A% a/ ]3 y5 w4 j" woutput axr1,
+ y) u9 K6 D! W) e q9 n9 E assign mcasp_afsr = mcasp_afsx;
2 g; K W, v7 {9 [* a/ G% Eassign mcasp_aclkr = mcasp_aclkx;. q: P5 j1 d. @ { V6 c ?
assign mcasp_ahclkr = mcasp_ahclkx;
. x2 ~# R; t0 p& h3 O |! b' h7 vassign axr1 = axr0;
' k! Y5 k+ Y# f3 r
" Z' }/ k( N: z( E+ I' E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) \7 A: H/ a2 e: ]static void McASPI2SConfigure(void)* R) z+ p# ]( B, O
{% D6 F# Z) y. s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# w# h+ e$ ~. V* m2 x3 P) O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 _* v0 n# k& \! }% V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 v7 N- G2 m" b. `/ O9 N' b7 I# g3 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& ^+ _. j# _$ p" u% t! |% sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 |0 ?; ~7 z8 \; `4 G' t. j
MCASP_RX_MODE_DMA);6 M: w/ l) }. V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, l: a; p$ S' [& B8 j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 T% F) U2 R. DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- P( R0 U7 d, _* bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 c$ m! d v7 ?5 QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 a% r. j2 J2 m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ t& G5 X* L: ^' f% a0 ]* }) KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- t% Z l! E& Y5 P6 W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( R2 x! q, r" ]! ]# `" n( F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 i7 O2 Q# L3 S& J0x00, 0xFF); /* configure the clock for transmitter */
) s& u- h7 j7 Y" u3 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ M3 n$ M) B- u$ T: i; ?) SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * ?) z: k3 N* j4 M. ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ l) j$ [2 Z7 l, J
0x00, 0xFF);
) ?7 M- Z. N7 K# i( H* ` b4 G1 I9 c' f, c7 G# j) v
/* Enable synchronization of RX and TX sections */ ' p- c% ^/ {5 i2 W0 Y$ \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 \$ l( U! e+ T0 {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: Z' [. d7 Q$ x, Q" R" Y& p# D" E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: M) L/ {* K% Q
** Set the serializers, Currently only one serializer is set as
- o" m' s; e6 U: \. x$ e' ^" c0 w** transmitter and one serializer as receiver.' X8 K" Q0 r; v2 m: o1 s$ Q
*/
3 P! Q7 ^8 y) r# l/ nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( O- d& U7 ?& T8 d& r5 @9 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, D' i; S }1 L' V5 T. A
** Configure the McASP pins 0 D& C$ R- {/ u; f
** Input - Frame Sync, Clock and Serializer Rx
! H& l/ C. z- t* h) P Y/ d# X** Output - Serializer Tx is connected to the input of the codec
( t* {6 t- q( H( m, G*/. |1 A4 D7 B( w, u7 w- B' D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) L' C4 @6 J6 j4 }4 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 D x# W2 p; E) f( pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 Q0 j; ]0 p3 O( y# w' e| MCASP_PIN_ACLKX6 `" H8 l& S8 O2 O0 S
| MCASP_PIN_AHCLKX
. `% q% Q: [! o/ |' @ l& ?3 h- d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* {8 H$ {4 ]8 O+ L. U. V% g" ~& @8 J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 h# C& p1 K2 C o1 v% G8 C) e| MCASP_TX_CLKFAIL
8 W& n- V, G+ j% c6 l| MCASP_TX_SYNCERROR
' r& }7 n7 ~: P: i: c* e5 T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : e B0 G3 H, X1 ?
| MCASP_RX_CLKFAIL' V' L ^! ^; A9 Y6 m9 T
| MCASP_RX_SYNCERROR ' N& D4 t6 o! q7 C- R {
| MCASP_RX_OVERRUN);
( V$ b% C+ ^' W$ t} static void I2SDataTxRxActivate(void)
. l1 K' `/ G, {( ~- I+ E{
" A) g& O4 J9 m* E+ f3 @/* Start the clocks */
9 v! z0 L/ {' @# R% |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! k3 t* `( }9 K7 B* R4 k$ rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 [: K6 e7 r1 s' z* m& U' rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& D3 A/ {6 j1 P$ a# z6 ^EDMA3_TRIG_MODE_EVENT);; w% d1 f: e; b! c$ v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" t6 Q. y4 D( e0 g( b) fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 G; ]0 N1 Y8 W; ?2 C: m3 g ]) UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 r W( o% X6 N/ V2 p. l$ {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ e- _. U6 O. c$ M/ r3 P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 s" T. e, K i4 P9 U' ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, m, z9 _% l! O5 \# Q3 L6 ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 L% i. Y, Q4 N# w+ ]( ^! r} 7 }/ o' P$ x$ q; C/ d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
X- q3 m+ ?3 U, w B |