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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& [7 v0 }: |9 B, z7 Q6 S( S
input mcasp_ahclkx,
: D; s% b/ I9 u: G" x" K3 H! {input mcasp_aclkx,
$ W M, a& @, a( C/ [! ^; l8 Xinput axr0,6 D$ W, a( D; v, I" B* k. b8 R
) m# l+ F- M3 a5 Voutput mcasp_afsr,
! I( l) W$ S" S& [. youtput mcasp_ahclkr,
( c9 V5 S# ?# [/ O! r" _output mcasp_aclkr,
1 G1 L3 i& j' k. P6 y2 \output axr1,
3 [; r, K7 h3 {+ K assign mcasp_afsr = mcasp_afsx;0 M2 I0 ]6 f/ I# A- X/ q- ^+ G
assign mcasp_aclkr = mcasp_aclkx;
; h5 ^8 }- L1 j" X9 z& _assign mcasp_ahclkr = mcasp_ahclkx;; b& Y; a$ f" ?% O1 R# S
assign axr1 = axr0; 4 X* \5 `4 i( u
" ?. P, `0 Q! @& }: ^ l" y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: _7 H, T+ R nstatic void McASPI2SConfigure(void)
2 x. ~& v2 ^. c" _( X{
! l+ v, e' m* d: u) W9 x% h: r/ S$ XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' ]9 {, q, k& g, zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, n2 j( o. `, x( J! ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% s- k; ~# y" f+ H; ^$ a5 ]. r: ~( \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 o% p5 J! Z# U; L4 |+ e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ g) d7 J4 W* }) P3 |& n
MCASP_RX_MODE_DMA);5 A, Y# @6 ]. K* s( s- S# P+ a0 t; v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% P0 l2 N6 s1 c2 k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! I9 x5 }7 F5 ?4 {" QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 ^( O1 ^ M. }/ s9 _8 h4 E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 l' i. \# f# O) e. h. uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 z, _' s. j( G; {0 E7 o9 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( \! i+ Y/ F# T: s, _5 o* ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 f \6 Y- F% e( T9 Z) _/ _4 V5 CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: k4 R0 T# a5 \1 XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; x# T# |5 H/ h% _- |1 U
0x00, 0xFF); /* configure the clock for transmitter */
3 n, n4 {& b0 C- Q K6 H8 ]- QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 j7 k9 R: V! {) F, ?, UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ p3 U7 o* Z& ]& AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) d( ?2 K8 V, C7 q0x00, 0xFF);* J; |2 X: L6 Q/ _- r+ @) [7 k( C
7 n _4 N O& |9 K
/* Enable synchronization of RX and TX sections */ $ C: {) O8 E) X& z z, S8 N# q7 L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 R! Y3 d+ y* S5 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 w2 G# D3 c- Q* Q1 x4 O7 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 Q; l7 o. a: ~
** Set the serializers, Currently only one serializer is set as4 c! {" T: u( `5 T
** transmitter and one serializer as receiver.% j7 Q! k5 f: e
*/
3 q% `/ E7 ?4 z- i2 G1 @. iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! m% t A; o1 m7 l4 M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; u8 {, G' x d* t3 n
** Configure the McASP pins
& E% z- j2 h6 d' f. G) p% L** Input - Frame Sync, Clock and Serializer Rx: Y$ a" r6 {/ `$ h8 M
** Output - Serializer Tx is connected to the input of the codec
' }+ e. \9 Q( s1 x( K! o*/* [/ @) H) ?. s9 w/ ~- J- @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! O2 o" Q/ h) S4 r5 C" } {; C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 \ R" | O' |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; I+ e" w0 j4 `5 I
| MCASP_PIN_ACLKX: r# p; m* ^' p* I$ h
| MCASP_PIN_AHCLKX5 |9 [' o3 Z3 J1 {+ U. {- z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 Y, J" G5 j1 N& ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 I) C" Y5 @, e- e; w- p| MCASP_TX_CLKFAIL
" t: M, i7 H; ? j| MCASP_TX_SYNCERROR/ I5 N& V( d3 L3 x0 G# @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( Q" _( J# ?- G+ H: V7 c, x
| MCASP_RX_CLKFAIL
7 @+ @8 T0 D" {: s" {| MCASP_RX_SYNCERROR 5 ? A3 `$ ^: [4 B+ \2 h2 y
| MCASP_RX_OVERRUN);
; b; M! E* {7 r4 f} static void I2SDataTxRxActivate(void): E" P* w! q& O/ }1 s" f) H% k
{: i; g& `/ d# }& U( Q" |
/* Start the clocks */
+ l# G' G; w: ]3 ~: k3 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
V: j; ^/ ]$ p1 N! i( IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& ], m) C/ u) b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 e4 q0 M) [+ h- H3 xEDMA3_TRIG_MODE_EVENT);8 J, y, K1 {: U& f5 T l9 [* H! D* E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " M( d; E$ }8 ^. u: @- ^7 b# W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! W. |( m+ Y" e5 Z; J, P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& e6 n6 U6 m L+ cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! P) x G% q. M7 D" e: W- T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 | l l% e* i1 P$ OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 J: o% m* O fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# v: B- s$ h, c6 W3 K O}
0 ^; Q, ~& u( J6 Z$ ^. `/ U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* j l# u& v7 d, n |