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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 z, C9 X( T6 r9 Yinput mcasp_ahclkx,& E2 S/ u+ m2 W& {
input mcasp_aclkx,( O* u; f% p3 c5 \: e K# E
input axr0,
& i8 L( h9 C% A% Q) f2 _6 D! d6 q
. e% F& M6 x B- D! u# Z" @output mcasp_afsr," N& S' d1 w* k2 H
output mcasp_ahclkr,
5 n3 K, C- N; x5 q+ w6 L: houtput mcasp_aclkr,
5 m* z# v( A) \output axr1,& d( X0 `7 C% M5 `/ e$ ?
assign mcasp_afsr = mcasp_afsx;
3 p' ]6 B5 y/ P; U' d( kassign mcasp_aclkr = mcasp_aclkx;, X' {2 y& e& ^( z0 n
assign mcasp_ahclkr = mcasp_ahclkx;
6 h+ c- g3 a, |1 z. Cassign axr1 = axr0;
3 Y- s* I7 d# r* |9 c8 i" m8 s
# u8 ?: W9 ]4 f& d' _, G/ N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; F- G' T% g5 @% ~" Istatic void McASPI2SConfigure(void)
7 H# @* N3 @5 i# B) d8 ^' o6 G7 x% e{, V [3 \" u, b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! I/ I) e% |* |4 T$ C3 X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// Q9 B5 I% q* ~0 Y( H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% }! y) U0 w( D" U/ {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 h [& G" M P% o0 W d% P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* T+ }! j2 H- [
MCASP_RX_MODE_DMA);
0 A- v- D- l. v- g$ N' |% {* F' ]& yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 Z2 S8 S* P9 O& @6 h. j& z" ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; M: J M; [! L+ b& rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & H6 r! U4 e$ j: w6 J% b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& e! ]- ~7 I) H- {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 k$ U/ R6 n- x8 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& N# N |& K' L# K4 w& D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 X! x, G9 @% Z* ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' b9 \" O: j3 IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; }' c) y( _0 }7 E1 [
0x00, 0xFF); /* configure the clock for transmitter */
' V9 c- v$ U& s* U9 jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( P. b }: V* `$ mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % _! E( Q/ {' V% y1 F1 Y/ b2 x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# R! D8 E3 q) \5 ~+ n$ B
0x00, 0xFF);" e* M$ s, k S6 V" l% C) V( J
]4 r. C. c& R& g/* Enable synchronization of RX and TX sections */ 5 H4 Y& c8 R- O% x. K# n; N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 o; H1 q$ Y; mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: ?5 Z% y! S2 N2 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% R0 X3 F: ^6 w** Set the serializers, Currently only one serializer is set as f, y7 E* f9 A2 Z
** transmitter and one serializer as receiver.
( R! G% G# l7 Z I: }*/+ A( o6 q! Y9 S R V7 A# {" E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& \4 ]5 ~ X# R2 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 X8 E7 X2 |+ S$ H
** Configure the McASP pins
/ ~/ [$ a. f. g6 b `/ b** Input - Frame Sync, Clock and Serializer Rx
, z/ n: @9 y4 l. R/ Y8 ~$ R- t** Output - Serializer Tx is connected to the input of the codec
% H8 V% O; ~3 Q; I2 V*/
, q9 i( l$ j9 l9 L2 A$ i ~4 |& p/ R1 YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 |. G% I! V& V- h8 d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. v9 ?1 L, o% g, _% NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 Y5 |8 R+ S3 }( e| MCASP_PIN_ACLKX3 l* {# A+ \( X) z+ J8 ?
| MCASP_PIN_AHCLKX9 v* S, C, v) R e) g, s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 W* w4 ^% N! c! W& L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' O% ~% U% D% P1 W' s5 d
| MCASP_TX_CLKFAIL 0 @* v5 e0 Q0 W4 c
| MCASP_TX_SYNCERROR
Y" K+ S1 i% a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - _* h% L* A7 x( @/ H
| MCASP_RX_CLKFAIL
9 k- p2 G( f4 \+ ]3 L6 || MCASP_RX_SYNCERROR 7 ^0 ~; O" W% Z0 {8 H
| MCASP_RX_OVERRUN);6 z8 ] N; U9 k* y7 H
} static void I2SDataTxRxActivate(void)' G& G9 Z& S* N
{
3 F, E2 t" S* |4 S8 p4 D" S- m/* Start the clocks */
~7 A- ]3 a6 I1 p6 N, I4 u. B5 ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 z5 c4 k' G+ | y2 Y& p% [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! I" S0 S+ U& b* y, CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ R& ]6 b# h9 G/ [
EDMA3_TRIG_MODE_EVENT);( T5 ]* C- J: l; m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 I' \! H; c x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! d {5 Z7 N: f f, N$ i8 mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 p! b: b# _( }8 l3 f# fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( i0 u, \6 h9 t1 K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 A% \1 l5 f" O) ~* n/ W( h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: Q( _# T5 _( q! T8 z4 G3 j& ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 j& {/ w5 a2 q9 k* [4 z
}
" O6 j+ s% `; j& B* w5 U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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