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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( J% G/ i5 a* C$ W2 R. B+ u C
input mcasp_ahclkx,
+ e8 A$ N+ [* {) vinput mcasp_aclkx,
' _% d2 m$ r% h# y$ Iinput axr0,
# J- f5 I. Q9 B" x
3 j& f( G8 T) B# eoutput mcasp_afsr,4 Y. E6 Q3 j5 ^' M3 p2 w
output mcasp_ahclkr,
2 ?2 ~# Q9 S. {& a! s y) l# w" ~output mcasp_aclkr,+ M! a- c! e) o* m5 _
output axr1,
' T, T# T B }6 w: z assign mcasp_afsr = mcasp_afsx;2 Y) H8 t7 v3 k6 J3 V6 ^
assign mcasp_aclkr = mcasp_aclkx;( a1 |. s" x8 S, E) T. N
assign mcasp_ahclkr = mcasp_ahclkx;- p4 p; R$ ~1 d# {
assign axr1 = axr0; ' p" s8 P4 o0 I
' e; Z7 v7 ]8 L# l1 K) Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% n Z# o5 E! e. `8 }7 Xstatic void McASPI2SConfigure(void)
% X& y* ]6 F" u) J{
) `. }! W, N2 c- E+ gMcASPRxReset(SOC_MCASP_0_CTRL_REGS); A: k' F Y1 T8 k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 e' n, q2 P0 tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
?) u7 h) K# J( b% q* Q: G' h2 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! v( ?/ y* O8 @) ?$ I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 U6 N3 |' Y. t" S/ A; u
MCASP_RX_MODE_DMA);
( D9 x9 U* q- oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* R q6 i4 {' ~9 Y1 p* f8 O( J7 Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" {" D& {) i$ u1 t9 Y/ P- w- xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! F4 L# o6 v6 Y8 V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 K6 D! H, _- u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 s+ Y1 U. A. V5 J; R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 Z' L4 z7 J8 N4 c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ H" _0 e& F: Y. j: k c+ \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 ~6 J' i& ?8 M8 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- P, R+ r& n& s @* B0 A5 P# T+ h
0x00, 0xFF); /* configure the clock for transmitter */5 s3 T% v, o1 @( o: a/ f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 ]7 o7 a" X, i1 t# D' oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % s/ [6 G& U$ f+ ^ f* P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 ^8 v. ]" r1 c) m
0x00, 0xFF);% y. o' b, C& ?! m" h" A; r! N( S
4 X' o' @& }) O8 o& ^4 K/* Enable synchronization of RX and TX sections */ 7 L2 S4 q) J2 \, |) k- s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' S7 u# D d5 s3 K: j l: iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' i, N1 J- { m6 }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 Y# j5 W& R$ D: ?
** Set the serializers, Currently only one serializer is set as4 J4 e! ?, K3 i+ o; c
** transmitter and one serializer as receiver.
, a+ E- ]( B+ z$ v: j& p*/
$ m" c7 I, t" GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& e( I( u& y, ^9 ? c# C4 W! ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 s! a/ X; N- |( B2 { B** Configure the McASP pins
% {' [" @! g3 ~$ t `/ P4 H** Input - Frame Sync, Clock and Serializer Rx7 R. a- d+ i' ?7 @( S& H2 R- D
** Output - Serializer Tx is connected to the input of the codec
0 A. H' c6 \. D*/
- }& q( t+ [9 {+ t( {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! o: z% _( H' p- ~3 C. @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# P/ o6 D/ |' c/ m# k7 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 Z- H, |: f5 I8 q; K5 F" E+ W
| MCASP_PIN_ACLKX
4 ?1 t/ ^& ^$ W' K| MCASP_PIN_AHCLKX
. Y8 C- l- O D" w. `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) I1 Y3 r# S" m) k; ]; [2 y1 u$ p$ _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; w% U$ g& D) Z9 [; v9 d" F
| MCASP_TX_CLKFAIL
7 c Q5 X( p! M. Y, x( y& V4 u| MCASP_TX_SYNCERROR
) j5 q q8 D7 S6 J5 X2 ^& L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, R3 _( @. _( W" L6 M! c" @| MCASP_RX_CLKFAIL
0 P' o' C: g$ Q. k; M: E; @| MCASP_RX_SYNCERROR
4 @1 [- S \' Y3 H( @| MCASP_RX_OVERRUN);
9 K; F" p6 j4 K3 ^- A$ j+ T} static void I2SDataTxRxActivate(void), x! G& i& V9 Z2 E) a
{
+ ~$ z3 `9 `5 ^! z/ P u/* Start the clocks */
6 i$ k' `" Q6 b# QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 O/ L6 Q4 z( P& F$ [7 D2 dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* A6 p3 U7 x% N0 w6 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; D+ L5 X$ U/ a" J! r, S9 d! O: P
EDMA3_TRIG_MODE_EVENT);
1 F3 o/ i G' F5 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; q. T6 t z" f' OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* X& L' U* Y9 L- b9 kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); k* G, L/ j% D5 \4 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ _% W: P9 p) L. f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 {) M& R4 l( y1 v# C% k" E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 ]% J+ z" A' w# @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 V& W) b6 N9 Q4 | I0 L& x
} ( D0 C) T& k/ `# E7 x$ A8 b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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