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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- k* `8 U+ ]& ]; j& X0 oinput mcasp_ahclkx,
$ e; P' C! |# p- G% oinput mcasp_aclkx,
# X, f( @( F* u; F" l& ^" c7 dinput axr0,/ @) a7 |3 B4 \/ n( a$ P3 V
) k) ~2 |0 K9 v5 O0 u) z1 N
output mcasp_afsr,! L0 ^6 |1 U+ C: Q8 \/ F6 M1 A. ?
output mcasp_ahclkr,- T, I9 Y1 l0 U" D! I
output mcasp_aclkr,) a; _, U" @7 L( @+ s, E3 x" q
output axr1,
, F _$ N& W! u9 |3 q7 H assign mcasp_afsr = mcasp_afsx;
5 l5 }8 |) n$ P6 W2 K/ A5 vassign mcasp_aclkr = mcasp_aclkx;
+ b4 T( r ?' e' I6 j& l7 l2 Xassign mcasp_ahclkr = mcasp_ahclkx;
, f5 n$ ?1 Y1 K E3 nassign axr1 = axr0; . o# U/ y2 ?. n3 `
( Q6 H' s8 W( E& K) D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ b1 ]& o V q$ U0 ]. kstatic void McASPI2SConfigure(void)
% C( D3 V! y) \) R0 k{
% `& }# V4 M$ {0 R; nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; w6 L y3 ^/ E8 k: x+ qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. R9 [! U% f8 I) s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. `% V& A/ A2 `4 B4 T, }; Z {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 `$ a# W3 A# x# s1 AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ X1 m5 }" X1 f) U
MCASP_RX_MODE_DMA);
+ C) _/ m2 j2 IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 K: @9 a2 }( X; j5 ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 ~1 ^+ D) F- Q J+ f+ F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 B, P) \. O% S4 Y& |( ?3 V6 `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- b5 {1 n; a# Y' [8 l5 ?5 h6 q- {, |2 iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: I7 U/ |2 ?' n' M- `; T. l+ \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& O3 i: ~8 V; k$ IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* J+ I) {: B' }0 jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# }/ O! ?# t# h" T% w: }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 {2 n( N$ S8 q7 {8 P
0x00, 0xFF); /* configure the clock for transmitter */
0 \. V B, F, d* Z2 BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 Z/ @7 Y+ |: f( P* ?/ C4 q5 xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 k5 j( l, r6 K$ }9 o/ D! C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, w8 r& `$ H+ m: W! _2 c9 C0x00, 0xFF);1 H' S% g' @& F, F- z
5 P; m( X) X' v( c6 z1 E& ]
/* Enable synchronization of RX and TX sections */
: K) s7 N }4 G5 G% ~2 h/ rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
m! R6 d% Q" T+ p- ]: Y1 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' t1 x+ q0 z+ V5 n4 G+ tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 c1 y& u0 G+ _* G
** Set the serializers, Currently only one serializer is set as4 L) a# U3 g) C
** transmitter and one serializer as receiver.; {; r! r' H! l, s3 a
*/
) n7 p) n3 S4 o" n# HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* w0 j) Q9 @3 z. ]$ r, i$ DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, ^" J$ x& r( m. y3 q" ^** Configure the McASP pins ( M. c3 e! [. w' f
** Input - Frame Sync, Clock and Serializer Rx c7 Z& q" c6 O) [2 h& A* F9 E$ R( D
** Output - Serializer Tx is connected to the input of the codec ' k a; X- h0 y% ]
*/4 B4 E0 F: M0 U: N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 _; k$ r$ F7 ~/ O! t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- V! ~- Q5 t" {% p% V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, o2 }+ w# F. b6 K; n| MCASP_PIN_ACLKX5 X4 i0 p, d9 X4 o; s
| MCASP_PIN_AHCLKX
- Y9 l3 l* T9 ]0 _" m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( B# x7 t2 o1 F8 A$ GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& ]! w) i8 w0 [- g" D, b| MCASP_TX_CLKFAIL
; W/ `' F2 b. f, H9 g$ G0 n8 C| MCASP_TX_SYNCERROR p! y% b0 |/ w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) N+ E; u8 H* d# E4 \, y( W
| MCASP_RX_CLKFAIL
6 w6 f9 x! o; f! i, O* t2 g8 e| MCASP_RX_SYNCERROR
4 G9 T9 N0 P$ m% g2 F1 K# m| MCASP_RX_OVERRUN);
9 L" _; U7 S4 F; X' I! m( r} static void I2SDataTxRxActivate(void)
& v, @9 n/ i+ T" Y{
5 l' z$ p$ V4 D u/* Start the clocks */: E* Q& H7 \- A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ R0 @9 n. ~0 q+ K, ?) f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) f: i6 f* K& h8 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& \! Y; X9 l$ E% z q
EDMA3_TRIG_MODE_EVENT);4 g) {3 G1 d% S2 w# K$ o4 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! S# v% V) J9 @* H5 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 L, K, N6 _: w3 F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ P3 p" M8 A5 A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% I& i# c0 a/ w1 P4 r [3 ^3 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# {& C! \' _6 \0 N7 o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* n! Y0 |, h! M: Q# z+ F8 ?0 o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* `" V# c- I6 d! Y) p6 [1 L f' {' h
} ( M& b/ \* f5 n+ G; E7 J/ l0 g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 x9 i k0 ?- e0 k: _
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