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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 I1 n; i5 m- Z. n# R/ R3 linput mcasp_ahclkx," Y i! _; P- ?$ v
input mcasp_aclkx,% O8 Z; X7 T) ^* W0 f \0 l5 n8 V* d
input axr0," B1 g* Z( e4 o7 i
; c. ] E" y' T9 s1 f$ z1 doutput mcasp_afsr,
, {- w: W D1 I' K w1 C: b7 b3 E' joutput mcasp_ahclkr,
+ _ j$ I3 |3 Y+ m2 @4 u; koutput mcasp_aclkr,) q/ R, ~$ k8 W$ \( R" u x4 q
output axr1,
6 v: y' r$ f) E7 I! C% t$ f6 I+ O0 I assign mcasp_afsr = mcasp_afsx;
" W* N0 A0 a1 r! x5 F, _) iassign mcasp_aclkr = mcasp_aclkx;
" Q; N0 ~' E7 j" {5 G4 oassign mcasp_ahclkr = mcasp_ahclkx;
! |( f6 U5 v( D2 i! ~' W2 E, c$ Dassign axr1 = axr0; 0 w% P2 X/ @6 \: Y3 o' M
' r. l! \4 N, J5 m! p0 K m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
@ r& b- M, Q: {static void McASPI2SConfigure(void)' g- c+ t9 z1 x; [# M' q; ]" Z4 U
{
: h( h' s9 r% E/ o& aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! ~, M% z) y$ y1 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; L7 T& x$ ^9 M) h: P; f4 k$ h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ N5 l$ S9 q( TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% _* L' |7 d0 M0 FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; w0 g9 g6 N6 z) N) G8 i* mMCASP_RX_MODE_DMA);
2 Q' U& M7 S7 D z/ C4 ]+ n& QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% j5 M# W) E5 }! C/ x% `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! n% w: d. M# f9 \5 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & G# ]5 i# H Y: ` e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. w3 V# r3 X, W4 \+ f& K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 w$ A8 [& h( pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& ?5 a! M/ Q6 E U) m1 r3 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 f+ D, |/ D+ V! z5 L* u+ SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ Z5 G W2 @& t2 P5 b. ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, E8 g* z& O" d) z. B
0x00, 0xFF); /* configure the clock for transmitter */
1 l. X1 ?" ]; \7 @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 j( j0 [( O1 F4 a5 B" ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( R0 ]* t3 a9 C. H. ~3 m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! W" D; s1 A5 ]0 c
0x00, 0xFF);
; p0 t3 M7 @& D# [5 \+ c8 i9 Q% p
1 ]: a& g/ @' m# K& X( f% G% g. s) S, n/* Enable synchronization of RX and TX sections */ * A8 u2 P) l: o/ b9 z; O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' R8 o8 r5 d8 o' I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* `0 Z _; R. j, XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ S* P) {! e! I: ^) F* V( n5 Q( X9 ^** Set the serializers, Currently only one serializer is set as" t0 i7 q- `& Z& h5 r1 N9 v9 ~7 F
** transmitter and one serializer as receiver.
- }6 [5 _1 G' E- L6 d0 w*/% g" h4 z' ~ N( s0 ]. Z- a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: d; Y3 ^) K# e: [' O! V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 K- E- M7 }3 D9 M0 \4 Z** Configure the McASP pins & p0 ]3 w* [" j. i0 n e7 P, h, I
** Input - Frame Sync, Clock and Serializer Rx
# T% G* I5 J1 A$ B0 d** Output - Serializer Tx is connected to the input of the codec
_ d. Q; K% B*/
& X# O0 @2 ?+ s& r& i0 V3 BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ N$ m6 J% _( E& ^" r) |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ y/ W2 A0 C. y; s/ Z8 \% {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX d4 \& i+ I1 F# m$ |
| MCASP_PIN_ACLKX
1 d9 L( |5 s D y* `| MCASP_PIN_AHCLKX
: I/ M, Q! v/ u+ q$ a' x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ B3 n: N1 H& m, ~1 ^. h8 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' i- C" M ~' H9 }3 M% u| MCASP_TX_CLKFAIL
% M K4 u, L* S8 C| MCASP_TX_SYNCERROR; e! s, K5 Y* x% j% Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! g6 r" H/ O8 Z1 u9 L| MCASP_RX_CLKFAIL
" h7 [! x% t v3 {| MCASP_RX_SYNCERROR 7 f4 Z2 y( V; B$ k) J7 L% W# N- ^
| MCASP_RX_OVERRUN);2 x/ x. ~. ]9 `: @ V0 v
} static void I2SDataTxRxActivate(void)
) \6 b6 \5 e4 n+ Z{6 @! r) P9 N' b6 r/ {
/* Start the clocks *// c) S8 c8 _! p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, B0 P1 {% n Z; ^% b* w1 U/ N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 E8 b0 m, K4 Y. ~5 U# R1 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( I1 y& _1 j% e+ [8 sEDMA3_TRIG_MODE_EVENT);
% N4 D% G- ~8 W3 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ C2 V* R. ]) BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; R) s8 n8 S- I: r* ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 U) o% x8 P- v' G- ]; g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 O7 {3 H' E, p- ]2 n0 X% pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' s- S& w; D7 K5 n( l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; a$ S2 u0 M$ a* w. [8 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: H% R) g( h# v* M}
5 \# e7 |8 `% i* H* N4 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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