|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( _8 g, g$ ^; j% r+ v7 U# K2 \input mcasp_ahclkx,. t) I* U6 f, u1 e: N: q8 Z
input mcasp_aclkx,; P5 \! R0 \9 Q" N
input axr0,5 D+ g f! Z; d" V
2 Q' c* \) s5 P2 N3 n f0 G
output mcasp_afsr,4 s7 i* l Y4 T6 H3 C R
output mcasp_ahclkr,
+ a0 f3 Q& p& C' l% y7 G0 Voutput mcasp_aclkr,! S: M! H, g6 e8 F [; ?
output axr1,
: A& P) _" [$ | assign mcasp_afsr = mcasp_afsx;9 A* V( G {4 k3 L3 o
assign mcasp_aclkr = mcasp_aclkx;. ?4 s: L0 t* ]7 O/ s% v
assign mcasp_ahclkr = mcasp_ahclkx;
7 [ f j; n9 ^1 t4 l O6 sassign axr1 = axr0; 3 W9 m, G/ _" y& L Z' y0 C A$ { s
( g" d% j0 i# N4 _8 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! f% W9 J' L: f# S! o& mstatic void McASPI2SConfigure(void)
; w7 r8 ~ G3 S7 S{1 ^' x5 o& X: M! U0 r
McASPRxReset(SOC_MCASP_0_CTRL_REGS); @4 p8 Z; l+ R- h6 w4 h& \0 ~$ p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( P# Q$ y* Q2 W4 r9 Q! d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 ? k4 F/ T5 Z+ B) d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! Y: [$ q1 j7 n9 J$ p& q% ]' j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 w3 f8 ?5 w5 v3 l# o6 j _$ m
MCASP_RX_MODE_DMA);
3 I% t$ }, ?: q- D' n3 f) s7 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
A' e5 d0 U* XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 E7 o, z* y5 m8 r! N _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) l5 f/ Q* s! M- ^# T! IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. z$ q4 d: x" X+ iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ e5 ^' ?7 f' @( G- zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 B, v: [5 H0 E9 y' g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ `- x% ?" q) P$ \: bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & Z8 B" K3 [/ `4 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 Q) S2 {8 [; u* p' m v0x00, 0xFF); /* configure the clock for transmitter */
+ c& M* [& n& {- J# F$ X2 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% w( R$ b, X, m) e* n& QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) H3 F: [8 _1 ?7 c. ]+ G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 l* Z* b" D+ p0x00, 0xFF);
9 L" @# m; [/ d+ {1 g$ V3 ]' s; Z& V( Y! z. o- Y" z- Q% B& G
/* Enable synchronization of RX and TX sections */
; p0 c8 F, b! K$ OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: x% X4 Q% A6 b; p8 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 }& d5 _* ]& `$ m1 d! pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. R% g% y7 }: d** Set the serializers, Currently only one serializer is set as
- e# V. H+ ^3 g9 Q9 D' k5 o" }; j** transmitter and one serializer as receiver., i; ~5 _4 q# N+ { \( p3 g, }
*/& }0 ~, I' q9 |% b" p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' ]! `! k1 i( l8 y$ I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 G d7 @% A+ \& d" a** Configure the McASP pins
; \1 k) T' y: B' X v** Input - Frame Sync, Clock and Serializer Rx* _; a: s; V2 g% F, m
** Output - Serializer Tx is connected to the input of the codec . E5 s( o! a2 q
*/
) S8 k9 k3 }7 P$ A. U' bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" M" ?, ~6 `9 ?; p. K. I' s) C. |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. i( O' v$ E& g/ v% DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ [4 K! z0 `6 U! v# T0 d0 b3 C' ~
| MCASP_PIN_ACLKX
0 E- x" b# f$ M' J2 V! m" b| MCASP_PIN_AHCLKX! \" U& ?, F7 X8 ^3 y- `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! b- @7 J+ J! ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - l) I5 ?. H" o( O; s0 {9 J, \3 Y
| MCASP_TX_CLKFAIL d/ s( a, h$ d/ V( G
| MCASP_TX_SYNCERROR
7 \8 ~. d0 ^" Z1 }9 h5 i/ b. @( y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 c9 i# w" E4 S" ~1 k% m# L| MCASP_RX_CLKFAIL, P! n( x2 x9 [$ B) Q6 D
| MCASP_RX_SYNCERROR 6 @2 ]9 N0 W4 O, a; p% p2 A0 c$ J
| MCASP_RX_OVERRUN);
$ _# b; b Z, T7 a0 w+ T! d4 Z! J4 A} static void I2SDataTxRxActivate(void)& Y' u9 I7 {' v7 G( b
{
/ u# z0 H b2 n/* Start the clocks */
, n0 q0 y8 g$ ]5 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: ^; I5 O% ~8 r# x, ]. U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) }" y7 b$ a0 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ ?1 k2 b& y9 b
EDMA3_TRIG_MODE_EVENT);9 P+ Q" E0 i E, o7 R B3 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* h) O$ {- j5 h; j0 y- N' CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. H8 M3 P3 K8 g# @* p4 x7 l. J$ _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* A7 G. K) J0 N xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* x8 U. ^5 X- {( p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 x( W- {3 [8 h Y) LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 _0 x4 U& Q3 V0 T( \6 v. a& f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) T1 c& H4 T' V8 k9 G% H) s: D} 8 {. T. Z9 R/ w+ G( f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
4 @1 C' v5 D' S; Y1 t0 K. @+ w |