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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: ^' F8 [# T2 }
input mcasp_ahclkx,: ^: B% t) S @' y
input mcasp_aclkx,
8 s% j c' S4 ]' p) ~& winput axr0,) V# b2 T) c3 j. }4 s
3 P3 c- X; Q. k- @4 v
output mcasp_afsr,& l/ A: u0 X+ D& r5 | M' a
output mcasp_ahclkr,
9 |1 L8 H! E$ g% R5 loutput mcasp_aclkr,, F! u9 h9 _ I! K- b3 p+ Q
output axr1,0 W+ Z2 D# R( K& ~
assign mcasp_afsr = mcasp_afsx;0 C4 X2 Q% |: @) h _
assign mcasp_aclkr = mcasp_aclkx;: f3 `0 l H; h5 H8 s# l9 s
assign mcasp_ahclkr = mcasp_ahclkx;
2 i0 k$ C9 {- T+ lassign axr1 = axr0; ' ^4 G( @9 G, D0 Q H* Y& @
+ Q0 ^% x9 k- d3 M2 y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- S: `# Y! ?& F- I; T' b3 U& n! Kstatic void McASPI2SConfigure(void)) H7 |) Y& k5 `, E' Q7 H* r" U
{2 ^6 Q8 S8 k# d) ~ p" ~' l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& C9 R( d* Q1 t8 T% e1 y% }/ XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) u5 t. v& f. L5 o! x. XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* \) \0 ~1 T4 L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ z- r3 q* [8 M% N* l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 ?6 D0 `- ]# X9 \% v) p9 Y/ n6 I
MCASP_RX_MODE_DMA);6 g8 b% m+ Y. R- C7 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," }, l3 v4 N$ Q/ Z5 T( D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* N! ^/ t% D( n- [3 q5 }1 yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; B2 H8 z3 M5 `/ _# q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 h1 {5 k8 p* f( |9 TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 j S8 a& j" `! J$ \# o/ U' P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: c$ a8 n; x, j% X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 p, ~; d6 R; u$ b" FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % m/ J2 S' e7 ^/ @0 ?3 K2 p Y6 L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# p' I6 l+ t E& n; o9 g0x00, 0xFF); /* configure the clock for transmitter */
; D' z) U, x0 p7 S/ o- L: KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) M1 y8 O* @ f1 HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + f( v6 j% O) s1 p+ a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; f7 g" O! ], {' C/ d
0x00, 0xFF);4 t* l( s2 t# |- P' ~
# F' P5 R2 N5 y- O8 L/* Enable synchronization of RX and TX sections */
) n5 D7 }9 f& mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# u8 X, j: j" u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 y/ S6 v4 }, s6 L# `( C: l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 J! q. c. L+ Y" |9 H* D( a
** Set the serializers, Currently only one serializer is set as
: t: s3 u- I. H |. s** transmitter and one serializer as receiver.9 G# r0 ~. j7 c$ ?
*/
. _' r2 X8 l% {! o+ WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; [* y$ E0 ]2 x$ c) k3 {8 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 h% A8 `# _: q% @% R** Configure the McASP pins ' ~# J1 p) T! |7 K
** Input - Frame Sync, Clock and Serializer Rx& x; X7 P% a Z$ B& H2 [9 n$ _
** Output - Serializer Tx is connected to the input of the codec
7 O' U7 z! B8 v" d3 s*/7 i+ U9 p* n2 o8 U3 t, V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- {. J& R' u# ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ t0 j! X! Z( W' [; \$ rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 k# s( R/ ~( U3 p
| MCASP_PIN_ACLKX
1 Z C2 l! h2 X. M; i1 `- B| MCASP_PIN_AHCLKX
3 p# @. I1 d3 H1 C! G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: @1 F7 \4 q- e/ E. B, e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 T. U4 [/ v d: t- _+ L
| MCASP_TX_CLKFAIL ; n4 J1 ~' ?7 U$ b: Q: q% e
| MCASP_TX_SYNCERROR3 u1 g$ @6 n X% C# f% E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 L) W2 N9 }/ u+ \/ @! C# y| MCASP_RX_CLKFAIL
7 `! W/ S2 Y( {- k| MCASP_RX_SYNCERROR - O0 N! A: M2 a% C$ e1 M' y
| MCASP_RX_OVERRUN);
( Q* y" d. n% Q: j4 Y} static void I2SDataTxRxActivate(void)
4 Z9 k" n% ]: F+ g* \: m{
) L7 Z+ \ g+ p/* Start the clocks */4 {) W' C$ G3 b& \5 j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ F+ G j" _& p3 T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. }; J5 Z& k/ y# b hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' s+ b# p5 M* BEDMA3_TRIG_MODE_EVENT);
0 w( {% b# o6 C6 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 j# I4 Z8 V' u0 Q: mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! Y4 R6 r' }4 s3 }2 Q d; }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 }6 m6 w9 z# G/ b5 |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# Y% p3 U F: [, N4 m# P4 ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ \; |/ h" D9 `+ n0 i6 {2 Y' H, WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- H$ o" J G2 t- V9 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% h- h* T& o( U( `
}
0 R# h4 l6 h! D0 H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 T+ F6 d$ J9 Y+ s
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