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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: j- @5 \2 _% Y0 |6 H- Einput mcasp_ahclkx,' T3 w7 ^: R' [2 f8 R/ t
input mcasp_aclkx,2 j+ ?) B; W9 _, d. ~: I
input axr0,$ ?4 e2 ], |' b9 G* W1 N8 Y
' D: T* }# p( |# s8 C
output mcasp_afsr,
' o% U/ C0 x: k; b5 e* C Routput mcasp_ahclkr,0 m9 C$ j5 A3 Z# B; D3 N
output mcasp_aclkr,
) w' R: d8 E- n3 a% u2 Boutput axr1,
) {7 y6 C& O9 P. b7 F4 V: T: Q assign mcasp_afsr = mcasp_afsx;
" ?- P1 ~' L6 G s) E! e, ~1 x; sassign mcasp_aclkr = mcasp_aclkx;
2 k" y: A5 \3 t# }5 ^assign mcasp_ahclkr = mcasp_ahclkx;% m- w. ~' J( e! K% x
assign axr1 = axr0; * @% R0 p% l% i; G, b9 \3 o' x
$ b( X$ b4 m3 x0 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; M' j; S2 S( i2 L5 D8 B
static void McASPI2SConfigure(void)
' a+ K: ~( P ^0 \2 q{
: d* P7 c( p4 eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, q+ M' g6 `; TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ L% u( H# _! l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% A. y- d: _1 i8 s* p3 G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: j' L: a; c7 t; L, J* C. ~6 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ Y- M/ x. z# H2 `& X
MCASP_RX_MODE_DMA);2 {' ?2 S4 x2 W* ^5 d% n) s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 f2 Q! C- K7 J6 BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. j, b, T: i* a( ?( EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # k' U# `% S1 @3 U9 C, p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 D; H) S4 ^% eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " c5 Z. ^6 o, g; Z! A( Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( f8 v7 C! i, k! IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% T& g0 A6 q1 C! ]) {4 x. IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: O! s( n p$ s1 O8 \$ T: BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' d' w7 `/ U% _$ c5 E1 A: B$ j0x00, 0xFF); /* configure the clock for transmitter */
( J4 r* N4 Q- ~8 I" ~) vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 `' [) P( e8 `, O! A+ C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 K8 Z# y7 u% kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( U5 G+ D% j) w0 R# |" A0x00, 0xFF);3 ~/ A3 D( k8 }4 f+ `
8 H- f- T0 l( l
/* Enable synchronization of RX and TX sections */
3 d! P& s: V! |, o2 V2 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, ?( d; y( M9 h" R% v. sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' p) W: `, u0 d, ~9 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" A) g7 l+ u& _% z1 q5 i
** Set the serializers, Currently only one serializer is set as
4 e: ^+ f1 e, r" s2 f$ z V** transmitter and one serializer as receiver.7 N$ m( |, p. k$ ]- ^( I$ y
*/
9 V6 ]. ~* _- M, Z* K" YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 l4 r" Q4 l: E3 }9 J0 DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* t, V/ N" D1 m1 u** Configure the McASP pins 8 F$ E: ]) J' @+ d# k
** Input - Frame Sync, Clock and Serializer Rx6 l" _: |- @3 j& I: L
** Output - Serializer Tx is connected to the input of the codec
/ @( `5 g( J$ l6 n*/
! q) c' O8 P/ U; m+ zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- h' {3 t* i8 w" U9 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 u# [# d( A/ D3 y! f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" `$ Q: @) |5 ?
| MCASP_PIN_ACLKX' b# ^9 T/ e+ G( p0 A3 w+ m
| MCASP_PIN_AHCLKX) B9 w, O% J3 h$ D0 A' V9 @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 \+ |8 j, @4 U6 q n) T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 E% W" [) g1 S* s% d1 }6 X
| MCASP_TX_CLKFAIL
& h$ K: h! h" {* b* a8 w$ D. K| MCASP_TX_SYNCERROR" X n/ W2 G7 k+ N3 D1 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) l9 U( r, c8 d0 b3 _
| MCASP_RX_CLKFAIL
% j2 t0 H" s9 F: L5 a2 e8 w| MCASP_RX_SYNCERROR ( k7 |, K2 @( b1 \5 r
| MCASP_RX_OVERRUN);# s U$ X8 U7 \: I9 W8 S' G
} static void I2SDataTxRxActivate(void)
0 X* X2 t+ b- C. X; {( J3 s{
2 B1 T5 G; C$ c/* Start the clocks */
+ Z' ]3 P) z( a. V4 wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) e3 w: l4 P. b+ a' W) \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 ^) X& i* [( L6 z/ ?! `: hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 C( g7 d# @: ?) eEDMA3_TRIG_MODE_EVENT); g) e0 J3 t$ G3 |+ Z7 O0 F. M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 y4 E! G. S; I8 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. S8 r9 I1 z- C) p# ]8 q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: l. d1 ?, }4 H/ wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! R) I6 Q @9 w) [5 e* R: I! I/ jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# v7 i' O: _* S; Y1 w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 y2 z% o" I2 O& VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 c9 V# `: g* j% h) o/ N0 p9 {! p5 V
}
; g% X- q! T; s* c# o# H1 v! t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
9 i( K5 z6 F: e. q! [7 W+ h* ^( @ |