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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) G4 Y, w! d9 ^input mcasp_ahclkx,6 [" l e( L$ W6 ]. x' b
input mcasp_aclkx,
$ { h1 V4 R. y7 n y- Minput axr0,3 T4 x5 t0 T! n9 ~
8 K1 Q, |3 p( x/ l/ s' @output mcasp_afsr,- S$ p# k1 Y/ s7 ?6 z
output mcasp_ahclkr,
H4 k0 d- u/ A. x7 l1 f* voutput mcasp_aclkr,3 C/ U- J3 S4 B' [& H
output axr1,1 N' l' t3 A8 k2 E$ a
assign mcasp_afsr = mcasp_afsx;
9 l: k0 L+ p- E3 kassign mcasp_aclkr = mcasp_aclkx;9 l: A) I' K, M( v+ k- v9 B2 i. K5 g
assign mcasp_ahclkr = mcasp_ahclkx;- W6 @% U$ h9 ]# x. h* v
assign axr1 = axr0;
0 U' b5 T8 U/ s: Q6 m
) _5 ~) ^2 `. Z- V0 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; J* ?3 d* B2 Astatic void McASPI2SConfigure(void)8 @" v' S5 v" ~) j5 U
{
& P6 A9 V! A& B8 SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
t# }/ i' x. X8 d dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 o5 Q& i( A( G( ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 G6 R1 o5 K, \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: U$ c1 _! r) O. j6 j# QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& D2 P$ W/ A u0 V4 @5 V
MCASP_RX_MODE_DMA);) @- q# ?; J; e0 ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( u/ A% q; N* v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 M. C( h8 a3 k# P) T# R0 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ Q' B; j: I" pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, k/ G" s0 p* n9 n7 v+ D: W7 I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & d# E4 f) W9 q7 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 E' {. }2 {/ e& I6 x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% s5 o) B! V) G! P. v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / [3 p3 Q* X ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 e% y. H8 _, V, Z V4 a* t
0x00, 0xFF); /* configure the clock for transmitter */ q1 Y1 V. k- a4 x- ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) x! b }, N0 M: K+ ?) g0 aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 l/ ~) c9 c% `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ ?% \! j; P& T" L$ m4 \0x00, 0xFF);
! O1 g" m: u' n0 E; @: c0 r6 L$ x4 t4 M0 k: O4 g8 \
/* Enable synchronization of RX and TX sections */
5 _* U1 T) `$ T, iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 c+ T/ L7 M( K# k' j$ }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 u3 y( |+ n: n ^: |# Q6 w: [; i' W# bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 \5 k4 x2 x% n, X' q; Q
** Set the serializers, Currently only one serializer is set as
" Y3 _. ^6 O2 [8 o! e; A3 v$ y! v** transmitter and one serializer as receiver.
8 p" S: G8 Z) [; a4 b0 M*/
( Y. F. |- v6 B" P! g0 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, C. J( R6 A/ O! j% rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 ^- T5 C. e p6 z U** Configure the McASP pins 9 n! p- o, C6 j
** Input - Frame Sync, Clock and Serializer Rx% g: ]* |) p' ? v5 e" ?' [
** Output - Serializer Tx is connected to the input of the codec
* s3 c% W2 q' z) \+ |: g*/- E, ^5 Z" ]; W3 S/ e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( m3 k; b+ C" q, c2 E7 X7 B2 DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 C2 C) }* ?% b* g, y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ i3 A; u, u. R) m| MCASP_PIN_ACLKX" M0 g/ _( } M
| MCASP_PIN_AHCLKX
1 B- u3 g: P* Z0 k0 \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. `, A9 x( D2 D( W5 f% jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . q+ K$ S5 U; B% A( ~ B
| MCASP_TX_CLKFAIL 0 Y' V; B" i6 R2 m) a& V6 @6 @
| MCASP_TX_SYNCERROR
( v+ e1 r6 H/ k1 G E6 e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 h5 j3 T6 K7 L* v; T: R' E8 e| MCASP_RX_CLKFAIL
& H/ P) l3 O3 m, p) P| MCASP_RX_SYNCERROR
9 w! J6 J1 X4 I6 F, z| MCASP_RX_OVERRUN);
* I( t. E$ b: Y& X4 r$ K} static void I2SDataTxRxActivate(void)$ L3 `" R2 i4 g9 H
{7 K5 t. B; [" U0 |/ Z9 z
/* Start the clocks */
& \6 T8 L( p% KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# P. M6 b4 s' ]1 f1 W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, n& U, u# Y& @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 B1 w" l) _8 F! B7 ~; S, mEDMA3_TRIG_MODE_EVENT);
0 `! v% {6 M2 ]8 p- mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * c8 ~5 K' ]* l9 ^& ]4 |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! p7 g J i2 K, t2 d A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. T- `8 u# z, p) R& ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; C" F' q. }; O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// s; o! T3 Z" H) F1 B) C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( l- n8 t$ J2 f @; m) B+ f. u. }. iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 i9 J1 b" l }
} & x9 p2 m/ L: r3 r& \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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