|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" t Y% k" B9 Q$ iinput mcasp_ahclkx,
, x$ k* A( B; Y( y* L7 Rinput mcasp_aclkx,, b3 Z4 @0 y5 T3 f2 [8 Z! j* N. E
input axr0,
; {3 E* t' j# J1 t+ h8 {
6 z. R' E4 g0 m1 O; {; Goutput mcasp_afsr,; |& B! ]$ x2 M- n# @
output mcasp_ahclkr,- t/ X/ p0 P/ ^4 i' H
output mcasp_aclkr,
/ {2 {. k8 ^ z* poutput axr1," ] O. u _# Y# S v& L: c0 [/ P# Z
assign mcasp_afsr = mcasp_afsx;, g5 o" R; H% \
assign mcasp_aclkr = mcasp_aclkx;
2 @9 f7 Z0 E# o( F" q& S' Iassign mcasp_ahclkr = mcasp_ahclkx;; R0 d0 b1 \7 | W) x: ?
assign axr1 = axr0;
4 P2 d) K6 F8 ~6 W: o
, ` a5 k# Y$ }) l8 q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 f k A* F# \
static void McASPI2SConfigure(void)6 [- k. I$ G' \% s0 z7 I
{
0 f! I$ k0 j) G& J0 X5 ]3 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 S2 N" R4 t/ M& C' b0 _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// U& h) {- _5 K) U V- l/ f4 Z/ c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; v7 M% \8 L( n- z& ^4 u5 TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( V1 ]5 B2 @; ]6 ~" a. u. WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' k i, U4 S# w, ] v+ V+ z' K7 i) [MCASP_RX_MODE_DMA);
1 P# U% }( n4 C3 {" X7 X$ ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 ]8 y% |- @% [" X. X3 }, TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ i N. F0 _/ O' ~, s4 ]' _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * W& A9 C8 M2 e& |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& }/ j+ k; Q6 L* a2 _$ e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! G& Y- v! w5 R S# E7 V: q: p. O6 aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 `7 h6 {4 a8 a. t3 W/ qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! ]4 @7 L) ]! [* ~9 H" {3 ^( jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 a7 A0 _* U) M- T/ v0 U; u% n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 C- c, ^7 Z9 I% R7 o0x00, 0xFF); /* configure the clock for transmitter */
5 K* d$ T& X, H0 _+ T* aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 j- N7 X# b' V" S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ X, P: h7 k h! w: r; a8 X2 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 u a% h) I* n. b0x00, 0xFF);& r. K6 k" a# O ~% N# W' v
, {2 Z4 z" R; W( f0 S) m* d' c6 U/* Enable synchronization of RX and TX sections */ - r1 y, I3 y, ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 f6 u- o0 E3 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 e9 j! h2 a8 _9 x" G* H @$ vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 m2 F( w& q) A2 A5 g" u: Y** Set the serializers, Currently only one serializer is set as! J) [& E) a# l% }2 }: w6 O
** transmitter and one serializer as receiver.
3 P, X5 J9 Q. r. Q3 l( r*/
- s: {& i$ x9 LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ U/ q$ ]6 @1 {: tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 E- P! ^. q# C$ C# K5 e# L" e
** Configure the McASP pins - w9 @* c/ H% B& R" k& b1 B
** Input - Frame Sync, Clock and Serializer Rx3 k( q8 B! k8 S8 \
** Output - Serializer Tx is connected to the input of the codec / }* x. P0 K8 M- E2 G$ |$ R0 {
*/
9 H; {6 ^! n% V& x, x6 b, O# `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 e2 b3 o( I2 T3 R) t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ _; S& `: Z9 T. OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX o; {8 ~% a4 C$ q& ^4 g9 q/ p
| MCASP_PIN_ACLKX
" I* K# P4 C! M| MCASP_PIN_AHCLKX( s M8 s& F5 y6 b3 ~6 n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 X, _/ p0 X+ l: X0 y5 {, U* qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 b) p8 s+ b: [9 L. R% L( \| MCASP_TX_CLKFAIL . C: V% V& y7 E3 t0 f& E: v" G
| MCASP_TX_SYNCERROR
9 V/ g: b4 o0 X3 g2 c9 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' Y8 a, x2 w/ M/ t
| MCASP_RX_CLKFAIL
% A, H q9 A# Z8 H| MCASP_RX_SYNCERROR
: T- Z$ Y% b- K| MCASP_RX_OVERRUN);
9 r; A, `/ w9 I9 g6 @7 F/ u} static void I2SDataTxRxActivate(void)5 `8 e. R4 X* e$ X7 t
{
L8 o) y3 q! B3 E& S' K/* Start the clocks */
! T3 l& s. ~8 [- s6 B7 \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 `% K: E) Q4 lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 d8 {* W0 o& H4 j1 q5 g! YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* a2 }. H8 p4 l! r8 z
EDMA3_TRIG_MODE_EVENT);
' r. @; ~) i7 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 J; b# J% P9 x9 y R ?0 T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ t V2 {2 k" N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; \. ~& E) B" u3 K z" E4 X- K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" \8 w0 e' Q0 _; }3 |# m/ Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 }/ T0 |3 ~: J2 N3 N* g$ pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# o7 B0 ]. x( ~7 u# S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: l# \% r6 [! q6 n6 Y/ p4 m1 B/ n}
) W( A- J" i+ [$ ]2 u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * ?8 \6 N, l3 ]0 x. Q3 \
|