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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 R6 I: J k9 V5 I& k
input mcasp_ahclkx,) }# a' k3 o* Z. @% V6 v
input mcasp_aclkx,# Z9 I; S6 o1 s; {
input axr0,
+ Q% [- h1 v( i* U% A2 `, ?) t, W8 Q/ n5 l |( A
output mcasp_afsr,, ?$ w" u) g9 f7 F2 F6 ?* k) r: |
output mcasp_ahclkr,: Y: }1 H7 a* T1 k, r, @( Q' \
output mcasp_aclkr,
3 T Y+ k. X+ m) N) ^output axr1,2 ?" L0 B# y3 u
assign mcasp_afsr = mcasp_afsx;0 H+ U. ?# ?. A3 w& @/ |2 U2 V6 [
assign mcasp_aclkr = mcasp_aclkx;0 v6 e' a" {, c" s/ v# M9 T) @8 _5 m
assign mcasp_ahclkr = mcasp_ahclkx;* h- d+ Q( K# L! p
assign axr1 = axr0; 4 d. U6 Y& U) V- v4 p! H+ D
5 s! w3 }' Y" n! L/ p- Q: D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, Z! ?6 K2 K! e1 ?# I7 i+ ostatic void McASPI2SConfigure(void)
% o V1 d* T% s$ D/ G7 x1 y{
6 c# P& `4 A. W- `+ D' oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* Q# Z( Q$ L- Y3 L8 mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- u; I7 B8 f, d" N4 s0 l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ j, q$ i4 m& o: i$ X ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ G* c q- ~, x) ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 ?* f( b T; d" N0 l; C7 q' W+ zMCASP_RX_MODE_DMA);
w' r2 {- y, {0 f+ dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: W2 Z2 x" F; T8 u" \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
P# I% |" g4 v9 DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & n, G9 z {+ M/ S6 w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ ^- [. E. Y& `" a1 b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ x+ E' G% s5 K/ h7 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) n/ [/ G- P# w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# y. A a/ b. r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " w/ Y/ k- k4 n0 U/ l; _/ H% ?( w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* ], D" a0 W2 l7 M2 @# h# E0x00, 0xFF); /* configure the clock for transmitter */, A& T- s- u/ m y N2 Y, t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 x6 g9 [% ]- C8 J2 r" `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! W7 x/ ^1 P1 p6 H, O H2 s2 q, f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& N$ U$ ~3 v# ]7 b
0x00, 0xFF);; ^$ {2 T3 E7 a3 p8 @3 a
8 I+ N/ F6 ^% L
/* Enable synchronization of RX and TX sections */
# M3 w" E& `9 ^& eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( Q7 |4 @& ?6 t" ~) D) k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 h# T1 f( S: _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ Q# L6 R z! r$ ?* J7 W
** Set the serializers, Currently only one serializer is set as
6 o1 h; T l1 V" g) [5 \3 ?, i( U** transmitter and one serializer as receiver.
* e+ I* ?) |" Z; R; h& u5 q$ H*/- I: F) W0 O) j5 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 @) M5 m X& h' M9 ]! JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 a2 q3 P9 ^0 c: K: H
** Configure the McASP pins
1 D* X& b. N6 y% Y/ V' W** Input - Frame Sync, Clock and Serializer Rx
$ q& f$ \ O) s0 Y** Output - Serializer Tx is connected to the input of the codec ; N% e' v1 _$ l4 b N E( J4 g( e) k
*/: b }4 k' Z3 m+ C+ ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 j3 a _ q- W% e' l+ A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
k3 A% j; z `5 M8 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ x5 B; u2 n! s7 K: _, u| MCASP_PIN_ACLKX1 Y1 N; s* k4 r' ?/ y- b! q, Y K
| MCASP_PIN_AHCLKX% B3 H" }1 n$ h4 {4 r& J# ?* G* O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 k/ P( U# s: G3 e: Q: S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ `) @# Q: ~3 A& Z, [+ `1 D| MCASP_TX_CLKFAIL
/ c9 V/ `) L) ~" l4 l| MCASP_TX_SYNCERROR7 ]* O9 u3 o# z- ?5 x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 J' {0 A( B1 `$ A8 W| MCASP_RX_CLKFAIL2 {* E9 ~0 K: {& }) V) Y
| MCASP_RX_SYNCERROR
+ s* Y& @% R5 ]! [| MCASP_RX_OVERRUN);- k3 k- ^1 D# n
} static void I2SDataTxRxActivate(void)
! ~! U) b/ r( w/ K{
) p z( D. B8 y$ a/ H/ A/* Start the clocks */
: e9 M5 O O+ @$ u6 A& xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& W9 H- T2 G0 w& |: zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) ^5 Z$ `8 i% z# j8 m8 w% ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' q9 l5 a1 W) e* ~8 j7 M1 JEDMA3_TRIG_MODE_EVENT);$ d' b8 H3 v# x9 {& c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 f3 @" c9 }+ t7 x: O' EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 l0 q( i! g2 q1 l! A" }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# m) V- u) K( |8 C# U, PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 L& t' e7 K% t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& k& ~3 S0 E! n* h( t0 k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- }9 C% E, K: U& T/ s+ m6 sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 p! h D& F; I9 [% n- k7 A9 T6 ?' Q}
. S0 G* Z2 ?* z/ l: e1 Z `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # G8 E, [7 n+ |% L6 H1 m
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