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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( v' |9 m. z5 @9 L# J" E! tinput mcasp_ahclkx,4 g: p# q6 C5 ^ j: Z8 V' ]: i* d
input mcasp_aclkx,
$ e: O$ M6 s' X5 H& P$ F, xinput axr0,1 t8 V% P- W o. Z, p* ^2 A
; U2 Y/ J t( Q) I5 H- t0 V
output mcasp_afsr,$ c' }% L5 h! p' L
output mcasp_ahclkr,
4 y$ X2 I: A2 Q$ \0 woutput mcasp_aclkr,
0 `5 \7 v7 B' Y! P: t$ S' ?0 Eoutput axr1,
7 l5 B( ?+ T% y. n" c( ]- M assign mcasp_afsr = mcasp_afsx;
; L( V7 \+ T" B* H2 {$ { I- nassign mcasp_aclkr = mcasp_aclkx;9 L5 G- m. s" ] h/ ^
assign mcasp_ahclkr = mcasp_ahclkx;1 K0 P0 N C U/ C4 q
assign axr1 = axr0;
8 n* r. y* l, x$ G& [
" `7 J3 G% ^3 L: D! z; ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- ?) g8 M3 J5 L9 g6 f7 {static void McASPI2SConfigure(void): L' }1 j4 V1 [2 `) `& ?7 _1 [; m
{% l. |# _7 \8 \) ?" J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ |2 O& t9 d/ BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& f$ E% k) C5 ]+ {/ cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 P6 S6 l3 C- t* I# t5 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, _1 l. u2 S1 UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; c/ M& O1 N( m0 J5 J! Y
MCASP_RX_MODE_DMA);" r5 k5 Z0 ?+ Q% f( `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 f& k% a$ k+ r; V+ H0 f2 b# W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 L+ `) s( X& b" c5 T. a6 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! ^! i% A3 M9 \" V( [% K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ f J& x5 n% X: S2 {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( K- N! Y. K! r7 {2 |- H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- F1 ] Z4 p9 F" AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 ]1 g' C8 r- f3 ?3 FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ c0 R2 z; x9 gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ d$ c# u. `8 C* X* {0 A+ p* A0x00, 0xFF); /* configure the clock for transmitter */
& Y# b8 b- f0 @( D& y/ `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% u) n) I% S8 X @5 r4 a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% `1 i- r/ K4 [5 x, XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 ^0 H6 B' U- s0 f0 l
0x00, 0xFF);
$ i5 n8 t/ i8 F1 |& G3 Y& l
3 E1 @0 ~! R* w/* Enable synchronization of RX and TX sections */
1 {2 s' J( [. D0 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 J9 T6 ^- F$ O& `2 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' d9 s) Z: h/ y* Q. s% B; AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 D5 y: [& d. C1 Z0 ^** Set the serializers, Currently only one serializer is set as
* A- s1 u- t; g5 e** transmitter and one serializer as receiver.3 @$ |, v& e: V7 \' @9 e& ]9 d# l
*/
8 M+ H6 Y# s& ?# w( yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ @( E! y4 o* |7 _! L* ~3 a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: M2 {% w7 f4 n7 U** Configure the McASP pins
- [ z$ _& Z: O! ~ s% y4 B** Input - Frame Sync, Clock and Serializer Rx
- ]3 L. k: P. Q7 G/ e0 M** Output - Serializer Tx is connected to the input of the codec
- t# G1 {. S9 m0 N. ^( y*/( g' }7 p# o6 h$ k$ z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 q( p* R. q: n2 k" B, _8 H6 ~" G' FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 U1 \. {: y: r- U9 g% k7 W2 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; S$ s0 U4 p% w8 R| MCASP_PIN_ACLKX
9 \* {2 o1 e2 D7 b. V$ k1 |8 k$ \7 d| MCASP_PIN_AHCLKX8 b# g) b; h: W7 O; ]- q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 G! H) I2 `2 B. a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " I8 z- l% h4 j6 w/ o
| MCASP_TX_CLKFAIL ( H1 X) u: f, m) U( C3 c
| MCASP_TX_SYNCERROR
, n! u* }. e( d$ M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # c% v5 A% k7 p
| MCASP_RX_CLKFAIL4 N4 N# \+ L4 N1 s
| MCASP_RX_SYNCERROR
' M) s9 c) W. ~( {0 S8 l6 @| MCASP_RX_OVERRUN);1 H s- A! r o, d: ?( A4 U
} static void I2SDataTxRxActivate(void)
8 F# S. U! x# g{
/ L& _" V! O. _2 c v/* Start the clocks */
; X# T% ^) W8 J/ [, b4 p( @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 y3 c4 ~; ]5 B r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! X: z% V$ D# H0 b1 N5 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% |* o0 d4 N7 d. M1 z9 JEDMA3_TRIG_MODE_EVENT);8 o5 C( j) ^3 O( a9 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * B% ]- D' I4 |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 Y2 | O& l6 e* XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( ~4 I8 l0 k! V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% r: k% Z) _: Z+ [- Q: wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 H: K D1 `- k! P4 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 H% `5 I8 ]9 y |2 `7 n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. g4 L; U5 n% z+ k% ~- V}
2 I1 i4 |! I/ Q5 M1 _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 w. O* N* B& T% m1 T5 h! Y1 u' `, k
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