|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 a2 a' o. I; L3 T2 P; g" ]/ s$ @6 rinput mcasp_ahclkx,
- l0 Y, o/ l5 yinput mcasp_aclkx,
, q* d7 W4 b, W& V' T5 X% jinput axr0,$ @3 D8 R* u! k T0 ]6 C
% |0 y4 R0 n6 o# P0 [output mcasp_afsr," W; H0 r9 V0 g3 \# j& h; }* L# F- ~
output mcasp_ahclkr,
0 e0 U0 y; Y. T Uoutput mcasp_aclkr,
9 R/ T, y' y9 K! }* q/ N" boutput axr1,
, ~( m) J1 k0 Z; T assign mcasp_afsr = mcasp_afsx;' i+ Z6 P' N8 h7 I- Y
assign mcasp_aclkr = mcasp_aclkx;$ ^* J3 a j3 R5 O9 A, n& w
assign mcasp_ahclkr = mcasp_ahclkx;
6 `! y2 V5 W0 S$ a" sassign axr1 = axr0; 4 q: G4 \. W) F4 q: M, U
0 h) n: s& G% }+ c1 X* U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- Z- l$ b* F. V9 sstatic void McASPI2SConfigure(void)/ S/ v r* V" b2 n4 S
{
4 `5 Q: D/ [" O" Q3 E( EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* r Y; K3 B" O8 f! ]5 p( d/ [7 `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" s9 \" V9 ?9 I' `( pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& l4 S/ I$ k$ s3 \5 \' WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 @. A) ~, ?2 l0 l) _+ x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
B0 A& }# I! G7 p$ lMCASP_RX_MODE_DMA);
, p* _) a% P8 e" `% f2 aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% L; C# }% K; l& n3 v" V2 ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ C' t9 R4 F0 o9 X4 P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # i& y9 O3 Q! T( T5 ]& W. ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, s! Z; ?" r& E7 t* @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / N- L/ r0 W4 D) N' U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* y U M+ c& c; Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! n2 J: ?9 I. q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 g4 {9 d+ C/ \! x: B- E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 [/ M/ ]9 o# ^0 H0x00, 0xFF); /* configure the clock for transmitter */( m4 y! L7 @8 {( q: n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- w* N& V" t0 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; h7 u4 N. `. H; y- p* U9 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' T* ^8 J; g% l9 [( s0x00, 0xFF);5 }% @1 \5 X% _: g. ~, c2 s
! y- A( ]- N( c: Y+ z# @0 U
/* Enable synchronization of RX and TX sections */
7 s. U$ [# B, n) j) J5 DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 s" e4 L0 N, `) CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 t% f; R6 t! gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: C& Z, g$ o) l5 ]" i3 A/ {/ l
** Set the serializers, Currently only one serializer is set as
* I4 }# v3 @$ R** transmitter and one serializer as receiver.6 j$ p9 b/ c/ Q7 ?1 |0 c7 _3 F0 c
*/3 T8 k9 Z$ I. g3 z" `; a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. p% Q8 h) g' B/ A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# h1 T2 q3 ~2 { C! I: L# U, J** Configure the McASP pins
0 G: O# `$ ?% E$ N$ w" x6 m; }** Input - Frame Sync, Clock and Serializer Rx* s" \4 v' a9 i$ x: K: A
** Output - Serializer Tx is connected to the input of the codec # d. f) j/ y7 u7 m4 w3 k: e
*/$ _8 B! Q# v- W7 ]! f" p4 \) z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 x* F9 N% Y, N! ~0 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ Q7 `7 z* B- V% v: aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 I7 ^: l. U# r9 j9 j
| MCASP_PIN_ACLKX: s# r5 i( U* I `, S2 t
| MCASP_PIN_AHCLKX7 d- E$ W- U; \8 U: E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( j% V3 m5 j# o# P @( H' u3 fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - y7 U( [/ V1 A. S* m3 b' S* x
| MCASP_TX_CLKFAIL : k* Y2 V$ a) R: X
| MCASP_TX_SYNCERROR5 _/ j: x1 O ?$ R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 e; m0 K- w) W- q| MCASP_RX_CLKFAIL
( l2 Z6 ?5 q( o+ O8 ~| MCASP_RX_SYNCERROR ' `- |$ K( |3 ^6 f5 Y
| MCASP_RX_OVERRUN);) [& k+ l9 U) S$ }! o, x- P3 d
} static void I2SDataTxRxActivate(void)
" {6 w* z% F) b; B4 O4 a. O{5 t: G Q: J K1 Z
/* Start the clocks */2 S; p/ V o& ~& _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 d8 A1 r7 `8 V/ _! o( A8 _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) j* r4 z* u" w# H: wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; h, U5 V# [2 N- j- d3 P! kEDMA3_TRIG_MODE_EVENT);7 ]3 `/ ^3 S% {+ Z# x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 U) C7 b1 b# S- k# A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
L( U4 E7 `' MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- A: c$ K/ h3 ?+ p9 h4 q x8 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ c3 n4 Z8 [1 @0 A8 j5 \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* s) P9 O* Y* h9 L4 b% `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) t$ i: D3 g B" C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" B" {! r: p- F- B2 M" M- N
}
7 `# B9 p% r2 i: f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 X- M4 h. f0 n- a: C
|