MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
2 T- a, e% n$ _. A% c7 Finput mcasp_ahclkx,
; c# T; ?3 B: Finput mcasp_aclkx,
input axr0,
7 }4 `* N' n7 J3 T. g, V
output mcasp_afsr,
, c2 ?7 W0 ^. Q7 D- o: @1 routput mcasp_ahclkr,
) y/ m, F( R  ^7 U0 t9 Eoutput mcasp_aclkr,
/ V( a* U- A5 E4 G6 c2 Koutput axr1,
( a% \0 F3 c# j8 h

assign mcasp_afsr = mcasp_afsx;
& {1 {' G+ _6 u! K4 N6 T. W2 B4 Zassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

' s% E' F$ m# `: ?

static void McASPI2SConfigure(void)
/ @- W) e4 j7 P% d  k{
& Y  L) u1 T: o1 D! j& X5 f2 xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
! ]" V& t( B7 p' R- o% rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
7 k! J3 G8 f: n- R- }# ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 ~5 f. @/ C7 d5 w; oMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ ?+ C% d0 z! V9 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: l" i0 o* x0 EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" H0 J/ W8 x" R8 u: oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" E* L- e7 }: f+ T  S6 q* dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 e( P" B" F6 g: w  S6 uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; ]- r: k. F4 L+ a! K8 H/ ^/ X2 N8 Q2 ^0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 n& o+ h+ b' T2 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
8 M1 v5 m# i3 b7 I+ z
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
! f9 i: k& k; m% e/ x; DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& ]# k* |9 {* L) B* F: h! b/ ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
# x" J: y! x% @+ Z4 H# x7 X) r. O** Configure the McASP pins
+ B( _# K7 g6 A" a6 P+ i% W7 g$ N. p** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
) f/ D6 ~) Q. J; E$ J7 a; k*/
* w4 m2 O( ?' ?8 m& IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" D3 f/ X% ~1 u1 @. FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
1 r' T: u, z' }1 w6 D) sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& Q2 g3 Z2 Z# H+ X4 L# o| MCASP_RX_CLKFAIL
+ J8 v) L) [: N" {8 N- o| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
% `3 m5 a3 D+ K, s) w8 q3 x}

static void I2SDataTxRxActivate(void)
5 g$ }) h* |! A* r4 o{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- s% p( Q; o7 u5 K; i5 uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
1 B. l3 [  @; q. N" H" O3 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
. D5 H% T! j4 }$ V3 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; T% W. C# K$ {6 D# T$ CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
# [/ e& y$ G5 G" ~; g# a* V5 [5 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
& ~- y* W7 V0 c# m2 Z/ b/ SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. `$ f& Y3 o+ G" p}

/ t/ P. H/ v; j1 J% k% i8 \6 _. R! \

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.