MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
: M9 }. C6 q! H* i5 X' d5 K0 Linput mcasp_ahclkx,
# p" O; |7 [" z+ X. ]input mcasp_aclkx,
4 o: l7 x( g, V2 o$ u% Qinput axr0,

4 C- H: z8 M3 J/ |output mcasp_afsr,
+ D) u# z! U- ]" loutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
% l* b8 v+ z- s- n+ `

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
, _8 w9 d: [  i0 hassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

( O9 F8 D6 J* o$ F* N# w# B" y
4 h; U# h" P3 c3 v  f

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
8 l# r( d& x* }& p8 ?: nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" V4 }  Q6 Q0 H3 P7 kMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
4 d9 V) e) C# f: z8 EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 q/ N( ?! R9 v2 U" g# j, \) v/ RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: y4 ]* g! q/ H; V3 DMCASP_RX_MODE_DMA);
* R6 G% m4 y' z( m8 Z- vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 A( r% ]- M% z- s. NMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 a. O- ^+ b% w6 }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 D' p4 [0 ]3 aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; w& G$ N8 G/ B( nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 @% M$ [# r  l% u- ~0 L) j0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! V: X) x8 j4 F0 i. f# T0x00, 0xFF);
. _& f3 Q( f! u8 Q; n+ O
/* Enable synchronization of RX and TX sections */
2 ~* X9 R' V7 N, I2 x, GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
1 H2 E* r3 g% x+ K' ^, i** transmitter and one serializer as receiver.
*/
6 E& [9 h+ Z9 j+ |- @/ ]/ BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( q, S& s- w; @" A3 Q! j5 N) Y& pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
6 w0 y% U) Y/ C9 s) C** Configure the McASP pins
$ B5 \) `& l- T2 S1 w& Y4 x. K** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
$ N0 W# O5 o3 uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
4 ]" O# @/ x- u7 Z4 t! {( f6 j| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
: X1 u/ @9 K3 @0 L5 JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
7 s( r4 n$ T7 M. U+ {| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
9 l0 A9 C& \0 Z2 A. A; X6 }* x| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
8 ~8 \9 w! {) k; T/* Start the clocks */
, y7 t, F  R: h7 g+ \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
0 y7 H1 X% c/ i; v4 j' s; cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
2 ?9 a. ?, {" A' M% b8 H7 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
: q( P, y1 O7 c0 U8 Z4 d. x) Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 |+ Y1 L* z+ }9 l5 PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% [; A' x: f, G. e4 h7 K}

. ^! ]- w' O( s* D! p5 z

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.