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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) ~7 [, v( J, T( y. C
input mcasp_ahclkx,6 N4 |$ @' L6 J' q, s
input mcasp_aclkx,! ^6 X8 M0 j: K+ q* r* h
input axr0,
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* u; h% B- d$ @- b% \ ~- w ]( Z7 Q! soutput mcasp_afsr,7 r) p. i1 o5 ^+ A! T6 r
output mcasp_ahclkr,0 U" H0 ^; W; \. i6 f: C
output mcasp_aclkr,& I4 q$ H% d) w8 P! B
output axr1,
2 D$ v8 e) R, ^6 \0 Y. v- M( j assign mcasp_afsr = mcasp_afsx;
0 [( p4 f! J, j$ w! x+ f, E6 k/ L, @assign mcasp_aclkr = mcasp_aclkx;0 e) ], h3 J% T! E
assign mcasp_ahclkr = mcasp_ahclkx;8 {1 Z% O. ^" n
assign axr1 = axr0;
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0 c8 @& T/ b0 m9 K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / t: z* }" V1 ?& s2 ], U
static void McASPI2SConfigure(void)
2 y( i A& U% w{
. g# F- @& \: [( ~4 W gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ L4 A! V8 ^" k; k, n: o9 m) w1 l) ^9 @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' _6 U8 P! M6 v# ]3 G0 V' _" RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 v- Z3 T2 Z; ]' N, WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ J/ v3 V7 l( c% p# R4 V1 [& u) ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 ^ i/ J$ q- c+ @ A! t$ F
MCASP_RX_MODE_DMA);
x! { k4 A0 v) tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 N8 ?" u6 x* M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& {# Z0 p/ M C( T$ S2 K! s' g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 r: b! o' g3 W3 I* kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* @1 M: t2 z9 P) Y, V2 a* f: F/ JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) h) ^ j' i' [: U% b3 H; v/ LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& W) v: Q" ~/ @. K- \2 z3 F6 _3 _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 G F1 I2 C! S" X: f. z% M5 PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; i6 ?4 z, ]' `( J ?& {1 T' ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
I) o5 r. T, @8 e0x00, 0xFF); /* configure the clock for transmitter */
4 C9 A0 B1 [( m( E' K* \" V( WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; h& l7 ~7 x7 Y3 R% w; S) DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) }: b/ g$ C$ E# O8 |$ _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 P5 G6 }# [: a3 R M' r7 E0 V0x00, 0xFF);2 m& l: J! ^6 S/ o) U
# M7 A8 k. s: G3 U' F; Q/* Enable synchronization of RX and TX sections */
3 L1 L0 }+ W. x1 J/ I qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 O/ w! h5 u$ ^/ `: ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* S- w( e p% ?8 t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! U; L8 `4 b# z! g
** Set the serializers, Currently only one serializer is set as. t6 s J0 f+ x3 B6 F% A; r, y* |9 A
** transmitter and one serializer as receiver.7 O: t L& I( F3 d! g" k
*/9 ~+ t8 V3 D) ~, o) u* ]/ h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; w2 o2 t- \* r# v) VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 K# T. Z8 I+ f1 B
** Configure the McASP pins - j6 @. |5 ^) V' d4 K
** Input - Frame Sync, Clock and Serializer Rx3 Y! ~0 Z( F( S
** Output - Serializer Tx is connected to the input of the codec
0 L& U! p- x- b9 o6 k' J5 s*/' L Q9 Q3 S8 R5 ^ m: Y7 ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( P F# Q' E/ p6 M1 h8 \4 E' l. cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 t/ D0 C2 ?" V$ \9 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 F {4 y4 g9 F4 h3 T' r, m
| MCASP_PIN_ACLKX0 }8 f4 l t8 ~" u
| MCASP_PIN_AHCLKX# T) j {% X- k% r" l. Z, l1 q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ T' \% B( v6 V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( P2 Q4 p8 M& K I1 {| MCASP_TX_CLKFAIL 2 \/ K4 n: E1 \) \
| MCASP_TX_SYNCERROR. N) _1 R s8 w& z5 ]4 i- |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * S+ [0 f: X& w
| MCASP_RX_CLKFAIL2 R2 r1 L2 b3 u; E+ P [
| MCASP_RX_SYNCERROR 8 S: f% u9 G9 P2 u5 R1 N2 M& ?6 q
| MCASP_RX_OVERRUN);/ q/ S3 e( M( h& J: e7 O, r
} static void I2SDataTxRxActivate(void)
* d) [) u# X3 n( ~{1 v+ A$ _+ b7 |8 S8 \+ s, ?; W
/* Start the clocks */ S |9 e# m5 I, x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ [; O0 j% A/ O/ |! G. n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* i* Q* D @4 D/ o5 a$ O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 w* z" Z# ?# s. |; x
EDMA3_TRIG_MODE_EVENT);" Y A1 Z! [. d- K* N; b0 X. O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 D! l/ d, B2 x1 o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& A" c1 u4 d' [/ Y$ x* rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
^" |2 g: Z/ kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* v2 r9 U* f" G8 [, J# m3 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 Z% X# b9 Z$ G7 _6 ^" Q6 j6 {0 NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 r- V5 ^+ w& X" p& B# f6 i# W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 ]0 z: \- F9 m0 f2 n9 X( x
}
6 x* B# M2 n# `# D) |. O7 T/ m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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