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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. o# U1 J# D( g; R3 ~, y) b
input mcasp_ahclkx,
^6 F* E/ b- N, n( vinput mcasp_aclkx,9 l0 k+ g! G; O+ F/ l* B; r
input axr0,
. _8 x* U0 K8 m6 C0 [, I3 W0 g# W0 Y) [" b- B$ A
output mcasp_afsr,7 j/ K! q7 o5 `5 f& z
output mcasp_ahclkr,
/ ? N" x9 Q( g1 Youtput mcasp_aclkr,5 _1 C5 e1 J- ?! C2 p# g9 i) E1 Y
output axr1,
! U5 e3 b" |8 }4 v" Z6 g( ~% r; z assign mcasp_afsr = mcasp_afsx;
. K% R4 [4 b0 N! g/ \; \assign mcasp_aclkr = mcasp_aclkx;
+ @4 d2 ]2 t. jassign mcasp_ahclkr = mcasp_ahclkx;8 a5 \8 g) h5 Z# G8 B: k
assign axr1 = axr0; ( l2 @/ L6 x$ J k# i- |' q
! C( Y% v2 R6 E* v1 W y& M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 A& A- D. M/ K7 C( \( L4 M
static void McASPI2SConfigure(void)- u! f8 D d( T
{
4 z' Z# s7 Z; m: SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) i# x+ [. l* F1 d: R0 IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# I/ r! S6 q1 w0 F1 wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 t2 k" n5 S- s0 n2 w) u6 _5 X: s, E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 E4 p+ |0 P- f6 Z, [1 I4 M t4 ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 }, c! D9 c4 P0 Q2 xMCASP_RX_MODE_DMA);4 _0 M0 P8 _+ u3 c ^% W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) F/ l* B0 A" u. u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* i2 v2 f. t% I9 @2 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : C6 z# {, e) L+ i, R2 T6 h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# V: \5 e8 l7 A; D* v JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 M$ {3 D. N" v7 VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 o6 q2 A! c9 B- U. ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 @9 [# r: o" m, U1 f8 l! n% j' |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , N! f# ?. X- E) H% _% @& W6 f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, A5 z" C" r) I9 G
0x00, 0xFF); /* configure the clock for transmitter */
/ e, ~+ v* e. E% C- GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); O, N% X) }/ i! `3 \6 {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! M/ r/ V# {% b, R# i; s0 V, `+ n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ s: p0 {' m" r" s& P: z0x00, 0xFF);
" K* N! T' y5 `* D4 F+ F
# { b+ U% E7 M1 g/* Enable synchronization of RX and TX sections */ + K/ E, C9 A7 d5 J6 K2 _: ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 z6 R% g! f& H8 ~3 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# _: Y6 l5 ]8 O* g2 H, Z( A7 l gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 L% R7 W" B$ z/ d$ O6 Z* w
** Set the serializers, Currently only one serializer is set as
' b! p! F: y5 ^: R, m; e" l** transmitter and one serializer as receiver.
! P2 X; l B$ W0 a- C# l*/
0 T9 @0 x/ I. }/ v6 WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) y8 [0 l' j9 Q/ i$ H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 I5 S' S0 ?; c& ?
** Configure the McASP pins
5 H G5 s5 ]2 Y, I% A# K/ m** Input - Frame Sync, Clock and Serializer Rx, _/ [6 }6 g/ f; H9 U9 \
** Output - Serializer Tx is connected to the input of the codec
' n+ a: r2 r2 }*/; A8 g0 s; k/ `8 p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 O1 m0 W0 i6 b" d( k" ^: R$ ]9 F+ v! xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 r: V! e8 K1 g; b& Z8 L& bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! ]0 f3 i7 m6 L* H' m
| MCASP_PIN_ACLKX' e$ i. B& q9 f3 R
| MCASP_PIN_AHCLKX( c1 L" w9 H* |3 l4 P3 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: `, [* [! F7 p* I) rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : L1 X1 c0 E4 [, Q
| MCASP_TX_CLKFAIL ) F8 u8 U: s e+ j
| MCASP_TX_SYNCERROR
% |' p" f) f* D3 d! t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & f% R* ~2 T; G- T' W
| MCASP_RX_CLKFAIL. S, Q4 V- u3 f0 R8 `" q" B
| MCASP_RX_SYNCERROR
: P+ I% x, m$ t( T/ @| MCASP_RX_OVERRUN);
5 T' t" e3 J& u! d+ E7 Q} static void I2SDataTxRxActivate(void). l! b& `8 k; y, H1 C* i; l `
{
2 V+ r" M b9 w/ b/* Start the clocks */
3 j# O& S4 ?+ g$ N/ h( KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; x7 s( G; O8 h( k6 iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 c1 a7 p) I$ F1 X/ `2 Z/ w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
^. ~0 c" Y4 k7 u+ q6 n/ {EDMA3_TRIG_MODE_EVENT);6 Y4 Y7 d: [% d+ g6 W, n% W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; j, s5 ~; Z! m% T. ~% u' EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ z2 G4 m% d8 t2 T( F: u, [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' G5 `3 |- \4 E/ b( V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; h: t. R/ H% ]! f. U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; _* C& m# c8 Q, }5 p, r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 u$ m! a, \) Q' x, s) C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ u7 A* n8 ~2 N! n5 o! [}
/ S/ Y G' m$ j2 D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # S1 @2 @/ s2 ? q G
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