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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( a, B/ @6 |9 F4 }
input mcasp_ahclkx,* Y+ E0 l, k$ ~9 {
input mcasp_aclkx,; U! T, @+ Z9 ]7 k2 h" y3 V) b
input axr0,
- }- A, d. m4 s% X$ d8 R! B7 Q* s/ b q
output mcasp_afsr,; i+ r( Y: F& X7 B$ g0 N) H) N) M
output mcasp_ahclkr,
) v- w" ^. I% M2 {' f3 B. p2 x8 M ioutput mcasp_aclkr,2 I1 v' v8 Y; E; Q n6 E7 P
output axr1,
! {; i4 a& s7 f- S assign mcasp_afsr = mcasp_afsx;6 |3 @' l; a: `. g6 g
assign mcasp_aclkr = mcasp_aclkx;
3 n+ Z5 b& O. s2 i sassign mcasp_ahclkr = mcasp_ahclkx;
* o9 V( B( o+ F! K1 W$ jassign axr1 = axr0; 1 ^2 W. f( |; k [8 h# y& s: L2 Q
, I9 J5 U( K! E! C" V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 Z% |1 S3 `! X" N4 Nstatic void McASPI2SConfigure(void)
, @& f& j8 F# D# P. g5 o{
: ]0 f7 V; `1 b9 JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! v$ R, T* Y/ q! T/ @4 KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; {/ v7 X+ A1 Y. D' `, g* kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* A, {% G' F* u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- W4 Z3 g4 D0 g/ D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; S: i/ E8 Y/ @
MCASP_RX_MODE_DMA);
0 t2 N( Z5 d+ f) I9 S4 m2 {5 CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 {: l5 X8 h0 K' h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" |# @. }' W5 z9 f7 R1 |: N. N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 ~( V, e3 g6 g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. T# M! t3 _/ Y2 q& h$ r; O5 UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 }5 T. _0 X: I$ mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% T5 v4 [5 Z9 M* r) iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% V: h D) v4 B' f% ~ [- M: |7 hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- d, D# `0 P6 S' ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( [8 S0 W1 s- X% `. k+ s: ~6 \
0x00, 0xFF); /* configure the clock for transmitter */
9 K/ N: K5 A) K" h% uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) s, N9 `0 i; L1 D- OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 R) { }$ _" p* s' G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ q1 e2 U/ R. N8 p5 a" y- l0x00, 0xFF);6 z& t. { k, ]
' W. _1 L. o. K# Z4 Y
/* Enable synchronization of RX and TX sections */ # m- ^ U( |4 D! ]1 _) C& a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
v! Y* \8 l" L. ~! V. ^- L: ]3 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 O2 h/ y; G5 ^9 b8 p3 u( t- A1 H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) z- r- [. R7 G; [! ^1 E$ ?** Set the serializers, Currently only one serializer is set as! N$ j/ }1 D5 e! K5 b
** transmitter and one serializer as receiver.: N; H( j; a. i9 K" C0 V# }
*/
- H8 U" p5 R. s1 p8 f% v' H6 T9 yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ L# j# I$ m# k8 m! `5 O: o$ ?; CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% `, C- `( B+ H: T6 h7 X( p! W+ k. t% O** Configure the McASP pins
* w6 Q; f2 H5 r( N V d** Input - Frame Sync, Clock and Serializer Rx# n: |! K( i( ]
** Output - Serializer Tx is connected to the input of the codec / T+ b9 C& x. a+ u, m
*/
9 [ ~2 ] V/ _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; \1 F7 D: r5 {# `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& _4 H8 \+ s1 m' t# h# FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* o6 ?9 D! [- {' C) [7 u7 E
| MCASP_PIN_ACLKX
- x4 U8 z' l' Y! o& } i) n/ ~; _| MCASP_PIN_AHCLKX
# @% X0 r8 w; E0 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. F7 z2 Z4 w' a4 R- n) h& t$ c( dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 e1 S# b+ `# a9 C1 f| MCASP_TX_CLKFAIL
; R- S, }1 X1 i- k| MCASP_TX_SYNCERROR9 z8 o) ~- T/ k7 [* l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; M3 w0 ?' J; _$ H
| MCASP_RX_CLKFAIL. P; J$ Z: Z- d* F
| MCASP_RX_SYNCERROR
! f0 [, g- \' N- @1 c| MCASP_RX_OVERRUN);
6 |+ c' H2 J" p+ V$ N+ f} static void I2SDataTxRxActivate(void)
~1 W! W. ]) a9 \{
/ {; _* x3 @/ C( n x3 n* s/* Start the clocks */# y7 [8 }7 [4 l6 Q, t5 i% j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% i/ M h/ h) @: j4 {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ B B$ ^5 ^4 a; h3 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 P4 d0 q! n% ]: |" u; m/ H5 X$ s
EDMA3_TRIG_MODE_EVENT);
7 ]# p/ N: n$ j3 c, rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - e6 Z7 h/ V. E3 ~& i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
z) r) Y+ W; O/ `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 ^1 J2 V2 `4 S% g' N; {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 I6 K* M0 w, mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) i( w5 e7 O0 e$ h3 d5 [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" ^+ @' ], U8 S6 }$ F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; B& f3 Y% |5 ]* R' k7 ?}
0 J4 s w; J( i, P, S# y7 O3 k+ ~6 j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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