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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% ]& f: K5 N% U$ b9 dinput mcasp_ahclkx,
" u% q$ b) j* D% [6 e- ^input mcasp_aclkx,
7 z0 x* G8 A1 {, w! Q, J9 _input axr0,
6 t: D8 b4 O! P. f9 I ~. s; W
1 t O$ u8 o- m- d. L Aoutput mcasp_afsr,
! e/ e& T. y% |& S, m# poutput mcasp_ahclkr,
% u2 I. U0 |" ~" ~( t' V8 f; b4 Goutput mcasp_aclkr,
* V" @. `4 r. ~& @output axr1,
. a2 K$ G. E$ g k* X2 c assign mcasp_afsr = mcasp_afsx;
( q3 p$ w7 Y' V7 B, Q c+ oassign mcasp_aclkr = mcasp_aclkx;& |" z$ c5 `+ I) u0 b; T% U
assign mcasp_ahclkr = mcasp_ahclkx;$ \: c) u3 [& q% X, u1 o
assign axr1 = axr0;
) j3 S2 X4 K. W% a# l- @4 k: U4 V. k) b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * d4 j0 F$ X5 i/ H2 d
static void McASPI2SConfigure(void)
- _$ ^0 c: T; j7 r4 o( M1 Z{
7 p& [: g% j6 g+ F8 K5 X0 ~5 FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 Y* u& h, q& `4 b4 m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' h) l5 f3 ?1 y# ^ x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' O+ [6 @4 E0 x9 T7 P8 H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* o- ^* J: `, V4 u& D. gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* {" z- x7 S1 n1 j/ t+ _7 a
MCASP_RX_MODE_DMA);
, _3 ~0 O* q8 C/ |) g5 M8 }/ B4 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 x2 _; I: `* N) k, T+ kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) Y! N5 n8 Q' z+ a% e8 gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , F* x* N8 m$ p5 l" W, Y3 K9 Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 \+ K; h- n$ m% j5 r1 z3 fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 E3 } u: x# Q" R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, K# V4 `% r f' O' u! l: M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 [! O9 H, r( T: p* [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 m8 T# |5 o# C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! K: W4 ]" I' S' @5 v- Q% j j3 M) ^
0x00, 0xFF); /* configure the clock for transmitter */
) i! P( |, e/ a MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- n' t, R* w4 O. B+ f/ K- H- ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- B( A1 j$ D$ a6 PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, b& N: v- }8 N$ O
0x00, 0xFF);
4 C& Z# G7 p3 Q6 V
/ I. _$ `4 y$ @5 y* U/* Enable synchronization of RX and TX sections */ _( m! T5 V7 ?( {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. g6 S! M3 g0 p* u) b$ c) ?6 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! [. Z) D+ S' m# F3 O& UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* [$ g: F1 X% h** Set the serializers, Currently only one serializer is set as J0 O4 I& x0 ?0 N( U# E
** transmitter and one serializer as receiver.
8 X7 H+ y; Y3 x4 l*/: S% E7 B' n- A7 Q* x4 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( B. z: }' D) P, E v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 o8 _4 \% S5 i$ r" s
** Configure the McASP pins 5 X4 b' G( m" N+ Y3 f$ s6 e x( t. b! y
** Input - Frame Sync, Clock and Serializer Rx
, f, }* s- H# ^( h. k- Y* H** Output - Serializer Tx is connected to the input of the codec
- v& a3 ~8 A \. r7 y* @*/
. T# Y3 K) W: `" [* uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. H) v. J% i- fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. z7 x" P- c& F/ kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 O- J8 j, v( n3 u| MCASP_PIN_ACLKX
3 a- V; z! E& {| MCASP_PIN_AHCLKX, M9 |+ J& y* S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! G& W7 V1 g* |1 P& W0 d3 z1 {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; B4 k$ s) _( f0 O l k
| MCASP_TX_CLKFAIL
0 N( R7 H' a! a7 y3 f6 {. d& z| MCASP_TX_SYNCERROR6 z [/ }" v7 \. E) K( l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 k4 l3 ?7 T. `3 u0 J- N| MCASP_RX_CLKFAIL
$ V4 P+ L6 l" u {6 E| MCASP_RX_SYNCERROR
' i8 `, n- B H# B| MCASP_RX_OVERRUN);
: T+ e) B3 M1 Q# x! [) ~2 {3 D} static void I2SDataTxRxActivate(void)# x2 F% f8 f) i5 O; x6 | ^
{
2 \: C; y2 }5 F4 W+ n3 u/* Start the clocks */( i0 E Q2 Y0 g% M$ e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' Z, r% Q; n8 l* G9 N. ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% X3 v) _" ^7 O; u% e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; n2 g/ W5 y$ e2 cEDMA3_TRIG_MODE_EVENT);* u: B3 s0 ?( f" ]7 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 ] o; X( U3 V$ ^" ]& Q& ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 s+ h: U2 J; q0 J; q- l( |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 l% A3 G" L. D8 j- t- i; G- s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% n5 k( z3 M1 y; u( w& Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ e% Q0 i% m% J+ A. r& QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; B$ g8 D& s ~; W& mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# s( e2 y. H- Q* h( c
}
, q4 ]8 F4 t: Q: U" ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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