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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 G! W: n0 [. Q: b @3 Jinput mcasp_ahclkx,
, {+ A* @% H5 I' K. qinput mcasp_aclkx,
! |" `+ y: L6 x& Finput axr0,& @3 j/ L5 |* X4 f
8 w1 x+ O: e, ~6 L: C" Goutput mcasp_afsr,: V/ X/ w. v. F3 \: v) a0 I
output mcasp_ahclkr,
& i5 H. F! G: }7 d( @output mcasp_aclkr,1 f$ K1 S4 z0 H0 i- B/ b* b
output axr1,
6 n8 e. U8 W8 \& C assign mcasp_afsr = mcasp_afsx;
: n0 t0 \9 M9 N1 X% eassign mcasp_aclkr = mcasp_aclkx;0 F1 z4 u: f" ~+ i. n" C
assign mcasp_ahclkr = mcasp_ahclkx;
% [. m* p9 e- T, J( O7 A. Nassign axr1 = axr0;
/ x n9 N7 j7 {$ s- C, \/ @1 c# H' f, ]* X; G" N6 K4 y, Y+ G! P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ t: e( o: l) |3 M0 Mstatic void McASPI2SConfigure(void)
6 U# L2 W% t1 q" I: z9 _2 g2 A{
% q9 M9 E! i- gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 P" r' d' A: ]; m$ Z" R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ T/ @ w7 L7 U% l: A, ?# fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 B$ Z- H5 P9 NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' U3 t/ ^/ T4 b3 {2 Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
n, g4 Z0 ~5 Z- J/ S. pMCASP_RX_MODE_DMA);5 M& C9 D* Z3 b$ B1 J( P& M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" y1 e. p0 ~; y# A% j l, }3 M9 aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( p. D" P5 P5 g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 Q2 Q/ A" e6 x0 S4 P: w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 b; `* n+ e/ A% d8 }4 S/ CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 V1 a5 E' z) u5 |5 y2 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 I* t& [) E; N6 i0 ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 @, j9 T) c$ j5 B! n5 TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); V- V, A4 s' |. e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& M5 X" P1 a7 z- ?1 O0x00, 0xFF); /* configure the clock for transmitter */
; h4 S, E4 W% cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- O3 J6 _! T+ U* f% r! t, jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! A* X/ e& l3 B1 ?7 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, {8 M2 v# ?+ z
0x00, 0xFF);
+ z( ~+ o' z0 o
9 Q/ `: j1 w, V4 ~/ n* y/* Enable synchronization of RX and TX sections */
. l/ }3 s: ^+ c3 Y9 Y5 \5 F" _" q9 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% T6 t4 k& J. o5 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) U0 S/ y, j8 n; `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 p7 a o( T3 ?' O( [3 k7 }** Set the serializers, Currently only one serializer is set as# J2 f+ G+ K$ Q
** transmitter and one serializer as receiver.
8 U% [5 o- Q3 r, d/ x/ Q*// q6 w3 N- h3 T- U* K: D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ x, }- j. y! u5 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ t% X6 S8 h( P; Z; A4 A# P** Configure the McASP pins 7 b1 k) k/ i. m% S# w }- l2 h
** Input - Frame Sync, Clock and Serializer Rx$ x7 w3 X# `6 G3 [- }! e" h
** Output - Serializer Tx is connected to the input of the codec
; h* w2 X8 y9 @7 K*/
C4 N9 T' h U2 |* v) QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 ?5 `* G2 u4 C( A* t* V3 z" M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* y5 c5 o9 D/ fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! R, v+ m. W8 R5 E2 j/ C5 e/ w
| MCASP_PIN_ACLKX
1 H4 Q4 W5 O. X5 Z' d3 n0 p# W9 b| MCASP_PIN_AHCLKX
$ U T- B9 z: ~" q! m6 ` r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
z* p, @; @7 p2 a6 J! u; ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ Z) H. I8 j- s" U| MCASP_TX_CLKFAIL
4 U) N8 Z' D) w7 z, J. R| MCASP_TX_SYNCERROR6 a0 v8 E0 l) b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " |" b# n& D4 D( a8 l
| MCASP_RX_CLKFAIL4 A; e0 L- `* \3 I; G, t+ n
| MCASP_RX_SYNCERROR + f' K* P1 H3 x6 k+ s, H" ^
| MCASP_RX_OVERRUN);$ f1 Q2 w" m( }: C* h' `1 \
} static void I2SDataTxRxActivate(void)
" V& _: k! K" ]6 |+ Q+ U, F% P{
, A3 S$ ]( R9 S9 }7 p: Q/* Start the clocks */
; B) A2 x1 j/ b( a" VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. A: x2 h6 h5 M, o) T! ?% w- N' r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# M. _; y. U$ e' K2 O' E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 r4 ~2 K; i4 H! dEDMA3_TRIG_MODE_EVENT);
0 x! _1 z- [: R3 L: ^# P! _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 N; @4 s' E& CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; y1 r6 d2 c+ r; V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); P1 S8 Q- G% z; x7 s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: K3 K# ^7 ^) x0 R" r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 l. [8 h/ F" X4 X" g$ X# b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# s% \+ m8 f8 b( g; [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ w$ b$ @4 P& b) m! S! ?
}
! Q' k6 J+ r) B; V3 o. }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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