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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 t; Z) U2 E- e+ ~ o- Y2 G# @ Iinput mcasp_ahclkx,
6 S& t# A- U. D" yinput mcasp_aclkx,
|! N& r6 c4 V3 L4 _. ~input axr0,/ E9 d+ q/ E! H c
. m# h5 N+ C2 E* a, \' n
output mcasp_afsr,4 U1 ^' t! k' W- H! o! [; B
output mcasp_ahclkr,
. }5 w: Z' s5 f3 h4 {& D4 S6 D# foutput mcasp_aclkr,6 O2 \( Z# r( A3 ?
output axr1,1 ~0 x3 f9 K# }9 ]
assign mcasp_afsr = mcasp_afsx;8 v: S' \! r/ p0 q) F
assign mcasp_aclkr = mcasp_aclkx;/ j# S }' m, }) w- o. t8 h) r
assign mcasp_ahclkr = mcasp_ahclkx;5 {% ~$ J3 {4 F4 r0 _' n) P
assign axr1 = axr0; 5 C! [% g& X5 T5 \% J4 ^$ N0 `
" I/ X) Q! E- k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 ~( Z2 n* T* C/ ~
static void McASPI2SConfigure(void)
3 g, ]6 L/ h% K+ i3 x% o{! A- X G1 Z O& }- U% k4 p* G, R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& U- M& n8 a+ C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
j2 o9 ^9 J, ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); y1 i- i9 y; U& N; Q, e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
A' F- b/ H" k- XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& o3 P' c2 O' u1 b
MCASP_RX_MODE_DMA);2 r( o) v2 \ t' ~: b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 l! T. O N U2 F- ?/ t' ?! M+ eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; S, R+ c2 j4 [; g# ^# S! W: g7 r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ d- F- _0 B |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' o7 r& u; F: D2 ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; ]: L7 U+ c: b% U6 W4 A% q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 S2 m8 x/ z! TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 y% N# M. @6 eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ d& J" v; X% U# ~" mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% V; @- [# P/ a
0x00, 0xFF); /* configure the clock for transmitter */
6 R( [& b% K" ~5 R) QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; I5 A9 S- N" F7 z7 m% M* E7 f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 o/ g% X& G4 J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( s9 S0 T! l _% G5 S0x00, 0xFF);8 @2 V# L) K% `! [8 r `! e# K& a/ \
$ P7 _* R$ U$ b7 b% n
/* Enable synchronization of RX and TX sections */
) p" c& k& U# b" [1 w6 C2 y. v& gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' N ]9 E6 G3 D9 y$ `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 s/ V8 s% y; j( r2 M0 Q2 X: e; \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 I3 s0 k2 |( x" v** Set the serializers, Currently only one serializer is set as
8 w5 |0 d5 Q) g5 x+ ^+ @** transmitter and one serializer as receiver.
7 h6 t% o' e- A: `4 O; j% G*/* s0 G( J R( {% w: d. ~, _. P9 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! u; A z" _8 h; I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! R! s, L3 V7 D** Configure the McASP pins 2 M" @9 K( u7 L- `/ |( d; Z& \
** Input - Frame Sync, Clock and Serializer Rx4 I: A& \& ?' X9 \
** Output - Serializer Tx is connected to the input of the codec 6 e( O" t0 b3 n, v# {) |
*/
4 o0 P- k* N+ a$ i0 S7 l5 T) aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# B+ u" y3 \$ j% Q, w6 W: IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. m6 s6 v( o& w( V# D5 GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 i6 T3 r) r* ]% d* k0 \
| MCASP_PIN_ACLKX' U; Q5 P# H" i7 k8 D: g
| MCASP_PIN_AHCLKX
: W; A! H- z; Z1 d b/ y. Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ G; t+ L( x/ I6 g& J/ ]3 z# C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ p- U/ A7 A% K| MCASP_TX_CLKFAIL
$ B2 M. F S) b+ _ a6 ]' C| MCASP_TX_SYNCERROR( v; c6 G/ M7 T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 Y+ y$ M' D. I. i4 X2 X" L3 K/ Z
| MCASP_RX_CLKFAIL
' u! u4 v. \9 B- w$ j! R; \! [1 f| MCASP_RX_SYNCERROR
" e8 ]* Q& o. i5 B$ b3 E| MCASP_RX_OVERRUN);
$ V8 L/ [# ~8 ]( q |; V. L& u} static void I2SDataTxRxActivate(void)6 Y0 c% z% o0 O
{
L6 j4 g9 k5 u9 c0 r/* Start the clocks */# n1 t3 P8 j/ k0 O. f) ^- b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ D7 \/ G1 a7 h& f, P: uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 t) p, J" o) X. E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ e* E( v) E; f5 ]& wEDMA3_TRIG_MODE_EVENT);4 O) q" o0 B$ A9 h7 H5 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ \2 o0 ], C* MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, W- p9 J* `% Y9 |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 x0 y9 H, A+ F+ M! G3 |$ lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 g$ k& X7 J6 t! o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ q' |' E# C% O- }2 _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! }8 L* @2 J6 {& c! Y$ {+ ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ d* n& h8 U$ F) z6 X- c+ ]} , Z! A$ k2 U! J1 l" d1 ^* X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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