|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; G B# p; g0 |+ l; r" {, pinput mcasp_ahclkx,
1 v# \3 G# [) [, p3 u8 ~: S+ @input mcasp_aclkx,1 g: e3 Q9 H) J! I6 U }; K
input axr0,' ^5 Y7 \2 G: k$ s4 K
* }# \: {0 K% `: A: doutput mcasp_afsr,( H. s, B5 p9 t8 ~ s
output mcasp_ahclkr,% B2 u0 m! a# Y( r4 z, t5 s6 G
output mcasp_aclkr,0 C v. d* G G
output axr1,) d; x7 a1 x% B4 I3 l% Q0 [! {) V) q
assign mcasp_afsr = mcasp_afsx;! M, F% C" q3 J* \5 k' N& l
assign mcasp_aclkr = mcasp_aclkx;
' H# I2 {. j3 z' E5 Hassign mcasp_ahclkr = mcasp_ahclkx;: I6 s a3 k& }0 a1 }5 Q! e1 m
assign axr1 = axr0; + ]2 F6 M. q& ^* V
) f+ k6 t0 t6 M# s" ]! M+ ]2 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 Z+ k* } P1 E/ n' }
static void McASPI2SConfigure(void). b9 x4 n: ~0 n- q& D! U9 ?6 {
{0 F; v* d: D7 l: ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% [, T( K* r+ p' ?6 OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ ?& q4 P9 {; v# fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. A4 v' k* B6 k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 ~0 H0 b) {: ~4 E6 {% qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ P" X3 f$ K0 d9 E
MCASP_RX_MODE_DMA);
) W7 h0 k1 Z3 F# S4 M7 YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 C# j+ D7 A' w, DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" ?: S# d$ @7 A5 s6 c- L7 SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" a6 l) w; l* I' s2 W$ T' HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* n% T7 S# n, X6 G' F% ~8 n9 N7 V ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% f3 R/ i! @7 ~: y( y6 r# Q! fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# o1 K% b* N: M! Q- ]9 S+ U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 J* J5 ^# B# ^, W7 Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 Y2 u: I) C; G: [* a' ~ fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 O4 U& X; m$ }6 h& l8 K0x00, 0xFF); /* configure the clock for transmitter */1 d- |/ p' c" j7 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 a3 l- @7 H! a* A2 RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 t |: D+ B+ D( @" Z' E I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( I4 r* i; o! g3 I0x00, 0xFF);
) G6 h2 g0 c4 X I6 Q$ e
2 o- N4 A& e8 n! q& k/* Enable synchronization of RX and TX sections */ $ Q$ l; P, {7 E+ B( X2 V% U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ w: C. V( A8 _. @( YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& I( R; @5 l4 i/ z/ Q' UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 g5 ?1 k0 t% ^% N; O4 P1 I- ]** Set the serializers, Currently only one serializer is set as( A: A1 u z3 o/ k/ c- e6 ?; d
** transmitter and one serializer as receiver.' `5 g% `/ I$ V$ F Q! O- ~# e
*/ X% j! P6 T6 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# J' p; j0 {" e! eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 ~' t. K# ~0 k9 y' W
** Configure the McASP pins
, `5 B- N6 |- @+ R9 ?** Input - Frame Sync, Clock and Serializer Rx. c- y+ R; N2 w; m
** Output - Serializer Tx is connected to the input of the codec ; @4 U5 \7 T) k) p' j0 \! V1 Z! N: f
*/! ]0 z+ N6 k1 G1 n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 M8 k6 u5 r& V |1 cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ b' {! S% d6 P0 I+ JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 p* w; N# _" i! M" k1 }
| MCASP_PIN_ACLKX
+ c% x4 }- D. G; W V3 z5 H| MCASP_PIN_AHCLKX# Z1 O9 Q& D1 |3 d+ i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 K. {6 b g4 ?- ~2 JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # B V% |0 _* [! L% _
| MCASP_TX_CLKFAIL
' \; M9 n" J9 R' W# Q9 d$ B# ^- E| MCASP_TX_SYNCERROR
; D/ r9 \( U$ v, i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 D0 Y. L, `+ ]/ f) U* [3 |
| MCASP_RX_CLKFAIL
3 h V# I- l/ T! R/ H| MCASP_RX_SYNCERROR & e7 x) t& I. R+ F( b
| MCASP_RX_OVERRUN);
6 C7 J4 ~, N& T" {0 W0 ^* {} static void I2SDataTxRxActivate(void)- J! g! e; y4 C# _% Q M! l; i' b
{
- n( o: f- }( K# f' r& {7 o/* Start the clocks */
) r6 x, G% O! `- LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( Q W* c( d+ o( I$ s* Y$ E$ R& t5 }3 O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 k0 v: B4 l9 U; ]1 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( u( h+ k" T3 G4 m" T
EDMA3_TRIG_MODE_EVENT);2 A& I& R9 @+ x [& r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 c- d3 ~. ~/ G- e& f# D- Q' qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: F+ B# d6 D5 C) p8 v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! c4 z3 |8 n8 F7 C7 R) P# g7 D/ RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ v% C( g5 q4 T: o7 @7 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# I7 Q# t @7 ^2 R' V* o2 }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- e2 p9 y/ ?: V* k0 u/ x# ~4 }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) x* x( v! ^ h {
}
) `) W" F4 r: {; J. I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " I% r+ [- l, N! P9 n$ H- H
|