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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ D" }% C% O/ Z3 u, |2 Zinput mcasp_ahclkx,! u( P; Q3 b( X, ?
input mcasp_aclkx,+ T$ i2 r0 Z3 u! |0 w# b, W5 H
input axr0,
( h+ C0 ?( P; A0 _4 ]( z2 H$ N' _" D# [% f
output mcasp_afsr,
1 j$ Y* T0 O$ e8 m7 \output mcasp_ahclkr,
: s* E+ m7 @/ l) houtput mcasp_aclkr,
$ m$ G4 r: h! b) Coutput axr1,
" j6 N$ ~( o9 j9 u7 S0 W* Q assign mcasp_afsr = mcasp_afsx;: x/ A* W8 L/ f9 k6 G) ~2 |$ A( u
assign mcasp_aclkr = mcasp_aclkx;
6 T/ r. T$ g9 I& M# A" wassign mcasp_ahclkr = mcasp_ahclkx;" H# E$ Z, v& `1 d( l
assign axr1 = axr0;
5 N2 f' v: U& y, h n! c2 e' i1 S* j5 n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 ?2 I, Z7 `) g; X0 T& r
static void McASPI2SConfigure(void)
# n/ `" Y6 J" l2 X8 c) G' G" \{
# v% v o) y6 N$ IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ g2 Z* {! z8 I! ], x+ HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 J4 Q f+ |* t$ G# [ n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 F! V4 `/ e4 _# M) k3 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 w% _" W8 {' s3 a2 F6 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: x- G: R9 ?% sMCASP_RX_MODE_DMA);$ x& f) _, J% g# ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: {- W6 |8 s8 ^) @& JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 g+ g3 z1 ~( V! l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 ^ d5 c" |* R; P. v# L* AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
w6 d9 L+ l+ \# C0 \% @) x( eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - a4 v$ F+ n0 ]; k' s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// h: P0 E$ D" C+ y1 @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" S) y3 e! c' k) CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: a; e, g2 B2 JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ ^' v4 F# B0 d# G1 v/ E) q* I- l4 O0x00, 0xFF); /* configure the clock for transmitter */
R0 s9 t2 s8 D1 o4 i! l2 a8 p$ `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 u) F% y9 w* G; S* uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 N4 A+ j3 F, L" u- v0 SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; G, b- h0 T2 j4 Z$ K9 \
0x00, 0xFF);+ M3 G) P t" } [' F a
. o# G/ M5 t7 H6 J( q
/* Enable synchronization of RX and TX sections */ : V6 `- ]5 t# t; }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 v; }# V, @( Q/ FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% M5 Q6 W4 B( dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' ^+ ~5 s; S l1 h! e( t
** Set the serializers, Currently only one serializer is set as
! J- E' O, g. x3 o! X** transmitter and one serializer as receiver.
1 l, F- i: |7 `& Q6 v( h$ B2 u% N- L*/
# f- j% }' c+ Z# K1 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% `3 I! }* u5 I8 ?3 d( |0 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** ^4 |' i9 h. H; F; V
** Configure the McASP pins
0 l2 r3 D4 J- V** Input - Frame Sync, Clock and Serializer Rx
" J* J/ e4 w. K, q( z+ U- U** Output - Serializer Tx is connected to the input of the codec
1 O: m' w1 X6 R, K*/
4 R; Z' n0 L8 U' ^. i7 n) zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 Y- v& }+ R* q9 M" Y& _/ |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 L; n' Q& Z8 }+ m2 H% j; V2 Q! V% s3 cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& Y! Q; l3 m7 R5 |$ F$ ^& W| MCASP_PIN_ACLKX
( `. f; X$ A- G6 w9 ~| MCASP_PIN_AHCLKX5 b; U' M% K D2 g# M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! n/ y4 w+ w4 c% p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ M3 p, \, X `8 I; y, R& Z| MCASP_TX_CLKFAIL - H$ J/ w- U3 I9 G7 E* z7 S
| MCASP_TX_SYNCERROR" e5 r# `# L1 q) R3 I& k" k/ T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / j, x/ ?* P/ _3 l, z4 N+ A2 h/ p. \
| MCASP_RX_CLKFAIL1 }3 ?( t# |( p. ?* J5 o9 `6 T5 ~
| MCASP_RX_SYNCERROR - v+ n% N% _5 u0 L% P% H* `! O4 Q7 b
| MCASP_RX_OVERRUN);/ J3 B3 n/ w1 M7 D
} static void I2SDataTxRxActivate(void)
) x4 R8 V; E: t9 @{
8 J6 z& E, X" v# _/* Start the clocks */
+ F) f4 J! c ]! e* ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) Z I/ G* D2 Y" \; qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& X8 I* ~8 h$ ~9 |1 g. f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) m/ G# g n& n1 x+ f, K6 e/ t! a" A8 W7 K
EDMA3_TRIG_MODE_EVENT);( J2 }/ b* j! E; l6 r6 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ B* s( f) Z; I5 ^! UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% w/ j: y6 i- E0 E" Y# yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ c/ a/ U( H4 s* u3 O& A" l, A5 [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" ~$ \2 f# \8 ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) p- C$ @& d7 f3 B8 U: R. DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; @' q3 w$ y M' f _/ |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. `2 ?4 b- s4 b
}
* q! U7 W3 s) p) V& _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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