MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
/ ~7 H. E. U( tinput mcasp_aclkx,
$ E9 v( l" H$ A) I6 l; Kinput axr0,

" @* Y! r; I1 C) d5 c6 j$ noutput mcasp_afsr,
output mcasp_ahclkr,
5 a) h; k* F# l; T. @( U/ d0 _output mcasp_aclkr,
- Z: G& P* Z! k% Y, [- ~output axr1,

assign mcasp_afsr = mcasp_afsx;
2 M# P; {" {" V1 `3 F6 U2 dassign mcasp_aclkr = mcasp_aclkx;
' m& a' t$ H+ q# Dassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

7 ~) P* ~$ y- d- D3 h

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
! d) y8 {4 Q5 q, d8 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
  ~7 T% C; ^  ?- i2 u" |4 b  ^& jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
2 Q3 }2 Z1 G! M, y3 N9 C* h$ wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ I. s- T5 R- A% R5 G; bMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 q$ W/ l. h! k, X3 qMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( w6 w& E6 _& @) K0 `# zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 f  S% V5 C* Z- @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ n( L8 b& n+ rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 L- E! b0 B+ G3 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
+ d9 m+ G' f# {+ V$ b! [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# j2 A- W$ g& U0x00, 0xFF);

/* configure the clock for transmitter */
: y# o, j: N- W7 L" D; oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 s  V; L' |6 }" o' ~4 L. f3 M" yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 L: m. @$ i: r* }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
. ]9 J1 v3 ?' ?+ x# V7 ]; dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
4 W. o6 \, x2 `# m*/
/ j2 b; G& F4 A& g6 J1 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
5 {8 M0 m) n$ `! p** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' ^. Q  V/ \' x7 {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# t+ C( u3 }8 \3 J* W/ E( d. z$ y| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
$ c1 z; }6 u* d" }8 f4 `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" v4 ~% Q+ B$ E5 y| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. z! O: V0 I) ?* {: t0 b| MCASP_RX_CLKFAIL
& C( ?% T8 d5 t6 L7 V4 `| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
% z9 p5 V$ R) w/ k}

static void I2SDataTxRxActivate(void)
+ ~0 N0 C% y# T6 A+ F) L{
  U5 \: L5 s9 y4 O/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 `- Q6 y, ?' y3 g; yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
3 A2 X5 l0 S1 o9 ^+ BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) K' _( G, _1 S2 E/ DEDMA3_TRIG_MODE_EVENT);
, S$ G% o" D) @) q, H% O  oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
* o+ N! E0 T, C6 u4 |, A0 _* \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

  F0 V! a+ Z5 D/ p' K1 s

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

& w- u) o; a5 A7 E4 S2 J9 k) T* f