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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: Q0 K* n. l. A, @
input mcasp_ahclkx,4 X* M7 ?( ?6 q; P2 f
input mcasp_aclkx,
8 Z( w+ N! l- }9 n: R, r% e. ~input axr0,9 s" ^ o& ~6 w+ D+ i2 ~
+ b" f! f$ z) {output mcasp_afsr,4 }3 c- r: f$ C7 W% T$ Q
output mcasp_ahclkr,
; u& s. B2 H4 Noutput mcasp_aclkr,: L0 G) h" q3 X5 O- J# ?! |
output axr1,2 b+ M# G# l+ n! q/ M* h+ r7 `
assign mcasp_afsr = mcasp_afsx;
' ^" m4 d$ W" t: ^' A- z0 [assign mcasp_aclkr = mcasp_aclkx;" y1 \- y' T+ B6 |0 ?( H1 y' h
assign mcasp_ahclkr = mcasp_ahclkx;
5 Z" m1 `/ N1 d: Kassign axr1 = axr0;
I$ B8 v! V! A& y) Y
: s' ?4 S$ M* B f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& [# I8 g2 H7 {static void McASPI2SConfigure(void)) c0 k5 `# q3 W0 p; |
{: W) r) o8 I! e; O* i7 m* _8 Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& B2 u( u5 v6 z, H) q% lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 _+ ?* Z; k/ d" j: TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 y* S" ?; F8 C1 B! h/ M, X& I* DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' U$ u) D* U0 u/ p: l0 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 z" x0 R$ T$ H2 y9 P1 \- a/ h/ K
MCASP_RX_MODE_DMA);1 f+ i$ r( a: g$ W- w3 W8 Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" L1 Q4 [1 ?1 K% K s/ DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 G y* x2 @ r: @. o/ u4 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 P! w1 f6 m+ U A1 s6 n, l5 uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% v6 T6 K9 K, F8 U4 ~6 V( X& i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! h' A |' t, z# E+ k: BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 P2 }* e* M# EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: v/ E4 T# Q. { KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 B$ W7 c4 K8 `1 J2 Z$ f6 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& Z+ f% f1 Z' [0x00, 0xFF); /* configure the clock for transmitter */
1 _% l( i( h u, l- L4 ]' FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 H6 e, e# i a$ o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- J& C3 ]% w, w0 x3 k9 B- P2 v/ u+ W! [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! ^8 ?) D+ {# Q/ ^# S0x00, 0xFF);
8 m4 r6 x7 e6 R# X
- i$ B6 B9 {/ B0 W9 o% U/* Enable synchronization of RX and TX sections */ $ h% n+ D; q8 S% f: |7 F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& b5 }% A, g: t) rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ w7 y3 i% p: U, z7 R; X* E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 w: ^% {0 P4 l
** Set the serializers, Currently only one serializer is set as$ G; a8 R/ M6 r! ^/ t
** transmitter and one serializer as receiver.
, t; T2 K% v. b! Z' u*/
+ x+ G1 h5 b0 m. Z4 j+ Y- F N. v0 |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ B; B# N+ h( v v# hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' M+ ^ ]( D: d% W0 \** Configure the McASP pins
/ L0 k; q- q3 k/ a# ^7 |** Input - Frame Sync, Clock and Serializer Rx
+ s( g8 M$ |& F6 e( N** Output - Serializer Tx is connected to the input of the codec 7 f: A$ ?9 P2 J( X9 j
*/
, L2 E2 C& d3 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& T. e: _7 O9 U' M0 g' h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" ]' Z$ Y) o$ p* c- I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: g0 j+ b& b9 ~* F" W0 w
| MCASP_PIN_ACLKX& l _* M0 J- K
| MCASP_PIN_AHCLKX& {; |3 n& E( o) e, C# J2 L, b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) m5 d+ w" B3 D+ fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ n6 G. S |8 Z! `% }3 d. I e| MCASP_TX_CLKFAIL # a* U, r0 B% w# a: F! ~
| MCASP_TX_SYNCERROR
' i7 D/ u! L5 Y4 D) b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* m$ u1 E4 S; s8 ~. E" t) `% Z| MCASP_RX_CLKFAIL
2 L1 o0 |, o+ q$ v| MCASP_RX_SYNCERROR , J3 ^0 Q( E) M8 h
| MCASP_RX_OVERRUN);
0 b5 b) {; R* A* g} static void I2SDataTxRxActivate(void): ?5 |6 ^7 N! Q2 z
{' N6 s1 @% J$ A' \' f( p* u8 p
/* Start the clocks */2 x' E3 l% Z4 [2 `4 o& E6 T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 D7 p1 ]! X2 S1 @" aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) V( `8 l2 {& \$ H, R5 j% o0 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( ?) J/ b2 `9 |# a B0 s F! E
EDMA3_TRIG_MODE_EVENT);% R0 b) X4 }. x8 E# W; S8 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : R! _. \' R* a: _0 {- L4 x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 S% ~5 M; @. Q; rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. }" Q# u+ |* d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ M1 f7 a. g( H! w* j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- F- V, ]* M) ^9 `7 nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 m' e. F) z3 @9 C# Y0 Q/ a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); b7 u2 l- p2 V ~$ W
}
2 v! J0 o) h# l& T1 o" M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' \0 t$ ]% D$ W" m/ O
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