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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; F9 N S5 [/ N8 Rinput mcasp_ahclkx,
* N' A Q% \- O% W) r6 winput mcasp_aclkx,: e3 }7 v% _1 |2 J z) e# ~
input axr0,% C: F6 R) E$ x0 ?: x2 y1 P
: N" h" w: J; t9 z8 O ?output mcasp_afsr,$ S: w; l6 b* N& u. @0 \5 |
output mcasp_ahclkr,6 v0 P( N$ N% m3 k' _0 f
output mcasp_aclkr,
: a: q9 S+ B1 C! w3 C3 voutput axr1,: U3 `3 J O6 O0 |0 @7 r8 e+ j% c
assign mcasp_afsr = mcasp_afsx;; X+ Z+ t2 D- x$ S; P& D4 p
assign mcasp_aclkr = mcasp_aclkx;
9 ?1 F8 h. g x& Jassign mcasp_ahclkr = mcasp_ahclkx;4 U+ {' r4 Y. d5 h) Z
assign axr1 = axr0;
& [4 u9 H) z5 v9 I r4 e! Z/ K4 N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " B4 C' ~: I" Z/ C. B5 H
static void McASPI2SConfigure(void)/ n, E$ Q& F0 J; B6 }
{
5 a. V; I" q. @, C, N) uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 V0 a! n: T3 c% Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 [" `) A" x+ K. Q& |' G0 ]. }# RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- ^) K2 f2 s- b2 g! l" w9 h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* `6 A2 R* F, ~$ k) }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: h8 x0 M& `" S3 M# @+ y1 l. qMCASP_RX_MODE_DMA);, J, ?% g% A' }7 `* S8 Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 G A6 p: M; H9 m0 [" j9 M9 VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 y) Q. {3 i) {8 |- I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 b) M. M) u6 t! U+ u1 B1 i# ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* ^& ^& G. a3 ~. d1 m' f8 ?% ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) I. o7 S* T/ ~9 } F: Q4 ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. U/ O* ^) C, g7 ?4 _6 c' ]/ V, V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, p3 p4 s; y% N% O7 M- E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( N- L/ ~- b c% ?0 j' D- h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ M4 f) [" g* M! P# a: n$ A0x00, 0xFF); /* configure the clock for transmitter */3 s' K, E T# n- L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 [1 e6 F; U/ q8 e/ NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 F: z2 ~8 k5 B/ N R" s! yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: X9 v4 C+ z6 U" t( H+ Z ]
0x00, 0xFF);6 b( }4 j, V4 U& b1 e% c7 Q; W& t
. v# I" j/ n" [- H f
/* Enable synchronization of RX and TX sections */
( u- N: R9 L# X, j" dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: b$ s% |8 ?, @2 p( mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 H" j7 N5 ?9 a' m/ V2 t) H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 }3 ?8 |, U. a/ _
** Set the serializers, Currently only one serializer is set as
. y* a( K; q7 f8 g( W W** transmitter and one serializer as receiver.# L# J. U% H6 @ G% Q0 S# J
*/
2 v# y/ m0 E/ ?" j6 tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ R6 u6 q" }5 j) iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: l. d( v; w b: k I( ^
** Configure the McASP pins - v+ o4 i7 d- \7 G" s4 x
** Input - Frame Sync, Clock and Serializer Rx* Q2 c. C9 q, s( P# S- l7 z+ w
** Output - Serializer Tx is connected to the input of the codec % i& U9 x' z) _& e% Z' {3 f
*/
, z4 e! m; q5 a2 X0 O4 ^' lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 l- \- U3 A+ a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) J" l, @% O6 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; b) s5 m) f$ Z) \, `
| MCASP_PIN_ACLKX
1 T3 g, e5 T+ W& i| MCASP_PIN_AHCLKX4 v/ L( N# z$ K6 m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. h8 I/ N# m4 i: x) a. c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 g( D3 v8 a6 t$ J( }# q; D* |
| MCASP_TX_CLKFAIL
- ^" I& o8 |* i9 w1 v| MCASP_TX_SYNCERROR
& {4 k4 p9 d8 A0 y% E" E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
P5 I1 H4 b' C6 ]| MCASP_RX_CLKFAIL# N4 p( H4 T- ^4 ^. E8 G
| MCASP_RX_SYNCERROR
1 \5 W2 P" G; A2 G/ b$ E2 _6 p| MCASP_RX_OVERRUN);0 z0 E0 v* x* g! y- B. E6 z
} static void I2SDataTxRxActivate(void)
1 K2 ^* q ]4 t{
5 C& G7 r& I& c7 M/* Start the clocks */
+ F. n, G; O$ }4 v& XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ m- X3 c/ s% ]2 {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. E+ J" y! J5 @! o8 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. x: T( @2 Y2 U3 X& |9 @EDMA3_TRIG_MODE_EVENT);
! i9 X; f% G, [( k$ N, Q* ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% `; \. Q- u. F" H% [. ?+ ]. C8 R. ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! Z4 L" {6 K1 F4 h9 t7 F, x* }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 X; o' R0 T/ V: aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 ^( g0 J: I3 D# O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* l( f) n2 Y9 @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 r: N# }* X0 a# h) x, y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . I6 A( o8 ?3 B7 l4 S
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