MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
! w+ F9 R7 T+ }. A0 Pinput mcasp_ahclkx,
( F( N  X7 a- r. W) x: x3 k* {" einput mcasp_aclkx,
. i/ z2 I1 R: K# ~input axr0,
& P9 R1 ~; Y% m
output mcasp_afsr,
output mcasp_ahclkr,
! c7 k9 a- t* routput mcasp_aclkr,
output axr1,
4 P9 o# W" v8 ~" N$ O

assign mcasp_afsr = mcasp_afsx;
4 a( r6 J$ A1 Z- Rassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

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static void McASPI2SConfigure(void)
* ?8 c/ I6 P2 ~" b/ P$ c; p  j{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
4 n- q% `4 [' ~* L5 XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
  ^# F5 N& I4 C9 o: A! k) n; OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) H  w* e8 s- |MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ [, y2 }: @: y  }! U# EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& x, f1 W4 n) Z* ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' @4 O) y& I" }! E6 DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' O1 N0 }0 z4 s: O; ]9 c* W7 kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) S3 k5 \. V. y2 fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
! _4 D6 w+ T+ [& _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! H+ L/ ^6 E5 G/ J: |9 y% KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 f. S4 Y7 k4 z! EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

' c) G2 b. X+ N& D/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- W- i0 |) H; OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
5 W* e. b, e3 W*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
: t% A. u9 S2 B7 z. `/ z2 k) ?** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ v: o) F; m8 p. n" s1 C1 HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 `, r$ }" L/ l| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
9 p" U: d7 c" l, X| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
" ?9 r2 j4 x: |4 h7 w  gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( `3 d3 B7 h. i" l+ [# i6 q  b| MCASP_TX_CLKFAIL
5 {& E. _+ _0 \. N, e7 J: E| MCASP_TX_SYNCERROR
: ?1 E/ H% i+ M. c3 T' `( z| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
& y* p% g8 |; f* N+ n7 O6 j9 W| MCASP_RX_SYNCERROR
8 p0 ?6 i# Q/ h| MCASP_RX_OVERRUN);
& ]7 u) h! P( C  o) N" h9 z; G# Y: m}

static void I2SDataTxRxActivate(void)
5 F/ S  A% {  Z! H- S{
2 ?% l# v" g% M  z5 a- |" Z* b/* Start the clocks */
& M" K: \! f- Q9 `; yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 F  W0 G6 t# `- L2 e7 hEDMA3_TRIG_MODE_EVENT);
7 d9 K' V4 g9 W% l6 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) \( u9 P5 M& c. V. J! b7 q( U4 \% HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# H; Q0 s, E: T7 b5 \& lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
( ?2 ^1 A' B# s3 M+ vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 F7 I& j9 Q3 }9 ]0 v9 P; ]2 a  K: gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

1 `# Y4 _! Z4 E5 s

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

7 l& z$ y1 g5 F) \