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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 a( O C0 l6 jinput mcasp_ahclkx,
. Q# P* w& W t. g! s( C1 Linput mcasp_aclkx,( Y0 ~: N/ C! t% G" B" c' h* e
input axr0,4 ]' y+ v. Z3 q+ b, Q
# p$ F! C; _7 l! w" s# B3 d" j
output mcasp_afsr,
! Y8 C! m2 R( qoutput mcasp_ahclkr,# Z: Y* M/ v4 g
output mcasp_aclkr,
3 B6 c8 r' R9 J7 `output axr1,
! r) L- J' u; N/ k$ n% U assign mcasp_afsr = mcasp_afsx;
2 X3 O9 p9 l3 Y8 w1 `assign mcasp_aclkr = mcasp_aclkx;0 ]2 N5 n* w$ U7 j: S: R
assign mcasp_ahclkr = mcasp_ahclkx;
& j4 q; ~ M/ J/ [* w% b; n# |+ Dassign axr1 = axr0; : ^+ r4 g" }# M2 m. k. ^
7 S% K4 Z2 S7 O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; o" |. g: [5 R) I1 Sstatic void McASPI2SConfigure(void)
7 a: f t, n4 p$ V( K6 x' `{
9 I; c% q- e$ QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ H- L) N% F2 @" f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( G7 p+ {1 }7 [/ e- XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ p0 [/ m! H7 r4 GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! a6 n4 E3 ^: J% ^% Q+ d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 b; h& g# h( ]( M4 M T5 zMCASP_RX_MODE_DMA);
6 n9 \6 W ?. @8 `9 F' rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; B; n4 n2 M: w: d- nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* o* t8 Z" {; xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( K/ |7 ]' |* K5 L* C& q* E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 A" Y* ~7 ? } x4 h7 [% d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 H9 Q1 b( Z! N wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 J2 R+ X/ c m/ N' M5 N4 Q9 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ u& X& j0 W' c# u" U4 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 t" k& J3 g/ r" e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 t5 v: v- n% \5 O* Z4 L( R n! U0x00, 0xFF); /* configure the clock for transmitter */# T% O4 C6 z* `, h. R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' [% r1 Z9 W0 m' QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) I' p0 x# f6 j! J7 [. nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 r2 w; G: J0 K5 K8 F- a
0x00, 0xFF);
. h5 a" X4 A9 A" K% Z
7 L8 L4 u8 w3 P! @* ^0 s9 Y/* Enable synchronization of RX and TX sections */ 0 x$ `5 d( ?* q# p3 H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! g) N$ I; i! q' @- h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ b+ _) Z/ n" ?* T+ D; cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% U! `$ V6 y/ |8 n k
** Set the serializers, Currently only one serializer is set as6 S$ y, h* @! q0 A" F4 Q' K1 s: f
** transmitter and one serializer as receiver.) q) [! D& r, |% H' ~
*/; ]7 x; z. G# ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ a8 W. \: Q: Y2 z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ y) f& l$ B8 _, u" _4 R
** Configure the McASP pins
" Y' `: x4 q2 r5 ?+ a** Input - Frame Sync, Clock and Serializer Rx6 x7 \$ F3 K f
** Output - Serializer Tx is connected to the input of the codec
# m j7 Q9 A7 K. `& e*/
G6 w8 H4 L+ dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- o. a1 N3 E7 b5 h9 \+ q8 `5 e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 E& y3 g) M! W7 N( I( m5 }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: D: {+ E( T, r& l
| MCASP_PIN_ACLKX" b; E3 S# }) o1 g7 e
| MCASP_PIN_AHCLKX
0 L3 Z/ P& J# }' C* N, \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% P( ], {! R# `1 h, ?* @3 S0 i$ ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % `: `5 p. Y$ O9 |) M& y( c
| MCASP_TX_CLKFAIL
) v- J3 |6 e8 D6 O$ t) O( U/ K| MCASP_TX_SYNCERROR
/ Y$ q. U# i6 S' d* U# Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( |9 T( K! y+ J9 E% Y8 s| MCASP_RX_CLKFAIL
+ ]3 x, C% I4 \+ v! ?. I| MCASP_RX_SYNCERROR
/ a9 f: w- I1 D& ]| MCASP_RX_OVERRUN);6 B8 ]# H& j; m
} static void I2SDataTxRxActivate(void)' ]# ^- U- J) X# z5 K# u* J
{5 h6 T* D! G7 Q* t( P7 O3 A% |
/* Start the clocks */
4 ^- G/ C3 t, k0 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& l+ `- A# @6 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 F+ f* ?& k! C/ O7 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. R* D: M: J) ]% j5 ?2 x$ i
EDMA3_TRIG_MODE_EVENT);6 l2 Y; ?6 ]( K' r! h( z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 @7 d$ G4 V( F* U' L# @9 zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 Z F( \! Y4 j+ ]) ]7 Y: l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 X% }2 G% k7 N2 Q Q5 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) J2 W2 }/ ^, @( K. m2 P9 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 Q) `5 h) k* N% ?% `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% B$ ~# `# y+ W" E3 t, t: t4 `- |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% o. n5 N/ [: Q2 c% ^" c$ |
}
% \" P( x' F$ U7 C: G/ e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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