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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# X, @0 P/ [$ Q$ T8 T; ~input mcasp_ahclkx,; c3 i' y0 ^/ X5 W V9 t9 t
input mcasp_aclkx,3 a' s9 A! M7 t2 t
input axr0,/ I$ e; f Y" |0 b2 m
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output mcasp_afsr,, t1 f9 K5 @6 W6 R9 v/ F9 F& V
output mcasp_ahclkr,( k0 q% {4 \2 r/ e% U0 }% z
output mcasp_aclkr,' V4 }. C' t' ]2 E, t% {* z- q* S
output axr1,' [6 G( I6 d4 n8 K$ h4 F, y
assign mcasp_afsr = mcasp_afsx;- L. D+ |( X& t$ r, D. H
assign mcasp_aclkr = mcasp_aclkx;2 K ]' {$ r7 [/ k" k
assign mcasp_ahclkr = mcasp_ahclkx;
0 V/ j; W- `/ ^6 |( d. Bassign axr1 = axr0; 7 O2 \6 d. `; z, K& w5 ]1 \
, b4 _9 E; ]$ b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! W3 q" l4 F$ [( N& d; C/ u3 a0 w
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' _' m) T' N" W, R: KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" [& `1 G8 e* M7 A; k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); X6 p* }6 _* o0 M4 U3 Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 E C9 K* ?# q# c3 j& w3 f% oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, g! g6 u! _8 ]& W
MCASP_RX_MODE_DMA); p2 U+ u/ C- u$ ~7 [. C# F2 D+ A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 L3 n9 K+ X) W4 `. T5 FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ w# B! [! | j( L7 Y+ P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " C( c) K1 U& t; f9 P& h% ^9 l" y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 ?. o5 J) v; T- o* M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ ]1 K8 u8 s0 L! }$ ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 C. k7 |8 ?# {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
X x5 E+ m Z( w3 QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 P" \: @$ R* I3 c% Y+ q/ hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( f9 v8 U# s6 |* _0 T, e; K0x00, 0xFF); /* configure the clock for transmitter */7 \% y [5 ~0 A8 Y2 t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 [ T( d2 E3 g0 v) N" t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 ^2 ]7 {6 x& j" N% v( h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 ~# M: f5 b. {0x00, 0xFF);% n+ [) ^( d, _! M. f* K# m; w" w
6 M) e% h" E1 h. s/* Enable synchronization of RX and TX sections */ 2 i3 l% ?) N8 I. l: n4 |7 ^8 X5 ]8 B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 c+ N+ i" S3 R2 P/ [3 tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 K& X) g' [3 J5 ?# X. b! d: H/ ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 B3 t" A4 F4 o. ?
** Set the serializers, Currently only one serializer is set as A! l% t2 E" F- g
** transmitter and one serializer as receiver.
J. Q' ]4 N/ ~! V9 ]# n*/
* D. @0 O3 F' c6 M% i6 OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' c3 c3 U: Y/ d- f; @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) `5 V. }; x0 Y; O. g" o
** Configure the McASP pins $ a) g( e# w, @/ ]9 {0 P
** Input - Frame Sync, Clock and Serializer Rx3 q) y; m( R. N5 i
** Output - Serializer Tx is connected to the input of the codec 5 u# F$ M( F4 Q& Q$ Y# e- L Z# H
*/
; j/ D( s& i3 P* y- h1 G _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 ?+ J' S$ q* `9 Z: a; K4 @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. ~% K/ V% r; D. {; H7 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ @- Q/ F9 f& x/ y| MCASP_PIN_ACLKX
- y1 y' ?( k2 @: z' c2 G. j4 f: _& \# m| MCASP_PIN_AHCLKX
& g* r6 i- j2 t5 U& I* M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 p# n3 @9 Z* j# N9 j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; J# e4 ?0 _! i# p. A' || MCASP_TX_CLKFAIL 2 H% R# I- F# l+ [; `
| MCASP_TX_SYNCERROR
; D. h/ }0 _# @; E7 |/ u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - Q! K0 Y6 R. k7 F1 n. y
| MCASP_RX_CLKFAIL, e/ d7 L* J( W/ i
| MCASP_RX_SYNCERROR
5 }; T" s9 z' w3 H$ P6 K$ A6 T9 p| MCASP_RX_OVERRUN);' M$ Q2 A7 D8 D0 {$ e; d- P4 t$ b
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */7 N3 I8 R4 y8 K( l# Y( U6 j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) J. E+ X M0 nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( |/ f1 S$ I& M0 b( s/ wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 G7 P# w3 U! q0 c, x' s
EDMA3_TRIG_MODE_EVENT);
" A* t0 o% t+ a# eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ M' s) t) M# { l R5 P6 YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 R% ?! O( @, B+ I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; X4 d6 j/ A+ h8 ~' tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& G3 \0 [7 f, C# rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) R( p* K7 c2 ?' d; w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ x) x: r6 h n! FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( Q1 y- A0 b% [
}
3 X* K3 _: W! D6 j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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