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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' s6 X H8 p1 Y( B* R8 binput mcasp_ahclkx,
: R4 H) w; k1 w" `+ T4 P( zinput mcasp_aclkx, m7 J& m- {2 i6 D
input axr0,) \# @/ x, g4 {8 m% r
) x+ f7 ^0 Q& D. E# V$ zoutput mcasp_afsr,4 L* Z! L- I/ f4 z8 d9 A& ^; Z! ~0 E
output mcasp_ahclkr,) T/ ^9 A1 t; r& P T' t6 O/ {0 N
output mcasp_aclkr,
- C) m# W! N/ c: W6 Zoutput axr1,; t0 H! y7 N s6 u9 f9 W6 Q
assign mcasp_afsr = mcasp_afsx;
, c+ u1 d# N) J* @( _; r+ Bassign mcasp_aclkr = mcasp_aclkx;4 R' N0 @, Z; b0 w4 {. E( ^
assign mcasp_ahclkr = mcasp_ahclkx;
" d+ Y8 Q+ w2 L& _assign axr1 = axr0; 5 p; N2 s9 v/ h H+ k) r, a0 ]8 t
) d& q; G! P! l/ f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 X d9 Y+ C! J, A* M3 _static void McASPI2SConfigure(void) V" }. G# S# _- z4 O% v
{
3 P: Q7 ]. ?5 v& _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: S7 k. T8 v; X0 e: p cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 O0 e7 m8 h2 x s: G) ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: G# w" x# L: V( z6 V4 yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 o5 |, O& v& U! wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* Z. U: z) }$ B6 N7 N" P& D4 N7 G
MCASP_RX_MODE_DMA);4 P, i- r! I! B3 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# r1 p5 S$ }, T2 [9 x3 G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 c* Z$ h' ?; uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 Q5 a& i( }' x6 [6 D; t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 I7 N% Y) Z" e {4 G3 l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 J3 r* U* ?( J: }8 S* p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& M8 }$ f4 i7 e0 O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& [( @1 K6 f( c, L1 A) B4 D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # n- l! c% s, d2 ^6 o/ I0 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) |# \- b8 M+ Z2 z0x00, 0xFF); /* configure the clock for transmitter */
$ J& S9 @3 Y) e, n5 uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, R+ a/ k) T* [' _8 y+ R/ U+ a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , m9 r2 t9 V. t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- q" W' G" [5 s+ M6 }" e0x00, 0xFF);0 U7 ]& u, c0 L3 a# Q/ w0 F
$ p2 Z6 u B# o, w; T9 H8 F- Y
/* Enable synchronization of RX and TX sections */ 7 t3 d2 d- M* F# B% X8 V* Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' T i( r+ v& W9 r7 y8 V+ g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 |1 }3 f' J) ]" j4 q& w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ `0 ~# W& n! u4 \2 m** Set the serializers, Currently only one serializer is set as3 K! F) z) b* y# T) W5 V
** transmitter and one serializer as receiver.' I+ x+ i" J, B7 O
*/* U2 J% X9 C4 z' n1 L7 n4 m9 |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( T0 G: X! h! A8 [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: N* ?: ~$ X. M2 `( X3 _( j
** Configure the McASP pins
5 X7 `7 G9 |) I' l# j$ P** Input - Frame Sync, Clock and Serializer Rx
" I1 o( S& @. _1 x4 S2 W: q** Output - Serializer Tx is connected to the input of the codec ! r- ~6 k+ z0 w1 _. z% o# d
*/
% g9 H1 T4 r1 T7 a2 |1 sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 I- `7 e; f. D4 M# z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# p! ?% D+ L5 g. _6 O" tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( c M+ C8 {: A| MCASP_PIN_ACLKX
q! u6 l; T: g; C3 @| MCASP_PIN_AHCLKX9 U# C/ j+ `) `5 j0 }( m" F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 e$ d) h! i# u; B. ^% j- u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 X/ R! y5 @) n1 V' d# O' }5 k; s| MCASP_TX_CLKFAIL
; ]' f# w) ]0 J# m| MCASP_TX_SYNCERROR
- h5 m/ F9 J H' N7 c0 D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 r7 @( X) b! y- n4 |' U| MCASP_RX_CLKFAIL; P$ X+ J& G$ { k! [
| MCASP_RX_SYNCERROR
3 S8 U* [( e$ X| MCASP_RX_OVERRUN);! z. C: K9 l' Q- I6 R
} static void I2SDataTxRxActivate(void)
) x% E5 V. I; E2 Q$ L* E{
0 v$ g( S" R- B/* Start the clocks */
8 z7 n3 O* e' g: O! pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! X; c3 I' }' n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 K; S( T% X4 I: F# E7 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# S6 D0 U7 D! ~, r: S& Q
EDMA3_TRIG_MODE_EVENT);
. d3 u ?" [, W. ^( B, @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% M) H* K' G) J' LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* c9 {- |5 K: f- j* P) eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 n0 F2 \8 g' I ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ m) x% z' q% ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ A4 J+ t% }' f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& X# A: d$ h- _5 Y/ W3 u) Q9 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& ~$ i7 i3 B) x7 M1 p* p1 S
} $ w/ y; p8 c/ B2 W5 H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + \: ~/ w. Q1 D% K+ n, M" n, N
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