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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* S. `6 H8 o" @4 S* P) G$ A# r1 b
input mcasp_ahclkx,6 T# @0 b+ J% ~- O# ?( m
input mcasp_aclkx,
$ y4 ]1 i9 Z: |# c' K; e+ U* }input axr0,3 C5 ^0 T& c# B3 J2 E+ Z
! h2 @# P' @# s2 Q5 [5 g' z: T+ {
output mcasp_afsr,
7 t+ C& p! U; M* z* ~* H+ q' ?output mcasp_ahclkr,3 d4 t" K4 E$ m
output mcasp_aclkr,
, e7 Y+ g& s" ?! L& t* woutput axr1,& S! i5 C+ t+ ]) H5 }
assign mcasp_afsr = mcasp_afsx;
]# _" x8 E9 y; ]5 Kassign mcasp_aclkr = mcasp_aclkx;
, t4 z, H0 u X( H& Q* p2 @6 Yassign mcasp_ahclkr = mcasp_ahclkx;
4 H/ X6 D: K Hassign axr1 = axr0; 3 j, {5 u) b3 s- m
* z; y1 I5 v$ H$ r' {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' A3 k& Z! M5 e$ X8 E- v3 Mstatic void McASPI2SConfigure(void)
0 ]" [4 a8 F+ k4 I{
6 U3 T! @# k9 H2 [4 O: H/ AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) T; L5 k. I1 V- Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 x+ ^6 y' P" {7 W5 f7 w' R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' K L- e! S9 `$ U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* b& |7 m; _* G* c# D: P- h* NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 `" _# `) i) w8 {! e6 K
MCASP_RX_MODE_DMA);
. @3 d7 K9 g |" JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 Z# C) y. B" G- w% t0 n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ H, m4 ?* s. }: k6 KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 N; k6 g9 M5 J1 N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 R8 c$ ]& |) m WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 O; I1 ?$ x o$ KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( O9 d& |& [! m+ F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' `. S' q. Z. `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 t: |# _7 {* h0 lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 E. r# I% t# R; y
0x00, 0xFF); /* configure the clock for transmitter */
( U) |2 M6 U& H8 t9 JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% W0 T1 R# Q9 d0 \1 A; g S: |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( S. J- ]" c0 K9 D( ~" r2 n$ V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* }9 b- K1 t2 E+ G n* P0x00, 0xFF);
$ |' s+ Y2 ?* u8 ] V" N, J. r: N- l
/* Enable synchronization of RX and TX sections */ - B4 M# s) z; I6 s5 W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, q5 Z0 M P. s: L( pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 ^6 Z" U5 w, V+ s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 h+ R- e/ v( W+ y& d! E) I** Set the serializers, Currently only one serializer is set as8 T6 V- V9 `. v6 `7 u
** transmitter and one serializer as receiver.0 n& U% ]0 x' r, }" D% S ]- Z
*// Y' ~7 R9 M1 C9 Y" Q; |6 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ H# H5 m5 T x5 V- [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% w# c1 s, b3 U6 N. ~
** Configure the McASP pins
/ A& Z+ u' v* X3 m; I** Input - Frame Sync, Clock and Serializer Rx6 p0 X# n! H6 w9 ?) t
** Output - Serializer Tx is connected to the input of the codec . r7 K. a: ^) |) c
*/
% B; l& ?3 l* j& u% ?! VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 z, ~) a" J% v' j, t; G2 z8 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 R' R+ _5 T7 V$ V( H$ e. J* ^5 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) U, |* M- J$ Z& K2 O2 `$ C
| MCASP_PIN_ACLKX- [4 T: K; f" d$ ], { T
| MCASP_PIN_AHCLKX
1 ?# h) a+ {" o/ z. z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 ]0 o9 y3 `! P/ _ BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - ?2 ~! l: o" a
| MCASP_TX_CLKFAIL % _/ u$ y- C* D! t% H
| MCASP_TX_SYNCERROR- l! q8 }: r) V5 p+ I3 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ B% r- _$ I# Z0 K& g! D
| MCASP_RX_CLKFAIL7 U3 U, o5 r5 z* t
| MCASP_RX_SYNCERROR
0 v) p2 d0 ?2 b* n" y7 _| MCASP_RX_OVERRUN);9 r$ `/ c: g& D
} static void I2SDataTxRxActivate(void)4 Q1 h3 f* X7 ?2 Z! ~3 g. ]
{' \6 p- X* s- B3 N# |
/* Start the clocks */
3 d5 K7 G6 W% D( BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* }* y- e, B+ P( m6 X7 m3 a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; C& [0 y+ S% OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# y8 b" q2 l7 n7 K
EDMA3_TRIG_MODE_EVENT);/ z& O; G8 p( d Y6 a' y* r' N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( X# t, ^2 n7 p! P: L( W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 ^. B8 ^: x5 s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 Q, F$ p3 ~7 s1 G1 q* ]; tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 M* e$ n& f; M: Z0 bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 {1 L% I+ Y$ b% J: IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" c& Q, o! F# f1 U; m5 @7 R% c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# I: b, E$ w" x}
# _* ?* w2 ]! p9 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 Y8 p! b: s8 k0 A0 b6 J( V5 ~
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