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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ q2 \" i( ?( u& q) ]
input mcasp_ahclkx,
0 n) y6 y/ | w9 U) x B5 v% K4 Cinput mcasp_aclkx,* h* V; i& s* {& W( @, a c0 L
input axr0, h1 H: W) E% r5 f- M* o# u7 R4 i
; r) o; u; g }$ k4 F+ r- F9 N* J
output mcasp_afsr," x; {6 _, j8 j P
output mcasp_ahclkr," x3 A6 L2 c; q6 T0 z
output mcasp_aclkr,0 Y' ]0 G+ {2 s
output axr1,- k( Y: `* S- O( s& o4 I
assign mcasp_afsr = mcasp_afsx;4 Y- P# \( W: {) o7 E4 B8 a
assign mcasp_aclkr = mcasp_aclkx;
8 W+ d" g5 q/ y; Y& Jassign mcasp_ahclkr = mcasp_ahclkx;
: B% C- ]$ J# P' f9 Wassign axr1 = axr0;
5 }8 |3 Y' b2 \0 x+ m" s3 }6 d
* r# H+ G1 V7 s, B. }4 Z& W2 Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ x4 G/ o* |: c: w q
static void McASPI2SConfigure(void): b+ I5 Z; X) e; [' P
{5 {7 l8 K! N U) j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% ?* c* J3 A. n! B! j3 g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 g# Y) t0 @+ @% EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 T3 L# c& {( G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ [$ u5 h2 i7 Y# H9 E2 ?. y7 [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& e6 R# q# c b+ O1 p' U* V
MCASP_RX_MODE_DMA);
- `- o" _0 k+ ]& T, l2 BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# ^8 N% I& i6 \+ Y/ P! \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. ~/ c4 O2 [7 c. J% B. k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " z4 B5 |( D# O7 A4 f3 E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ ]) d2 x7 |4 u5 _( ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; r9 n+ l/ y/ W% Q; p0 e% S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 ?' v* c2 `$ V9 v- F' K! JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 H8 V, s& ^ D# {* U+ G0 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 G7 W ~2 z3 ?$ i+ C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ G- G- e7 |+ J4 Q' P( |0x00, 0xFF); /* configure the clock for transmitter */6 @2 g" F4 y1 P1 E. k% t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 s$ m& x3 Y/ d& ]' Q7 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; Z9 W! m7 p5 [* k7 v$ I6 r6 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( A% Y# `& B# x' H& Z; V
0x00, 0xFF);
5 Z3 A( T, |6 k' V4 Q5 N5 R# K. [6 l {
/* Enable synchronization of RX and TX sections */ 8 k% ~; c! B/ E6 b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; D2 |' b$ U( j# z$ }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& _- A; h- K2 U- Y! N7 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% B2 f0 G* }/ S) A: h" L' k' F
** Set the serializers, Currently only one serializer is set as
$ E& p0 f. i! Y. Y5 ?$ N9 q** transmitter and one serializer as receiver.& |5 r' I, _: P. G. ~
*/$ i3 e( w0 Z/ M/ P- q! f, [/ t- q o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& {" Z, E. T) B& Y, LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 U7 [4 Z! S: s6 d3 u9 j8 |0 I** Configure the McASP pins : E7 j" c# {* n" Y% O$ i- q5 N
** Input - Frame Sync, Clock and Serializer Rx
- ^" Q! `/ c4 F9 K! d. b* e3 b** Output - Serializer Tx is connected to the input of the codec
1 x" w4 }* S. x. _*/: g9 I+ j6 E& j4 S: h2 m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 k; X+ Z$ k( E4 @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); A' U( C+ {9 P0 g* ^( N0 \& d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* n# I$ c" Y/ E
| MCASP_PIN_ACLKX
6 \% L M- H$ E! t3 K) p+ Y| MCASP_PIN_AHCLKX2 q6 z% N# D6 I" b; ?. d$ A) V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; x. ~) S8 ~7 u- W% d$ K5 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, d( v4 V8 Z/ O) m| MCASP_TX_CLKFAIL
1 Q6 i* ~* w9 y9 @$ v| MCASP_TX_SYNCERROR2 W4 ], s- M8 T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + u5 I5 J- Y1 k
| MCASP_RX_CLKFAIL
4 P# p Y `8 d| MCASP_RX_SYNCERROR ( C2 Z2 F% a6 \: |! E
| MCASP_RX_OVERRUN);
! d& z" p: o n: G' u; J* U} static void I2SDataTxRxActivate(void)
; i( Y0 L- ~ K! Y+ D! n9 L{0 F9 R5 ]/ S3 \
/* Start the clocks */4 {4 P% m a/ @. y! C" }7 p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( b6 E) x6 L( Z( r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( y: u. }, w, ?# r! n# ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 F. j3 c8 y* ~' ]+ `: mEDMA3_TRIG_MODE_EVENT);
6 {4 `% j" U- ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ j/ j# j5 m4 z: G; O% |% KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% o& A9 N" D+ M. [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: e. k) s+ k. B/ Z$ |( `3 Y) T" K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- @' f* a# t$ ~( U7 p3 b" p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) g0 A$ q, `0 `& p: ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 }! K+ J2 V7 `8 _" F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 v9 d9 s- k6 ~6 j' b6 ?}
! R. I K+ X v* i, l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! I0 r6 I4 I5 x \ H; v' h
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