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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; k9 D1 W5 _1 K% [5 p8 W. `input mcasp_ahclkx,
* ]) A9 t4 \9 f3 Einput mcasp_aclkx,3 x. S: w0 o/ c0 O& `
input axr0,; I4 I6 u4 |# I6 g+ t0 N4 q
% ?& [6 [: a- X t
output mcasp_afsr,6 ~ L2 Z4 d2 Q, J ]/ ?' W# x: ]
output mcasp_ahclkr,7 }; m, V9 ?3 F/ q7 V* w9 \/ G+ k' v
output mcasp_aclkr," ^9 d' o" }" i0 z/ e( u1 {% C1 D
output axr1,0 j5 Y8 f4 ?7 h F8 V2 E) g
assign mcasp_afsr = mcasp_afsx;
% x1 `3 c4 m9 Z: eassign mcasp_aclkr = mcasp_aclkx;: W0 ~$ ^2 _, d, T' Y% E) |# @. i
assign mcasp_ahclkr = mcasp_ahclkx;6 a& ~# E) X* o6 X
assign axr1 = axr0; 4 H( \! s/ B; k% y& C2 V
+ v" {3 p! J# [5 Z* e3 {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 ` F9 l5 o, {3 ?& O
static void McASPI2SConfigure(void)
/ Y9 B, J! k7 K( p# h' i R+ D{
4 V) j) M0 ~" `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 a% n' @: `7 F: OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, D# b. I& g! d; D$ a, w6 H9 qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& \7 _5 y! w1 p' G2 D6 x# | g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* R4 J) f# z# wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ?% x" X Y A
MCASP_RX_MODE_DMA);
0 h- n" {2 {" g6 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 d4 `2 \9 G- V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
|8 c/ R$ i% R+ b' M+ B. nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% M2 x0 l. n9 EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 R. {* K2 P" Q; {& l$ MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' e/ Q" w( j+ b# ~" w2 C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// q4 _2 X. K4 q5 D1 @5 H$ S/ G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 I: p0 T3 I& y4 a7 b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; V; _! J7 I( c- m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# }! O$ Q! j" k+ p# k0 f( c. F z6 o
0x00, 0xFF); /* configure the clock for transmitter */
' t% _& f# n" A& [! q6 x4 N2 hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: i# c5 V+ M5 b. @) E3 E) OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ d" H; y1 e: E$ P) _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: I0 q7 \4 a% w; S4 W6 j6 O [0x00, 0xFF);! d8 i5 H% \4 u! G; f: f" t k% x
O. G5 f( l! g7 g1 c" |4 B* g
/* Enable synchronization of RX and TX sections */ , O+ V' N" M% C: H$ E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 x% z) `, R) t6 x$ RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* X) r( O1 D q$ [/ h! [& e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 W7 @$ L7 B3 ]! X** Set the serializers, Currently only one serializer is set as9 e8 c3 y1 ? d
** transmitter and one serializer as receiver.
. w9 a# Y8 z6 \+ S# A! I7 O A0 J*/4 _; X) {2 d: r" p, S. {- z( X' T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 |" T+ B+ ?$ v J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% a. k' F/ g+ W5 w9 c0 \6 c: s. `3 ?** Configure the McASP pins $ F) G9 }8 E) @! I
** Input - Frame Sync, Clock and Serializer Rx- s% r U# f& d* K
** Output - Serializer Tx is connected to the input of the codec # G8 p* e' O+ v/ @8 K R* E
*/8 c( D1 e* S" Q1 v' I; ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. S& M% u6 x7 E* aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ P+ B# y% U. g% n# K- h9 x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 E& |$ |6 c/ ]( ?
| MCASP_PIN_ACLKX7 m# x2 x8 V/ ?. ]$ w
| MCASP_PIN_AHCLKX% Q9 `, E" j" N5 B( ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, R. K$ K3 x% L& X6 }2 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - {4 M% l o3 H6 y, U/ B0 ?
| MCASP_TX_CLKFAIL / m! _4 `; b# v, u- M
| MCASP_TX_SYNCERROR5 `3 Y$ W8 q' o* k, q* p8 i K% ]: c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) r* t8 |( {" K: A5 n6 ]9 T! d| MCASP_RX_CLKFAIL0 \' G+ F d' q( E( q1 f, f; a
| MCASP_RX_SYNCERROR 8 J* l3 {- G6 t& F3 V
| MCASP_RX_OVERRUN);% {% M7 v7 _/ p. ~8 y3 j
} static void I2SDataTxRxActivate(void)% C8 \+ ^* E6 F1 @
{
7 F0 X, v' u. y% p) d/* Start the clocks */1 R! L: y! ]9 J4 ?* I2 h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 a* x& y) ~# t+ GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// z1 t$ u' Z) V# V5 ~. F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& s' d/ ^; ^9 REDMA3_TRIG_MODE_EVENT);% Y% \. B m `5 J7 O# i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 L0 X" Z U! ^2 m8 O* E3 U! l" n; NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% l% V6 x X5 v f/ B- ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ p: g+ S# ]0 y( {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. L: ^ z. A$ N+ rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 i7 n0 U; u) u$ a% Q2 `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 o. t8 r& K5 g6 ~+ b# a3 O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# e: ~8 Y+ O2 r! `}
' I4 t; I' S) P8 E: Q. r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * j2 @) ?) l' a8 k8 s/ q5 [) X7 ^
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