|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 t& z, Y% j; _( p; j/ u/ P6 Oinput mcasp_ahclkx,
% l9 u3 i1 g# g: y! p; }input mcasp_aclkx,
! e4 x* x- E8 ^ ]9 J$ Linput axr0,: ^, g& r' X; [' w
: Y4 \5 h+ W' G. \output mcasp_afsr,
& E, u' \0 Y0 r7 b. T0 u8 |output mcasp_ahclkr,
4 \6 ]& _$ ]1 j1 a% k# Voutput mcasp_aclkr,
7 N: A' B3 M" ?output axr1,- [' D+ x4 l4 L) |4 D/ J
assign mcasp_afsr = mcasp_afsx;( u2 }1 R5 T4 H) r. _5 X
assign mcasp_aclkr = mcasp_aclkx;) l9 u2 }, ~( C' {* g
assign mcasp_ahclkr = mcasp_ahclkx;
* R4 _% v& O1 \- j- B) s0 z5 Nassign axr1 = axr0;
. c. f" r+ i0 |# C% L$ ~5 g. d7 v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 r5 S: k# s' ]4 Y' M& l
static void McASPI2SConfigure(void)
. B, P) T0 {5 g4 z5 U{1 V# K* ], l3 k# @5 v- y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( n8 d8 @* B4 [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; }0 }7 K1 e0 m2 C; p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ ^: H5 g4 ^+ ~; K1 d0 `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! i/ E& a" {! y ]8 X! q4 {# X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% W6 F. N1 l* u# p7 u
MCASP_RX_MODE_DMA);) ^5 n, Q1 c$ P& _: f% y: m) U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' {/ }( o1 y) P' K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& i0 a) `6 B7 @" x. U2 a0 W* jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! C; U( ^$ Q3 m: y# \8 D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 ~8 q/ a, n- S, f* X, G6 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . S' B' Z0 b5 E, l# z/ r- Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// g* u8 b G' B4 z. F+ x* \# a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ i& a6 f4 R% ?4 ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ J" Z- [1 o% z4 D, H& \& n. Q& @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# R* @0 m1 L2 x8 o. g' q, i0x00, 0xFF); /* configure the clock for transmitter */
% K' b8 U+ p+ Z' O* x8 SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" e0 @7 O3 G7 {, J/ n7 V& _/ F3 T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# M: m5 `2 W2 e& h+ p& t! pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 I, J' H {/ u0x00, 0xFF);
$ ?; v# b$ A9 }5 G" R* c# O4 ~3 A2 T) l4 g
/* Enable synchronization of RX and TX sections */ 3 }3 J2 `# w" m7 A& p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 |2 u+ s' [) e! c, z* r+ E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" L" y; W6 v* g3 ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 J l4 \" \5 f& o0 c2 o3 I' M0 s) s** Set the serializers, Currently only one serializer is set as
- ~2 L) N4 g/ U** transmitter and one serializer as receiver.- E' O8 ?$ \' U
*/
% E( T1 @$ {& e: u$ \, E6 YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
E9 p+ C8 c1 SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) `4 |- J& W7 m/ n& x; I** Configure the McASP pins
% m2 ^9 x& ~0 j** Input - Frame Sync, Clock and Serializer Rx1 H2 e/ I) O8 r" h" T3 b+ D4 R
** Output - Serializer Tx is connected to the input of the codec
! z+ w& z1 _: F4 ~) v* h*/
+ V1 l( g. ?6 H: ?8 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 ?. z# q5 m$ N0 }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 z" r4 F# c1 O) J! E: O x) m# F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: Z& e, o) a1 D0 A8 \3 r' B% s
| MCASP_PIN_ACLKX
. ^, t2 t% l8 h4 N| MCASP_PIN_AHCLKX
6 q3 w5 o9 ?) H8 m% Z) y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' T1 j6 |( N- W/ f/ \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; c7 L% g# ?1 }% o) g( u9 A| MCASP_TX_CLKFAIL # C1 q4 \; K9 y: g# n3 J7 G
| MCASP_TX_SYNCERROR
$ j$ ?( t- u! x3 \9 e6 s- k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 Q' P# A! Q* F' x7 Q0 W
| MCASP_RX_CLKFAIL
( b; ]7 S; [/ D! r$ G9 m7 y& t# f| MCASP_RX_SYNCERROR : o0 ], I6 j- L. a5 c7 e6 m
| MCASP_RX_OVERRUN);
/ X! Y5 {! S) V. m' w1 P& ], ^} static void I2SDataTxRxActivate(void)
* W; M8 f( W+ z" ^7 R0 C$ Y" t2 P" @: l{
5 z) L6 A' P/ G% O4 H/* Start the clocks */
, u( V. r+ D' `& o. J$ K* LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
C" v4 ^8 M7 c4 jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! Y& |8 F8 b1 v. Z" e- Q, }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: A: {2 L! I0 F/ g, oEDMA3_TRIG_MODE_EVENT);
$ M, s7 E1 k+ G4 \$ NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, p% N0 h5 ~( v5 m$ l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: P8 _% Q) l: }8 L$ L# L* s& Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 @9 ?1 A/ [" g7 t2 [$ X9 Z$ c& i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 \, }+ t$ S- Z3 |4 ` G+ l+ hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ x" u) Q: v# C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 g1 F+ J/ E9 h& p: h& O( v. f; l, JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ m: I% ]5 Q# ~) d- a
}
5 {* }/ f/ V% M* d9 Y; s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 \& I1 g6 k+ c- w/ n3 a
|