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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 T# V9 E4 a! j# d6 U9 e1 binput mcasp_ahclkx,
. ~1 K! A) i( ]/ c% f: ainput mcasp_aclkx,: |0 D- u! L' x4 i: ]
input axr0,+ q. A: V' [+ N9 Q& X$ Q# f \
7 Q% \% O6 o: d7 y4 F+ S" H0 toutput mcasp_afsr,
. g6 t7 U* z6 _ voutput mcasp_ahclkr,6 ?7 P; N4 H1 ~/ D3 b* B
output mcasp_aclkr,
5 y8 b; C& c1 Q1 N' C/ ^output axr1,
+ n2 d" a: R# ]; c* w/ X6 z assign mcasp_afsr = mcasp_afsx;5 B& j x/ Q! n6 u+ \
assign mcasp_aclkr = mcasp_aclkx;
* e4 Y* j' c( D, ^" A/ \assign mcasp_ahclkr = mcasp_ahclkx;
+ U) B2 k% y$ p( Y" `/ \assign axr1 = axr0;
9 L4 X# i, a( j/ ~: u
- @. N& d# _3 b# H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" j u4 F( H: u; Xstatic void McASPI2SConfigure(void) X g1 z1 s; o# ?; {/ n
{: b# B2 k' E2 p, ?4 T1 I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# I, T8 y9 j! e% QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# S: o5 I' Z$ ]8 E9 U4 |7 ~ i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 ~- R3 r8 X. p; SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 D" K! H- `( l7 O: P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* ^6 h; v6 g7 f- O0 x1 g: R
MCASP_RX_MODE_DMA);
/ V8 Z; v2 {8 M# i/ y- e$ K" L+ uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: S, q! b& _4 l. F* L pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ l+ F5 l- {& G7 ?1 H8 S: y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' V; C4 g$ Q% E3 ~, gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. J+ B0 i" j# S" s: o( `0 l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" y! q4 l5 W- l$ hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; R+ `$ o7 w. W! \% ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; {' X( T0 m: s* E E" V8 A6 m: _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : Z+ Q) Z: g) O3 q2 [1 m# V. z4 v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 t. m A3 C0 B. o2 G: Q5 G7 G/ g0x00, 0xFF); /* configure the clock for transmitter */
- p" @# s5 v- P4 W7 _% @1 Y/ Y7 sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); `7 g! \9 r" G# @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + r( O( u2 w2 q" F' x4 f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ v6 o* R0 C0 {0 l
0x00, 0xFF);
+ G3 `$ J7 ^1 F2 I* p# G% z$ }- e$ U3 i; ?
/* Enable synchronization of RX and TX sections */ 6 [% g0 h# p# ]( H& g5 x8 D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 _* _3 x- M9 z+ l6 ?! W+ ]! v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 s# D* t0 G4 j: B" B6 QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 W" v# q: n& `** Set the serializers, Currently only one serializer is set as
) \+ E* v1 Q5 z- D2 H** transmitter and one serializer as receiver.8 H$ m* M; \( x3 @
*/
. Z& E0 }8 b6 K8 d& JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 {! F' a) T5 k j/ n( s R. e9 D3 p& v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 N( x5 Q: x1 L( j* X0 `** Configure the McASP pins - Y+ q. k. O+ ^6 |
** Input - Frame Sync, Clock and Serializer Rx
9 X4 d J# Z& p8 G0 H** Output - Serializer Tx is connected to the input of the codec
+ O: g2 ?' z& Z c1 g/ j# S) t*/
0 Y ` I0 _. E# U; a7 |! _3 xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' k2 Z1 o" H( o9 G/ U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. y R+ g u# N/ S. O" T! t1 V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 C# [# }: H2 f8 Z
| MCASP_PIN_ACLKX
3 Y! c. J% C# b3 w: P! y$ n| MCASP_PIN_AHCLKX( N3 q# e+ O/ Z4 `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 j# a0 g J6 u" F! F4 Z! A4 B& D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . |( s [. R6 W
| MCASP_TX_CLKFAIL 5 t% F3 _1 Z& v6 P
| MCASP_TX_SYNCERROR
7 e4 ]5 y" l: A1 U3 B7 z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 ?9 r% I0 M5 M7 ]2 V
| MCASP_RX_CLKFAIL
4 m( }5 `, i0 G6 ], B# N| MCASP_RX_SYNCERROR . o0 z% T Z% n0 L- E
| MCASP_RX_OVERRUN);
6 P- K; J, J& N} static void I2SDataTxRxActivate(void)
7 F; P b0 r# y2 }{* n. W' v8 Q- I3 j* Z
/* Start the clocks */
0 U3 ]& d- I2 p9 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 ?9 n! S7 |4 sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 w- O+ A9 [5 i: d+ `- i" MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: _% C+ Y7 \! q# @( ]+ cEDMA3_TRIG_MODE_EVENT);6 [8 b, z0 U# D% \; Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 I4 l* m& a8 c- ^# I+ J1 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 ^. f% X; ` M) R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- x5 O1 ]: b5 v, s4 n" x5 sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& r, Y3 ]" k* t6 E+ F+ C" Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# |( O0 Z' T9 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 k, b- Y8 J2 h2 w' Y% @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 }6 p+ |: m0 \, S8 s6 ?* A& L9 O/ S
} . l. X+ }4 L4 N2 A' f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
" @% ~4 ~9 r( A+ {7 } E8 ~8 w- L/ Q! ^ |