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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! e7 |3 l& r3 Finput mcasp_ahclkx,; A" o9 T/ y: O, d6 R* O
input mcasp_aclkx,
' T b ~) Q) i jinput axr0,6 g. s3 s# \* U- d" E" }
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output mcasp_afsr,
0 W- o; B' w7 r5 f. @output mcasp_ahclkr,
% {5 A. R4 T3 A9 y* z3 routput mcasp_aclkr,, C6 X5 \. H# Y4 k+ j( k/ Q
output axr1,: {+ _0 M+ _/ `; o0 x
assign mcasp_afsr = mcasp_afsx;
* o! o. ~; ]: e8 L9 F6 Sassign mcasp_aclkr = mcasp_aclkx;
6 {8 s4 z3 l8 |) z6 passign mcasp_ahclkr = mcasp_ahclkx;
% X6 i. u1 v8 b" B5 z+ A( M5 Qassign axr1 = axr0; & c5 r; k* h( g% u0 n/ Q
9 ^3 t' p0 Z3 M, b3 n+ ~, E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ b( X* ^3 M/ f" @: k- N, b3 istatic void McASPI2SConfigure(void)3 U# m/ O, \$ \! M8 [, P* n4 E+ u
{3 ]0 X- B y2 N3 J( T% E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ ]. B% V+ P- W6 n2 x0 ` sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* `. E' ]6 C8 o6 N3 r5 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! v ]$ V5 ]/ ^) u( K) @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) F- O# C9 F. K' d1 Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," y9 D5 y* b) C4 N/ g! }9 U
MCASP_RX_MODE_DMA);
' ?3 o5 n9 t9 J7 }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- Y& `4 x$ e( ]; E. A3 |2 U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- f& W2 z* i5 r$ k y* m+ j; cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( `" O0 O) J0 `& C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 ]! {" y& H% L1 G! ?* D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 M" z, y$ R4 N; A; o2 [1 D; c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 v5 r4 R1 d, D9 ]# A7 ~' V( r6 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 [" B; m# {7 | QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " ~+ R, j# ?% |* E+ P/ W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 `0 x$ ?3 ~$ F8 `# {: i2 M
0x00, 0xFF); /* configure the clock for transmitter */$ S& [- I9 }8 |, R0 b8 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ l C+ @) Q1 z! u Y& HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! J9 [. g2 O. b( G: U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," n/ r( H4 U0 C/ X! R$ n
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
- R: ?/ ?$ |, [; M. \0 }' bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; I' ]4 v! k( C& ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; k$ J7 L" t) j( sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 i5 S7 E$ N# @9 F
** Set the serializers, Currently only one serializer is set as5 W( w9 u! B' w5 E
** transmitter and one serializer as receiver./ _. Y( V3 {+ N
*/2 J9 t/ o" i9 x# J$ l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& H" c* \. g1 Z# O8 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# E. s6 e* F+ H# E8 F9 ~** Configure the McASP pins $ \0 g, K: u/ u1 U
** Input - Frame Sync, Clock and Serializer Rx) w$ n9 J, q3 h; |
** Output - Serializer Tx is connected to the input of the codec
8 F) G: O5 d. l7 c$ j*/
" G" t4 j' `2 P x# k; WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); P/ f! Z0 Y- U/ V" g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& p8 n- e9 Q" m6 E- o# q% X4 N( jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 n2 Z5 D) t3 Q) l- E4 `7 V| MCASP_PIN_ACLKX( Z# A! |5 q7 X3 {: l
| MCASP_PIN_AHCLKX& ?# a& u. p u: i z; d1 Y/ K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: g. P3 _& J- G' C# V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 h. J7 b* a6 }( z1 ^" O$ w/ ?
| MCASP_TX_CLKFAIL . P+ [/ x7 M: X3 V
| MCASP_TX_SYNCERROR
3 p5 R% [ F( t6 Q! || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . G! F" a+ H/ t8 p
| MCASP_RX_CLKFAIL/ b% J% Z/ ]: U1 y6 E2 p! m
| MCASP_RX_SYNCERROR
& s, C+ q. L4 h! x| MCASP_RX_OVERRUN);
8 L% E) |) m% d _} static void I2SDataTxRxActivate(void)6 }2 }% A4 A2 \( z
{
! m& D: q8 s3 [/* Start the clocks */
9 F# V- x( ]+ e9 p. V6 BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' ?$ I" S" C- C$ X. }* V; L3 OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, n7 c- I$ g& AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 f+ n# G4 ~8 M) S, h) Q sEDMA3_TRIG_MODE_EVENT);/ |! I7 Q4 B( C5 \; Z q. V$ a$ H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * A! c Y% M: \. T, O' A5 _4 ]/ z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 W( ]9 e% n# x, w6 w% o: ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, C y& O/ X8 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, ?& J; L! A- @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) i. k) {- x$ [( F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ [, c' Y0 M% v: T& j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 ~, Q# W$ k( |2 w. |
} / {0 L) C0 h; ]- r3 T$ C0 C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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