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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 n3 Y: I* L, F8 w- a
input mcasp_ahclkx,: F6 |6 w1 V5 Y6 Z
input mcasp_aclkx,6 u/ U. q6 d* I
input axr0,! }( u% [' I! e" o. [; D4 \2 A# g8 B
% A/ A9 S% T0 F# ]- J, i, s F) s x: {3 s
output mcasp_afsr,
- a F, ]/ P( |" }" Routput mcasp_ahclkr,$ w( `8 }" b( E0 ~- R
output mcasp_aclkr,4 B/ j+ G3 O) h- a
output axr1,
T) s% k2 r4 h/ _3 @# m assign mcasp_afsr = mcasp_afsx;
; `$ C* Y3 w% R) J: `2 N! cassign mcasp_aclkr = mcasp_aclkx;
& I8 H; d: L8 P9 {, massign mcasp_ahclkr = mcasp_ahclkx;' D d( ?+ }) X8 E6 u
assign axr1 = axr0; ( F. j1 S9 ^5 c5 d* d+ ]
( c9 X9 \. `; B0 n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 i( o! d, X" z% ostatic void McASPI2SConfigure(void), e2 u/ h3 v) x) |9 Y2 P
{. {7 _2 U: |& p, \" ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 P8 j6 P' `0 A- t0 V9 e9 oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! Y& G, z) m4 E! g# ]8 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( {1 U' H/ n2 W' r. Z2 M5 W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 ?- P$ K2 P' t' m. q6 P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ b* S! I% \- \MCASP_RX_MODE_DMA);/ F. s5 i1 H9 X; k+ F. T% S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, g) t& A6 x8 S6 C% N N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 `0 `5 T8 v+ Y- k/ \2 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 a! j5 K1 A5 G8 U! [" x5 x! B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 z% L% ~4 l, v+ T+ D0 C8 A' Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( x/ G. _$ y2 ~9 X& a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" y" E8 i2 Q1 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( T* l% O* n; W# E7 w; aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) V! k6 ]) x: \7 J1 s8 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- u: o$ l$ v; @
0x00, 0xFF); /* configure the clock for transmitter */ e9 @) s2 f- Z. p0 @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: h4 s. T- k# i0 E% e$ r4 b" RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: P1 L9 Y" X" N4 @* y+ jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" y& D N) k, i0x00, 0xFF);+ |; {" F( K9 _$ y4 H* N* I L( S
" K8 ? D( q( Y* Q! x" t
/* Enable synchronization of RX and TX sections */ ) t( E+ e+ t8 ?- `$ Q8 v3 Z1 u( [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ m% y/ ~, w+ r4 l8 OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 @, L! Z9 v |7 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 j8 e: r v* C
** Set the serializers, Currently only one serializer is set as% d3 c) s5 P1 D1 ^$ g( m1 L0 R
** transmitter and one serializer as receiver.
" E: B) g% \0 k5 k' ?% Y- P" m3 h$ ?*/% c. V! }; p% `2 A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ Q- M* s f1 x- S* G% c. h) AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 r; B0 @: k7 g
** Configure the McASP pins 7 b6 b& j& [/ A% C) B
** Input - Frame Sync, Clock and Serializer Rx& i7 A6 v0 q3 T! }# g
** Output - Serializer Tx is connected to the input of the codec * M4 Z8 s* j7 P+ h5 G
*/
. o" }8 h- a' j, U; G* Q' r5 NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 v% m' d9 W' X' x& o; MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& q, U, ^8 [! A2 Q: pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, A3 D1 `6 m7 n
| MCASP_PIN_ACLKX E. D4 B% I$ @
| MCASP_PIN_AHCLKX
+ Q4 z% t+ r9 s" [+ \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- a+ t: k8 h, J5 E6 M, r! X7 \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 u3 z- x1 T+ e' \1 Y% D; A
| MCASP_TX_CLKFAIL 4 m8 b7 u, P3 |* }
| MCASP_TX_SYNCERROR0 }$ C8 [& T6 C2 c5 B. ?$ E2 `2 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; M% q$ p: O. Q$ i' ?* x5 x
| MCASP_RX_CLKFAIL
. p- Q* s+ u, s1 U$ _5 d3 \2 x# n| MCASP_RX_SYNCERROR 9 h5 F/ s& l+ X, v# Y* I5 W
| MCASP_RX_OVERRUN);: }1 Y1 @& G0 c, R: o
} static void I2SDataTxRxActivate(void)
l# Q0 Z x& m+ S& P6 y{9 t" |% f8 N4 X& {( Q2 P- ^
/* Start the clocks */
$ [6 Q' l* X, ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) {, V# D; \! i. WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 s' T3 W% k/ M5 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& v l/ ?& G; D8 o ~( U) o
EDMA3_TRIG_MODE_EVENT);
$ Q$ ?( t7 P7 {0 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " j) f: \, B! W3 n6 ~$ Q* ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! A4 ?; b/ g+ P. D$ W2 ~$ q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) }# J8 W+ I5 h5 [$ z; PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& B* N/ B: M! f; p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' v3 y6 J! p' P4 y* \7 O- |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 J n* e' Y: C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" h" @6 M! J" P9 A% ?2 Y# r2 _
}
7 k3 p. T- h" y) y- q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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