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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* d d+ F/ U* M2 xinput mcasp_ahclkx, r( R3 Z m$ m( P
input mcasp_aclkx,2 j( Y8 T* R G
input axr0,
6 j5 d; S3 [; _7 O2 E/ n0 W) T/ Y# D: F) K
output mcasp_afsr,5 u1 C+ N4 V/ I
output mcasp_ahclkr,
: l2 `# P: y, A1 b+ youtput mcasp_aclkr,* u6 m3 A( z# f3 s ], E+ M
output axr1,
8 E6 H# ], a% R2 R* F assign mcasp_afsr = mcasp_afsx;% U! Z, z0 r% h. F0 n" ^: C
assign mcasp_aclkr = mcasp_aclkx;
; k( ^' ~3 {8 Tassign mcasp_ahclkr = mcasp_ahclkx;% Y% b! p% I8 o4 `
assign axr1 = axr0; , ^1 A6 a& v, W: u) d. V' b( _
y: @; d6 z) n0 c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; }! @, V. M) ]/ o- \; |4 g/ `static void McASPI2SConfigure(void)
! D. _% e% @3 g( F7 v) Y2 C+ i/ Z{+ ~# r) w$ Z( E' L K7 h& f( `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 g5 O$ M8 @4 VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" U, P. g& H) Y1 @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 @" Q5 U8 s7 I: p; l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 b6 J9 c2 ?9 H! a' W' lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ L+ n3 Z4 C: W. a d6 kMCASP_RX_MODE_DMA);# [ B1 d4 q. {* E9 Q, J; Z A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ Z; g1 E/ j7 JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- B0 g/ `. C X3 a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 m4 I6 ^4 C5 ~. P- N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 R% z. q) V3 B/ {& cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 k/ S* S3 h: I# V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' W% }$ w7 P+ ? Y2 D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, j& D, M2 b: G, e/ O( M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. P. z! t" ^7 e1 M, W9 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" ?+ E( m" p) y( q0x00, 0xFF); /* configure the clock for transmitter */. a5 h# x4 d7 D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" j' t% q5 t( {0 t& U( e8 n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
H. s# e2 Y( ]3 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 X/ ^8 v" C$ W% S9 L" V
0x00, 0xFF);
1 s/ d( S2 X6 S7 B# p ?& g- H% T" d; q! `1 D% m
/* Enable synchronization of RX and TX sections */ ( A- m4 c0 t4 V3 V& }# S0 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, L' Q) Z; [, ` Y0 D" c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ e' y" e2 H$ Q' V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% F* {& y; {( e. O: W' p$ z! d
** Set the serializers, Currently only one serializer is set as
( }: B% V# i/ |2 W2 H* h** transmitter and one serializer as receiver.$ m5 _4 a, |: ~
*/* i" m6 b% s( K) u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! P. g* m6 T4 `9 ]; y! Y W, ]# L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 T2 ]" ?5 k% d; m7 p: z: g** Configure the McASP pins
( ?6 S" M' t; t E$ C** Input - Frame Sync, Clock and Serializer Rx
6 P( y+ M$ Y8 q% D1 R** Output - Serializer Tx is connected to the input of the codec
4 J) o, ^5 z; N& `( ~7 ~*/$ B2 E3 O. W5 `+ s! v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 A5 Y* k, c, @0 f* P8 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 |3 z; z! [* Y+ o* \! jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 N# x' u3 V7 [5 P% ?; j: X p: ^. v3 v
| MCASP_PIN_ACLKX. ]' J/ a$ _' N3 ^3 ]9 ?/ \
| MCASP_PIN_AHCLKX2 e a2 U5 @2 r- L5 T( C% i Q+ ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% C% |# j* R6 L" t( @; z6 `2 bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 _4 X5 [; e& X C9 q) n. z
| MCASP_TX_CLKFAIL
6 [2 a! j0 H j% J$ ^| MCASP_TX_SYNCERROR
* `! h, w) v: ?8 c% l3 a) h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ i" V6 C ]7 @2 s2 M| MCASP_RX_CLKFAIL) r: ^2 |" N7 @( `5 G" |
| MCASP_RX_SYNCERROR ! D( _% ]+ n% m) I) W- |1 T
| MCASP_RX_OVERRUN);0 ]" |3 c4 s T0 U2 N' K5 o/ e
} static void I2SDataTxRxActivate(void)
% O, @# t( w1 \. A/ p6 j* s$ Y{
* x. p! F+ Z; V; Y' _6 F9 ^9 M/* Start the clocks */* ]3 `) i" Q# a5 f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ |/ \. R1 Q2 U1 \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* I, v& K/ B9 x, E J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ r. S, G( f5 f! }EDMA3_TRIG_MODE_EVENT);( |4 K' g o& N/ j) K" E5 y1 {/ c6 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ h0 _1 C7 y! m) h1 e+ M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. q8 J7 a& q6 F8 M/ f1 }; k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ V( A3 `2 v$ r3 c% L4 w% T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ w9 O+ V1 @# U5 G& Y# h5 q5 k! G& R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 q* m4 y+ V6 J1 [1 c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( K. k5 B$ u( w$ H: I, p; `2 TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 O" y4 f1 U& u' t% W5 V+ N} ) y& G3 C( P5 C5 x/ \3 j# v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & O" E) x5 f L+ V$ Z
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