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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 _& i" V' O, A
input mcasp_ahclkx, e: `2 L1 u- C9 L# U
input mcasp_aclkx,5 r0 \" m( J4 N) r5 R" r# h6 W
input axr0,0 k2 F! ^, w! w5 m2 R# j/ F
" L) h2 ^& |5 V/ l9 A
output mcasp_afsr,: }$ f' h, d6 M6 G
output mcasp_ahclkr,
g, x3 W/ L- `# b& G& v7 b+ {' Ooutput mcasp_aclkr,
7 N- c1 Z( R7 d* W0 {output axr1,9 L5 q8 w7 L* [8 m
assign mcasp_afsr = mcasp_afsx;+ }- l; e/ t, W2 O7 A
assign mcasp_aclkr = mcasp_aclkx;" Y5 T2 w1 b" {1 a3 N( M6 M
assign mcasp_ahclkr = mcasp_ahclkx;; d7 ~9 K" w1 w
assign axr1 = axr0; 2 D l3 J C" I: \9 }: ?8 ^
" L3 ?4 V( s. ?2 n" M8 Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 u' @8 V# i/ s1 \$ rstatic void McASPI2SConfigure(void)! e i' T0 a- k$ i X' K
{5 T+ v T# I& @9 K* s$ m7 \* i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, a4 W g+ {( z# \- G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" Q; _# o. v/ ?& |% AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) Y- M+ ?& f* E, W: s- tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ Y, n# \# z t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ V! Q" R- v4 C3 ^, s, tMCASP_RX_MODE_DMA); X3 g W- e' {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, F- \2 ~5 p+ Y: } [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; o0 @$ @/ h: S5 m; W" w7 K# m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" |) G- s+ V' r6 `" x4 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
E/ J- w4 O( M' ^/ y _% RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / l, ~8 t. a) }* H8 W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ p0 t( v7 L4 ], YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 @2 E& @; R8 S! w2 p$ VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! d; O! Y; s; t9 m$ R- EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- J6 b6 K# Z& j, I9 e* H9 H& O* `0x00, 0xFF); /* configure the clock for transmitter */$ A% L: O8 G* m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& u" _3 q3 G* |3 P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; y# v# u& `# C4 n7 YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; d& K/ e7 E7 s5 S# _
0x00, 0xFF);
; u3 w- m U! J. Z$ q$ ~* l/ {2 @! ?. Y3 b2 D0 F* H! m
/* Enable synchronization of RX and TX sections */
: S' N. @1 g. G9 U) g( A$ aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! Y. @5 }9 O( @$ o& p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; @; W, M# N9 y/ D5 v5 B4 gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ _3 | [" Q% m( ^
** Set the serializers, Currently only one serializer is set as
" e' a0 B% `2 `2 V5 D9 D2 y** transmitter and one serializer as receiver. O% z! X) X; e0 ^. Q& Q. h
*/" C3 }% t3 l1 E! Q% u' T6 v, a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ f5 e$ {) X( z4 A& L# ^( d, Z) {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 B o$ a* \$ H
** Configure the McASP pins
/ Q. r# N" K% f) D- N1 L** Input - Frame Sync, Clock and Serializer Rx' v9 v% O" {; q1 ^8 `/ C
** Output - Serializer Tx is connected to the input of the codec 1 } s4 Z# v* D- M! x5 _
*/) m" Y% R" M+ n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) s( F1 s. d: _: y9 }6 F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 K1 g ^$ V! O8 G2 l2 {% h& dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 S- h2 j/ J# y2 s( C
| MCASP_PIN_ACLKX) y8 t. I: _5 E; H! m
| MCASP_PIN_AHCLKX, D* o. U+ ?" `- F: {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 `6 n- C" N( r4 xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( M* U6 G! J2 ^$ F
| MCASP_TX_CLKFAIL
2 A/ X( W% D3 o2 ?* W8 B| MCASP_TX_SYNCERROR
q: u! }% ]. N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) u: K* M4 \" _* G; A0 l- h
| MCASP_RX_CLKFAIL7 c3 ?$ f, n& Q) Y9 q5 I
| MCASP_RX_SYNCERROR
. F- _# I( X, U7 K| MCASP_RX_OVERRUN);
4 g3 K4 V; { ]1 H8 k( `} static void I2SDataTxRxActivate(void)0 ^8 Z: z, x! S& s, i4 {4 _4 p
{
, H9 v4 |) O# n! f5 F! |/* Start the clocks */
' M, l+ A2 f8 D6 \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' G: c' ^, v" o3 S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) b! |5 R& o. I! k8 ?/ W" z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 E( P! Y n6 x! g& l
EDMA3_TRIG_MODE_EVENT);
# z; ~ X( S ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . \2 s- q& f2 B( l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, L! o! f% O8 c9 ^: l' x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. @$ e0 x& j* G+ @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! |2 c4 U/ [$ G6 }) O# E8 y9 Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 j7 h) B$ z1 S `$ \/ i3 L+ I* NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ W7 C3 Y2 n7 s7 R: u4 Q* E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ x; w( N( l- I& B' T} " a5 _$ R3 {& p& V+ H( e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. N% _ [0 V8 p* `( H* U4 [0 D* O
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