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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, ]- L4 D( U! L" @( z0 Q% \: kinput mcasp_ahclkx,; E: ]& I1 q: |* c
input mcasp_aclkx,! h! U; O" P' d! g. M1 U
input axr0,
* }5 o1 S2 h2 [! c# [, }! z% ]+ s" D- t3 O. e( S
output mcasp_afsr,
0 x! i e5 o, O6 ?output mcasp_ahclkr,
, L# f7 p/ L$ ?output mcasp_aclkr,
# v* H/ _/ G& p, k: m( x2 routput axr1,* C' f1 v( M2 \$ r$ I
assign mcasp_afsr = mcasp_afsx;
( T" @5 e3 D- x1 oassign mcasp_aclkr = mcasp_aclkx;
# h+ A; J3 `' Aassign mcasp_ahclkr = mcasp_ahclkx;
: E2 s; ?4 q; W6 j3 e7 i" passign axr1 = axr0; ; B/ r+ j& K6 }3 L+ [2 _
3 {% T) L; `) ~0 g$ X' J7 }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 q, R3 E4 v J7 C$ Hstatic void McASPI2SConfigure(void)
- Z* k6 x5 K( N' Y# M9 f{
+ u/ d& m0 F, {# o/ C, BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ `6 k/ b; e; d3 TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ X& R3 U6 j8 [. r5 W/ I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; m4 F/ B' @9 m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- r1 ]" z% p7 mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: `8 f4 Q) y1 W A$ |3 pMCASP_RX_MODE_DMA);
7 H! | s! [/ X0 F( SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 m( ^ Z* A6 W- A- P& A" \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- J' ~+ J: T% X/ [8 @% W4 ~3 U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# c' a; K' L# h0 G8 ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 d4 y' [6 y+ J2 x& m7 `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + z* k8 A6 X- C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ i: c4 J3 N) Y u6 _! \# iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 A( {# P% P& a) S0 s# c& C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- M4 B, d: w) sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- ?1 f- v; B; W. X. T# f% c0x00, 0xFF); /* configure the clock for transmitter */; C1 _; P9 B; _) s, ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 E. t- ], x9 A% q8 L3 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 D) U- d" _1 `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 K" |7 ]6 h2 Y* T* D4 H$ ^0x00, 0xFF);
7 q x# e7 g2 x5 N+ p+ r1 x5 h) d$ K; t3 b
/* Enable synchronization of RX and TX sections */ 4 }# v/ q* W, Z; l! m/ o9 q7 Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 i/ z$ P) M. K" N# b/ d: n. }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: S0 ~. z5 t2 z) ?9 W+ @$ o# r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# Y6 a7 S2 J7 Z, ]
** Set the serializers, Currently only one serializer is set as
4 l2 i) G9 e+ H( p n+ B$ j* k** transmitter and one serializer as receiver.
2 h% ]& Q, P: K# \+ g5 x' ^% n( L*/
3 O h+ ^# t* Q: X" h9 bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ L3 a* N1 d6 ]% o) ]& ?# B4 R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. I! ~8 \4 T8 `5 L/ ]) |- d4 p
** Configure the McASP pins
# K, g3 V, X8 b, Q7 Q6 A** Input - Frame Sync, Clock and Serializer Rx( D3 K# S! |& u( d
** Output - Serializer Tx is connected to the input of the codec - |% l I* c: v' u
*/. L+ V1 A9 `" r/ g0 C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 q! B' a( C9 s2 Q$ x0 d7 ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
\ U& @) S; _. ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 Y/ K2 P7 W, ^7 J2 P* N
| MCASP_PIN_ACLKX* r6 \) ~& Z4 ^ e: a- O
| MCASP_PIN_AHCLKX& V) D7 G/ k3 |4 L; ?- J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- y9 m; u$ U" p: y% L+ \6 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& ~) q; p o7 O1 q, Y# w| MCASP_TX_CLKFAIL ' F3 g/ v* ?& G5 H; Z/ w/ J. l; F
| MCASP_TX_SYNCERROR( I, W, u: f" h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / g5 {( `( V; Z: y* A1 q1 A+ v
| MCASP_RX_CLKFAIL
% v$ M: V* [# x| MCASP_RX_SYNCERROR ' s' ~8 _' p4 v; U
| MCASP_RX_OVERRUN);! B* }. r) I+ Y! k( K( F6 Z
} static void I2SDataTxRxActivate(void)
$ f5 F- j5 A- h8 Z3 p{7 T+ V+ c3 I! n3 D2 @) p" n
/* Start the clocks */
& e8 @: g- W0 W# A+ m) rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) Q5 r+ e+ B. O4 k# s* h3 k# x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 z( K* i# E5 R; u# h2 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 X* `* y: N: R* Y
EDMA3_TRIG_MODE_EVENT);) [. _2 g' N. [0 S8 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 \: Z6 I, w' S6 o% dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 X; U. R+ B$ G3 X& f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 i @1 E8 _' H/ N. ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// z2 j! B6 ?& X& a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- R1 A0 X( Q' D( \6 ?" K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
G$ u. F) Q% B6 Y/ _8 ?7 rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& b3 n K/ _6 M2 a' L" W( O
}
! P2 ]6 U3 o" a4 Q. S+ U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * N2 K8 X0 ?. ]( `9 S7 ?
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