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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# F9 P. H/ j- Z* i) Pinput mcasp_ahclkx,) D6 d0 h3 [% u5 S
input mcasp_aclkx,4 c, j9 z5 S7 t1 I5 b0 |
input axr0,4 y7 N' d% c% U/ X
' S5 g; y1 D0 `" h) g. O
output mcasp_afsr,! C! @0 [6 G7 _; N1 D1 b
output mcasp_ahclkr,- |! `- _$ f7 [
output mcasp_aclkr,: T9 g: b' ~* m' z( ^8 o
output axr1,
% S. j+ a3 K" r& X9 {4 [ assign mcasp_afsr = mcasp_afsx;
! c' r* R4 U5 z( [assign mcasp_aclkr = mcasp_aclkx;' I( j' H5 I6 ~7 Z' e
assign mcasp_ahclkr = mcasp_ahclkx;5 y0 {) n) _+ d9 e4 G; E# Q8 P. ], l
assign axr1 = axr0; 8 J" B4 v2 b! }# n6 l
+ r3 c3 a( g. e0 Y5 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 o2 J0 }- v2 ^3 V3 Q7 a+ ?) k
static void McASPI2SConfigure(void)5 t. x, L- H, k" J7 X
{. y+ @; ?; |+ W/ e% k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 J3 Y& Z, j( m" w% h" A2 {9 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ P5 `1 T6 P- l1 ~2 y8 w, L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- ^0 k, o# m+ \1 f* h1 zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! V& a6 @+ k% m2 U5 R h( o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' X/ `9 p( [9 P- R: j6 X ~, g0 `
MCASP_RX_MODE_DMA);; {: b! Z- C6 l3 I) \! p. w0 k1 Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 A/ d4 d, C0 lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# T8 l( Z5 ] f) ~+ D+ `& p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" I" [! ~3 O" J$ z4 D$ N( R( sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ `7 b1 P. h* B8 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 y6 |7 q" i( q" N2 D1 L3 C6 hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 l; S, m# b7 w. P% h( @# E( JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 d" K* {. k# ~, f m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / f5 B4 N) q$ F5 f$ a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 K6 h7 o L. |. Z6 [* H3 s6 q6 r0x00, 0xFF); /* configure the clock for transmitter */4 S6 @6 E/ c( ?9 G# g% I0 A$ n5 C, ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" j1 T: E2 s9 w6 \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , T- e8 o4 X! j& F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! t D: V5 N$ @, i+ a
0x00, 0xFF);3 D% Q4 z) ], n! l, J
" N+ w2 M6 P" p# o/* Enable synchronization of RX and TX sections */ ) q7 C7 B) C% s" Q' x! M8 f6 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
\' `1 Z1 h4 ]6 o q) N1 y) ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 L! J; p; J) d; `- k; WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 d7 X. x& S+ H! Q, e
** Set the serializers, Currently only one serializer is set as
$ V& k. A7 ~' O: a0 R7 z** transmitter and one serializer as receiver.8 j* P8 F8 _# |' b; q1 ~- o
*/
7 k7 C$ P( s+ F# i/ a9 iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& C( X$ j- q9 }, K) J( H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 L- M( h% j& }" H; o: i
** Configure the McASP pins
2 @# D- Z; b4 p2 ~** Input - Frame Sync, Clock and Serializer Rx
& }/ Z/ ?: q6 U" U" S( m5 q** Output - Serializer Tx is connected to the input of the codec
1 t% z# f& ]$ C; f& O& _: l*/! L+ S* I; g3 W0 e/ ]& F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); l: J! X% w% R* O; M9 T( v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 d- p- k! H1 L. X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 ^: r6 [% n) q `' }0 q: y
| MCASP_PIN_ACLKX* r9 Z: D9 {- J$ W. q$ D' k2 K' T
| MCASP_PIN_AHCLKX
. N$ r) J* v$ y' m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ u" U- ^1 v/ c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- w6 X7 a( V* z i| MCASP_TX_CLKFAIL
( M1 f1 _/ g s- l# \| MCASP_TX_SYNCERROR
$ s% k1 s8 Y+ K- w3 E# w# U% u$ e5 c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 |0 b1 I( K) x2 `- v ]
| MCASP_RX_CLKFAIL* O' Q, J# W- X: b8 c
| MCASP_RX_SYNCERROR 1 F7 f1 P* a- M2 X, V- I9 y
| MCASP_RX_OVERRUN);0 C8 X3 B- e" W8 B) e; `: a
} static void I2SDataTxRxActivate(void): }) M5 k) h- |5 W# H
{
8 X0 D b2 r$ }/* Start the clocks */
& i; Y. h4 X% y" E9 J* u( i+ TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# f0 J1 n/ J. b. w* n8 NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// t1 J5 R+ e7 w, R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 P& C" g, Q5 S |! i/ ]8 F* _& EEDMA3_TRIG_MODE_EVENT);
, ~8 z9 n: ~0 @% G- _ A9 _; TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# ]; O+ {( Z* hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 J8 I1 ^" z F! k6 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; x0 `- q4 n, x" x8 h$ |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% `7 W( X; H' m. T4 pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 n! ^( O) @) `- oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; g9 ^: Z6 Z# s6 G! wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 G. E* Z4 T1 O% z
} 7 H5 Q, B( M8 ~: ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( V1 z ?5 e3 f9 f0 \+ `' t
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