|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: q4 I2 z% y/ ?0 M" O0 `3 Q
input mcasp_ahclkx,
J# X- W0 X) O8 X- m2 T% l; T+ P4 Kinput mcasp_aclkx,
9 t$ a9 G9 V ^input axr0,
5 T5 z( r0 }. {7 o3 X& m* G
, K6 Z/ m! f1 t1 F4 i* o3 w! Voutput mcasp_afsr,
- n5 @) O2 G/ t( K4 ~output mcasp_ahclkr,
- W' q$ y5 l: M! Doutput mcasp_aclkr,
0 E7 B3 u+ R% }( d3 \1 noutput axr1,
& b$ ^) d5 g% G& L assign mcasp_afsr = mcasp_afsx;
2 S9 I: L8 ]7 j) R6 |" {" Massign mcasp_aclkr = mcasp_aclkx; d) p! z+ C4 X+ C+ ~8 m5 g
assign mcasp_ahclkr = mcasp_ahclkx;
1 G* O& t1 X# g, p- P! ~assign axr1 = axr0; 8 Z# p; ]+ I9 l/ b" k+ D
9 h5 ]" C9 s% u( {/ H" K0 b. `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ H" _- U5 @" Q9 ?; T- D8 E/ e$ S
static void McASPI2SConfigure(void)
. u- `4 H# k. S; n/ k{
+ ^* r5 ?# R* J' V; U v/ wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 E; M% O1 U; N- W- l. v, wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
~) [- T9 F! \2 D# V7 c. oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% L. ~7 q) @ `( _3 iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. C3 ]7 m% Y6 T. W2 ~8 s! B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- @" E2 N4 R0 y
MCASP_RX_MODE_DMA);( }$ ^ {9 X l$ R; D3 r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. A7 s! _& J* g% X. v4 W2 |# R, kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" `% }* p3 l" }/ H U8 x- ]3 ?$ MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 g* _- R! c- u8 H9 W5 e9 vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! y' Z- D, t1 @$ c: E4 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 C/ X/ J' [7 Y: S$ WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- C" p8 K, u& GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. S+ `4 {# e- E( K3 [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ]% r5 U( Z& I& E+ |, CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# g s6 ^, d5 K* J/ h0x00, 0xFF); /* configure the clock for transmitter */
% ^0 x, c7 N$ x" C& nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. M+ \; z+ L, z0 V1 TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . E$ L |( X& }; w2 F, ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* k; }; g3 N+ U& d
0x00, 0xFF);
# L B0 d# c% D* [- U" E9 M/ v7 X/ F0 ?8 p; y
/* Enable synchronization of RX and TX sections */
, M2 k; ]0 k. z x( p) zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; \9 l+ @& `! S8 s2 A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& i& K: [. r, A& T6 u+ Y6 {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 @8 [' e+ C, K$ q** Set the serializers, Currently only one serializer is set as6 }2 K$ E1 T" \) j
** transmitter and one serializer as receiver.1 s+ l& t: }" T4 N9 ^- k5 k
*/% d* \4 A& X" S1 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 l& V8 T9 U/ e" e: I1 MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: E) W* }1 p @9 u** Configure the McASP pins ( R6 M# e/ c0 g
** Input - Frame Sync, Clock and Serializer Rx* P8 E+ Y5 L+ Y8 w! l
** Output - Serializer Tx is connected to the input of the codec , I0 p6 [9 H- G( W" O
*/0 G/ W. l& D' X7 o$ b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( Q2 R _2 ]: m2 G1 A" M: y5 m4 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' X7 `6 a9 p# ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX n4 G1 m9 i! e& z/ U
| MCASP_PIN_ACLKX9 z& B$ }) X& C2 \! w
| MCASP_PIN_AHCLKX& F, h9 ^% a, \8 ] U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( R, d: r7 e. F+ f6 T; e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" L2 z9 |: K) O, ?6 Q7 y| MCASP_TX_CLKFAIL
{' i% x3 R r$ U+ X8 x| MCASP_TX_SYNCERROR
# ^1 |6 j% b. g3 Y: Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) n( _1 _# \, u, j5 l0 q| MCASP_RX_CLKFAIL( d+ [" L/ K: D* R* c5 O4 }
| MCASP_RX_SYNCERROR 3 X% Z+ t+ z; [- G/ W
| MCASP_RX_OVERRUN);, I* [9 p1 g% H5 i0 E# b
} static void I2SDataTxRxActivate(void)
6 s8 I# }* p2 V8 e$ P{
/ F' l. P( p; |) Z/* Start the clocks */
9 a1 M. [7 d! Z, W2 M( [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 ^% A O0 {8 z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 e+ W! x& Y2 R( S) tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 a5 h5 c/ ]4 {! r5 [3 a6 [EDMA3_TRIG_MODE_EVENT);
) M& F" M* R. T. W& D' ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' Z+ ]; I/ Q; @8 G+ KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ @. k7 n* v: l, W W* W; @1 WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ Z. f$ p" d* ~2 }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, z# T% I+ W% L' P, [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) u' @( l ]) N% E8 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 |. ?! z" x$ F6 L& o' k m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! X1 X: P4 | K9 f- J7 G( g B# {
} - F* ^! u' [' C5 @" N# H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 [/ i& f5 H& j. I3 u$ F+ b
|