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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* B9 t S; @1 ^, M
input mcasp_ahclkx,
& x1 r. \0 Q, \% ^" ?4 z# kinput mcasp_aclkx,$ k) r- w1 |4 h9 I* \
input axr0,
; w/ i2 z \6 E3 o. F7 P
. ^& u9 V2 S$ i# {output mcasp_afsr,2 ~; t6 f. Y% \ Y: Q
output mcasp_ahclkr,
' R* N; L, j! Xoutput mcasp_aclkr,
- t& s! M# O3 O5 q+ Ooutput axr1,
( m# N' b3 W6 t: O. `& Z assign mcasp_afsr = mcasp_afsx;
" F% m( f" K- s0 ^assign mcasp_aclkr = mcasp_aclkx;
! E/ _& q/ L4 O0 O0 A& Lassign mcasp_ahclkr = mcasp_ahclkx;4 g+ V6 B7 Q8 W: O( U5 _
assign axr1 = axr0; 5 Z7 D) m2 w5 }; v, U9 n+ A& `
0 @, }) \( |* Q1 A' N( K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & k& m. e5 L6 [4 R" |/ K
static void McASPI2SConfigure(void)
5 A3 C# q* s9 p) p* ~' j{5 y2 ]2 }4 B8 l2 D/ X5 B! {9 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" Y$ n& p9 G7 a \McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. q" u; G9 H0 b0 zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 c& V. M, ?3 B% w1 x0 v; B; I- [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 e! X. g0 D6 e: p% W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 @, Y9 B- ?: R9 C! `
MCASP_RX_MODE_DMA); u$ z3 m* g! {2 e" |3 p) U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% N Q% E5 O# s) M# h2 ^1 `# J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 v/ D# Y# p& Q3 `7 R: N/ A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 _" J& T! f5 c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 P6 \' P+ c( Q. @- q C% P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 s9 n0 i+ C W! s( G9 C( {3 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 j% w2 Z( s" U/ f7 g" ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' _4 B4 Y; E+ Q' v( R4 E& zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, e& a% }) \3 Q7 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 T Y/ V' ]6 o: u
0x00, 0xFF); /* configure the clock for transmitter */
% S2 G9 F3 W# S, |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 x( p* C- S1 K& }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); R9 o. p' l. \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 g" X( y w* f/ u4 l0x00, 0xFF);
1 Z- _7 z0 K3 B% H/ _8 K. J+ T" X5 k, y+ m) Y
/* Enable synchronization of RX and TX sections */
# N( c& }' l/ G8 mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 J% G/ x% y m9 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, `4 O* V: p* @0 C) |( D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' o. g8 a8 {8 \8 E& y% _
** Set the serializers, Currently only one serializer is set as3 z: _/ w9 _! q+ Q1 u6 I/ Y- n
** transmitter and one serializer as receiver.5 h3 g4 W# [2 Y, K
*/
; V+ [, _3 {& p& P" Y0 N" RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ a! d* \& q F+ s7 O$ p! wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& m1 t- a3 w2 V6 l. B, J. v }** Configure the McASP pins / V7 Y6 y' k4 q) W4 ~' m2 H
** Input - Frame Sync, Clock and Serializer Rx
9 a' Y) N8 }( c& U/ p9 l% k4 S** Output - Serializer Tx is connected to the input of the codec " S$ J8 F* d4 K" h: T& V* }0 ]. R
*/
% {# G7 h( ]" s$ ^5 TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 L; _" ` B& B$ W8 I* Q4 _) jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 T- y$ U L7 B5 p* T7 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& d* M& X8 @) l$ I4 h% Q y( ]% L) s| MCASP_PIN_ACLKX. A" x6 H4 M: I7 O
| MCASP_PIN_AHCLKX0 ~6 M, x' m9 m0 W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 f3 M2 T6 V, X" S" _3 q3 _( ?* GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 }" e& O. h+ Y" O+ f| MCASP_TX_CLKFAIL 5 V: i3 |! V1 I2 c" N
| MCASP_TX_SYNCERROR
; E2 H% |4 b X0 Z) t9 w! E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + i) Y) V( M7 L
| MCASP_RX_CLKFAIL* ~+ t! T$ B2 U, ^( ?+ b
| MCASP_RX_SYNCERROR 0 F9 g5 [+ G$ W% `
| MCASP_RX_OVERRUN);5 V; z( v/ C7 z x# {
} static void I2SDataTxRxActivate(void)
, Q' H# A" Z+ \: V+ s; Y g. O{3 Z; k2 @! y9 _* u! x: D
/* Start the clocks */
2 `, |" i0 `" F8 D6 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( N9 g \# [- l. eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 Q6 z: U( R1 @; ~9 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 z+ n; B0 e( e# c. uEDMA3_TRIG_MODE_EVENT);, c2 |: G+ o- ^: h5 U" G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & i2 U! b" m P A6 U+ H: t# h9 ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ W- E4 i6 U& V6 E+ {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) f' W+ ^7 l& \6 {( oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" k' x. l' E9 a2 L9 n* S% o6 Q$ s' o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* Z0 c; ^* R0 r( d! [& j Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ j8 H- D* {' ]; K6 W7 L6 W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" T( g z0 _ a _}
' I4 u* @( r1 w3 ]- X) q9 Y' m8 m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. J) l7 N9 s3 z# V% M% G
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