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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 o! i0 [9 |! r3 V; \8 j: v0 Z1 S
input mcasp_ahclkx,
9 r3 H- ~) p& a) v6 X) a' Winput mcasp_aclkx,
) z8 g# T8 q1 p! X, p Q0 ~input axr0,
( [+ s3 V ^& B& _2 v& q
8 w8 V- w% L( U. e4 p/ y& \2 L3 Houtput mcasp_afsr,# r& v4 t1 @- n/ R+ ]* W2 X; C' e
output mcasp_ahclkr,9 [: I1 [( M0 S7 U
output mcasp_aclkr,5 C8 J$ u9 v7 Y- E4 N3 F" K
output axr1,
9 q( ^/ }6 [ V! Q8 Q/ R- U' V0 } assign mcasp_afsr = mcasp_afsx;$ F. _7 N5 Q: U$ J1 `5 J9 @% v
assign mcasp_aclkr = mcasp_aclkx;& u. j' U7 x/ I7 T; F5 U
assign mcasp_ahclkr = mcasp_ahclkx;* F9 ^) L- J5 s- `$ B
assign axr1 = axr0; & i6 x6 Q2 c6 ~# s& r
/ Q& U! F! Q: D( p b8 H9 k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! Z& A/ V+ P6 }" ~8 ]. `
static void McASPI2SConfigure(void)
9 T# V; y, P' E{
" P! a( B: Y4 ~' }* O! Z0 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! }8 x9 e8 G! s5 qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, ]3 t) ^# V# Y5 t* W" D$ ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: a6 G. f: A* i1 g$ |5 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 t$ b) l! y0 M2 H7 ^5 ` ?4 `+ lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! e% ]# b* c/ C' Z, jMCASP_RX_MODE_DMA);, B" j8 _8 q' y1 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 U8 b; i0 s- a# E. P2 j" ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 v% ?" A, j3 E# o. s9 V9 Q8 Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; d* D% N6 h, W2 n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 l) a! @+ N ^+ p# g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) p2 o3 d j- L, j( Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 f) M) A+ H/ y; rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 p; z' B9 ~* C7 q+ tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! k0 E( `0 z& s) S0 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 p# a P& Y4 b t' q" \7 H0x00, 0xFF); /* configure the clock for transmitter */8 Y; o9 ?2 {0 u+ J" f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 e+ c. b% e& tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: r" V3 s. b+ T2 uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) x- }0 @, D2 x: v- u: c0 _0x00, 0xFF);2 J3 ]; Q0 {5 d* ]! u. W" `
4 G* G" f2 m+ N4 c g/* Enable synchronization of RX and TX sections */
% V, W5 ~! j1 Q% W8 a8 lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 _9 x+ T2 y/ D% ^# v) vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 T2 i2 A+ h3 z0 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# o8 @" s3 `, _- p% n
** Set the serializers, Currently only one serializer is set as
, ]2 z7 l/ X! S: W7 \** transmitter and one serializer as receiver.. b/ m) U( `2 G2 S/ ~
*/' k( j2 r# |6 T, C! M, `) U" v; U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 ?. W' d& X" w- iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 H, i5 l' N) d" X+ H9 L Q0 |( a** Configure the McASP pins 7 L' V( g3 m! L: m
** Input - Frame Sync, Clock and Serializer Rx8 h* j+ G! x4 h
** Output - Serializer Tx is connected to the input of the codec
$ s2 J2 D- G9 z- C! l*/
6 O" r2 c/ W. n7 I# w( k! X# uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 O8 Z0 f |* @) u# j& o# Q* e# N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: r, Q; i5 n3 X/ S v; YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- [! _" ^, W6 M5 ]5 ]: K| MCASP_PIN_ACLKX3 w; y+ A! W8 K# L) o" i
| MCASP_PIN_AHCLKX
# S( c6 S: L+ `+ b4 T4 }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! I" |( q7 P+ y" H$ }* d& _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! L3 _$ D# h/ @' N1 Q( t( Z* A- S
| MCASP_TX_CLKFAIL + X2 D& J: d: f! U% l6 W* L* a( L
| MCASP_TX_SYNCERROR1 h( M8 }% g# P8 B7 H5 `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR t$ \/ }: D" I
| MCASP_RX_CLKFAIL. g' E( K7 {( b8 F# V
| MCASP_RX_SYNCERROR + P2 N* ?, a) v& ?
| MCASP_RX_OVERRUN);& y8 W( f+ m ~ S
} static void I2SDataTxRxActivate(void)
8 b' r( s$ X. d{
' `, z+ m3 K6 i' ~5 q' O/* Start the clocks */
" _7 c. L" _. |7 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ X& d# Z2 _* n, j( b# f" bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% X* S: k b- T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ K* V/ H4 @# O/ [EDMA3_TRIG_MODE_EVENT);
5 p5 b; W" V/ F. k( wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; O7 S8 |: @6 {7 W! K5 T; ~6 v1 b! l1 iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" E$ Q, p& F! x6 J4 ?* g- Y9 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ m+ A; O0 s6 K0 d# [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! |( [& P' h) Y" h0 s8 r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) q1 J8 U1 n/ o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 h9 f% C6 R5 ]+ N0 I% b6 y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 B$ F2 ~! t3 O
}
2 g2 j i+ o! C. ] D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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