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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. t) R& F( `" A9 Z; Q* y* E- `
input mcasp_ahclkx,
3 L0 J7 k5 T0 q O: Dinput mcasp_aclkx,
4 C' U" z* \$ g _2 X/ ]% einput axr0,
8 S4 f/ T0 ]- m! }" F- A2 d: S: E4 i
output mcasp_afsr,
: C4 L7 w* c E) j& j0 t" c, Y0 i) _( foutput mcasp_ahclkr,
0 b3 g }9 H6 Foutput mcasp_aclkr,- M- m- g+ d! d9 B; Q
output axr1,. b* }) V% v( B/ S/ g8 B) g% |$ J1 t
assign mcasp_afsr = mcasp_afsx;
3 P: Y+ `% @; f( lassign mcasp_aclkr = mcasp_aclkx;3 R- D5 `0 [' n0 Y0 E2 }
assign mcasp_ahclkr = mcasp_ahclkx;
5 }, o# v+ U9 r% H9 c% aassign axr1 = axr0; 2 y- \2 c0 p2 C
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " T) G; N, e+ ^4 j
static void McASPI2SConfigure(void)* m- N, f6 F+ E: ]& g
{. u6 u& T' Z- A. Y. S1 `3 L4 V P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, }( ^1 q+ @; O5 F5 U& |" u& Y) C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 L* b& a4 x6 k8 o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ B" P U) }$ Z8 n. J# b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 L* @1 t& n! b: DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 ?3 a8 u1 r2 H9 E4 ~( j2 ~MCASP_RX_MODE_DMA);, y }8 j1 ]; `+ b8 m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: h; S7 ]( X; TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// L7 g9 X, c. n4 B Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" b) |& x. R6 E- ~- u# _9 D, h) [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# e7 Y& F5 ? h$ o9 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - M0 E8 ?, n" I/ @- X9 ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 ~, v. Z$ u5 _# Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 C5 ? a1 s, L. N' O# [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( x, p% _8 g6 i# P1 l, ~8 H# |4 G2 ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& ? Q$ N( U2 _9 `4 |" n, r5 j0x00, 0xFF); /* configure the clock for transmitter */+ U# I9 O/ h' h& V, b. G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 m/ H& H" q$ o/ Q: |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 [: ^# E( {7 ~$ ?9 ~' \$ x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( I2 ]9 f6 `; K+ h
0x00, 0xFF);
0 ?/ X7 X7 m8 E5 W4 g- h4 `1 O% Q/ p. F/ L1 [+ ^8 d
/* Enable synchronization of RX and TX sections */
1 z8 }$ k P+ a$ Z/ r- kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& }5 i; K) O; C3 n% M* O0 H2 ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 f$ k$ C, v" L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** Q: a6 o1 ^( Q* ]8 J
** Set the serializers, Currently only one serializer is set as# s9 Z5 b4 X, F$ v- Q1 K4 S, @4 A
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, z6 @) G* l9 Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( y$ a- V' _# Q) e8 ^/ { A) F2 [3 ]** Configure the McASP pins
4 E9 ]# Q1 N4 Z4 W( e** Input - Frame Sync, Clock and Serializer Rx6 R# \4 O& y: C+ Y2 v7 J
** Output - Serializer Tx is connected to the input of the codec
" Z% N* R& K" {$ z9 B) W*/
2 c S. t; a6 Q: V# s- K' bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ X' L6 U/ n+ [ }8 Y. a4 ~, e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 _' ~+ p) b: l0 R! [* g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 H- H+ n/ K, a1 g q/ s| MCASP_PIN_ACLKX- |& \- [2 A6 w. {6 T
| MCASP_PIN_AHCLKX8 J, i' A. U6 L) D5 T! S, Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; v7 x8 a0 @+ u0 ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " ?6 }" H( ?; K: N+ n2 ^
| MCASP_TX_CLKFAIL
( _/ [- ]+ F5 M) [! D* J| MCASP_TX_SYNCERROR
, q- w# {6 T) v) ^1 N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 a# u4 e$ W, W8 H0 o! Q; X0 `
| MCASP_RX_CLKFAIL! q* X& {' g1 [
| MCASP_RX_SYNCERROR ! f2 s; d1 Y' _" w! |3 ~! C) m
| MCASP_RX_OVERRUN);5 w. ~+ A& T1 i# |' L" s, c
} static void I2SDataTxRxActivate(void)5 _: F9 a& M% N P
{
' u& k# Q+ u+ d+ \/* Start the clocks */9 u; p5 \5 {1 c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 r. L. ^( p: q8 ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- B9 x6 k; W8 y, a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 e# O2 j2 \- \+ c3 R0 Q
EDMA3_TRIG_MODE_EVENT);
' n9 X) ]4 y( h) N& OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / v R% \+ Z6 W# S% Q8 P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ v; J2 O Y C+ @2 F3 p) TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ Y) |" i7 b, n8 @0 K! f6 M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% L+ J( Y$ Q6 r5 ` e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" D) b; u9 W( k( C% {6 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ W0 d# V- l- S, D+ K8 |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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) Z# D& @- a7 M; j# c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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