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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" B1 v$ ^/ e! G8 u. Rinput mcasp_ahclkx,; n% p7 O* m. p* u
input mcasp_aclkx,, `7 `8 S3 u1 L4 ?4 R( y
input axr0,
! l! o, |+ _% g( s- i
. g- w7 _3 C5 r' K# d- X) q: X) Koutput mcasp_afsr,
5 {" z* F, G5 |- }: T" joutput mcasp_ahclkr,
& l' K: g4 o) z, w3 z5 Soutput mcasp_aclkr,
" I, b6 J! B4 l9 I6 S1 U) Woutput axr1,$ k1 O& `. u! D0 H7 }/ X: |
assign mcasp_afsr = mcasp_afsx;
b0 d2 m9 d& l/ w5 A0 |assign mcasp_aclkr = mcasp_aclkx;3 r9 ~, |+ }1 Q+ k7 ?
assign mcasp_ahclkr = mcasp_ahclkx;
1 B# W8 j9 u' @. j& _! O+ Sassign axr1 = axr0; 8 u7 U2 K a$ d" R+ I% U
5 M) @6 Q8 U8 ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- L9 Y' f2 V2 T: T( E( r% @static void McASPI2SConfigure(void)
& e4 E- c- j' Y, D- d d{
) v& C q R8 `7 L* s: T+ qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! X, ? z; J# t. D Z; n9 f3 K# A2 N4 |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( W8 _$ R4 A7 O% K9 w$ _( o6 h: mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& `: n) B( N; u& |7 n( F9 r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: K8 I: B! ?( y" G/ LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; X/ v* J9 H; P6 Y: i7 {
MCASP_RX_MODE_DMA);0 y4 f! s/ p7 R, T i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% A* p' l) [% ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# \ Y' _/ m# @9 u; K. d4 J( g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) V# W4 C( ^% U5 z, Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 G. v# @* O& o+ F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' Y2 @; v( ^' u2 I+ i& pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
b1 m/ Z8 B6 j5 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' c# M, h2 y: ?+ J5 \: C6 oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) |/ a) @* V! U+ J1 m" SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ N3 r, g, U' q) Q8 Q- c
0x00, 0xFF); /* configure the clock for transmitter */* Y% p. f! V- k; Q A) R& s, ?' R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* h. ?6 Y. _' @ XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / f0 e" B% z6 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) _& f0 L% M% A1 k6 D& t5 g! b3 T3 i0x00, 0xFF);
W" u% v ]/ T, H
$ O+ a3 |$ o3 M \/* Enable synchronization of RX and TX sections */ ) Z; {" l. N/ g7 b% j; m- f( E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 U& v* a$ m( k! rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 z3 B3 t! A# O6 y0 n1 W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 d% C# ~9 s% U** Set the serializers, Currently only one serializer is set as
7 n) y/ ^! y9 ]) }* t7 i/ K** transmitter and one serializer as receiver.
* ~7 ]1 d9 T8 i+ U*/1 J* J2 F$ Y, |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 E4 b! L6 Q, P; W. K/ ~ KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 n/ y0 T4 h6 o** Configure the McASP pins ; l, k3 C: G% V$ \9 B8 c3 H1 d
** Input - Frame Sync, Clock and Serializer Rx
9 a- b+ c- f5 c5 x3 r& _0 f6 c2 e** Output - Serializer Tx is connected to the input of the codec 4 p4 d- Z: T7 O) p$ B7 L# X8 Z
*/6 q2 Y& @( B& u8 e% t2 \- s0 `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. [4 ^. e: @8 ?- U yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, @ s Q8 W& q, D I; V5 [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 P: n, S8 L! b( P8 ?- O: o| MCASP_PIN_ACLKX
% l5 d: F) J( p9 s: C| MCASP_PIN_AHCLKX: X5 I: Q" a7 E2 g5 ?) b" E+ u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, e2 U0 y' ~" a8 Y& N) ~1 r3 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
c2 o4 n3 I& `$ Z" X| MCASP_TX_CLKFAIL " f7 _1 |% L& n" \) c! _+ }
| MCASP_TX_SYNCERROR
' ]) n5 ^% G7 q( } d: P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 k8 f% t. y: c+ u; X0 d
| MCASP_RX_CLKFAIL
# h, m" l6 W, \0 H/ V+ t9 D# {: r| MCASP_RX_SYNCERROR
( H7 C( t0 Q3 w3 T0 W| MCASP_RX_OVERRUN);/ O) Q+ E* l6 m3 |
} static void I2SDataTxRxActivate(void)# b4 |# ^3 U. t6 N
{( t/ Z# B8 a( G$ T
/* Start the clocks */6 @& u$ D1 [& r" e" n& p8 h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 y0 i( ]2 q9 E8 H3 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! o' y( O" {/ x- m2 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ L0 v$ U! [3 S# M0 a
EDMA3_TRIG_MODE_EVENT);
. m9 [! {9 a6 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! a- g; _- v9 [! m+ ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" S! N4 A4 B6 a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 d, ?4 ], D9 F* H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- l; Y2 e. I/ P2 X( u$ Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 k& {" x0 I% n' r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! l# f7 n9 h8 B Q7 Z+ wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( G6 g1 L6 Y3 m9 Q4 q: d
}
0 t* n: {2 B# T" D8 U) Y3 }4 H/ M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! o8 i7 k) \7 {- O
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