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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: `% f# |$ [ e+ d+ A& e2 ]; U, @8 z: Y$ [input mcasp_ahclkx,
# I& i; b) k! M- E" Kinput mcasp_aclkx,
6 A$ f" Q _) w tinput axr0,
( K2 {9 T9 v6 ?( j6 Q
3 a1 G$ t% \% A' [ J, D) C1 Eoutput mcasp_afsr,
3 L5 O1 m1 T j# i5 M6 [3 Routput mcasp_ahclkr,) |; r' s, N1 O* n' [( X
output mcasp_aclkr,* z1 T+ `0 j# G) @' n% B3 x
output axr1,
# ?1 |/ v- {1 G1 Y" B assign mcasp_afsr = mcasp_afsx;" _0 A5 j% p0 u+ w# p
assign mcasp_aclkr = mcasp_aclkx;% Q# c7 A; E) b/ T4 n
assign mcasp_ahclkr = mcasp_ahclkx;
" w6 m, _4 W* t! Oassign axr1 = axr0; ( l( j F& D% N8 t
5 S8 M) P7 S q7 A* l9 X) A% [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 a: L! R0 L) c$ e- D
static void McASPI2SConfigure(void)5 c* q+ v, w! \% m/ L* F3 B- l- T
{
* H7 W n% S1 I6 \3 pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, E- v0 ~" k6 ^) P6 YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* e; o k" }" n" u% d4 yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 W8 a+ L, T, g! O+ h; ?2 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- o+ n: w0 c' r: m% NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' E. l" H6 X) {& ~7 n5 D O5 A. Z
MCASP_RX_MODE_DMA);- D1 w8 ^. D; P8 z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, V( {3 P( [& M' _2 j. ]$ k" e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 l% C. _ c; Q0 a. ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: p0 Z0 K# u# {4 D: dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 P; P" e1 [ k1 [: [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 U0 u( |( @. N* ]1 ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& H# }+ q3 F& J* l1 h/ s. i ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( W( c7 O# G; U$ I- U/ r4 U D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 ?5 B0 w# f8 @: i3 C1 Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" g2 A5 H8 `, a0x00, 0xFF); /* configure the clock for transmitter *// t- O5 r. ^3 ~' ], _ g8 o+ g& G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! |# n: D& I' V. n: fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 e' T# ~3 |5 ]& I1 C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 r% }: l6 Z5 ^0 O8 T- ? Y; o. Y0 }0x00, 0xFF);, h' p- }! ]5 T* U2 M! D5 d+ p
: C% `+ N" h p+ T, q
/* Enable synchronization of RX and TX sections */ , S+ m: D, Y; D' y+ \( i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" R$ D# N% w6 M% d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 K: \ R& W/ w4 R3 u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, l( E9 Z- C0 r4 e4 t8 Z** Set the serializers, Currently only one serializer is set as
) T- |4 x; h; I- J** transmitter and one serializer as receiver.8 F/ f6 J: ]8 F' _* _5 H; f: u1 H
*/# s7 x1 g/ C! {& m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) ^8 ?. l/ h8 Z5 V; [! i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 {7 \- K* i: y4 o+ v- W) R& p: w
** Configure the McASP pins
& Z, J, f3 {; {# g0 K** Input - Frame Sync, Clock and Serializer Rx# }( |4 x# N, @' B8 m
** Output - Serializer Tx is connected to the input of the codec " @3 C; U) e- u3 N: J3 H8 j
*// a3 ~1 G6 J3 W, P! `% F% U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 q6 ^3 t" G: |# uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
L; p$ F( i7 M7 bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) t+ K4 C# @9 T' x, g7 D% G: H8 l| MCASP_PIN_ACLKX
/ O. W/ c! l/ r| MCASP_PIN_AHCLKX
5 n, c+ d9 c1 i) { m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, i6 X& @. p$ w) ]' J8 K- NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 w/ f2 s+ b# ?. A& t1 }
| MCASP_TX_CLKFAIL
9 a4 B; s& V+ Z( _9 k' ?# Q" H- h| MCASP_TX_SYNCERROR: C. G# ]8 m5 S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 w0 A" ]/ \ @! ~5 U2 F9 M$ T| MCASP_RX_CLKFAIL
5 E* g$ g9 ~) { e| MCASP_RX_SYNCERROR " b3 G G0 M6 q
| MCASP_RX_OVERRUN);3 b$ ~: U2 M O, m! L
} static void I2SDataTxRxActivate(void)
/ `# ?9 x0 l& g{
. k( ]0 D. ] `6 g- |( X6 m/* Start the clocks */+ @9 x& K) n- I2 G/ u' R5 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( H" N- D4 z3 q3 J( _. RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) |" A% V% u: ], Y+ n; |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 v6 S4 @. v' ?2 Q4 B' s3 z3 m
EDMA3_TRIG_MODE_EVENT);
9 M: d0 G [% h7 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , ?& R! U" c8 C# r! h* n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ e* B7 H. W% q7 N; [: Z, _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 x8 I7 b8 p& t9 y `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; j5 {' \) f5 o5 f# q! ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" _4 d9 X. A% I0 e( FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, H( L, T$ k; X4 e E& N. R. C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! }) C9 n* h N. F& U; k: R
} - w, d5 ]8 g8 F [5 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 B! @$ ~! [* {1 {: a6 L- _, V
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