|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, [$ @# H3 z& n9 D0 L6 z0 qinput mcasp_ahclkx,
1 @' L1 ^% j5 ainput mcasp_aclkx,- }- L8 v) F$ C* B( J. \
input axr0,; W+ P* I i( \. {7 |$ |$ K6 [
. {3 c H: F. t/ u7 s! @+ y' zoutput mcasp_afsr,
: I& M# p1 e% w6 Y- X7 ooutput mcasp_ahclkr,7 X3 q* j0 G- m7 h2 }
output mcasp_aclkr,3 f# E6 M3 V- Z" {6 ]9 Q/ b. b' X
output axr1,7 g; Y/ J2 ]0 I
assign mcasp_afsr = mcasp_afsx;
$ }2 M! v \' r% nassign mcasp_aclkr = mcasp_aclkx;
9 n+ k5 d l$ h. r+ X7 Zassign mcasp_ahclkr = mcasp_ahclkx;6 z- t Z) w' t; x2 G- F, Y
assign axr1 = axr0; & ]2 s+ i. D% _( C3 N2 `
. t$ C: l% `7 Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 X, x9 U u$ D" u! s: C' F
static void McASPI2SConfigure(void)3 i/ Q3 X: G" P! }" n& q( s7 u
{
$ `/ H5 C3 U8 T. n$ E" DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 ^! k* F+ A+ c+ kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 W M* P |$ N- W! v1 E4 s$ |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 A- g: g. H: b/ |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 _( s2 ~# `2 x. h+ l# g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, Q8 i+ n- T; n& i3 z& B* oMCASP_RX_MODE_DMA);& f( V- W$ s6 U/ r3 W# M; W: c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, y- i1 l3 f- ^8 ^" s2 D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ ~! \/ k3 `: [4 {, J% J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* M$ D1 r# @2 A2 v8 |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: j7 _. E% H7 C( |$ k% l! N* w' Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : j( m; x' N# }0 V. B, Z% E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& `3 @" k6 C' ~7 D2 |6 u( e7 D* |) y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- X _8 G4 {, s7 W) O/ u. z9 \* Z% W- o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 W2 i0 M5 T, n' S7 ~$ [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" M+ K" X/ X9 U) E9 l# b2 C: z0x00, 0xFF); /* configure the clock for transmitter */; Q- s9 ^' H* _" l# ?/ N, i" N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 ]$ {: V( |; Q8 @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 t) l: J' I; k" j( j+ u0 ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 C8 _/ I! p* ?0x00, 0xFF);) i- P4 q- |* M( o* S6 F$ ^
" j( O1 c9 e7 L, Z+ v" Z
/* Enable synchronization of RX and TX sections */
" a) h' K& C% V: c0 JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
I" U8 @0 f+ { S. XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 C& }& s" e5 A& V; n2 w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 v6 e2 O9 V- u1 Z/ E! @9 v( ^" ?
** Set the serializers, Currently only one serializer is set as
0 B; X" ^( i8 l( }3 C; H, q** transmitter and one serializer as receiver.8 [4 Z& d5 Q3 J7 ]6 |
*/4 J" i: n* \" l8 W8 ]* b2 w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" B' j, e/ T) Y2 E P9 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- s; e! s* W4 L0 F6 n) p** Configure the McASP pins
+ N7 Z0 p. [' D, l1 f' L** Input - Frame Sync, Clock and Serializer Rx
$ G$ ~2 a# l) u% H& A6 |- f# y** Output - Serializer Tx is connected to the input of the codec ; M2 e* ^: W2 p& }( A
*/
2 N: Q- i' |2 D" H* M8 ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 K( t2 s6 x7 L" c: zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, \) O' `9 g( {9 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# `+ F- g4 e/ f N& z( z| MCASP_PIN_ACLKX u- Q( c: ]" k. R8 x' E8 Z h9 E# M
| MCASP_PIN_AHCLKX7 C% n; n) j& ~( T0 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 N- j+ x/ `' x: u2 }3 i; \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR Q y; c( ~0 [
| MCASP_TX_CLKFAIL
4 H9 |& r, E- o( [| MCASP_TX_SYNCERROR# C" W q4 L: P/ H3 x8 f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & b! J4 Q! N/ i: u, c7 ?: P" K$ P) x
| MCASP_RX_CLKFAIL8 g* o, u/ i# N, @
| MCASP_RX_SYNCERROR
, T U6 G" M: }4 t7 o( j| MCASP_RX_OVERRUN);; ]: r* V+ w% C6 ~3 V
} static void I2SDataTxRxActivate(void)
# G( T0 q: y: ?8 C e{
0 q* c; b. ]6 q" G/* Start the clocks */
. P* \7 u3 R3 r3 \) \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 m4 j. L0 K8 I$ d: cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ `% k% u7 n3 f4 T6 t7 Z- U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& ~" d6 ]- Z7 lEDMA3_TRIG_MODE_EVENT);
, s( V- R1 s- A& s; _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 Z, }* w/ |- y- P- q: Z9 Q$ Z. KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 Q1 \: D! a) L- s# u+ X) OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 R9 W/ U# W* F) C7 z; N0 g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( o2 }% n; U+ p' H7 R$ |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 z; t' ]2 F! ^7 J! ]- X" VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) }& ~, P! e3 M* j0 V1 z3 ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, j' L1 A9 @6 J
} : o2 b; T$ \1 R9 [# W+ x3 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 q+ Z/ }" K" r
|