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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 F/ N* O4 g: P N. `
input mcasp_ahclkx,
/ G4 Z9 R0 A1 j" [- U5 }( g/ ninput mcasp_aclkx,5 c* Y# N7 ^1 w: o2 ~0 m
input axr0,
% x1 c- Y$ ]7 O+ R4 q* u' D5 v7 u# Z9 u
output mcasp_afsr,
7 @9 b( }8 Y% a Y9 d0 _output mcasp_ahclkr,& \* m+ Y; B. K. J$ f c
output mcasp_aclkr,
. U2 W1 M& ?* m. b. boutput axr1,
/ X6 G j6 E" m% o2 T( h2 { assign mcasp_afsr = mcasp_afsx;: p, N% D- \, M$ o5 l3 L
assign mcasp_aclkr = mcasp_aclkx;
6 Q/ j, p/ X8 @6 b( r4 s7 xassign mcasp_ahclkr = mcasp_ahclkx;
; a: }# X! m' [3 ~- v+ F. B& M; Eassign axr1 = axr0; 7 H4 _6 `0 g( g% ^5 c- a8 S" f: _& r' L
1 p- n; v2 F( v4 g9 W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " k* ^4 h: r: v2 r1 R( n: W
static void McASPI2SConfigure(void)
/ }) P1 Y1 F& W* a+ S: g! ?: k, z{
$ c' W' c$ j+ K5 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 D4 i; Z, i! @8 Z2 p6 I$ ^3 cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& O- }! S" _: n0 J* DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 u! w0 H9 q. G r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ ~6 r: w# M2 G( [- P0 UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 u A, B& M8 ?9 K! H
MCASP_RX_MODE_DMA);
2 _) r P, A* B4 ]% c- w+ c6 WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ p: r' g! p3 ~7 Q5 r5 _( U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, t! ~2 Y# B x9 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
l0 H2 w8 p0 v# Z7 m6 pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* u2 t, Y: r* q) Q& e; f5 Q9 OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 A% U4 |2 q- O! Z6 G& m) K1 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 a4 }1 R; m/ t& }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% [! P: k$ [( x& ?: t, } f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% Z- h9 _0 A+ O: C- V9 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 D2 b" s: x) ^# L0x00, 0xFF); /* configure the clock for transmitter */
" N \( h3 x0 o+ `1 |5 J+ j& [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' N" L% P! s+ c: F# h) X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 f9 s6 T1 w8 ~3 X' E+ E, t- H* P+ g) lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 [+ ?* b, `$ K/ I1 I! N: O$ A2 K0x00, 0xFF);: s4 R" c8 I u \3 c4 Y G/ {
) s8 ^6 o& q8 v6 C" ~; w: X/* Enable synchronization of RX and TX sections */
, i s1 C9 V" t* \8 l" L. EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 f. ^( j( J) o/ W; Z6 g( AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 s2 W) t9 ~/ H6 ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. N1 ]; Y0 ~& m- ^ \
** Set the serializers, Currently only one serializer is set as
* N% V( @! P* `% |/ e( e& t4 _** transmitter and one serializer as receiver.9 d: K8 E7 \3 ?. ^) U0 j4 j. t
*/
! l. {4 z, |$ t, v- C5 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
e, {. z# P/ T7 Z5 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 `6 t: |1 r$ c5 |" E- j** Configure the McASP pins
1 {' [' L1 q5 m7 t8 |; C" E** Input - Frame Sync, Clock and Serializer Rx
" v/ z- W* c! t9 h1 G# {** Output - Serializer Tx is connected to the input of the codec
9 Y+ ^/ H* }1 ~: j! Z*/# Q, J; [. |. m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ l$ q6 U, a8 Z2 p2 Z1 C0 ?- M% o% @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); n7 @% |6 g2 }9 e/ d1 o2 @2 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ A) M0 U; }2 R) U; D) l3 F
| MCASP_PIN_ACLKX
: c, n4 @: m; D| MCASP_PIN_AHCLKX
) P( Q9 `$ m- E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! S5 K Y0 ?+ b7 yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ M* l. K% D& R| MCASP_TX_CLKFAIL
) T4 E/ L) U% l% I# H0 w) e| MCASP_TX_SYNCERROR
: p/ p) L$ c" h$ O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 K1 K O8 O: U! m- ~" x7 e
| MCASP_RX_CLKFAIL
. } h, w; ^4 R% m2 O| MCASP_RX_SYNCERROR . Y9 {. Y7 F' F
| MCASP_RX_OVERRUN);( Q6 q; a5 z7 v3 [, q
} static void I2SDataTxRxActivate(void)
7 c/ f9 X: X* T0 A' H' v{
8 s1 @( @# Q! i( _9 d+ v, d" W/* Start the clocks */, Z2 h0 R9 P& ], q, l- L& G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. q4 C2 _; N, Z" G+ t5 MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# |4 w) P( U6 e Z4 M8 v( C! X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* L" ]3 m1 ?8 h& T, wEDMA3_TRIG_MODE_EVENT);' }! G7 I5 t' R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % L, `0 n8 G7 T! X& |# \% k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' {% s: i& R7 W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 C O: N/ i8 u$ N1 N/ |; U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* R# N6 L/ |! F+ f; }; [$ vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& {1 X0 \7 a' j+ R4 w# |& N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- T S- I8 z7 BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 X/ @" u, |3 H/ n; K% x} & V) t! F2 t: m, z2 t9 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - Y4 N6 B3 ?, h: H
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