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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% A. Z5 K2 d( rinput mcasp_ahclkx,
- h5 V7 N" m& C+ qinput mcasp_aclkx,
- x" o `: O4 ?* U7 ~# D! Jinput axr0,
- T& H$ Y3 l# G; a, C$ e- D- m# t* }) T8 t, a
output mcasp_afsr,8 H, @5 R) W+ B
output mcasp_ahclkr,& c# ]# o& d3 O
output mcasp_aclkr,
9 W" R: r8 B; N* j; r Noutput axr1,' q5 J$ W& R' E# H' }+ s8 W
assign mcasp_afsr = mcasp_afsx;) D! @2 q R) n. ^$ H
assign mcasp_aclkr = mcasp_aclkx;: E, Q/ i6 ^/ V* {: O7 Y
assign mcasp_ahclkr = mcasp_ahclkx;' z" Q) j- K* G& [
assign axr1 = axr0; 0 J+ R* x' H# C$ b" |( g6 K( C4 W3 ?
! \3 u4 h2 h9 x2 s2 I1 _& i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, @/ U% @: \; B) ~' `* \& ]static void McASPI2SConfigure(void)
: y% g6 G0 t! E% `{$ D* S8 {& }; }& E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 M$ T9 R) L V# Z. M3 T$ EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 K% z4 C8 y# M0 l3 ]. A! eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% K1 l' p9 \( _1 Q' P; n' ]: \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* W m0 s) }& g: Y+ mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; ~) e. e: c# {/ PMCASP_RX_MODE_DMA);2 X U9 j7 {) I% Q4 C4 \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ h' f" g9 e6 w. s) [# nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 Q+ Q" N/ s) f0 \0 zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% r J1 b v! W* XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% t! i, Q' d* V$ Y) o' M% s' p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 K/ O2 r: r* w+ F- C" p" p9 m1 Q( OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 x( l# B, ]' j: f4 _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ G3 g" I5 _; EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - H$ x5 d; z; _ U/ v+ T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- @# Q$ M3 v) W8 ?9 h6 F7 o' U0 [2 K! k0x00, 0xFF); /* configure the clock for transmitter */; K/ q% N4 \7 g u& I u# [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 p: m0 P# `' H1 S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! }# b/ Y% f* y8 B, P _" KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 W6 [0 W2 m# n# s/ Y0x00, 0xFF);
! |2 \, b6 [: p. P+ z T, U6 C h/ B% c, f+ [
/* Enable synchronization of RX and TX sections */ ! r+ c, t, s8 n* q$ R& U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 n0 ?" z4 M' B- R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. w; _: d; ?7 B1 J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. ]1 x& {8 \+ o* v# O' b
** Set the serializers, Currently only one serializer is set as5 q! ]5 Z! X' G2 s( Z
** transmitter and one serializer as receiver.. X8 D2 _3 C7 h) n9 j+ G1 ?- d
*/
/ O1 c& k& l- ]% M8 L5 F, y$ LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* V" r6 g1 ~! O: M' I* r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ m/ N1 S/ I ~0 u3 c% K0 O! A) D0 _
** Configure the McASP pins
/ q! I: T& C0 {( p7 p% l9 o** Input - Frame Sync, Clock and Serializer Rx
2 W1 a$ m* D) X! L8 Z# r** Output - Serializer Tx is connected to the input of the codec 2 c6 N+ f+ f [7 E
*/
5 F2 D; U/ ~7 RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 Q. s9 F$ I2 O; C4 b7 Y' M/ g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 W6 E$ ]" i7 |$ ]' A- t0 L! r; `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" }" e* o) o0 {! R7 @( E
| MCASP_PIN_ACLKX
) i1 R5 @% P5 D+ h| MCASP_PIN_AHCLKX' k0 K1 \. l; L. {: a0 \# n" e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( |' q R; c: I+ j* D, R0 t$ _* E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. ?8 `1 o' X+ || MCASP_TX_CLKFAIL
9 t$ l# T; Z" w' R/ n W| MCASP_TX_SYNCERROR+ R# G2 U0 a3 b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! M7 W, l: _$ w$ F3 B* m$ G& \8 x| MCASP_RX_CLKFAIL: I4 E. U0 m g1 _* M9 A
| MCASP_RX_SYNCERROR
( I4 Y0 W% L5 U- ^1 U) S7 v| MCASP_RX_OVERRUN);- i8 i3 G$ K) S! Z: O) \. m b
} static void I2SDataTxRxActivate(void)0 l8 ?% U8 |6 T
{% K9 H3 V3 W7 c) t: |, o
/* Start the clocks */7 ]; u* t) l9 V0 {+ t7 H G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 R: P3 t% p& ]: Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" Y" a; r% n( T2 |! IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 g: w* I2 q$ {0 m" ~' U8 K& @EDMA3_TRIG_MODE_EVENT);
$ m, R% }6 U- dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( F1 q4 W. y# T* `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 n' Q- }+ I/ `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 g' J* X! U9 {- r' vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- s& }& F7 `( y! `$ S# d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" u. A9 ^1 h% b8 ?4 z7 {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 A7 p F+ G9 Q& Y3 i* YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 T! ]% M' |: k9 o4 a} $ B3 @" t3 n+ S1 m% t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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