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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ D2 W6 A1 o, b. i, N
input mcasp_ahclkx,9 _$ [0 _- d) e' L8 o. |! K
input mcasp_aclkx,- Z* M3 z$ `6 M& f2 n) S" q
input axr0,! t( J( \. n s, m6 @, @+ m
. ], B* O( J1 _% U$ [/ {
output mcasp_afsr,: T3 {5 w4 w9 v+ E x2 k
output mcasp_ahclkr,1 s5 S, o7 X! M3 {. k+ W
output mcasp_aclkr,
! J7 I- \9 v; H* h1 y# ]% P' houtput axr1,
) l) K+ k' v' l4 o assign mcasp_afsr = mcasp_afsx;
3 V: c9 N+ u0 @! m1 l( V' yassign mcasp_aclkr = mcasp_aclkx;3 a; m/ i( b. a& f: C2 v- P8 Z' p* E
assign mcasp_ahclkr = mcasp_ahclkx;
9 Y& {* h% Q1 `. q4 a4 g0 Q& Q7 C3 q, Uassign axr1 = axr0;
. ~) \) i4 d& }( R) M, F8 o: _& e6 r) q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! y2 Q; }1 O2 x2 I- |* |
static void McASPI2SConfigure(void)
( j6 R! l+ h' I5 \$ r{+ R- k( k4 y) A3 U" [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, c; W* n. @6 IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 l% y+ Q( a' X4 ]& L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) V; [" y0 g3 X1 _9 P) d& }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) X3 t7 @% P+ H; UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( ^+ u& t, G+ C4 u/ pMCASP_RX_MODE_DMA);, w8 Z1 s/ o5 B$ V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( ?. d F' J/ R- u! J2 d; w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& W5 k0 ?* @3 n" E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# R0 C, Y. @+ d' i0 ]8 @% C: m6 q5 dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; w( E& `% U9 d; x1 Q7 u0 Y/ g* t, kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( r: \6 a* V6 t! X+ N1 t1 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: N4 L% M9 z2 t+ e6 fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 j! }1 ]6 d. ^- W! g2 u. x. Y* i# }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 B. |0 B% a* ~+ e$ f. jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; ^: a6 [ U. t: f R0x00, 0xFF); /* configure the clock for transmitter */4 d G; l9 J f- n0 X2 d2 }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ ]# l: i: X9 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 O$ A1 }3 q; q9 I7 C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 i7 H. b* r$ t0x00, 0xFF);7 A8 t! [; l' Z3 Z- L
3 Z: G6 `9 L D2 V1 b; ^ t; i5 J
/* Enable synchronization of RX and TX sections */ / } T* W% x) G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. w6 c4 A2 J6 I3 o. N) D- f' x: sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 T7 Z* ]2 X! z" \$ c6 |* ~" ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; {3 r, A, O6 U2 _4 ~4 N
** Set the serializers, Currently only one serializer is set as+ ^/ D ~) G# b# @
** transmitter and one serializer as receiver.
) c: |5 ]* M; w3 a0 O*/8 y5 X) M3 Y6 n$ [# P( C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* N+ ?& x; h5 h% g- j6 s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ N2 C! ?7 Z1 i; A' f6 Y; ]** Configure the McASP pins 5 }6 M/ X; b0 \5 P
** Input - Frame Sync, Clock and Serializer Rx/ J+ y: k3 X7 K+ M k$ ^' { I k
** Output - Serializer Tx is connected to the input of the codec
2 X" u) m! o0 Q% Q*/
& k$ D: i, D9 ~/ W. T6 v3 y+ ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" z1 k4 ]+ t/ w: _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- ?; |% y6 M' \3 ^% R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ \, }2 X+ j) n/ v2 W, A. H4 u1 u| MCASP_PIN_ACLKX
+ E' P' N, U. }9 s# z; ?| MCASP_PIN_AHCLKX2 x: A7 w; Z/ ~" S$ X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 j7 S. s9 i1 o( B9 j8 n7 Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 ^, T' }2 ]0 y2 R% W% U
| MCASP_TX_CLKFAIL ) X& P4 S0 x9 B; j+ O3 o8 \! m
| MCASP_TX_SYNCERROR
: k* _: g2 Q0 E- q# H& z* J7 b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # S0 E# c% \$ H. W$ o
| MCASP_RX_CLKFAIL
0 a$ w ?9 F+ b9 K| MCASP_RX_SYNCERROR
* X" h& e! S. U, Z; _7 M P| MCASP_RX_OVERRUN);) R4 q" o$ P: I6 S+ B4 u! t
} static void I2SDataTxRxActivate(void)( d% c' @- F+ L% E
{/ f4 n- n/ u d0 b
/* Start the clocks */
) a' Z6 Y: \4 I, ?9 R6 l3 f& h7 OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% h: D' G: b3 e( I q" FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 Y @* M: M3 V4 V* l- `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 A, t" J' t2 J1 q2 T# q& K( D5 vEDMA3_TRIG_MODE_EVENT);
, g( y. _2 o; P# v0 }7 B! B3 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & w1 m& D5 I! A" i3 O1 `) J* r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ D6 ?2 N* L4 j6 C) y$ bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. K/ J2 L6 ]7 F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% q, w- C5 n; h% ?: @ c. L- }+ p2 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 Q9 ]4 c- u6 PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* m8 D! ?- d" Y y! t P% L; mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 W' F% f8 x+ }( L
}
1 T/ A" r! M% Y" d) H+ X7 A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ j1 v6 _% D: s, ^, ^/ @3 r( i
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