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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 a7 g# p* r- K' Vinput mcasp_ahclkx,/ w4 l2 [% f8 Q5 |
input mcasp_aclkx,$ f% p; R5 C9 ^! T
input axr0,
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; C. @- Y, E- M8 routput mcasp_afsr,
( m5 n b- a3 N( { x6 X0 U& Y8 Aoutput mcasp_ahclkr,5 i7 v# i% F0 o9 h8 H1 S
output mcasp_aclkr, J, }0 Y: e% P8 ]0 k; t
output axr1,
9 v g- { v; {9 \/ s7 f assign mcasp_afsr = mcasp_afsx;4 `9 {( z) A1 l# U
assign mcasp_aclkr = mcasp_aclkx;
9 z1 |* P7 E% eassign mcasp_ahclkr = mcasp_ahclkx;
( }; x2 G* k' _) u, p7 iassign axr1 = axr0;
# T% ~0 _3 l4 t1 o& e+ K6 l% ]( k
/ H. {2 R( T. A( J/ @. X8 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 l) L8 g- i- j6 x( n* x+ p! @5 N
static void McASPI2SConfigure(void)+ T0 x% f& h D+ I' [
{
4 \, j7 ]' n& E. E' LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 |! o3 `9 Z* i/ zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ \% ~4 a* H# |4 L; S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 e) Q9 {" t1 G/ @" c5 @( d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 x" O4 ]) \- QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* B6 B" o [8 b' FMCASP_RX_MODE_DMA);
0 O; s- O1 \# V. _" h9 c+ JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 w8 G$ z' l9 I. J- o; w; LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' n3 U5 ?8 x- @/ K& T8 _3 @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 O% m- H5 `6 O8 j3 h0 c% Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* r% K/ l6 x5 M u. QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; K6 Y, o9 G. M2 M+ J5 R% YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 v$ H- G' [ s, v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* k8 r9 T% y$ _' C% a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 u+ L' P7 M3 {& EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( b. e) q& H5 K' _0x00, 0xFF); /* configure the clock for transmitter */$ d! K" F1 I, F* u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! c& m* \, T' y: d. o+ P; YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 W A, D4 z4 Y6 A/ l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 A. b: D7 P5 C$ m0x00, 0xFF);3 m* p5 P1 Q( b$ x" t/ R
; j+ Z' _) q; x+ ?% q/* Enable synchronization of RX and TX sections */
# V* O K* f2 @; L- r! vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 U! n* J" w0 ~! PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- v1 @, a B) W7 ^1 P9 oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 N# s" u& A+ T# W* h** Set the serializers, Currently only one serializer is set as
- A- k6 ?% h3 b1 L& d** transmitter and one serializer as receiver.
( }. W# V# M6 _6 V" ^$ ?; u*/
; m, t0 x4 Y+ v8 Z0 p! O1 i9 j8 h3 N- SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% I: c7 ]- N4 ]6 p9 M6 h: M; {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" P: a- x( [; |! Z+ M** Configure the McASP pins + \" j4 {$ b$ c- w! K( Q
** Input - Frame Sync, Clock and Serializer Rx ^; b: O9 K4 |* I
** Output - Serializer Tx is connected to the input of the codec
. S5 v5 a0 h( q( u*/
3 o# M8 }' ?. h) [- pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# |- i; V& j) G6 i0 H! V) G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# \/ R9 ?' \5 q7 z# X7 aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 o+ O$ ^, G) }# g0 V3 z; y7 Z
| MCASP_PIN_ACLKX1 T, ^1 z7 |- E- ?
| MCASP_PIN_AHCLKX, m* J! p: Z$ p1 N! P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 B: N( a7 f, U6 v) PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 u( {0 o( z' |' g4 n1 `| MCASP_TX_CLKFAIL 9 Y: f* k* W( i9 f! D5 P
| MCASP_TX_SYNCERROR' q- T7 q- K& B$ N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) M$ Q) v) A i( d) o7 C| MCASP_RX_CLKFAIL0 }) z; n; O g" H8 K- W
| MCASP_RX_SYNCERROR
. S% p. E0 z- M4 f3 I( y; F| MCASP_RX_OVERRUN);
& m- i: h# \: K) ^. `} static void I2SDataTxRxActivate(void)( x$ ]* e/ B& u: i7 n! q
{) M4 \4 z0 Z r6 L9 ]
/* Start the clocks */
( y! {9 U4 r+ M- U1 vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 u6 }% M# @$ U! cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 P# f# S8 q) i# e; i9 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 \& v( E8 \8 ?' P9 C8 C' \4 Q# Z+ b7 ]7 iEDMA3_TRIG_MODE_EVENT);7 N* e) b1 J, P( A3 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 q( }# u) Y/ i6 w0 A2 Z; A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ x6 g! q' {. Z. e% |: t$ gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, r' t1 Y9 x' x4 ~7 t5 uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* O* N1 b/ ^ O R4 F( K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* F% C* I4 o% I; nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% h% i, _3 U+ }% r; c& {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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