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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 N v* D* L0 `
input mcasp_ahclkx,
% s# `# V* t b: m: rinput mcasp_aclkx,
- b# O3 i2 g6 I# o( \; t( p( m- Y; Sinput axr0,
; x) W6 r" W6 o
9 o/ u7 m' y$ }+ h% ?0 ~output mcasp_afsr,7 p" O) ]+ r' `! K
output mcasp_ahclkr,
# F5 f, A9 X, C0 O3 Woutput mcasp_aclkr,1 a* n9 r, d# H* u7 W
output axr1,5 h0 ^. _9 M h7 m+ H/ y
assign mcasp_afsr = mcasp_afsx;& A+ w, M- |+ @" g4 L( J' B5 Y( c
assign mcasp_aclkr = mcasp_aclkx;
) g8 `9 y2 m/ [0 A kassign mcasp_ahclkr = mcasp_ahclkx;
$ R# Q1 Y: S3 b. r$ n/ C% Rassign axr1 = axr0;
9 D( p" f6 K) j0 }* a) t: |7 J) U
* ^1 H5 k O* ?. ]( W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' p$ Y- L; s1 N5 i
static void McASPI2SConfigure(void)
: Q( H& S& [; J' @) D( L{
. q. e8 s4 R6 kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% _0 z; P* v8 yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 l, d& A% f* G3 Q) R B9 b+ PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( A0 c8 P$ m$ B# K8 XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 r( K( V& u* IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 s9 u2 F U" k( o$ `6 `' AMCASP_RX_MODE_DMA);! K; _$ [5 U7 U: `4 L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' J* p0 p9 W) j% H( L# l; fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ h" ~& f5 P; A2 ?" R5 M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 A7 }$ G$ X$ T3 P& `. s5 c& i, U, JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 e9 J; c2 r- d" O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& O6 d6 l5 B4 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& s5 C, W) l0 V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% ^8 }/ g& ^9 x7 _" u$ P3 C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % `3 t" a9 \( |+ M3 v5 `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 V+ D2 u. {# ^# C4 g
0x00, 0xFF); /* configure the clock for transmitter */
# m7 `0 A5 T) z" a$ P6 [2 G( rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: E0 b" R, l- h$ K( V. g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) G _4 X& Z; JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ |2 q! |% F5 _0 v. L
0x00, 0xFF);7 d0 K5 w! p) b `% n
" j: U* m/ B# r5 V
/* Enable synchronization of RX and TX sections */
6 @2 [ l q; [$ O4 HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 H( {2 S+ g' W2 z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); [4 Q1 d+ N+ F' C% }3 y* ]1 T7 l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' J8 O1 v# i3 I7 ^9 r" i, ?4 L
** Set the serializers, Currently only one serializer is set as
|+ u5 c; O3 F8 \7 ~9 C; X" R; t* b** transmitter and one serializer as receiver.
P: E+ T3 e+ U+ l*/9 e. h; }/ [" n( {1 h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 V( `* \2 m6 T2 A1 qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" f6 y2 Z: ^9 x+ T/ S: P- U** Configure the McASP pins 6 g" z; V) o4 a; y
** Input - Frame Sync, Clock and Serializer Rx
- o7 c4 I) v# x* A9 l* |$ z" O$ v** Output - Serializer Tx is connected to the input of the codec % Z/ ^* b7 M% e
*/" P% v( B9 A* ]3 n6 x, ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" c) \! O) q/ C |" T2 V) r" ~% r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 m! n9 F! q) i+ y. y! E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ E0 p4 n& l; S& m, v' M% }" s2 @| MCASP_PIN_ACLKX
0 [. M! @ `2 d- w/ }: N5 X| MCASP_PIN_AHCLKX
1 v! }) k* t' u" b* O; w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 M# m8 n, m& Z, o5 B8 R6 XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) T# Z( a& ]) T5 R' D& w' z
| MCASP_TX_CLKFAIL
u# x# Y6 g6 Q) M- J, F/ u| MCASP_TX_SYNCERROR+ [& y* {" s) t" t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 j* U- {7 e& m, A! p| MCASP_RX_CLKFAIL
7 E+ A+ Z# G* ]1 f: G [- y* o) y| MCASP_RX_SYNCERROR
" d4 j$ G- K' \| MCASP_RX_OVERRUN);# l2 T: c3 y* m
} static void I2SDataTxRxActivate(void)
7 u0 r# x: O4 e% r, K# h" Q{
! Q3 y" ]2 T0 v; R, X& e& q/* Start the clocks */& h) c, c' E5 ^) h5 Q5 \0 X& B, W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* B7 j M7 p& _9 _1 I+ y x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! E$ Y! c% ?7 u: }( vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 s! W3 ]/ D, f, H3 l0 m
EDMA3_TRIG_MODE_EVENT);
' X/ S2 z+ b! i R JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 m! S4 Y$ [4 ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 R$ X( \$ Y. e* Q: ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& O6 U+ _$ x2 G9 O' r4 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% H. S3 C: g' b% J) twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 n. G7 m. f' O* _" K) ^2 P# K4 }6 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; U% {7 A( a9 X8 W5 kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& ]& p$ W; M7 v6 e/ y5 ^
} 0 ^ g" [* n6 V7 y- ?& P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - ^3 m4 B3 p6 j( j3 {& f# b
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