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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) X+ N6 {& U% D& W2 O4 einput mcasp_ahclkx,& A2 n H x1 ~: u
input mcasp_aclkx,1 K- ?# Y2 H' Y: [4 B
input axr0,
8 u$ t% N& X. g- z
" f% i( q- F/ Z$ {. g7 e# `output mcasp_afsr,4 j/ N3 J( \$ E% |& ]* \3 c$ t
output mcasp_ahclkr,2 X1 U. F8 I; `; V6 W$ n E
output mcasp_aclkr,
' N( Q9 g0 U; P* n2 ^5 Eoutput axr1,. l' H& x+ v( a8 j6 I
assign mcasp_afsr = mcasp_afsx;
2 L# c+ G* E6 B3 H3 t2 }assign mcasp_aclkr = mcasp_aclkx;3 o. c5 a; U* V4 ?: J- v4 Q3 F
assign mcasp_ahclkr = mcasp_ahclkx;: W8 W% w/ r8 R6 M
assign axr1 = axr0; 6 ?- l* C! c! Y1 D Q
1 h) U* ~" [2 y$ l7 q. K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ?3 l5 H2 h# r8 A
static void McASPI2SConfigure(void)
+ m' Q& N& S/ s" t$ a9 M{
, U# W) D5 k- [+ YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% c; i1 A! t" G0 ?1 T/ B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 i2 ] b5 r: }( I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; B4 @9 [$ h+ C1 @ eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* Y: R2 y4 I) b& _. l2 Y6 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ M% M/ d" e8 u" k" V
MCASP_RX_MODE_DMA);, L6 M. ~. b& y! p3 m$ |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 h3 `( A/ K! ~9 [; m. lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- r' O2 {. N4 K* |* DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 a# e3 i- _! i& e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 X2 O4 ~" M+ R! E; W( [' _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % `+ h$ y: f7 ?* E$ h1 Z: t1 C5 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 n0 r- R1 r- r6 v% h0 E) JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); m) E0 e! u' ]1 H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 T, I/ v# o" Z) [8 j+ P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 s. w* B/ p: r* x( O9 U% u4 T0x00, 0xFF); /* configure the clock for transmitter */
8 h2 D$ B! V2 x" p" E3 ^. fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* V( b6 w& c% p# Y* J0 _* S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 w* F3 K: o A6 N' Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" F) d8 M, g3 l- {2 E0x00, 0xFF);2 W* h I' b+ g4 R9 F
: L+ Z- {: r& J* [1 M
/* Enable synchronization of RX and TX sections */ * Y6 U% w0 Z0 H9 h/ `- \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 t" U* g4 Z# N6 e F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
`, ?* g" ?# k9 d2 o, {8 \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) k$ k- r9 ^& i( X" g/ J/ M
** Set the serializers, Currently only one serializer is set as
7 M6 n1 v6 e$ x3 T' C9 m8 s- Q** transmitter and one serializer as receiver.
/ n. P9 y" t, ^9 y' V, k*/
# f( s6 q, _- c) `, A) nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 T, z9 L$ l( P% c; Z# H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ T% [* K0 U9 S4 U** Configure the McASP pins ! r* f$ s/ V: m3 c8 u
** Input - Frame Sync, Clock and Serializer Rx
; c" `+ n/ s; s% c$ o** Output - Serializer Tx is connected to the input of the codec
* _/ b% S8 Q; g*/
& i1 D$ Z+ n8 n: ]' c% V) l' iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 A( N7 g% D! M2 F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 s# H( b7 W* `+ K8 z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. G8 K; `2 e+ f8 I6 P; B4 I- _- y| MCASP_PIN_ACLKX. F+ A# t1 D0 Q; V' p: c+ C% q
| MCASP_PIN_AHCLKX
% x1 r3 K1 l# u+ S6 A; g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 L* |6 F) x1 ]2 [$ w) M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 K& @0 l1 c. Q& q/ N% s. t| MCASP_TX_CLKFAIL 2 R* M4 l5 z% z5 k, a# S* ~% {
| MCASP_TX_SYNCERROR
; K1 X* F4 l0 {7 Y+ c& r- N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - A* b* [8 p% c: s0 o7 P s) c
| MCASP_RX_CLKFAIL
& [' r+ q8 {4 [" R$ _| MCASP_RX_SYNCERROR & _* x3 g6 z$ C P6 r3 z
| MCASP_RX_OVERRUN);! w/ J8 h e% B. e; ^ T' N( p5 i
} static void I2SDataTxRxActivate(void)& A, Z$ R5 k" ]: W; |
{3 {, `' O0 {3 v% \. R
/* Start the clocks */
% e: t2 T1 @: Q% L0 N' o, ~3 YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, g/ _9 N8 R, l+ BMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 @# M; |; k- B# z3 x$ W2 B, E3 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- Q4 W3 L' R* H
EDMA3_TRIG_MODE_EVENT);
( }1 L/ x( j! m. O/ u; z: `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 i( ?. Y0 F7 t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, ?, ?6 m/ U# ^4 Q8 aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 P- X6 n) j3 J+ o7 a! ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- d! T ^4 ]& a& ~8 L8 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 I Q$ }5 W; {) T. N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 q$ \/ [" |2 M) m" Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ ?0 h' T- r4 @/ Y( V& J, U
}
% p( b) W/ ?& o) v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
' N5 q. g0 |& X0 ~2 ]1 g3 q. S0 C |