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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 H) J, m3 W6 {4 U) @* N( ]
input mcasp_ahclkx,
3 g5 c8 M' a1 M6 b# N& v$ t5 oinput mcasp_aclkx,
m# g# ?' o/ R8 r" q$ q. Einput axr0,7 ~3 n$ X* P* U' P) v
, ]% P2 }2 Y+ ]# Woutput mcasp_afsr,- m9 i/ q( {0 D% X5 {
output mcasp_ahclkr,
1 `( Z0 C# @, Z9 y- Routput mcasp_aclkr,( v- u# ~' Z2 b
output axr1,6 r( ~. j7 r! M
assign mcasp_afsr = mcasp_afsx;" }* i: r/ t+ X7 [( j& R2 n
assign mcasp_aclkr = mcasp_aclkx;. P3 E$ X& m5 ^/ V) h
assign mcasp_ahclkr = mcasp_ahclkx;
& V+ `; z# t; q. G% u# j4 Xassign axr1 = axr0;
, c# \. Z# K# y" K; D5 P! G; M, G) ?1 Y$ _0 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 d" j, r- X" x9 Ostatic void McASPI2SConfigure(void)& R: o: v5 x9 w$ p# h
{
7 Q! i7 ~+ B6 J* t0 ~1 }, xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! ?; _9 g& V* h P4 h4 s( DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 W: ^% @( ]; @- o, u! QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 m6 P& }" B" J% B2 mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( B$ ^) a/ w' N5 W( }% tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, T* y$ x% _9 z2 k) v$ }MCASP_RX_MODE_DMA);4 v. i8 t1 |- N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 X1 i# R6 t9 j! FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 X- p# ~' i( j2 Q* y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ X: F! e o* C' {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 n* @1 d4 n; b2 y( nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 V- ]" w0 E9 j$ I! o/ @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. t. }* L. A. Y1 ]5 P' N, I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 X8 D9 a( [6 s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% `, T" [! I. \4 H. l0 a- b; LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( u6 B5 r& Z e8 X/ o+ t* f, R& V% Z0x00, 0xFF); /* configure the clock for transmitter */7 c3 p% |2 I" |9 E3 T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ r' q* Q5 {& c% B g5 y& o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 U8 b; w4 \ p, c: j2 ?! z9 z, M1 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* |7 u* Z! s& t! d
0x00, 0xFF);
3 T" q+ w4 N; R0 m3 q
* P" Y. r" T4 @8 W/* Enable synchronization of RX and TX sections */ , E7 s7 Y# y6 E4 w# p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
`& s0 v+ J) MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: D2 o0 G1 m+ w1 pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' e) |2 h* V' M _
** Set the serializers, Currently only one serializer is set as0 c7 T- x, v2 e" k# ]
** transmitter and one serializer as receiver.& l3 m! t. S: a. u. S
*/
0 B$ o; b9 i! n2 j1 f4 XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# a7 j, ~0 V3 K5 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 Q+ H9 l# u: P( M2 \; } G** Configure the McASP pins
4 j4 r- b- U0 H** Input - Frame Sync, Clock and Serializer Rx8 d: t2 O1 e( U
** Output - Serializer Tx is connected to the input of the codec ( O( z* \4 x& m4 V7 q
*/9 S1 p; N' e# z+ W3 Q( f j+ F, B% Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ D6 {& Z8 R) L8 g# p1 vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 U9 c$ i" N8 k. s3 ^3 J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& x! N: P$ Q' ~| MCASP_PIN_ACLKX
% w' q8 N7 W. S3 D9 e, m| MCASP_PIN_AHCLKX; W$ z, y8 P, _3 |. @* `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ V2 g4 a" K, Z! t" A) `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % z' Z+ D2 A7 k+ R4 A$ c& J7 b
| MCASP_TX_CLKFAIL / \1 d( f0 v7 F5 L4 z" i, c
| MCASP_TX_SYNCERROR- q; @# p" A7 ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# b( Z+ J# o6 c- M+ ]+ M| MCASP_RX_CLKFAIL
: a# g& i |/ [. M7 I| MCASP_RX_SYNCERROR
* X& F" A% [; U| MCASP_RX_OVERRUN);9 G( A8 x2 a5 ~8 I4 W% k7 l3 z
} static void I2SDataTxRxActivate(void)
7 `6 h: k; W" c& G) i{
3 B0 t- }3 ]# Q8 y, {% N/* Start the clocks */
/ z& w S% G" w* S0 W; s+ LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# q6 F. g7 `0 d, H5 Q. I a3 F: g; kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 y- Y8 d4 B" J; r2 i0 G4 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- \+ b; f' }2 X- ]. `! a# |" `' r, vEDMA3_TRIG_MODE_EVENT);+ P3 ^ n: t$ l( o ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 R8 r5 z) B3 \( m0 T& ~ t7 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 |! Y4 ^% [6 B' B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ q1 D1 c$ b3 j# h* r6 F QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 ?9 [$ a4 l9 t2 k* `# B' Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ I; Z3 Q# Q5 z" X0 I7 E) YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; ?# V! a' S6 z" X1 R, c9 e$ S5 MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# E5 L k! y& l' @$ _} 3 ^% C! Y: B _; Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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