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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( \: E- }/ U3 f8 a$ x# Dinput mcasp_ahclkx,! {; c. w V8 ^# E( _) S1 C$ v
input mcasp_aclkx,! T1 X7 X7 ~' Z2 f1 W7 S: N$ R
input axr0,4 o$ }, t+ y; L- N' v# C" x' Q
* b% j# l. G) u+ k
output mcasp_afsr,7 }$ u. }* A! \1 M# J. F
output mcasp_ahclkr,
; [, b |: q; o- I+ c+ }* foutput mcasp_aclkr,
; P: U1 [: ]' a5 z: Soutput axr1,
- V/ w! o+ e2 ^) \3 ?, k assign mcasp_afsr = mcasp_afsx;
, s$ O! v a( Z9 _assign mcasp_aclkr = mcasp_aclkx;" ]2 c5 \; G" M* o. d" g
assign mcasp_ahclkr = mcasp_ahclkx;
! ]; t0 d5 ` t" s# Qassign axr1 = axr0;
5 [4 g& ~6 ?) e. Z# g; M2 Q" X% ~& n# q7 q/ R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' k% r9 }6 n; Ostatic void McASPI2SConfigure(void)
4 z$ u. b2 }% U: y8 J{
4 D/ F$ t U6 h) O* A( ]1 OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ n' Q& x/ A& u7 |+ d- O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# ^! [: X( Y; c+ t2 F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" f. H/ k% L- d# ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- L$ W* R; U; _7 g* w+ ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- `* S& D: k( O2 o& c8 DMCASP_RX_MODE_DMA);, ?3 |) t3 a: G% X7 }8 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ Q- S2 K K; Y v( e* ? |2 J: h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' K& \: |+ `9 b5 m8 P# f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 p3 n6 Q% J, S+ ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 n! u$ ` b2 `- W% t' z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* A6 i& _2 o+ a% a8 \) s& rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 y# {' X7 S- a$ n; |& w2 @! J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% \$ h. |1 y( S8 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! r: x+ P; q3 U* O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ b. o; b( v) t0 g% Y' G0x00, 0xFF); /* configure the clock for transmitter */
% l1 o6 c0 n( ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 C* V2 |5 T' L( x, h! Y- ^( s7 RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( o3 e$ }: Z& L0 `) K8 @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ z$ u0 t" F* e7 X1 Y% q0x00, 0xFF);- s& B }8 t% m! Z! l0 U, B
+ J4 U) Y- c8 x/ u+ |" t/* Enable synchronization of RX and TX sections */
; m3 V# a o3 r8 ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 _. E6 L% |* A! z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ `$ i0 F0 k! e1 x9 L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; `1 A |5 b% p. U** Set the serializers, Currently only one serializer is set as
, v9 Z9 r5 @, ]& l- V** transmitter and one serializer as receiver.
5 e3 p6 C, G- ~. D6 @3 Z. W*/# Y( X* }) W& M( Z/ V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% {4 x1 U! |" `) S& [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% [. B% U) j( b0 B9 N/ R** Configure the McASP pins $ L' Q6 O3 a* _4 A3 P% C/ h
** Input - Frame Sync, Clock and Serializer Rx3 I& Q: }8 f4 p1 a7 ]
** Output - Serializer Tx is connected to the input of the codec 5 k# f# |0 ~, s
*/
* r# K* X" Q9 b7 g/ A9 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 U0 h* U: V) L- C- I% _4 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! f! o0 i2 H- m% @& p0 P' f! C! {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ d' c5 l% Q) l' d3 n| MCASP_PIN_ACLKX0 r/ A3 j) @7 {4 v1 _5 J6 K6 X6 h) Z) ^/ w
| MCASP_PIN_AHCLKX9 q1 W; c( O0 S( u) \( D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: G1 \7 B% g H. ?" D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; \" d' d; y: o! v) [- l| MCASP_TX_CLKFAIL " A! j {! x" ?8 {, V
| MCASP_TX_SYNCERROR, u, u" z' `8 ]( L a- l( {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - f3 |( W+ }( e! b
| MCASP_RX_CLKFAIL3 P9 U% R) p% L8 g* t0 J0 i) L
| MCASP_RX_SYNCERROR
6 s4 ^% N4 a7 P- n; L| MCASP_RX_OVERRUN);2 B0 n5 C; Q3 y F S( c8 H
} static void I2SDataTxRxActivate(void)
9 I& f; I' O: j; a: v3 \{* o9 z' u+ Y- }! V
/* Start the clocks */
8 b$ F5 B& ?# S" @7 g1 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 m1 Z4 W0 F( ]3 G: { Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: P, A; T, |* p; w7 @' J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' U: h: x) c# X, M) H0 x3 M) Y
EDMA3_TRIG_MODE_EVENT);
0 b9 O- Z& O$ x; u3 Q9 t; PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 @1 ?! r5 }: M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ f6 V9 `9 U+ j0 h/ U9 X- G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 q4 A# W$ g4 ~0 |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( c, I9 E) V. l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* M2 D' C3 b8 @' K) h, Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 W" } x) l6 a# w5 S' [4 N& S) c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ t: r; ^+ |7 p
} ! o5 j: l3 {5 f8 F' @1 E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) u; X( @5 n1 K
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