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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) H; B% i9 I5 }
input mcasp_ahclkx,
( E1 }- q* y8 W: v$ N5 r! @- Yinput mcasp_aclkx,
l0 }5 B! l$ a2 X' iinput axr0,
q7 a' K* K- D- \0 a5 }& d" }, |1 ?0 r# }
output mcasp_afsr,
3 h! G; q# _" e# houtput mcasp_ahclkr,
' ?( [2 s7 |, X, i U J8 r% routput mcasp_aclkr,3 E" M6 Y4 } D. _
output axr1,: I G- ]% P' ^( j7 X/ z
assign mcasp_afsr = mcasp_afsx;, s5 l4 m( _, j0 T% v
assign mcasp_aclkr = mcasp_aclkx;
1 U0 Z% F9 V8 E E7 Y& g8 `assign mcasp_ahclkr = mcasp_ahclkx;7 K# l, A/ {) T1 }8 z$ o H0 H
assign axr1 = axr0;
# \: ~+ Z) w; `9 `. D. W! U7 `. |# a M6 {$ Y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : k* g! ~$ Q6 ?/ W
static void McASPI2SConfigure(void)
6 c% F2 F, K- a& b& L. J{
6 _2 c$ x4 z$ k xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 }7 B/ f8 Y) ?" d* U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; u n6 G% w% }5 ~8 x9 @5 b' ?- x% r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 R* \) n3 ?: Z8 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 {2 J1 p/ k4 Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ y" U; q+ X* eMCASP_RX_MODE_DMA); b- ~1 ~/ D$ l/ L' ^8 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% n& F# w; H/ t3 a' K( o7 r3 q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 W( C: Q7 h* S9 \- L% C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / |4 d a# \3 s4 ]& @+ j3 y2 Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# o2 }9 ~) W' ? E" t; QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / e+ c3 ~$ @6 J- w+ v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 ~1 c) v6 l! RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) o+ p6 [. k. G3 s# B7 N4 I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' J- Z/ ~. V% B8 X$ zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# s& R" ?7 G) d* D4 _' E! a% _0x00, 0xFF); /* configure the clock for transmitter */
) f& G- T# Q9 R! `+ YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' w, s! X3 K$ D7 Y( f- S4 k p- x7 [ mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 M# D$ _. w- {9 i: k8 fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: K, [/ F4 \/ @- M0 t, g0x00, 0xFF);
5 {8 u) S( j) s7 g2 @' H! K% Y' m H9 {4 L; i `, l' Z
/* Enable synchronization of RX and TX sections */ ; _1 G* }7 K ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ r& R) ^; V( ?6 m, E8 `, g! L& U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( `2 \2 v. K$ bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; |- V2 ?, C! f- M0 V* y** Set the serializers, Currently only one serializer is set as& {3 D& B! N p
** transmitter and one serializer as receiver.8 c% ^, M. P# j
*/
5 @: C0 r4 t+ Y' i& DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 L+ ?5 ?3 r5 ?: G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# b: v# e: O3 ^- {2 Y. \9 S** Configure the McASP pins & z2 ]7 H, P/ N
** Input - Frame Sync, Clock and Serializer Rx
* R& |3 D% e E+ _3 e$ b7 d** Output - Serializer Tx is connected to the input of the codec
. l) }' u# ]( s2 o4 O*/
4 u3 v/ X4 H% W$ ^- {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& e+ ]% w- d; {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& ]: H" V8 V2 a" m" J/ ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 S+ Y" f7 F8 X& ?, ~6 t t| MCASP_PIN_ACLKX
9 W: B! K* ?8 Z5 d3 P| MCASP_PIN_AHCLKX0 r' C1 w& v1 ?+ c2 l! g7 z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 J5 {/ d9 q" Q+ SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. I5 |) F: P' v; z7 n# e. E# ?| MCASP_TX_CLKFAIL
7 V8 E$ A2 g0 n, p* d- m6 w| MCASP_TX_SYNCERROR( E( c( A6 Z) c8 P# Y- S. i! E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 U0 }$ C( q( e) R| MCASP_RX_CLKFAIL
8 h! a% c8 y9 e2 j| MCASP_RX_SYNCERROR # k5 o: h6 }/ N, m9 W( _) ^( @
| MCASP_RX_OVERRUN);8 H; M5 v" K: i. a% p. `2 o
} static void I2SDataTxRxActivate(void)
, E7 P& v7 r: m" R0 K{
# @( O$ P. D- E2 N3 d' _: B/* Start the clocks */
3 J% [9 R! h5 h+ j' NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 E- N* t. d: Y+ ?% P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' U4 p f- W1 h' j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 f9 I; f! j- \- M' ^0 b3 e# n: ~EDMA3_TRIG_MODE_EVENT);
' J- `2 i) O9 X8 X9 w% }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; p7 u" o+ o- U- o, y: j: CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& S+ P6 r/ @/ t5 _" U& ?7 v9 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ \5 Y8 y5 `; r6 ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: r) I# F0 k& y0 Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( I# i' Y+ `8 S7 Q I7 f1 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 F0 j8 \ M* D3 x: y0 R0 ]& t/ nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" x: \$ k0 E" ^# T* c# e} + }. C; p: Y! p; h5 b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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