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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 v2 `1 ~ l; P0 ~: U
input mcasp_ahclkx,0 x3 p) o7 y9 u8 N
input mcasp_aclkx,$ a1 ~& P1 G/ B
input axr0,
4 o6 A3 `. E# s; O6 \9 K+ x3 E; s' ^7 j/ [; V% m
output mcasp_afsr,
6 m5 A' m/ {4 r- poutput mcasp_ahclkr,
: H6 G9 n8 u' c# ]) p: {0 J' t0 Boutput mcasp_aclkr,
$ s0 p/ e8 c1 c$ H! D) Poutput axr1,& S G' {; r' }, B
assign mcasp_afsr = mcasp_afsx;3 V. X, R8 X& Q/ N
assign mcasp_aclkr = mcasp_aclkx;
; I/ X! v; \( lassign mcasp_ahclkr = mcasp_ahclkx;! T. S4 _" J& r' y2 i1 J
assign axr1 = axr0; . G) b/ T0 E( ^# s- z) x+ T
7 z U& L3 ^; y- j7 z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 l) U9 s! e" t6 x- G
static void McASPI2SConfigure(void)/ y" e1 B+ s9 w+ r2 E, f
{8 P0 p( O. `: c3 q* D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& B M+ s& C8 \( H0 o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! M. S' V' ?. P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* g( D4 \. U: f, a( c+ d% JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% _! t; Z8 p) z$ S1 x/ lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( u7 {3 x% F. q9 DMCASP_RX_MODE_DMA);7 J9 @& q8 ]) k% B3 Y# t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 B& _* R3 n. Q. O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! j# i5 p" L9 w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, @+ ]( Q& s( H# m5 v: B& t/ KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 A4 {5 e, x0 l% ^. Q. a CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
v. q6 Q, B) g- [, `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// b& M6 u% V/ ^% R: P) [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 E2 N8 R3 ^4 K% ?5 k8 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: B+ i. E- b8 |! oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 A9 v" D- D2 e; z& e0x00, 0xFF); /* configure the clock for transmitter */
7 }: S( d' D8 Y) sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 S% P. j- k# J) H2 y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 g- p8 Y& Z7 w2 T8 X+ c1 Z& wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," a" t& L% C5 x* E7 E$ R
0x00, 0xFF);# B! H% g# ?2 f8 P) v: c% N- s/ c, o+ o
! l' X) [4 o6 f/ z6 {
/* Enable synchronization of RX and TX sections */
; N, }1 @; Z9 m+ ^. G5 M$ CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; A2 ~ g8 Q1 e3 w4 F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 L. _% X7 B3 I, _0 d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! t* o( t# |* w1 [: ^3 d. f** Set the serializers, Currently only one serializer is set as! l; d6 X1 G. z7 |9 s
** transmitter and one serializer as receiver.
( D5 q: |9 I- C4 |' C: |*/
2 j+ S: s% ]( wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 }, m; j) K; _7 l- L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 `6 \( J9 S+ v% m. V | f** Configure the McASP pins . l, F: G+ s1 |3 _% i2 V B/ _4 s
** Input - Frame Sync, Clock and Serializer Rx
3 d2 i+ F# E$ v2 k** Output - Serializer Tx is connected to the input of the codec
7 q# A1 n/ X9 Y+ z7 L*/
3 f% s# W8 Q7 i7 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) v W$ S, y) w# W' H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 r" w; N$ C' c$ I5 tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% ]( \1 L: W/ h. [
| MCASP_PIN_ACLKX8 L* E4 g$ e3 x8 V
| MCASP_PIN_AHCLKX
) |- T+ s+ L& c" z: L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 h+ `5 T: U; {8 E. m: g+ d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 K0 b8 D9 t1 N. q1 c t/ Q+ t| MCASP_TX_CLKFAIL
1 [$ ]; z9 b& p0 b( { R| MCASP_TX_SYNCERROR2 W1 T: o* @- a3 X* F0 Z! O% m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 V% D8 I: }: |8 l, o% [, D
| MCASP_RX_CLKFAIL5 J( c& e7 T. G3 z; ]
| MCASP_RX_SYNCERROR , g5 Y7 _! t9 r
| MCASP_RX_OVERRUN);. C% K' N: a9 w# F$ L, A+ Q7 [
} static void I2SDataTxRxActivate(void)
: t- X; W' `+ b8 L. u \{. G# n: y- ?" h; T
/* Start the clocks */
- E$ i" j8 z iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# [4 t+ }6 z4 d2 ^' J1 ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% ~$ I y+ p* e K! ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) A. P# I+ @8 [% ?3 E- PEDMA3_TRIG_MODE_EVENT);( Y1 D+ U$ c% F& }8 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 d% h0 g7 f: x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. i; r/ l' S( O/ L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* P+ s3 `8 C; y& R+ R FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 |' v* t0 P' p: N# [% W! r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" r: R- T* F- X! d6 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. ~! w" ?; [1 A S) e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 L; g2 U% @0 R/ R- K% ]}
3 ?0 d' o) a( q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 l$ Z. \2 a- K9 t+ s
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