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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 e. G2 ~6 D( J8 k6 q% g* y' Ginput mcasp_ahclkx,
( I' h. K+ H% ^" d2 Dinput mcasp_aclkx,* \0 X; b1 \ C! T; ~' ^
input axr0,
4 s9 v% @9 o" x3 Y. Y" R& s% X9 c/ Q- H/ m$ C
output mcasp_afsr,
F6 |6 v8 e* y& o( X* i' C. Noutput mcasp_ahclkr,
5 a* O6 \4 Q/ S$ r- b: loutput mcasp_aclkr,
8 c/ u( u% r* S% j* ^8 Y; o* F$ Eoutput axr1,
" H: _' u! y' k& z6 C4 r+ N3 x+ _ assign mcasp_afsr = mcasp_afsx;
" ?* @% t+ `2 v [* s& nassign mcasp_aclkr = mcasp_aclkx;2 k8 e% s5 E7 u4 F, j0 M
assign mcasp_ahclkr = mcasp_ahclkx;5 A5 G) P8 m* u- x8 N) o) q
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, U" h! W$ s @$ Istatic void McASPI2SConfigure(void)% m8 a7 x3 I; r9 s8 C$ H4 a4 y
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- \6 k5 o' e3 F% d2 l' H Q j* }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, G) L8 P& C0 T9 M5 @" y* j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) @, ]4 @$ |; _9 a; nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% c$ `+ L6 q# |" U. oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* @0 N- O8 O+ j* M: L% b
MCASP_RX_MODE_DMA);
6 p+ K1 g2 z: j* FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ B C! ?: X8 ^2 ^+ ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- l! p# n; c, ]& P) M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ x4 Q& s5 o3 n+ N: P% w: FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 _0 `6 q B$ L) _* x4 U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% G% Z3 J- c: W! c5 t/ ?: WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 X' T3 {. L, k6 P0 M' VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); R/ p9 c/ ~# J3 p* O( U5 ^0 h2 Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# e# C3 v; x: D3 sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 n' ]. P+ {, ]; U0x00, 0xFF); /* configure the clock for transmitter */
4 E r! J+ O/ n$ g, AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# y2 r' v( T H5 R- _$ EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 f, x' R1 z* h; l0 I* @+ VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# x* u& }; r+ m. _; f5 {- K0x00, 0xFF);
% M( e: J% N- t/ [6 b3 Y$ G R! A9 I8 ^$ I: F6 ]
/* Enable synchronization of RX and TX sections */
3 g5 m0 [& t! l8 Y7 cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ S! f9 `2 i; X$ U9 zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ s( m* F' i. g, `! c# C; K% t3 m) b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, j: T- J- o% D6 R1 v6 c, e2 i
** Set the serializers, Currently only one serializer is set as
1 [ w [6 d3 f8 x6 F6 r9 B** transmitter and one serializer as receiver., l, d- g6 b9 h
*/2 ~ M5 h% X" m3 ?+ w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" S# V3 E- b8 i( t$ _ Q: DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# N% x$ }, G6 M* ]
** Configure the McASP pins
2 b5 i2 H$ m9 a6 q8 B1 n, Q% E** Input - Frame Sync, Clock and Serializer Rx: F6 Z b0 E; h# c5 `/ d
** Output - Serializer Tx is connected to the input of the codec 2 M2 ^6 }% b+ m8 y( Y6 I# T
*/
/ h1 b3 R4 R- TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ a x& }! d6 P) ]4 G% `3 L$ S. fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, n$ P' q8 I o i# O: `+ YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! ^ g+ a9 ^3 {6 p| MCASP_PIN_ACLKX
4 Q! Q' ~: \: `8 L| MCASP_PIN_AHCLKX& o5 b- W2 h8 o. E0 @) Q7 k5 x0 v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" ?; Q' O# \ u7 Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" m, X. |) x! m F1 C% C7 L| MCASP_TX_CLKFAIL 5 S5 P! G: {2 `) a% ~* _
| MCASP_TX_SYNCERROR; v% o( l3 C1 ~4 o4 p* w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 Q5 |+ L4 l5 o3 L W
| MCASP_RX_CLKFAIL
0 J$ \" }# X4 }9 z3 Z! U| MCASP_RX_SYNCERROR 2 W% ^+ L; W; n. }+ ^1 Y
| MCASP_RX_OVERRUN);4 a7 E1 c. r) N3 u. u B
} static void I2SDataTxRxActivate(void)# }* J2 q" ~. j/ h' s6 _% f
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/* Start the clocks */' E+ [) Y) c' A" c8 N, m" ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 u3 s9 C- `2 O! \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ ?! H3 g9 z( B: H" |- W# Z t# fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 [( V( b O0 l7 L/ }EDMA3_TRIG_MODE_EVENT);
9 r" j) Q& a+ g" x2 Z; OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 f! ~7 j! J" P% r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ i- \1 ]( e* J% J$ L' p1 r5 s: S: R0 a. L& NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& u. p+ |) d: D( V7 MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* b7 M9 U; p3 r6 Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: `% f+ i% m8 C) o N+ CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- n0 X6 ]' H8 A0 h( ?) {2 H5 M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) }' S' S( H( N4 p @" ~, n2 b4 d4 i
}
) }- T7 Q- c4 Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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