我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 n: O* |) L7 B6 i% Rinput mcasp_ahclkx,0 z9 q R4 S; j- R( ^, F6 \" Y
input mcasp_aclkx,
9 D9 I+ I" P4 t# V, Iinput axr0,$ b, m9 Y3 N' C8 v8 N
) F$ @$ u: a- u0 u& I% ~' ]
output mcasp_afsr,
5 Q* I& N" _' youtput mcasp_ahclkr,
) s8 ~7 F; s% o$ P2 c4 ]output mcasp_aclkr,3 x' X8 X. p6 f; g9 m% n
output axr1,
9 S; Z- t c# V0 E' Q7 X assign mcasp_afsr = mcasp_afsx;
, ?% @- A: X0 p4 \+ K7 r. nassign mcasp_aclkr = mcasp_aclkx;
! A; C9 o. p$ P! g: C0 t+ x7 y% Aassign mcasp_ahclkr = mcasp_ahclkx;
! v: e5 k/ V' M) V5 F+ z, lassign axr1 = axr0; : ?8 [4 f; A3 T" J. K5 M
( @# e. H6 k1 u. r7 C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : ^- U2 B% ?; i b9 ?/ N u' z, }
static void McASPI2SConfigure(void), W& H7 y9 u, @7 a1 F/ Q
{
- A% H3 W; K6 |% {4 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);. D# X+ E; p; d/ \' q- \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( d8 c2 o' i+ u- `$ o" XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# X7 a7 Y% v3 q3 k3 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# H5 q9 p3 A; V* _# Z( y% _2 |) ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: t8 j; {; c0 E! @' j$ b m
MCASP_RX_MODE_DMA);. S k5 U H3 x( _: T1 C, p2 g& k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ?6 c" r x6 N& }/ C% j HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// r2 ?2 ]3 d, ?: `3 A' c* t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. j6 r6 h2 E t L' v6 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ p4 u8 \0 _. s a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : \) ]: s7 R, r. v/ {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 c0 a2 f. E* B+ G) R) }8 G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 ]' d) F7 [* d1 t1 L- TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 V+ f, {3 U6 Z7 x+ _/ N, d( a6 p, @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ Z5 A3 u0 [6 O$ C
0x00, 0xFF); /* configure the clock for transmitter */0 n9 v2 F% I8 g2 w# _0 b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& u Z, b9 ^# E& x ?0 J& @0 Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 w* S/ ^4 e- R& v. k0 L, ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' k4 H- [! R6 V) W# L" a. ?2 h5 e* E8 H0x00, 0xFF);
7 t9 c0 ? h' q% u# Q
/ w/ @2 ^! P5 F: u# g: P/* Enable synchronization of RX and TX sections */
, s, V3 J! q/ _! M; TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// t0 S# H! q, Y' T! y- H/ ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. ?) V! i, u! d" sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 O6 k I. t0 w# s5 E** Set the serializers, Currently only one serializer is set as( C2 ~6 B; E1 } [: ~
** transmitter and one serializer as receiver.( i9 [0 E, R# t1 @
*/) J$ K- d- i4 Y1 C& n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 a0 P, N5 t. k6 `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ e. Y" R2 A* R4 a7 G! ~9 D5 ^7 [" c( N
** Configure the McASP pins
: s- i7 e/ d4 E) w0 e** Input - Frame Sync, Clock and Serializer Rx
/ y% T) D/ d* L9 X' x. g" F** Output - Serializer Tx is connected to the input of the codec 6 p; b) x/ G2 _0 u0 h
*// L2 l9 I- F/ t) N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ t, d$ s8 P; ]6 A0 ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' b0 B. ]; P# x" U+ rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' F/ V9 R3 |! W* r! V$ S9 f; q* z v
| MCASP_PIN_ACLKX, u& Y) D% @# d# j, y
| MCASP_PIN_AHCLKX. |* r0 ~2 m$ a% }: P. D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 m# L, V- W6 B2 H& YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 D, y2 r8 h" A( K+ s| MCASP_TX_CLKFAIL
6 c( z: D0 T2 {# G) r+ E; O2 Z, a- Z| MCASP_TX_SYNCERROR
1 c) y0 q( M' x2 D- ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( g6 g+ r# w# d7 J/ z6 K* F1 j' l
| MCASP_RX_CLKFAIL2 r# K: D, _; o0 z
| MCASP_RX_SYNCERROR - K5 M1 m% P6 c+ U/ ]2 ?5 O- C
| MCASP_RX_OVERRUN);6 s+ Z/ x! V0 Z ?
} static void I2SDataTxRxActivate(void)8 L- B! i" h6 N+ E0 K& u1 m/ O8 e
{
- f& f Q7 v6 ^4 l5 _/* Start the clocks */
7 M9 n# A5 {9 F5 v ?( P6 tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- ]2 E. y: P) O2 I: rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 g$ E7 ]* f! E0 F' A7 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. _. w/ r( x0 r! oEDMA3_TRIG_MODE_EVENT);8 I! @; [# M$ {" o3 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) I" M& Z6 _+ _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 W8 D9 G* I9 F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ k. z# V- T2 j; j! `# x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! \) I5 i, U& V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, X P9 A# F' W/ KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 s, r5 s `, C% r0 e& ?2 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ X3 m, Z3 G: u% ^/ K
} , q. o" [+ B1 U; ]: R3 ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . _& ~# }4 a, [$ y* E* k9 I
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