|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" a% | H$ B4 x9 n6 J1 ^3 J: Winput mcasp_ahclkx,
4 C2 h! {# G- }4 Rinput mcasp_aclkx,, H' Z2 k k9 @$ q
input axr0,
7 H' ]' X$ d; r' e) N, r7 E/ |8 y
% d7 @# h( e+ \2 J8 R0 [9 l( Houtput mcasp_afsr, c: G* h3 ? Y/ ]- w4 f2 N4 O
output mcasp_ahclkr,
6 j- d; a1 f2 ioutput mcasp_aclkr,
$ f# X- o7 n; G& j7 Q1 eoutput axr1,
, T; {, @; S8 |( V) ] assign mcasp_afsr = mcasp_afsx;
# t# P* \' [; c4 C7 e5 Zassign mcasp_aclkr = mcasp_aclkx;
: b5 w1 o! p) L+ sassign mcasp_ahclkr = mcasp_ahclkx;
8 y* V8 d8 l: w- i% nassign axr1 = axr0; 1 {& C% P. f: E' I1 o) c9 ~. N
" b- G+ r% W" p& G5 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + l1 V# E0 x8 x |* o' _4 {
static void McASPI2SConfigure(void)
$ y6 j& d# l% e% a# t# D3 ?8 @{) I6 B" b5 i4 W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) B' m$ h, a5 V, y H7 ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 ~7 @& V8 O! }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 \$ }9 a& w3 A# A3 v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: r' j0 l" C' U+ g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! X1 H' P, w- z! W' K3 gMCASP_RX_MODE_DMA);
6 B; z5 A2 o9 {" y/ pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, u, x" y% J" F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 S- {2 c2 Z% D5 y4 wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- o; S7 j# g7 A4 C5 pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, Z- N1 }2 [' z/ YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 x! H" n0 Y% O7 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ o, q0 z* O ~ G% F, d6 {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ K- h: u, m0 ^; |$ @) ~$ `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : V& i7 z8 |0 y8 s" P. f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 C4 z# A2 U9 A7 g$ }
0x00, 0xFF); /* configure the clock for transmitter */4 t3 G, m# `( o( ^: d" T! K& J. Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' t, E7 Z9 w6 M! M) q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. n" P, m: p5 W6 ^: CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 U9 ^: f' d: | c. W
0x00, 0xFF);
# b* m8 K: l3 k m9 H1 m4 G' F0 S; M4 U1 p% v6 _5 ~
/* Enable synchronization of RX and TX sections */ % }0 c8 |7 C% o( j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' u% g( ]# O$ j- r0 R* n4 P' ?5 X8 z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, `4 W7 \: d2 C8 F- K* O8 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& H0 P4 t# z1 n: Q0 i& P4 z
** Set the serializers, Currently only one serializer is set as
( I, c1 e6 y6 Z& `( o** transmitter and one serializer as receiver.: j! F- O2 B: m
*/
( q; [' n5 [" G9 E8 |- f/ SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' @$ A7 n6 Q: T. D+ R% GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 z( X# B0 u( {. K# ^
** Configure the McASP pins
" c& j, E" L' I3 ^+ l: r** Input - Frame Sync, Clock and Serializer Rx
# d9 a" W! q9 U1 S, W** Output - Serializer Tx is connected to the input of the codec ~# k7 ]0 j2 E9 r
*/# l$ k; |, H; [8 V# Z, p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 M* W1 ~2 Y8 yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: V5 z5 B! q0 |4 {/ C* f. ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 X0 P- j" `/ [ W* j$ h$ S| MCASP_PIN_ACLKX
0 l6 @: b5 b* |4 V* p( B _3 D3 q| MCASP_PIN_AHCLKX ]% B9 j+ W/ b+ {- J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, f/ \; Y' ]1 d/ @" n! cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & v, t: j2 w9 N4 k+ I2 S( h @( R% ^3 l; z
| MCASP_TX_CLKFAIL
2 G9 {' v8 u+ g$ h" h| MCASP_TX_SYNCERROR
e. U, G6 H( e& ]5 z! `% F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" I; T6 ?8 }0 k8 Y- m+ f7 Z; @+ a| MCASP_RX_CLKFAIL
; ~. x1 U0 ^9 j! s$ O% h, u| MCASP_RX_SYNCERROR
* L r8 V8 B& b m/ R/ X7 o| MCASP_RX_OVERRUN); I: |% D/ Q6 K' z+ a$ l7 b1 ^4 j
} static void I2SDataTxRxActivate(void)6 k8 L; z/ D$ p, l, [8 d
{
$ V* x7 _# I8 t p- U! {/* Start the clocks */8 ~3 y" H i) Q; U' e! S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 u. p9 D1 z' `, q g5 h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" M% d; u2 d5 H+ {# s+ DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% Z+ z. k6 F7 Z' k- E' x
EDMA3_TRIG_MODE_EVENT);. u f" F6 P5 S0 c9 F9 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , d$ f3 z( O& P. c1 S; m& ? L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 q/ g2 W5 U3 W; k" x, U$ w* HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 L0 [4 E; }0 e* p# k/ |/ k G9 g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; m$ s' |" A+ S" ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- F0 `% A: D6 ]7 j5 M: a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 }/ O: k! z% [/ {6 \$ P" s. d# K8 vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) s, b' D( T& q& M) @
} 7 b* p5 E5 M8 H2 X, [5 d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
( v- k1 b0 `3 b |