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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 p5 w# B; E, Y& r0 ^1 k. Tinput mcasp_ahclkx,; ]& b5 Z S" K3 ^* v
input mcasp_aclkx, A6 |% D4 [% U% J! f
input axr0,( `( r2 w2 n9 l; c
) j0 u; j5 q: I4 p( b
output mcasp_afsr,4 Z! z5 \' U$ r5 q3 ?2 [
output mcasp_ahclkr,& M5 v6 P2 C5 U- A5 J* Y
output mcasp_aclkr,
7 m2 t. W# k. R4 S6 J$ [output axr1,, Q, n, b& b- I2 f' u
assign mcasp_afsr = mcasp_afsx;7 {: N) h+ Z3 L* h; u
assign mcasp_aclkr = mcasp_aclkx;6 p [) A6 `2 I; l
assign mcasp_ahclkr = mcasp_ahclkx;
; ~2 Q3 r! j; `, k% xassign axr1 = axr0;
# C0 |2 E* @! j2 `4 y( v$ [3 g1 V& B/ y- z0 c# i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' t9 z* ?/ d+ j
static void McASPI2SConfigure(void)
0 ?* e. h* ^1 {6 C9 e \{* z4 }6 C- E, R7 C+ Z- u$ D! f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 l% [9 G# V# s# w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 c9 _" k" |7 O5 a! D7 R) b+ MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 ?. [7 z# K" sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; l: O, j! [/ F0 S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 `; }8 m) T- ]9 M# V; P
MCASP_RX_MODE_DMA);
1 z6 S4 ?: K& l* A$ O- x/ X# r OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 w8 C( E, }% Q7 h5 v5 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 S0 D* w$ l$ `" z5 J9 m% ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' i) D' g/ L+ M2 s( QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' \7 }# x8 l- o2 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 \! Y* j; y' x+ H3 d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; ]& z3 f/ D7 s' P% zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% ~' P# D3 @2 u# UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # _9 g: j' }+ l# }! X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 n* t [% G! ^+ w- q0 q5 ?0x00, 0xFF); /* configure the clock for transmitter */: N/ e: D) p' [- V: u3 c5 l- W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% F4 {% t5 z! D" q) _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : q0 M# _0 G7 F. A* G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! a, S3 w$ B( v% y. A3 t9 }
0x00, 0xFF);
6 t0 M& a8 \' e- l
' J: p* w5 l# o& k/* Enable synchronization of RX and TX sections */
% \& z" o! A5 x$ ~ PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 d$ p) H7 ?7 G1 Z! p* j( f8 Y( i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* n5 A1 W& m3 g0 tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 h- c5 o K4 U# }7 p** Set the serializers, Currently only one serializer is set as0 n+ l* K* A, {# T6 A
** transmitter and one serializer as receiver.# Z+ x' }' t5 i) e
*/$ b/ e# x* B" f8 r; V) e( X/ q. c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( ?4 `& x# ?! q: s% _* v7 y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) w+ f. D1 v8 [3 `, V* s/ }
** Configure the McASP pins
: h2 @8 _% l4 _0 z* v3 j8 {! n** Input - Frame Sync, Clock and Serializer Rx( g+ w9 ^! T; Z! G) o
** Output - Serializer Tx is connected to the input of the codec
+ j& v6 {8 }, r' Z8 m3 Y# X- f*/
; R% y! v j0 e4 W5 OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ e, O2 X9 q. S( v# i8 E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, R0 A H9 V# K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* ]% H. E3 x: v| MCASP_PIN_ACLKX2 L& j5 G( t8 n8 K, ]& _. d/ j; i1 O% s
| MCASP_PIN_AHCLKX( C% D0 H9 Q: r- u$ A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; E+ K0 k1 g* `! @; G8 c6 K) sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 n4 N2 |1 ` v" _2 O# N; w4 ~+ W| MCASP_TX_CLKFAIL
( ` S5 i0 p6 R: {$ t' z. ]4 @| MCASP_TX_SYNCERROR- E! D5 {9 G! y+ f3 j* w1 A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 y( P" V! Y1 Q% H
| MCASP_RX_CLKFAIL
9 l2 F8 n! s7 c: a! \/ i| MCASP_RX_SYNCERROR 6 ?7 i( U: v5 H1 A# a
| MCASP_RX_OVERRUN);( G; |1 \6 m9 f+ L
} static void I2SDataTxRxActivate(void)
. B h1 b& m& f" g{
_0 F7 P+ S, @1 P3 C K/ x/* Start the clocks */
3 Y. n" b8 S% nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* ?& H5 s, D* K, y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
x2 V1 |- i, ]7 ~3 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ V2 ~+ ]0 ~* ^4 _( |& Q3 gEDMA3_TRIG_MODE_EVENT);7 i k0 J; m, G& S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 g1 O- [, y. ~: IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: I0 f0 g: |- c9 ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 o. q& W! L5 V6 i" pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 M/ ?# @( w ?/ W8 Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- c z/ b9 W* B9 K" {( y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. ^. L. P) S0 Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 ^3 T; `, E" P# K9 Q& b: I7 K4 m
} , a3 e( c( H) y4 ~' H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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