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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% k! v# h x, Uinput mcasp_ahclkx,. _$ o$ G/ C7 M! q/ r% s [* g
input mcasp_aclkx,8 [& e1 F" m2 ?( I# ?$ W
input axr0,: Q1 y) Y* }" X3 `* y
* O3 ^1 r; X# C% H* D4 e4 c* Qoutput mcasp_afsr,
; L& f; d3 f8 K2 |2 _output mcasp_ahclkr,
! v' k3 A0 O. W. k. O ^( ^, \output mcasp_aclkr,
; U! D' u' ` D) Zoutput axr1,
. G2 I0 Q2 u( C: B2 S5 `/ R assign mcasp_afsr = mcasp_afsx;
) ]* p. O- W+ ?( g7 K; Hassign mcasp_aclkr = mcasp_aclkx;
! [" k6 g' Y" k- Z; O) k0 lassign mcasp_ahclkr = mcasp_ahclkx;
$ B' j- p2 K2 U1 [3 Z/ Jassign axr1 = axr0; _2 g7 G7 w5 e t6 U% [5 z! t% M5 L
3 L8 b. D# b- e$ X( r9 p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! r" u( \+ R f* N5 L
static void McASPI2SConfigure(void)
g/ V8 I/ p0 @" `{
O- O) Q( V( k1 G) D) ]0 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* Y( D# t; B+ `3 V% ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% Y( }# \% e+ O! S; `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& F7 j! K0 a5 G, G: S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, f, {' Z8 a( ^ M# V; o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. N. S" h3 t! y8 h3 w
MCASP_RX_MODE_DMA);( {! `& [* _7 y6 L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ y+ O0 `1 k6 f( k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 q+ L( g. t5 M& f, F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / `) v2 f" r! `; R7 ~5 U5 d0 A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% H2 p8 Z Q9 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 x9 t. P. N+ ?! `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- h& y. {% _0 F! u! XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# f+ a' D0 s& {; c& Z/ d$ K1 sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- `7 G0 ` d5 p( W/ U- y) ~$ ~1 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. t p" P4 _9 R) o0 E e0x00, 0xFF); /* configure the clock for transmitter */: ~' Z$ Q3 E3 g' {! B$ Y0 D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 y( [" d g( }# T" GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( _" O7 F, T2 V; [& rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% g( w0 h) U' a% P" O
0x00, 0xFF);
( j; e4 g2 C5 W$ b3 {& X0 t T% U$ f' c! g% [5 C; K
/* Enable synchronization of RX and TX sections */
* I5 n- C/ l( j& Q9 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 ?/ j+ a" o5 U4 P* v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 f _5 X9 B* Z* Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% F; q5 c- Y0 w T0 {% l4 e/ L** Set the serializers, Currently only one serializer is set as
1 U! h7 s! R) R** transmitter and one serializer as receiver.
3 N% C' g5 G% I! D& y7 F( e*/
: j; Z$ }$ {" U! lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' `7 [( E0 P, H: s: d3 O0 I+ ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ c* u. T0 t# L* x
** Configure the McASP pins
4 |1 V; P" A; n0 p** Input - Frame Sync, Clock and Serializer Rx
- V7 b4 w }. |3 u# v2 `** Output - Serializer Tx is connected to the input of the codec ' d- w$ N; |3 }: O1 l* x5 c4 m" b
*/
0 d* F, i! `4 {: L. `6 tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ q( r) W. k% F& M6 N* {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 g. z; |# p' ?" q. g! E# C9 [7 @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% l! F$ r% B) N| MCASP_PIN_ACLKX% ~5 a' \) I& U/ e. i& |; t6 X" l
| MCASP_PIN_AHCLKX0 X) ^! { _ F5 g, \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 u* _: `4 t2 e1 F% m! EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- ?' M+ x l! k" || MCASP_TX_CLKFAIL
+ E- b: [& l! Z0 r| MCASP_TX_SYNCERROR$ T7 }5 i3 W5 ]5 T, T$ b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* a9 {7 S5 o$ ~; [| MCASP_RX_CLKFAIL
1 Y3 T: K$ t8 y. L* j$ c( i% @9 R- }| MCASP_RX_SYNCERROR 7 S4 |3 g0 b* y( X, S! a( \2 D
| MCASP_RX_OVERRUN);
: s: t# } i5 F1 K2 ?. N- x} static void I2SDataTxRxActivate(void)
: R. ^( n4 K" ^6 H! U{
2 s- m% J" w% D9 S/* Start the clocks */
* s+ H& w: P# V$ K; S i0 Z/ rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 n8 H! m3 s" N: P H7 h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) h8 s* m8 r- o: b+ t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* k7 t% q6 d& ?5 Z% w) C& EEDMA3_TRIG_MODE_EVENT);7 Z. W2 R, m, o; U3 b) e9 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 F- s7 U+ e0 i4 u: a0 W% FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. @! w }! ~9 H3 I' PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" \8 B- u2 J2 U4 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 n1 ^0 R: e. e9 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! [% }0 r0 V9 f& [2 a0 q+ BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ b( m3 H7 z/ \+ G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ z2 `. T, G! h9 z- i8 ~; f0 C
}
7 {; o4 C, K" B" e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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