|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 D4 M8 Z, Q. t6 Tinput mcasp_ahclkx,
* C. v5 }3 Q! p! E$ \# U; Z/ ]input mcasp_aclkx,1 v! q9 D, S1 M5 Z6 h: u/ D. R! B$ _
input axr0,
* J; g* W+ ?) p6 B S1 R, r$ E w) D# D& _. `% l$ a _
output mcasp_afsr,6 `9 l% w+ P. ^- y$ O. E
output mcasp_ahclkr,8 N2 ^$ x( F# @( h# U. ^
output mcasp_aclkr,0 S1 t7 M5 B; k! v7 }
output axr1,3 E7 l# C* @; S
assign mcasp_afsr = mcasp_afsx;1 n& a2 t8 u& b% @$ [+ n
assign mcasp_aclkr = mcasp_aclkx;
r4 r: D- Y5 J5 l0 Lassign mcasp_ahclkr = mcasp_ahclkx;
; H8 d! J' R$ {# @: _assign axr1 = axr0;
, Z! N4 b) ^" i( q# Q. h
2 G) y$ z/ M3 F5 O" E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; g6 n; t" t% Kstatic void McASPI2SConfigure(void)) h0 X- ]& D. N1 ~) |, k
{
, V- [6 j" ^3 j; V L$ c5 P( eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 F( H& ^8 J7 D5 N1 D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: b0 Q4 v, v4 s0 o4 s9 C* E4 D( `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' ~$ I+ j( }# O3 } B- l) y; ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! Q: o4 r2 G% g& i k* ^8 k; M8 G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& \; n: E, ^+ B" K) C' I& v' [MCASP_RX_MODE_DMA);
" s9 J, M( U7 O7 |+ t$ C7 C& I, UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, m& d0 h4 g+ Y1 e9 P7 q- WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% _! W- m$ V5 S4 q; v( V) }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 ^* c& ]) i) A$ v0 dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. G+ x5 d3 C/ \4 }" {2 N0 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, C9 H* B' P7 ~1 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ d2 G! E3 ]9 j5 y' y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. h# @ {+ b( m, }# l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ]9 H; R7 l3 `, q! ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 W" F+ ]2 p7 B+ ^+ W0 ~0x00, 0xFF); /* configure the clock for transmitter */
; Y- h% m U$ f) k9 F6 pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) K r; ~& A" O& kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 ?( E9 [0 s7 V Y2 O( LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 Y: U3 j4 |; ~ [5 N7 N0x00, 0xFF);( @7 d6 p& ]; V- \1 k( p
& D8 c, H F2 N$ A/* Enable synchronization of RX and TX sections */ 6 V7 s, J+ ^& b3 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! R Z! s N l3 r% f4 r" G9 tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# `( W; x, i9 x* p; u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ P* r+ V2 o( J# d x/ }) w** Set the serializers, Currently only one serializer is set as! j& _& }% B9 F$ t4 ]
** transmitter and one serializer as receiver.
9 N8 Z+ v9 A% e! Z0 I- \9 }9 l*/4 \' _! O% w+ G; ?" p1 I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 q# O8 ~2 K4 S7 h. n/ [, V" ?: c$ TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 m) N$ v, A6 ^2 F2 K2 B3 G* ]
** Configure the McASP pins
; O% v6 W6 j. Y** Input - Frame Sync, Clock and Serializer Rx# W; S; n* A5 v: U5 [
** Output - Serializer Tx is connected to the input of the codec & Q. N* T& U5 f6 p% E, m/ a
*/
; b& z5 G- _# w) E7 Z8 _* eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. H6 `- U. _" ^$ k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. w# _* b" E2 z J7 ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* p6 c/ A: Y: f: u| MCASP_PIN_ACLKX7 h" @0 U* }. R% g6 C8 r( T) ?6 d
| MCASP_PIN_AHCLKX
( t$ h4 i: l. @5 N5 b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 U- C: e" l1 @1 p, T8 a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - v+ x8 k3 z6 B; z
| MCASP_TX_CLKFAIL
- O4 ?2 t5 F) m* I# L! ? D) r| MCASP_TX_SYNCERROR' o3 R: H* A1 f* y T1 H8 Q; A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; y% U8 k7 {9 z2 N& m
| MCASP_RX_CLKFAIL
) K- Q& }1 g4 q| MCASP_RX_SYNCERROR
, _1 h/ }5 l- i3 ^9 O# L| MCASP_RX_OVERRUN);& f+ W+ [ Z- n0 x. B: ~, \
} static void I2SDataTxRxActivate(void)( C h6 b7 f+ a D& s- Z. B
{
( K$ o. ?- R. N3 y/* Start the clocks */3 f8 R8 J) i! S* t1 \, q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& G% ?( w2 Z% Y7 @; K: @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ a8 }1 {. B5 L. s4 p9 d {" WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* Q) E# Q. f" S) aEDMA3_TRIG_MODE_EVENT);! `7 B- n! u) M# W0 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * [9 O3 |* c- B8 j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ [5 g3 F& B/ VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" k( ~9 z4 H: c D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 B8 y5 K2 |; \; r& d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; W* g' d: z6 c1 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% J) ~. r' O: O3 y: U# ^$ S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( L I- Q5 P# ~# s) z. g, g" ?
}
M7 P4 F* S6 A% S" h. H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
8 j3 o5 M v# C* B/ K7 \ |