MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
* O0 K3 r, O8 cinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
) K& L( w: s$ A, \# _. w
1 M$ L/ |4 T; P# ~) Coutput mcasp_afsr,
+ G4 s' h6 S" |) s# H% foutput mcasp_ahclkr,
% I* |5 h5 t4 t' E; {3 d8 toutput mcasp_aclkr,
output axr1,
7 C" c. t- c) _! v

assign mcasp_afsr = mcasp_afsx;
% s! X0 V/ a. i* s" v# bassign mcasp_aclkr = mcasp_aclkx;
% h2 W9 a& K2 j; j  N3 l9 w# Bassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

3 _  Y4 k. V9 I/ Q: n( G3 F9 c
5 b' m2 e) o$ Q; }

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

" I6 C7 P$ G) w* R; C6 ]3 w( V3 @4 s

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 z; ~2 K; m0 |0 L) ?$ Y) CMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, Z5 i; B1 j. z2 W! J; g& G- rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
, o; ^9 B7 @1 ]6 p/ t# QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 h% s: F2 N' Y" o. G8 DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ }: Z6 r  S5 n2 m# V% NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
9 m, Z' q: p8 c' K5 D3 C2 vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ ~9 o  X9 r1 k- [& {: ?: M$ GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
0 F: j" w/ ^6 s* EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 s$ [! [' w$ Z% U5 d* FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. v+ M# p; n, z8 e5 {6 {; x: f0x00, 0xFF);

; x7 c0 `: _4 x% b/ U# Y/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 z/ M2 g$ Q: ^$ J2 aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
0 u' p# q) R* m8 j" Z7 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
4 S* C/ d& ^5 j* m** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
. |, T$ Z+ X# B*/
3 f; Q* z; E- O+ I, a5 tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 G! t; P9 y" U5 [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 T1 h8 e. w- u5 U/ V5 P| MCASP_PIN_ACLKX
3 p; D: r. y; q4 w| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 g6 ^3 q$ W( K9 {* L' i| MCASP_TX_CLKFAIL
/ ?- u2 H0 c; v% x# h% D| MCASP_TX_SYNCERROR
- M2 T( U) s: T$ I4 V" ~| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ e' |( r) p- h| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
* P8 o& X: S5 `8 c, C# [( I  R! Y/ JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: Q2 w. n3 ~: P( C4 U, sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 D7 B$ M# U1 u7 }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
4 h: y% J$ l$ m+ a7 C* ?/ b3 q5 f  cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
* l5 `) r* A# X, L7 ?2 Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
: k( n2 r6 ~/ P1 W8 J$ rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 Z- F2 R1 v% L1 s1 B, y7 g, A0 XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

. V$ n( ^& H7 N. Z0 P; x: a

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.