MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
: u2 G) d- D- A# x, p% k3 W* Pinput mcasp_aclkx,
input axr0,
# t, Z; v8 V) L( q: n
output mcasp_afsr,
output mcasp_ahclkr,
; H, m! F3 y* u6 U* Boutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

; R5 r" h/ N' {" w5 ~
0 _( t  Q) B  ]# X; v

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
) q" p8 x0 o& l% d7 n- N$ V{
$ T$ [, Y  D* c5 O5 Q- K% _; q+ SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 @) R) R" y$ b% W0 MMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& A- |. n6 m0 w" ?/ X8 dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 q, X, ^" U4 R. x' LMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 S5 G  ^, P2 B! F" h8 S) XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 }6 ]. q( G: }3 Q  EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
  V# v" p: r% k( Q; z1 I& B3 Y3 t, H0x00, 0xFF);

/* configure the clock for transmitter */
% ]+ B0 w/ l. q" @/ {8 p4 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 C; F' Q) k/ H0x00, 0xFF);
% b+ ^" w$ T4 {8 d+ e! S, \. C, ^* |
+ w. B/ t" x; G2 c& L3 o: d/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
3 x( G. j/ G! X) _' U** Set the serializers, Currently only one serializer is set as
% {$ u* K9 S( u** transmitter and one serializer as receiver.
*/
7 [: r0 h" b4 D9 t; W  k. i$ }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
0 w* q2 z5 q6 V** Input - Frame Sync, Clock and Serializer Rx
# x* N; T4 m) p7 p/ T** Output - Serializer Tx is connected to the input of the codec
*/
3 i# `  \2 l' hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- z$ R: y; d) Q5 g! eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
# y  W. X! e; B+ ~5 q; y* Y5 d| MCASP_PIN_AHCLKX
3 S+ J/ t' c. L2 x: B3 M| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 ]" Y0 f: T! q6 \. Q( ~& c| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
( `5 {9 p/ z4 v8 k0 t: }1 Z| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
, v# u6 ~- z" L/ ~1 R| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
2 x" H( \, o# k  E* t{
$ [9 R0 q% B, }& E, [7 M9 n/* Start the clocks */
1 W$ Z4 I  D  y! ^- JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
% z. B! a+ w% D. R) s, W3 c6 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
. T* D, j5 H# _1 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ h' H2 t- ?" h. T5 ?5 y) O: sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
; c5 Q" E- A; f" B4 E$ Z" p' BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 V3 f, L1 c' w0 D" e4 d! tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
% g$ u% ~6 D- Q  p. KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 {& c/ D7 u6 s. n& c5 }}

/ C3 q' i$ Q# A$ w

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

: b! B/ G: P- b" h/ ]