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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 n- ~( ~. p' R- L+ Pinput mcasp_ahclkx,: f# j" ]+ g+ U9 t! U; P7 E7 M
input mcasp_aclkx,% I4 C, U& Q D; A) J8 k$ @- L
input axr0,( L3 \4 _9 _- p
, }' Y* \0 z y- H1 woutput mcasp_afsr,
5 u0 i' B& k0 Soutput mcasp_ahclkr,+ \& q* q( h0 n$ Y O( T
output mcasp_aclkr,
) Z* B5 k. j/ W! moutput axr1,5 G- B& e' n0 |. k
assign mcasp_afsr = mcasp_afsx;
: q1 c! L! m0 Vassign mcasp_aclkr = mcasp_aclkx;
3 ^9 h2 n# T g2 [. Aassign mcasp_ahclkr = mcasp_ahclkx;% f8 W$ e4 ^+ E$ `
assign axr1 = axr0;
4 {; V/ H+ d1 @" @+ w
% a" z* k+ V: \2 H- ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / c N3 K( h/ \! l2 z' g f
static void McASPI2SConfigure(void)6 l8 V2 U) b- g% ]
{
8 b. _' b: C I: I% H+ ?8 ~. f7 iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
z6 J1 m& m& }5 Z0 cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 ~5 `" |+ ?2 c- e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' B/ q, p$ a2 C# ]% ^3 O" HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 J6 E/ Z e# g! XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ x3 ?4 I6 ^( C6 T' t4 C: ]MCASP_RX_MODE_DMA);
( j& D2 T9 H. B. l, J- t' W6 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ E; i0 k8 M/ o9 |7 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. B) D7 [+ @& q3 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 F: |5 J5 d' IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 s2 o$ @: c3 f+ Y$ MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 p9 e4 K8 h0 T' M/ v; P, }* @ kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- j: e; Y9 K, M2 k. k9 bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 l9 v% ?. C3 e$ `6 I! S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' `) N2 Q: I+ e" c* a; M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. ]. S$ w9 l5 _1 J0x00, 0xFF); /* configure the clock for transmitter */+ u* w* ^$ ^& H; C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ Z: V, k7 ~) s! H. }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , _% ]0 u6 c5 t1 }- i @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 t I! @+ Q. E3 V8 Z- N0x00, 0xFF);/ i4 l! Q' r. M: _
! ^. M; Z2 w" Z; _5 J) h% [8 K" n/* Enable synchronization of RX and TX sections */
: [' g& k ]- v: cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" \+ G! @6 r/ H% ?) A* n) AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& p8 n9 ]* l; d$ L& lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ R( t. H" u. D4 D! J5 p9 z9 e- _- p7 H& l** Set the serializers, Currently only one serializer is set as) ?! u2 O/ Y/ o z6 u/ o( G3 C, [
** transmitter and one serializer as receiver.
L, R- W, S2 a*/
% f* m! a! \8 r+ z, E9 [0 O; `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ r4 h! d7 c+ l; q7 j& V* RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** p. N9 X3 B, f2 A: W
** Configure the McASP pins 3 w y) Y. r3 l+ O& m
** Input - Frame Sync, Clock and Serializer Rx4 Q2 Z% N3 e: k6 @6 }
** Output - Serializer Tx is connected to the input of the codec 7 C5 G9 W: I4 o) d: w+ f- R6 Z+ [
*/
, ^% T; Y8 b; h' {" R: h. qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, S' C# S7 [7 h- S y% E; bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, R' ]4 x" s1 R7 T4 K$ SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: f) Y% y. F8 p/ h6 _6 s& K3 ~- w+ L/ S| MCASP_PIN_ACLKX
* D& w* M. ~; f& B| MCASP_PIN_AHCLKX* o" S- X, C' u9 o7 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: l! |' j+ Z/ z$ \3 [# pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, v( G6 Q. Z6 V. Z& N: | k, q% G& `| MCASP_TX_CLKFAIL ) E9 P! O% J' n% v+ J
| MCASP_TX_SYNCERROR
4 q4 M C2 H9 U& o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* t5 t+ S1 T9 u$ X# j| MCASP_RX_CLKFAIL
& P# M' s+ R4 ^( H5 i- v: B| MCASP_RX_SYNCERROR + w7 G4 |) j" G
| MCASP_RX_OVERRUN);3 t+ S4 t# v- \. M
} static void I2SDataTxRxActivate(void)
, D+ S0 h, I( \{% s! y6 n3 P: j/ z7 L# a( P
/* Start the clocks */
; B9 F: T ?+ m, KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( X5 N O# w5 s( M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! g! @, V6 K u5 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 z ^- P; R! T4 V8 E3 N0 P jEDMA3_TRIG_MODE_EVENT);
0 E3 Y k s% I1 b8 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 y6 a1 i+ F3 d( yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, Q" }& Q" v; {$ X1 {: k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! j4 d3 ~6 L# q$ g0 f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& ~/ C* `& r2 P5 i- \% ~& ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 S7 J0 @1 X/ o7 p/ ]. L& Z& aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 ?$ I4 @2 D8 w7 t# uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ H) F0 ~3 @! I}
1 v$ w7 w/ y: F9 N& V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % q( W v) B' A
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