|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 L2 q, ~) G( ]! b% k5 }
input mcasp_ahclkx,
) q. k6 l; W3 _& y( Ninput mcasp_aclkx,& ~! N) B8 U+ F. A+ s! [
input axr0,
; z" _( X$ l% I o6 e2 t5 u" l7 M" @5 J' K, J
output mcasp_afsr,
& F: v/ g( t4 O5 g' A- o# Q% Routput mcasp_ahclkr,' f! Y8 z- o5 C6 A8 A
output mcasp_aclkr,
8 W( e2 r% j; \# Ooutput axr1," _) @( {5 ~" ?, R9 n
assign mcasp_afsr = mcasp_afsx;
$ {7 P2 h6 T" g& e+ F! kassign mcasp_aclkr = mcasp_aclkx;
2 v6 v! A2 w+ }% zassign mcasp_ahclkr = mcasp_ahclkx;
- {! u) J5 q+ @$ W+ w: } P& hassign axr1 = axr0;
3 N- r+ m; t7 d/ v) E/ c7 Y
. ]- I }" j+ o1 y* C* a- l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ C+ h. J6 c/ u" kstatic void McASPI2SConfigure(void)0 X' r$ o5 r$ G% m3 Y) Y
{4 c5 W$ e' b+ I& B* \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
D% j/ ]5 ]/ x" s) C! KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# z4 S+ @- x# c2 F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 e1 e/ L9 D' X# ~, B* V9 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. Q; L4 f G( O% H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 \- q0 {2 ^' A' c. o; g% `
MCASP_RX_MODE_DMA);7 I" S' K5 Q/ J$ u N1 ^. {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 U1 k$ d: |) M% {5 h4 |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; z2 d8 g- M7 {9 O# d f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 k1 g$ H* p3 W4 ~7 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. I2 r5 @$ N- ~9 R' A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( n& P9 N6 ]+ A; b9 oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) f$ [" a% w0 v$ B% OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( M, L4 w; D4 H s3 HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * U9 u% k3 {# e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ G& J: y: q1 M h
0x00, 0xFF); /* configure the clock for transmitter */
2 W0 Q% X5 m8 v# EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 u7 S1 Z, y+ v- W, FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / [ ?3 A) |% n# Z; y0 n3 t$ V; R2 ~, K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; |8 q$ K0 ]8 h% I) v0x00, 0xFF);
P9 M% z+ y& D: V: W
8 z5 G7 K7 Z, |, `: ?. K# U: R- C/* Enable synchronization of RX and TX sections */
: }( `. e& c: g: SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! s$ z2 Y' T3 |: x8 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 m0 e( a T. ~ y# FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 l3 s5 ]* Z& ]% T" n. }' U$ s( Q** Set the serializers, Currently only one serializer is set as
) } Y$ E0 j4 W( w; I( ]9 m' O. u** transmitter and one serializer as receiver.
- m4 S6 w: C# {; L6 L*/# r) i2 g* w7 e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' @5 \- w' c) o# l4 tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" Y6 x" A: R/ W5 D
** Configure the McASP pins
7 [5 ?+ y) L. x** Input - Frame Sync, Clock and Serializer Rx
/ \+ D7 S! M) z2 a* N) s5 F** Output - Serializer Tx is connected to the input of the codec / ]) M, n7 ]! q# d& y- A: D! o S- @
*/
* c9 `+ |$ Q# Q+ NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 ~6 P4 V. _6 F0 d, O5 O. R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, L4 v9 K% Q! T1 r3 x/ Q+ d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( X7 v- I# J7 M# m
| MCASP_PIN_ACLKX
4 u+ R; P0 f' C |* v| MCASP_PIN_AHCLKX
/ p- F5 v8 [ R$ B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* t2 x, q+ E% c dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% Y2 u. k2 ]* K| MCASP_TX_CLKFAIL
5 q1 I4 O+ C8 D8 |9 a| MCASP_TX_SYNCERROR
: @0 [# l4 a0 I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* ?7 t: u: ]9 P/ F| MCASP_RX_CLKFAIL' K& ^; s$ ^9 ?3 B4 o
| MCASP_RX_SYNCERROR 4 c' e D+ }& p1 u/ E2 D% j u
| MCASP_RX_OVERRUN);% @5 v. L1 Q( P+ ~9 u& p7 d) u
} static void I2SDataTxRxActivate(void)
C' X( @* j4 D! q- ^& h" N8 F{
1 z* l% C" m* ^1 q/* Start the clocks */
. k5 i8 @% u# E9 ?2 G4 r% A! }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ i' V- M- w$ x* W' W0 S& D9 vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; U. S0 D0 ~0 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' K6 j( N. W: l! C6 p( s. l
EDMA3_TRIG_MODE_EVENT);
% G1 m6 s8 J9 r0 [2 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . H s ?; Y+ s$ f# V1 Q/ s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ l2 T2 T- G0 h5 H& N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ ^. S4 M5 b; @) W3 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 M, r* x4 h, l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 R! W& t2 n5 g7 PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! R- b0 G9 n, p9 } q, X) \3 IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* z8 e$ { \2 A* W3 V$ y% q4 M9 G} $ _4 \8 c& _. L8 B8 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
. |+ D6 y5 M6 I* X. A |