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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* ~( W( W1 d6 L0 {1 Z+ q/ I$ `
input mcasp_ahclkx,
- u. I' u o! z0 I; C8 e6 Jinput mcasp_aclkx,
! A+ q+ D4 D. n$ L5 N$ winput axr0,, B& y1 c6 s7 L' p. `1 C1 R5 @9 b7 J
% O+ Y) s2 b% U* }output mcasp_afsr,
c+ j( K9 G( G: v5 q! toutput mcasp_ahclkr,
% B% k, p. Z4 D- Moutput mcasp_aclkr,
2 P3 g% ?) ]% d, Koutput axr1,
6 K w0 \. G: U4 R4 M& X assign mcasp_afsr = mcasp_afsx;
2 R$ l0 e# t" ^9 passign mcasp_aclkr = mcasp_aclkx;9 p- H0 z3 @% U2 \7 Y9 U2 p7 Y6 X
assign mcasp_ahclkr = mcasp_ahclkx;
$ n) D+ g2 _ d+ [+ @" ?( Uassign axr1 = axr0; 5 v2 h5 }( w; i& p+ m6 F1 T
* d, j- z' _- N8 S2 A$ h7 M9 D$ f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ T# v e* k0 d L" h- L. `8 B3 tstatic void McASPI2SConfigure(void)
0 _, L9 g9 r* g; w! L{0 g S4 R0 v; N8 G) C. G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 b% c% a4 \& r' u- o! @. Y9 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% D8 R2 }3 s" S' j; D) E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 Z. w$ N6 C' _3 f, w& N3 L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, T) D c1 C" M2 g8 P4 b3 yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ X/ w m: Q" K9 w
MCASP_RX_MODE_DMA); ]0 ~) a$ g& ~4 K; _; G6 D! t @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* A8 C- y0 |, Q# r1 d4 S% O+ |# u3 tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ Z% z% C3 L/ b, c- KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 W- U$ Q+ H: Y: p5 X. j8 z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ N# i2 I# [9 I0 q1 o. ^. p. ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 c& \/ s9 e; [' ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, q- V0 q, `& U: y# v7 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: g5 E. c' b* h' h% `# X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; c! ~9 K5 G+ {" m% \1 k6 {5 ?! W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 l1 K& S7 S* I
0x00, 0xFF); /* configure the clock for transmitter */% ]. ^: \- u; F# i/ v2 I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: ^0 g5 r8 j8 K/ V7 M7 m7 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% r; R( k6 V) {( mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 k0 \4 ^: q/ t$ b3 c# a
0x00, 0xFF);1 L! g# O/ S- ~. m$ k' h
9 ?1 s1 l# b( Y% e* a) i8 k8 v
/* Enable synchronization of RX and TX sections */ 6 ?# N& t% @! C$ W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! `9 h2 F7 U6 v( uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 y6 b! G0 K' [, C( M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 {7 E1 S1 {$ G# \
** Set the serializers, Currently only one serializer is set as
, r/ h7 J, |* [+ R+ d0 ^+ l6 i** transmitter and one serializer as receiver.
1 D, D% z j- g3 o*/- \$ |: H _8 s4 g" j! ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; V4 g/ C5 H" l& }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
E' e* s8 z+ X** Configure the McASP pins
( R! S7 W5 N7 |3 |** Input - Frame Sync, Clock and Serializer Rx
1 h( B! ` Y2 Z6 N0 \9 f** Output - Serializer Tx is connected to the input of the codec
( I& U% B% o4 V% a# U*/
6 z8 x% K. }% }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( r* ^* M' Y: |" M$ q3 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 V3 v6 z5 ^8 B4 s8 [) w- F2 c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ ^4 A3 }. ^$ m9 v: c
| MCASP_PIN_ACLKX
* R: G0 G3 A! D5 C$ f| MCASP_PIN_AHCLKX
# `3 _) r) |0 ~* x& X3 ?! D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ ?* b6 {9 b' T0 F" C) o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 E" M8 @3 X! ], F| MCASP_TX_CLKFAIL Y0 Q. A/ m& u! L" z! z: \
| MCASP_TX_SYNCERROR0 X' M9 d- n) n0 w3 u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 {* m0 r& |& i! H+ n
| MCASP_RX_CLKFAIL2 F$ K ` u& N4 s* D$ r. j+ Y! Y, _
| MCASP_RX_SYNCERROR
% _0 J8 S; b6 s) p% Y$ z4 C( x0 z0 ?| MCASP_RX_OVERRUN);
4 p5 |, k" ?% Y5 T, L( _- u} static void I2SDataTxRxActivate(void)( @- P. h5 P" ^+ @, P1 U
{
7 ] X: G* Y) W/* Start the clocks */' g8 T2 q$ g# H, T N( K/ I9 K S4 m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, [8 P( n2 s" m) b# m: xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- c1 D. @8 v+ T4 i* g* E- o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 T2 _' h' R5 T, mEDMA3_TRIG_MODE_EVENT);9 s# E7 \9 I+ \9 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # y. a. F) `. Q2 x3 b& b2 ?3 x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ e* r/ {+ J( O9 z' [3 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* \( V) N R- y% ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: @2 K$ l/ z8 K; E& T3 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 K& }2 U V. K. P. k, a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% m0 t9 W! p; ^0 vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, M2 P" _ \6 C3 B. Q# S1 C5 Z
}
" o6 p$ v2 I, F$ n6 o; P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & f6 ~8 r0 h' {
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