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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 Y/ S4 R( a4 Y: ^' P Oinput mcasp_ahclkx,# ~; M8 v/ b* r! Q: j g& S
input mcasp_aclkx,0 q6 m' o, t+ w' B
input axr0,, L' v0 ~6 y: K- ~! i2 s7 c3 E
% D# Q- h; a! S& foutput mcasp_afsr,7 p$ e9 }# u" l( c
output mcasp_ahclkr,3 o5 {; u( v. ~$ `
output mcasp_aclkr,2 u" N9 S6 @" m8 R) w+ L
output axr1,+ c' y4 |: ?( J9 _2 f) F5 Y+ x
assign mcasp_afsr = mcasp_afsx; q4 G$ `! |4 y4 B
assign mcasp_aclkr = mcasp_aclkx;
8 b! X% D5 H6 M7 W" S6 T0 z7 M3 Iassign mcasp_ahclkr = mcasp_ahclkx;6 K1 Y& C0 B) Y+ S1 h: T. u9 G
assign axr1 = axr0;
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( |9 S& A/ O. u4 }* Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 X- y# N s( d* U/ C+ kstatic void McASPI2SConfigure(void)
- p7 X7 E6 P# ~* G3 j0 Z# d9 p i{ _7 J$ Q$ r- L. n; h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! o4 z2 m# n1 D" {3 k# ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 x H I6 x% b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; u/ i* y: q) K0 {3 f7 C; g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 c+ y9 g( \: U a* Q% V% o3 [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) Y" D2 Y$ X) x* ^/ z
MCASP_RX_MODE_DMA);
4 ^$ x; s3 s) {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, s* j- E0 ]% E7 E" h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 i m a7 z2 q3 qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + s8 q/ O5 p6 V/ \) a. A; @2 T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); Q" v2 b' K3 }, T9 }2 `, k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
X% C- r; X- o' T* CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
^6 L8 _, h2 y7 h+ c/ u; |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, y" O% M) t, H+ I$ `: E0 tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) X+ P+ I* T+ F. K' c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 ~* ~6 V0 z n3 D9 d1 K' M0x00, 0xFF); /* configure the clock for transmitter */
% H' L7 u/ c& ]& ^; p9 ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 y. D7 n0 ] K! ~$ uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 g+ Y, T; x- U: y7 S7 r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 V+ i v- c0 j2 _
0x00, 0xFF);
' ^1 A6 J- J8 B! b& M3 b# A8 T* s- S' Q: J7 y/ `, ^/ A
/* Enable synchronization of RX and TX sections */ ' A+ v* u2 g5 }9 R; f# j# E( {' o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 G) O! |" m# i0 F N- @5 kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% c/ H" O7 K9 _( ~. H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% n6 J5 B& ^' k1 ] _; M% r
** Set the serializers, Currently only one serializer is set as
! m9 C& }, v* l# Z( d, V8 u** transmitter and one serializer as receiver.
, e& l% `6 U( K4 |*/
$ C, R- c; A# x/ `! _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ V9 U% z& u0 w7 A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 q* K8 a2 a: c7 M
** Configure the McASP pins ! G$ _5 `) [; n" {2 K
** Input - Frame Sync, Clock and Serializer Rx" d: q0 e# H$ Z7 o
** Output - Serializer Tx is connected to the input of the codec # c- M# A9 R1 p2 O
*/
8 J4 K9 S. ]% ]# o3 P& X0 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) Y- b0 d6 j# \' P; C8 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) q" s% u, `5 v: e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- \% i' s5 d- B, R) ?& d
| MCASP_PIN_ACLKX4 G0 S7 {# H# L. W) R, ?
| MCASP_PIN_AHCLKX
/ M& S3 m: T- T6 w9 S0 ~* }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 E! d: A. \5 K. F9 u+ n0 I3 M/ ]& Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ R8 g3 h1 g' a% i
| MCASP_TX_CLKFAIL
9 x0 j! d7 P/ N3 ]| MCASP_TX_SYNCERROR
2 X3 N$ K1 _% `9 g* i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & k1 r3 ^+ ?0 _
| MCASP_RX_CLKFAIL
8 G# i/ ^' M7 l( L| MCASP_RX_SYNCERROR
1 B1 x# ^. ? X% d A0 {| MCASP_RX_OVERRUN);1 E i0 U8 n! ]( _
} static void I2SDataTxRxActivate(void)
! @) J2 @+ [' X{
/ m6 w6 Y3 i. G3 ]% e- V# g" w1 ~/* Start the clocks */
3 [! c5 M2 E0 e6 O. nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ @; s z4 M; V+ Q: r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! \6 c+ ~+ d- k1 C. f1 O8 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," l3 B4 T) h# d( L
EDMA3_TRIG_MODE_EVENT);
: j, _" @% j5 ]0 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; M2 n& m0 R y1 p z; |) jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 a. k- H' L. }2 |. F* n: |$ @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
t$ ^7 @- d/ |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% w$ g% i6 y2 a& F0 f" l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" _2 {4 o7 U4 Q: N+ A# v3 _5 q7 ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 E* ^# C, x# t$ v" vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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