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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 _" J1 ^" f0 a( ^! S1 ]: A0 A" o1 }3 V
input mcasp_ahclkx,
/ Q& J0 _6 m2 H n0 `" a% ~- Binput mcasp_aclkx,
" @3 `/ \2 K$ ]2 q5 tinput axr0,
. V8 ]2 Z+ r' {$ J" x2 p
4 l5 Y+ b* Q9 _7 c7 r/ Soutput mcasp_afsr,, y1 x1 M: u6 I7 H1 u8 z
output mcasp_ahclkr,2 H; ~5 ]: U( _- ?6 B
output mcasp_aclkr,) `! }! a4 S2 k/ |6 ?: C7 Y
output axr1,3 T6 m: u, T0 I
assign mcasp_afsr = mcasp_afsx;
- {+ {: [+ e+ x6 R4 V8 Sassign mcasp_aclkr = mcasp_aclkx;
, D) L, X7 v; q; S: Y8 |assign mcasp_ahclkr = mcasp_ahclkx;
! q7 v' ~7 s" q: F% V4 hassign axr1 = axr0; 1 w- j9 M0 I, |4 n' i" H a* w( Q
6 T* E* H5 T. i& B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 M# j+ v; f$ Rstatic void McASPI2SConfigure(void)
7 J2 E6 F* ^1 F7 j9 U9 x2 v) r{# T1 T7 x, c" G) A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. k0 h4 b' _. W! J% L$ T3 e( QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 w) k! a2 k, j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ p3 Y' N9 ^- SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( ?! `9 N1 \, IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 D5 z% S9 [$ |- r
MCASP_RX_MODE_DMA);
, z: H+ o- p3 T9 Q% ^( Z3 WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 g$ J. w* l2 [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ e1 W' \* ~4 O2 Y/ G6 |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" O9 k9 z, a6 }4 Z2 X9 P& [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, T4 c' j7 e; U& h; E% ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) t# ^! K: k4 a! m7 j/ MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, T, |8 n8 t" [ RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; R6 ^" r1 H6 m" S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / R, m0 i3 E5 F* B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 I3 u# O1 p# i0x00, 0xFF); /* configure the clock for transmitter */
& f" [. ^# ~: D) H# Z, wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 B3 [5 E1 T5 b8 Q; s* |, r& [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % V H/ Z* p5 Y& Z7 h0 A `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 r. W+ b7 F6 t4 Q- k% V. q0x00, 0xFF);
8 q3 d5 @1 r9 p- q% t4 @/ ?1 l: T" {- ^% e v. p
/* Enable synchronization of RX and TX sections */
1 |) V6 ~. o/ ~" T6 x- w6 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' `, W+ y' b/ \' ]$ kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' _+ Z: K$ A( H! l7 W# x7 E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# G. p8 n& b5 X4 Z( u3 c6 q** Set the serializers, Currently only one serializer is set as! |. L( j4 t% \/ s' {( C6 w3 i
** transmitter and one serializer as receiver.$ ^, ?, z; t: ^1 |& }
*/
( Z4 p; f- T& M) H% v! O0 v2 dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 F- a8 `8 J; ~; c1 i4 D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 W0 b. Y8 c5 V7 D2 M) w
** Configure the McASP pins
9 G2 D+ s B' j6 m** Input - Frame Sync, Clock and Serializer Rx
/ a6 m' w! h1 O& U( B** Output - Serializer Tx is connected to the input of the codec
j) d7 W, f/ v: z5 k( j# x1 e*/
% }, ?$ o: Z) iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 x8 z }% ~) n) [8 X* ]4 F- zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' l; i; J! A8 ~# Y" Y+ R A& E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 C* p; X" B5 W! R# Q
| MCASP_PIN_ACLKX( a! H2 P1 A6 {& Z
| MCASP_PIN_AHCLKX
, r2 `1 j( w$ o& O3 O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 K( D4 j1 ~+ J( A; ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % i; P: ?4 R k7 f- P4 i
| MCASP_TX_CLKFAIL $ ^$ z2 W. P4 X6 @, |
| MCASP_TX_SYNCERROR
8 p+ z/ v0 k) z% c( ^# w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' g) z: B. I0 `4 d' g% m: K| MCASP_RX_CLKFAIL
) s z/ g& e7 ]* N O7 J| MCASP_RX_SYNCERROR 8 @/ i4 C( s, c5 c9 t& X1 h6 z S
| MCASP_RX_OVERRUN);
3 ]& j( ]- v! S5 Z& w; V% ]5 g& a: R& j} static void I2SDataTxRxActivate(void)* Y0 O) s2 m7 j
{
/ A* B' [& J9 V/* Start the clocks */
7 o) @2 k, `' s! p) QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& n8 h& X# k- CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' R% D! s$ b0 J5 |% j; l/ aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 G; h. t" e, m+ W- ^: M
EDMA3_TRIG_MODE_EVENT);& w3 G. ]2 F+ s& [: v) c% a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: M& Y4 H. T( j6 b7 ?( j8 t) JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) ~) @) e+ B, C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& a* X. y7 j- Y6 n4 L3 E: |$ O- c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// h" P1 K e8 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 \% v5 l% k, E4 R. a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 h' j, t. w( c* l8 X$ J0 r9 W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% f' T- K* I# z, a
}
8 \1 Z4 I# B7 N2 Z% \( b( p. f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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