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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; \' ^( `& Z2 X# ?7 ]0 O
input mcasp_ahclkx,
; s+ c( s0 m9 \1 l9 B9 {: q5 jinput mcasp_aclkx,; F! V1 j2 L, U% c, _+ }
input axr0,
. e B& G% |% U+ Z5 v. ^* V6 h( V; B/ M1 L* I
output mcasp_afsr,
! u1 Z0 w1 v( x6 ^) T E4 S7 [. routput mcasp_ahclkr,! p7 E0 |& n* c. Y1 I+ }
output mcasp_aclkr,
& Q2 }" X' M0 Q- Foutput axr1,. E* s1 H3 T& x
assign mcasp_afsr = mcasp_afsx;
) _; @0 n/ b6 N# [' t Eassign mcasp_aclkr = mcasp_aclkx;
- ?$ H5 J" I9 @1 i3 Dassign mcasp_ahclkr = mcasp_ahclkx;
0 z9 b, H' o! |& p; h/ m0 {& h. dassign axr1 = axr0; 1 F0 P! \6 W+ L8 _
, W. c" t# B* z/ b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% R6 K- D) y! x+ e0 w& w, nstatic void McASPI2SConfigure(void)# A* v L) b& M p# _' s) I
{, Y/ |3 g3 ~5 {, L' F5 a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 a" v6 J1 M! O+ ~5 ~1 ~% B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
L) z; m1 e% q% JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 l: E% ]# n+ _4 t- O9 iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ `' ?( N. ~; U0 f- O5 t$ {+ Y/ n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( R, _* |( q* X0 W! u8 R* QMCASP_RX_MODE_DMA);; [6 A) C1 i- G6 K) w. K2 g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 Z! p. X& V7 A5 t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ @; P0 `3 B5 S2 t2 PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - x# I% N. t) N, U% c6 r2 ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ @+ r3 w9 J6 K2 NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . B6 W1 c M' {- ^0 p+ z0 P/ h* V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 k6 [3 O( T' o8 ?5 s" h9 A- hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 b7 ~) A* _2 b+ v0 g' y7 s( z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 X. B& ]5 P: ~' \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) e: U( c! W6 E- A) A: h0x00, 0xFF); /* configure the clock for transmitter */
% O- p9 P/ O8 d& M( o b$ N" NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 I. [: L0 l: QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : e `: {+ o7 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. F1 U' y- r6 G: l4 A( {" ^0x00, 0xFF);4 S" a4 ^6 N" j. |8 L$ K7 |
' e5 r. E. ?* {" J' g
/* Enable synchronization of RX and TX sections */
( Q" t% I$ o/ l# ~9 KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ p" |% N! Y3 w2 J8 d' t' d* d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" ~6 c7 |0 h9 U2 Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: l3 R+ M! a1 Z+ o" G
** Set the serializers, Currently only one serializer is set as
; q" M, i& Q! R" d6 a' f** transmitter and one serializer as receiver.3 L3 ]! o3 V7 o2 t3 e
*/
* [; K/ e5 W3 N) }, t0 d) u8 XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. u- G& y# u) A4 U( r! tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& x4 h3 H: g) ~) u** Configure the McASP pins ( M' q/ }% L2 [, f9 o2 O# }9 l7 @
** Input - Frame Sync, Clock and Serializer Rx
6 N+ Q9 u! A5 @0 U$ {0 p* w- i** Output - Serializer Tx is connected to the input of the codec 9 \2 C! J3 X- k
*/
" Z3 n. x& c1 H* C# O; W7 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: x, f* g2 q8 e+ ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 {$ W6 n) w" }9 q* y0 l$ B) C( |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 t* s% p- @, ~4 c| MCASP_PIN_ACLKX! r4 ]4 \* R- r- e# Z% V& \. Q+ H
| MCASP_PIN_AHCLKX9 n. m/ a X/ O. y& m5 G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ a; x: p7 C4 Y$ ] VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR R S) L$ f' l8 i. `5 s
| MCASP_TX_CLKFAIL
+ r; w! |4 h' X# z1 |) i, x9 I| MCASP_TX_SYNCERROR0 N1 ?( C0 q$ b9 E1 z3 c. M: R$ c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' K0 `/ H! |; a) S| MCASP_RX_CLKFAIL% b$ K- I) d. G2 X G" T# g2 ?
| MCASP_RX_SYNCERROR / c- Q8 b o) k8 h' u9 K. E
| MCASP_RX_OVERRUN);
8 ~0 n0 O% F, f5 m} static void I2SDataTxRxActivate(void)2 s* J, d# H! W* Y
{- A- @( k( W- P
/* Start the clocks */& ^. D8 Y4 {; |! F4 k) A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: |" t: B8 b; j, A3 E. qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- i" z) y ~2 o' v* Y( o2 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" _1 U2 u& ?0 s0 h7 r8 KEDMA3_TRIG_MODE_EVENT);
" H2 B; @% T( c1 s3 q5 y% YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 F" m( x% _( H- t- R2 b! w% _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, B2 Z) Q- Y8 m% ^- N5 N1 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" x' z l( n- U* a4 ~: H$ h- {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* t) I+ K3 f E5 F' v) R0 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& q0 b' b ~) T. z. }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 N1 J# x1 [; ?7 I R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 _- z2 Z0 n$ L/ B- k ]
} 2 D( I$ L8 Z. H- X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 b3 G0 U9 u% ^4 @$ J! u7 a
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