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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; ~4 n* s' {7 z x0 ainput mcasp_ahclkx,
! ^+ Z, L1 ~3 u5 S1 i( t1 |: binput mcasp_aclkx,; G; d, q3 z( D# E
input axr0,
' l4 g9 ~2 B8 u
# } u. h) ~. k9 n1 [# J% ^output mcasp_afsr,
) W4 X: a) G7 a0 J! Houtput mcasp_ahclkr,
6 z: u' c6 u0 D& D m5 `9 \/ routput mcasp_aclkr,# v% S' i( {9 ~* \" |' `
output axr1,0 G4 T7 ?+ B5 J4 x
assign mcasp_afsr = mcasp_afsx;" r8 C+ {/ T$ Q# F
assign mcasp_aclkr = mcasp_aclkx;
1 |- f( ^) Y7 A; D% Tassign mcasp_ahclkr = mcasp_ahclkx;
# |$ r1 T0 F7 ~% L# n7 d! j' tassign axr1 = axr0;
( \! h- s6 T! C& b; t. I, T& }* s+ b! L: s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: f, o4 z, v& Q2 C- x Mstatic void McASPI2SConfigure(void)9 \. k8 g5 E' z, X- J
{5 G( _) z( N7 ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 {! W0 B) |7 M" i& |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: c% ?1 J# p, t: ~" u2 y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
I4 W* u. y6 K5 t& {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: {4 [9 m9 @( |5 V% W9 q# u6 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: }8 R# `( [9 B6 K& ~2 DMCASP_RX_MODE_DMA);7 d: u, Q5 B# p7 R& h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 c, v' O/ X% o# h! G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. T0 K! U' t) L" ~* w1 f) dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " M8 b- d& @7 y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- @: u) Y* ]4 h8 Q$ _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , ]! ^2 N: \# F; C7 G- K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* J/ ]7 q/ Z) L2 I; Q% l5 I0 oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ t5 e" g' S9 {' d/ _# H7 QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , T+ I4 @4 g/ `2 u& h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 \9 G+ J( W$ K3 i5 m) w" Q
0x00, 0xFF); /* configure the clock for transmitter */ G( k' S6 m9 ?2 t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 L/ X: ]: F6 L# k% O7 M' _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 l. y' i" e i& f k( ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 o4 [4 K. C* D9 q5 G0x00, 0xFF);
. m# m; V% U7 m, |; c; C* c' F8 C2 t! v' r
/* Enable synchronization of RX and TX sections */ 1 A; L# G' C7 r. a3 T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, z% \, K2 u2 ^ Y8 W/ d8 oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 E# [1 M& p1 |! ^% z1 e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* g X1 e0 B S5 o$ D** Set the serializers, Currently only one serializer is set as1 z! C: g; C# W$ Q" u* c
** transmitter and one serializer as receiver.
' L/ n$ [/ m" T+ p' ]2 k0 j5 Q*/2 X' B* W4 N/ y% z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* m$ g/ _1 P$ ^) mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 w2 @: @, k8 O
** Configure the McASP pins
; l. @6 g A+ H+ C" z; M** Input - Frame Sync, Clock and Serializer Rx
: b) ?: D7 e; Z5 o, h** Output - Serializer Tx is connected to the input of the codec
. E1 q' I! p2 Q6 v*/* j. e5 e* S6 Z: F2 H t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 H1 }# t/ C( c& A& n; _2 _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); S4 X: m5 r, j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: B' }2 ~" W3 h1 y4 H, u) o| MCASP_PIN_ACLKX* q3 D5 Z' o" Q0 }* Z7 }
| MCASP_PIN_AHCLKX4 L4 L ^/ Y( D- j( b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) S0 {* ?, V! P- b8 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& V4 ?' L$ l- N) ?1 x| MCASP_TX_CLKFAIL
" Z: ~2 [, P8 G+ ?% ?| MCASP_TX_SYNCERROR7 q8 ?- K, n. D! B, r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 g" a1 p# }; M' ? t) G- G
| MCASP_RX_CLKFAIL; H* s& l1 x; U( A/ b. t3 D
| MCASP_RX_SYNCERROR
! d5 _# a3 g+ w0 D# i| MCASP_RX_OVERRUN);
3 k" p) j6 L7 \6 x8 m} static void I2SDataTxRxActivate(void)
( Q9 J7 a* s4 L7 G{" n p2 J! k* M4 Q1 k
/* Start the clocks */
, A$ Y' v. {9 e! O, `+ V4 \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! Q, u3 \1 t0 E8 L6 w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; ^' r, y% O6 F/ @( `2 `2 t* z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 ~: m$ L$ v7 f' k3 R/ X
EDMA3_TRIG_MODE_EVENT);5 d3 |& [4 m9 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 G( C9 t" @, ~1 Q, H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 b5 k0 h; r }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 d) ?& i% m+ Y3 {/ C1 DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. L2 E/ f$ x8 G! N# Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 u2 u( w: L: @7 C$ ?! G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 n( K1 W1 M: j. ?/ k; `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 }6 G+ `6 c% B* }. _ l$ ^ Z% c} " q5 g- f6 a) L0 |' G8 v3 f% z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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