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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, ~1 S$ G8 B$ m: O1 u4 U6 D
input mcasp_ahclkx,* ^! |% ~) f# b& X
input mcasp_aclkx,
6 ~$ p) T( R( y7 T7 b+ jinput axr0,
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output mcasp_afsr,. C0 o: L. r% q. U! g& j
output mcasp_ahclkr,9 M8 k# F3 ~2 h2 u/ }4 ~, ?
output mcasp_aclkr,
! B1 T" V& C. d% Poutput axr1,
4 G2 g7 g. c3 d& Q+ R assign mcasp_afsr = mcasp_afsx;4 Z- A& b6 N8 h/ ^
assign mcasp_aclkr = mcasp_aclkx;
8 X+ ~8 o: T% {2 W3 l. ^# vassign mcasp_ahclkr = mcasp_ahclkx;3 x- Z# Q6 w O3 F; [2 v+ u9 [2 X
assign axr1 = axr0;
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J- B* L7 w% M7 x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 X" ?1 I' o5 V0 l- \/ Tstatic void McASPI2SConfigure(void)
) w1 d% K6 D" p1 \4 |, A) A4 g* Z{
1 L7 R9 W: g% c' j/ h" bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 S- `* f1 U6 M$ _/ k* C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ t* P0 i" `! K" e$ m" k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ q" ^! D- F# n: \& l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: y- Q6 q: V0 k! E/ Z' ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ {8 u) `) y* g; ^- i
MCASP_RX_MODE_DMA);1 l8 E! B5 B6 ^; m# h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ a, c% q2 c2 O* P9 P# Y' e0 r N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 E$ N. U' u) J( }$ O) X4 R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 `( F, X3 d9 x* MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! [/ b! k" A9 Z( P3 G. r$ m8 q3 t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; F7 g6 g; _' M* s4 `: m# Y9 S6 HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 Y2 d. H: W0 Y& ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% @9 t, b% g% W1 r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# @4 a6 e8 P& v. J1 SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. C% }- F k& ]9 J0x00, 0xFF); /* configure the clock for transmitter */ N8 m0 b4 S. }/ J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- e* \" X3 }$ U* [# z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : J* g1 t. b, m$ j; Y2 a0 o$ Z2 Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ O, s. E' d/ P% K0x00, 0xFF);
5 g. {5 _/ W9 w$ ]7 u* ?5 W- n6 K% G, L# s9 N: b
/* Enable synchronization of RX and TX sections */
2 Q, ?9 t! g. T, dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
U( [6 O9 K: N- {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% f: Q& n& c% H P% @, W% jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( G6 ?/ {$ @/ K& @9 N0 t/ X/ f
** Set the serializers, Currently only one serializer is set as
# \( s$ D( D# M3 u- n& P** transmitter and one serializer as receiver.
# l. p2 x* U0 d0 A: }8 a+ L. T*/
8 o' U; w2 P5 x) u2 s3 J( {! i( H1 OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% B8 U$ z/ V8 a3 F, rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 R* m; Y0 M3 n+ n* f( x; a
** Configure the McASP pins + D. I/ {0 l- @% E R2 k8 ] b
** Input - Frame Sync, Clock and Serializer Rx
+ M' S0 L7 {# I** Output - Serializer Tx is connected to the input of the codec
" s9 @9 Y2 l9 F7 _ n9 K2 t2 y# g9 f9 j*/
2 p! M( i- }2 J( N$ W0 P! P q. WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 j4 \* Q7 e) N$ d! Y1 H" KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ o% g* z9 _9 Q, @: Q7 C( vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! f( Y2 P+ y1 S
| MCASP_PIN_ACLKX
' C; Q; h+ n; u- @9 ]5 ?| MCASP_PIN_AHCLKX
9 B' ]. l3 f" i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' D1 b8 ?- s) _6 m3 P8 CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 U( L0 g9 V. {2 I
| MCASP_TX_CLKFAIL
9 G( m$ m Y) J* K7 S; j& x o| MCASP_TX_SYNCERROR% Q3 ]* Y0 ^) |% ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 Q5 J8 N( w* M9 \1 n| MCASP_RX_CLKFAIL
* a1 A5 v6 S2 Z9 p Y: o! k* `| MCASP_RX_SYNCERROR
1 G1 X2 w4 A2 O; R| MCASP_RX_OVERRUN);
5 @# \: W. g/ h* v7 f2 b6 u} static void I2SDataTxRxActivate(void)3 f$ N. c; Z$ a7 n! W! U1 L+ a
{
- m) H, ~( W: Y: X& R4 J0 p/* Start the clocks */
2 Z9 O. ^* k+ `% u' v e+ t" ~) @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
k1 }- `5 G7 tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ N8 H# R* C* P2 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 a0 M) b0 \/ n3 ^EDMA3_TRIG_MODE_EVENT);4 b' B h6 x+ H1 F: ^# \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 ^/ R& M+ ^: @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- T# L2 c! v' N* w+ c. d. T7 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
Z. ]4 r. K& g7 f# nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 Y, Z6 j w8 p, I7 m7 ?. q4 qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( S! j$ b: I5 X8 L. ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; a6 Q* y% |- o+ C) |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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