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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ M: L; D7 Q; y1 r$ N% X0 v/ Rinput mcasp_ahclkx,) G2 c# m. b- H& p
input mcasp_aclkx,
: Q5 S7 v" ]) M- X$ oinput axr0, m R; k! d! k: C
. d3 a1 b3 }5 F( g
output mcasp_afsr,6 P5 X3 i9 j1 P3 F4 v* b& R$ m8 \& X
output mcasp_ahclkr,4 T# F ]5 t' |6 `& |6 g# S
output mcasp_aclkr,5 t* \0 k4 O- V% ]; f0 c& U% w& b
output axr1,
; I% |+ s+ R0 E' T- d3 [0 p assign mcasp_afsr = mcasp_afsx;0 y: Y( b, F" a4 S+ ~2 f
assign mcasp_aclkr = mcasp_aclkx;( `* A5 w! s+ I8 \* o
assign mcasp_ahclkr = mcasp_ahclkx;0 I& N( {- r6 ]3 X
assign axr1 = axr0; , \' g' Y! k: E' v; k
- N) Z, M) S @: H9 q! s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; Q p( d6 c8 n! p$ tstatic void McASPI2SConfigure(void)6 g' Z2 [# _5 G) x6 ^8 g" h
{9 M7 p. g# o+ {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
s9 c. v- K, [& t/ L2 g2 N5 xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! N. P$ G1 E: v4 i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: h3 G. t" R# d3 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! I7 m; B( N& P+ v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 p) E4 @# Q2 W9 w( F" kMCASP_RX_MODE_DMA);
8 O6 P0 U7 v5 p) L4 O8 MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( K3 X& p3 A( r7 V. WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" o) b+ v7 e' N' f! d2 y$ i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% ?0 D9 J8 A" {/ }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 O+ P+ L( c9 t- H4 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& v! Z% O& x/ y* ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 T% U& f. S6 T6 d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 ]# Y9 D1 R* N. J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! j+ H6 Q# @$ T5 b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- E' ^4 P8 D3 I/ @3 f
0x00, 0xFF); /* configure the clock for transmitter */
+ `6 T2 B6 q* G; DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" Y3 h% Q8 N6 f2 r( P7 aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( ~+ P8 }" }4 V0 Z$ X% K* zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 d% s% a( A* G8 T1 J4 f
0x00, 0xFF);
; \7 L$ J. E/ x$ N9 a r4 v( ^0 t! [. V" w- z
/* Enable synchronization of RX and TX sections */ % Y! h1 b( W. B! D" a4 a0 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: Z1 I/ K2 l, U8 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 V; b2 E: V- QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 k( ~* k- H2 }+ q
** Set the serializers, Currently only one serializer is set as8 l/ V2 v3 z3 {% }& m0 `3 Q' n$ N% I
** transmitter and one serializer as receiver.# [- X- i: g$ ~1 M% Q$ b
*/0 `5 h& t! [! I8 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; e' r6 x6 G# @0 W: `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 G7 @$ Y n, ~* d0 J** Configure the McASP pins
1 v# b4 A% ~$ r" A** Input - Frame Sync, Clock and Serializer Rx
; K; H( z8 m* l/ v5 e! }** Output - Serializer Tx is connected to the input of the codec
# E. H- N& r# y! d/ W*/
3 _8 q; V# d1 s' w; BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ `# H4 q2 q) m$ RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. R6 O, `' p+ c. s" z! C- C9 A9 ] pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ @' c; ~3 g1 |6 Z# a
| MCASP_PIN_ACLKX+ A1 u5 b. Z$ j
| MCASP_PIN_AHCLKX" q7 D9 p: f% y M5 _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 \& n+ U( O- ^9 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 K6 D$ W# S1 |, ^6 e+ C O/ v$ M' P# j( {
| MCASP_TX_CLKFAIL
6 }6 o( o" L+ C& b4 I| MCASP_TX_SYNCERROR
- @' m) p. `' R( o$ E: z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% I: F7 e# u7 [+ e; `: P" n| MCASP_RX_CLKFAIL1 `+ D( s; n2 H* b& u
| MCASP_RX_SYNCERROR % V( _: l) M% H1 R1 P2 [( w
| MCASP_RX_OVERRUN);
2 L, v8 P2 @$ X8 a} static void I2SDataTxRxActivate(void)
, I, D& Q; v; ~ G: F% C{
# t* z) w" u2 p: n4 H/* Start the clocks */- H. c4 E# e/ m8 m, y7 k) W/ h% O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 Y. t+ `5 n% l0 S6 L! q* d% ~) v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ O K& r8 t& [) B: f9 N% \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! ]) q0 U P) t2 H( D2 fEDMA3_TRIG_MODE_EVENT);
' _8 b8 V" b" Z, a* ] g8 R* yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 G2 W# s" D+ |3 TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" U7 F/ m, |: T9 v* l0 P8 A! vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* N9 Y) J5 b1 S1 P8 x% \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 }* @0 {' e" p7 P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 {2 i; j. {1 j+ x8 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 \ v. E8 y" I) m+ d5 w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 @ O( [( z" O+ o} # L7 P: C" Q: N6 M$ u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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