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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( l. Z% ^6 ~4 `0 k
input mcasp_ahclkx,
) f! z( ?" i( f% D/ ~) Y! Uinput mcasp_aclkx,% A, q5 q" [! b! P: x" `" a
input axr0,% o$ r8 t5 [2 V0 J' s; x6 U' V
) V3 x( y6 y' _0 e+ j3 N' koutput mcasp_afsr,$ F' } A7 t& h0 j/ x6 L& ~+ b
output mcasp_ahclkr, A2 A" F& B, ]% g* D7 a$ R- Q
output mcasp_aclkr,
4 v8 q. s; g" k+ woutput axr1,
4 U8 g0 q$ | L1 J5 L' f1 m assign mcasp_afsr = mcasp_afsx;
% y2 \0 G( A: ~8 G" @1 Q/ P/ } ?assign mcasp_aclkr = mcasp_aclkx;+ ~& q+ }# m) q4 Y1 p- w
assign mcasp_ahclkr = mcasp_ahclkx;9 R& a8 ]1 t7 _$ U0 V2 c
assign axr1 = axr0; # J8 J' z3 x# R1 U2 ?
1 b- v% s A) y: O" E' ]+ \9 p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% u1 v6 F7 t% p K( t+ Estatic void McASPI2SConfigure(void)& b1 v* v7 k ?% x2 \4 Y$ B
{5 H2 b6 I$ q# P6 L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% z# j6 @1 y6 e1 G" uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 x& q. b' l: Z7 U. n* J) l9 S. ~5 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; u" l5 a# Q: z& d& S0 I8 IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// g$ u. Y+ y& L% A$ s9 C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. p( N( Y' k$ ~: r" W
MCASP_RX_MODE_DMA);
9 f5 ?2 D7 y5 nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& F* Q1 Q8 t+ U# j$ y& t! P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; W9 w' b+ A6 W! CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ }( _0 D7 m j- h0 \& B$ MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* G9 I; P5 v9 Z+ y( l0 `8 T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / N2 i% q0 n! k* v5 ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 i) K, m0 e/ |: J7 T8 ^! ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: Q8 Z6 U- R7 G k) p( FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! o" L" d4 o1 _! P! B: lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ I7 a! F1 o+ ?; W
0x00, 0xFF); /* configure the clock for transmitter */& D B8 F: ~9 W. R# o$ e% i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& q6 c z' R! e5 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 D7 D6 D5 j9 ^' K2 z% N, t" ^5 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ E1 r7 V* L! X: I& C
0x00, 0xFF);+ x% h4 P5 U0 \) e
: Y/ i; Y5 M. u. k' s: }
/* Enable synchronization of RX and TX sections */
. Z5 S! \6 L. N. o: l- _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 d8 B y/ T/ [4 g6 ~% n8 G0 F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; @1 y0 J4 L: R' G- MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# V/ N5 D, g* I. f7 a** Set the serializers, Currently only one serializer is set as# n8 V# A- r1 t& h% X
** transmitter and one serializer as receiver.* H; d) W' v" n; S% @3 w
*/
7 F8 a. r8 r v5 N* cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 k6 O) f$ ~& @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
R0 K# `+ _3 ]0 C* _8 R6 [** Configure the McASP pins
0 }; ]6 `- w% q# ?. ^# S** Input - Frame Sync, Clock and Serializer Rx0 b9 n! \( `( e# r/ h0 | U/ h" t/ a/ D
** Output - Serializer Tx is connected to the input of the codec
; \* d4 y8 O/ \* s2 s! W5 L*/
* x9 u4 d: O$ }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% U) W9 ^3 I1 B/ X7 x' L, `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 c: x+ T, a6 U- ^# QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 W: b, S$ `9 C4 j a| MCASP_PIN_ACLKX2 U( [3 X( G+ F3 S2 |& r
| MCASP_PIN_AHCLKX: \) o# K, D& u. E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& }% V) u! t) V. H" f w5 l2 G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ g: e9 w) @2 Z| MCASP_TX_CLKFAIL
. T1 B7 q" R% E! ^| MCASP_TX_SYNCERROR
% q- X1 {" t+ X. z4 k9 ~. c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' R" o/ b9 j- F( P* f% i- y
| MCASP_RX_CLKFAIL
* m6 f- b( ]+ E8 I! t* L% |3 o| MCASP_RX_SYNCERROR
o) Z# K: J& D| MCASP_RX_OVERRUN);+ Q1 P9 I3 }/ @0 C
} static void I2SDataTxRxActivate(void)- X9 Y4 Y+ m$ S0 M- E$ `
{
" ~; |* ?' A7 n! n# A/ M7 V8 X! h/* Start the clocks */
2 g! t3 A8 Z; S' j0 mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# a( t& e- V% D) T1 T6 `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 H* R1 s G) \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," S9 o( i, H0 g
EDMA3_TRIG_MODE_EVENT);6 g. v+ |" R/ X) q, v/ k1 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( t4 \, X1 C. ]6 G- @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' f9 P+ z t& C) Y6 J6 j: o5 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" O: ? @0 K( G+ c3 l. cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% R# @1 ?8 w# Z) y J. b' wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% J, T2 v1 h, _; ^5 Q) ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 k( H6 I. [- P' F) ^( yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. i. {4 x2 T3 i# c% P4 r}
5 W, T( O, V! l. w! `& y: }7 l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : F% s; z+ h8 ~' b, h! H
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