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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 H; C+ Q$ s% ~2 c3 a6 E" }/ vinput mcasp_ahclkx,: i$ [$ P, ^& u" m4 [
input mcasp_aclkx,! D, e+ }3 o( r0 H/ }
input axr0,
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6 V4 l5 G7 R9 O, ^output mcasp_afsr,
5 {% `( n, d- E- D4 koutput mcasp_ahclkr,) H3 a7 M0 y! G" A. P: G1 T
output mcasp_aclkr,! _: z0 ]6 V" ]. a" u. M8 |
output axr1,- H, s" V4 T! ?* H8 q3 [; M& F
assign mcasp_afsr = mcasp_afsx;
, w4 a' J. m/ W7 _3 d$ u, ~; Tassign mcasp_aclkr = mcasp_aclkx;
! y% z2 v1 q& H2 ]5 W- X1 f6 zassign mcasp_ahclkr = mcasp_ahclkx;' q3 Y2 l9 D) I- l- f4 K$ {
assign axr1 = axr0;
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6 U# j! t6 ]3 @8 z8 N; J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; Y; G4 K5 @4 A7 o8 I3 d/ D
static void McASPI2SConfigure(void)0 G7 T; x# N* } i: \$ j
{
, U0 _" H G2 ?, o) vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 ]1 x* i% o- N( Q2 t) Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 z7 l2 M9 }* @6 D$ q+ A hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 W) J4 m+ G3 {3 a( S; |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 f* F$ E# |/ S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; D5 `$ ~) I: d" s5 ~7 Z& @
MCASP_RX_MODE_DMA);. N+ @3 V* b* `) O" I3 y* p+ t2 L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 R; h" ]! y. h6 |& H6 ?5 H9 T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: O- {9 O" R% U3 o% x0 p* p" Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 R- _, _0 k9 J9 ~! tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) o. \" I9 I; [3 g7 S Z! O" H: B, [2 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 v/ V. g7 u6 \( O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" N+ q7 h, E. j% n6 a$ M0 PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 c2 A, w4 F% R; cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( [5 t# O/ t$ [, X) C! d& l5 e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ z% L8 L: w+ I+ y
0x00, 0xFF); /* configure the clock for transmitter */* ?" b* M1 t* t1 P4 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. X+ @) G+ G! a! Y5 c- v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, w7 x& Y9 [) D8 k5 iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( p1 B5 r7 ~3 w0 `2 H
0x00, 0xFF); O* a0 W' a$ Q Z
6 [6 r/ j6 d+ ~3 H! s( m
/* Enable synchronization of RX and TX sections */
) t/ E" K- i6 k0 N' G/ q+ kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ s b% n5 w/ m0 ~6 I/ p! pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 {+ x1 Y( z- A2 G* S: e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 @, w' T+ h& `' V" e
** Set the serializers, Currently only one serializer is set as) V9 D8 B ~, Z
** transmitter and one serializer as receiver.! b9 E' S6 q: R% p
*/" \5 _ K- R" d( w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 P6 o# r# k4 o4 Y7 OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 \ |7 V. I& t8 w/ t** Configure the McASP pins
& U. B6 r ]9 E% B+ r! h** Input - Frame Sync, Clock and Serializer Rx; v) C) E* t6 |7 y
** Output - Serializer Tx is connected to the input of the codec ' I9 R' ]3 x( S& l
*/* L5 s! j5 ]6 @6 b, [$ S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* }& B1 v% z1 B1 H- `* U, ]5 dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: T9 v* K2 U! \. J7 t. B& }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) t) a/ P1 b) P! t7 `/ y+ @
| MCASP_PIN_ACLKX
0 |# ~; z* s& w8 h K) C8 W, M. y| MCASP_PIN_AHCLKX4 W1 W2 A( @ e" K5 o, a$ Y% C' J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: q/ g$ L' q$ z" oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - J7 K5 X8 u4 z# {
| MCASP_TX_CLKFAIL
* N! c3 O8 N4 c| MCASP_TX_SYNCERROR
" c4 P$ V" f& n9 p: R/ m+ d* ?7 O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' j1 c6 x; |6 l5 R
| MCASP_RX_CLKFAIL7 y! e1 e4 W9 `. H
| MCASP_RX_SYNCERROR
7 B% ?- u% Z. J4 S/ J| MCASP_RX_OVERRUN);/ E. T3 C$ v8 n
} static void I2SDataTxRxActivate(void)
: I! B( ^, N, J5 M1 Z{7 G/ Y+ ]) |( a/ W0 Q$ {9 v
/* Start the clocks */7 E( [ l- v. v. `: e9 |* Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) c9 b* Z6 d* }0 H; lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' B& F2 z& {4 Q0 _& dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( b5 i) [# a5 L/ J- S7 i# i
EDMA3_TRIG_MODE_EVENT);6 O1 T: I8 h8 v& P3 }. v# I+ I8 f& z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ G2 W7 c- {! ?: WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 t) @, L) e9 X$ C: x6 C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ z" i5 \" Y0 G) u3 Z6 t2 z+ l O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. r# d: v, z% Y' z+ T6 [6 E) u& F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 ]8 R2 X: A6 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% Z; T6 W0 Y8 L, A! AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; u3 r1 U. q& O' e1 }2 [5 }. A! `}
+ `8 H8 r/ |8 f" X) ` n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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