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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ D" B+ _9 v; |( [/ y7 E
input mcasp_ahclkx,
. A/ R* w9 b0 ?$ |% j1 k/ rinput mcasp_aclkx,, C/ U1 s2 ?' o2 i, p: J
input axr0,
% }9 ~8 `% n8 C5 Q9 f/ Z
5 t* Z y8 ]' A" D% i, goutput mcasp_afsr,/ w, u8 X& J d
output mcasp_ahclkr,
0 O u6 @7 d0 `9 Q' foutput mcasp_aclkr,
; G3 `( n8 H/ soutput axr1,
" _1 V: b* L. Q+ j assign mcasp_afsr = mcasp_afsx;5 o. c/ O0 f( h* e' E4 r6 N# V
assign mcasp_aclkr = mcasp_aclkx;
' B9 r9 }2 ]6 c0 H" l: J5 hassign mcasp_ahclkr = mcasp_ahclkx;
4 q+ V( V" b% e" x2 F* hassign axr1 = axr0;
, n! T5 ?2 ?( H+ v' l- n+ S! A' A8 W @1 }4 O0 ^! C- `7 P* u/ |0 S0 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: O- i4 _7 [+ G8 H$ ]static void McASPI2SConfigure(void)5 B; w: _ y( t
{
' x8 V+ E/ G2 M; E. GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* U2 k/ q* u F( w9 ^( eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: h) |, |/ I$ F" w" O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" T# U: a/ V GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- h2 Z+ H+ Q' \4 u1 T9 w6 O3 AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: ?/ r5 Z7 O6 u( V
MCASP_RX_MODE_DMA);
9 ?5 z A0 ` e2 t% t" O% RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' k7 e# X9 D0 kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# y9 U* G$ p, \$ D$ ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : t5 \, F- j# `: G2 d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: m" }( q# N( h t6 ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 s# {! A* h% N5 D- FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- t# a2 e" K, Q- x, ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 {0 c1 N7 b8 |* E$ c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- b4 r8 `9 r2 t* Z) bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ R% x: P k- \ f" g
0x00, 0xFF); /* configure the clock for transmitter */$ A$ m. I; g) i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& b. n' v& ?* N9 O+ q7 O1 D% F ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# l' ^, k X1 Y3 f9 [) lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& e: P; l/ }* p: i9 Y( ?- j
0x00, 0xFF);
' j: V0 J$ k$ ]. R% O
% ^. K8 f( A* W5 x0 D' A9 x! m/* Enable synchronization of RX and TX sections */
2 c, ~' }+ e* p4 R: V4 q' BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 n/ ~! U) X1 }4 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( J0 J9 P* h! K: X, U1 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, \: J, J" l' h8 X. m** Set the serializers, Currently only one serializer is set as6 i5 v3 @- X$ g$ q
** transmitter and one serializer as receiver.0 i) U9 v& {) o8 ]% S
*/
: \1 w G/ y9 m7 I; |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ A/ o- ], T ?" l! N$ MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 ^, P! N$ F5 T" v
** Configure the McASP pins 2 R8 {' N/ f$ C0 x6 X1 r! N
** Input - Frame Sync, Clock and Serializer Rx5 I. }6 M- _0 w* }4 V% C
** Output - Serializer Tx is connected to the input of the codec 2 h/ W7 \: M9 x! {
*/
0 A% T0 `' B/ K4 ]+ FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 A. Z" d, L% h3 H) Z1 i' WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" H( }( Y) _; U) N) T& ]5 `8 u% J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. x% }4 s3 ]1 `7 Q5 E| MCASP_PIN_ACLKX( v( d! F! w* V; h. ]) N$ x& ] @
| MCASP_PIN_AHCLKX; @6 w9 N: h$ y7 r' u8 _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ f. G4 @0 M# I, _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% _' A# @; d# |& S2 f% F# C| MCASP_TX_CLKFAIL & a6 F5 ^% K5 s
| MCASP_TX_SYNCERROR) D) ~( q/ `8 Q( b1 W/ N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, U! N% H7 U* e. f| MCASP_RX_CLKFAIL
2 B) u- M/ ]2 g| MCASP_RX_SYNCERROR 5 @) U d, A K
| MCASP_RX_OVERRUN);" @! z" ~* \3 n9 R
} static void I2SDataTxRxActivate(void)) u- x" Z7 n( G* U6 R
{
% c- d' K% }( g: Q; u# K4 Q3 m/* Start the clocks */' C: p3 n' V2 S; a j/ d. d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 _& H( s ?3 p" a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( a, ^7 V% M, ?! f9 a0 E8 N& E# v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 F9 h; P/ Y. s+ q& yEDMA3_TRIG_MODE_EVENT);0 Z. L# c0 S1 z/ d" q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 `+ L* Y X# o' m: M# }/ REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. m$ O# c/ x) Z$ U7 ~/ \0 K& uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); Z( V5 ~5 o4 d N! D1 v7 a0 K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 n* g! d) Y5 Z) g: j5 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. B6 L5 X" K: V. w& [* I: Q' b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ P+ I0 y/ [+ n0 ], d- m- z3 k+ F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
P0 f x- `% _7 l6 ]- b; f# k ^} ' s1 O0 T; w8 E1 {/ u- W7 f/ j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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