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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) u$ G. z% |8 M
input mcasp_ahclkx,7 P; s$ T% V4 t6 a* _6 k& }- E
input mcasp_aclkx,
9 W$ Q q( c# t7 A' V3 O: N: e1 Xinput axr0,4 V' H& ^ y7 ~ D1 ~& z+ h
: b- I5 H u( O6 {" soutput mcasp_afsr, h9 ?7 W, D6 [$ w- f: S
output mcasp_ahclkr,
+ g% ~- b. k# W: \output mcasp_aclkr,' O6 a+ s5 O# l% o L1 K
output axr1,. e! M' o; \/ w' k/ x1 ~# ~
assign mcasp_afsr = mcasp_afsx;
4 V- Q) [, T! |& A, O2 kassign mcasp_aclkr = mcasp_aclkx;' j, h8 C9 _) g5 R" W1 }" Y6 k
assign mcasp_ahclkr = mcasp_ahclkx;( q2 H5 M; p% c4 y u9 o
assign axr1 = axr0; ' ?# x/ t3 D" k2 m+ ?! z
3 j/ W0 q$ T8 F$ N+ U8 o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ C$ B1 `% P* c4 T5 o& v
static void McASPI2SConfigure(void)8 [ q* H% E) l2 J# K
{: c$ ]8 w! A: ]& {. Y. u1 Z! l. i0 @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 G2 [( w% ~ _3 I G+ l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ J( p8 ~) k, h" H+ K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! U, s7 ^6 x8 P9 K/ _! ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 m* c( A" s" y9 Z7 ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 j z8 O4 z9 f" e0 F/ M7 ]MCASP_RX_MODE_DMA);
, {5 R7 A$ N0 m* a6 Z [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 X, T% Z- ?) @7 q, AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 S, I4 r6 K4 u x) ^4 oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , @/ h3 ^+ y9 s6 s6 T+ w/ ]2 U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( H% f4 U: r, g. c4 b9 s) O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 |$ A, `' ^- Y) w! t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- a; Z- Z" W( r1 C: e: \! Y( NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" Z+ H; ]$ B4 ]& z0 C, ~4 _0 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( v5 c, Y H! j$ ]9 i$ v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' Y: ^2 i6 Z. v/ s& r- D4 ~/ E0 }( d
0x00, 0xFF); /* configure the clock for transmitter */
5 d; @, |" l) F/ I8 ~, f' nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 E+ b/ W3 @! T$ ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 t! L2 f4 w! |3 X# `/ p. [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; F/ j9 W- e d6 ~2 |
0x00, 0xFF);
: v4 a, ?" K6 a3 k- b( A5 y
) l5 l+ {$ h6 u! z7 X/* Enable synchronization of RX and TX sections */
! [" j+ l; L7 ?& j( ~% kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 F. `' M. O3 a4 N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) }( \$ u7 s5 M: FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& A- ]. q: X. o. [** Set the serializers, Currently only one serializer is set as6 x: u7 `5 ~, F" g% M
** transmitter and one serializer as receiver.
9 T0 U0 p; a% q& Z' ?7 a/ \. r*/
& L: P& U+ Q+ ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 w/ B8 M& B# H( q$ SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ J' N& g, m* I, Z) C+ L** Configure the McASP pins
9 u+ i2 [5 |% n1 w( |, P4 g** Input - Frame Sync, Clock and Serializer Rx, p& Y' S' u' F. @: C& p0 X
** Output - Serializer Tx is connected to the input of the codec
3 h: v) s8 c' b5 B1 s# f! b. b8 z4 y*/1 c0 z; X* W7 |0 m E* ^( Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ t5 @( i. X0 [' r0 b7 }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: G& w9 q. n/ @( e. r2 gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# O8 ^& z. w R; e# D% r| MCASP_PIN_ACLKX
% a# o5 b1 }) m' e$ Z| MCASP_PIN_AHCLKX
( E5 M. c! ]2 c* H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" v: h' s& H( V! ~6 P' C5 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 P* R, V" m2 n6 g$ I! D| MCASP_TX_CLKFAIL
5 @" [+ h f) G, D4 c- K| MCASP_TX_SYNCERROR$ Y% M; j v2 l6 w5 j2 I- n) N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! A- F: Q M# [( j! {$ u2 H1 M| MCASP_RX_CLKFAIL @3 k# \* |- ?: M4 m* k
| MCASP_RX_SYNCERROR $ B2 F# i( k7 V; q# E3 q6 x% n
| MCASP_RX_OVERRUN);
( B; U D D0 i& f' q} static void I2SDataTxRxActivate(void): K+ ^ s$ U2 P% m6 C5 l
{
' q" V! i6 x" r: r. X/* Start the clocks */
, ^6 A& _7 ?. l% z, w5 s6 f! @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ ]* L/ S4 e6 I' J! i) B; ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 m' I- @5 I G: ^, ^0 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% B0 K* C( N( y9 l& P. Q+ e0 KEDMA3_TRIG_MODE_EVENT);2 c7 @- V! `$ W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ j" k: J1 Q0 CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% o2 P: ]% z2 [+ }1 F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ H* c7 |: h2 R" oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" M* t) X+ O6 X/ ~8 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ F; Q+ H1 ~3 G \$ q) mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 I$ Y, ^6 ~9 L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( `8 i9 ?1 X7 c
} 7 J/ L' j* S0 D6 T& T: u2 g& L$ l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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