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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 h5 I6 j b5 B) P' ~/ k
input mcasp_ahclkx,8 U0 m% |$ S" [* x
input mcasp_aclkx,$ w& w9 y. g8 o& C/ ]+ m1 I7 c
input axr0,
( N3 ]# J* Z' U$ F8 w8 L2 L7 @9 s; h: e
output mcasp_afsr,2 J; o. A* J2 i; |
output mcasp_ahclkr,
8 P! ^8 A$ K) m! s6 F2 W- s foutput mcasp_aclkr,
4 A$ N5 X; f( V- Goutput axr1,. v. i! \" P# M8 z; ~* @
assign mcasp_afsr = mcasp_afsx;
8 E9 d1 T- S; ^$ m6 W9 ?3 U% t* Gassign mcasp_aclkr = mcasp_aclkx;; A* m) q5 N% v- y
assign mcasp_ahclkr = mcasp_ahclkx;
. `# O/ ~, l( z' Vassign axr1 = axr0; , C, z4 L5 G% j* J& B" x+ m
2 c3 N& {: \' W! w1 l7 S: A# N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; r" T9 o9 @* H; p+ S9 l1 Q [static void McASPI2SConfigure(void)
+ _( ~& ]3 g# {) n{
1 f1 d" i4 ]6 J5 j. L7 y/ Y' ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);) _7 a8 w/ R S0 M& Y3 q7 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: _2 V2 _/ D1 I( XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) c6 i- k$ _1 A' e% V4 W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 V- H! B4 c/ u1 W8 R, q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( W7 t: v+ r# tMCASP_RX_MODE_DMA);3 I2 L& I/ K$ Z& ?$ G9 K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 v3 d" S) _2 Q. |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( |+ U9 [3 h4 M8 E9 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + h1 B8 P0 t4 s, g5 o' k. v% r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& X1 h* v. y) u3 g5 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & e! F. u- d2 m, ?; Y7 T* m( F: F5 C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// r' p* U u5 [% ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" Y( _4 d0 `3 t& F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 P. ~) [4 o, d( C0 x/ i( bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 ~9 ]* a0 V8 a+ Q5 w0x00, 0xFF); /* configure the clock for transmitter */0 H! A& h q6 Q4 a! }2 D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ q; `$ S, J( g( M; n. ~$ m2 M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 E$ z2 N. ]5 Q( S: b5 @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 f$ `3 q" B- v! g6 @& r
0x00, 0xFF);
+ e9 }6 X4 o' a$ A# c
1 o% N& S5 l; Y7 q) [, U/* Enable synchronization of RX and TX sections */ 1 K4 d# y% \6 i2 y5 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ H# P; h' h/ j0 W' ~6 t% |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' ~5 d3 k$ |% xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 L( d6 e+ a( l$ [
** Set the serializers, Currently only one serializer is set as
5 y# j8 \: i! P; b* s/ h** transmitter and one serializer as receiver.
E+ h5 z8 Z* G' l' }; O*/" {; _* G! E9 ?4 Q. T4 Z& d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 K! J, s$ `3 {, ?; i7 c( c9 E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 q. Z& m/ K$ F9 Q
** Configure the McASP pins 7 `: q( l+ \1 h, R
** Input - Frame Sync, Clock and Serializer Rx2 P3 H/ d- O' y, N. C
** Output - Serializer Tx is connected to the input of the codec
1 M! `4 ~/ B$ L! Q+ |0 d*/' o9 c; o, k( m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 _" H$ N* ]& ?5 u, y7 gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 V9 ?" l! a( [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: ?- A9 J$ x0 @
| MCASP_PIN_ACLKX1 ~. F. t# t& f. a2 i
| MCASP_PIN_AHCLKX# q1 _) k: J6 @7 a. F! C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 d" }+ o4 J* {; {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; }3 y- I: q" U% r4 s2 g$ N| MCASP_TX_CLKFAIL
, a& Q) B, ~) y. l4 e2 n| MCASP_TX_SYNCERROR% {6 @3 @7 u1 f4 } l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 P/ T9 A9 v+ e( i! o8 T| MCASP_RX_CLKFAIL
4 B- |. g2 U0 P2 S; V3 E" x| MCASP_RX_SYNCERROR
H/ D- n8 e# }6 ~| MCASP_RX_OVERRUN);! T7 o5 x& Q1 C' W9 \( u8 s
} static void I2SDataTxRxActivate(void). [' ^8 z: V$ H, v
{) C( r* e4 e0 ]$ e9 }
/* Start the clocks */
* F8 Y' P! _ ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; X/ x: [6 B1 ]# a* ]7 i9 V% s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. K3 u, Z) X: D+ A! z" K X' x$ WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; N8 x1 w6 e( k9 m8 u# O) ]
EDMA3_TRIG_MODE_EVENT);/ ?/ b2 B4 Z$ T5 d0 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 n( o/ B# E+ i" \; K$ |5 Z5 E# q3 A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. B: {# H( l0 R( E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ K$ t$ E# z D9 ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% d& i5 Q, j" J5 S4 v# \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 g$ n! }. h+ lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; W" u# L+ ^' |5 w0 [2 C: ]6 ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: v- ^9 L1 u. S# A0 b. X
} ) l d/ f4 R4 Z) {6 @! Z/ T8 h! s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # m3 s$ m" ]/ A5 u% c$ p0 W
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