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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ w' n3 f( d/ _input mcasp_ahclkx,1 B1 f# ?, n/ O
input mcasp_aclkx,
$ Q9 Z; j. C2 `6 @! Dinput axr0,9 v- B) ]: W: ?5 |( i
) s4 q) X! R+ F
output mcasp_afsr,6 o/ W0 U: n- a) P4 d4 V
output mcasp_ahclkr,7 m m( i( |3 D
output mcasp_aclkr,, t0 S2 L7 a- V; L
output axr1,
% C# h+ W( G' m# p; m- {; n+ F assign mcasp_afsr = mcasp_afsx;
# x: `$ ?( W- A. j! r" g3 E& \/ `assign mcasp_aclkr = mcasp_aclkx;4 Y0 S( B h5 {1 B" L
assign mcasp_ahclkr = mcasp_ahclkx;" k$ N* i- y( a1 y
assign axr1 = axr0; - ] S: F' h3 B5 K" R
( Q$ N3 @( V2 M% n) W! ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! B! K+ X/ C5 N! F* R" Ystatic void McASPI2SConfigure(void)+ W% }3 L% N8 U# i- s: E$ X( D
{
, o( R D1 r( i" v4 F; J7 J w! f, ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 n# A8 c6 { I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( y3 k- }6 g7 K# w1 IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# v. O0 O, @5 U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
G" Q# H& K0 u9 UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 e& F% g5 s$ |5 @' c5 Z
MCASP_RX_MODE_DMA);5 a' r7 R" A' M( Q, W3 O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ d' Y: ?; {0 M2 G; j- ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& b* G+ b# i1 R3 n: ^+ s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 ?% s2 v9 M9 A8 O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; c+ F3 T5 o2 B; Y; DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, O; P5 y# G6 x1 K, y- p WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- _% d q3 D, r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! ~5 s& D# X) T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" S6 N# O! Y7 C7 F4 e8 O+ f! wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& q0 [- O8 ~# {3 m( O. R- k
0x00, 0xFF); /* configure the clock for transmitter */
9 C2 |8 ~) O s% AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) @3 q1 v& `' U$ d& j% M. R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& Q7 [$ W. ^6 {( K# F B" DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ S5 M% S. v( K! a0x00, 0xFF);
! ]' U0 j3 k/ ~. A. \" x% H( V! d2 b5 o2 q
/* Enable synchronization of RX and TX sections */ ; A1 |! d2 s( L2 c1 d) Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, M4 @% h! F. i; n: ~4 N+ j( B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 z' t; f: s+ E1 d4 U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 r9 v( {# m6 L# l& [# B3 ~** Set the serializers, Currently only one serializer is set as
8 N' a/ C6 z4 \** transmitter and one serializer as receiver.3 n+ `: ?0 I; T; ]7 z: t
*/8 Z- H/ u; f9 n/ p, f+ ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ X' D" b% h8 I9 Q( ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** V: c: {( n. ]+ O0 N% _
** Configure the McASP pins . O/ J) |( t7 u8 \
** Input - Frame Sync, Clock and Serializer Rx1 c6 c9 J g; ?' @% r- M
** Output - Serializer Tx is connected to the input of the codec
& T: X& |: z- R. O*/- b8 C# N- ]7 u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 V# ?1 h. `/ @0 j! Q" \, p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" r6 E$ X1 J9 {% V5 B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 d) e$ T1 `* o( g| MCASP_PIN_ACLKX
, u5 o% `& j5 p8 k| MCASP_PIN_AHCLKX9 Y* p/ t8 d/ j7 Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 v6 A) e5 i9 H$ @9 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 p, M/ ?# z8 \, i# ~. d( J| MCASP_TX_CLKFAIL 1 M3 V3 `1 l5 d- T& c* u4 v
| MCASP_TX_SYNCERROR
7 L8 N* W5 W- x2 @! V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 [, U9 Z+ i2 e1 X2 z& A+ G u, h| MCASP_RX_CLKFAIL4 ~( a, ~5 r- Z7 s
| MCASP_RX_SYNCERROR ' v/ f2 [* U2 I# N' B" `
| MCASP_RX_OVERRUN);
; K) h' U' l S" Y" Z+ B} static void I2SDataTxRxActivate(void)
7 }; P- f6 i- Y; p. d/ d! e{7 I$ D" n. h4 N% y" B% H. _
/* Start the clocks */! x( ^- |7 |4 N7 I, }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ M% f1 `* y; k$ ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// }& S0 _0 l) [5 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ t/ K/ N/ j5 ?. N
EDMA3_TRIG_MODE_EVENT);
) E9 R2 M+ e5 g% XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) F) Z( l% t' k. s9 W- }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. q- H2 n; V2 p% E9 K) w% \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! n! ]% X W" UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ ]+ n2 C d& v3 Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 B: Q7 G8 T# YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 w) p! v; `& pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 d( Q) m1 B5 s: i8 Z& y}
+ \/ e, x( T3 W( m( l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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