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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) t- c o9 y; f! I3 ~1 j- ginput mcasp_ahclkx,
# V' P+ \4 I* N0 C) S7 Minput mcasp_aclkx,# V+ }8 q, m; h9 T: e/ A
input axr0,
% K( |/ T4 q( b. ^9 F% w Z& Q4 Q
( @( B; L2 `6 F9 i7 O3 Routput mcasp_afsr,0 @) ~3 N* ~1 _ {
output mcasp_ahclkr,
3 l6 J! N$ V: V& O9 R- Ioutput mcasp_aclkr,
/ V! D3 L: A3 |# |9 eoutput axr1,5 C- \. K5 a! f- X1 T/ F+ P; a
assign mcasp_afsr = mcasp_afsx;1 u1 C: m' M$ u* ]
assign mcasp_aclkr = mcasp_aclkx;
6 v4 a& v( v) ?( c0 J" Passign mcasp_ahclkr = mcasp_ahclkx;
% V, G0 z! K& D3 Hassign axr1 = axr0; & B6 @1 m4 ~% C8 c0 C5 p$ Z% K
: H' R& m1 _, Y, J6 S( H& M( `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' } t1 V3 c/ S" m8 J# d( G9 E" N5 ?, ^ Istatic void McASPI2SConfigure(void)
( a1 ^3 T" A, v) @, V I: Q{6 X6 @. ^8 L3 ?& x! Q# r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! P# F' N5 o u; H' H! Z: \2 FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% @) p# X! f+ \# HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# y; E9 e- H7 L ]) w2 O3 [! {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 p! E; m3 v" n+ x, |/ g7 ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 r" V2 I$ ]5 K/ W" Y
MCASP_RX_MODE_DMA);
4 I" `/ A+ ?# QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 i% d& g( o- D6 ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 p4 X) r, W6 X5 a' N3 B5 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) o; h4 l; ^" E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
n. f1 a v: |: x+ J! ?+ q* hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 R. g" X" G+ I; i. `) i& D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 w# P4 X/ K) W. h5 u! q* sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 G% A6 e& w; E+ N+ u% v, BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ E w+ N# i- ~# AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 D. x" b5 T" l: I0x00, 0xFF); /* configure the clock for transmitter */
+ U, l+ [* G5 N$ t, jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# K7 W+ D; `5 W5 _( R' OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 [- W$ o4 X- t$ L9 \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 S" S l0 P/ H5 O( y7 @) r0x00, 0xFF);, L% y z( r3 t
* Y) W6 Y) `8 `- ]: m2 t$ S* g, q/* Enable synchronization of RX and TX sections */
0 m/ `+ |0 F6 U2 C' G/ ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 T( b5 @2 ^3 A+ |+ X) t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 ?+ ~; `3 Q5 ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' ?1 I+ ~; B) M' E4 R" i** Set the serializers, Currently only one serializer is set as
' c- \9 c! `3 G* T** transmitter and one serializer as receiver.2 M8 t% h- K; j- Q& A
*/
5 t4 n. r; ]# ]7 d5 KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( G+ a* O6 s' u: ?- tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; b, V" L" h; l8 X. i2 X% R
** Configure the McASP pins 8 c8 V2 D0 T$ B- ~& S
** Input - Frame Sync, Clock and Serializer Rx
7 X. I) C8 u7 K& f3 d! q+ X/ E** Output - Serializer Tx is connected to the input of the codec
4 f) n, Z2 M8 A L5 b; a# D- f*/: U! U; ]0 v/ e) c Z; _2 x4 Q6 g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 }; d- n- l$ `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
F1 |+ g2 Z& T( G6 F% vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 x$ i/ d; C% F' a2 V
| MCASP_PIN_ACLKX
8 r% m8 p- _ t' E9 i) E& ]| MCASP_PIN_AHCLKX" T# h: g( ]% V& X' U8 D& \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# g0 g0 B P x9 F- P+ m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ Z5 V# S: P2 F: ~) k' r| MCASP_TX_CLKFAIL
7 i% ]# g; b2 |4 p5 P| MCASP_TX_SYNCERROR
' p; \) s; v! K3 Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; ]6 ?3 O9 W( j' ^0 X. n; k
| MCASP_RX_CLKFAIL1 q; S0 l3 r7 _. ~
| MCASP_RX_SYNCERROR
. d' ~$ ?, v$ f8 s' ~| MCASP_RX_OVERRUN);
: I) t; q9 c2 ~- A( W' G+ l, t& N5 [} static void I2SDataTxRxActivate(void)
. [. _9 }+ ^. p6 J: t% O6 k{
]! `7 U' W+ L/* Start the clocks */
" }7 a e8 r' p4 N G7 ?0 {0 R. YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 e) U! U! e1 ` e# q0 O" e1 w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 G$ d$ p% E, Q. W+ |1 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. L& T$ R' ]! ? }* s( O8 i7 TEDMA3_TRIG_MODE_EVENT);
; X0 w" N0 L/ B' pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 d) i* d0 J. e% w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ I8 o* K1 Y2 {! N; m$ W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: c; c, \1 P6 e V+ SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! T0 h7 w x) x6 W: u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 R# G! q" ?' z; v* TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 }& T" g; j- z7 a- G2 fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ H- \. `$ F) n( Z( d- j} y- f4 |5 o/ Y: w7 ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 t: k( y; E6 |
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