|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 w" Q* l1 e0 D( J9 a; `! tinput mcasp_ahclkx,- {2 I4 Z0 F+ s# }5 l+ p
input mcasp_aclkx,' ~& W8 z, Y2 w+ v: M2 w
input axr0,
& J0 a5 o$ ]. e: N, h& t; x# L
3 g6 K. V+ d+ T( a2 V9 Y/ Poutput mcasp_afsr,
6 [6 E t' w8 O- n2 i& Moutput mcasp_ahclkr,
5 O$ ~7 a3 |" n( Q% G4 voutput mcasp_aclkr,: P, `; c$ l" @6 L
output axr1,, P$ m! {* u/ L0 C
assign mcasp_afsr = mcasp_afsx;# ^" p+ w( w# ]) C
assign mcasp_aclkr = mcasp_aclkx;
; g ]) F: U2 Vassign mcasp_ahclkr = mcasp_ahclkx;
% M Y B( \- A( r4 Y2 cassign axr1 = axr0; / u4 ~( Y& Z( N. w, T: H
7 B4 R& p3 k% p' R! }$ ^! Q1 t p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ f: v8 r4 b7 i. q( h7 ustatic void McASPI2SConfigure(void)1 _/ b, P5 h$ F7 Y; o$ h
{8 \$ \/ p! b1 G5 t2 T+ ?7 x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& y; a2 l2 O/ D: Z) X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 x4 S, \# s: j5 A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 Q5 [( F. s8 f- X- [0 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ A$ Z" V/ q6 e" QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 ^* j7 O* p+ g, hMCASP_RX_MODE_DMA);- j8 j \6 u5 Q- ~0 Y. Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! Y- D/ o+ H4 nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// s' W5 a6 s# X4 z9 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! W# j/ E8 X/ o, z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. q! j# X z4 S% D; G# y. eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - t" u X9 @3 b E. x3 [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% Q$ h' p9 M4 `# E, u# t' h2 p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, n) t( J) ]; S* V" G a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 x) q& v. M$ J# @7 Y4 e" Z4 G% r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. b8 X: P# ^% l3 u5 L+ j+ q2 o0x00, 0xFF); /* configure the clock for transmitter */; h+ W5 x1 Y m3 V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) Y- A1 E' V$ V, d4 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; N1 L0 F# B* r. `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# F2 `- t5 n! p/ A6 J% q0 f! a0x00, 0xFF);& c) m# ^3 }/ J7 V
2 o% ~2 P& K- P3 M) \
/* Enable synchronization of RX and TX sections */
' ^% [4 e* A0 s% d3 h; ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 V: b" W, ^7 u$ D# X8 o3 {. |& A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); [) u. e( b! N: ^- P9 }* F1 t' d2 w' l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; @1 |9 b. n7 g: A2 c& `' N+ Q
** Set the serializers, Currently only one serializer is set as+ V" `% U' d# R7 G0 n
** transmitter and one serializer as receiver.6 f1 p$ o9 C( K6 c, |8 e! e' B
*/
7 |2 ^4 _! D T) e" YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 z' F) D ]& N% A# Q* KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 ?& c7 M- E# H+ Y0 E5 ]/ x
** Configure the McASP pins 2 j8 W) m% G: R& ~
** Input - Frame Sync, Clock and Serializer Rx3 m* d* o4 a9 [, k
** Output - Serializer Tx is connected to the input of the codec
) j, `" n! K" z7 I! ?) O% z. \*/# P) M# x [. J) Z8 q2 H6 w n) w
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: y* w; d+ a& V. c" ?0 e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ o0 t; r8 P @4 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ x0 |; q* h4 E* r
| MCASP_PIN_ACLKX a1 W! o; u. S2 y" ~3 y. y
| MCASP_PIN_AHCLKX8 |$ w2 d3 a" U) [" _- M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( c! u, P8 U6 B$ w9 D4 g+ UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ v- w4 S8 ]% J6 O% F' U, t3 w| MCASP_TX_CLKFAIL ! }# a3 Y4 G" R8 b1 J( l0 P
| MCASP_TX_SYNCERROR+ w9 n& f( `9 r7 n! M/ P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; M1 Q0 [- h" x! O| MCASP_RX_CLKFAIL, c/ b! q4 U( Q# w
| MCASP_RX_SYNCERROR 0 U5 W/ w& c: v* N! l' L; b/ o$ F
| MCASP_RX_OVERRUN);0 R# _* N; I" u0 v
} static void I2SDataTxRxActivate(void)
8 @ X' o; x7 t: e' n) Z4 n{
7 t4 p6 Q, M. l2 n# U0 t9 e) Z& Y/* Start the clocks */
$ o" A- }. `2 s1 a' u/ S7 BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 g+ f0 ]& i) C/ q: b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// w/ ~" u/ l' R& a2 n/ F! }8 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 h' `* B: F; A- U
EDMA3_TRIG_MODE_EVENT);- a0 {* P0 V' v# L# C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 z" F4 X; O- _0 ]- e `) c7 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 O# y) z7 M' s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) U. E0 u- U4 f# I+ p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 ?) y; D' r" {3 Z9 _# l! F" o' S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 Q7 L) L9 ~5 h O, VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" \0 W: v* `0 l0 [ U: uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% h1 {! z0 ~7 H, n" F0 I
} - w9 y/ J1 I" ?" Y! Z& L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
" d; {6 U3 E& q. F+ d# a |