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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 d9 g6 j6 Y# }
input mcasp_ahclkx,1 Q0 Y" G6 w3 {# N% t5 N2 ]' h
input mcasp_aclkx,, `# y* s" b5 J2 q# z& Q6 ^
input axr0,' h% ?9 p; v" l0 S% H( y' [3 ` Z
# q1 r _# B7 A* k) s9 }output mcasp_afsr,1 h, c# l2 ]" K. P
output mcasp_ahclkr,% `+ }& {& y5 ~- \
output mcasp_aclkr,
: Y% J% \ ~* k! a! [output axr1,
* J: O0 A2 h4 P assign mcasp_afsr = mcasp_afsx;
; u" S7 {3 t% R! m; u% B4 {" M# k$ Passign mcasp_aclkr = mcasp_aclkx;
3 F L5 G$ ]3 d# B+ V! l9 N) vassign mcasp_ahclkr = mcasp_ahclkx;" }4 q$ W9 ~; V& I- x* t$ O* O1 S1 m
assign axr1 = axr0; ; k- H5 e+ T: W0 J: L) ?' e+ B
$ D1 r) x" B8 J% l. ]7 F# b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " i2 F |0 L; h. R7 Y2 c
static void McASPI2SConfigure(void)
- u7 |1 E1 L+ v2 N1 u2 ^, `{2 N' z9 y) V+ t+ {% z, }" e! ]/ L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, N; W' b& f/ L/ e; I4 B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 U7 Z: m: [' J; t+ f$ YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ c) ~* G; I3 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 [9 `( D2 D" U; ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
F( J P' B+ ^1 KMCASP_RX_MODE_DMA);- c" ]8 @8 Z( V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," P7 s9 D( \* u5 m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. _0 i: B% E7 \9 S, K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % ~1 q% F. ^. s! y# B3 n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' \5 _6 y; U8 \$ @9 d+ r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% n) }) i% S1 u. r( ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- }- Q' r& D4 `# f+ @8 QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 Q* l' U( }# F# L! s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 t9 g' C; ]8 Q% G/ K; O0 C& JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 c5 d3 a$ J3 J6 Z
0x00, 0xFF); /* configure the clock for transmitter */& L9 j5 i5 ? O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: x/ n* B; y: N" `/ \" _, @5 [. }( }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 O, X- O, m+ _; p8 N$ _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' {/ V$ Z/ U% L0 i
0x00, 0xFF);! s$ B i4 ?9 G3 t9 S: @/ N
. T q' x* K' \5 Q c( t8 Q1 z/* Enable synchronization of RX and TX sections */ ( L! S* a# C7 {' \8 B, F4 M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ A! t& Y2 H F% B) Z2 H; Q/ C+ H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& E; _' a9 e- n$ u6 k/ ^6 \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' _/ Y/ p: e# m0 f' f; ~* w" \$ }6 U
** Set the serializers, Currently only one serializer is set as
9 l" Z+ Q3 c6 H( J6 \; N3 s0 m** transmitter and one serializer as receiver.
5 Z- P2 f* V" S. e*/7 u& ~& y. s) s* s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: {; C9 v9 L" p) X6 C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 e: |4 s# t! M- j
** Configure the McASP pins . p. Y* n k, C- k, v4 l& g, H0 Z
** Input - Frame Sync, Clock and Serializer Rx5 l W5 t# G( P/ L5 i
** Output - Serializer Tx is connected to the input of the codec
3 k* B6 H2 ?7 ]*/
2 G y0 {5 k% `8 m6 ]8 T. C7 S0 ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( w$ t# v1 I) Q: m5 T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! k. Z4 z v$ ^* r( G2 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( G. s* V4 n5 r( f: K0 ]4 Z5 d
| MCASP_PIN_ACLKX: v& U1 ~2 M4 B* n1 y' D% \ f
| MCASP_PIN_AHCLKX; |+ b( ]3 R; c3 e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- V* K' V5 f3 k& H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; W. O+ T! _$ X| MCASP_TX_CLKFAIL
& C( \) v5 @' m; u0 s( L- E. l| MCASP_TX_SYNCERROR% z$ ^2 S0 B2 }+ x& d5 t2 D6 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; }& N' }5 }, {, I& v
| MCASP_RX_CLKFAIL
# Z# f, M. w. x% i& q/ ?| MCASP_RX_SYNCERROR
5 l# N. i7 }% F- A| MCASP_RX_OVERRUN);
' K( F. }/ e, q" s$ @7 ^} static void I2SDataTxRxActivate(void)
% a5 x3 j/ s1 ]7 W: P- w1 r{
' d8 ^9 C( z) K. ?/* Start the clocks */3 N9 O0 G, N' B. U+ y1 {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 T) ^+ ]3 M2 s( FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( K# e' J4 K- H4 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# ^' j5 R) x3 @7 L8 ]; i; R/ h9 I0 L
EDMA3_TRIG_MODE_EVENT);5 V" `+ V& J/ |4 i! e" D' M/ q8 F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 r, m$ x' K! ]! b0 J- J9 A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; X; D" F" d7 z. BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 \9 r: @% H( n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) S* _: ]/ M, t7 c; k- \4 [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: x+ _; C) \6 |5 e* l) SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ r9 q" K# O1 R' EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 e. ~5 K2 o$ E/ e5 P J9 m} / k6 o5 @" v# ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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