|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 w& ]8 p5 m3 q) c* D1 H
input mcasp_ahclkx,
' P, U4 {& M0 u2 R4 j3 h+ u/ C" qinput mcasp_aclkx,7 S0 _3 [6 ~. u
input axr0,: l2 F0 ?/ m# S& p
) t5 D& v; R7 E) X" e+ f/ coutput mcasp_afsr,! b% P7 V& W5 H2 V' m3 c
output mcasp_ahclkr,5 x; \- o0 M- R& m6 S- i$ u( w
output mcasp_aclkr,. `* ~9 T8 v3 n6 |
output axr1,/ s Y: ]) ]3 ?* f
assign mcasp_afsr = mcasp_afsx;
. u8 }5 P1 c, f" zassign mcasp_aclkr = mcasp_aclkx;- ~7 Y, q' J1 v- Y, l
assign mcasp_ahclkr = mcasp_ahclkx;$ v7 m% H/ X# ~, ]
assign axr1 = axr0; V" z% ]) E7 Q$ K, e
- Z: E3 _8 [) D; o1 M; p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ n0 U2 Z2 s3 G
static void McASPI2SConfigure(void)2 h! B3 A" q3 t5 k* Q/ F" b
{/ F) z4 O0 I3 K; L1 I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% I# o- L; l9 y. a( T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- x. y+ u. G+ x+ KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, s& V0 i) [: z7 v) Z* [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ R4 V/ j3 f3 [& CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% w9 U; N. B! b& _4 K1 W
MCASP_RX_MODE_DMA);
/ X% j# j7 P/ X q7 EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% B' u8 v) p# ] j* c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% H; c- o% V+ B% |/ d) `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: T4 l$ Q9 \3 {8 X; y( {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 W: L; m- _+ ?$ Z' p+ @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 Q1 r% c/ K0 S3 A# sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) V/ G _* i% L2 n5 bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 N+ Z4 ^& s- q9 g3 _4 G! d' }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 n& c$ z. }; Y& b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- {) M2 _+ P# \. ` b, Q, P1 S0x00, 0xFF); /* configure the clock for transmitter */) @3 _- U0 `) l: H/ c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( q' v4 S: D8 R6 L- G* V- {5 _7 `- D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - q7 x% B7 _( Z3 l* n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! U: U3 E, i- A7 }7 X# A; ]* E
0x00, 0xFF);! Q8 h+ U& `! k. E- Y& g9 i
% M" A4 h3 Q, d0 n/* Enable synchronization of RX and TX sections */
. `1 a2 w; h/ o5 F6 g; L& I0 ^; I8 N6 WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! {: O( t4 E9 r8 w+ Y' u* }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 F* d# O5 w1 X, RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 q# }3 F: g7 Z8 f t** Set the serializers, Currently only one serializer is set as% W* a( K% a" v- e
** transmitter and one serializer as receiver.
: {: Z* t; o# f! B7 T9 G*/
2 ?0 O7 t4 v- [, ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 V# F. M$ h( j- u$ L; D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- Z* |5 T) h* K** Configure the McASP pins
# K( j/ s( s" g- @0 I6 B** Input - Frame Sync, Clock and Serializer Rx
+ E; s: @7 a' L7 P** Output - Serializer Tx is connected to the input of the codec 3 M8 G" G" n' Q0 t; u5 W1 Y
*/
' t( z6 q/ l6 l sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: z% X; O# X1 t8 q* M' n8 jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 C S; w d5 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 F2 ?: c( s; p) X| MCASP_PIN_ACLKX
% W7 c3 C7 S8 q% g| MCASP_PIN_AHCLKX# ` S% ]0 s9 p7 ^3 Z6 i2 v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, q* H) w9 z- o& P: m* R, l6 @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % I/ y: |) E: _% T( o+ z8 X
| MCASP_TX_CLKFAIL
. o1 b. Y4 }' @| MCASP_TX_SYNCERROR
4 E5 x* ?! U0 [0 y9 m! D3 A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 V0 @* D3 J$ o4 h# H| MCASP_RX_CLKFAIL4 X% e+ k$ m8 \+ |
| MCASP_RX_SYNCERROR
7 S7 g3 z; u1 r! Z9 t| MCASP_RX_OVERRUN);( s! q$ M$ c' K: P, ~9 `
} static void I2SDataTxRxActivate(void)( x' I& ~+ D7 U# t( m( T( j) b" G0 Z
{0 e: t7 Z# _3 {1 c3 s+ ?/ i+ ?
/* Start the clocks */" a$ V' g/ Y; g$ K( d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 I+ i$ O: ?; J7 iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ S3 C) P+ k- R7 A! l- a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' ]. d2 g( e5 w/ U4 YEDMA3_TRIG_MODE_EVENT);. ^3 y% @- m3 D7 q: b7 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- @- ~4 P( ^4 {. b" W' fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 v+ N3 `- w3 Z- h, w; [7 y0 ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 K5 x$ c" B I. {5 P6 yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; l, I% z( S, t8 u4 K) E/ [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; k2 p7 p2 E4 l3 w# V) [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& a: ~' G6 c3 F7 N0 RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# U0 u) u8 ?. Z2 I}
& d, S7 l0 d& c* ~: Z* x3 x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) b& f. K( u- ` |