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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 h' M. Y; i8 `2 K0 [; Tinput mcasp_ahclkx,
/ E! q' j/ Q4 c7 a' G. Einput mcasp_aclkx,
& V" W& L0 f9 z8 k2 ]6 Uinput axr0,1 R- p. J- S) l5 M! J H$ P% Q) R) S
9 m5 E9 a; n$ j1 l1 u) b, A% X( ?output mcasp_afsr,+ c* w9 a2 c5 Z3 q- J% @
output mcasp_ahclkr,
( C+ j. X: Y4 Qoutput mcasp_aclkr,
6 e a# C- u' }/ Y! z, Qoutput axr1,- M4 y' }3 r! Y$ U9 |, }) [
assign mcasp_afsr = mcasp_afsx;( p1 p% E. [, I8 L" r
assign mcasp_aclkr = mcasp_aclkx;
, d+ q/ X Q$ z( X! |' Aassign mcasp_ahclkr = mcasp_ahclkx;
% q2 h" C( Y% H* _# f! Q% o1 }assign axr1 = axr0;
, X' D/ w3 R! z1 ?/ I. n
$ N/ V2 z+ h) ]& `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ X7 f/ H! ^5 [9 B: Istatic void McASPI2SConfigure(void)
" G1 y- \, d# A$ {- z{
5 ]) o/ b! J' w3 `$ r' SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ I/ S" L: g4 P* F1 VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% w$ P0 E) g, U [. s5 H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); e8 }4 A! U+ M$ K" {# d, }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 U, T1 P6 \7 D: GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 c+ E+ N% W3 B3 lMCASP_RX_MODE_DMA);% ^* Y5 ?7 a. o+ j% n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 C( I' A6 r! E# M" B0 z; ~6 PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& A* F# c8 f4 i- l5 `1 F5 T! fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 y7 \+ ~5 R8 u) CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
S+ O: }3 i. d3 R; k, U; uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - s) z8 L" F* T! n/ t! \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 o% j% I2 ]! N) `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 D1 l4 z8 J% n+ ]% i- gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 F" f& [1 x, n t: RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; N |' G, j) I K" u5 B0x00, 0xFF); /* configure the clock for transmitter */" \, i% U7 d9 f! P( W0 W& y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* }9 {3 Y% d l, D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 m2 A+ }, S. W* s0 F) p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 C' E$ I% M7 i0 t5 f7 i# W
0x00, 0xFF);
2 W5 [# }: U, y" K1 o. ?9 f S
4 k4 s. n. g7 \" ?, Y# h2 [/* Enable synchronization of RX and TX sections */
$ P. E* I8 U) o" c0 Z, dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# Z3 r r% A" SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& A7 D% @* \+ D. i0 n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' W# L; a* y! O1 F/ @** Set the serializers, Currently only one serializer is set as
1 h, Q8 i! s" |9 r, L6 @** transmitter and one serializer as receiver.
- T) a0 E' T( o) K*/$ b7 x) j) x3 y: J2 \! e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 U3 l5 c( k: ]5 o6 Q% P- m! R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 {7 w5 M' H! g+ w** Configure the McASP pins
+ i8 H; L1 f# O5 v D! u9 r4 q** Input - Frame Sync, Clock and Serializer Rx
9 x: s F! G; h0 I* O** Output - Serializer Tx is connected to the input of the codec
. W1 O: \3 I9 w% \" D2 V*/8 R% I% L8 o& ?" V0 r: @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: E5 G2 Q, E( p+ k/ E8 n1 C! j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) ~# w& t4 x! q% I8 T' \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
w+ A; {( {' v9 l; J0 N0 W6 O1 g| MCASP_PIN_ACLKX0 L! w1 o; R; M. e% v9 s# `" Q
| MCASP_PIN_AHCLKX
' R2 K8 o& \- Q. k, {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; v' j5 [- N4 P- \$ T) }8 d' ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & L: T! o) w0 [% h2 k
| MCASP_TX_CLKFAIL
6 c" _, {3 o. r* S$ g3 J$ s| MCASP_TX_SYNCERROR
, Y8 K6 X& C" p( a2 a) R7 _1 L6 ^6 O5 G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 t: K6 K+ t. R" z7 @
| MCASP_RX_CLKFAIL
" t5 o, H' Z6 D' j! X6 O| MCASP_RX_SYNCERROR r, v/ |/ w I* X& w
| MCASP_RX_OVERRUN);) [+ x4 | r5 j1 f" R0 A
} static void I2SDataTxRxActivate(void)
* d- r e* N$ M, k0 s{
# {& J' Z+ J$ U8 o! f/* Start the clocks */3 o B& R+ h- U* q$ g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 {; g, u# A) @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 D1 s$ _. J6 A, k* t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! B3 C3 l* h4 N7 _EDMA3_TRIG_MODE_EVENT);6 j; w n4 @, B( M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , t, d" Q) w7 u6 y4 M1 Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 `) j) s# o( q; N# A( G5 G0 uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: Y9 K! f' d. l" e$ L& k: h) y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 F7 r e" s0 V# f+ S i2 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ B, \( c- M( P; p& ]2 O! iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- O, N: P6 B# u" A6 y1 U$ tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' k3 F0 ~+ l _- o}
) |- D" S3 ^% i0 j U/ {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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