|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 S ]( g! Y8 _1 A$ O9 ginput mcasp_ahclkx,
( D3 E- I! M) |* @4 ?, n( A: S) F2 M; |input mcasp_aclkx,
6 N. ~2 G; Q* r: n7 ~: m1 \input axr0,
' w# L r8 p, y }( G3 G( ]6 S7 ?3 n6 y
output mcasp_afsr,
% x1 O# C# a# ` w6 S' d/ W% a5 Houtput mcasp_ahclkr,* ]5 z: F6 R6 _! s
output mcasp_aclkr,
) p! {" z. ?4 K3 Y& loutput axr1,
7 @$ H) c+ y* y3 c assign mcasp_afsr = mcasp_afsx;% \0 b$ R0 [- _
assign mcasp_aclkr = mcasp_aclkx;
% K% L) w+ s9 f$ W9 xassign mcasp_ahclkr = mcasp_ahclkx;
0 [: U- F5 h8 M% Tassign axr1 = axr0;
; t+ g# w* g$ J2 k$ v. x$ u% R3 a) H( L7 p L) M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ j$ C2 a' N4 {( |static void McASPI2SConfigure(void)
+ C# W. t5 U1 @& c# S, j{
! J; A* o5 \. H0 J; W& @McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 w4 q$ x* W, b7 ~ O3 o, G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 l2 J d2 z0 p0 ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! s. O0 a. \4 B' z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( u: a0 ~4 q' v9 S' MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; n n* c3 [% f! n$ WMCASP_RX_MODE_DMA);; Q( A, E) }: E3 C$ u. K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- V' Z0 _! Z2 u- k& YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, I0 v9 ]- i* r! K( b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 Z: _* m. ^0 x NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 b9 [( ~% k( e; EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * |- [# n8 J/ |) `5 J4 U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( P- i/ z& @0 N {9 J( I f% U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
d; x, D9 a, F; v+ ]- _, oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( ]6 g( C7 Z; e. [6 V+ O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 N, A4 K+ L% a$ q
0x00, 0xFF); /* configure the clock for transmitter */4 u4 i. ]+ k' p; N/ e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 D$ H% j- x- {1 c' }2 Q4 Z4 {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. k' l! Z: e% b; b6 S/ U8 Q- n; }/ gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 v, _% x# }: Z/ }2 C
0x00, 0xFF);
# b/ ?! l# p4 y" Q. x4 r: j; O) |1 F* W, l9 F
/* Enable synchronization of RX and TX sections */
- C/ x9 `3 [# r1 M6 P u, KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 f- g, c- K/ ]; ? K o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 Y/ x- ?2 j8 f% x4 [2 x" Q7 IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& L) B* j! s5 d) J* S3 E1 G* \
** Set the serializers, Currently only one serializer is set as" ~# j# N; w: j# p* V+ H
** transmitter and one serializer as receiver.! b/ l; }" E2 [) @! y3 W
*/
) e" M% o; R+ X& L, m+ ]8 e# vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 }. a. p- o0 m2 @; j7 A/ HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: B5 N( W' {2 @( ?0 ^* f
** Configure the McASP pins
0 U9 f q1 V! U1 [: q5 v** Input - Frame Sync, Clock and Serializer Rx
6 S4 b) e! r" T% E7 A+ r" U** Output - Serializer Tx is connected to the input of the codec ! J0 G1 H7 t$ K" q$ X- j4 @& p
*/
W! K1 l7 R" u8 ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ | v8 G" p- G' o' ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ F( ^& d" m" _; r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 H+ e1 x; H5 B- C* B' ^
| MCASP_PIN_ACLKX7 l, E/ ?9 i6 f6 S1 A; |, O
| MCASP_PIN_AHCLKX3 M, V* f7 u y! q- A( Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 H" N& t$ P+ Q0 k& j( d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 L8 b5 G4 D) m0 i| MCASP_TX_CLKFAIL , e' z7 z7 D, N4 F( g3 x( r1 u& Q
| MCASP_TX_SYNCERROR3 [) }! H7 W) j* I% S" P" S4 U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 P' z, H- ?8 ^. h( Q| MCASP_RX_CLKFAIL Y+ V$ p( K# V1 |" ~3 d% i
| MCASP_RX_SYNCERROR $ R8 c) D, V1 \9 \1 D3 m1 f
| MCASP_RX_OVERRUN); K8 M/ [ \. P5 J5 x% b
} static void I2SDataTxRxActivate(void)
) L0 E& x4 j5 w: V- b/ }{; f; a! ]/ Q* o; M+ {
/* Start the clocks */! G$ c6 V' P7 X* I, I q3 ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' c& O$ l: `& `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) ~" m# {9 V: JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: Q" Y/ d" ]" ~) }: }EDMA3_TRIG_MODE_EVENT);
5 f2 }# o' a* `7 \& BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& O/ S9 P: |1 r# F2 o6 @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% o! Q" D! i' R4 Q- n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) [5 @, a* c+ f H5 \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 n: F7 R0 B" T; w B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 y& W: j5 r$ w! M8 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 y V% q" ?3 M6 O3 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% Y7 n$ z& z3 J7 t4 I$ c( J* B! {9 @6 {! ~
}
0 f" _/ {+ Q) @; S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- w6 o+ o' N5 `- r |