MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
: M" x9 A. t1 \7 linput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
! k6 {; }, S& o- |. n" Q- M5 e7 K% @: F$ Z
* G7 _' ]; W3 ]2 houtput mcasp_afsr,
5 i; L' `8 c# k  B1 t/ g8 Boutput mcasp_ahclkr,
output mcasp_aclkr,
+ }( E$ f4 |2 M) w7 B  z: ~7 e$ Soutput axr1,
+ ^3 }3 d6 C. Q& T% w: V/ y

assign mcasp_afsr = mcasp_afsx;
' ?/ c( u, w. d" {% X2 |assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

6 U  `: i; p4 r+ ?! D1 E3 r

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 I* t& _6 b. kMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
, Z1 j4 ]9 @: d  m5 h& V9 SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ u4 _  g" y. t. F, X$ s8 r* E  P  MMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 ~/ N& T, }' x  DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 c1 W7 R! a- ?; fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" S) u  G# `8 E" GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ y. a/ t& j6 pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ f" k: m- c5 i. a" e4 q! d0x00, 0xFF);

/* configure the clock for transmitter */
. V- B' B! k+ _/ k& L: f- @0 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 L8 g- Y2 z( b0 AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) w5 T- D- ]5 S# qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

' @) O% z- r, {" S- N/ _) K1 P; S0 D/* Enable synchronization of RX and TX sections */
$ E, h5 |% y# t0 _6 G  u0 AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
# C( e6 |! b; l7 ~0 c; fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
9 L" V- h( r; Z5 |$ x** Set the serializers, Currently only one serializer is set as
/ A$ ]9 Q, }; a; H, i** transmitter and one serializer as receiver.
*/
8 s+ \) {4 T5 h- SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 x: R) M0 c# x2 N% D5 TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
  g& N( W0 M* x2 ]1 P- K3 a** Configure the McASP pins
; @4 z" j7 h! h** Input - Frame Sync, Clock and Serializer Rx
  r0 P; A+ b0 v9 S** Output - Serializer Tx is connected to the input of the codec
5 _- C+ k9 C, o*/
. {1 R; \4 r9 [3 T8 ^' k1 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# [/ ]4 W, I  ?9 F6 @$ VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, B  u3 M7 m/ W% f, _' ]! vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
0 _- _/ k# g, Z6 E9 I$ A8 _| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
. l* q% f: s# A$ N( X4 Q$ wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 i- Y/ u6 [/ X- x, u* c- W% I8 O| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. P6 @7 _/ o/ F8 \- ?. T| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
3 ?* {( }, C1 R3 l* i| MCASP_RX_OVERRUN);
2 Z2 B1 d- q; b# C5 K}

static void I2SDataTxRxActivate(void)
8 ^0 U9 P$ ~4 Y, |; x8 y{
2 W! l+ X2 w1 O! i/ K/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ K5 t; f3 M7 S* FEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 K9 t7 q- m0 i: C% |8 M3 sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
0 V  l8 B1 V& g# I8 j) Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

- n6 [3 w3 p) f9 _+ C

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.