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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 A+ a% R( |$ `2 {) @6 _1 E! e( L9 jinput mcasp_ahclkx,. i8 t ~" i, ]! q7 ]$ J
input mcasp_aclkx,$ R& F+ W; B: Y" x
input axr0,! K y0 i. u; Z: C9 Y
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output mcasp_afsr,
/ u/ l% a* s7 |' G coutput mcasp_ahclkr,
; q" z" P/ v2 t0 Noutput mcasp_aclkr,
$ J7 f! m0 b- @! foutput axr1,
" ^' b- S( T4 Y" c4 {) x# ^ assign mcasp_afsr = mcasp_afsx;; ^$ _1 }3 o7 n9 {0 o+ B1 p
assign mcasp_aclkr = mcasp_aclkx;5 T7 H& S6 T7 L5 q2 H6 ^
assign mcasp_ahclkr = mcasp_ahclkx;
; C% g; F0 G! D3 m9 T, eassign axr1 = axr0; 5 P, i# B( Z* Y
, y% i" V* l% R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( F! H; x. f3 W' X
static void McASPI2SConfigure(void); |0 v$ W. C4 A$ m
{3 k" N; f5 K! _- e' O1 @- t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, C$ H& S/ p: b, hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 `/ [2 V9 E+ x) ?7 N; [- M# G" V5 \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; U8 W6 q% S! p8 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 S3 v) V; U! P5 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* Y' k& Z+ y) i8 z6 SMCASP_RX_MODE_DMA);
. j7 C4 S0 i1 s5 U+ NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 U# B! c+ X% e# A2 ?7 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 m; ` `. n- q) W+ b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 n4 N* D0 q" Q# c9 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( L5 t3 ^7 w7 n9 Q, D2 E# ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. P$ I {' E, Q8 Z, W U2 ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& G Y8 T9 S L0 TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ |) i/ y% ?' Z, PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 ]8 c7 B& ~; s3 }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' S4 U& h+ B* H
0x00, 0xFF); /* configure the clock for transmitter */+ L) ^& Q( y7 h6 I/ J$ r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. C) H) O/ t4 k+ l6 c4 G. g [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 e% ~! H$ w- c) p2 v, F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 W! X$ i# B- V& j/ A# L0x00, 0xFF);3 k9 O5 p, O- q6 R/ l; r% A
5 L! }8 v% J6 S( X
/* Enable synchronization of RX and TX sections */
' b7 {% c+ [# d: K* zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) Q5 y" m+ }1 Q# e3 y7 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 U: J3 t2 n: F C5 D/ L0 N9 e& n$ OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# X% D7 L4 o7 }6 M
** Set the serializers, Currently only one serializer is set as, B3 D; B8 U+ z y& m
** transmitter and one serializer as receiver.; a, g& K( G. O& s
*/9 }& H) T' S, H. q" T- c3 i0 T% f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: @ U2 x/ v, e6 o# WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 D' d- M- g6 F* ~
** Configure the McASP pins
% p2 l/ [' b( S1 V" y; i' ]** Input - Frame Sync, Clock and Serializer Rx- Y9 @/ j* N2 N1 u: n
** Output - Serializer Tx is connected to the input of the codec * E g# Q7 y0 Z8 a9 |
*/* |7 q* {8 n' }3 |% y" A' I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( V1 L' T1 W. J; |* z1 Y2 ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 b. m+ G8 o I4 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! y, G3 O( k0 W6 u3 }9 r5 _; o
| MCASP_PIN_ACLKX$ g C; H/ K6 n
| MCASP_PIN_AHCLKX* R, E- R$ I. U8 ^, u- W, }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( A* H9 U4 L7 e) {' N! C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - ?* H! a2 ^3 ~ t* l5 N( h% O; T
| MCASP_TX_CLKFAIL
; Q! _& D& |! q# M. V& h. \| MCASP_TX_SYNCERROR
$ e0 I; q: Y; a: H9 p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 I( l- L# C7 D* W+ n
| MCASP_RX_CLKFAIL
, Q+ j' L+ @- c1 _7 E: D| MCASP_RX_SYNCERROR
1 w) @! v7 o J" B. E$ N3 V| MCASP_RX_OVERRUN);) d7 T1 z! I: X( \
} static void I2SDataTxRxActivate(void)& A% u" D' J! ?
{
$ V$ o9 n% M, s- E5 J& j+ {0 ]/* Start the clocks */1 Y! M1 A E! K, y4 r7 ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& h. ], c, c0 e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 D, ]2 P+ c: Y, C9 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 k0 F! q. m( sEDMA3_TRIG_MODE_EVENT);
- w3 u; y9 S/ U9 S G& F0 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / s3 ^. n" b- d: B1 N- j5 b" [9 F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" u/ p; J6 V/ D- ~3 J. l) a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* w% E$ i3 K" K# q9 l: P: E8 e3 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 z6 w' b2 I2 S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 n2 _* ^+ R$ x; z$ C' [$ v' RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 ^' V% w( s3 _- j+ V' Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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