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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- B/ _2 Y- p3 i- j
input mcasp_ahclkx,5 Y! b. n, {0 B0 I7 t9 R
input mcasp_aclkx,+ i( y+ e0 f3 _/ O" t
input axr0,
; [, V- `7 ` h$ k% b" x! L- V6 Z1 ~5 B0 E, \- p; d& `" Y
output mcasp_afsr,
2 r3 W( `3 F/ B2 s4 @output mcasp_ahclkr," ~0 |' f- m: f6 F; ?5 T2 `- B
output mcasp_aclkr,, Z4 }6 Y+ }% Z% H
output axr1,. ?# L# M% ]9 F7 W
assign mcasp_afsr = mcasp_afsx;
' |$ T# v% ~3 H) l) e" iassign mcasp_aclkr = mcasp_aclkx;) T1 a& U+ f t2 s& V6 P
assign mcasp_ahclkr = mcasp_ahclkx;
! H) b" P8 P1 j' Q; R z' W. L; W; F/ Cassign axr1 = axr0;
! h/ P4 `# O' T/ V) r1 o' T/ }& N6 T6 O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 @+ r, s( {1 y1 h+ r7 ^+ cstatic void McASPI2SConfigure(void)9 L5 ]. i# I% L3 y+ a! T2 B
{
- Q1 F* c8 r5 i9 D: s; `% m. HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! p# ?+ _) Q: [: Q' j% n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% V ~# `+ G6 y- a! g! S4 U# j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 c/ Q% p5 P; @' m1 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 d: V* p6 W; ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% C6 X) w9 r4 P3 M2 V
MCASP_RX_MODE_DMA);
6 S. b5 F U; I& y$ d1 v- TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, l6 l7 m% O$ ^* r: \1 [% _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' H1 y4 g |& H# e w& X+ f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 C. l9 [' F1 A2 X! Z( d6 S5 x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' E$ b! E6 y4 R, WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* B; ]) q! k/ \9 h, |. mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' h5 L# X! V9 H. D: g' a3 J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# w8 s2 y+ n& _5 F* `, X* H5 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& A0 @1 s4 r& h5 TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: j$ V& q. {5 p4 T, n0 k3 A
0x00, 0xFF); /* configure the clock for transmitter */2 G* P4 E# c' l# f# Q* ~, q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 O( f- h$ u0 i+ u0 eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' s6 H- T4 b" K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* |. R8 Z. M, @1 ^4 o n
0x00, 0xFF);
0 {. J- } R* I, z# B
' X* U0 i& f! v0 I' ]% f/* Enable synchronization of RX and TX sections */
/ z8 z& ~! `8 U% A6 K& t# n/ IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 R v( h3 ~& B2 {3 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
D3 O+ O: L5 [! tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& ]7 `7 J) I7 S9 J) T( ]6 E/ T
** Set the serializers, Currently only one serializer is set as- I, H9 r# }. ]. v1 ?
** transmitter and one serializer as receiver.( k1 Z( {! o* P
*/: c1 ~8 [! E9 a7 _4 C) \9 n3 ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 K; a4 N& I* t1 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 C: \' A; ^8 a3 `/ L/ [) l" T3 j0 v
** Configure the McASP pins
, k& B8 ]* I1 t# J* k** Input - Frame Sync, Clock and Serializer Rx
, u( g; O% n! G H- r5 ]** Output - Serializer Tx is connected to the input of the codec
& R0 k# l6 W. O. H1 v*/
7 H. E6 M4 y3 a+ Y+ vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) h5 I" d" Y3 k+ K4 y& [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 X1 ~7 W( c% y7 j& k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% w' H9 n' q, e1 S| MCASP_PIN_ACLKX6 j' C" I! |0 I# g9 s: ^, L6 H
| MCASP_PIN_AHCLKX4 G; k+ b% [8 Q! ~) b5 P3 D9 w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ O; `; o3 l5 pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / ]' d; f, z/ }7 E& c* ~# K
| MCASP_TX_CLKFAIL 8 V: z: M: {& x7 [/ }
| MCASP_TX_SYNCERROR+ g6 q4 c* `* I% g- `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& k. d; c: [& V0 p| MCASP_RX_CLKFAIL
1 q- O3 c$ n y| MCASP_RX_SYNCERROR 6 g p4 H- [/ V
| MCASP_RX_OVERRUN);( b' \; H L! [" w% j6 m* w
} static void I2SDataTxRxActivate(void)+ Y. S; N( f8 \7 W: m: r) q2 P
{) n9 i# F6 a5 \/ ~8 V4 \/ {( c
/* Start the clocks */
) c7 m- x/ N9 X3 b2 P# L# OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, B h. ]: a- Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. } n. l, a' T$ b6 j( NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* h% M9 Z" s3 J- @+ N, {
EDMA3_TRIG_MODE_EVENT);2 N* X/ i8 H2 p2 F! N$ I% X" K2 E; a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + H0 e0 e2 Y7 f/ H8 |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- Z, q" n6 Z5 h" CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" B9 c: Y7 O. u3 n. rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 z$ {. G4 A8 p @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! R- o& ^5 M; K' l0 [! nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. k* s* C' [+ O6 ?8 ~: f; o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( e# [! Q; E" q: c} : E3 ~% {- O) I! S$ m% _. h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / r" l1 n7 M6 n: a, V
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