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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* W, Y6 H3 T9 }( \# Ginput mcasp_ahclkx,: \& R# C: }9 K& q3 [( ] C* `) m5 j! _
input mcasp_aclkx,) j$ a5 @$ C( ~, v% g( g; r
input axr0,( A) x! p/ p& H( ^
. V! l* S2 X7 X6 m! |- K n% Loutput mcasp_afsr,
6 K1 @. b/ ^& ~4 |2 [5 ? P$ }output mcasp_ahclkr, R/ U! E) j2 Y: X7 L
output mcasp_aclkr,
) {9 n2 p7 c" `9 y- M) g# Ioutput axr1,' ?! I& L7 z' T2 x3 J( s
assign mcasp_afsr = mcasp_afsx;
! t: y% ?/ S& Fassign mcasp_aclkr = mcasp_aclkx;: ?# N- n9 n4 o4 E7 W% X+ W4 x3 F, l5 u
assign mcasp_ahclkr = mcasp_ahclkx;. p/ `+ E. m+ ^$ \ R$ t
assign axr1 = axr0; / }% |9 K) z" Z1 `1 P; { Q
' D! A. @" G; Q: K. Y; } e2 B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * D7 Y, ~( ]" E* c& P' _# s
static void McASPI2SConfigure(void)7 r" F" ~7 {0 L+ r G% C$ T
{
4 t/ L; T+ F, z5 f: f; Z- pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 j* O- w( i4 ~: z! s5 _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. c0 @4 t, H7 I) nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 k4 [/ e7 v/ N3 V. v: n% {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% o" P! R7 Q& l6 G$ X: Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ G( z/ } {6 J$ c* [ Q. W4 v3 t
MCASP_RX_MODE_DMA);
! ~4 M7 W S3 E6 F/ N' X9 J4 ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 k; j0 ^3 t8 [9 E; f* D, Z. jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 X8 ^6 w9 q0 |. E/ o5 S3 g4 Z8 [ q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 u( P* l* {4 i+ S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 f& p2 U: _7 A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( e% U! f! K6 A& h% M" \: {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. P' T! V% _" k( W$ AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% k7 [9 R6 C0 P3 Z6 K0 {, oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 [. ]' n" w( `- J. I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) e O+ ?3 X0 \% U
0x00, 0xFF); /* configure the clock for transmitter */
$ ^* O4 Y7 U# g! X, e' Y" ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; y5 E7 L: j5 K0 o g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & ? M$ a8 `- U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ r7 Z& @3 V2 W: @& q' I
0x00, 0xFF);
+ z+ L, ?+ B. ^, L L0 U* D7 w! F
5 _) h" R/ w' P" W: \ v, M/* Enable synchronization of RX and TX sections */
0 I4 l% i9 {; V* u) C* qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* L1 R. G" Q: ?6 j2 m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ z& Z; ?; A& E* K5 H( y MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! G7 c6 O6 X/ }% G7 ?0 w** Set the serializers, Currently only one serializer is set as
8 a/ k! Z$ X [$ e8 @** transmitter and one serializer as receiver.
7 K& C9 G+ z2 ^) z*/
" ]% ]7 M) k+ U# X' x, MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
p" }( k" s$ T( e6 \& v; y$ i; o/ fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 ], U5 Y1 q4 i** Configure the McASP pins $ D" S5 {5 w" N% e0 |& o; t$ k; s
** Input - Frame Sync, Clock and Serializer Rx
' a' w0 f6 B+ `! m& j** Output - Serializer Tx is connected to the input of the codec , P0 t7 p& `' R8 x' P% f4 ~+ m5 _
*/
+ w% ]' I# b5 GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 L9 p @7 W1 EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 ~9 @$ y% w% |$ e* @9 R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* K! S" V% i- D- q8 F| MCASP_PIN_ACLKX7 M F5 [' f/ k- s, i) c/ Y D5 U$ B
| MCASP_PIN_AHCLKX
9 K& E9 [9 j2 I* _8 ]2 n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ ^9 W$ r: e2 v' N1 U. r( x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) {0 V0 X' a0 S9 d% V# }
| MCASP_TX_CLKFAIL ( X$ g3 T; m7 J4 }* r$ A
| MCASP_TX_SYNCERROR/ _% d9 p0 ^% f9 g+ a1 [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- L: ~& H4 W" q4 S| MCASP_RX_CLKFAIL
+ S/ v7 x- U* F) y8 t| MCASP_RX_SYNCERROR 7 D V3 L5 B7 L
| MCASP_RX_OVERRUN);- ~( b8 x3 S1 m. Z
} static void I2SDataTxRxActivate(void)
- r* W8 j' J' k( E" K% h{
: D/ c P! `, [/* Start the clocks */
3 j" \1 M3 {/ c l) v. O6 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- d" T2 D4 r( L4 ~8 ~* zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 N5 @- P$ {4 ?5 K4 x: aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 {' S& p6 X3 ^EDMA3_TRIG_MODE_EVENT);' l U$ x9 z j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " ]. j5 T& d. |3 ?2 R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" |" k1 E5 H7 \- E. t% ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
j) k i% n; uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( ~+ m0 p" J4 P8 s3 ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" a2 M& |1 `3 K$ N' sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* i# t3 E, P7 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( A: _* }2 U6 M
} , M D) Z/ U/ z; r% @1 O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 Z8 K) g3 f; T! F
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