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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- q" }6 j5 p0 [
input mcasp_ahclkx, B. D3 D; [3 x
input mcasp_aclkx," _( f' I; q' l# c4 X
input axr0,
" F1 i5 U& G7 G/ A' R
3 O) A, r- }; houtput mcasp_afsr,
0 q. D. I; P. ooutput mcasp_ahclkr,
/ H w5 H+ } w: }- Uoutput mcasp_aclkr,
' H1 D; E3 c8 Y+ [output axr1,% G4 B: J+ G4 \8 ~0 e
assign mcasp_afsr = mcasp_afsx;
: p- ^! V- W& l: u s8 vassign mcasp_aclkr = mcasp_aclkx;; I/ n: M/ B9 I1 P1 H1 X
assign mcasp_ahclkr = mcasp_ahclkx;
( y. Z9 I* n+ k+ a5 hassign axr1 = axr0; . p* _" r" W) }8 ^2 X8 t
7 `' m5 k* o! Z* P; b) h8 P8 Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / N6 Y: i I2 N2 h4 B* [+ P* `, O
static void McASPI2SConfigure(void)( i, |, i% {1 ^1 a5 {8 W
{8 P) ~) |; _1 O3 ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# g2 l0 ^. ^! ?3 N; S% DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; |' P0 S$ |/ m I" v$ g0 K/ ]) j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 p ^& i3 j2 j6 l: S1 UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ S+ M4 A3 ^, x; K; o2 ?7 }+ lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 w' |1 Q: g0 i: w+ qMCASP_RX_MODE_DMA);$ X9 h' p9 t# b" n! J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ e0 X' m% J6 ~, y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 ]3 w& t: @, R" Q, O4 a- Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) [5 I6 T t' _# {' Z% T" q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 }* a2 Q" O+ _1 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( A0 G6 D" c! C+ _$ iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* l3 ^4 \ R9 }) b' a: ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 L! A0 z G5 y, Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: U9 O3 a7 x+ `, l4 G( P gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# d! q6 y! D' G1 J6 ~' d0x00, 0xFF); /* configure the clock for transmitter */2 q a8 O9 ?0 ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 Y* B( h5 t9 S$ g' P' PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; `' l0 g- C4 [" g. c5 `% aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; t/ r3 b) f4 x: C* H0x00, 0xFF);: U0 i* R" d/ h8 W
/ j2 N: U3 O( o/* Enable synchronization of RX and TX sections */ ' n/ M3 u9 ^% {1 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ Y/ H' Z7 T0 g3 @' b" J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. w6 W8 |! @ ~ a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 W$ r, j0 d" @6 \: C0 z$ C** Set the serializers, Currently only one serializer is set as
3 Z5 f" c$ G( n** transmitter and one serializer as receiver.6 a4 E+ a% o+ y5 g# q2 t
*/
8 h6 A' c4 P) F$ |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 u$ n7 N% E1 T6 t" N+ j% }- bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 v* N, Z% L& {6 h
** Configure the McASP pins
7 w+ @/ K( R1 Y: a% Z; U- {6 _0 W** Input - Frame Sync, Clock and Serializer Rx
6 I( K- x! Q$ A5 `( b. w( W** Output - Serializer Tx is connected to the input of the codec 3 x! d& T9 ^6 }1 [$ ?6 p
*/& a: {: z ?" `- N/ R2 n7 o! M# r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 p+ W5 b4 ^* P! g" N/ u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: E7 E& Q* I# |$ l) @5 g5 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 W! {9 u2 \' ~% H4 g- Y% l# Z| MCASP_PIN_ACLKX" `4 @( S0 a0 c2 T0 \4 g
| MCASP_PIN_AHCLKX
, l" H; a% }; | J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 @2 q$ E2 Q: G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 S8 t& ]/ n$ g0 X' J( N
| MCASP_TX_CLKFAIL 0 b, ^* j9 s' z: K2 l, r2 X/ w- I1 J
| MCASP_TX_SYNCERROR
! I4 C" e ]( L- F- q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 T3 L' K5 Y5 Z; k, ?
| MCASP_RX_CLKFAIL% I/ U; \8 p6 }! D9 s
| MCASP_RX_SYNCERROR
2 Y7 v2 F0 j% D d R7 [5 a5 u| MCASP_RX_OVERRUN);
+ Y! |) l' A% F, Y7 m5 S) R* s( f1 R} static void I2SDataTxRxActivate(void)
, m# |" o5 c. s0 q0 A; S{ q, e) T; [2 E* e7 D5 y
/* Start the clocks */1 R/ ?8 _2 R" W2 Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. n8 \8 M6 B3 C4 e6 J6 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) t$ ?6 ~! j. N7 N" r. q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 W4 Q* ~0 |. ^# A* I
EDMA3_TRIG_MODE_EVENT);, \* d- o6 `6 g% T" w! _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 M* {! {8 ]) F% ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* F5 ^3 H, G4 `; c( _& Q, p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( `/ e; g3 o6 s5 j% r* {( Q6 kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" [! a0 C( \6 I# ^6 u3 q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 s/ ?9 @/ y- e. S6 X; m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 o) w! r. u. p, p$ s2 N) {' c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! M/ f! f/ {: `- a4 ~$ T/ S9 J
} 6 F" Z: B: q+ _1 Q# v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 D0 ~6 B) _/ i$ F
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