|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" w7 ]# v% P8 E. D/ `7 A0 O: }: iinput mcasp_ahclkx,
2 f) H# ]/ O6 { J/ W- Rinput mcasp_aclkx,
: b ~$ n; s, d; Pinput axr0,0 h F+ a9 I; a( N
$ S- l9 c4 ?/ z! G L0 Ioutput mcasp_afsr,1 |* Z$ U9 D/ f; \$ ?: N
output mcasp_ahclkr,- G8 n* R B! O4 r7 P8 } e
output mcasp_aclkr,' e: P; g6 H: w# p4 b
output axr1,9 s6 K( r n( D* a0 }& g
assign mcasp_afsr = mcasp_afsx;
+ i$ K: e. x, n5 ]4 {3 T3 L9 C, oassign mcasp_aclkr = mcasp_aclkx;, j i3 Q* b* W- X( @6 e
assign mcasp_ahclkr = mcasp_ahclkx;) w3 l: R" s X; Z7 J9 d. I2 ~
assign axr1 = axr0;
6 z& Z/ M% S. ?" l8 U1 I# ]& l9 {, Q
- T+ [* a# r2 i3 w+ u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* f {& e. @! g+ ?5 ~static void McASPI2SConfigure(void)
+ T1 ]5 _" |; x" f' q1 f4 F{5 L" |0 @9 i* \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, V# X) l. G3 k9 V, j* J: Z% @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ Q: I1 w. G# L4 \1 u: AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: `4 [4 Q( i1 }* b$ [8 r4 U% nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 K5 i0 Y |' {- M: ^% _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! k" u) Y- T+ m2 G d0 a S
MCASP_RX_MODE_DMA);! P" i! `3 s) F5 V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 c% n+ \$ R; Z- s( q. aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 i! ^# J1 X2 l4 S, D; @. x" A8 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' U( _4 P7 B! B, G/ V# ]# {2 w- Q3 m7 r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! r4 d8 N" A7 s G: L9 E' m: \! bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " F/ m) q4 v, Q& k/ M- c4 O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! T5 O) u; Z. ~! H3 uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 w2 Q" v/ l- A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% B1 N4 p" a7 P8 b0 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 H2 _& c8 F6 s2 l6 z* l+ \0x00, 0xFF); /* configure the clock for transmitter */
Y# `/ n+ R( g2 j* l/ bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! {* \. ?. w @( ~- O& I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * b+ l! W0 l a v" x1 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* s0 {* q3 W" V' g
0x00, 0xFF);, e, T, k! u. z
N: @) d" h( N5 u# f/* Enable synchronization of RX and TX sections */
( r3 x3 @3 H( A2 ?1 a$ k/ WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! E7 l$ ~+ L2 zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 d5 M: @ ~5 sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 v& W3 C/ B% m** Set the serializers, Currently only one serializer is set as
$ C& b- m9 A. ^* v8 r' T4 j** transmitter and one serializer as receiver.
; E9 U' I/ ?' Q1 i0 P$ U5 i0 i*/
' }7 B& Y5 N( i7 M4 G% z. lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, \$ c- y5 u7 [, G% D* R4 d B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 Y+ d3 \6 R$ g' L9 p** Configure the McASP pins ! c6 z$ G, y; S& E; H9 [
** Input - Frame Sync, Clock and Serializer Rx
" H T- j6 [2 G" |% T** Output - Serializer Tx is connected to the input of the codec
7 L3 r2 P' j6 L* ]*/
; R$ p; ]. ]/ g/ C, |3 w3 OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" f g: I5 r$ Z5 ?$ J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- a) y8 W1 g/ H0 k( f9 l) u f1 x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, n3 e* }0 i6 A ~7 a% b; K# R
| MCASP_PIN_ACLKX
( i8 B$ n( W. G/ r* f" [3 Z' L| MCASP_PIN_AHCLKX9 M) n+ L P- T1 N- ^! [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// |$ Y3 @2 h' f8 a" k6 _ X6 J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 \0 e1 J8 D, d i. D1 l8 ~| MCASP_TX_CLKFAIL
2 s9 _3 @: ?6 H+ W; B- ?/ }! Q, Y% Q. N| MCASP_TX_SYNCERROR
5 F1 G- n2 z9 C/ ]) r/ {; T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 {8 F3 y- d4 W+ d- G
| MCASP_RX_CLKFAIL) J; |) A! X9 H( h
| MCASP_RX_SYNCERROR
9 A% T% q7 i/ L# r| MCASP_RX_OVERRUN);# s% I2 u7 R/ `0 ?( I
} static void I2SDataTxRxActivate(void)
% c6 @- W; ~) n; j3 K% f7 s, |{
9 b' N& S, V2 U0 y. z/* Start the clocks */
; \" ? ]5 q1 e9 C KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" q0 p6 T5 q* ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, U5 f6 N. Q, j+ }! Q% S2 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; T' e) ?$ B$ E/ B( H# q
EDMA3_TRIG_MODE_EVENT);1 @6 t6 [ q( Z9 a6 t& M: C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : K& S: y4 t! Z1 ?, v& J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. a" M5 u! _: W6 m& n P$ _, OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 f9 J. I. j# O0 vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& m0 q, S+ N! Z7 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% }. }/ q" i5 o% I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: n* q) L" M5 D$ M oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ q' ?8 C2 v3 X}
, }* J6 L& r3 Q* `$ T7 ]& h1 Q+ ^& k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
$ E9 \7 p) j, T+ }) b3 ^ |