|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. y5 o H! V' C8 O/ }. i
input mcasp_ahclkx, j* J5 {* }0 i$ L
input mcasp_aclkx,
: n# L8 R* x: U! X8 t% Q! k0 Finput axr0,
0 W3 P% v. D0 J5 A) A6 e" i# w2 c# Q5 R7 v% F6 Q: J
output mcasp_afsr,
$ s/ ?8 [( E4 X$ R1 koutput mcasp_ahclkr,
4 {4 a/ R, `* a8 woutput mcasp_aclkr,8 g' n: y; g, V2 d4 L! U: C
output axr1,
( H7 Y+ _( j: s( r- ?0 ? assign mcasp_afsr = mcasp_afsx;. |+ K; K7 Y- l% Y D' R
assign mcasp_aclkr = mcasp_aclkx;' C! K7 s6 ~( M% H* D6 ^
assign mcasp_ahclkr = mcasp_ahclkx;
; E! `1 v5 [7 }# V- H! C4 B* aassign axr1 = axr0;
" I4 ?# W2 f; M* _, T; y( [& D$ I0 {! V9 [( j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 }( D0 p. f7 p9 C& H9 ^0 V5 Q3 wstatic void McASPI2SConfigure(void)5 u) Q) e! v- @- L3 \$ E
{
- c* n; i0 ?, m9 [# Y# ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: ~. H% A2 _2 a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* o8 ^; V9 }, d' ~2 S8 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" K2 V# c3 ?2 ]. C: f% iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! ]! |9 _) ~) e1 a9 R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. g4 H7 W, d* C7 V8 F9 K5 [
MCASP_RX_MODE_DMA);
f9 B" S" U( Z/ y- y. wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& v4 d/ D* o4 p% ]7 x. d7 Q, U# DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( z" i4 f6 d0 v: O8 b1 @3 m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 H) ^. }5 G: S: S; C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ C6 Q7 p. M( n9 e- Z- I+ A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 o* | \9 P' U& S, F9 t9 w: i/ cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
l' t2 R- t8 Q* t& IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 n: P. Y V8 s' C/ j/ QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 A1 f( K$ ?4 [7 l5 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 V& F {( }5 M4 a( }; U" o
0x00, 0xFF); /* configure the clock for transmitter *// U6 R; |0 k/ m$ \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* w, E8 |$ W2 y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 e8 z" u% z0 u2 x5 M# u# c$ Y* j0 ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* X, I0 u4 j6 D0 u; V; s
0x00, 0xFF);
1 T- \, m0 C; P, t& a7 ~' r/ S+ e# f w! r4 h
/* Enable synchronization of RX and TX sections */ 0 T# f. v0 U$ j! Z. C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 j- i5 C3 x( T* [2 u R" q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 a) i" ]! o! e P# P3 M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" ^" @0 w# a9 N4 d** Set the serializers, Currently only one serializer is set as
* n7 J; z% ]& d7 d** transmitter and one serializer as receiver.# `1 O1 K2 G' C+ p
*/& O/ H' {# v( S( x/ U) L0 B# w9 [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( [# q* q9 w) Q6 R3 p g1 m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 [4 t% ^# t o) g0 _% a' r
** Configure the McASP pins
/ n9 l8 s& s/ b** Input - Frame Sync, Clock and Serializer Rx0 t! u! V7 j% Z! N/ V+ m
** Output - Serializer Tx is connected to the input of the codec
1 o; K- f) s; T7 {* G) G+ P% K*/$ k) t* ]4 e! H5 S1 M' [# g+ C9 w
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' X5 e9 M# H3 A& P; [0 k* r8 b% [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& N# K' {8 u* v) S+ v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, x9 [( d4 f; Q! f( d4 f% u7 C
| MCASP_PIN_ACLKX! a& r. _; L& i
| MCASP_PIN_AHCLKX6 K$ M# O8 {! a1 P$ B1 E2 q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 } x* o( M, ?. A2 W6 d" J& ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . J5 L3 m' P, y/ T' Q. r/ D ]1 v
| MCASP_TX_CLKFAIL 0 n/ o5 g8 @. N. W& U1 e% r
| MCASP_TX_SYNCERROR
7 ?, `1 Q7 U) N8 R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + j0 W. K$ j' o
| MCASP_RX_CLKFAIL
' ~- D3 O" Y" |; c| MCASP_RX_SYNCERROR 2 E" s! @$ q# p M2 ~1 P' q/ H6 g
| MCASP_RX_OVERRUN);
/ Y! s3 m$ v h3 k% Y; C6 S8 A% K} static void I2SDataTxRxActivate(void)0 ^1 h. r9 W+ m, n
{
8 F4 S$ h( d. U& ^/* Start the clocks */
7 K& {, X3 h) x& T, P: u; TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 \% G+ m& g2 r$ p# a. @/ S1 c& \+ w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) I% S6 S, k9 S5 t. @( x" O- ^3 x6 I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 [5 Q5 O8 H2 d
EDMA3_TRIG_MODE_EVENT);; @6 M4 k, B! X4 }2 @" b& I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 W. i r- |; W. D$ }+ k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// x$ F: R/ W+ K- |5 D( k" r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- F j2 ]( ?9 ]* K0 l( N4 E# l4 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. E& B1 S8 t9 C6 K% }! t3 s% L r" fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; A& w* J' {" [! k- B/ YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 P' X2 o1 K% q$ K1 v1 B: P# a3 |, w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 A! @: G9 w9 v3 V5 Q- y7 P} ' k5 I& u; U$ }( c- V- c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
! B5 ~2 [2 I r. f+ d3 ` |