|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 N5 e) u- c! _" S* oinput mcasp_ahclkx,
' F1 X6 {4 W8 c, oinput mcasp_aclkx,
* N2 \. M$ ^' ~8 ~; k. o% Xinput axr0,
0 F3 V/ a8 T& ~- Z) R% n* b8 d& ? z! o
output mcasp_afsr,5 q- B* X, z* ` {: i4 }
output mcasp_ahclkr,# H6 T6 n K* Y4 Y+ ]$ [8 E
output mcasp_aclkr,; v7 J8 m4 O& a" ~! Y2 o
output axr1,, b7 ?4 d5 B" t4 Y
assign mcasp_afsr = mcasp_afsx;
2 K+ }% E( ~9 V: R# c0 J0 \assign mcasp_aclkr = mcasp_aclkx;
+ \- z. S& ~7 Xassign mcasp_ahclkr = mcasp_ahclkx;
6 _! \5 S& A* z! s& U9 Hassign axr1 = axr0; . J" O: k1 @: o' _3 _
% _* ?! ^' f) E. r4 n3 _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 F5 Y9 W, _% K& \static void McASPI2SConfigure(void)
' A% B( O: r* e- U( n& @- \& X9 y{
7 L, _3 E' ^ f4 T A2 b; KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) e3 X) e+ V: Q4 T. jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 Y3 N# L+ A6 M1 Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* m1 o( }5 ]3 q; c4 T6 @2 l8 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' v/ x5 d, }1 s7 h4 x# R" y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: @3 \! l) u0 q! wMCASP_RX_MODE_DMA);
. z. y# Y) m) b0 F; R( j% aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; }7 z7 n- G4 E. l8 X" w/ |0 A2 w9 {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: }1 y) P) j2 a( ^+ U: FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* q) ~' s) `$ mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# P- \' p/ g$ ^! H5 SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' u; p. n& b2 w" c: Y+ n" ?+ U; A9 { }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" C l- S0 \5 e3 {) L3 m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 ?, Y! Y" d( E( e/ w1 s2 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 |! r. J6 D* l8 ~! ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( b* h- m# v* `' B8 i$ J: e
0x00, 0xFF); /* configure the clock for transmitter */5 P, a/ q3 r% M3 p7 E, P% ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ b. k2 @, i- E) ^, d6 }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 f) i) c, {. X) R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# T' V2 }0 A3 C+ C- _( C
0x00, 0xFF);
( f1 A- `: J- I& ~! q+ v7 T
& _0 ~; l# G% _1 \- y/* Enable synchronization of RX and TX sections */
7 a( c# ?% v) u/ }. P9 WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' d% d- l& M' [; oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ e+ z5 A$ W0 T3 k) u; oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 d- o* n# \3 X; [
** Set the serializers, Currently only one serializer is set as0 i9 o& s/ [$ u3 m! f
** transmitter and one serializer as receiver., e+ j1 D) N5 q [( n8 P
*/
) r( k/ }! Y& B9 n! q9 t7 O9 TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; O5 [0 S* N8 F( D" d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ S% P* }- m6 p- E* X** Configure the McASP pins . P% J, h6 t% F
** Input - Frame Sync, Clock and Serializer Rx
, a3 p- W( r9 S9 }2 T! Z# ^** Output - Serializer Tx is connected to the input of the codec , `, [0 K2 }" _' Y! u2 p( q
*/2 W, b0 V! I( _# F2 n% J- B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: b. N7 t! i( \/ A, j9 a5 z, |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' K! ^; u1 a6 w, _ k+ Y% j, q9 B3 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# @& t- i; ]. k8 X' q| MCASP_PIN_ACLKX% W( `. n" _0 C, Q
| MCASP_PIN_AHCLKX
+ J0 r6 R/ H% A9 T. R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ a5 {; l2 [" X* F' r$ FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 c4 I/ D$ n# m) z) R4 o* i; d# w| MCASP_TX_CLKFAIL
1 f+ v$ I' a7 G8 W| MCASP_TX_SYNCERROR. v, }: I8 C0 {2 s% q" K2 z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - T$ e7 q! Z8 e2 a/ W5 K7 ^
| MCASP_RX_CLKFAIL) u3 O9 D" _. y0 i- s
| MCASP_RX_SYNCERROR
! _# e# z7 y7 i1 ^| MCASP_RX_OVERRUN);
) i% G/ }% {# H+ | o} static void I2SDataTxRxActivate(void)* \* ^- p1 A/ p( k0 [+ I h
{) e7 S; A" I5 t
/* Start the clocks */
, x" Q# ?" z$ q9 Q0 `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ v2 [( p* ?$ H: J$ UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! P2 {: t5 ?. ?* ~1 n) b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 {5 {7 F3 p" f! I- |6 K! k6 u7 I
EDMA3_TRIG_MODE_EVENT);
9 K$ q0 {; l& A# iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; R }6 O. g G" b! dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( e5 K: i2 M) S* M+ A7 X+ g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; J0 X E! V7 t: P3 nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% [0 i1 b( U) L4 g2 r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 S9 s# J, A4 z1 ~7 C$ |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& m6 m, T1 d$ e4 {2 JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, f$ J L" {. M6 p4 x5 U% u B
} ! A* v- u# o8 D2 X' g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* k3 o' E3 V i; A: g3 l! X( o |