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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% p5 V& q. {; F: b+ Vinput mcasp_ahclkx,, Y; A& \% u$ D( S5 ]
input mcasp_aclkx,. ~! o. D+ X( {0 \* v3 J- I& q; S
input axr0,! K7 P) e D, v# b
% a; y& [: T0 k! Coutput mcasp_afsr,1 a0 i- Z6 r! X, |& Z
output mcasp_ahclkr,
! ]# Z `2 O$ A; a* X, Z& V) Qoutput mcasp_aclkr,8 D! g3 h% N! L; [
output axr1,: w; H9 H& s7 U" Y/ p
assign mcasp_afsr = mcasp_afsx;
0 L5 f! ^" @" \2 z1 Vassign mcasp_aclkr = mcasp_aclkx;4 I! l2 I3 a$ k5 d5 W( k
assign mcasp_ahclkr = mcasp_ahclkx;
9 A# g) }5 A* z) kassign axr1 = axr0;
% z# O) ?, ~% R4 O$ n/ `/ p# s
7 Y4 ?4 U( f) h1 m i6 X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) l( y9 D' p0 b8 Ystatic void McASPI2SConfigure(void)
; S% d3 C. D5 F{
1 m$ U3 I- I0 E" H* d; g+ E6 JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; g: l, e2 Z) _' \McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 w6 `" |! t9 m, e4 ^, [; o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( q1 |( H7 w+ X) m1 UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 J2 s6 ^' ^9 K3 R7 E! W# L" yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ X7 C9 D/ A h# o, O) @! d# IMCASP_RX_MODE_DMA);+ d0 Z" t) `' u- J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," z4 L4 P+ s v: b- G. U3 o( X. G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ I3 m7 v8 R; {1 X1 B4 G# Y$ ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 D3 z, c8 l- L9 T7 E0 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 O* @: _/ e, r+ qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( V) O6 S3 ? b: I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" P3 D4 c8 K0 }9 F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 L& I" [; G2 M$ G! M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); L$ D2 D% Z6 U. p: c" ~- x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 L! I; L6 Q' |, U2 Q' ]; o
0x00, 0xFF); /* configure the clock for transmitter */
# q5 X5 }( E4 Y; t" y3 @( {9 s% JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' ]0 ^, h6 b; [0 u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 w; y" X5 D& @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# p% b5 `: t* h$ @$ c7 w
0x00, 0xFF);
3 N' s* J; W9 s2 s( p
0 m: \6 E s6 w9 Q. P+ e/* Enable synchronization of RX and TX sections */ % p$ _8 r1 K' z3 _* o" y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 r* M* @' Z$ f' R/ e% O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# v7 i% F5 o$ o; b" h+ D% N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 V1 y5 L9 p2 t1 _ [
** Set the serializers, Currently only one serializer is set as
- ~' b e0 R* P" F** transmitter and one serializer as receiver." p9 Q6 n' A2 `/ ? d$ X! w k
*/4 k9 B5 S3 C: [0 E7 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 N' m4 {9 C' x" R! x- TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 X1 m5 ^9 m1 u+ t9 q
** Configure the McASP pins
' n+ p' O0 Z9 q/ U' k4 P3 v, F% z** Input - Frame Sync, Clock and Serializer Rx
3 w6 @, m3 @* k** Output - Serializer Tx is connected to the input of the codec 8 {! U# L1 V8 P% ?& |; O* r/ K8 x
*/
8 k7 `$ t; u: yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 k/ h: f Y4 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( E8 L5 x1 |; {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* v# t; d/ P" x3 j& u. \6 x| MCASP_PIN_ACLKX# T2 }/ Z) B6 i2 g y! r
| MCASP_PIN_AHCLKX. V' i" X6 |6 v- \# x- e) I' E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 r. y/ }* i) @( E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 O+ y8 d; Q" w- || MCASP_TX_CLKFAIL
' K# ]6 o3 r; K% k) k| MCASP_TX_SYNCERROR
5 h8 U/ y/ W1 x6 [3 Q6 X: z' w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) E- f# O7 F/ g0 n9 a# v- O| MCASP_RX_CLKFAIL
* o) k8 |# J& Z# l$ M8 ~" D| MCASP_RX_SYNCERROR
& r# y, X5 \9 w2 F2 H$ L| MCASP_RX_OVERRUN);
3 f R6 [8 Q7 ^% A8 S0 _* v! Q} static void I2SDataTxRxActivate(void)
( B2 o6 Y6 s1 c C{* w. c' ] P; ]" e8 V" g
/* Start the clocks */
6 K1 l- r: J3 r% y, A; T; fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% W* C4 k# U0 Z0 k7 P* z- t) \3 xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 _, S3 w1 C9 Z5 p* C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 k. V C6 p4 F9 d$ L, ?
EDMA3_TRIG_MODE_EVENT);
8 F1 E) H: c! lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
P4 e) L7 }$ @6 qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ s" ]: ^/ L) g- N$ ]5 b9 TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; N( i r6 b: T) R! d, f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. a, L6 i' L4 f6 a' Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ {6 m: j1 O' D( dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 x# f, [8 E/ h8 w+ r: g4 o' zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 z; _- W; B: h# c3 c
}
* H3 h" |1 [* p4 m! D0 E; L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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