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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: R" [* e' D; l7 V ]4 e/ O5 `& m
input mcasp_ahclkx,
3 H; c$ Y8 T) C: iinput mcasp_aclkx,
9 K {) u0 C! U, t: binput axr0,
8 \7 J4 \$ n4 c \, x/ X
) L# y8 n; t7 w: ooutput mcasp_afsr,
1 B. r. c+ e2 C* Joutput mcasp_ahclkr,
$ v# t. V3 m/ Moutput mcasp_aclkr, i" J: m) c$ z5 s9 d
output axr1,
* M0 n# G) }8 E% k' E8 B' O assign mcasp_afsr = mcasp_afsx;
0 B* W8 O: ?# x; Fassign mcasp_aclkr = mcasp_aclkx;1 a) I# \* a; f. ^ M0 j+ ]
assign mcasp_ahclkr = mcasp_ahclkx;* _; K! \4 H. o
assign axr1 = axr0; 3 k/ M3 Z* y8 D. R& s
+ e3 L+ D* g. l6 m* N; a3 k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' H+ l: U8 ^# @$ P- f+ Jstatic void McASPI2SConfigure(void)- R7 S U0 m' K4 z0 L' }+ t
{) `! q% i" A: C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( \; E4 O/ N; j+ m4 |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# y" \+ H5 N. D8 d* o6 ^, D) [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" f7 S& T. |9 j$ R }* O4 ?) IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! t0 w5 {. L5 X k. xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. s; Y! u+ Z' Q' Q' q8 ]9 M' d, c
MCASP_RX_MODE_DMA);2 R6 b% `# q1 } j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ {9 e6 I6 t+ ^9 Z+ O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% o% d) K a4 w) s$ k- PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' b+ z/ g& y$ v$ [& u. ` e* t: }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
G4 t5 d0 G, D7 O. sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! I* e% G7 z+ uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 \9 d2 L* j* v) @; [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: ~' p# c4 u2 D8 ~6 V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ R; s& X7 i8 g' C* I! k# B% w# ^5 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 d7 C/ n! s$ p5 Z2 D0x00, 0xFF); /* configure the clock for transmitter */
5 c, { j7 \! b, xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& H" I. `) n6 dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 h7 d2 \' |8 R: x7 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- j1 r( R* n# B
0x00, 0xFF);7 F4 c8 \8 Q9 a+ P6 w0 `3 V
- p% |% e7 U9 M+ G) d6 W/* Enable synchronization of RX and TX sections */
5 @0 w' _) ~" ?) C4 g. y7 [$ C2 {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 C( w, k* z% X! t T- ~$ jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) ?+ K) O: q8 X. dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; P! P, L' F; q3 S5 o4 Y/ u3 K** Set the serializers, Currently only one serializer is set as
( N5 {( [0 \' A** transmitter and one serializer as receiver.; V; h5 O- a7 w. f# v
*/
# S9 _% v6 @7 g( G4 bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 E' }! y( O! L+ L7 o2 `; @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, T1 @3 S: ~/ V/ C# z
** Configure the McASP pins . ]$ y/ W/ Y/ K* g
** Input - Frame Sync, Clock and Serializer Rx9 S1 t8 @, \# |+ C. ^$ @1 t
** Output - Serializer Tx is connected to the input of the codec
/ A! \$ y% l/ t+ r+ _*/2 r9 m8 b! u, j p& f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! G* k0 h! j* R( C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 N9 H. f, X0 |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# F- C* S& ^1 N| MCASP_PIN_ACLKX
& {- s3 @" |9 C+ e/ y) Y! D7 d; L9 y| MCASP_PIN_AHCLKX
( w o9 I2 e4 K% z s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ P% f- s M* q, F3 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 C! e, @* l& V! l5 v9 u
| MCASP_TX_CLKFAIL
0 t+ Z7 W* l& X| MCASP_TX_SYNCERROR
4 j+ a, I! x) l) ]5 t4 Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & @ E! `2 c8 w# m
| MCASP_RX_CLKFAIL
9 K9 T7 Z: J, R: p9 `| MCASP_RX_SYNCERROR
% D& y7 w! Y" g8 h0 f| MCASP_RX_OVERRUN); Z$ a1 u) i7 [) y, ] @( Z
} static void I2SDataTxRxActivate(void)" o. u* x5 s/ A- n
{" l9 I+ ^) h% R+ m6 |
/* Start the clocks */' k/ R# e, D B2 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" z4 s# ~/ Q4 t( i& t- D: M" jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* j8 G0 W# a. IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: I1 c B4 y9 K$ w# y/ | [EDMA3_TRIG_MODE_EVENT);, L% {( s) i9 K9 a* g# ]0 ^) X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 l: X! o) U) U9 [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! B/ r6 E" G: K7 {8 E N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' s. [, B I7 _- p: H1 T7 n7 rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- C `3 o6 x4 Q# O: o7 c: g: M0 {) M" Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: `% i- _% r$ M" k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- h/ u/ E$ X( n% ^+ |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ C2 n5 }5 `& A x; S- {3 R} 7 Y# P+ e1 x/ F! V4 q3 ?8 a1 T0 H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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