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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: P. b, c" ]: {! Tinput mcasp_ahclkx,
" ]* g6 c5 x9 ~! `2 minput mcasp_aclkx,
$ q3 O' N5 z- O$ Q. q( [input axr0,
7 X# N) K9 I: H1 y5 O
' P% L b1 ^6 |6 y& H, V8 v2 Z' k/ Xoutput mcasp_afsr,% O6 r, v _0 c% Y% A9 W8 h6 N% o. }
output mcasp_ahclkr,
, y5 [3 g8 c; U& \output mcasp_aclkr,6 Q) M* `+ o9 o9 x7 V7 P' G, _
output axr1,
) [+ O8 L- w9 \( T5 K: g assign mcasp_afsr = mcasp_afsx;
/ G3 A, K% t7 k }- Xassign mcasp_aclkr = mcasp_aclkx;
4 K( r: M+ S+ s" _5 ]. r& O' w5 gassign mcasp_ahclkr = mcasp_ahclkx;8 l0 L* I& y3 ?* N5 H
assign axr1 = axr0;
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' `$ Y2 y+ |' W! o5 t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' R7 U' z p8 I! ystatic void McASPI2SConfigure(void)
1 c) `& O; A# P8 |) }2 M, G{. q9 [% h2 @2 @3 d' I* ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 K: h2 Z7 x2 e! [8 t V+ HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 D, S# X9 ~5 `) m' \# _% N2 N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 M; y5 G2 s* u+ O8 t; ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. T/ }0 f2 d$ f1 P" aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 }4 r( T- {7 A% ]; NMCASP_RX_MODE_DMA);
. M& U# Z) L. g- B& g' K; }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 [% X5 C6 y X+ T( K2 {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 A- t) s' _( W2 s/ z8 ` X9 q, v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; K7 e5 L* E0 j$ N# e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& h/ Z2 I+ R Z6 r5 T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & J3 f- i( }! e" C$ E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) q9 P4 G8 |1 ~ x% y `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 A7 C- f% H9 \' h/ OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: E5 U' [$ z: J% v6 Q8 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' O0 S7 V6 L+ p. Q) q
0x00, 0xFF); /* configure the clock for transmitter */
) U1 I W2 Q7 p4 X& ?3 V; q; IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# y S; U1 G6 j# }# \ M3 e$ PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 L/ ?, s, z0 ~8 b9 O2 y7 N6 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; _0 k- W0 r+ ^; n- r; H6 ~3 {0x00, 0xFF);
4 G: G2 ^( T- r4 V# x0 Z- V% c* q- N/ w; k3 p
/* Enable synchronization of RX and TX sections */ + ~& S6 W9 F# y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ j+ c) d6 W' a7 gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( J/ ^* ]. o. W% i0 J6 T( a6 OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 ?2 x5 q' _0 o4 l+ n O; H
** Set the serializers, Currently only one serializer is set as
9 R) F- n( e# q- a* |/ S** transmitter and one serializer as receiver.
! f, g9 z; Q+ z9 v/ F*/
2 E& u; g& k8 L0 E* j4 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 h: b: z8 W, L2 }) [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- D7 x% x( ?4 G+ H5 L" i) W5 G
** Configure the McASP pins
8 @) G+ u* c+ e5 C4 Y** Input - Frame Sync, Clock and Serializer Rx
. |% M9 }! y* B+ |: O** Output - Serializer Tx is connected to the input of the codec
+ l, K( W+ w/ x. ~5 C, Y: ?*// m$ Q8 H9 q. c0 M5 i6 g: u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; h) M$ d& h! J; E# p7 s" y* `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ G" z5 h. b- B. z$ I1 P( Z; X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# Q2 @+ G( }) c: {' r8 n, Y
| MCASP_PIN_ACLKX
7 u m; w. G- r: W; g5 h6 q. N| MCASP_PIN_AHCLKX+ I5 Q- o- k$ @( h# v( `, [1 h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 ~0 ^! O6 q, O2 L( X9 F6 z( b6 mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 l( n8 Z' ^1 R9 `
| MCASP_TX_CLKFAIL
; L& Y8 z% d5 R' o3 B! P' e| MCASP_TX_SYNCERROR8 s" E8 N/ O, f0 X ^
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 {# H4 f5 z8 n/ u7 ~ M
| MCASP_RX_CLKFAIL
" P+ X+ B: `/ c* X \7 B| MCASP_RX_SYNCERROR . g( V$ V) W' p) N; E" F# f4 h
| MCASP_RX_OVERRUN);! }5 h3 x4 `( a7 b( v
} static void I2SDataTxRxActivate(void)% i( B4 ~3 Q3 u( H! Y( P
{
5 w# n. ~$ @& p# H: C! F/* Start the clocks */
; u' R# M+ A4 S) P; cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ U( G0 H7 p7 E, `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( e1 W8 C9 @0 {" i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 b5 d/ Z6 x, B: b0 a5 \
EDMA3_TRIG_MODE_EVENT);8 R1 r2 K" B. u, M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; p( ` l8 _- Q8 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 [) S; V- ~4 e4 P2 ^1 `: @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: X) |" o, L' J% S( V8 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& r9 K5 }& }' a2 ]5 b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 H# ~" }0 V* A0 [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 k' u9 W' I0 I. LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 E/ Y9 C X* m7 j( T) Q2 l
}
2 S! k: ]2 _) R0 D; n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . P4 c6 ^' }. S" d M
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