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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; j4 `% P6 ]0 u
input mcasp_ahclkx,
3 k+ ^3 j3 O0 o' S( t" b* g% `3 A/ @input mcasp_aclkx,
4 k8 R% n6 N! x& A6 M3 e; K. j* z% dinput axr0,( E, e" o2 I' F. U" C9 ]3 t
9 Z' k2 w5 }1 k: i7 M( e+ s3 L+ y
output mcasp_afsr,; c2 s9 `; k$ F/ W/ t
output mcasp_ahclkr,
6 [* x3 m. f9 w8 p& d& x# Routput mcasp_aclkr,
( s: h: x- K0 b o) s moutput axr1,
3 Q8 X) ^( W% m1 a$ {8 ^1 y$ N" b assign mcasp_afsr = mcasp_afsx;
# p/ o: g& g- C2 M, Uassign mcasp_aclkr = mcasp_aclkx;
0 \# ~% m6 M \- e' q6 t+ b) |' massign mcasp_ahclkr = mcasp_ahclkx;# `3 N3 z5 b, F: Z& A
assign axr1 = axr0; ( O5 b- _% W: W# y( P; Y6 W1 l
) W+ k4 R5 ]# ~$ L3 ~+ D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; |9 g) X g0 f% Y3 ^ ostatic void McASPI2SConfigure(void)
! W d, x7 o: `9 Z{
5 F) R3 R- }4 V; o1 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! T3 Q1 M d z- s" s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" g% i5 C6 y u0 i- FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. }5 A' z* f. H. _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. s. ^4 ?4 h3 G2 O. d* q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. H W% s+ e4 w1 W" @4 J; K2 g2 [
MCASP_RX_MODE_DMA);3 |* K' H5 G. p# t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 u+ E: b' {) f! [ q. s6 G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' g+ J3 ]# \' _& m5 j. q1 }5 y9 h' aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% v6 [# w9 m( e. H8 f8 EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 W; z/ j2 B9 i: n0 L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ g I( z4 v5 }" T. VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 t0 E0 p% e$ N. c) w/ [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 E# B+ Q6 i+ |9 w* H1 HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ W9 l" `/ T8 w' BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 T" e: [, H6 x" c3 G" n0x00, 0xFF); /* configure the clock for transmitter */ K. y* K' [. _. D+ E/ Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. l A! p' `6 U9 X% ?8 q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, _ Q! H+ J: E2 r& z0 @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 E: X7 P& h; ]. k
0x00, 0xFF);! Q9 I& Q5 F; R# B' e. K
# q. r8 u; N$ r, m- r, B R/* Enable synchronization of RX and TX sections */ : D+ v/ L8 h: L/ J% S% {7 ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& A, {- f2 {) u+ k$ n6 ~, }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: V$ p) f+ z. n1 A( s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 q7 e, b, [$ f, {' c
** Set the serializers, Currently only one serializer is set as2 d8 e+ D7 n# E3 W( S% L6 a
** transmitter and one serializer as receiver.
$ H; _. \, j- e# q+ h& |*/2 _. m6 u4 y4 ]4 h6 T) N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: e- s( W, N8 ~/ FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( I+ D/ L" e3 M/ O3 R# D
** Configure the McASP pins
& K0 p7 f& ]- ^" M4 G/ a: w** Input - Frame Sync, Clock and Serializer Rx( h0 t7 T( c2 t; m( ?& X$ O
** Output - Serializer Tx is connected to the input of the codec 1 w! [+ e+ i4 O2 F7 s0 H
*/
* }- d$ \$ d* ]5 B/ ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* z( ^, C, a; D% ~; jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" ^$ F, A1 r) R# t8 ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ O" b6 M/ z. e
| MCASP_PIN_ACLKX9 r- ~( a, k- `
| MCASP_PIN_AHCLKX
0 a' U U2 f) N, s% v& p8 @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 M m- A: r1 U0 e+ V: W0 mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 ~& I/ E' Q, X6 b7 ~
| MCASP_TX_CLKFAIL
; b. F2 C# l' H2 c2 l1 C" \% @| MCASP_TX_SYNCERROR
- {. ^+ T( u' K$ |8 _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' K, J; r+ |# F6 q: G6 _" p| MCASP_RX_CLKFAIL5 d! h8 l! [/ m" t
| MCASP_RX_SYNCERROR $ _1 @" Z- M4 {! K1 X, u7 ?) L
| MCASP_RX_OVERRUN);% y& k$ e" r3 _# i0 k% ]
} static void I2SDataTxRxActivate(void)* _9 A& Q# a+ d9 ?- O3 R
{
) R; G! R" ~* E# h/ h/* Start the clocks */+ }% t! J0 E; R, Z& S9 r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 H0 o1 F1 L' ~1 ]4 z& ~0 t: ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ ^, A8 y- F0 {+ j; j# bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ X5 O# T5 ?' v! y9 u
EDMA3_TRIG_MODE_EVENT);, M2 G3 D6 X4 J! ^) n% O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / U: l' h% O* @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 p/ Q# X' f( B6 Y% n9 PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ m* l& ^3 e/ v2 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: ~& z) B7 x6 swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& R# h% n$ A4 s9 }9 a( HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 l- v8 @6 n. _3 z3 F" j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 j4 {6 k ?3 E} 7 L1 C' Z' }5 Q) Q* s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - ?% a+ V, U5 L1 U# o+ @1 ^
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