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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% Y3 l1 v4 @3 _input mcasp_ahclkx,) W/ C0 R+ E9 H! h6 s3 ]
input mcasp_aclkx,3 A8 S/ q5 X" ?" B2 o8 w# B& T
input axr0,
+ x, d7 {4 L- \
9 @+ F$ F& i) T! t" Houtput mcasp_afsr,
B; c( H- P7 Z& I# routput mcasp_ahclkr,: q7 ?$ L: Z3 w+ V
output mcasp_aclkr, o5 L! r: k: A6 w! p
output axr1,7 b6 e( i7 Q. s5 w
assign mcasp_afsr = mcasp_afsx;! U2 L- d5 M2 {- ]5 b, d
assign mcasp_aclkr = mcasp_aclkx;
& ?/ k3 |) l7 e& I: W7 k; Zassign mcasp_ahclkr = mcasp_ahclkx;
8 h& `4 ^1 i: S3 a$ Nassign axr1 = axr0; " ^$ t& u% E" M; H+ ^9 [
3 M* E6 V5 t6 u2 I* n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 h- A' Z" I7 Z7 [" p
static void McASPI2SConfigure(void)* }; S7 i% m o: ]& W1 g! [
{
. U2 \3 c) g+ X$ `! wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; h% U2 W+ Z4 LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, j5 k/ I5 [9 t# X: f: _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& k/ y( p& l' V+ _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 a" L8 ~2 e4 K e' p$ P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# L1 u1 q5 y, L5 GMCASP_RX_MODE_DMA);
9 _5 V [ o2 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* [6 O. D( q# _$ C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& m# x5 g; D1 p! Y3 @* Q6 v* b# @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! u9 ^. M6 k1 t* r4 b, G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. V. y* y# d& lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' U# G9 ~2 s0 p6 T: z9 ~" c; S4 Y. |; b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' u( `& |6 C/ z( \9 O$ j9 L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* i9 Z4 c4 O( j0 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 W2 h! i( w8 g7 a2 u4 i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- S( q- h, @ x' R6 G7 ^7 D9 y
0x00, 0xFF); /* configure the clock for transmitter */
/ Z9 s& B5 m8 K6 IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' f+ P% K. |& G/ p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* Q/ v. B% T, c+ H' q; m: F. x7 _! EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' J$ j' w+ ~ |4 D7 U1 v
0x00, 0xFF);8 N0 m% S5 }' m" R6 o% t4 @: B
/ ?* m$ m' f/ ?( R# D5 p% \
/* Enable synchronization of RX and TX sections */
$ P5 Y' I$ F; X, f5 |/ R+ v( ?1 wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- S3 C1 l N- U/ e7 QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" A" {( j6 C* M! P1 m: V' g! a4 ^2 rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. @ N. x7 \$ h% }! @** Set the serializers, Currently only one serializer is set as
: O1 {; ^2 h# V6 T1 @** transmitter and one serializer as receiver.
* ^. S7 ?0 {9 b1 G8 g1 p' @*/2 W! P$ ]5 A* Y9 M' |0 Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- ?1 x. K+ v& S& {$ h% gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 {) f8 e v+ R q2 y$ T2 a** Configure the McASP pins 8 X2 V k' c6 i; w- J( d: m
** Input - Frame Sync, Clock and Serializer Rx
; X0 f2 K F/ M& P** Output - Serializer Tx is connected to the input of the codec + Y* J/ l0 {7 y% V7 F
*/
( O3 u5 Q0 |& \9 u3 S: L+ EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) O) w4 B' Q& `! h6 l sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# h. \/ [. i2 i/ _( _8 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% c) N" b; }2 w- t( x
| MCASP_PIN_ACLKX# j7 [. s; d6 A" l
| MCASP_PIN_AHCLKX
4 ]- _& T: g3 p4 L6 H+ U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 U' P$ I, ~5 y! r1 t2 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% e( p, M4 q6 b0 f: A: n| MCASP_TX_CLKFAIL 6 ^; T8 v* x: E. s8 r& z. M
| MCASP_TX_SYNCERROR
9 x" @" @; i! p. _) L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 i$ |. B, s) o* h- R; k
| MCASP_RX_CLKFAIL
- { q# B6 j. S, }$ D4 ?| MCASP_RX_SYNCERROR
1 a1 c! _) }$ B# X| MCASP_RX_OVERRUN);
$ C' b5 S v/ h, |7 p0 z} static void I2SDataTxRxActivate(void)# c8 J8 o' c9 f, m+ _
{
( J& s. V) [$ w/* Start the clocks */
( ~8 m( q, s$ T! U/ |+ ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% S7 U9 {$ @1 M2 l# E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: ~5 J4 f( w! R- U1 U" t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 m @7 A$ _" T9 v- V; c; d7 K
EDMA3_TRIG_MODE_EVENT);
. R0 k$ N3 t& T8 E, M NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- p0 R0 I6 n3 k; pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 b! H1 ~5 }) O% y! s) B0 v( j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! a% }1 L9 c7 CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& S1 P( L' u% |8 u. p4 j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; c# ^6 v# c U; U6 W0 Q: q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ Y; f' F8 D: o# d7 jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; u2 \( d' X( S0 p7 F} 3 f8 y/ S$ C! ^- K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 j' w, h; M- U5 t/ t6 H
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