MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
6 ^2 `" @  u$ o% B! G8 X5 m  ainput mcasp_aclkx,
input axr0,
1 T1 b9 m2 o) }& J& i2 |( l
output mcasp_afsr,
" g2 f3 v9 q9 f  g" x( Ioutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
6 U# e" U. j4 Y& P

assign mcasp_afsr = mcasp_afsx;
/ o# d5 X, a. w3 Y' \5 bassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
( S4 M) |2 {, \/ h* P4 p( {assign axr1 = axr0;

2 \# r: P6 x2 e
. k6 L% c7 s, ]5 J( {3 O: z& e* x

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
  V# A- z7 Q* F: G2 G" J3 kMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
  U0 y6 z$ Q/ h  i( KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
1 a1 V7 L; L! WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! C# p% ^' j& ^6 X6 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* K$ ]: P$ S" s5 U' GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 G5 I7 W7 o1 j1 \' g) \* ^  uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
! a- B8 Y- q+ H" q, ]! RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, Q# B+ D, I) X- u1 m) \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( E& s" w4 {! I+ w2 K0x00, 0xFF);

/* configure the clock for transmitter */
9 F  @9 ]' b) ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: l0 P4 K1 x( f( p5 {' `; sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& H; C) q6 g. {3 ?& }0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
7 {" F5 W7 }& X% t6 R3 S5 r9 WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& N. |, O+ D2 l+ d) B8 CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
% C" _* b2 O, K$ `9 e3 r  O) O** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
, X$ |6 r/ Z$ ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! a5 {( d) L  b2 IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
: i1 J. H- J/ _/ g** Configure the McASP pins
  y& x. T( L! V: g** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
" I4 A. q0 k% O2 ~1 R*/
3 T0 j+ S) b4 W* \+ e/ SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' z9 N7 c2 j1 ^% lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 E# H7 p, M+ b' p# n| MCASP_TX_CLKFAIL
2 p0 d, x) C% j" E# N/ K| MCASP_TX_SYNCERROR
8 Q7 y1 T8 ?% P- {0 M" U| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
) G6 g$ u* P# x6 S" F2 X! V}

static void I2SDataTxRxActivate(void)
+ k: m  [$ ^1 ]0 F{
) t0 H9 y6 D: w; U. \/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' _1 w, x7 t3 u( _: {. }$ H+ Q" _$ N, FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
( {$ j  ?- M2 r3 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 ]6 ]0 P8 ^/ t. P; wEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# ^  d& I$ X) S2 q( D7 TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
1 a- T- ?8 S/ k6 a6 w7 O# h5 r5 _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
  P( r5 M$ S: D1 V3 jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 i0 I+ [( M9 M, o6 Z( T+ bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

" x8 _- ^9 d6 X. Y( w6 x3 c

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.