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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ ^" C i0 {7 U7 Y6 w; \input mcasp_ahclkx,
- ]& L5 b: c/ L+ @+ r) Sinput mcasp_aclkx,1 z( B# v8 k, r3 {) t: n
input axr0,# [. M+ Y& }! b% Y
' P2 W( R$ g& o! |% o D# ?
output mcasp_afsr,+ s+ G. Q, j. u5 x. j
output mcasp_ahclkr,
/ Y0 _4 s% S& V5 w1 P4 O: h0 L9 uoutput mcasp_aclkr,
- [+ O3 b: V$ @- X6 _output axr1," Y: G; P) O9 M0 x6 i1 b, {. j
assign mcasp_afsr = mcasp_afsx;
. B/ i( ]1 I2 X; T' h" I0 u6 D- Zassign mcasp_aclkr = mcasp_aclkx;3 h/ a' }# Z4 Y/ a2 e3 i. R
assign mcasp_ahclkr = mcasp_ahclkx;; ]+ O! j% [( G8 ?2 z* h3 C; W( N* c
assign axr1 = axr0; : S) O; k+ l5 r& t
& V5 N4 T" \' Q$ I2 i$ ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 N: b) B# |( }2 a6 k
static void McASPI2SConfigure(void)# g2 @# z" y6 N7 d9 Z6 e/ g) H
{
; U. i* T! r5 V8 xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 I1 J8 r4 T" y7 |- d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 b! z3 G& a1 ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- F) S. b4 l9 g2 T% f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 }) A% k# x9 {/ K8 Y2 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& V- p3 o2 |. `1 T
MCASP_RX_MODE_DMA);2 g6 F! @2 }2 \* Y1 h% }" q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: [# E4 r# W0 w% I+ s) E; M" eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" t3 A4 j0 k, _+ K. xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 H- x( t, p* q2 p1 S7 X. c* `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ f" F0 J% q/ SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * U! n! F' n6 W0 P, G$ a5 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ W, v& Y4 F+ s* _9 k# hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( {5 _% w" |1 }2 c, s4 M7 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: p0 i, ~; q. V5 r4 p- SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ i2 b5 _: z, N; H0x00, 0xFF); /* configure the clock for transmitter */5 r4 c1 D [* T" |& u) n; T2 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 u$ b' ], X0 w( k% U2 Y1 |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & X' d' k G+ e# d) a- ?& a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 [; K3 {0 @. y, @" J
0x00, 0xFF);7 n* ?" e4 S. c/ n+ ~, H
+ U# r& e+ D+ v8 P
/* Enable synchronization of RX and TX sections */
9 I& U4 k+ C& _8 F0 Z# v2 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* H7 X" Y6 }! d& p1 T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% b9 X0 E1 F7 x2 g: `( T7 N yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 m! M2 ]; }, I+ C6 v' Z** Set the serializers, Currently only one serializer is set as! Z9 ?* c* i9 G7 W' k G
** transmitter and one serializer as receiver.
, h3 {: |3 b! u9 ?7 e% w8 U- _*/
8 Z7 q1 H. C; f) |6 C0 ~0 S; rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 j# m( ?- r) f5 o# t6 R y% U7 A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 c, k k8 f# ]8 Z** Configure the McASP pins
* d, e% m; g2 `9 p" p9 q4 ]! F** Input - Frame Sync, Clock and Serializer Rx8 q# B" W$ m" y" U
** Output - Serializer Tx is connected to the input of the codec
+ @0 }! e' I8 E; [: m: b1 T*/; ] g/ s; M, `% I$ O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& c: H" F; X6 P2 H: JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) @8 U; @9 c! uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, N' n/ S* @# T5 e. ~7 g! t: }| MCASP_PIN_ACLKX
R& {& N a( b3 U* J| MCASP_PIN_AHCLKX" }1 B! h8 ]+ q% {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ N. g [. I3 K; g% uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# J* _' U R4 @% {/ w| MCASP_TX_CLKFAIL
! r( J7 P+ z# \! S& k7 v3 o| MCASP_TX_SYNCERROR
! I- {) M+ C1 v+ q$ c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 [ r U! D; s
| MCASP_RX_CLKFAIL
4 S5 U' C# ^- L5 G3 ^2 ?| MCASP_RX_SYNCERROR ) C! P1 t4 u2 q
| MCASP_RX_OVERRUN);
5 _7 m$ |6 @7 Y! Z2 w} static void I2SDataTxRxActivate(void)
: }1 o- s7 e3 K) ^$ ^{
: w0 b8 v7 ]& j4 [( f1 Z/ W/* Start the clocks */+ ^$ n/ u$ O0 @7 k2 i/ K" Y6 C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 w, x/ s, H1 ~: R0 @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ N, ^% ^8 { _0 z1 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 `3 `& L" C- F: pEDMA3_TRIG_MODE_EVENT);
3 i5 e W* B. B$ k; mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 E$ @9 S9 t3 H+ Q9 N4 V$ {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" `+ M/ o! S' m4 [! m; [+ E9 [4 N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; P( Z- n( G) Q3 U& O# Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& E# y* k, D4 `9 [0 v `/ U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 l5 ~" L7 L5 U+ A( m2 Q4 n, X4 F/ Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; O: }( {8 K0 n4 h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ N1 S/ y8 \5 Q' c}
9 q) {$ N! e: d" q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / V9 U! U% u2 h+ B/ f
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