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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" H% d* M# H& C$ d0 \! @input mcasp_ahclkx,
, W( x9 T: F7 X( F- P, T5 t; w* ?input mcasp_aclkx,
h* g1 c0 V |5 r) @! c+ ^3 K" G/ Rinput axr0,
$ n/ j2 p+ ~1 j5 A( h4 ?1 L' S0 ^* k4 e
output mcasp_afsr,
6 g# p! {! j8 q! B* W9 Ooutput mcasp_ahclkr,0 }1 A) y. }4 l0 g! @8 W0 D
output mcasp_aclkr,
* p5 Y+ {( G: k( _output axr1,8 A/ r8 W' p. d" Q a1 ~
assign mcasp_afsr = mcasp_afsx;% v1 K1 H) i" \' b9 f
assign mcasp_aclkr = mcasp_aclkx;
& d9 W# r9 B. j( r; o( M5 Vassign mcasp_ahclkr = mcasp_ahclkx;7 f8 ]. a; }+ I9 j
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 M1 ]& f& l y5 ^5 X6 R8 Q
static void McASPI2SConfigure(void)
6 r; C4 i l# _. L! s{
8 g8 b3 ^ R8 P# BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 ^' N# D+ R: H) U1 @4 xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* t: Z/ {1 @# y! W- ^8 ~) L: S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, M! t% ^" S1 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 w; V7 B/ m* @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* p3 f; p1 s0 ?! E6 ^# o5 W
MCASP_RX_MODE_DMA);6 Q( `; f* N4 P* e6 k6 t$ @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' P+ O8 U2 b D4 g' |, n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 H, m% b! _. {, S) kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% f- I$ C7 |1 |2 H* ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) n' B! a/ ?* D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % E3 Y+ m0 E! K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 P8 w, u% m8 |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( i3 `- P4 E8 S2 Y( g& ~& I3 sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. R7 S; O. b$ i! GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 _: J/ P. V6 |
0x00, 0xFF); /* configure the clock for transmitter */9 k3 ^8 ^2 Q* o# Q$ F- o. M- D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ [. }) C S/ p6 d9 T; h9 j; C/ g2 cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' v, B* ?) G) N) `0 F; f( e$ TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& F2 ?) Q2 x- r: o2 K0x00, 0xFF);
$ c: G: B) {8 ^( O5 Z) p/ `; r- l
6 Y% Q' V w/ a7 T5 B/* Enable synchronization of RX and TX sections */
. }8 t& B2 d" Y- p( a' CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# h I c( l: @# e/ Q6 }% G9 {+ [) z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 W/ R7 ?8 @5 n7 H8 e8 M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 H/ f8 }4 h; v% @4 _# p+ w
** Set the serializers, Currently only one serializer is set as9 [2 |, P) v4 B j) B- U: W
** transmitter and one serializer as receiver.) r( V, H% s, x6 S$ \$ R
*/
% N& z R- [, I0 h) z4 H/ ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! z* b! }$ S$ P# Z" r# O/ A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, W2 _% a# l% D& m U2 V. y0 p** Configure the McASP pins
- O6 t7 S- [- G. \6 h$ D** Input - Frame Sync, Clock and Serializer Rx
: l, T$ o p. O- P4 o** Output - Serializer Tx is connected to the input of the codec
) B: s( j0 ~6 f*/
E9 c- k/ }6 p$ C3 cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. S q6 j: f/ a1 I0 XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: E ~: W+ e$ t9 k/ jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( }3 Y2 i5 P# {# h$ G( l$ h| MCASP_PIN_ACLKX; y& i* C" r+ s9 ^
| MCASP_PIN_AHCLKX( ?, e6 K L% m: @' H+ H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ g' S/ T- w0 m7 ~( b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! p: m' z- R8 P" z% ]/ r' F1 x7 Q, e| MCASP_TX_CLKFAIL 9 Q* l) {* v5 \; O8 n7 G
| MCASP_TX_SYNCERROR: u+ A+ ]$ H. m# M5 E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , A) ?# N1 g- j3 P- y7 B" T0 U
| MCASP_RX_CLKFAIL5 c: N% ]9 ^% e
| MCASP_RX_SYNCERROR $ L# l8 A% |8 J4 \5 l, C
| MCASP_RX_OVERRUN);
- H! L+ [' H1 o- U$ x# E2 c} static void I2SDataTxRxActivate(void)# v: |# M) {" n2 E
{7 g1 A$ k7 x6 E8 o
/* Start the clocks */
; ]4 W. }1 [) ^. ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* \) T% l4 ^# w3 k% w: f7 L1 {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- q8 @6 [- ~ f$ [6 o. g! t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' n6 F8 c' ]( s2 i% UEDMA3_TRIG_MODE_EVENT);7 L3 U6 J4 }7 n3 W# _+ ~+ R. U4 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / T. y0 U. S3 \) T" O u) }' I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, w# `) F$ R3 A2 h ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; x2 N; C) q" I! h# }5 f1 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" C( _6 j% k4 {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 `+ {9 c& Q$ `1 i; AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& F4 n% Q& _2 j3 a: L7 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 \% V# f/ `* ~: n4 e, g; e} ! c x% M2 Y- i; G2 }0 Q$ M) z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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