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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* I2 ]1 B$ q: E2 `1 }! X! j+ }input mcasp_ahclkx,9 z6 o0 u7 ^! h' t+ G) u4 j/ O' S3 v
input mcasp_aclkx,, _% X& o0 V c* q9 L
input axr0,, ]( b8 c& o: h) F u, {
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output mcasp_afsr,
# F0 M% C; }6 i. aoutput mcasp_ahclkr,
$ K7 V* `: o; Houtput mcasp_aclkr,
! T0 L, o' |! R" \. w" x' goutput axr1,
$ A& X5 Y6 f& h/ k assign mcasp_afsr = mcasp_afsx;
$ W& z1 @) K$ ]0 gassign mcasp_aclkr = mcasp_aclkx;
+ E5 s( l5 {8 h: L) m' Uassign mcasp_ahclkr = mcasp_ahclkx;
0 J3 o0 b, Y: Rassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 x; S) O3 r3 }0 r6 A
static void McASPI2SConfigure(void)
/ U0 l* u! n- P8 y! S; K# F{- ^9 R4 U- T0 G9 z0 f8 T$ e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' r8 Y' a& ^7 ]6 R# ?; k5 z1 Y7 NMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& z m- R" L9 R: g/ w7 M9 ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& V2 w. a" _4 }" g9 O+ Q! M7 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# R/ B' l$ g& O! J, f: rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 ]4 k* y) w4 R0 d9 BMCASP_RX_MODE_DMA);2 [5 X/ q- a2 B# A% l6 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ o" J1 U; A' ]9 T$ g6 Z8 c0 ?( lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& `* m" m' j! s8 _' \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. g' `/ U& C# g$ h) tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 ^! ^* a) L5 D2 h0 _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 d7 _- h) H. _1 M# `5 XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ \3 |! ]- e Y. GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 _; y0 N9 a7 a3 B8 O" ]7 O- a, ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 d( N: P5 i. W7 B/ B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& I1 {/ n7 V7 C" L# g, @( Q# w0x00, 0xFF); /* configure the clock for transmitter */
: \7 R- m [& Q, s8 z/ }( ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! J8 Q0 ]! p& E$ a- o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" B) }( z6 B+ ?) P3 S. W; X; ^% a' AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- I) U8 c1 x2 a$ {0x00, 0xFF);
3 }( D% j+ j; U3 f% r* J1 ]2 i9 h+ i
/* Enable synchronization of RX and TX sections */
5 g% V' H7 a" |' y3 F5 SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# G& _+ w$ `+ x' B6 j- R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ U9 O! g5 t7 \ k: b+ b' s5 e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 ]7 x+ k! ?+ [/ I# Z# d% C9 \** Set the serializers, Currently only one serializer is set as# ?# _) r9 K* f+ e" I. }9 y
** transmitter and one serializer as receiver.
t3 l( D1 C2 A+ v# {* u& u9 D( b*/
- L* h2 U/ B, \( h: A$ W+ _4 OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. f7 ], w) p* k6 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- S) k2 g M* \; a
** Configure the McASP pins
- o l5 W# }; l** Input - Frame Sync, Clock and Serializer Rx% o7 w. j) x5 V- O' r- `
** Output - Serializer Tx is connected to the input of the codec 5 H" p8 @ _& K1 ]' `
*/! @3 t+ j, \5 u& N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 ^5 |3 W3 E) i3 I+ h3 e+ `% SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% ?" r* ]0 x; x- }' M9 {. }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. ~( Z5 H2 L2 D' `1 C6 q" a| MCASP_PIN_ACLKX
7 N5 ?' c. M: b/ P7 \6 c& i| MCASP_PIN_AHCLKX
. {, B: W7 l% [. O/ F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! e6 n1 a( ~' S) s7 {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 M6 D2 _! o0 E
| MCASP_TX_CLKFAIL
* _( N1 Q' Z9 e7 V$ Y5 U' E| MCASP_TX_SYNCERROR
2 K$ G# |& @) K; h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 H' O$ Y t! O
| MCASP_RX_CLKFAIL8 j! z' @* T+ }4 H& I( E6 f7 l, S& q
| MCASP_RX_SYNCERROR
; Y/ |( Z+ w4 b2 ^( c| MCASP_RX_OVERRUN);
* Z) I! J4 u. {1 O4 H1 z! h4 x, o} static void I2SDataTxRxActivate(void)
( P& }7 z" T, k( h{
) z2 k$ \, f' [: p/* Start the clocks */- x+ ?, i' T/ b) @! X0 C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: t: j7 \! K$ S2 r9 `- i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% l0 h, {( [% e: r+ @$ CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 U) u5 V9 H* w8 @: j7 ]/ _2 Z
EDMA3_TRIG_MODE_EVENT);3 d t$ A+ z$ o8 L& a3 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, z! k! i' Z+ I. f8 w7 l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 z9 o7 ]8 w) l3 z3 \" J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 ~- n; v: `- n( g+ hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) n% | M7 Y' T# E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* I/ C% e) S+ E6 \* c0 E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 u: Y% E5 f* c+ N& N& r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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