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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! K I& m1 V; N Q9 {input mcasp_ahclkx,' _% q0 \ H2 W+ e( n$ P1 G) g
input mcasp_aclkx,3 z |4 h9 E1 E1 i' F
input axr0,
! G: ^9 Q( I- {+ |3 k7 D5 o9 u( z4 D+ C; o
output mcasp_afsr,
/ B" }% S. N$ ], g" routput mcasp_ahclkr,
0 I8 M' E9 |. i2 ]' c* g9 {output mcasp_aclkr,
6 w: }% a/ ?1 D" w: ^- u! Poutput axr1,- L+ Q' h- _. q. r; I
assign mcasp_afsr = mcasp_afsx;
. p/ F- X1 k; M4 Dassign mcasp_aclkr = mcasp_aclkx;
. ]/ Y+ _" ?) E# Y* C2 lassign mcasp_ahclkr = mcasp_ahclkx;. z3 J6 Z& ^$ a
assign axr1 = axr0; j3 k4 M2 V( M' u8 |
) W% T% B4 J" _# G- R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ W* \- i% P) a
static void McASPI2SConfigure(void)
1 V; ` M5 J. w0 m- a5 [{+ K, e* i7 R1 N1 e% [) L# t d3 \
McASPRxReset(SOC_MCASP_0_CTRL_REGS); u0 \$ S! x/ J" ?( Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. X6 U: k N6 u, [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# F5 X8 g" [( \1 G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ \6 t8 _9 k8 a3 O+ ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* n" B' r8 O* f# M! t# BMCASP_RX_MODE_DMA);
; B8 z0 I( H9 IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' c0 T2 J- P) dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" b4 w- o7 L* Z0 N: PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: d$ E0 U9 F* h8 X8 V* u% b' f3 d7 \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& R2 a) D* N: u" o; p( \) ?# u GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : V+ N& b/ K9 W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! Q- }5 g7 a5 r( V6 d& z# A5 {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& U. l1 t; K2 u$ a; p; QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 F4 p( e, N: J# `, m/ w5 R. \! uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 m4 ~7 o* o4 i0 i4 ~9 ~) ]0x00, 0xFF); /* configure the clock for transmitter */. @9 j7 U+ B: K3 l {' U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 o2 o: ]3 x, D. f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- m3 F3 e5 A; y2 ?5 Y: V, ~4 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' @; F9 D( o. X5 S0 y( |
0x00, 0xFF);
$ G5 }1 w% V( ?. y( ^. Q1 X
7 t. u, E. x U$ P: N* L9 i/* Enable synchronization of RX and TX sections */ 4 H1 g% D" C: ~$ ~) U; t. H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
Y3 v" u, s# r0 l! [, QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, k, h: t; p- R; s2 @7 H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 ^$ ~( [6 b( I/ K# F
** Set the serializers, Currently only one serializer is set as4 H, |& n; l5 x$ u- w; H
** transmitter and one serializer as receiver.+ }+ K+ C/ S9 ~8 |
*/8 X# O% H8 i7 J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; d! w5 R/ e" a, ]( j3 s1 z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
d! p B5 h! i: Z% y& Z1 g& V J** Configure the McASP pins
( b, o$ I$ J4 `& O& E** Input - Frame Sync, Clock and Serializer Rx( [* @9 _4 z6 N4 N6 O# c
** Output - Serializer Tx is connected to the input of the codec 9 s$ ?6 ~) [: G: f) w
*/
2 r+ z" N1 u. d( h( H% T! RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: V* Z4 k8 C2 E& f, T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" Q$ o( v+ W. ?3 L" `/ Z, ]6 c) H- ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- t' z; i1 i+ i# v) ?- O6 a$ s8 A| MCASP_PIN_ACLKX
5 z. z7 t1 F7 I) @ Y# X| MCASP_PIN_AHCLKX2 D a1 l- m2 z C( {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 T1 M* s; h8 ]! E6 Q d+ Q5 i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 x( ?# D' Y+ d7 O ?; R& }| MCASP_TX_CLKFAIL * G/ R7 A$ ^! w* H8 x
| MCASP_TX_SYNCERROR2 H& r' o! N! c1 Q; [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 f: {$ k6 Q( W' j# l9 x5 @3 Z' D/ Q+ W
| MCASP_RX_CLKFAIL" o% A1 P! i7 ~, I9 D' [
| MCASP_RX_SYNCERROR ! {3 ^+ A; e" B" `; t
| MCASP_RX_OVERRUN);9 M3 u" `# X/ X/ {2 A0 ?
} static void I2SDataTxRxActivate(void)
4 m$ R- ]% R/ i: A% ?{" H9 x( O) \ b1 u' p2 {3 _
/* Start the clocks */
) }# N& W5 U) W6 m1 h- ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 V5 R9 N% G3 T4 k6 Q7 P4 Y5 K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// C M" [( ? V: F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 N# C+ H. U: |+ V2 M# N. P
EDMA3_TRIG_MODE_EVENT);
. b, S* Y( z, ~. `) k# ?7 I, E2 pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & D! C% c" F8 z, Q: R! v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ X! h/ G- O* n! y- J0 O% ?9 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( H7 j' [5 i" J" L+ r: p+ V# Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" ~- q6 r! r+ l7 Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 x ^2 a9 M' |* E3 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! h& K% F0 u5 J- m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 A, x+ v. E$ B. K. \: }$ v8 i}
2 `5 `" ]( l, N3 |6 `1 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 ~' {. m& j: J1 L
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