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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, k& e4 \( C. d7 q* c7 Y# J. O; r* Winput mcasp_ahclkx,
5 e' K, r+ A/ q" H' P$ j) ninput mcasp_aclkx," S' Q1 P9 W q) ~2 e2 ~8 k
input axr0,* f- F: f" t7 w6 i- x) y" r
6 E# T5 P# w5 ?
output mcasp_afsr,
& U: @7 X8 m- z+ N" s6 Boutput mcasp_ahclkr,
' \" l9 r+ I7 N4 noutput mcasp_aclkr,4 m% {+ |6 X1 z, m+ R7 E, g W
output axr1,
5 N' ?: n# p. I5 C assign mcasp_afsr = mcasp_afsx;
. H% i* A3 |4 g, c+ tassign mcasp_aclkr = mcasp_aclkx;# E- q+ c4 k3 E0 S4 @! T
assign mcasp_ahclkr = mcasp_ahclkx;0 ?6 P4 c( ^, A2 R0 j0 L
assign axr1 = axr0; " S, F O4 K, ]/ A8 \' U
/ w( R6 z) l' U' G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 ^/ c3 U% u# E1 B+ K/ \/ V- ?
static void McASPI2SConfigure(void)* ?! T) d( f9 y5 k6 j2 S l; n
{
2 v6 |% k; c* N# V y* Q3 RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ r& I( q9 t% F3 e% p% K7 J/ eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 ]* z0 ~9 V2 G& ?1 A- v' I' J" u/ R! x( RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: N! A# e e4 i0 aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- b- O8 G) F! X; [. I/ E1 j% Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 J8 e/ `+ r- ]MCASP_RX_MODE_DMA);
: x2 b8 J6 x) L, s* w4 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 T' z/ K$ F n# I& x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
}% _# F7 g" G" ~2 O7 f. V# D. EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 z$ e' p2 v3 o- q/ Z: r9 sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% H- r5 c1 K- y% m* U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 V8 I: T4 J/ |( ]$ G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# j e R2 w) K- F7 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ K; i% A4 o. {6 r5 J6 H; zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* ^/ `. e; Y0 o7 n" c, g5 {& YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 a% [* Z/ _% r% v' t8 @
0x00, 0xFF); /* configure the clock for transmitter */5 I( ]! H3 s/ m* J! i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 Y+ @2 i" e8 ~" H* h4 p* }; J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); u, ]; Z8 R. v# H6 V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' n. [$ L7 v$ M7 |* i
0x00, 0xFF);
: i) j, D4 T1 `; u5 E9 s" t# X: x( S5 S
g: {8 r. J: ~) T5 l9 R/* Enable synchronization of RX and TX sections */ 9 x# Z& e" r& H- ]) u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( X7 ~" y* V- o0 Q) UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ ?- j8 o% M' }, D3 s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 ?( S3 o4 t" ~
** Set the serializers, Currently only one serializer is set as% p! c2 _- @2 r8 W
** transmitter and one serializer as receiver.
* G1 Z! _5 q0 j' A1 Y*/' i2 f1 h. h/ L5 D4 G) l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); C3 A* m* d" L% Q& ~! m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ Y1 E% Z! A/ g' V** Configure the McASP pins & Z' ~" P: u" O: P2 z) p- w1 V
** Input - Frame Sync, Clock and Serializer Rx
7 {6 u/ R V5 T6 p6 q** Output - Serializer Tx is connected to the input of the codec
& ?% M3 h! V! Q# c. ]' v*/
- o$ l, I6 H! k% PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ d" w2 Q+ X% o! c/ Z" [. _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 P6 Y. T9 F0 l0 n( SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ \- c+ f. @6 P+ p: k| MCASP_PIN_ACLKX, j4 L- Q! g% U+ C1 w6 w; a
| MCASP_PIN_AHCLKX
! o9 P. l2 N1 n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 S2 w4 P$ @- uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ h) q& R! W& h# F: {- {| MCASP_TX_CLKFAIL ( g7 ]; }+ n$ L7 D
| MCASP_TX_SYNCERROR5 x, W. V K1 b& |2 A9 P M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / A* l+ l" G( P, E
| MCASP_RX_CLKFAIL" `* W3 G$ v: W. M8 `7 H& Z
| MCASP_RX_SYNCERROR ' S' ]; h! r; I) k+ S
| MCASP_RX_OVERRUN);1 g" {6 A1 Y0 i; o+ X' @
} static void I2SDataTxRxActivate(void)! W- r3 s( [& ^3 I& ~5 q1 L9 I, V
{
0 J& ]* ~! V, K( l5 h" D/* Start the clocks */. ?; y) z- z9 x* B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, l9 \1 \" J0 }. {+ S! d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 [2 A- ^) b/ c' X# l2 A3 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 O+ F1 F& g j% w! @) I5 vEDMA3_TRIG_MODE_EVENT);" A; j* b, \1 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 N! R8 R6 Z( G. @$ E# n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% u! N# m( B; N# x$ Y, b. m9 Y4 N9 JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: `( K% G4 w% R+ _* A. c$ m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 N& S4 e' i9 o" V# owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 f% y( g0 j/ z, hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 H, F7 N7 n e! u; y# kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* B, u1 Q6 [/ j0 g} 0 }. r) W' p5 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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