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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, b& a# F+ R1 x9 Dinput mcasp_ahclkx,
- J- S! v/ ~% a- w) t, Z. n" Linput mcasp_aclkx,7 K6 I& X. s; G2 F2 ?0 w) i
input axr0,! I- L: v7 K( d+ y
- h& X8 o/ Z9 P9 {! ^. U
output mcasp_afsr,# ^0 ^0 v$ L- W' O2 L
output mcasp_ahclkr,
# ^& O1 C6 M X7 `0 o3 a' Voutput mcasp_aclkr,
6 Q8 f9 e7 a5 G( \3 J* X' @output axr1,- A1 q1 X3 k3 d3 a' e8 V$ [
assign mcasp_afsr = mcasp_afsx;
. b% `6 U+ U2 V# Q" U: w* Z: l7 n" bassign mcasp_aclkr = mcasp_aclkx;4 }) h# E: N+ q4 m; `, v6 i+ Q, c! X
assign mcasp_ahclkr = mcasp_ahclkx;' r9 _/ O% M% q, x: s/ V
assign axr1 = axr0; W* V! L. d6 j6 D
6 K( B" O" i0 w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ |& o3 N1 q) Y& bstatic void McASPI2SConfigure(void)# j1 _& |9 {+ n. b- V/ o3 _- v: \) K
{8 \3 m) Y+ l1 r( U' d! [0 [/ F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* Z1 E+ j1 G4 u/ x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" x' ~; `' l$ s" \ A/ D dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# Z* w1 T8 S/ J1 |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 T+ Y) K" l: d0 |, R% o. `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 @; W5 Y/ B! P) EMCASP_RX_MODE_DMA);
, r5 P; P( I6 n+ |/ x YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 _1 A- C4 z3 O& X! x# J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( b9 T _4 e3 I2 ~) b: @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ {& D- Q, h1 B& z4 K) `1 n$ H/ D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' H4 {) Q& H* ^; _6 e+ CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 l; H0 Z, E" U5 m' N" MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' }+ U/ f ^: @. k3 m' kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 i% q. a) H& g3 U( L% ~3 j* ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * T7 I" {( _& M% d3 F; r5 P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( t/ ^6 c8 n5 C, Z+ B3 o
0x00, 0xFF); /* configure the clock for transmitter */% k8 b4 J% \, W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 x, ?* y( U$ k L) J- { e" A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % ~7 ^7 [& x+ s/ n2 m% Y4 g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 I9 r: f+ |9 L' v r# t/ j) c4 \& _
0x00, 0xFF);
6 t1 i4 D' a" k1 j( h" e: T1 k( X: l% g, g, t b3 E3 M* l% Z
/* Enable synchronization of RX and TX sections */ 2 S) \& T1 P: q' m |3 l, h0 x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% [6 Q7 P. V9 _' s: n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- Z" R+ \- Z- K; P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" |$ K, Y: d! H- W& b** Set the serializers, Currently only one serializer is set as/ s6 j% D7 R2 U, I* c) [( P" B
** transmitter and one serializer as receiver.
2 v2 V9 ]/ {9 Z' ^$ S: y*/
+ \9 C. y! l7 D) r( E* V7 l' K9 YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, W* j( X& r$ pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* j6 a9 P$ {8 h4 y- a, e1 y( n
** Configure the McASP pins $ M% g* Q6 |: D) P6 p U
** Input - Frame Sync, Clock and Serializer Rx
; U( Z% b$ C2 W$ j0 I$ M& h** Output - Serializer Tx is connected to the input of the codec 8 ]9 X2 @! a' k- e+ _: `
*/7 t1 s& \ V+ S+ c% s2 V- Q8 i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, f+ R* c( \* x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 R0 P6 Q/ _* k" _( S5 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ D+ t% K/ y# V2 T5 f, l8 U
| MCASP_PIN_ACLKX
# k( \' L% ]" I5 Y" f9 K( A| MCASP_PIN_AHCLKX3 N3 f& u! P" h' I1 T/ ~# R0 G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, r* x) U) x# c% n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & _8 a( `8 z* {
| MCASP_TX_CLKFAIL
% A( U$ z5 V/ x( U| MCASP_TX_SYNCERROR
9 ^5 u; V! \, R, u5 g$ k9 Q0 k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 K: _4 U4 p( |6 B& E4 m" L| MCASP_RX_CLKFAIL( r# m6 G/ v c
| MCASP_RX_SYNCERROR 6 p" w) E! D2 U T" u% n( G
| MCASP_RX_OVERRUN); ~ ^0 Y; H" ]
} static void I2SDataTxRxActivate(void)6 A. j; q9 F- L: U
{7 P1 T: ^1 `6 K, l0 X$ k: Z
/* Start the clocks */
% f" [/ y/ R( ?; q5 G- l$ m8 v7 _8 X1 tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, Q) Q- a- ^& g1 KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
m+ h& [# e; ^2 B0 w7 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 M2 ]8 |$ h8 b0 ~" [
EDMA3_TRIG_MODE_EVENT);
: ^2 z. Z+ B7 Q# V% S: X+ S' DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! L/ r" }/ a9 cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; [: j9 m2 T5 o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 ]2 p0 \! `0 p* rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: N9 R2 j( l- T M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 j: M6 ?9 x# |. ]' l6 `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 f1 ]$ Q U: f4 R) xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& E" ?$ {) F( U; a% B
}
7 z2 T( I8 R1 E: I/ t* {- p! a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + Y1 K" B- g2 v) y/ u
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