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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 J0 _: P2 v1 Y1 p
input mcasp_ahclkx,
! Z! M7 k# ?! `$ @0 hinput mcasp_aclkx,
! X. h ]. A7 ^$ a6 M$ Ainput axr0,. x; q* J. k, o( z7 f: u, F8 R7 m) s
) ]% O. P1 B3 ?2 V' i' x: \8 V E5 G. coutput mcasp_afsr,3 V! @) b( t7 y, C X1 a s
output mcasp_ahclkr,
) F& H5 c: ^9 Z- voutput mcasp_aclkr,
1 @, _ a& V; i! e% t. E, [7 ]output axr1,1 z0 q$ H" X% ~8 }! U
assign mcasp_afsr = mcasp_afsx;
% E: y6 q! j7 u3 b6 i8 t7 Rassign mcasp_aclkr = mcasp_aclkx;
6 [ b- {' o Q8 ^6 c- _( r0 rassign mcasp_ahclkr = mcasp_ahclkx;. l( y5 m k9 Q
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 P3 I @0 R, R5 v! zstatic void McASPI2SConfigure(void)
1 p6 G X" y& ^ N{
4 |! G% T3 C; U8 q! o' B$ HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 K: X, m* U6 i# m+ \2 U oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: z% G3 @6 I% }$ l2 U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- _. H2 A: c( J: \' M) K7 y( `2 s. ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 W2 v" l b/ L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; g+ C' N m7 L3 { x! a6 H {: }' Q& K
MCASP_RX_MODE_DMA);
6 _6 ?# |7 p% r8 ^% v6 L7 SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 |" v1 N' r) B. d+ v$ I. |5 r; gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' c) k, a2 z; O+ ^3 y, |! y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 g% x) F# y$ _) E3 C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; G8 _( n( s9 ~& i. V C% K7 J0 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . z" n3 D5 A5 n1 f. G. C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. D) f5 w/ i# b2 C# Q% d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: g9 b0 j7 d9 {$ SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % `; v* e& b- w6 m7 K6 L* T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ u: R- O, H1 l/ A1 k- n
0x00, 0xFF); /* configure the clock for transmitter */
P# W6 Y. h8 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# e7 A! F4 q! u7 Y, K) g. l9 S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & q, k% e7 F8 d/ l* Y) ]2 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 }# T3 L& a' l- }" w0x00, 0xFF);5 F& W1 S$ ]) j
2 R* e3 j9 O8 u/ s
/* Enable synchronization of RX and TX sections */
9 m$ v6 q. ^- p7 UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ z" }4 ^4 c+ W v8 }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ x0 r, o% A! V3 n- ]; f7 t( gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% N' e" [6 ]6 y- f8 E* w
** Set the serializers, Currently only one serializer is set as
" [$ b: {- d5 c9 U; |! p8 ]** transmitter and one serializer as receiver./ C& h& i* v7 j
*/9 O S7 y9 P6 I, t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: ~2 _; m7 ?( mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 E( Y! Y' @7 j2 ^4 B% Q& _" A
** Configure the McASP pins " n" h5 @- h" f+ S7 n
** Input - Frame Sync, Clock and Serializer Rx
$ c3 g1 g5 Y" C9 d; v5 L- \** Output - Serializer Tx is connected to the input of the codec
* p6 e( ?- \' Z3 r- \9 v, v*/5 {, S7 }$ I' C6 x2 _: @* Q% I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 S2 m( ]5 l; e+ E+ k! k. Z% |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. o; ^$ Z8 ?5 k( \4 PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 K/ k$ N, l7 Z/ J
| MCASP_PIN_ACLKX
( p5 j" c$ {& i- s( @; L| MCASP_PIN_AHCLKX
* {: v. x( O1 K0 v. E" W! D" w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ }' v4 j/ y& I8 P8 [# U; u; bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 p" G5 p/ W& }1 _9 N- r3 O
| MCASP_TX_CLKFAIL ' j) \* K0 J4 A
| MCASP_TX_SYNCERROR
5 w& r' D. X6 }& t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / V# @4 L& s* S" q
| MCASP_RX_CLKFAIL- h: u9 \- u' R; d. Q" x
| MCASP_RX_SYNCERROR + M4 C4 d. g0 i1 Q: e# h/ n& {
| MCASP_RX_OVERRUN);% k7 {- D5 Y( y7 p
} static void I2SDataTxRxActivate(void)
9 u! j$ w( h, W7 o{0 E- Y+ D t/ m7 Z l1 @
/* Start the clocks */
5 u6 `# J3 v3 Q. Z- I$ DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 K4 G, `: t4 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 E- w4 m4 L# B/ w, L0 f4 a) `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! C. d8 p. ?1 M' b8 \
EDMA3_TRIG_MODE_EVENT);' J; h( [$ K' q. o- V3 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 U* E' W4 n% ]8 e$ d, O; H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; S0 N2 D; _- P' _5 WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* t- B) H4 Y O/ P- A6 t2 s6 X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 W" g: `, o! J, j- p, s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' O& H( V: Z% W. LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 \$ O+ R4 Q7 Y4 r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 y+ x8 u% d; x. ]; U) }
}
3 c+ R& h! l$ i6 O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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