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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( f. c$ F) E D% D) T& Tinput mcasp_ahclkx,% A# J2 c: O! _5 x1 W; @2 ^
input mcasp_aclkx,& n/ n* P, S7 e# p# \/ {7 _
input axr0,8 p: N. n& N+ n3 R) ]( g# R
- o! Y; S N s x. n
output mcasp_afsr,
0 H k' o8 ^" w5 uoutput mcasp_ahclkr,( k9 V$ u( L2 }! i+ B) u
output mcasp_aclkr,& t& Y5 R4 @# [
output axr1,
, e0 q6 i5 j. a assign mcasp_afsr = mcasp_afsx;6 Z5 M& n. \8 U, S& ^+ w- _
assign mcasp_aclkr = mcasp_aclkx;
d U$ A4 Y9 U. _ k7 E: Oassign mcasp_ahclkr = mcasp_ahclkx;' s8 `3 [/ ?# t6 v0 X8 A
assign axr1 = axr0;
[8 }2 s5 M7 I7 ~/ y2 _% d: A0 x) ?! i5 {* t) h# o) h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % O" r: h" Q# {7 P& n
static void McASPI2SConfigure(void)4 u$ ]( z; t& }
{4 C/ O4 N4 I+ U# W( P& V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 S# o. Q1 e! N+ U* S5 YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 t: n0 w! T4 C1 D: e7 j* _ b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 |6 _+ Q0 d; C0 G6 U5 N" q" I5 UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 G- _8 f4 k3 M5 i" l: PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) L! U2 o& P0 d6 N" Y8 k- P, M: j
MCASP_RX_MODE_DMA);! h+ H: e# F ^2 s; e1 V7 q: V& h1 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- E: a" ^4 [ h! r# ~) p% l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 Z: }9 ?1 O9 e) P- A; E% ~) t# P* A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 u; Y, U Q/ J! A3 ~; Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% C2 J# D/ U% Z+ \4 O# ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 F2 {$ N5 \" R4 m6 N' H3 iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 |9 y. J/ k W: A& K! |! h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ M1 e8 J7 b7 |* S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . e. X( B! [" E, Q& h4 i o% n% Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# \. s2 g& C5 E {) @
0x00, 0xFF); /* configure the clock for transmitter */
8 x; g. I0 d, J% q4 e3 o$ j, M ?* bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. Y. d3 g) K3 F" C# UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! R1 p6 q# p+ h+ y' B0 _- b' d! H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# b+ A7 Q. p# h5 z0x00, 0xFF);
: v( g4 N$ J" a9 ]
3 }& R& C) m0 n& K' d( K/* Enable synchronization of RX and TX sections */
% u, A- a p% }+ L. vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. z& t$ |* l- `; o( H3 J+ y0 SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 ^* b0 f- O1 X: E! C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- _/ P" w( i1 ]! K1 K: o( ~
** Set the serializers, Currently only one serializer is set as
5 |' r" k7 w2 m5 C" C** transmitter and one serializer as receiver.# w2 L/ n/ ]8 {& W3 F2 h
*/
- D3 g/ J8 K7 B- _& pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) p `7 I7 |, p" u: M8 ?" e. w$ JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 w( {$ h* m- E5 j: \7 a
** Configure the McASP pins 7 ~; G* y% N4 F8 W7 h
** Input - Frame Sync, Clock and Serializer Rx
. t- @0 n# U6 |( d** Output - Serializer Tx is connected to the input of the codec % p; P c2 t9 b9 X, Y
*/
) @* g/ Y/ ` h4 ~& oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ y6 F; K$ c7 x) y+ b9 [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 m, p M2 i6 F& cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) I7 C( s f" ?) m+ W+ q' O/ O| MCASP_PIN_ACLKX" N. q' T K. s3 u4 O+ C& N% j
| MCASP_PIN_AHCLKX
$ y E% ?; N7 P$ T, ~2 m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, w# I( k) a+ d* ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 Y9 r3 j: L' L7 Q| MCASP_TX_CLKFAIL $ Y* F# c2 @! v/ U
| MCASP_TX_SYNCERROR
$ Y1 l( b: \# M4 v! d" |+ U# M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) [; v1 y- r- B# ^- h, K
| MCASP_RX_CLKFAIL
( E2 e4 F1 u# i5 U3 s| MCASP_RX_SYNCERROR ; x# ]: s# U/ ~5 b
| MCASP_RX_OVERRUN);
3 A5 ~, W2 G# m5 _} static void I2SDataTxRxActivate(void)( y) k8 v% p; c, U5 \4 e
{
. B$ I2 W6 c* j9 @/* Start the clocks */% m' y3 d% C/ m; d; u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! O. x; Z& m5 ~$ `/ L# l& }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) X2 r: j5 ~& H6 _) I3 {" G7 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; O# V" h6 C7 D
EDMA3_TRIG_MODE_EVENT);# v# J, n- C" Y6 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , R( ]7 w# Z1 C4 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! e3 B' v( @8 mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 g! g4 Z2 C$ b, ] e" s+ Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 p0 y& F1 {/ i4 W9 b3 U; k% rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 |/ P. o4 \& }+ x7 b% ]8 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. b2 x8 o6 k4 i+ F/ Y0 B# v! Q9 vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ a, R. Y: a. z# h5 n
}
6 x/ S3 g, t0 i' `! Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # N+ }% q$ x; Q) j
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