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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 h/ A* O# a8 p) a$ uinput mcasp_ahclkx,
! A& R3 e# I5 L% `input mcasp_aclkx,4 \' y! K% K* M" J' I
input axr0,4 G, f" E5 [- y3 _1 b
/ R- g6 w7 P i$ R7 \' Eoutput mcasp_afsr,* E: Q5 w% W8 `# {! w
output mcasp_ahclkr,
* q6 s! N# U4 z1 xoutput mcasp_aclkr,' y# s+ C( N; ^7 C
output axr1,
" A2 K0 b+ x! S$ D assign mcasp_afsr = mcasp_afsx;
* G3 A, d+ |- a7 u- S- o- b- Dassign mcasp_aclkr = mcasp_aclkx;4 N: l0 i& x3 \ C4 y/ L$ r
assign mcasp_ahclkr = mcasp_ahclkx;
. g" B7 N* L e) v+ Uassign axr1 = axr0; 2 I* q0 `: ]. b
( l2 K& a0 p( n4 k3 s0 o4 Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 F8 r3 z0 Q' l( o! {static void McASPI2SConfigure(void)
4 \. _* J5 W, S& \7 i{
8 ~% N% z: a0 O6 G9 jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! F7 h& }& N! d9 y' S! g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) |2 A0 H' S7 a3 T7 P) [. k8 H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) n: D- r% R1 d& J0 O2 O8 MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% p$ Q' P3 Y' T2 t+ H9 p6 G/ p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( P( ^9 \4 ^- gMCASP_RX_MODE_DMA);
) \% l$ R* p; nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; Y" L, j; U6 _" KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" w3 v7 [) J' x! \; `# v+ lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; Y& i% Y( u# F: i4 A2 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- t Y; V, w; fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 v0 v+ m; p/ x9 A- k! Y6 j4 c% gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& p0 ]2 T5 q1 \3 N4 EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 R" E9 ]2 R. y/ H1 Q. V) D& E% T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 A" ]' _; K) `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 d' y7 u6 g2 ?( E: Z! i0x00, 0xFF); /* configure the clock for transmitter */- o1 n% ?7 \' p! Q$ r& _9 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* s; v2 c( u: u# z/ Z3 b( [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . U! y4 N, ?7 ~7 A) F+ c; e; z, {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# S* K3 w& @, f! v, u' ]
0x00, 0xFF);
" s9 `1 B" j D1 S' A
9 i v* J9 j" c8 N5 a6 e- C4 e$ t/* Enable synchronization of RX and TX sections */
( }1 M9 a" v$ q. q$ \8 ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ v' V2 f: ~0 @: q2 }' R: B, EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 V' T6 I9 [6 _: [! B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 k# j: d. J3 r4 C8 O ]. W3 p! |$ A+ r
** Set the serializers, Currently only one serializer is set as
' @5 g2 ~+ P5 R J7 z# S- W( y7 G8 b** transmitter and one serializer as receiver.6 U* x3 H4 K4 T+ _
*/
! G, J0 g' f% o& P7 F0 d' XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ b8 n% w4 B4 {6 v% `: h
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 r- h3 J* n2 L% d% x! o4 [
** Configure the McASP pins 2 a# |" c! m+ w2 o$ b9 S! W( c
** Input - Frame Sync, Clock and Serializer Rx
6 L# D8 w5 i7 @/ K+ j** Output - Serializer Tx is connected to the input of the codec + r% z5 e6 @( ~! }' A1 W
*/" B m) }4 j, i, @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, u) s) N4 g& V$ ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# U; {) c7 B- j& Y# ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 M- f. _7 g& X| MCASP_PIN_ACLKX
9 N' I& T5 l& I) w# {# e| MCASP_PIN_AHCLKX
1 i0 q0 |3 q( A8 w. e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
W: E1 w$ N) gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ V/ H+ r7 p% R3 F5 g5 Y6 B. }9 J2 B| MCASP_TX_CLKFAIL 5 T: |/ u3 r# C& m; W+ K* U
| MCASP_TX_SYNCERROR2 n" f. V, M! B. U* {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 y8 \# l) `. b9 M4 u: x| MCASP_RX_CLKFAIL
" J k g4 c1 Y( t| MCASP_RX_SYNCERROR
7 d' U5 K' f5 o( h/ @; p# V| MCASP_RX_OVERRUN);
3 N l4 g, l8 E. `' V3 ]$ {, L$ k} static void I2SDataTxRxActivate(void)
2 z1 g* C" ]! f; t: Q' k; M; Q( Z/ P{
9 E7 B8 _" f8 I( ^( x8 j# Q3 N% N/* Start the clocks */
; K& X+ K, N) |" E0 [& s/ vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( f+ @0 C; |, i( [! H8 kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) J% w! L5 N) c0 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ ^# j; X6 p4 H. i& g6 y
EDMA3_TRIG_MODE_EVENT);
$ F! g, y' p% SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 a& s2 h" ], z2 z1 |/ X# dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& g5 D8 X7 C d- ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 C" J) h+ _1 v* B; T7 S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. W8 s0 w0 V! ~( xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- D' h2 L' }# V5 F# M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ c0 W& ?4 G% l: uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ ~) i) X, X' H* p# r" V
} 2 C5 N4 N; l/ I+ S8 j2 n# U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
8 [: `+ X2 a1 f" Q) a( J |