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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 D* N# F1 }# T8 W
input mcasp_ahclkx,
2 _( n7 e2 h! y8 j9 \* J% \input mcasp_aclkx,' ^2 z' a: l% Z; G4 u
input axr0,+ c6 M7 m- ~+ F) E5 K8 K1 r9 ~" U
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output mcasp_afsr,; h5 i- P" R" w# y( B
output mcasp_ahclkr,( F6 a/ j- t, F9 m3 E0 l8 h
output mcasp_aclkr,
; s+ Q! K7 E( U+ L9 x( O6 G% goutput axr1,
- Q9 s( r7 g. z5 v assign mcasp_afsr = mcasp_afsx;, }1 W& e! i+ R: _6 u. a
assign mcasp_aclkr = mcasp_aclkx;
. ?; h6 `( b2 ]assign mcasp_ahclkr = mcasp_ahclkx;# R! E0 }7 h5 w3 c6 D3 J
assign axr1 = axr0; + I# ~/ o( z: c1 {1 z5 h
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " J( u4 P- W: o! g( W6 i# g( M
static void McASPI2SConfigure(void)
# K+ d4 J6 K4 O0 R& n2 H+ y, C/ r{
( z1 T7 x" m7 @3 zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 Z4 c$ E; D6 [4 e- F. s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! C4 b5 ~7 m! G$ KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 x2 x: h$ ?9 L3 m& [# s& l) X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" d6 {- Q4 g7 s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ~% d$ ? q+ H' r$ ]0 D* N* [MCASP_RX_MODE_DMA);& R, k; _" c5 j4 [- ~8 r* @! J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
\9 D! f8 l7 Y4 W6 LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* A# i4 E0 ^& N; y. C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - M( c. S& q+ b& X7 G- o: N& j! k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ o! @) d2 G% n& v6 J9 W3 j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 q2 P9 }* b3 u/ Y+ T, z) r' DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: D. {" k! @6 h: m9 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
Q, v1 q/ M/ lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . U* ^6 A, u% m4 l: B S( {3 u( D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 e/ `1 ]& A9 J5 O/ v0x00, 0xFF); /* configure the clock for transmitter */8 y9 X0 ^% x6 ~# `1 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; E9 L% b* B3 z6 G z5 }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : M) [: ]/ k% J: ?* g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ v& G: @; y+ p* r8 S& y$ @( l; w' C0x00, 0xFF);$ a5 q/ F7 \2 }! ]( o% H2 J
) Z& \; O& m# K# o4 y4 P- [% P
/* Enable synchronization of RX and TX sections */ 1 Y6 Z/ y w( v& d5 Z# M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 R1 y) O' i0 A1 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& F7 R0 O/ g8 ^6 H& d6 g# t- {, _- b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 Z( K) O/ R0 R" ?5 s** Set the serializers, Currently only one serializer is set as6 w/ Y L- A6 D, C# j! a! [
** transmitter and one serializer as receiver.
# \4 j" g( f5 s+ z% y7 y*/
& n# B p" b6 b( |/ H' z1 @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. s, M( U; C+ ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. Z& a, j# \9 Y% @$ n Z9 ^$ B* Q
** Configure the McASP pins ; K5 L! q" |; v
** Input - Frame Sync, Clock and Serializer Rx
1 i& ` }5 r0 V! p/ K% ]** Output - Serializer Tx is connected to the input of the codec
4 _ D- \ f# C3 s Y# W*/
]$ ?+ Z. U$ ~4 S& H9 hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; f( G# G& ] Z1 I/ ~1 e$ `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. |. _! W, {* a% P% P% {: Z$ aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX ^+ E! k: ]4 ?; M, ^$ j3 h* z
| MCASP_PIN_ACLKX
) h) b' T( G% f* T3 o0 z| MCASP_PIN_AHCLKX& o8 O2 a0 L9 P9 y2 q$ x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ b* F% i& R' R+ ?# \( g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 h" m% O z* U0 u. a
| MCASP_TX_CLKFAIL ; ~" @) {/ T& S9 \/ e
| MCASP_TX_SYNCERROR
% p0 N! z3 j; R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + e- M) t- {9 _3 _% p
| MCASP_RX_CLKFAIL
( g) S6 H# m1 S6 y3 |: y| MCASP_RX_SYNCERROR
3 \- ?+ S+ S2 B, K# {: U+ u+ p| MCASP_RX_OVERRUN);
7 \: n1 K5 `- W1 Y} static void I2SDataTxRxActivate(void): C* e, E Z5 }: O
{
: m9 a! t: c, z! J5 X/ K! A8 w/* Start the clocks */
. r4 S2 C# E4 e9 j5 `) PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ D4 }1 ?$ y8 ~0 W/ K- _+ I* C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* L! O8 Z1 V( \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 s, f" W9 w) S' x( }
EDMA3_TRIG_MODE_EVENT); [% E+ I, I4 X8 w8 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! K/ e0 G1 c8 r# H0 B1 E5 f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 s- v7 j/ f- k1 L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- O4 Z0 D8 ?& D& S) }: r% a: @' lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: v7 B/ I% c" j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 Y1 a- [7 ?& s" P2 K/ W5 a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" a+ C& u! \# eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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