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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 N; F) a, h2 u2 ^, ]+ Winput mcasp_ahclkx,# G" |5 Q) Y6 C3 K I- ]* M& P, j
input mcasp_aclkx,
( f9 N" T G, c: q7 |& @( s* finput axr0,
. o, \- y7 b5 s2 q W F2 H
* B; }1 ]- Q0 Koutput mcasp_afsr,8 I& J) V* h1 C! }
output mcasp_ahclkr,
; d& J* A' \8 |. r% loutput mcasp_aclkr,
: {% ^5 F/ A6 q! ^( e! `output axr1,
5 \1 c( @1 }2 K A* U& P* u% k- d( L# [ assign mcasp_afsr = mcasp_afsx;9 |+ L* T: g9 v0 h( @
assign mcasp_aclkr = mcasp_aclkx;7 w4 {7 \* _& d: C. U. C
assign mcasp_ahclkr = mcasp_ahclkx;2 A5 [, U1 N! |( @6 a- M% g, m, P/ @
assign axr1 = axr0;
; X3 g. z! H- Y, @' t4 E. i3 P- W7 A2 T i2 y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 e! Y) o5 w4 f8 `4 Z1 w$ U4 Q
static void McASPI2SConfigure(void)
) g+ t. \! \- O2 G{7 f3 h" G) @) ^" R- ]" m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% h8 O* ~1 g1 u c6 A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, b* Q- h- b9 X& ], ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& ~1 X5 F# R* L' V+ k& W1 [ k" m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 y) f; [ k- V* \% m" m' [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 ^ u- A8 S7 R) d7 e, z
MCASP_RX_MODE_DMA);5 W0 ~% B. q$ O9 o c& V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ u, L+ U4 S: B. \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 g, ?# u# W* n" V1 [2 f$ T+ cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 G4 a% ^" @/ G- B1 p) |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" c- B" |) y# S7 `1 @6 V9 wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* u: z# K) r5 \9 y& X0 {7 W- d# z3 IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% J0 }- F* q$ S" }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. O: l$ Z8 [$ b* Y9 E2 cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( r7 V) V7 Z6 O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' F: b5 A& o$ p5 Q: g- y/ P
0x00, 0xFF); /* configure the clock for transmitter */
! C: z; j: c0 D/ O. kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! D9 J3 X9 W( b2 a9 ^. p; a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ k; E' ?5 {, Y- W: e; J# rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; a1 l- _* k8 Y# q4 L; q0x00, 0xFF);. [% X, n" |& \/ f- M$ ]; A) p9 K7 d1 ?
3 J) ]1 [+ W: ?7 L f/* Enable synchronization of RX and TX sections */
: D( ~6 t. z$ J" \' V. V4 |: rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 B0 ]/ G& r+ Y5 \" eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 W2 Q1 C+ h ] N2 ] e) z# q) Z% x9 `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 R+ @" E& W6 w% w** Set the serializers, Currently only one serializer is set as
8 u3 U: T1 N- C** transmitter and one serializer as receiver.
5 w4 H3 y' s8 l) o- f* Q) S*/
y! z2 o! B2 B/ Z6 G8 EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ I. \7 N$ U# L% }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 Y' l% U2 O8 a# o- m** Configure the McASP pins
* o; a( G5 j: U. u3 `3 f, f' c( C$ ?8 r+ P** Input - Frame Sync, Clock and Serializer Rx
3 r* F6 O. Z+ E6 F( c" G, Y1 D** Output - Serializer Tx is connected to the input of the codec ( W0 n. c. K3 r0 [
*/
1 i6 u% Q1 X; b+ f0 u4 DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 P. {( q9 O" x7 f5 d& zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' c8 X& g$ d- P& j3 g- H- sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 b$ ?2 K1 x @! g5 F- f5 t| MCASP_PIN_ACLKX5 Y- c8 g. x. H3 @; X
| MCASP_PIN_AHCLKX) o7 B) r8 J; D. v1 }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: G7 [1 X& g2 M' Y1 |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ A! Q& R' F- ~
| MCASP_TX_CLKFAIL 8 ~4 H" j T3 }2 O3 C m
| MCASP_TX_SYNCERROR* _' |: H" m6 c& a9 J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , \$ g" O9 {' \; @
| MCASP_RX_CLKFAIL* \5 `6 X8 C0 Q8 U. z
| MCASP_RX_SYNCERROR
+ |3 \2 c2 g" ~. x& @| MCASP_RX_OVERRUN);
) Z' a8 L7 ^- `' o* u! B} static void I2SDataTxRxActivate(void)
4 N+ Q) A# }* q{
( @9 {# x. q+ I1 [6 ^* }" a/* Start the clocks */
4 z( u1 @# H+ z+ [: K" G$ u# `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% Q( j9 k! J- a3 U$ B1 _" ?4 B9 l& [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% |6 F/ H: T, c5 K' T6 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, |& f" P7 W7 B/ m) `; W! Z( j
EDMA3_TRIG_MODE_EVENT);
0 N$ B& p# Z6 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % m5 r9 }5 W5 }/ ~; H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) `8 e8 s% L7 p+ eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" B4 `3 K9 ? p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ d/ \0 T4 I/ u% I) Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 H4 v- F O, E1 ~1 P2 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; @5 Z: ]( c& G9 s" CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: j* \; e( a9 S- W% Z
} 4 ?% E! u3 X6 W/ n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 G8 y, t1 D+ n& V/ z1 N
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