|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: g# h! v1 w! [- A3 X) v4 g: H& vinput mcasp_ahclkx,
0 T! P2 n0 z$ Cinput mcasp_aclkx,
% f- Y' o; M& Y( i& c5 F) sinput axr0,
2 x, K, d4 ~: j
' x" c$ o" G- aoutput mcasp_afsr,( J4 Z( i* Q3 W0 l0 U
output mcasp_ahclkr,
" }8 N1 J: v7 k, N7 u/ o Koutput mcasp_aclkr,
`, e8 C6 ]. B( boutput axr1,
4 b8 B. ]2 K0 D assign mcasp_afsr = mcasp_afsx;7 l* t* h" ^9 @3 j/ G+ C
assign mcasp_aclkr = mcasp_aclkx;
+ A0 D4 C+ {3 zassign mcasp_ahclkr = mcasp_ahclkx;4 X7 _0 h# W4 I: k
assign axr1 = axr0;
7 ~: [8 a( I) ]/ T+ o8 B9 B7 j3 n- o) }* |* \! i/ F2 E4 z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% F5 Q& w: u, Y" q, A* {: ]* U- vstatic void McASPI2SConfigure(void)* T+ p* }' B7 z/ p8 ]( d1 T
{" u) a, ^# L2 Q7 J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, h2 K0 C, `& E! B; E7 C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" P# A/ Q2 {: N2 ] q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* G4 l8 m, f+ g! ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& m F' a. {5 i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 k+ t; Z$ d/ e3 ]2 pMCASP_RX_MODE_DMA);9 p/ F+ z v3 E0 C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ G& I: E3 }# v+ q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 q$ r: w0 H4 a, D# X- m1 @2 hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 a- ` ?9 @: m/ N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- X1 t2 ~' C0 f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) ~/ E, B8 ^! T' `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 r7 c2 i) K! C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 o. ?) ?1 q1 s# f2 a* ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 c# V$ p; ?' p) l1 x# xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! ^9 D: k" ? R: i+ V5 d0x00, 0xFF); /* configure the clock for transmitter */1 P; n6 o; `( T# l9 [3 [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 T# N: c7 }& |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + y0 F0 i9 s: o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 }/ g0 B; E; p
0x00, 0xFF);1 K; k u) D0 h
- M7 f0 w8 X- w" G3 D
/* Enable synchronization of RX and TX sections */ # W8 ?: o) V6 \& J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 y$ g5 v/ ^9 C* [* A5 A% q, S; VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) Z/ [" R6 K' |; b% tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ K2 L* N' {9 O4 G! G5 u9 z
** Set the serializers, Currently only one serializer is set as
0 u% ]3 d% n+ [" i* `& D** transmitter and one serializer as receiver.+ M( B/ U" K# Q
*/
( j) M8 G t- ~# G' TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; ]- l0 h9 B6 G( TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' a- l( Q! S1 o6 a( n5 u9 L7 M** Configure the McASP pins
! e( H0 M; c2 y, R6 w k0 D0 z** Input - Frame Sync, Clock and Serializer Rx
' v+ J; O1 }6 b& \. c** Output - Serializer Tx is connected to the input of the codec ' m! Y5 m5 Z' R8 {
*/; n0 b2 V7 X: i' j8 X( ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: C/ l Q5 U q- |- l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( m3 {6 C- [$ u1 |4 Z: h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 F2 q. \0 v5 t( p8 z| MCASP_PIN_ACLKX/ h4 l( q/ T- v$ `+ Y* d
| MCASP_PIN_AHCLKX
r4 @# k9 T; c; u$ w0 S. p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 W9 C( }3 m/ Q) h3 q; I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! q2 H2 B5 s3 J1 L) w6 ?9 s
| MCASP_TX_CLKFAIL 6 k+ A" r5 v$ h8 b6 D6 _9 \
| MCASP_TX_SYNCERROR7 N* u( c* @6 g+ Y9 P/ u; `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 I) Q. e& l' T* Z! j# y
| MCASP_RX_CLKFAIL- s9 y/ u" b7 f# s# H" M5 p; R
| MCASP_RX_SYNCERROR [* M" V7 S+ _5 {7 G. h
| MCASP_RX_OVERRUN);
; [$ l. e6 |8 ~* y7 U h/ }0 o$ m} static void I2SDataTxRxActivate(void)8 t" Z" F4 T8 O! E% U1 f6 H
{, o' T* x/ O2 J$ i
/* Start the clocks */
: @7 f# ? t0 h" |8 m5 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) q) @# o) R( ^' w# X* Y3 {; S' f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ a8 d( a; B+ e, ~0 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! k& V* r9 z! @, ^7 HEDMA3_TRIG_MODE_EVENT);$ W7 d% m4 O- U6 t& S% x( S: Z/ q/ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' o) V' l2 i9 E1 V1 G: V3 F9 b3 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* Z s* P0 L$ @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 ~1 F* G: G- {" @, @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 k7 g( D d( n' Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" L, Y4 i. u# e C1 Q% {) r- hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ U* l/ C7 |, H6 g. x& Z+ c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 \! K# i: E; `}
+ a* r' i& b: H# q4 ]- }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) c( Y) X# \0 j- k$ v
|