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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& x8 F% X# N, t0 Q& B1 \input mcasp_ahclkx,8 \* B' G( a6 Q: M. h
input mcasp_aclkx,
; `/ u" J+ _! z0 X9 j3 t1 u8 Rinput axr0,
: x. J# ~! T' h3 \/ ?5 p: T# C1 R
* l8 I( e7 i5 Q* H( voutput mcasp_afsr,
* E9 y4 ~1 [6 d( J9 W4 u' }$ e6 ]output mcasp_ahclkr,
7 K, l' { z# F( r2 qoutput mcasp_aclkr,& G% P* L) D. ]4 p
output axr1,
5 _5 A1 Q' K0 [% d7 B( w& W2 k assign mcasp_afsr = mcasp_afsx;
1 q9 j* `- ?$ B# ~/ I2 U+ ?assign mcasp_aclkr = mcasp_aclkx;& w* g L; M/ Z+ V9 V1 K( n, H
assign mcasp_ahclkr = mcasp_ahclkx;
% n1 E, m C& c2 \assign axr1 = axr0; 3 p) h/ R# l r- ?8 C
1 z/ R: I. V! k0 F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - q" Z4 v2 n) T' }+ x+ F3 q6 R
static void McASPI2SConfigure(void)
" O( t) W5 Q2 [{
X) K5 q- z( m, N: GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 r8 j) m* W% f3 |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ q+ T: B: Q' HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 Q7 m8 u9 h& @2 `0 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 s- @) O' U I( |+ Z! xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 u, s& {/ {2 W9 `* z2 J- n
MCASP_RX_MODE_DMA);6 U' F9 Q) q) g# n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 e6 q; [! U* m1 ~* DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) U; r( @( ?2 O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! ^: w6 @! s$ Y- FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, q; o% h! f9 W1 L$ s. XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( g# q5 P0 N# I# y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; c+ f7 w4 [7 }; L0 J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! V6 j2 [ m* l/ {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 |$ ^% [ V. Z" l5 B+ [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- Z: ]! ^$ [ M& x- Y0x00, 0xFF); /* configure the clock for transmitter */
* _1 r5 _; @6 l* v) \5 YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 m) S/ }/ r, i1 O! EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & u' l- |' l: J* U6 G' B9 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 T/ E* t, M' }& D( T- ^' z, R0x00, 0xFF);
: D% U% S0 S. R o" w" ]& v7 d/ p- n$ @& O% m6 V
/* Enable synchronization of RX and TX sections */
- B Q! B) x: n W5 i" IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& h& Q' J; X, |! Y1 T( q2 J+ ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 C7 r$ ^9 t4 t9 R6 z- ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) ] G0 P) j2 b2 _8 T1 y** Set the serializers, Currently only one serializer is set as! e7 J U- {' k7 [. m" p! S
** transmitter and one serializer as receiver.# G/ t$ J5 O2 W- w
*/8 k4 x9 N- m" `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. E) I M3 F" R( y# \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, J2 d. l3 c5 ]* [# E# K! v** Configure the McASP pins
( F7 w4 [ x; i0 T** Input - Frame Sync, Clock and Serializer Rx( H* i' b+ _$ Z$ \8 l, l
** Output - Serializer Tx is connected to the input of the codec
( L- v+ d" ]3 A- ^2 }" P*/" ?& Y4 M# ^$ c% s- Q4 Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( e. b! P m( }; z6 d# j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' b. t4 ^8 j8 f( c0 wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ [ Z2 ~ l I; T2 |3 K' z8 L
| MCASP_PIN_ACLKX# c8 M' |- g( ? n h
| MCASP_PIN_AHCLKX8 c* b6 n. g9 J" g) U0 |4 l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 z) U7 w, ] \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % b9 Z( i. P: u2 P
| MCASP_TX_CLKFAIL 6 M! c& `9 _, Q$ B5 q6 q
| MCASP_TX_SYNCERROR0 Q' h! a& L ?1 t/ e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 k; m$ [$ b! v' d| MCASP_RX_CLKFAIL1 D' q8 u# }- S. L. k" h
| MCASP_RX_SYNCERROR
3 _4 P3 p$ D2 G6 ~. I+ \| MCASP_RX_OVERRUN);# B1 [* W9 e. I! d$ `4 ^7 c+ I
} static void I2SDataTxRxActivate(void)2 q8 K. N, K/ ]/ B: o: k4 D. s e
{' n8 R1 j# j8 Z. Q$ c
/* Start the clocks */
1 o9 Q$ i. M; j+ C$ aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ B. W/ S3 }! f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ k1 ]8 |* ^0 R: s6 R# A9 v. `8 u, wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 |& q& o; l4 |0 sEDMA3_TRIG_MODE_EVENT);
8 y$ R- Y$ v2 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 z; O! l! P- x. P7 l9 l9 p8 I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 C, Q9 I# p, x9 Y; oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" C) G! ]* h, \1 v2 d) m \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 r5 M: T! ~4 O. Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. `7 x; U6 y: v: L# EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" B3 u, ~" v! \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" m; R7 B: a1 h) V6 U+ V
} - R l2 C9 V/ g2 ^- f7 l* {. i/ D2 h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' a1 G/ C4 }/ J! e' [% Q
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