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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& t# X! j+ e5 u" y ^2 h v
input mcasp_ahclkx,
, X! i1 r6 c. h5 Pinput mcasp_aclkx,# v( f6 d! v. G
input axr0,
2 e+ G8 ^; v3 _3 l T3 {/ T: V* y& ~+ K! t! q8 M3 _/ z8 S5 @3 U
output mcasp_afsr,: W8 p- K* y9 R' l, @
output mcasp_ahclkr,0 _2 J" V3 `/ K' X
output mcasp_aclkr,
; k) s4 H$ E, P# D2 _( ooutput axr1,
6 L* T0 g p! e7 [: x assign mcasp_afsr = mcasp_afsx;& C' V8 S; Q6 X2 k- r" h0 f
assign mcasp_aclkr = mcasp_aclkx;
! l, l( i6 ?* c4 C2 S9 Q1 Gassign mcasp_ahclkr = mcasp_ahclkx;
& D- p, F- W. {5 `assign axr1 = axr0;
; L: h/ }& N& X& \- O: P
H9 p t$ s6 e, ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 ~; K+ X( F; Ostatic void McASPI2SConfigure(void)8 K" r z$ T$ A
{* x h! g4 u4 B$ l- s0 R# M! `* q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ r. R, K) _9 S0 k% b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. A* j! [) T+ T2 }" k* |: }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) y& u; {" s/ A0 o" b" P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: ?6 s( x' j0 p4 T+ H, U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 r; W% O: h& B2 ^# DMCASP_RX_MODE_DMA);- g D6 `1 M9 y: T" Q3 G2 y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 |+ H6 K# P. Y+ j3 k G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 Y# U( L2 A% @' p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; W: v9 |0 ^, t3 r& t$ v8 J: xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 k% _! K: @/ G- H9 |0 ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * Q: X. {+ A. z/ u$ ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- ?$ c' Z2 \ u/ m. z& h) F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. A1 C8 c& |, l4 I; t( {0 R% n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, ?: P* Z: J& g0 }6 dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) m# S6 u( v7 {5 C- Q0x00, 0xFF); /* configure the clock for transmitter */8 F6 A3 l; m/ A( v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% i; Y) ~/ d. K7 HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 e# [% b9 i5 \$ a0 j# D* ?: F" SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ l3 D- K2 a& u0 m' z( R0x00, 0xFF);
1 {9 @5 B1 ?; K7 D5 S
. X5 l. t# p/ X/* Enable synchronization of RX and TX sections */ + \0 M3 X3 Q+ M' R' ?4 a$ y C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 H U/ t: v* T8 H* ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 a- n' ]; b4 M# E% G4 c5 S% V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ h) I: a, B7 ~. ?: E9 B. R** Set the serializers, Currently only one serializer is set as8 ]8 _1 A5 z" r6 n8 \) {
** transmitter and one serializer as receiver.
: M! B3 c/ c) H7 y) Y*// k$ ]( \7 g. S- P7 ^7 H9 _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 H0 i: r+ f$ m7 b8 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 G' P; K% B- a' |- `
** Configure the McASP pins
* d' L& F) m1 R {4 ]** Input - Frame Sync, Clock and Serializer Rx' a* Q+ \- Q. C. _0 e" o
** Output - Serializer Tx is connected to the input of the codec ( x' c5 f; t$ N* Y! N9 }7 @ Z' E+ F
*/
9 e, b! r2 q9 a1 ^$ I+ a3 g1 zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 y2 ~) V- c* Z% I, J/ WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 T5 t4 F; Y9 P# ]8 o# j- O) A ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 G: q2 ~+ P8 ?$ g5 U| MCASP_PIN_ACLKX5 { K6 C4 b$ ~# |
| MCASP_PIN_AHCLKX; @1 O; F9 d' H! r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( ~# p+ S% I4 F LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 Z: u, W. x# R+ c* e5 i$ r; U
| MCASP_TX_CLKFAIL . \- h' p H3 M, ]: ~7 o; [. [
| MCASP_TX_SYNCERROR
" V" `) W7 C2 Y4 p( _+ [8 }7 d M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: R2 d" a2 v. @| MCASP_RX_CLKFAIL
% H1 d, P! j+ \4 Q8 \| MCASP_RX_SYNCERROR 6 D7 g/ z6 W, M6 g+ K! |
| MCASP_RX_OVERRUN);* T' T% y' x+ c0 C3 }& V
} static void I2SDataTxRxActivate(void): y. [& l- v$ F) a1 Q- R
{7 u+ D! q& v% X# m! D6 Y+ ?6 M+ z
/* Start the clocks */
N0 _+ f* x0 T4 Q% KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% P, V: T. o7 t2 `, _! L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, f5 j" q5 ^/ d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 x" s5 \4 x$ `. IEDMA3_TRIG_MODE_EVENT);
6 z: W9 i* }+ g+ G% _& EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 t, p7 k' `7 O( T8 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
o6 Y) B" ~! ]' {; RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- b: b. a3 f7 c: S; }" EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 c3 V$ W$ A# a; {4 G7 T& nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, J$ E7 a( T" S) \3 T& R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( y1 o4 f7 q- l! m3 M2 Y& E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( m9 |3 |; [5 Z
}
1 O' B8 L' l* ~% G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 l2 [! q0 x$ k8 O4 I2 @7 _
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