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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% {$ z$ E2 Y( t' binput mcasp_ahclkx,; H1 }" F* }' |0 ]9 H% k( W W
input mcasp_aclkx,
) Z+ ~! Q( P: B' v5 b9 M- x& rinput axr0,
% l' q" {6 g I) W, U5 ]- \, E- K" S8 C$ v5 x1 n
output mcasp_afsr,/ w5 t8 c) O# q2 D
output mcasp_ahclkr,
& n$ n# S; [: O' p: Y; P2 g5 houtput mcasp_aclkr,. q3 a% M. f* n0 F9 R U
output axr1,8 ?2 t% B0 q$ p% j! S
assign mcasp_afsr = mcasp_afsx;
! j. I W' F/ Z# R3 \% Iassign mcasp_aclkr = mcasp_aclkx;
: Z# B& g* u# p4 K' L Massign mcasp_ahclkr = mcasp_ahclkx;
7 Y. S5 f' s/ W1 A) ^assign axr1 = axr0; 8 q' [' n: g9 k4 J& J2 R& B
' |# w! F$ e. W" P5 K m) v, c* }3 I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 ~9 M$ M" w! D9 a; t8 S2 vstatic void McASPI2SConfigure(void)
( _3 s- N# H5 z/ i1 a* i/ C3 K{
, G v, N+ d8 p9 k2 j* k- e; \" mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 r6 c" U' ]& s" pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 o l, j8 m1 a, a! N( s* j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; X% l# J# a) a5 _" O& U! f0 e* p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% g2 ~) o3 {7 t6 y4 |. {4 bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% i* C8 i, |. C
MCASP_RX_MODE_DMA);
. z' @! G! v, b* F u9 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ Y& d$ k7 C% i. u3 M, d5 U3 z E6 f1 R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% y. W O) |& a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: E- p/ E! @3 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 O4 p, ^( k2 _+ F ?& OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 A8 P H, p( t% p2 h4 x% }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 c q9 C0 t0 r% w9 zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) U, e L+ Y% [: G+ C) XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 O* f4 q3 w$ e3 D/ b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 K: F8 f( |- H' a1 I i8 Y6 T1 ]
0x00, 0xFF); /* configure the clock for transmitter */4 Z4 _2 P# u) _. x/ `' h0 }; d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ X0 v6 q. M7 Q& M, w/ `5 S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 b: r) k# H$ I) j( \2 Z, D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! N" D/ U0 }: N4 e
0x00, 0xFF);
. k- `; m" A# Q1 i) h9 r; n' j! ~+ A9 s3 y4 R! P
/* Enable synchronization of RX and TX sections */
, r4 a- @5 Q8 v# _; @! ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; v1 ]3 Z9 S$ CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' D- p' M; z# J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ s1 m ?; f1 ?+ n5 G
** Set the serializers, Currently only one serializer is set as: M4 b6 T4 k m6 r0 C' A- S& B# ?. s
** transmitter and one serializer as receiver.$ ?! u# B! g* ?( Z L3 {
*/9 q8 W" l! I+ N. L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! |% s# t0 k1 K c1 W$ d! y; H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, `# H! S. T0 ^3 M
** Configure the McASP pins
' H4 ]5 ~, T% H- x** Input - Frame Sync, Clock and Serializer Rx0 A7 x+ _( b0 A
** Output - Serializer Tx is connected to the input of the codec 8 V; _( o0 Z4 L2 g7 K# X# r
*/
5 J+ s& q2 ]+ D- wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 r' @$ b8 U+ }+ n# o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 e2 {- p4 |! X' R; v: ]% X# x$ u, xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& Y1 _ N' |. ]
| MCASP_PIN_ACLKX! k8 f+ G* t `7 {
| MCASP_PIN_AHCLKX" b) D# a0 K0 `& r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 y1 M& p+ q) m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) O& D) u7 g, d3 {/ z| MCASP_TX_CLKFAIL 7 C. n" r. X( I8 I" v" o2 M* g/ G
| MCASP_TX_SYNCERROR! N0 A! H! v3 f- j5 O/ i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 f8 V$ E# g8 m# [
| MCASP_RX_CLKFAIL! c$ C0 ?2 W$ `3 j+ i! T
| MCASP_RX_SYNCERROR
5 x1 ] P6 v7 R0 G$ `) ]- T: l$ S| MCASP_RX_OVERRUN);
7 M' u' y' I, \} static void I2SDataTxRxActivate(void): s, I7 C" K# p( C$ }
{
d0 j2 D2 S8 a0 a9 L/* Start the clocks */3 R& o+ L; K/ A. K l, }) [4 J: P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% t1 E- m/ _3 N; X7 z7 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( v% q$ l6 j; u) n( _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 _8 F6 N& I/ {) {& M: ^: M `+ m$ x
EDMA3_TRIG_MODE_EVENT);' _: A% k+ C# c5 _$ c/ F# l9 B- ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . @) a1 {/ H) A3 h: G m4 Q5 Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 V W6 z1 h( G- {8 j& O* ^/ J% cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 G- O+ V) U; s9 W) ?' ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" t- ]/ v; _! V/ w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% u0 o/ I' D }2 k# T7 H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# c x& o7 P; t! f: R( M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; }* x7 R2 }8 j( j- L; L}
8 @3 P- W$ d3 K/ E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ f" z5 L7 W- W2 ?, M; L: z' [
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