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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' v" j1 c" v5 finput mcasp_ahclkx,
1 K0 C U L) x5 W0 \input mcasp_aclkx,5 U1 p/ B2 D: D5 Y
input axr0,
7 N$ D; n5 h4 V$ O- e
$ I! j& ?, l( J/ N6 F3 K7 R7 \output mcasp_afsr,0 Y/ P! N4 L" I, Y$ W' y% A
output mcasp_ahclkr,% p5 j- t; H# I: X* M, g
output mcasp_aclkr,4 k; _% [/ T2 d- I
output axr1,. F. a2 c1 k# C1 O
assign mcasp_afsr = mcasp_afsx;
$ b$ I* X @1 w; m# Hassign mcasp_aclkr = mcasp_aclkx;
% z- s, X0 ^/ C3 ]% k( Sassign mcasp_ahclkr = mcasp_ahclkx;. V H( u/ i) M: F% n
assign axr1 = axr0;
" z* q# i" o* X9 g; K, Q3 d* B+ g6 Y o9 |, J6 c& ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ L4 Y5 W% ~. O4 u6 \static void McASPI2SConfigure(void)
3 T# _7 S& y1 R{! n1 K+ e3 A/ ~: Z/ N$ r! D2 z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 h- c2 e5 L$ Q+ d8 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 v6 @) ~& p2 J, \7 r c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" L- l& v$ [ I3 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ N% s+ R7 ~1 Q! l' \# G1 X* uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! U9 d- M, L7 y# H2 U0 P8 eMCASP_RX_MODE_DMA);* U+ F; L/ [. j9 h# n. u; ~) g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 k- |* ^" Z: X- c* e6 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' a1 r! @! S" e( n9 g3 gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 W' f6 F" D) v; H! @" o. b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) y- m( {7 U. ]" |( W/ j1 n& }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ Z% i3 @: t3 `3 s# ?, rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- {' b' o' T* G2 ^' sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 o y# u, p' O% PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 ^* s* @ y/ j- d5 rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! R9 i- G$ ?# t0 M0x00, 0xFF); /* configure the clock for transmitter */
* L+ T3 r: X0 O; p6 b `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, W6 B6 j% K$ _+ V/ I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 m; n/ e! r4 @ ~$ c2 c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 ?' n A! R0 x8 H* c% {4 D
0x00, 0xFF);$ l" @- m: k7 c$ B
( t9 U( A; P! H" [7 t1 z/* Enable synchronization of RX and TX sections */ " c. Y, y6 |1 J: J) y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 A, t, b5 V- a9 c. Q5 M7 B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% l% \7 C, I7 |5 `0 Z. _4 q4 j7 mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; y9 C# j, A5 t5 p ^1 }, A9 y$ u, A** Set the serializers, Currently only one serializer is set as
; f9 g6 x7 n; Z, b( B. U( W# L. S3 P** transmitter and one serializer as receiver.0 D A) I% V5 f7 X' q' }6 G
*/
0 W% ^% u; s6 o8 K' \* ~* {3 j0 @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 ]" n7 _2 F" B% {( H/ X/ L. \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 E* @; g8 z! u% ?5 h- s
** Configure the McASP pins
0 u, e t4 A% K4 L2 q** Input - Frame Sync, Clock and Serializer Rx2 e7 `% v/ F& O T9 ]
** Output - Serializer Tx is connected to the input of the codec , l, I+ Q% _' a( J4 r
*/
8 V9 b" J# I, A6 ?7 ]3 @; q) F8 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) Z& A4 l. a) \7 m) Q( G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ [4 v$ z0 g: u7 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 a- Z- m9 ~+ K, D% K& F0 ^1 x5 p4 N
| MCASP_PIN_ACLKX
3 Y: B0 b5 U5 e: q| MCASP_PIN_AHCLKX
* E' e* w2 L- F6 |2 j$ v2 M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' \& v7 V- E/ C% [( r' o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. n5 Y+ Y* S [% S( L/ h( N| MCASP_TX_CLKFAIL
6 c t, X+ m- \4 h( h| MCASP_TX_SYNCERROR
1 h: t# |) a& d9 S' B( z" b$ F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
w* e9 ~4 m# J2 _; F |) l| MCASP_RX_CLKFAIL
! n# G' j3 d) ] U3 P1 U/ Z! r3 L| MCASP_RX_SYNCERROR
. R* S8 C8 L) n( V9 x3 k| MCASP_RX_OVERRUN);7 e6 W& H6 g- a4 L; ]
} static void I2SDataTxRxActivate(void)5 R8 \ {% J2 { P9 v" m4 j
{
+ J9 G# s- r: U; g' y. D* _/* Start the clocks */1 v- \ U' g, a# e0 j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ N/ O7 c. ]9 T) }* J) WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) `4 V$ e; c# c+ I% X# u; j8 _. Y, REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 B% R& y3 ~% }& t% ^EDMA3_TRIG_MODE_EVENT);
1 ^# T5 t u2 S% `" Y2 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( j7 s' o: s& p# k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 e: o) X1 _9 H' G( A. s$ i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: Z5 y3 U2 E. z( aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 F: ^+ l* f1 f+ \) x# G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; G0 C* z! J; u% A6 p7 x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) r( [2 e7 y; X: G: P! V, b3 s& E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 F$ o' B7 W9 h
} " n( H8 \7 Z9 `6 j* W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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