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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" @: g9 Q1 g/ e3 V" Q, c$ winput mcasp_ahclkx,- X# u T/ O' r9 f
input mcasp_aclkx,: n. m" R" G0 K q3 g
input axr0,# `. M. s! Y2 U9 C. h. a5 h
' M, d3 T8 F; U
output mcasp_afsr,, ~- t8 O ~# U" M6 o
output mcasp_ahclkr,
: U+ r- x4 J* q4 g, }& Poutput mcasp_aclkr,
' k4 B7 O" v+ `. ~1 M* z# coutput axr1,& c# k( q+ ~0 J+ S5 P& a% m0 H3 h
assign mcasp_afsr = mcasp_afsx; g# L* W/ l5 h( w6 f! o
assign mcasp_aclkr = mcasp_aclkx;; A8 C( d* r! f: u$ T
assign mcasp_ahclkr = mcasp_ahclkx;( M' ]4 ^- E7 r, S# P" w
assign axr1 = axr0; ( i, t% W9 j( c( T$ w4 y7 G
+ G* v. X1 W c% J% R1 D% y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; e w* @7 \0 f% i* P
static void McASPI2SConfigure(void)7 o `- j/ N: m
{3 l& S- e \. @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 [* x" G! ` ]. AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ h0 \3 H( u8 l; J9 H' CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 o5 w& U4 Z' Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 g! k9 P: }: ^" u8 ^% T1 H: M( p! TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 u1 T5 J+ O1 q1 N4 r. Q$ f
MCASP_RX_MODE_DMA);; c( W; U; [/ T9 a/ Y6 K7 o8 g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ w& G' k0 o" M9 F2 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& N/ Z2 L$ w+ B& aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& I" y! k( s6 b& ~% Z& VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# U, H* n: O: _" U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % j# Q% Q, ]( h6 z& d% z6 M! f: M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
J0 D! Q2 b9 y e5 Z2 XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 Y( M. N# ]- [8 v! q8 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ F# A+ d! H. e4 { E8 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! Z( m5 y! f" v" _/ w8 H
0x00, 0xFF); /* configure the clock for transmitter */
9 |1 A5 c) T- w4 }5 q% wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* x/ Q6 m1 @; i! _: ]9 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 o* B) b: S- g3 i) _0 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 R0 k ?0 s% r5 p0x00, 0xFF);
7 l3 {! P [$ Z6 L" z& h9 {) h. }# S2 N$ G) e R
/* Enable synchronization of RX and TX sections */ 1 l$ k; G. F) ^: n# [ }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* e# N3 Q$ L& ?; `& NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 T n) j6 F8 J6 k- [$ m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 I$ O/ F2 i; }: a: R. T% C: q
** Set the serializers, Currently only one serializer is set as
( o* z) Z* z! A7 d+ g4 o1 l: o+ H** transmitter and one serializer as receiver.
" @; N: n& K: _" P6 a5 O; Q* U*/
& [7 S4 {, n% ? PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 }3 U1 G4 m# y# {0 \7 ?$ z& A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ d* a8 ]* R4 q$ o( G# l+ W- W2 V
** Configure the McASP pins
$ a5 }0 f9 {. q w** Input - Frame Sync, Clock and Serializer Rx6 W+ |" q0 B0 `( ^' T Z6 c
** Output - Serializer Tx is connected to the input of the codec
. F0 U# }, u" I4 ?: ]*// E) D4 \/ M0 a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: V! |7 K; O7 V% w7 f# u# s/ V$ b: aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 e; m& r0 t2 H( x4 N8 {- uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# e8 X t7 s' c1 A3 I! a$ T2 B2 j# O
| MCASP_PIN_ACLKX1 f/ b; }* F* t' H3 R- L
| MCASP_PIN_AHCLKX! R4 |8 f) O* M$ A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 ^) \8 O5 v \9 w" X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( n3 S0 R# W; w F3 o' \8 I
| MCASP_TX_CLKFAIL 3 @9 ^* Q/ ?8 N8 L$ s6 ^
| MCASP_TX_SYNCERROR
0 R/ a/ R; R8 @$ g9 ~6 f9 `$ r# |# H) A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 ~& y- D- @$ U H! U+ ~
| MCASP_RX_CLKFAIL" w4 G3 p n& Q7 r" G: g
| MCASP_RX_SYNCERROR 1 C$ \5 Q- b; A3 T. _: W" Z/ l- R: R
| MCASP_RX_OVERRUN);6 L; o+ y8 T5 f, _# R' X: m' g
} static void I2SDataTxRxActivate(void)9 _( l2 q+ l% T' O8 {
{* j% f' V; U9 s
/* Start the clocks */
$ J, `) Q6 o& O. D- X$ eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" Q# e2 G* ~2 Q6 E! v/ JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, @2 o. W2 j1 C. _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) T$ p- O( X0 U& ^2 c# \6 z& DEDMA3_TRIG_MODE_EVENT);
8 M' U( I" |1 a0 B1 M5 C6 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' K4 m7 e' U( S* _$ uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 {. d8 U7 t1 b$ T$ K i# hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" G& z# ~7 X7 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 u# i6 }4 H |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 S- g# J/ S6 U& \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ Q8 z+ ~& Y8 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 n- l0 R! ?; O
} # h& V. V& [% p6 q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; F6 c7 a, P. g0 |+ V- C9 l
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