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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 L7 ~! j W- H' _" iinput mcasp_ahclkx,5 @. ]% Z/ T4 S! o4 f7 I
input mcasp_aclkx,
7 O1 i6 @5 N5 t) Qinput axr0,
3 ^& e& c2 q/ F, \% a1 N
. z" K: A; p, |" k8 ?3 X0 zoutput mcasp_afsr,2 b' } {& e+ Z6 k: E$ M* A
output mcasp_ahclkr,
) u1 W/ R, ^6 i0 Houtput mcasp_aclkr,
4 ~0 q0 u& P; Q! g$ @output axr1,4 l8 k e9 U: g) [- G- g' Y8 e0 i
assign mcasp_afsr = mcasp_afsx;+ c; ^7 h3 A9 \0 J6 \7 `; g2 N
assign mcasp_aclkr = mcasp_aclkx;
0 Q+ ] Q3 }8 C$ o" E0 oassign mcasp_ahclkr = mcasp_ahclkx;, `! P4 B7 h- z3 m2 Q
assign axr1 = axr0; $ x7 q( m; ^3 }/ A$ p
. G. x- L& {& [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( |% e, M+ J7 f! B# Mstatic void McASPI2SConfigure(void)7 k9 D+ d& I1 ?. G
{
$ X/ `4 T" @* i) v! |! eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- b0 O M( M; ?7 ]: y/ MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ c& n8 w# D# y3 X" e DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); m5 d! s9 D# I! x* }& b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ m- `2 V5 Y$ D+ EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 @7 U L5 M9 p7 ?, V) t4 S2 gMCASP_RX_MODE_DMA);
8 x, x3 S* A! A- b# BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& m% Q5 q# M" X0 A* K/ _ KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ y2 ?5 Q8 M9 H6 n9 z0 ^6 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . g" I! G! W' p3 w7 ]1 w/ v/ F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 W" M/ O) m! iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 W: n$ X, {) M! P$ | w2 v9 g1 vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 X. [7 r8 D! p H* jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' X6 u* g+ N1 v( v5 NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 q9 t: W Q% R' fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 `/ @8 e: \2 h5 {0x00, 0xFF); /* configure the clock for transmitter */
- z/ R3 \: W1 p! tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 X1 ]7 s ^' L1 I. {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 N, r) U- d! g! Q( y! k, ^' S$ n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& J8 B2 X0 K' X$ }8 e
0x00, 0xFF);0 }, b- d" L B" ?
7 |& J9 @8 s. W9 m3 x/* Enable synchronization of RX and TX sections */ 5 p" ^5 \; j0 G: a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& U: O1 t# b1 s) \9 ^$ |9 G8 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, B% a# \, Y' `) q+ J* C+ J) QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 i. o! h6 _: M! m
** Set the serializers, Currently only one serializer is set as* M7 e+ w, c0 ^# A6 T3 [0 O
** transmitter and one serializer as receiver.
' G: ^# z2 c$ S2 v* i R1 L*/1 x7 j/ O: Y6 b- a8 S& F1 ]8 N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 I, A$ @; z; E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** ~8 f* X! G8 l& K8 n# o
** Configure the McASP pins ' A0 ~1 x' J( c
** Input - Frame Sync, Clock and Serializer Rx
7 X+ |! \; w. ?6 S8 K3 W3 b" i** Output - Serializer Tx is connected to the input of the codec . S d; N7 t; D, g6 m/ y: P H
*/$ f# ~9 \/ y* w. [" X: n) n# F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ L" I# D3 l X [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' P6 Z5 z, z6 L% e+ S; Y) I, KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ c9 ~: k/ `1 G+ y, q, T! {, K| MCASP_PIN_ACLKX( J, \$ r, @1 H
| MCASP_PIN_AHCLKX
3 v* h$ Q4 ?" V: _* E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// y! E# r1 {" J4 b# y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR q: q7 I* m: [* X& j J$ V6 h
| MCASP_TX_CLKFAIL 8 S5 q$ l& f% i& Y6 J5 p2 u
| MCASP_TX_SYNCERROR! r$ _2 g8 h' B$ y8 {; Z& i9 M4 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' h l6 ~8 P: X| MCASP_RX_CLKFAIL) o* D9 {" V, k! M( P( m
| MCASP_RX_SYNCERROR - T" M5 @3 D4 _# K3 {
| MCASP_RX_OVERRUN);1 s; _2 R5 s; P+ \1 r
} static void I2SDataTxRxActivate(void)/ @% U, U8 }+ }3 B6 h
{
! _, g/ W* o2 N+ C2 ^+ j/* Start the clocks */
6 M# S% n" v" zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& { l: w+ [( r( U ?, f2 u0 v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
b: R6 e4 T P! hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& y2 c* ~: p7 L' `6 Z- L# h
EDMA3_TRIG_MODE_EVENT);- u- r w# v0 @8 q: p' @8 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 O, w/ b9 \/ u/ S7 f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 R \' v5 x9 G+ q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 M0 Q) w3 \+ P5 T% t kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 S$ {: f2 D s4 S J5 Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& _2 D3 @+ A- M% Q4 ] ?7 LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
z! N( R! k3 Z4 L! }5 e' G/ J$ s8 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 _# O9 K6 x- ~% d} & ^' L- }4 h, F8 F/ o1 r2 h, S3 ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 q' C9 e# h L9 S# s; s% F# u
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