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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# O9 ^) n" h0 r2 y2 `input mcasp_ahclkx,
# r4 i9 y: J7 M" e0 ~2 K0 ainput mcasp_aclkx,9 d/ s; N) J3 J2 D4 @) y7 N9 u
input axr0,
* j, E$ D; x+ `) a: @0 |3 w$ x
output mcasp_afsr,& J5 j0 D5 @" H
output mcasp_ahclkr,- q! b. H) D* K1 r4 R
output mcasp_aclkr,
9 X. Y! D0 R7 t5 p+ H( h. ~9 X2 Youtput axr1,5 [0 A3 G: m" [2 O; a" W
assign mcasp_afsr = mcasp_afsx;+ n' p! }, E ~8 `# S
assign mcasp_aclkr = mcasp_aclkx;9 Q2 z9 q Z% v) W- @" l
assign mcasp_ahclkr = mcasp_ahclkx;+ q0 i! ?/ B9 O; N
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! c1 u* w2 I: t4 G. \# A
static void McASPI2SConfigure(void)& [; k& B. ~% K/ ?
{/ N, m: Z' r. r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) a! g. v. ~' p. ?! h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 T( S3 V5 t$ e& U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& M( ?+ I# A: L$ F' f- z/ iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 \ f" Q" J" w9 U$ s! b7 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 s3 D8 G" \, j0 h% z' M/ p: lMCASP_RX_MODE_DMA);4 T$ J; Y3 l7 S/ m) \0 {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 F, F8 |# ]* u: Z. Y* Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 V3 T: q4 |/ NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# @4 d$ m: r* Z7 p9 h- M+ ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: W+ {( X' m" ^7 B+ |% g$ d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 T. r5 O. r: `7 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 o5 c( m$ ~2 N: k. Y. N4 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 C- @% G" S( P R1 ^. z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' E; t* i8 M# R0 ]0 x' {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 ?1 w, l+ ^: N/ g z9 P0x00, 0xFF); /* configure the clock for transmitter */
9 l6 ?! b( H( M. u/ z% @2 h: x$ }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) E. e$ a9 N T% F5 e% p6 k- [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* i' s' F3 E7 K& s% BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: t& B, g+ s- l& Z! @( D1 v' P0x00, 0xFF);
% y1 _ L. G; b+ T, D2 M
! a7 _9 S% G' N; W" C. n/* Enable synchronization of RX and TX sections */
' I* U: X1 \* E5 Y+ qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% }. T3 x) U; T! m' r" NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& r) ~! @4 e; U Y D% a" n/ B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 x( X" p) h- F8 c: C4 v7 y
** Set the serializers, Currently only one serializer is set as0 G4 B0 G- n6 d$ |$ }7 n0 e
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 \4 J* x$ o- j: |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 H! N. c! {8 @, w- \$ V+ r** Configure the McASP pins 9 J) j5 v, u1 h" `
** Input - Frame Sync, Clock and Serializer Rx: M) f3 Q1 ^" [
** Output - Serializer Tx is connected to the input of the codec . B9 q( J Y8 k% o
*/
: Z" g/ T8 e: z9 J/ k! h% gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- q8 l6 q! b- U- H( `4 QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 ?9 S1 u8 _) m8 @4 W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. U' j; c( M; P% M8 y& k4 S% H| MCASP_PIN_ACLKX$ F" S9 P$ q( v4 L9 K% h
| MCASP_PIN_AHCLKX! S r. ]- k1 {6 q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# e" X; t3 r7 v5 \8 | Q* hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . _; }7 K$ L4 U# q+ t: s3 U
| MCASP_TX_CLKFAIL + f+ M; B. D' j# C l) r& }3 x
| MCASP_TX_SYNCERROR7 _2 y* r. E: L1 Q$ Z/ T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # y1 S2 A; }# Z# S, Q0 V1 w
| MCASP_RX_CLKFAIL
) w+ G( D3 w; K| MCASP_RX_SYNCERROR 8 h2 X6 t5 u& }% i' P. J' \$ @5 Z
| MCASP_RX_OVERRUN);
3 d) _; B& y) e} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
; a, {# B# d) ~. J; K. M$ @7 OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ b' L3 G+ f; g; f6 l$ k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# N) |0 P2 V* ^% N' n" H8 m" XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 [5 }! f0 i( }2 X; vEDMA3_TRIG_MODE_EVENT);$ ?' W1 f' I8 ]( V* _, [* d3 _/ i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & z t; U m c% Z/ q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: k, h4 i& B1 B! A7 E2 J e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% g; N; t8 d0 o7 H: G& \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- u$ @2 r; m! W: z5 b z+ qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 \4 @9 w3 u8 ` U4 F3 tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# E: G8 [3 H$ G8 p! U- Z* l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! V* Z3 Z, j( ] K
}
0 h" g9 L+ O8 t& o2 ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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