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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. z0 A1 \9 t6 p8 V" x( R& b8 Minput mcasp_ahclkx,
4 W7 A2 R( o) S# binput mcasp_aclkx,9 a# `$ \! l) _$ T
input axr0,( o) ^; e ?: a5 s7 ?- f D% ]
# d$ f2 Y, ~+ M* B7 }7 loutput mcasp_afsr,! R1 W$ J t) K) x, M/ H4 _: c
output mcasp_ahclkr,
! v+ U7 K c3 }9 noutput mcasp_aclkr,
! |. N' g& F0 uoutput axr1,
' ?' |" ?# `6 f: l, C assign mcasp_afsr = mcasp_afsx;
/ H& d/ q' o/ n' I, T. J; Y# y- Tassign mcasp_aclkr = mcasp_aclkx;
! A* Q: N& I% l. ]) E# Y4 ?assign mcasp_ahclkr = mcasp_ahclkx;, K7 y: }8 n$ h( B" y" G, X S
assign axr1 = axr0; 9 }$ F! o, i1 H- ]- p
* y, L l' x0 B5 H# p. _- M* H' @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ s" v" `! b/ Y9 W3 fstatic void McASPI2SConfigure(void)
& O" w1 F) \5 ~; ? ], f: t{
% }/ U9 h" c6 h1 i0 Y4 E# t7 K/ mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 K/ H2 ] O$ B* wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ ]* T6 ]# I5 }) d- r' R5 d5 MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 v, S- e Z6 v( YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* u; j: m! Y. o- `5 uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( T3 G* E. p1 z! A5 \& H: ?
MCASP_RX_MODE_DMA);
% E2 w& D7 T6 n, p; _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 ?5 {! d* F& a9 P. A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( f- ]1 l" G$ z# u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. l9 O0 P# W& d6 x: J1 Z$ CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; [5 E, U7 y/ OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 ~. K! `; Z" N: D; IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ d+ |) W' {# e& Q/ n5 R' ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 u. H% ~. j5 z7 w5 t* s7 B' s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ p7 {7 q8 `2 h1 c, |* G4 \) C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 w8 e0 @3 v% _, Q5 g
0x00, 0xFF); /* configure the clock for transmitter */
* t% ]" g, J5 g1 l. H! |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% k8 m5 F9 Q! t. p4 N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : x% ]6 B, s# R' b2 M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- e/ t3 o7 o& ^& a0x00, 0xFF);
0 `( r+ T& G1 k! r- Z! [
9 q" @$ P7 j w# o$ B& w/* Enable synchronization of RX and TX sections */
- e6 V6 V6 {& @4 |8 |+ TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& _) h _( O+ S2 Q/ X Q1 N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- v" h% b A5 A" NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* P9 `5 w X" c. ^: Q# E& C8 U
** Set the serializers, Currently only one serializer is set as
. `# w3 d5 U" u B** transmitter and one serializer as receiver.2 v; N# Q) E3 W3 j1 m
*// \: b. `3 E, e6 V, S$ M0 _" P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
v! \% b3 s- y5 J0 ]$ J/ \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 K4 U) B: V: L* K
** Configure the McASP pins
- q: O8 _" p# T4 X6 r) y** Input - Frame Sync, Clock and Serializer Rx) A2 Z# \' I7 W& Z
** Output - Serializer Tx is connected to the input of the codec 5 B- M* P$ e4 P! ]
*/
, P5 i& F/ @. G9 EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 o0 m9 X6 I" |# V2 w$ c bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* ^6 W+ N$ h3 V( \% \4 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ k* }5 o, a+ R7 V0 @2 \& s
| MCASP_PIN_ACLKX, b5 Y( O$ s) a) Z" P3 C- }
| MCASP_PIN_AHCLKX( ?, U. U; ~( z9 ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- @7 t# }% G2 b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( X5 i+ y1 O4 K3 a7 p7 k8 a| MCASP_TX_CLKFAIL
1 ?9 e4 }/ e4 F2 N5 U8 g| MCASP_TX_SYNCERROR5 u" @1 t8 _$ V5 [/ E0 D" U ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 {7 c. A; P! {/ g! b
| MCASP_RX_CLKFAIL/ ]4 D' O) a" e! i
| MCASP_RX_SYNCERROR 5 m" f* ]6 B/ z1 h+ K9 W
| MCASP_RX_OVERRUN);
# I. T b# Q* r! \; y; ]} static void I2SDataTxRxActivate(void)+ E U7 m4 @2 K2 Y ?6 j
{4 b; R/ u* f, _1 F
/* Start the clocks */
4 m* [4 G0 X2 e. m( v9 f: v( nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 z6 r" l" q2 ]4 N$ U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" @. p6 G8 i, o' ^: R1 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," k1 i3 R6 y( P
EDMA3_TRIG_MODE_EVENT);- Z9 F5 U1 F" b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* @; L+ q- w7 KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! N/ F9 @4 |+ j ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ s: W4 F2 I: R. N2 l* S5 a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 u2 P V9 v" v. A4 m5 `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; N* D" V: y, o# _% UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 j( b6 x( c. K# l7 w3 l! oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 l' j. w+ V0 b% \. W' p, S} 5 Z* D, J/ Q# Z4 h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 ^9 S$ Y2 d% j7 A# N
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