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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* R, a, H$ u/ K; [/ b
input mcasp_ahclkx,6 t1 O+ V: t/ I
input mcasp_aclkx,
; J3 |5 @; X9 W% K: M- minput axr0,
4 \/ H+ p$ ]& E, L; M+ S* }, N
9 J) z9 W" n5 @ I: k" y/ ?# coutput mcasp_afsr,
, e; Y7 A4 {1 @output mcasp_ahclkr,( h( q4 G, g: ?- D
output mcasp_aclkr,
( J0 |! h3 G* `" Voutput axr1,
& n3 R7 w g+ _! u6 f" q assign mcasp_afsr = mcasp_afsx;
! h! y; u% B [7 [' L8 Y+ oassign mcasp_aclkr = mcasp_aclkx;
" y f% v: s! y$ D- u' u4 @+ r2 yassign mcasp_ahclkr = mcasp_ahclkx;
; ]% A. j/ y; iassign axr1 = axr0;
: C5 ]2 h3 s* x5 S* ]' R8 Y' z4 H9 x: \, u5 _- N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 M. L+ L- j; D+ x! N. ?2 Q
static void McASPI2SConfigure(void)
; H/ Z4 m2 T5 H* d{
; q8 j+ f' h wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. N7 P. l# O9 _+ A Z7 a# j* |" lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! u1 I" ~# ^ Q! t. hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ x( I. o) K y. hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& I8 `) _+ H/ ^& M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ V! ]( Y. F6 a- p3 w; ~, I
MCASP_RX_MODE_DMA);
# V4 v3 ^0 ]! F5 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 u9 X8 R7 n2 a8 D8 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 P8 y( V( T4 i) kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! X: x- _8 W B1 Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 \3 m. R' v V; x9 P. d5 v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; {$ A, B% U0 I8 Y, L9 _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. E2 O \& [9 Z+ y9 n0 f+ w4 _6 rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* f" l& D4 ]$ m, C7 A2 f$ x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ u2 \. f# t; t' k0 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# h G9 Y. F3 c
0x00, 0xFF); /* configure the clock for transmitter */
0 B* H# w4 n( x% b& B; W$ dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 Y$ k5 _" f [; CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 A) o) B$ E7 k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# K9 N2 k1 L# }' X% [2 P0x00, 0xFF);
9 o6 A& Z5 W# s2 Z2 K3 ^+ f$ q
~. d2 } Z/ S0 Q: v) N/* Enable synchronization of RX and TX sections */
5 ?1 y+ t( q( GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 [2 @8 A# {4 h% D! o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); J* G. a7 N" \" a: l2 k5 }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 N. c+ G" i, n( b
** Set the serializers, Currently only one serializer is set as# F1 U" r, M. R$ ~; p H
** transmitter and one serializer as receiver.
" w7 h0 m X; q. p1 o/ L*/
# d4 e) l- B xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& A# D0 L5 H( A: K8 @! N8 nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. r L" w) N) x8 ~- \** Configure the McASP pins 2 o6 ^& Z1 j, |. {0 w
** Input - Frame Sync, Clock and Serializer Rx
/ N1 I3 Z G( K# W& \, p0 L2 c: J9 P** Output - Serializer Tx is connected to the input of the codec , ^4 J) k1 L9 F( f. V# O. w( Y
*/6 x1 {% s1 o& l' n4 S2 z2 f! ~; t9 s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ T( C- Q+ Q2 C& `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# a5 c8 j5 x* }+ E; {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 J2 A- `; m% T6 \$ u' V3 a| MCASP_PIN_ACLKX; t; p, }) H# I" V$ A3 q$ m
| MCASP_PIN_AHCLKX
$ W' r V( I8 Z0 y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; a& k( e; P/ oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 V8 y; W+ T5 }/ o7 g
| MCASP_TX_CLKFAIL
1 K8 D( P6 t2 A$ a3 B| MCASP_TX_SYNCERROR
7 u& p8 K" a9 ^4 {4 p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ Z! |) J2 n$ u4 H$ ?" m0 P| MCASP_RX_CLKFAIL9 W5 W4 h9 c) F+ u+ I, D
| MCASP_RX_SYNCERROR
* [5 J( O3 f" [/ Q| MCASP_RX_OVERRUN);
( a# {- w2 T& _1 e" P} static void I2SDataTxRxActivate(void)
( ^. ~" U& z0 A& v/ Q{2 w6 R1 l5 B! u% N$ Q5 J' A
/* Start the clocks */
* s2 d- j8 @$ e" [4 CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: ]* c9 X5 }/ Y/ \4 q; l0 O7 H* C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 u# l' ^, W6 P) B. p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ f+ _& W+ j' p& U
EDMA3_TRIG_MODE_EVENT);; J% D3 D G) _- v$ c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - G7 `! T1 n) Z0 i' E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 }% N- x" A3 f) A2 T8 \/ L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 I3 ]. A! r) J9 UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ N/ @( F& }8 i4 F2 A# `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ V3 `0 o2 N9 w, u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* O7 i+ v! \" G5 a M: B9 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ m8 A- O; C7 e. w
} ' w& }1 s# p5 {5 J( L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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