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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; m" T1 [# h8 r
input mcasp_ahclkx,
* K2 J$ X( E( q- a" m1 Y0 W0 Cinput mcasp_aclkx,
6 K5 r7 ^2 g! I+ Cinput axr0,
. }9 N5 _+ t/ I) Z2 i
0 t7 L- x0 U5 Q1 N4 joutput mcasp_afsr," L& F G; D5 R- q8 n9 M, p
output mcasp_ahclkr,2 o! V1 A" Q) E5 i
output mcasp_aclkr,
8 m# K! n4 S, Noutput axr1," F, M5 o8 n5 H' \# L( i f0 i/ ~
assign mcasp_afsr = mcasp_afsx;9 d! U1 ^7 A. `# q# m
assign mcasp_aclkr = mcasp_aclkx;
5 W0 D4 g& o3 {: r# j4 S# P' \assign mcasp_ahclkr = mcasp_ahclkx;; \. R5 n8 T( \3 e/ J
assign axr1 = axr0;
! ]- q' F5 [3 X# [ F6 i4 M/ Q5 u c6 Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" m1 R3 p- r9 @' Q6 |& p, Sstatic void McASPI2SConfigure(void)
+ p. s* K$ h; l& _{
7 M5 O2 w0 M, V, mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! H7 M% V* {) |: q4 s( a8 A6 h9 v6 ~2 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ w& _& ^( r8 A) qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: Q8 j5 Y4 t( Z; F! {1 P/ dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 _5 j4 ?/ M) z3 H3 [8 R0 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, E# v" S; B: D8 c1 @7 q$ _
MCASP_RX_MODE_DMA);) a$ z& w" d: I# [9 w: Q8 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; a/ j$ N* p/ {9 ?9 u# k' J) f! a+ |: F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. [/ j& M5 t$ {& f/ r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( ~) O5 }9 M, |! V- e2 S( s% b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ M: H' t( e6 X7 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 V+ B5 q8 x6 m0 b. E0 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 y5 |" k9 X; j ^1 v1 o% \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ d" k! @, e x: h: @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ T, ?/ e3 K! q5 Q( HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 G8 Q$ `/ L4 f* R# [& r& C0x00, 0xFF); /* configure the clock for transmitter */
@) r. A; z( q/ a6 E% Z% b: H; L) ^6 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% u3 p2 M4 G( N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 u1 [& Z2 H, m* L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ s7 G1 e2 O6 P; T0x00, 0xFF);4 l1 d* e7 ^8 S0 b( N {) R
6 E' M0 ~$ e% y/* Enable synchronization of RX and TX sections */
- c5 |6 x0 M1 I' XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 b( S, m, g2 C& U6 |9 \' D* I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 t9 S# ~& g1 j7 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- H: N& M2 l9 ^4 a) o1 C2 r** Set the serializers, Currently only one serializer is set as
3 ^8 \/ F5 q8 i5 Z' D7 S7 I& ], H** transmitter and one serializer as receiver.
7 F$ Q, G; X4 Q$ ]*/
. C$ P. B& t0 }, v$ ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, l/ A5 N @1 f5 Z' F. a( H+ t: C. ^4 v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! W" w2 _) P$ U! L( e9 B1 m. z
** Configure the McASP pins 4 ], f }& q8 ]+ q' ~
** Input - Frame Sync, Clock and Serializer Rx( ]2 ]9 Q* i; ^4 I: _9 ]
** Output - Serializer Tx is connected to the input of the codec
. @. s& o+ z* j8 K*/
3 j. T, \& J' C5 f0 b. DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' O5 k3 D! J' `* L/ F1 xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& O" x( C. O9 F4 ^7 l e% j1 jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( v# b0 @1 u( w: C| MCASP_PIN_ACLKX1 a5 H' {- R4 W, P: m! N
| MCASP_PIN_AHCLKX7 S' L' n1 ^* V- Z% W7 p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 v- N. E, |- {% |! u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 r5 R0 l' Z( [$ ?| MCASP_TX_CLKFAIL
3 c) X; N% y8 v9 v| MCASP_TX_SYNCERROR
/ s: [7 ]4 a0 I' Y v" @. O3 s q. q5 l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * K" |7 X& c4 h9 g7 }, U( ^
| MCASP_RX_CLKFAIL' w+ K. g7 b3 u& n8 H9 f
| MCASP_RX_SYNCERROR
+ F. b. _+ F" Z& |- R' O9 `| MCASP_RX_OVERRUN);
8 T4 [2 d' u% Y} static void I2SDataTxRxActivate(void): q5 T4 q; ?2 E7 Z- V
{8 g$ P9 W: x2 t" z1 O1 g. N
/* Start the clocks */
! O0 e% a4 c$ Z" |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. Z& R, Y: J$ A4 _6 U$ O' q- B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! T! b* Q& j# s A( y3 ^6 U! {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, e; ]& k* ?8 o9 b- F; P+ E5 V
EDMA3_TRIG_MODE_EVENT);
$ @& i' o& I! Q. L5 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + R$ _5 j9 w" q0 f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 n- b' e' q: ~ P+ h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 G0 \8 N% V3 Z; n$ ^2 eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) ^- P( W) g6 R3 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 {; P- v1 B7 a. E* ~2 wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" |* o% c* u3 X! B5 g& j2 n2 |/ S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 Q; J2 ?( G1 q# L' | N}
/ k# I* m- T2 m6 }9 f2 `3 W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 e6 a; I% E: t; P- g4 F/ J
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