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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 j+ L! f( K9 @4 W- [$ j- Zinput mcasp_ahclkx,
& i; l. l" ?, [- ]& Ninput mcasp_aclkx,7 x. R0 J8 ~0 A# G) \4 g, K
input axr0,4 C! @. Y4 ~. N) _5 w# n
2 t# h( t$ r4 H- f2 U
output mcasp_afsr,
5 ]2 j) N0 i5 Z! a1 Koutput mcasp_ahclkr," I# D9 c' j) U7 V6 F" T2 z- n
output mcasp_aclkr,
2 g7 g; t# c& ioutput axr1,
! C% @& p! f; Y$ k2 p5 u5 A! O" k: D assign mcasp_afsr = mcasp_afsx;
/ I6 g4 y% `7 X/ V' Iassign mcasp_aclkr = mcasp_aclkx;; N+ i) P) P2 n- m6 j4 C; d
assign mcasp_ahclkr = mcasp_ahclkx;
' o: [* Z. B4 {% hassign axr1 = axr0;
( K# V& w2 y% ~* C2 [: R
2 g" a' |+ o2 n' f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 [7 P. g! S; `9 D* c+ F; {6 i
static void McASPI2SConfigure(void)
. `" W7 M/ e' E" E{
8 E- g [3 E, W3 \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 X E) j; G. m5 E. d# f) Z8 aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, \) Y, N& o9 E9 Z9 X6 w2 tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 o- `4 c+ n8 s; d6 J; q$ EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ I* @! _: a m- e1 T4 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: L% B; r4 @' ]- x" f- F) d! |MCASP_RX_MODE_DMA);
9 M S0 M) U* B. m) N) f8 RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ J- Q, n% |! V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 L ~6 k* W w2 y8 j7 L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 S8 I( y# c# c; gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 o# z: | F: `9 b2 Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& y& s. D' X; ` u H9 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 p* N5 n( w6 b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& l0 b6 Y/ V& M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 U5 l! A0 k# o! T! IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 W+ l9 G& o: N! H4 U* m
0x00, 0xFF); /* configure the clock for transmitter */
9 h* f* c* P* R7 r7 Z- ?8 vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) M6 z+ z5 |/ B/ a; e! ^9 c& XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 q. \5 S4 m( iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- O+ N1 E( E! X8 z( s0x00, 0xFF);$ ?* C0 r+ |4 C; }
5 X+ Y; C" ?4 B6 ?2 l
/* Enable synchronization of RX and TX sections */ , i8 F" {% D$ W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 T, u* p0 s7 ~9 D% L% M0 V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 r: H/ j' K, _& t8 Y( u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ ^; ~( t* o- p+ q7 }9 t2 R
** Set the serializers, Currently only one serializer is set as
3 Q; w8 m/ a+ r8 _/ Z** transmitter and one serializer as receiver.1 \! ]; z0 ?2 Q* ?1 [+ a8 Q2 R" x
*/: m2 u+ r# H u8 r, d) d+ m* b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* G; j7 y9 l6 W4 U0 [6 t7 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** q1 h1 ]' o: u( s c2 a7 \6 g7 o
** Configure the McASP pins
c! k0 y. N0 E( o o/ l** Input - Frame Sync, Clock and Serializer Rx
% B7 c% I+ r6 l6 P** Output - Serializer Tx is connected to the input of the codec
8 p" b% \$ p6 x9 g9 ~*/, C* L2 d+ e# Y% t( w; i3 \. E( f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. w+ F3 f& ?9 {; D, h, ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 K& v8 F w0 U* z7 h: S5 R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' w: ~, p4 @; h0 e& e| MCASP_PIN_ACLKX2 A z: z$ x$ X& L/ X6 m* J0 Z% O
| MCASP_PIN_AHCLKX5 c1 u" m- H% D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 ?; f! ^0 q/ p3 c! i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , |# w* z; r7 P
| MCASP_TX_CLKFAIL , r3 T2 Q; b0 e! u
| MCASP_TX_SYNCERROR9 k! t) E. J5 p4 {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 H+ ?$ z; n0 }+ M" [& h
| MCASP_RX_CLKFAIL7 O6 J! k- j8 _' x3 h
| MCASP_RX_SYNCERROR - D2 a) D- L5 ? Z* k
| MCASP_RX_OVERRUN);
; E0 P* |7 p# L! C& a} static void I2SDataTxRxActivate(void)0 T* |% {5 _: d& r
{
E$ B- |! G$ K: x4 i+ q7 i7 U/* Start the clocks */2 x. [9 l/ q7 I5 r: U% e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, R* ~/ i V- J* B& E, h/ |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ a! O( V* l& X/ r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 A* \ b. K5 U3 H- X7 CEDMA3_TRIG_MODE_EVENT);
0 g) Q5 g' A) S. q8 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! ^: J1 K& C1 [4 X, w; y8 Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 v7 c# R+ y# ?6 X6 ?3 Z' _* n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 ^8 I7 J9 R& i" K" F% FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 N. j' G8 u* Q$ e/ b: r: Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' o6 p5 V8 p7 Y+ P! {: d% z; J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" `4 _2 s( ?- r D8 C. `$ B9 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% c1 T3 i' a1 U8 s5 ?
}
/ u8 Z! h% a4 M6 m" X Z$ G3 q9 z' L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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