|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% S! `! _2 l4 {* U2 finput mcasp_ahclkx,
( n' M1 K* l; u7 o/ Ginput mcasp_aclkx,8 H$ R" z! @. z% k. h& _
input axr0,2 h2 V- f' \/ t! F% P0 R2 V
3 D4 n+ K& |6 A t( k" D( `/ |& R* n2 P
output mcasp_afsr,
* v( b% x- d, |( x# |& Qoutput mcasp_ahclkr,/ b! X* v8 J' j# S# d6 H4 d D
output mcasp_aclkr," d$ c9 Y# a0 R5 W6 Q- k$ f1 m3 N9 f
output axr1,8 R3 ^1 ]! _8 X6 S2 i
assign mcasp_afsr = mcasp_afsx;
( q( M/ f7 w& I: \assign mcasp_aclkr = mcasp_aclkx;
4 j% {/ `/ l" @2 H' m) y) z2 J* C; ~assign mcasp_ahclkr = mcasp_ahclkx;/ c* F7 E% A* Z7 k$ K2 l
assign axr1 = axr0;
3 R# q# Q4 ^- O* T( K0 p: ]2 T/ U: S) f0 e6 ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; P/ a5 l* U% b( c0 {- Mstatic void McASPI2SConfigure(void)
6 Q8 x; u, k" E: d6 ~{
2 Z& E8 a1 q1 f5 j# y' z% VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 o& c5 e# t% m' f2 X# O- I) FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& v3 S3 ?5 i0 @" L& X7 N! ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* {" c9 ^6 x! e9 rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 o3 r5 o9 T1 c, S+ h- JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ }3 ]) }$ D/ r5 e+ i) w9 v
MCASP_RX_MODE_DMA);
/ _* ?$ h0 M) A: D( d" k" n. B! iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. z1 g: ^6 \, i1 V% {$ B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; D7 q' b8 o: V9 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % c4 O* b# [# z: e, D& V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! t9 D' E# H7 ~# N3 @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / f. r) Z8 P5 n9 g. a4 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' n, W7 G5 {! I+ R0 t( sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, A8 }* V+ E* x9 x; R) }6 ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 g# i, k. E9 h$ V% b6 D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- s2 Y$ U+ s$ }7 d# a8 c+ E( u
0x00, 0xFF); /* configure the clock for transmitter */
, ~" [' i3 Q) ?' vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& m% o0 Y5 l! o9 w. [/ Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % h) E# \8 P6 a2 G* m/ P; N, Q l& B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 C. t5 Z# @5 s' c
0x00, 0xFF);
4 I8 g" R) o }- `3 t0 j/ j7 f- f! h* E: X& V2 }2 J
/* Enable synchronization of RX and TX sections */
: b% Y& C& E- y- R- aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 ]4 T+ I: C; t1 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 h+ M* ~/ V' \% a5 b9 [7 `( l, mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) i0 F* u$ c) B** Set the serializers, Currently only one serializer is set as: I# y# m& ~6 Z. r0 x; ?
** transmitter and one serializer as receiver.
: J/ E$ m) `: e9 z*/
3 P/ B6 r0 V# @! z- |# ]/ `6 SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* t1 s3 n( w( u) FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 e& `* j. m5 {9 q* m1 N8 k' Q
** Configure the McASP pins ) o% s4 g# i" }5 }4 o
** Input - Frame Sync, Clock and Serializer Rx P" @' W, {: K v5 N. |
** Output - Serializer Tx is connected to the input of the codec ! K d. W$ c: i5 P; b
*/
% u& \/ Z' ?7 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- P2 [6 ?2 y7 L0 V( r% D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ f- ?) U( [. c m9 m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& ~' M- \. T+ Z1 {8 Y) C9 ?| MCASP_PIN_ACLKX: x7 C' O4 ?1 a+ x9 G. a& U
| MCASP_PIN_AHCLKX# b: `. o% M5 Z! W' C0 O/ @4 l& T) [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! L. ]% |" U7 J( I7 b. {: N4 {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* K. y' v; k/ C0 o| MCASP_TX_CLKFAIL u) f, H. E L) d2 O7 @
| MCASP_TX_SYNCERROR
* P6 f4 |" x( |2 y( L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 k. @* }+ g8 l |! \& X| MCASP_RX_CLKFAIL% }3 i/ K% D& x& o6 D* q/ N5 a6 s" ~% ~
| MCASP_RX_SYNCERROR
3 Y) ^8 d/ A9 A) j- E| MCASP_RX_OVERRUN);
+ u8 [" H% ?, V/ u( t6 s' N6 D} static void I2SDataTxRxActivate(void)& ^9 P$ P. F% A1 c
{
6 l! W7 V$ u% x3 B" d7 Q c8 p/* Start the clocks */
G7 O6 k% j8 b5 o% oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) J# V3 M0 }: B# p' [' `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
b6 \) Y- C/ |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; I9 M% g+ E+ u' H
EDMA3_TRIG_MODE_EVENT);1 Z s8 V* U$ }! [9 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & R& k4 O; R1 t' d- U5 D# i) N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 F6 J. G; v' c1 r+ \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: A6 {, g" {8 fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. f4 }" v4 o9 O, g( Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 R. a0 v2 q" h1 T' A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ w4 d6 b3 c( T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 o4 w. \9 @- O7 b& u4 G
}
4 F! ~" Z# c t) H4 v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
: |7 ^4 {9 g4 _, s% F7 A |