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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
y5 n# i. X) Pinput mcasp_ahclkx,
8 a; F9 W. A: finput mcasp_aclkx,* b7 s* B7 {2 N9 S, \0 r& J
input axr0,
; {+ [7 m4 Q6 r7 }0 F
4 z) ?) B: n ^) `$ noutput mcasp_afsr,
) b5 x# f W# T4 E3 F% ioutput mcasp_ahclkr,* P3 q8 [7 k3 U, Z9 Z, F+ m
output mcasp_aclkr,
+ @" o. U: I! b) `4 {output axr1,
- W1 g0 {/ R5 V' E) J& K assign mcasp_afsr = mcasp_afsx;3 O; @5 W( f# g! o" h$ t
assign mcasp_aclkr = mcasp_aclkx;
3 L% B7 a [ X9 P6 bassign mcasp_ahclkr = mcasp_ahclkx;
J" W t6 a3 J3 V& X' q6 kassign axr1 = axr0;
9 j5 P: n+ [+ u8 \7 g4 U$ U! I" ^; V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 A( k# Z$ x$ a2 [6 R7 q& G* wstatic void McASPI2SConfigure(void)
4 u. g' _: d$ v* Z3 Z# a" Z{0 z6 v" t- t/ j, w3 ]+ V. D9 l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& b; ?. \' A+ C8 ~* d3 }# B$ zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" S2 c d, l( K5 G! b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- j8 ~8 t3 D# n- p/ b. E& O0 xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ x% T# ^: _0 KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" y, M; a" F& |5 eMCASP_RX_MODE_DMA);
. n+ D) u6 f" K! r& @% }' SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 J( N) e3 a! \8 M4 JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# |7 i3 d" v2 Y7 N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& h8 I5 [$ p+ Z& G7 A FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 _ P& {7 n; l' I/ D) o0 U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# x: F' ]5 X6 @3 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% A8 q6 G+ _4 N2 q ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: S; I( N* ~. V& `6 n- A. @- uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - m/ N7 Z6 ^1 b& x4 n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; P, a$ @2 p5 i1 l# c
0x00, 0xFF); /* configure the clock for transmitter */
1 b* B9 O8 H: K" x3 L9 c5 h% x: Y( KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 m- J1 i4 A6 u2 }) Q1 a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); Z1 y5 m. n ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 n! r; a9 u$ Y. r* C0x00, 0xFF);
% S. a* N7 `5 z6 v, x, `
$ i) l4 p1 A' D- {/* Enable synchronization of RX and TX sections */
2 i3 G' |# j F1 \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 X) R- U; k3 ^ R; B/ {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' b5 B/ Y5 a A2 N1 `4 \% l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, z! l9 T$ f/ c4 n6 p7 t8 i
** Set the serializers, Currently only one serializer is set as
7 \. A# @' U+ u6 J) e% ?** transmitter and one serializer as receiver.) w( ~1 K' r1 d
*/: T" D# H5 F: A" K* g3 f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* M4 Z; R1 b# X" h- f* z1 Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. f- h9 o; z7 J9 G: i
** Configure the McASP pins
- x' ]/ G$ @- d( a# ]** Input - Frame Sync, Clock and Serializer Rx) M9 P2 g8 m2 w. B. ]$ F( \
** Output - Serializer Tx is connected to the input of the codec $ O; [! A) a7 h5 j! o& ^5 @
*/
) ~: ]6 S. u/ k$ S6 rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 x0 j0 m- I3 z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' p9 n& C* G$ a9 }; YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 V) I. R- W+ ^| MCASP_PIN_ACLKX* E: ^6 s" \5 M) Q; o7 u
| MCASP_PIN_AHCLKX
{0 O: r' q! a6 `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* O9 E4 o$ c$ x2 |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " z7 m7 }4 R" J) J3 r! k- t
| MCASP_TX_CLKFAIL
: C+ m9 q$ p$ v5 M6 p% G| MCASP_TX_SYNCERROR
( O1 [/ [+ M9 P1 m) b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 R: }4 m. `" {. b
| MCASP_RX_CLKFAIL3 w d$ v' \0 O
| MCASP_RX_SYNCERROR
5 g/ F/ w8 r% E. J| MCASP_RX_OVERRUN);/ F0 z$ d y( ~9 D7 k
} static void I2SDataTxRxActivate(void)
2 Y( e- o+ O% H0 a& T* |{: ]; _4 z% ?2 k; r
/* Start the clocks */& w7 U0 H: v9 M5 L- _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: V3 u* O5 W" Q: H" k" ~6 T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 v: j& P, t6 Q' U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- P% t2 Z9 }% k" b5 U' m. ~
EDMA3_TRIG_MODE_EVENT);
( m: \' F9 ?* BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, g8 D2 q$ `8 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& N6 n* d* J! Z: R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% u9 h; D9 b; q' l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 B3 Y1 C- s& } J, e: f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 M3 }, R. a l! k! d8 W0 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 @0 a& y- i4 [: I: e+ A! I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* j3 r) D% b! Q. J- ~} ) e8 g2 @" k/ W# h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : o' z, h3 U: e' l# z
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