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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, U: s8 S" R) G; W
input mcasp_ahclkx,
1 T% W G3 g$ V f, Binput mcasp_aclkx,
# a8 C: B) z6 l5 G' G! Einput axr0,
. |4 m" B2 `- F9 }5 T! ?; M
8 `# A+ q, T& ]0 w; Toutput mcasp_afsr,
! b- a1 H9 j8 K: \output mcasp_ahclkr,
' H5 \7 t, I) l* K" C( I9 L2 toutput mcasp_aclkr,
8 h0 k* N; y2 } i ]output axr1,
9 r( t' C9 Z" c2 m assign mcasp_afsr = mcasp_afsx;2 H, P3 F# d& [7 r/ z2 I0 h$ g" I3 y
assign mcasp_aclkr = mcasp_aclkx;
: m I) f; f K5 y+ C' M3 [: lassign mcasp_ahclkr = mcasp_ahclkx;3 E! _& [; s7 Z
assign axr1 = axr0;
, t D* C3 E& S: P4 e8 {5 R" [' A3 d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* k L* p* y1 o9 |static void McASPI2SConfigure(void)" @; r. V; f. [3 I$ _8 {* i
{. o0 V1 |/ e; C- ^, ^1 A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 z8 ]2 J$ Q5 y$ Y5 O/ VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 s h5 b& u+ E, h. H! r5 H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ ?7 v& v: ~; Y& f! K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 z; |9 V+ V u! j; v/ WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 k1 s' W9 _, S# }MCASP_RX_MODE_DMA);
! W1 t. t# b* m' n1 F i/ b6 lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 `% ~# P2 U/ A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; c j0 ~7 G1 i. x6 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 V. ?$ _* i% q% `' G' [: J- H) d' P- _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ {! K' I7 ?+ a/ R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) Y" J& x& _9 I2 }8 _8 Y @% R$ v- @1 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* R* _3 q# i' B5 J" M( j; I* k uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! h- \ ~" ~0 H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : W' X" c" w3 @3 }) Y$ N9 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," ^( t P; j) h0 M# p& J' }
0x00, 0xFF); /* configure the clock for transmitter */6 I; m* [; Y& |7 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# i# e$ t- C" rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 A4 l3 t% Y2 f/ F4 l$ [' c4 Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 C7 ~8 A4 H/ R
0x00, 0xFF);8 d/ M( a- D9 E) v2 m& R/ f. N
0 @) i+ V* S2 c# t3 J
/* Enable synchronization of RX and TX sections */ $ i: q$ ~& D& U1 Q7 E6 V/ [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 T9 A# A9 M6 b9 u1 t3 o- r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, J1 J( ]% y% r4 q5 W( P% M" uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% a/ X4 D& q$ H" o# S! F& w# U" t** Set the serializers, Currently only one serializer is set as
2 ]# z& @% [- k& g0 H+ b** transmitter and one serializer as receiver.
$ j/ D$ E& N2 n/ S3 A*/9 M& S# U- Q5 H. m' @0 r! T+ X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 A6 }' w6 r0 t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 Y, j u0 E6 R* |** Configure the McASP pins ' C9 l% r6 T$ S! ~0 U/ G1 a$ S; z6 ~5 Z
** Input - Frame Sync, Clock and Serializer Rx
) v# E, ?- e' W# Q1 D% l** Output - Serializer Tx is connected to the input of the codec 2 J. u" P4 e9 I6 y P& @4 E# B
*/! V1 ^. I2 e0 \0 H0 E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 t8 r' A- x" q2 UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 s6 t! i5 `/ h B5 b. O {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: F! t7 P4 L1 v8 M" L, m| MCASP_PIN_ACLKX/ w# j# J3 c/ E9 z4 Z( f
| MCASP_PIN_AHCLKX
V4 J) ^2 _) e2 v1 A. Q$ e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) S4 p9 |( i: R: D+ a. p1 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - g- r- C+ S( S& g8 j
| MCASP_TX_CLKFAIL : q5 p" b3 ? y" Q
| MCASP_TX_SYNCERROR
8 [8 X/ u, R+ j! ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ S3 r2 R S7 i* Q: V0 |0 ?| MCASP_RX_CLKFAIL
$ B! k# i. ^4 w( k- d| MCASP_RX_SYNCERROR % d- i+ j% B% {
| MCASP_RX_OVERRUN);. i! r7 I, ?4 H6 {! j m
} static void I2SDataTxRxActivate(void)7 I5 A3 t; W5 p9 a
{* T6 |9 T$ I8 X* U
/* Start the clocks */
/ _1 }( N: L1 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ Y9 ]# S/ `0 o8 L3 F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 h; b0 b( p( p, ~! R% oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! L+ f: C2 z v$ S% V
EDMA3_TRIG_MODE_EVENT);! H+ R* u) `) J) }% x+ Q. {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 e. d; j, K( O' B. uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 H5 H* F, s9 N! _, aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 p9 h8 y+ C2 o4 }: sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- V/ `! t! S/ y0 P3 x) v$ D4 D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. G u6 z( _9 n( r' [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 g$ H4 A( R& E# X( G! f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# B. c) Y* t* I4 N4 f, o7 u} : y% y( A8 a4 S- p: P& }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 {; o' S% q- H, h4 k3 E3 x6 b
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