|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 B* F* |+ f6 m
input mcasp_ahclkx,' H% b1 S3 T+ `7 U2 \2 J4 q# c
input mcasp_aclkx,
; j9 d" s H3 Q" w" i3 }4 winput axr0,
4 o, e9 u0 ?' ]! j
/ E& a" L0 t) w5 M* ]6 Foutput mcasp_afsr,
; @$ q7 ]0 b- k1 b" l6 loutput mcasp_ahclkr,
! K R, K0 E; H# [output mcasp_aclkr,2 w5 p, Z6 x, C4 f
output axr1,8 W Z! y" p: h# ` S$ Q/ D
assign mcasp_afsr = mcasp_afsx;: n) j/ c9 B" M6 |5 `* v2 S: S
assign mcasp_aclkr = mcasp_aclkx;( r1 y- Q( M" y- I. G
assign mcasp_ahclkr = mcasp_ahclkx;
$ I) ~, x2 E- F9 ]assign axr1 = axr0; ( {4 {+ R0 o+ q& f; p6 D% ?3 `9 r
5 x. O8 Z; E0 a4 p; {; c& p/ ]3 K9 ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! E! o; g7 `6 \! W% `9 V
static void McASPI2SConfigure(void)
" B' X( O7 G9 a% |- J9 [{
( _, o0 W% f, v6 F9 M4 \- }McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ D7 A* R B/ }+ B3 s, xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- H, L7 \4 p* _ F) s: E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# |/ u9 E% ^' G& g- M: H& N/ zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 k5 q8 P" ^% R4 u v! N/ aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 R j1 D5 l R9 c1 ^
MCASP_RX_MODE_DMA);
& Y4 o w9 J$ k u3 g* xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& X% }3 ~# R- G; uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. _2 P9 e% X, S; I. N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - T6 E2 L* c" C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; F$ U0 i" \6 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 v9 Y6 H5 Z) a: @# I& m+ VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& R. d9 X! R, Q# N1 d+ kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 P+ l" b8 O, ^8 F \3 R! E- WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
f# G y8 Z8 D% V1 V6 rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( Y, P% D" q. c5 c- J, ~0x00, 0xFF); /* configure the clock for transmitter */
6 ^ r8 k9 x$ F# T9 DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ K" u6 H- v9 e- ^, RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ ~( o% l/ |5 T9 U" |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
b( F2 f0 s9 M' }: \0x00, 0xFF);
2 @+ Y$ q2 l s) [) A
8 v4 Z1 u+ F. M) c0 y/* Enable synchronization of RX and TX sections */ & @: u% ^- T! K7 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, H' i. L: i: f4 U- e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); F* i6 v' h1 v% B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% }* [; O' O% H ~+ H) x9 X6 T** Set the serializers, Currently only one serializer is set as- L* `; Z* n# E2 ~0 ^0 Q
** transmitter and one serializer as receiver.2 w# @ X; q! E
*/
$ v b; o( F2 e+ i" OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. _0 E; L/ Y7 v- o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 n/ x: `% {( e l, B( S Y** Configure the McASP pins
" [2 W; M# B3 Y0 D** Input - Frame Sync, Clock and Serializer Rx* s; v! |3 e% W3 T0 S
** Output - Serializer Tx is connected to the input of the codec 7 u3 a5 N4 J1 l" C
*/
* K# y9 D0 W# Z+ c+ ^8 B8 vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 y" w* Q+ l* e% _7 ^6 _' J6 M8 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 W, V3 _% o$ N3 Q. X9 c0 A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 i( P3 d# G2 E g. h
| MCASP_PIN_ACLKX8 p2 e- P+ I7 S/ l# O* u
| MCASP_PIN_AHCLKX
) I$ s/ X6 ]2 |+ \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% I: L0 U- X5 ^8 ]# g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + S% ~, L! y+ R# x6 D+ T6 U
| MCASP_TX_CLKFAIL 7 ?' n4 t$ O) E# L: |
| MCASP_TX_SYNCERROR, x# I6 Y2 s: g% A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 L; C/ P2 @" G
| MCASP_RX_CLKFAIL+ _) o2 F5 x6 N5 G
| MCASP_RX_SYNCERROR
! m( y& \; \! a7 }0 G| MCASP_RX_OVERRUN);
6 e! A! q; k' {% n) w# z2 [} static void I2SDataTxRxActivate(void)/ |4 `4 @, p( ~9 n+ m7 i) `) K
{
4 q: s. H- M1 p# W+ k2 e1 b; a! d% ^/* Start the clocks */6 X$ e* f0 w) u9 j# b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( s# C- i$ |! F Q: H$ m8 E! u2 C& H2 [+ wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' Z: W, b2 i' ]& M& \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# X9 v( c% }" t9 }4 w r( ?EDMA3_TRIG_MODE_EVENT);, M5 p+ k" D4 S* O8 M% O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 Q1 H/ Y' s$ h+ g: b0 ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 B# p1 Z! x5 f1 I: f' l) o: nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: Q' @7 f* h( o w; T! f: h( x1 s1 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! d" _' V, r' v8 G/ J* Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! I- S& N/ I) J4 @/ b( s. N/ @5 oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 [7 U+ b3 H9 m a# oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% K) J% c* M8 r+ O
}
0 @& A" d' ^# u: C l4 U( _1 ~( d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
! _) q2 V9 M* t7 {6 y, @ |