MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
4 n+ f( d& T  Y% L4 E7 Pinput mcasp_ahclkx,
7 l' _3 _3 E3 u( |input mcasp_aclkx,
$ v: K0 k  ~0 L: T' ~input axr0,

9 M2 W# A$ n' ]$ p( g( D: Uoutput mcasp_afsr,
output mcasp_ahclkr,
( j4 g/ s8 _) K5 x+ ]' {" j1 Ooutput mcasp_aclkr,
4 |+ u- O) ?$ P6 O9 voutput axr1,
# L' e5 c1 W# y2 d, w6 u

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
9 ]: J  H0 V; x- ]2 R- B6 gassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

6 z2 q: N' x" X" @

static void McASPI2SConfigure(void)
{
8 m$ S' S& |) p0 J: J0 n5 D0 xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
; N1 |- K: q3 ?/ b- Q7 W$ x% ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
+ X! U" s4 n! j% N! p- I- p4 bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% t; O0 n0 ]; T3 g# aMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% ?5 n4 Z$ A" p4 l# nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: F# o8 Z4 ~% M. @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# c/ n% p$ d+ d! Y- e5 X$ A8 NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
$ i; D$ s9 n6 Y2 L5 d+ z( f4 tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 }$ K$ n% n! t5 \* E8 wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 P! i; H+ k1 o! B1 y' bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. }; x% K6 i9 w/ y0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ t: J/ [) ]% f" A$ v1 p8 g7 kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

& [: i2 \" ~% m# }) o7 x9 u( x/* Enable synchronization of RX and TX sections */
8 n: ?5 `1 u- f, d. AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
, s6 L, }3 ~9 Z1 }** Set the serializers, Currently only one serializer is set as
' V5 R% c% Q% }+ v% `- T8 y** transmitter and one serializer as receiver.
9 V% l  \8 v4 [# o; T. n; y*/
) \* a7 l# {; E' W' G  X9 YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 X& `2 m& D: D6 q  Y6 x9 I5 @3 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
5 l5 Y5 o$ Q# W6 C** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
7 |" o8 `8 {, [) W2 f$ x** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( E: L2 b. V! E% e. GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. `$ B& J2 }# S/ x- BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
, |/ }2 B3 a- Z" ~7 B7 }. i% k0 d| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
+ w% k) J6 O* ~2 x+ m6 `4 _| MCASP_TX_SYNCERROR
9 ]# R2 L* o' u0 o% M- M| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
1 q) a' [* T% }" J1 y) {# F2 w| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
  Q  ~- L# @( u/ s* m4 _+ |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* a1 O: V. k0 Y& `" F0 \- hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
% h  ~9 w, p8 f* }; BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" ]) ]) P. n, y2 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
6 s4 M7 `8 I/ z8 f& ~# T4 G3 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ \# Y8 q! A7 E" _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
2 I$ i/ q# P; iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
) G4 A0 C; {( z5 I" c0 oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) j& e) Z, p" U}

5 V( Y* `6 Y0 M; @

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.