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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& ^! @/ @" Q% Q! `) V. i7 V; x0 N+ P
input mcasp_ahclkx,9 c8 a6 C7 q5 c& Y/ t+ I" t( u3 \; y
input mcasp_aclkx,0 c% {1 d: n& g4 E
input axr0,( X0 d5 z) F& w; E. f
/ Y0 Y& ]* m9 r7 m. r+ W& g
output mcasp_afsr,' }+ v0 p% x* S( D2 ]
output mcasp_ahclkr,
: u S7 _ A- E$ q8 Ooutput mcasp_aclkr,
4 |2 w& m, [* Aoutput axr1,* E0 }/ y) N4 m8 S9 T- ^" T
assign mcasp_afsr = mcasp_afsx;/ _4 m- Y4 z" F* N, f7 ^3 E+ \
assign mcasp_aclkr = mcasp_aclkx;
' N+ b. o0 v! ~: R. A& J5 A! [3 nassign mcasp_ahclkr = mcasp_ahclkx;) R: ]2 g" j# Z
assign axr1 = axr0;
1 z, r6 n. Y& P
& P$ I8 ~5 Q9 ~; Y+ _* E, k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 I" V5 g3 d8 Rstatic void McASPI2SConfigure(void)
& F) o; ~5 f/ f9 c; w, B& j5 m1 r9 K{
; i3 U/ o. e5 i' w! C& ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);& }* W, A' u1 k! V+ {7 P1 I7 }: S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 K* V3 r& K$ A3 N- LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% ]8 G2 \; B! S# x! F# j5 h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- |8 T' L5 ~5 G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. d _5 c; G# P! t& B2 ]9 PMCASP_RX_MODE_DMA);3 U% i3 r V; e' t$ q3 j9 g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! R, T* t; e' }, H; T/ n& A6 v& mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: r! }. t* v" n* ]" X5 L+ x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. K: `- t1 c% PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- K( G+ j" y# k3 Y3 j1 cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 h6 _& J) D( h E+ U' l4 ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 |# f8 m" T% A' k8 p! t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; l+ Q( x3 b; N3 J$ g& h4 CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # h. m4 B8 x @2 `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 \# O5 I E0 @: c0x00, 0xFF); /* configure the clock for transmitter */! o& j- B8 [ n) W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ k @: c+ ]; y5 q) ^8 YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: K2 C( Q$ j' W5 dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: D5 U' z5 I0 A, _/ c. w2 g0x00, 0xFF);
) h$ a( }) G1 g, r/ `! d2 `/ M2 f2 J. M+ x& E0 U' ?7 U+ d
/* Enable synchronization of RX and TX sections */ / y. V, l( l3 _. X3 }' G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ w# {8 O& X2 [( p H/ YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! r% z& [% X( ]) X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 H% }9 C& l6 S, c/ D+ l# q
** Set the serializers, Currently only one serializer is set as
1 y, }# I8 H8 |- Y0 d** transmitter and one serializer as receiver.
+ ^3 r! k5 E$ k. R% ^7 a*/
9 |$ }: z- M8 g- F' VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! D/ O2 `6 X5 m+ Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 H3 P j4 z9 N* e% q; Y
** Configure the McASP pins / C) I3 ^# N! q
** Input - Frame Sync, Clock and Serializer Rx
' j' ^5 \9 _, M/ X# h, M% C** Output - Serializer Tx is connected to the input of the codec
. k% w' R! R% w6 ]; i" E c3 }*/
* R* u1 C. H( Z0 \/ l6 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); D# W3 M8 `. y9 x) ~: ]# S- G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 s8 h X6 n2 q {4 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% y. j o' v* P' ?; _- L9 p% P| MCASP_PIN_ACLKX
0 n4 g- |; E$ g) n8 q! H0 l. m| MCASP_PIN_AHCLKX/ J3 l, w2 F" a* R5 B' D# c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- s! z) R$ V# ]! o! _) ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 v* ~3 i+ W+ D: R( O! q" S5 \+ W" O| MCASP_TX_CLKFAIL
: a$ ^/ }; T: b8 S| MCASP_TX_SYNCERROR
9 g3 z! B* g2 ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( Y6 |& {, `' F q" W
| MCASP_RX_CLKFAIL
6 S& [9 q9 G$ V, _- M1 ?| MCASP_RX_SYNCERROR ' {9 N8 [9 g; R3 T
| MCASP_RX_OVERRUN);$ |/ Z5 @3 @( }6 f' S8 Q
} static void I2SDataTxRxActivate(void)
& ^, L( g. w- K' t$ }# F- l* [" v{- w9 W( ?, Y8 ]- U0 P
/* Start the clocks */" B ^/ X# ~5 ?0 N: ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 Z, N$ x! B: l$ Z) K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: a# h: `& V& G" n j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, M9 R8 h0 t$ O
EDMA3_TRIG_MODE_EVENT);+ X2 M9 R, g3 U% K* O& l1 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * M3 f4 p4 w8 T* e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 o$ Q+ P5 h9 P& J* N" S" {+ i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 H) H' u: X: h9 R3 h' F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( N) v7 K0 B1 P) g! `. J, D8 }8 G( Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 D2 C2 O5 C5 h8 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- X7 B; }% L; a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ k6 k( r" m% [* B
} ! S0 i, w, ~: x2 Z9 E$ d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 \* M+ ~3 h7 S( j. n' H" {
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