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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ B3 Z5 c7 [% [; p! C4 [) r
input mcasp_ahclkx,8 Y9 x1 C5 k' f7 Y0 \9 Z+ b$ q( ~
input mcasp_aclkx," z" d# v( j( k. g+ l
input axr0,/ T& U* L- p- C! W6 ]4 y) ]4 ^
: V8 | \/ T! T8 P
output mcasp_afsr,
: X v2 k) r6 v' Ioutput mcasp_ahclkr,
; E$ I+ `+ F! W* H$ Soutput mcasp_aclkr,% |6 j5 k$ ` }/ ^2 e
output axr1,
+ f7 s0 t% _! ? assign mcasp_afsr = mcasp_afsx;. t" V- {: b; E, [1 H; y
assign mcasp_aclkr = mcasp_aclkx;) A6 ]$ W. K, W$ N$ s
assign mcasp_ahclkr = mcasp_ahclkx;
0 C- r. x$ l- F+ C, Fassign axr1 = axr0; & J9 }0 B4 p0 N
6 m0 r5 d5 g0 \( ]) z: {8 G8 J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ O! i4 v! d! V6 k& R8 p. G
static void McASPI2SConfigure(void)2 S6 t: u: Q& g) F4 z& W
{
8 ^: ~9 _7 B" C+ K: {McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 `9 v+ v) [$ n, Y# Q8 m5 s% KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# ^4 G7 a# G7 C( QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; K% u- M+ j3 Z$ b9 _ Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% h' g! b1 ~0 K" ^8 C4 ^( QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* j% w. B! n+ f0 VMCASP_RX_MODE_DMA);
4 Z' _7 T( @7 _. K3 r X6 V8 b ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% D. t9 D$ B4 O) ?. l7 z' F; @: G% X# ]7 ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ H8 I5 p7 m4 ~2 V% m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 i r5 q D( I' ]4 U \. j+ @' H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! f- s, E( c' F7 ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) e* C, U' ?8 i6 p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 h# ]+ g+ |, q A" a# ]" tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) x7 J9 K/ f+ Y- U# S: C8 ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% o4 U+ r/ w$ d+ w6 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& L, o7 o' Y7 c9 L
0x00, 0xFF); /* configure the clock for transmitter */
1 z! I, F3 y( j% D& p3 Z( f2 g; C yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 J/ Q4 ~, f; R4 b! P$ M( OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) D: W9 {* ?) s/ j8 @ e5 ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& a' z) D4 o4 d! K! O
0x00, 0xFF);
$ M' L T' G) a2 T* ]
0 j5 t9 G+ P: T0 @9 d. f6 M, N" j/* Enable synchronization of RX and TX sections */ + U% [4 h+ c7 j- ?' N; n. E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 ` i F) g- jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 {; E4 w0 k4 u" k" X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% p, s0 I+ L+ R% W. {, Z
** Set the serializers, Currently only one serializer is set as
7 x" @! f5 t2 x% ]. S** transmitter and one serializer as receiver.
0 H0 u! G/ L+ @: q% o& K, {*/- `$ ]( b% F% H0 E0 u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; z- t( {. K$ {# KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& l, r2 P, t. ?
** Configure the McASP pins * G8 V* z, z6 R7 z
** Input - Frame Sync, Clock and Serializer Rx
9 n$ p% I+ y: |: b- e0 _** Output - Serializer Tx is connected to the input of the codec 4 K( | d5 |6 h" N ]6 r
*/
6 G$ @; c& ~: H0 i1 p9 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 ~1 a8 L( Y5 H; E) L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 N) [; M( E- U# iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX E, B$ b4 V' k2 a8 C9 W
| MCASP_PIN_ACLKX1 ]4 B( q z! U. e0 E
| MCASP_PIN_AHCLKX
1 O, l7 R5 i6 D8 V5 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% \) s; }7 T4 }) xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 N5 b3 g/ E: L" x8 \| MCASP_TX_CLKFAIL
0 L$ a5 z! k" ] N% W, {| MCASP_TX_SYNCERROR/ f a- r/ M/ ^8 D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
v6 s, b J/ h3 M) [5 d. ]| MCASP_RX_CLKFAIL
4 v) b$ B1 n2 s& x& i| MCASP_RX_SYNCERROR
4 t S* I4 F0 y1 n7 I5 w| MCASP_RX_OVERRUN);
! w2 }& X# ~$ l) z/ X T} static void I2SDataTxRxActivate(void)6 l" \- W( `& x# R. _$ w
{
! o" [% Z7 G3 P0 S/* Start the clocks */
7 V, d8 [7 Z8 j+ HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 m# y8 D- C- iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- i* p0 b- O( u, e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ Z+ Z- Z( X; z! U7 N
EDMA3_TRIG_MODE_EVENT);
) z. [3 f! H& SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( L2 k$ @4 ^6 z& g8 a: o4 q3 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- B: j# l4 T7 `4 gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( l3 g3 ^7 C" K1 [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) o4 |, d O# A, U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 z# R8 A$ Q7 j3 p' P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# s$ _" T/ }! P$ Y- B p! d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) u3 n" n# ~# o/ O
}
' T7 e/ \/ Z. K( H& j" b8 r; F, I. U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! i; @+ v h. A' u0 _
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