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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 e) N! [7 @3 g' w8 W& K! ]6 a
input mcasp_ahclkx,5 D- r( W. I9 P% x% M
input mcasp_aclkx,4 I0 e+ E" M9 B" s
input axr0,
4 @& a6 a1 G6 }! m3 N' r0 w/ p8 }. l* }7 T" T
output mcasp_afsr,9 c9 B# q! a& q' L1 h
output mcasp_ahclkr,7 y5 z7 ^7 E: T b
output mcasp_aclkr,$ \* @" m: U7 j$ p
output axr1,
; f. u# c& G& a$ \% w$ H% ?( { assign mcasp_afsr = mcasp_afsx;
7 [1 t) v1 J8 Y Aassign mcasp_aclkr = mcasp_aclkx;
7 G0 X1 _: S0 O# e( Aassign mcasp_ahclkr = mcasp_ahclkx;! a* M; _3 g8 T: M; J2 p) J
assign axr1 = axr0; # } B* Z1 g- {
. b0 t# ^0 F$ }5 G3 ?. }( H5 b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: X% w3 s& |/ q, nstatic void McASPI2SConfigure(void)
* t; y& i+ o3 m3 g$ j8 G0 _. A/ q{
. l4 R) x9 Y2 j5 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 F6 T, N7 Q" K$ r+ {! VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- o7 {8 Y( k& B# t/ g2 n- g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( p4 J; v) B5 I- r j! M, ]! Y! ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ V' X: M* K; H. U, X. ]" jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: z" u) a8 M. E1 D, ^) ^" Y% O6 nMCASP_RX_MODE_DMA);1 _% V: M2 Q" z+ y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' l+ q3 ]# C( T' c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; G7 A; n5 j& B9 N r. xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 s7 ^! Y% q7 P8 @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# W% l* o6 ?! Z0 A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & r8 \9 a$ c0 e" {" L- v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ V4 K- x6 Q$ I# {+ J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- ~5 `* g9 k$ u7 bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & R8 Y u3 \6 x$ }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 g s4 z7 E2 P5 v
0x00, 0xFF); /* configure the clock for transmitter */
6 s. E% b1 _/ `; cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ }5 c ~" L6 q. }9 d' f: N% t: lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! D- t* s8 J. Z' W) M3 K! jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- u. v3 ^0 E7 ]7 J ]+ R
0x00, 0xFF);) m- X3 d6 P3 [+ b$ k9 z
& ?! {0 p. l3 a! n/* Enable synchronization of RX and TX sections */
1 B! P& b+ u0 a* U, H: U7 }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ V: [0 v8 X4 I' P8 \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 q% }5 p8 p& h. q" g) h5 D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ `, p- _, v1 ?4 q
** Set the serializers, Currently only one serializer is set as
: Y/ j7 p! m' Y# E0 D** transmitter and one serializer as receiver.
( X1 B8 V, p3 C, a*/
' X2 ^3 e" J4 xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ q1 T% k, t" a: N, B- a M' ?# e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 T& b! b. T) U
** Configure the McASP pins - V8 }( B( w$ u0 e' {+ E* d
** Input - Frame Sync, Clock and Serializer Rx ?$ \1 T' O' F
** Output - Serializer Tx is connected to the input of the codec 2 j2 y( S; {& ^6 o: w7 s' N
*/
3 `2 H4 \# Y* FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 ]; O G8 u. H# |& s5 V& {; h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" P9 J7 u3 D6 J6 y3 p; u P* }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX ^( g9 n' r% D. W
| MCASP_PIN_ACLKX/ A& ]/ t5 O; c* x4 c) q+ ~
| MCASP_PIN_AHCLKX5 {9 R8 x5 R# {+ l& ^, F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 z! m, b2 j7 }" [& I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 i! I, \+ K9 f+ A _| MCASP_TX_CLKFAIL ( D+ R! r! Y. s$ `+ U
| MCASP_TX_SYNCERROR
3 L" D5 Y- g( c0 k" k: Z) N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ V3 A; B8 S+ \; g, y| MCASP_RX_CLKFAIL l1 X$ d+ n) g3 e) u
| MCASP_RX_SYNCERROR % |. l1 L% z5 N# B9 A+ `- |
| MCASP_RX_OVERRUN);
1 g4 |, N3 j0 e} static void I2SDataTxRxActivate(void)
+ M' J! [' f8 Z6 B3 i{5 I" y& ~& ?! k; b- y* I
/* Start the clocks */9 d8 f* l/ ~6 T$ G9 I3 q+ t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 e8 w6 b+ f+ nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( G: F; M- C+ ~3 D" W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- _. V* U0 x0 U/ z
EDMA3_TRIG_MODE_EVENT);9 | H' I @: z. P( c L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* p0 ~1 E) J) h& @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 d: @2 n' [9 D% B( p) FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 g. |/ `+ k; U; `" FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* w2 X4 ]8 P' P, ?' P- u) _. U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ ~ U/ ^2 n' F L4 }( iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! k% W/ Z7 E- ]7 z U! E5 ?4 f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: ?8 K3 I+ U, c: p" S. o
} + Z/ S) j* Z7 N, n! x* j) V) Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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