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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) n" M& w# c) ?9 Jinput mcasp_ahclkx,
: a- T- a9 l8 q, H* jinput mcasp_aclkx,( P$ U* b% j2 q0 X! C
input axr0,: S6 q7 V+ \' \2 m, b, O
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output mcasp_afsr,
& O# t9 N3 H8 Z+ }5 uoutput mcasp_ahclkr,* Z, Y5 |# S, P8 [- |) N8 C$ [
output mcasp_aclkr,
% |& _& b8 I3 p. H% Z% V toutput axr1,
1 i7 d$ a$ `% Y+ m: `* c x assign mcasp_afsr = mcasp_afsx;! H: f$ E4 @! f% ~6 T
assign mcasp_aclkr = mcasp_aclkx;# c6 W; `# m# [& Z$ } n0 ]1 H
assign mcasp_ahclkr = mcasp_ahclkx;9 p: |# W6 D7 D! z. t
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + s3 G. l4 z0 Z' j* L
static void McASPI2SConfigure(void)# v" |8 m3 M {& ?7 c9 y: t, ?
{
4 b5 k k8 \4 w0 Z5 }" P$ D2 G# QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 M: G% a' R6 P' `; }0 z% W6 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ w$ ?7 R- l, S1 G" s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! b. X$ L( L0 x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 ], o9 c; [0 j/ t R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% C" v, \5 ~/ Z# XMCASP_RX_MODE_DMA);2 Y8 |7 C, x8 k, ^9 d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, [/ i- |- O2 W% ~& ]9 y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 s8 {% F( X9 C/ ~9 a: l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 T, Y+ {2 ^ h/ {% I+ J8 q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); S. D! C1 x+ s+ X8 m0 ^2 F9 w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : s$ S) Z1 c& V9 B0 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 b- n1 b0 O! m9 u1 C1 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 c& J* r2 i2 F; M6 U5 {* f( FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 Z! Q' f. C h8 |# U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ m% T/ a% p ^! O; G# }0 q
0x00, 0xFF); /* configure the clock for transmitter */
# L. {1 X8 P- x H7 O: PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: a+ r, B( c9 g6 }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : e' H% x$ R( [) K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& X, U( p; n# c1 p' C/ \8 k0 c1 ]
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
$ ]0 J9 C2 Q# A: h; XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" G. y \1 R0 C) y- s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 r5 _: }/ O8 W( R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( m/ l# G. b" M2 n0 X! e$ O- j T** Set the serializers, Currently only one serializer is set as5 R9 T% r3 \* M" a9 Y# x
** transmitter and one serializer as receiver.9 p0 S& s' G& Y2 N$ M' y8 |3 w3 k
*/
8 ]$ G T; l0 T. u0 B6 EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 W8 [( i3 Q4 b6 t1 U: JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 m, U) _0 y/ F0 J2 k3 e) `7 w** Configure the McASP pins
9 R- r; [9 b# k** Input - Frame Sync, Clock and Serializer Rx/ a- U) _/ D' r0 p
** Output - Serializer Tx is connected to the input of the codec 6 F: g8 p! w- f
*/
) i7 S7 w4 f+ `( W6 P; WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# a/ r u- J& _9 j- N5 {. EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 P2 A* E: `! Q2 c- e( TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" g- c% L% E! a, ?| MCASP_PIN_ACLKX9 B6 h+ Z" x% a% Z6 R; P: W! D
| MCASP_PIN_AHCLKX& F# x8 O, j) u b& O/ l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( P, v- F5 A c& e( z# Y M$ Q3 IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 z4 @) C0 O0 J: a7 l3 F
| MCASP_TX_CLKFAIL 1 l- k3 x5 V, ^( o# e
| MCASP_TX_SYNCERROR
8 y* \( C4 _# A0 t. L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR O9 w3 W- F) I5 O5 A2 x0 z
| MCASP_RX_CLKFAIL" |" t* j2 j |2 h
| MCASP_RX_SYNCERROR 4 l) [: D7 x/ J: M7 [/ M& k& ]9 \
| MCASP_RX_OVERRUN);! S( U9 e/ N) J2 B6 C- P7 t
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
/ ^4 z! I$ a; Z4 ~1 vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# Q; Z7 v! m" z+ R. s: [7 pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ h9 d2 y. G* N: r% `" s# _/ BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: i9 l9 Y% V6 ^! M) Z4 ? D7 o# l
EDMA3_TRIG_MODE_EVENT);
7 i8 |- {1 o/ d% I! ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : r! l- c# N) F% k+ V% {0 Z3 X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: u* X! ~- \0 g- a, QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 L* t6 Y; ^% ]. d, Z2 ?7 c. d4 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// l0 v1 o/ a) k. |; v9 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
W7 u! k! K8 G" t5 z6 f' x2 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, i. A! l& f: F OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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