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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ ~6 D2 r' J* |" G. Uinput mcasp_ahclkx,
; T) ~4 ^2 D7 W- D( dinput mcasp_aclkx,2 o0 v. m6 U3 Q, i+ f
input axr0,
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output mcasp_afsr," F- y. J$ W. u% v6 }/ q
output mcasp_ahclkr,) W+ E; L# b2 j l5 B2 i
output mcasp_aclkr,
& r5 g# H& R2 f8 A: moutput axr1,% o6 ^6 j( w. W! Z0 ]0 P5 Z
assign mcasp_afsr = mcasp_afsx;9 m: h% |) u3 f! i; l
assign mcasp_aclkr = mcasp_aclkx;
" l& w" f6 y: d fassign mcasp_ahclkr = mcasp_ahclkx;
# a9 N& i. [1 m0 j2 H5 V3 i _assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : m I$ D0 E% P. `$ i
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. f/ x% j# W; wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ g: D( j* o# g& g$ t/ X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 Q7 q+ t, K+ n0 e" ?) ~) n# x2 L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 Z! V/ v6 P7 xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 ^/ c2 t, Y( `- N( b5 p0 N
MCASP_RX_MODE_DMA);# u- u7 k9 c Z+ J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% C0 n9 N' g% D) t5 ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- ]3 [6 }7 Y1 y. u0 aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , F0 U+ Z6 ?1 n4 ]. ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( A4 o5 s" g. G( ^. v* b" nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. X+ s3 Y5 Y! P! `' ^7 @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, R- S" ^! X5 h: A7 m# A/ u8 N, WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ K* P& P* Q! A) ?" T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% j# N8 K) Y% V- p3 u) kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 b3 i: e2 d+ I! w8 ?) r d* P. M0x00, 0xFF); /* configure the clock for transmitter */
2 [- f* }, {( J4 Y, I; T; ?5 V$ IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 S9 E& `! D7 L1 c2 y4 kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 p1 [5 F( l% _7 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 O* i/ X3 Y" A, V) N0x00, 0xFF);" B8 C& u7 f3 V" V I
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/* Enable synchronization of RX and TX sections */ 4 F9 J* b' ?) F- o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 e, E6 y/ S) dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% [4 P* c( \, _7 l8 s+ T8 p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** U; Y$ H) n4 p/ M/ |9 }
** Set the serializers, Currently only one serializer is set as
8 t$ @0 c- X, D) r* [- a; ?** transmitter and one serializer as receiver.9 G. O" u4 `/ c& F% o
*/
) J1 Q! x: ]& D8 lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- q1 r7 g1 \4 R# H) lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" Y4 g2 X, g& J) J. }9 h
** Configure the McASP pins
* ]( t' v1 H) C0 {1 l/ G! |9 v** Input - Frame Sync, Clock and Serializer Rx
% Y# S0 E$ f5 _2 M4 ^** Output - Serializer Tx is connected to the input of the codec & f0 x6 d: w! l) u& ^+ {7 A, o/ f
*/
* E) f, g+ i# R3 d, k: lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 i( j6 m& Y3 }: A4 C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 M- O, ?( Y, K. E! gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 J/ Q- M* M- y4 z| MCASP_PIN_ACLKX
9 x5 C: k( j7 i: @. A7 L. R7 G| MCASP_PIN_AHCLKX
% |9 `3 {4 D8 I$ f( x0 @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// y8 s$ A+ }. }+ ]+ H. }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 U2 Y/ ?. ^( D# d: L" \| MCASP_TX_CLKFAIL
7 z# S7 e% b7 t. m1 i" O8 D- O( G" o1 H| MCASP_TX_SYNCERROR
+ |/ a* u- R$ w6 l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . y, A$ g/ S) I) d
| MCASP_RX_CLKFAIL
3 g' X0 y, w; C7 R9 M| MCASP_RX_SYNCERROR - k4 L& v+ Q2 n; T; |2 k: C
| MCASP_RX_OVERRUN);! j. z9 s& G$ W% }
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */& P1 M. [! b' n: r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" b9 X, V0 j' C1 i- n0 P5 n8 [8 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, r% y1 t4 S& @+ QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( B* q5 y9 n) n5 \& E
EDMA3_TRIG_MODE_EVENT);! m9 r4 J! d3 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. r6 }8 [5 X, @+ V. dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- l: r2 |/ B" @) a) d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 z: p$ I6 V, H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& U' H) G, a2 b2 D& gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) X" {: }$ K5 s0 X+ g3 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. q B- H8 }' E& P" f6 X- sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 \: B- {7 W+ J. `* s M
}
( Z7 M# s# g1 A+ C, \' ~& x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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