|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# \. ]4 P* G) o, p$ Ninput mcasp_ahclkx,2 r. G. e# A4 q1 I$ J
input mcasp_aclkx,/ v, A; o- _6 S9 G9 t7 u4 B
input axr0,
: X. H1 y$ U" D! H, k+ d# u# ?9 T# g6 D0 f; m& k
output mcasp_afsr,% B" m5 s1 J4 q% t. p6 o
output mcasp_ahclkr,; T: v- B( R; n; |3 w
output mcasp_aclkr,
% m! \0 q* F2 B5 o4 ?% q. boutput axr1,
* C' b0 v7 T' z; r' t8 Y6 w5 S7 C( P* ] assign mcasp_afsr = mcasp_afsx;
1 b* m0 D& a E% Y* V, c Bassign mcasp_aclkr = mcasp_aclkx;
i" V8 t8 {' m; X5 O' Rassign mcasp_ahclkr = mcasp_ahclkx;
5 t- O& {& w) [* E- \. Kassign axr1 = axr0;
7 C* J3 H1 r0 q0 e' u9 ?8 W5 X3 B% [3 J) z; X5 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) x. i/ _! J L$ H5 |# {9 x9 T( C
static void McASPI2SConfigure(void)
# A ?- g. w8 i5 t{7 w; ?8 Z& c- U% ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( n5 `# V9 B+ d$ Y" fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; s- C. p7 l' ?% z/ fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 {& @# Q8 N7 S) A& T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* X0 {: b J- s$ p4 sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: I% o2 G6 R3 o9 O z5 A, t
MCASP_RX_MODE_DMA);
3 q! W, O, s; H) N0 Y1 LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 h) ? b6 ~) p) v- T& d4 z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 h/ k# V+ D. _) p b8 r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- s- m# n" }! t0 C) w* U% f0 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 ^5 R7 U$ U) U% J1 [2 J. l) u4 OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: x4 R2 w. R3 J% oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ x: m: v, l9 {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 ~( I( b' N, ~2 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ Y: L, T- R' H- V! v+ Z6 F, NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! D9 @* {3 F1 x# E
0x00, 0xFF); /* configure the clock for transmitter */
, P# B! Q2 [, W- k( iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! T8 l5 g0 Q* w3 BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 q, s' k1 A" aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: D; I# E# G3 U$ j2 |# G; ^6 Y: D
0x00, 0xFF);5 B$ l s: m1 [+ h+ c+ e) d- R
Y. f: X2 X1 G4 a* I" z! T7 h/* Enable synchronization of RX and TX sections */ ; y# L1 q6 P5 f' u6 S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 n/ H7 y7 u4 B% L' r, n6 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. n) V- b2 `0 ~+ J8 G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; @" V6 J @! O4 @. _
** Set the serializers, Currently only one serializer is set as. ?. q" g% @ d7 z! }% D
** transmitter and one serializer as receiver. G" ]- K. ^, ?
*/0 S* t9 S( B) y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: i; A' I P% N8 q7 ?( Q2 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 G4 U0 M0 D& a3 _1 \** Configure the McASP pins 4 o6 _! k, I5 ^) x) X
** Input - Frame Sync, Clock and Serializer Rx6 O, _: Z- j' [9 n' ?& M4 ?
** Output - Serializer Tx is connected to the input of the codec * _1 Q" w4 I$ V* Z3 q' @+ p
*/3 t3 B# o9 s' c% d8 b% y6 w' {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# B) l; l4 y6 X9 s, S2 G8 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 o! K- B8 z! F: l$ @6 _0 Z& ~( X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) T& n7 C8 |" W) c6 `* w, z% a9 d
| MCASP_PIN_ACLKX
3 F, z) \" w4 d1 S| MCASP_PIN_AHCLKX4 U9 U" y' ~; o* B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ ]- T1 G4 ~, q7 L$ f! U4 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ X3 b4 s8 S6 G. X| MCASP_TX_CLKFAIL
% `% o* C( v/ K* b| MCASP_TX_SYNCERROR# W2 m3 ~; n. P; W7 y- Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR J; g$ L x. Q4 i
| MCASP_RX_CLKFAIL
: }% T8 t3 f1 G f% y% n| MCASP_RX_SYNCERROR 1 [# m! s* x6 K2 s# z- N
| MCASP_RX_OVERRUN);
$ \/ w' U" t: I5 n3 Z& y I} static void I2SDataTxRxActivate(void)* k* \& @1 ~1 s- d& }2 U% r, F+ \
{
7 t. Z9 T0 A4 y; S q2 ^/* Start the clocks */$ l! B! K7 m5 {& U1 J% P: V( k9 p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! O# J2 Q. e6 z- i# B7 x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! t Z- o& d; P( C" c9 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. J! d4 \: H$ F8 c( C
EDMA3_TRIG_MODE_EVENT);
2 c% a' }$ |6 v* _4 _: E, T. OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 q* w7 w. R! [* z5 ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 W0 Y4 z0 y- ^: t+ }1 p7 Y! IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 m, \; b5 g# i" _0 i& ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ `( |5 A8 r+ {0 @+ i$ y/ \# qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
G2 Y( r# F6 n8 K+ q5 D% D7 wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: M: R' K& s6 M7 c& x5 C OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' h m# b4 Z# k* E+ W9 E- }
}
2 F' K4 b( P- d8 {$ N2 k1 i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
# G3 z) p: a7 _, c0 A+ B |