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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* w! |- V) T) M& _& J, c8 r
input mcasp_ahclkx,
) B( u5 ]) H- s. g% B3 N+ yinput mcasp_aclkx,
: n$ _* `; S0 m2 `input axr0,
2 ~. V0 W f8 [1 ^1 n9 g
Z8 y. H2 k4 Z! Loutput mcasp_afsr,
: R+ A9 l5 u, K0 s I: X& Routput mcasp_ahclkr,
/ Y4 W# m) e& a* K! boutput mcasp_aclkr,
# P3 `& Y; F) J2 N& Houtput axr1,! a" L4 ?( J6 |
assign mcasp_afsr = mcasp_afsx;) e6 C2 Y& V5 Q1 T
assign mcasp_aclkr = mcasp_aclkx;
0 L( f0 C" F+ Q/ r0 S. Bassign mcasp_ahclkr = mcasp_ahclkx;
& S4 D" B8 D5 A' `assign axr1 = axr0;
5 i6 Y4 T( F; Y m- p5 ^
, h8 l7 Q3 x& ]+ t0 z: ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, Q" G9 R3 s: U: estatic void McASPI2SConfigure(void)
4 {7 ^4 h4 w( b1 D/ C- {0 D D o{
; x& R0 T3 H: @, y( C- ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ j. H- A6 `& w r# F4 R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 c+ u" j* `; D! L8 v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 ~$ j( t/ V$ {, F2 E. t3 D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// u m! j7 a: K7 K: V F" X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# B" o7 C3 A8 j1 rMCASP_RX_MODE_DMA);% D$ S5 w& }* e7 Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, _/ L+ m) O+ e V. b* Y; v6 x. n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( H H/ Y* f6 A* C8 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: q" _$ M, y. v2 P5 a8 l4 A* ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& w9 a Z; W7 b1 F# S* z0 \7 o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, `3 I, D5 Z1 s7 E4 W5 i4 Q6 k( lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( a7 ] r: e; |5 P( DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- t. M1 J; I$ S, IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" h3 [7 ~9 N1 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," K) b) o% `5 @5 B
0x00, 0xFF); /* configure the clock for transmitter */
) a1 z' W% B7 v/ pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); V% o. y. R& l# c8 Q' [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 ~& Z8 \4 l: O) d5 x o. I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 k: a. l# ?% G. ]0 e
0x00, 0xFF);
: h- a. c/ @9 Z4 {( M+ }4 Y8 I$ H
' f( j4 ]+ _/ H N4 B) X7 L5 O% P/* Enable synchronization of RX and TX sections */ " ]0 h' g$ S3 G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# x9 D% J& M! y l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& M. ~) X& K! K3 }2 L; ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ l% y/ F2 _* x7 ?! Q5 g** Set the serializers, Currently only one serializer is set as( Z) J% n6 a$ i
** transmitter and one serializer as receiver.1 } N0 S4 p. A# p
*/+ |. m& @6 N7 o( d& K, k1 o7 E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& ?& y# j7 }) m( iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 S5 @# R6 _% q+ f** Configure the McASP pins
, l# D y( o, S, |5 O' i. U5 Z** Input - Frame Sync, Clock and Serializer Rx) u: g5 i4 m* a# e% x# E
** Output - Serializer Tx is connected to the input of the codec ( f4 N( H4 I4 w7 w
*/% W! s$ N+ F6 e" H* `# e0 G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 R6 k5 o, P& j2 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 N# L) ?$ Z( K% M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 o$ Y2 h( Q: u( U) F: X- ~. X7 J8 g
| MCASP_PIN_ACLKX7 V; j0 R8 w; q a
| MCASP_PIN_AHCLKX
1 o- B7 S7 o$ d% ?2 M$ L7 g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, ^; c3 O& f d3 X: ?! zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# T: r" w5 e- V$ P, W| MCASP_TX_CLKFAIL + j& E! a e4 M. o) t
| MCASP_TX_SYNCERROR
7 U+ u5 }2 T) \; S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 F! @8 `0 @1 e1 v, G) z0 W
| MCASP_RX_CLKFAIL8 N( |( T+ L/ C: z* O- d: Z
| MCASP_RX_SYNCERROR & p% `6 r# u$ ~- L& b/ j8 B; R
| MCASP_RX_OVERRUN);+ S4 M( S* x* S
} static void I2SDataTxRxActivate(void)5 E2 _* P5 z0 g& l8 L* v
{& A; L- m7 X8 x1 M& P* C0 a8 \
/* Start the clocks */
3 ~: C5 N% n Z5 P" HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" Y$ [2 m, b l4 x3 A: B$ T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* x6 G) d. ~ r; ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 b6 w$ T$ o- f( m: e5 L& |1 h, f
EDMA3_TRIG_MODE_EVENT);
& H: z& q1 n! C. {3 s! CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% I9 @9 y4 N$ o/ z- ?9 ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% z2 N; @9 {* e+ U( sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" z# ~1 {$ g2 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. Y6 Y7 E8 ?. c+ m- rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# ~: o2 {3 ]/ U$ k, v( ?: {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 ]5 }2 G; ?; i$ B. IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 w! Q9 ]' ^) }4 D% z4 L
}
/ K ~& U5 h5 X/ K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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