我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* p+ u! L; }, @input mcasp_ahclkx,7 \: t" ~$ @8 J3 r
input mcasp_aclkx,( _' p. k, l* s; h- Z% O
input axr0,$ ]9 M/ B5 z N6 v
/ U3 o2 G( j- f" Y' o6 b4 b2 koutput mcasp_afsr,' q2 l6 \+ r9 I8 s+ L0 U
output mcasp_ahclkr,4 q$ N; @- k5 E1 Z: Y
output mcasp_aclkr,
, A$ @; R& N# `output axr1,
1 i7 o9 J3 r% r4 K% K* P* p" z assign mcasp_afsr = mcasp_afsx;0 i3 W# W" }( c: S2 ]2 F- u9 H
assign mcasp_aclkr = mcasp_aclkx;! |$ x8 c5 A- O6 A" Y
assign mcasp_ahclkr = mcasp_ahclkx;
% ^7 _# G4 z8 e) n7 Nassign axr1 = axr0; - Y4 p7 b( Z# Z8 n' ]! Q4 V
% u3 l6 D: O& b6 U _3 ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 `1 \8 l$ `" z4 Z8 w# }' Jstatic void McASPI2SConfigure(void)
j% S) D t* ^{
' n" p& c1 A: R2 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 p5 d& W- Z$ U: g5 M) s7 O3 |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, t, F0 h. z# \# r5 `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
j, Y' ~5 i+ c& z, i$ g; n& I, AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% X$ n' b" k0 r( _ N. b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# D) `, b& {2 m1 U
MCASP_RX_MODE_DMA);% w% g- ]" E% K' b$ w9 f, W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 B1 x; g% p- {- A* m# R% B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 T+ L+ @/ o) m. D: l2 u# NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ V9 n( [- V4 vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 {8 h! m" r- Z+ S* bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 O! g# ?7 r2 h I1 LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ u) f5 D% g- L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 b0 ~- d6 ^( iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& R( T# `( Z! U- E% x8 l& nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) d$ a8 i* y1 z, |- `6 l
0x00, 0xFF); /* configure the clock for transmitter */- C' k8 }' \) k% O+ t8 V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% o5 V+ G" g9 |0 |/ j" I- z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 E) `1 j) ]/ t6 dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* L. L* S% K# a6 K* j) B$ g* O
0x00, 0xFF);
$ ~% J/ U9 ^) \* a2 [! I% R5 j% c
/* Enable synchronization of RX and TX sections */ j; }* g1 B0 K0 f5 w9 R7 E0 M3 c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 i) H. N7 f/ @3 a" O6 g# A0 C5 LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' O3 k; n$ |6 p; [2 _8 k. p- tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) T4 \* b" I8 s4 y1 n** Set the serializers, Currently only one serializer is set as( R5 Q' M5 u5 p1 O
** transmitter and one serializer as receiver.
* p" P( B" o9 H. n! q" E6 Q/ Q8 x*/
# a3 k+ f" u* z7 l4 J& mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 b4 G( z4 l4 A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% U6 a1 @! E- v( d1 n( C# O
** Configure the McASP pins
8 c/ R. p1 Y6 b0 \7 h: F* \% b$ z** Input - Frame Sync, Clock and Serializer Rx$ t- ?% D7 y7 a3 G- x. H4 C! y
** Output - Serializer Tx is connected to the input of the codec ' z7 `) F0 ^" a
*/. Q$ d4 N5 {( q, r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 I( d0 j6 Y5 e2 u5 e- \8 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 m/ f! S; p+ |( [! N) n& F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, \2 h( U3 P& Q) C" ~! g. O| MCASP_PIN_ACLKX
; x/ X' |: X; l3 G3 y% p3 a| MCASP_PIN_AHCLKX
6 ^$ k) S6 k ~6 c- C+ l; L, q" ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ P+ m( e d2 i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 v: Z5 O6 J* Z% S" H
| MCASP_TX_CLKFAIL
9 Q# K1 C+ V1 g| MCASP_TX_SYNCERROR
2 ~* Q4 e- D$ \% s; d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 @6 k: A/ H5 {" g2 e| MCASP_RX_CLKFAIL
3 A: F; l! T" I6 N0 h- I| MCASP_RX_SYNCERROR 3 H2 G; I3 P$ X' i5 m
| MCASP_RX_OVERRUN);6 B9 Y0 N5 p" r7 Y/ b7 m
} static void I2SDataTxRxActivate(void)
& @+ N5 Z6 X$ b) I5 @9 U& W{ X& n- H) F2 C
/* Start the clocks */* L# E u$ l: j2 Z, w# h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* ~8 }- P+ _: a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 _6 A3 Y( u: {( PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, F$ W1 R6 w: K- fEDMA3_TRIG_MODE_EVENT);
9 V$ P% L" y8 z& W$ l' a9 [* JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ n1 `" w! o' z/ g, W% e5 V( {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 I6 c8 L# Y' e: m+ L g sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 @/ }( F0 r+ B# d& T4 q, s9 l7 LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 v; W" V: P0 T3 V$ jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 n0 y \) L( W6 b9 w g! O4 wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# Q! j' |3 ~* H# HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 u2 I% Z, @; o2 T0 g} * j7 I7 `0 M: D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
8 F9 b' W; `( C! ^ |