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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; V* \9 _, J2 B! V4 B/ r6 v# |input mcasp_ahclkx,
& _( X8 ^( P0 w8 @input mcasp_aclkx,
. d$ a: V7 N* [* ninput axr0,1 [ }+ w- L6 D* W7 y
- g& D% J7 {" u9 t$ a: B. A
output mcasp_afsr,, k3 ?+ R; c. {: g8 G1 F7 Q
output mcasp_ahclkr,
7 N$ c8 R- g. b' v% _$ ?output mcasp_aclkr,
/ [# f# b; j; loutput axr1,0 F F* k( J7 ]7 L, x1 S" n8 p2 ~
assign mcasp_afsr = mcasp_afsx;
/ u: ]( e2 p% W1 o! bassign mcasp_aclkr = mcasp_aclkx;
+ c# H' x; s1 O! W6 `6 N0 {assign mcasp_ahclkr = mcasp_ahclkx;% T& R' x4 @8 W' w* i" @& n! n
assign axr1 = axr0;
1 m k3 d2 k( r' d8 V0 ~6 C; y
/ x9 P) C6 B2 G1 p9 c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 R' o4 n+ n0 H! E' ~* Qstatic void McASPI2SConfigure(void)
3 U2 U1 p7 _: r6 \: \6 y5 V: h{! J& |) S' u. i6 s0 I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 I- U* D5 x {* N! tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; p8 W; o0 O+ ^2 j. I$ W( }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) G, o4 |% ?- ~: l P; x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. |# |9 L1 Y! q1 ~! IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, \+ h) l) k9 w h) \5 a4 Q
MCASP_RX_MODE_DMA);8 i$ c0 o3 P+ {* K3 ?# n0 ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
W" R5 T' {/ }" ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( O$ J2 Z3 Z/ c: E( g$ Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 D: d- H5 q1 d: Z3 R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 y0 |8 a. R3 R5 d, @% a4 \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # p) S6 a% L4 L* K, j9 O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 z5 U* N& H5 ?- c; R6 R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. t" B I; J: h1 A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * E$ ] L- t% l( J8 O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 R7 @- c9 V* H: g9 L$ h& B7 N
0x00, 0xFF); /* configure the clock for transmitter */6 }: z0 q& e4 D/ X) W( e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 l+ [' ~, j [9 L: vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & V: K( P6 k7 V5 B! d! L5 f H+ y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 a- N$ q. z" D$ h7 b+ \2 P4 G0x00, 0xFF);' {. \; x) {& E' J t: \* k' E. W
, {. P- r2 L+ F5 m D
/* Enable synchronization of RX and TX sections */
3 z4 V3 R6 B2 M. j+ U9 k" FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 I Z& R4 `. T/ O& o% p2 x9 wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ K% N: `+ M" qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* A, d8 I* T3 J2 O9 _** Set the serializers, Currently only one serializer is set as$ {9 d2 p& t1 B
** transmitter and one serializer as receiver.& g% h$ T; O' ], i0 ^
*/9 R0 o v' S" H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 t0 W' v8 h# {7 x( f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ P9 u% A( O8 b( a** Configure the McASP pins 0 \* q% G1 p5 \6 \$ x" h* `
** Input - Frame Sync, Clock and Serializer Rx3 U7 |4 j/ Z) W" b
** Output - Serializer Tx is connected to the input of the codec
! }5 {1 x6 m1 r9 a6 b*/
) [# C3 \0 m! g* BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 n @6 Y) V9 |) [9 V( y7 O9 A+ EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' U# G3 O1 t& B/ F ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" ~! P! e" z5 O| MCASP_PIN_ACLKX b1 Z* l& Z; H! M5 ]
| MCASP_PIN_AHCLKX$ g7 ?" D# h# {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- Y( Q' W( ~% D/ t, xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ ~3 F; D: E! J4 @+ y* v8 J+ d$ r9 r| MCASP_TX_CLKFAIL + x' y) y9 o/ D& Z
| MCASP_TX_SYNCERROR7 f4 e- c# h" O* J: P8 _5 c7 m2 w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 _1 ]! K' D. [: z4 ?% _ u| MCASP_RX_CLKFAIL# L/ B% y I4 ]1 u3 J+ }) q
| MCASP_RX_SYNCERROR
; j7 N1 a, m2 ?6 R| MCASP_RX_OVERRUN);
$ t( b) ~& I% g: e} static void I2SDataTxRxActivate(void)
{9 [: ?- _' Y. z7 H3 g, J$ ]{- l) [) T [1 b* s+ n
/* Start the clocks */
$ w( D) l. L; j5 u0 R' t3 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ d% T9 q) s e& G7 F, V4 ~: M5 \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. [2 D8 M; p: g) S( c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 ?0 Y I# f5 O5 X# Z
EDMA3_TRIG_MODE_EVENT);
4 I4 `9 [8 H* i, C2 Z' j2 z; QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( s9 n) }) {- [. h) M( o% q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( x7 U) R1 h; g9 g) r+ T& e- d( g( jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 R2 {; F- Z. c, K3 `1 I" X8 ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( b1 q8 f& J. v: S4 v {2 w) ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 Q! Y8 Q1 r/ F; ~( M8 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ f) |2 \0 v; y& @8 I4 KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# y4 B* {+ E2 g8 T/ {' x% y
} + V6 Q; Y0 v6 }6 Q g7 Z6 u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 b, y: I- ^" }
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