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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, ]; U/ K% v* k/ Y3 j. i+ G& ^
input mcasp_ahclkx,# @8 {/ R) h! I0 A4 D
input mcasp_aclkx,
# Y& ^: y2 P$ d/ m7 S3 |input axr0,
& H5 t7 ?+ b* ` B; ^$ F @8 P
( J5 @4 @6 b* S$ |- m" ~; Qoutput mcasp_afsr,
5 J( O5 d- ?5 I3 w) ^2 v# noutput mcasp_ahclkr,
$ h$ j8 X/ d; Z5 \6 ?+ D& moutput mcasp_aclkr,
- |, v& h- Q( Ooutput axr1,
. F. U$ X& R3 `' {+ v assign mcasp_afsr = mcasp_afsx;
1 }: c5 [, ?8 Xassign mcasp_aclkr = mcasp_aclkx;& D! p" _) x1 {" j" m
assign mcasp_ahclkr = mcasp_ahclkx;5 t k8 y r& t" T2 P" }
assign axr1 = axr0; ' }, k& y% ?+ M
( O' y1 {. ^8 Y" W: X$ \7 u+ k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - ~1 u/ F; I' o# f, V
static void McASPI2SConfigure(void)
% l6 {7 d8 k @% z{+ y* `$ D, b- W$ ?* G0 K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, m& U* Q: @3 X4 `5 L" `5 v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 ?8 C. L. i, C/ VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 m& v7 x, y; C7 ?# y! [' B3 yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; Q: J) x: W8 q: b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* y! }3 x: I+ S! H( z( cMCASP_RX_MODE_DMA);
' L3 ]$ {( n2 u6 Y1 ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, B! e, \( p# g/ d- d- fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; w; |1 }/ [: Q# C1 N% S2 U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 ^1 m' ~5 u( `8 E* o0 R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 p1 ]; I, i9 V, L, e- B( O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; w9 M( @9 X$ b: } T. N% F$ EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 e+ A& k$ n, g( e8 G9 gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: \0 t! c2 n$ D. _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: S5 e- f! C' y, B1 a+ eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, L8 q) E( z, a" A" ?% Y6 |0 j
0x00, 0xFF); /* configure the clock for transmitter */
* S' r" O/ g3 e) E- I+ }, OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: s; n. j1 o, H8 a+ b- k, G4 yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 U9 \: {7 G/ q4 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( S$ ^' j# A) |2 b# O7 D8 r0x00, 0xFF);
* N0 ]' B& ^* X9 _4 H) ~+ p9 i& g7 y0 K% J. @9 U& W9 `% k. ^
/* Enable synchronization of RX and TX sections */
" [5 z: X9 G* c! Z. }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- y9 j8 E: u7 ] X, D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 n- q- n4 F/ A% jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) D" E7 j4 H1 \! X' v
** Set the serializers, Currently only one serializer is set as1 _. i. ]/ Z- r3 r& h8 l# e
** transmitter and one serializer as receiver.
4 h% ?! z- v- d, ?( ^, U" ^*// j( Q* h0 ~: o6 o' ], S/ y+ `5 ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# A: u! I+ X! L( [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 j% k" C, F0 I5 F/ i4 W2 F; d
** Configure the McASP pins : m! j) K% A6 W! E0 r9 {$ }
** Input - Frame Sync, Clock and Serializer Rx! ?' p7 N- S4 n
** Output - Serializer Tx is connected to the input of the codec
( O0 W7 @* T2 E* d6 z* p+ O1 O, ]*/7 N0 r6 F* e8 c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& j" }- G) y! h$ z" IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% @$ n: r8 ~& M( Y; |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 s, b) { Y6 A4 N# U' P
| MCASP_PIN_ACLKX
9 _- D% C C/ Y2 x3 G" v| MCASP_PIN_AHCLKX
2 j( V* O. c4 s4 ^5 k! v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 c& P( t% p3 {4 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " m# V/ P& P: t2 {* l
| MCASP_TX_CLKFAIL 1 u5 [3 s Z" n) ?
| MCASP_TX_SYNCERROR
6 e: S; K& @3 O, I8 s* @) a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * k* }! i- Z( w
| MCASP_RX_CLKFAIL5 n8 k% b5 a8 m( g6 c% |% g8 E
| MCASP_RX_SYNCERROR
) E/ U! M8 }; _" X| MCASP_RX_OVERRUN);# {' G5 d0 D3 F. e i- K: G
} static void I2SDataTxRxActivate(void)
9 q, Q7 @3 {! ~, x* V9 S& w0 t+ z/ l" Z{/ k" L/ B$ o0 M7 f- L
/* Start the clocks */$ y) r0 j) N9 [9 Z' M) c' C. t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 M# M8 i- I- E- m$ dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; X ?& y3 \9 b. z; V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ u0 G! x- m* [8 t& n! E. u6 L
EDMA3_TRIG_MODE_EVENT); I2 I1 \5 k9 M$ M+ x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! K, ?' Q. Q' L+ }2 o7 Q8 T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 O' g: V& W( J% j6 X* y2 ^. Y! BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 i1 g7 q/ m6 `! ?# a, O, O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. {/ C8 c0 f- O. q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 W) t6 D9 W/ p% K2 F; C# P4 H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% O: f. U, q# _- W! j3 WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 O' E8 l. i/ m" m
}
5 L- D0 \2 f8 I7 m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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