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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
d/ }1 \4 W1 minput mcasp_ahclkx,$ N+ P1 F7 q' n
input mcasp_aclkx,
4 \) M2 M3 a8 Y, g, j; Sinput axr0,1 k. P" k" {: k
1 Q0 M1 @/ Y. ~
output mcasp_afsr,. X% n4 I# O) _9 y
output mcasp_ahclkr,
5 Y. S! E. k0 n; \output mcasp_aclkr,+ O9 s* k$ a8 {& ?9 S
output axr1,
2 k! {( f1 j9 V N4 t assign mcasp_afsr = mcasp_afsx;
2 L4 ~9 W- g+ T0 H! a" b3 oassign mcasp_aclkr = mcasp_aclkx;
' }3 B: n& k1 P1 Cassign mcasp_ahclkr = mcasp_ahclkx;) g0 C( f: }6 s
assign axr1 = axr0; 3 S, @; Q* Y2 K1 t% I' D4 b
4 _) x' o: ?, [ \/ d- F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % B! n. U! G% n3 `7 Q* H& a
static void McASPI2SConfigure(void)
* Y* D5 k& r9 q# }( p2 n5 f{
$ R7 }, Z8 d& d3 S- R4 JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# P) |1 x# i9 M5 X* UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 [' L6 L5 R/ DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 `6 w# U4 e) F9 v. _( A, y6 E! fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 B: E% D8 m) f. vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# E# N9 N5 o9 k! r
MCASP_RX_MODE_DMA);
/ {) }) d( U9 ?0 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! ^5 z' n' K4 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& [' s& q. `; v2 b y, KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; E' h9 c' f4 K% Z4 `0 h2 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% q, i3 ]8 H5 z" Y/ i+ k( ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( Y$ l4 W' O4 M- L. [6 I) {: r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) t Z3 {) o9 a! z. |9 ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 z& b4 a6 Q2 f) U3 A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* O: Q% W! \2 L# ]. j+ W8 D$ NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. F; S$ l. s- N8 X) J. C2 c
0x00, 0xFF); /* configure the clock for transmitter */* a% j) ~2 A, \+ _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); b( V; P5 |1 I5 h9 u$ `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 B2 T7 T- o" H, o# b% d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. L6 B$ Y8 ~" D7 [
0x00, 0xFF);9 k+ A' h8 `# {. U$ ]9 E
" s, V, w" k( ?, O4 _
/* Enable synchronization of RX and TX sections */
5 z) Z2 p, V+ zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ f9 \, Z- U0 w1 }: Y. X$ B8 v* cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 ]/ z3 [4 h( _. o2 V' IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( I% g A: X( k/ S! q
** Set the serializers, Currently only one serializer is set as
+ u7 ?) |% Y, |+ l7 v& f** transmitter and one serializer as receiver.1 ?7 D9 x( ?3 Z
*/& i9 E; Q- v- \9 m# ^0 ]4 [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 I1 |" ^9 ~7 }* ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 H6 [3 u/ A- G _( G4 Z** Configure the McASP pins
7 {4 q/ Q% _$ }** Input - Frame Sync, Clock and Serializer Rx
4 a, |; E5 y' g$ F! |% U** Output - Serializer Tx is connected to the input of the codec $ X2 I9 H$ i6 R+ d" C+ L
*/
o1 \" i6 L, E% EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 {7 f2 c* r$ q$ EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ P# v- b& _$ K/ tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 i' [" ^$ `/ J$ m: L
| MCASP_PIN_ACLKX+ p4 E6 V. Y g$ x! l0 j& V
| MCASP_PIN_AHCLKX
$ r- Y1 U0 m& F) Q! M1 {: w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 c) Z: I1 F9 x, GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. G8 e- {' f( S: k. r" {| MCASP_TX_CLKFAIL 6 C8 @( k$ c+ l q- k' _
| MCASP_TX_SYNCERROR! A# c% z& p# g5 u% A! ^
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 e% J Y* [5 h1 ~
| MCASP_RX_CLKFAIL7 E4 k9 {( U1 w% x; {
| MCASP_RX_SYNCERROR
& ~- b4 @5 Y7 _2 e2 M- f8 r6 R$ ]| MCASP_RX_OVERRUN);
+ R- [. L+ O0 H5 D" o} static void I2SDataTxRxActivate(void)
2 W5 I+ F$ a2 o$ Q) H{
! ?- D& }" e s1 @/* Start the clocks */
9 g. Q5 t; R, Z5 O# b9 k8 y; `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) P! X+ ?9 q- J2 N. u" ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# P _; Y+ ?( F4 d; f4 c$ V+ EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! C* \3 D( `" @* I, _0 uEDMA3_TRIG_MODE_EVENT);0 k0 b2 g8 T# m! N. ^$ i8 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. V0 {/ @, r( ]/ \7 m8 p: j9 d mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 U- A" ?* D3 U2 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& B+ A( P( Y+ s4 F2 B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* n7 w7 i# o* w$ P. I: C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' F2 A. Y9 d- `+ z' {) bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 _7 }( I4 d, n6 ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 [: k' W M5 {8 h/ Y7 T& m} 5 U- L/ H h6 L+ [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / n. T( M0 z9 J; Q! M9 q/ a* H
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