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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ \& d2 ^. K7 J/ B M! t
input mcasp_ahclkx,
! ]4 ^/ i! o& E& iinput mcasp_aclkx,* s7 h, p" g0 r
input axr0,% d; r) W0 h$ F/ K
, n( {7 m, A" r2 }' f- S, Q2 ]output mcasp_afsr,
% D6 d5 ? h' g) Eoutput mcasp_ahclkr,4 D) h: J' w4 B7 i
output mcasp_aclkr,3 U: ~8 K) n* G( S9 t- I3 l$ h
output axr1,
- p9 x/ _ b9 t6 P( G assign mcasp_afsr = mcasp_afsx;) `4 z: X4 O8 f2 a2 @* M; s
assign mcasp_aclkr = mcasp_aclkx;2 {% S F) H. @1 g
assign mcasp_ahclkr = mcasp_ahclkx;' j; H/ H( i( q9 i
assign axr1 = axr0; 7 [2 B6 c4 S( Z U
, G8 d5 x; G$ j! m4 L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % w5 [6 D% s: Z) n0 d
static void McASPI2SConfigure(void)( b9 ]# q, X5 }! Q) H0 r8 r) i ^
{
5 E+ l3 k2 ~2 j$ o( ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 O/ K1 h# r4 L& U, ~) A$ K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 J' p# u2 H6 ]8 {6 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 ^4 |# X3 L m& m! Y' G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; `, M4 d# {+ t( V' kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. h9 f2 a) Z% }' Z( z$ H- K9 z( RMCASP_RX_MODE_DMA);
6 G+ {. Y; [) o( m# I: W* A! `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 P$ F! _5 h& a; |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 `" p {& K6 ^4 T9 T6 L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ l1 x& y4 t; H. S* u. \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( S/ p7 W+ \ a! H+ |6 A% TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 {* n- \2 {# F) s& SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( `4 B2 [; F# `3 @' T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 ]3 u+ S6 n6 i! m1 l |) |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & E1 J& p* u c; A. w2 R2 u5 B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 d( o- j8 R2 t) V/ u
0x00, 0xFF); /* configure the clock for transmitter */
1 D- c% ?5 ^7 J6 V% k( j. PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* D h6 i4 [2 F( p- `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ J0 ^; x6 u$ _# m2 J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* m7 u7 Q! F3 b$ u9 S$ u0x00, 0xFF);
. z0 X9 Z! `8 a4 Y/ A
+ _) R7 S* t$ I' ]) t! U/* Enable synchronization of RX and TX sections */
8 [2 f! k5 q, `: c/ r' IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; f+ V" c, y0 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 I2 L' u2 i0 z! a5 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) ?$ J# {: G9 N4 p" y** Set the serializers, Currently only one serializer is set as% k$ G8 z8 z b
** transmitter and one serializer as receiver.
8 t* w& k! Y4 M$ O& I; a# y U*/
1 I O( `7 v6 R! u( d' @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 {8 p/ a3 E& u( nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
}" f8 F9 ]& k& V** Configure the McASP pins
: b, z6 P7 I! a3 `** Input - Frame Sync, Clock and Serializer Rx
' Z) n" q& a. Y% w* l, g) L) W** Output - Serializer Tx is connected to the input of the codec 6 H3 a& E/ s5 I" v4 W) P; U
*/
" k. k( V. H5 h) ^ uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% `5 @$ L: L& m5 K/ }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ h+ b1 H( e! O& b7 xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- W2 t6 I3 k' O# u5 X
| MCASP_PIN_ACLKX
( ]( {# l; ^* {| MCASP_PIN_AHCLKX- G. }7 d: m) Y/ U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. f% ~5 |3 P0 \! jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( `1 k9 g) [; b# S| MCASP_TX_CLKFAIL 8 D" J9 i7 t a1 k
| MCASP_TX_SYNCERROR J3 F2 I: s( Z A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * c; m: k" T9 a$ }
| MCASP_RX_CLKFAIL9 i. `. K5 n: G1 R
| MCASP_RX_SYNCERROR
* x* s! d1 J' j* ~0 Y, N| MCASP_RX_OVERRUN);9 ?* S" f" @, {. X6 Z, N6 Y
} static void I2SDataTxRxActivate(void)0 K! \. D, U+ S
{ ~- e! Q. a* n# b: v- T0 g" {
/* Start the clocks */6 o* P: B2 D6 d5 p8 D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) s( a# e- ^+ }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; C- b/ X% G7 `2 F& R& Y: W/ H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ O# G5 L, a" z* {/ uEDMA3_TRIG_MODE_EVENT);
9 i, D! L6 L ?& A" pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . A) P3 X5 a9 t p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 v" H( y3 h& T( U |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; o' I: P2 Y( S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. u+ U% H$ t# X6 {. ~& u u* Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( B8 K- T. T. `5 [) @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% C. Z2 t! _- P% a7 S& N& ?+ k) n: HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ m8 I/ n# X$ `- e}
& Y) i/ |% ^& p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 R5 Q. s" h$ T8 N1 V
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