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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* f Q) {- ?. ~) B8 J Finput mcasp_ahclkx,
( K* [- ^: g! z& i6 K Iinput mcasp_aclkx,
+ ~: Y/ ], R, r+ _6 Minput axr0," Q+ x* \( }% h" K5 H& D
' o0 A Z3 e" i
output mcasp_afsr,) C% P2 H# ]7 @: J
output mcasp_ahclkr,
8 Q* A& k) v$ \3 Houtput mcasp_aclkr,4 }8 d ^- f/ Q) N2 A& \; f
output axr1,; r, ^/ P- \- o/ `5 \" l* J* k& f
assign mcasp_afsr = mcasp_afsx;
5 e$ O8 ~/ A" u1 ]8 Y+ H9 ^/ jassign mcasp_aclkr = mcasp_aclkx;
' B9 A) Z. I5 {1 T1 q% ^; vassign mcasp_ahclkr = mcasp_ahclkx;! v1 l# x& }( O
assign axr1 = axr0; ( f C6 h1 P) M/ f$ ?: l& W9 k* t
0 w7 F+ d6 B, E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 O. i& t5 W% y2 ?. Sstatic void McASPI2SConfigure(void)
" V4 E+ l2 [& N" w% n{, z! U! s, e+ G5 ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: ~; ~" L' n6 a* w6 F; HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ I* |6 P& g5 ~& k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& y, C7 _- E8 D" ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; j' y* P7 h7 @" n. c+ W/ QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ D- J/ \5 h5 ~; R5 [MCASP_RX_MODE_DMA);6 d% y$ z* A" S' p d; @* A, \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; u! L2 A3 y" V: K( |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& `: l% A. |8 R0 [$ WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , J. m, {! {6 Q. I% x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 `% {4 d( t. Q1 D$ c. H" ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 p4 H- P4 j8 f8 ?# q9 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" o% C0 p2 v. ^6 l/ K' ^2 F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ }5 [, \/ S$ L8 j" F, UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 K: b2 k5 s/ I5 [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- Y& }- L# ~4 T2 J/ N6 K C
0x00, 0xFF); /* configure the clock for transmitter */6 z% A5 A0 w' N# |! W0 Q! a$ i; L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& ]0 S8 M! Q; x `) P/ S" dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' H+ k9 x; @1 q% Z5 V; j1 Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! z5 Y) [7 J0 `0 F# g7 ~0x00, 0xFF);
6 q! _7 V+ _; h8 y1 x( K' ^8 G" V6 J4 k) P$ I. \. Q/ Y
/* Enable synchronization of RX and TX sections */
! l8 [# U$ ^4 ]# p9 iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// g+ r: O3 I# F0 B) [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) k) N6 _) R5 w# f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- @( W& j+ q& {9 J** Set the serializers, Currently only one serializer is set as* P6 s' z/ Y* {8 Q
** transmitter and one serializer as receiver.7 v" }$ k0 N5 x: @
*/' p& e- g W& d2 F) C% t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) N/ f0 i$ j. R: L# z6 c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ n( h5 {/ x9 ^+ \5 h, b& l
** Configure the McASP pins . O% A' ~/ X3 h
** Input - Frame Sync, Clock and Serializer Rx4 V2 m: T' \1 x/ w; j# f
** Output - Serializer Tx is connected to the input of the codec & }+ z& b& y! k: W
*/6 X) k( r& n7 o+ w7 X: s& x0 j) s. L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: Z, e: Z4 `/ jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ g: O* H. _3 R1 O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- e6 ~" |. O& W2 y; \| MCASP_PIN_ACLKX# X" A* L: e; k/ }& P
| MCASP_PIN_AHCLKX/ A4 r+ }; r8 G; z: a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- L2 j. u4 N& P: L4 S8 L7 FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# h- g/ v. T8 y| MCASP_TX_CLKFAIL
7 n0 S. [) A% u) T9 |, x| MCASP_TX_SYNCERROR
# L' T, j2 B% Z9 A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % I3 F8 u3 A4 a3 x5 n# I3 m
| MCASP_RX_CLKFAIL7 {2 _. t" q7 K' D7 l
| MCASP_RX_SYNCERROR
' ^$ H7 z0 o0 y( d$ V G# A* G, M| MCASP_RX_OVERRUN);. f! x! n7 ]3 G
} static void I2SDataTxRxActivate(void)
! @' F6 |2 e" k$ [9 Z% Q{9 Q6 y- T. H1 O7 b- X$ k
/* Start the clocks */
! Y( ~7 ]" _2 [- A* SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" P* W1 j1 U2 m8 L4 w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' }" H% l. j) f. u- q0 ^; C# [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 h7 c) [% U2 }- Q
EDMA3_TRIG_MODE_EVENT);
! [5 B( ^1 k5 @+ `- I0 i5 [: iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . w! h% v. \6 D) ~1 q2 f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' m! r0 G! \% L( H# G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 H' [/ s1 e1 f9 X3 ]; v: m% F; n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 C( t+ C6 S! s, nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 G2 J3 |3 q2 p1 v U: B+ LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* G$ D9 T2 q8 |0 y# `* ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ i [( X* I* C9 |}
3 |/ @* v; D; z4 e: ~1 o/ v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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