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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 k! {1 F) s" _8 ^1 I7 ~9 P0 |; a4 tinput mcasp_ahclkx,
1 O# A$ y9 q& ]8 Kinput mcasp_aclkx,: C& g9 d5 \ @. Q/ [4 U' z1 g6 ~5 Z& C
input axr0,1 M" ~) ^0 A; j
, m0 }& Z' N* C: d! P& doutput mcasp_afsr,
1 X& j: n% ` ?output mcasp_ahclkr,1 Z/ d8 }0 w5 I& Q- X
output mcasp_aclkr,
& m& r1 @3 M5 v# c* v: ooutput axr1,6 ^5 B3 ]8 L6 u% |
assign mcasp_afsr = mcasp_afsx;
0 T( a0 E# c/ F$ X7 D- n. G0 i& Sassign mcasp_aclkr = mcasp_aclkx;
& R( O) m$ h. e) j" A" q* P; Aassign mcasp_ahclkr = mcasp_ahclkx;
/ ^5 v8 Z6 r. B. N' {; ?3 @* Kassign axr1 = axr0;
- w. O% ]- ~. `
t( b5 x) h7 @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 L9 _/ Z& R/ X' T0 |3 Cstatic void McASPI2SConfigure(void)& S, m, J9 F* ^' _' V- Q0 F
{2 b( R/ h, ]# d: o5 w! d6 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 H5 E3 G8 K0 E6 b/ S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* ?- @$ W# T' n$ A$ D/ kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; G5 l0 n: K9 k) M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 q' \" ^0 s( k- E/ Y8 G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ y/ r- J2 Q! u+ @$ L" P9 p" S
MCASP_RX_MODE_DMA);
) o- _+ k1 \. _- F6 b9 ^ o1 KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 w5 i3 _+ g4 i. |& bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 y9 D9 B `* p8 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # d2 l) X U0 B( C7 Q9 p4 b# h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 `* l. c5 \+ d0 o1 c6 P& O! s! E+ {8 k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% H/ _8 b, e. ^& O. D1 aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 V! B. { ^+ w) P4 e/ j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ a' G- p* @2 T+ p/ @! i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 j7 }) p1 c B" q' O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& J" E2 a4 M$ n4 A+ a
0x00, 0xFF); /* configure the clock for transmitter */! V+ r$ X3 m w) q& T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
^0 o3 e5 o( k# y3 U& HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& ~! M4 T' E5 z, w7 |6 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 F% H# e4 a( q" P7 b) A
0x00, 0xFF);8 Y. V6 _ z. S# {) D( l
2 o3 ~5 A6 B% x# m- j6 R9 v' _+ S; A/* Enable synchronization of RX and TX sections */
) i( n% P1 X& J4 VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. c" d' C' @/ p3 hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; h& {3 F% } c! U6 H5 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- ]3 O, ]! M) l+ W% v- P, \** Set the serializers, Currently only one serializer is set as
" m' O! A5 L7 O7 [* C7 ^& N, g7 B** transmitter and one serializer as receiver.
" E% `5 q, V$ ]: r+ d: n*/
6 K Z# C7 G6 i `6 ^# X$ N) ?$ XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ a: R7 m, B2 q% @) N1 ~% a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( ?( Z2 A% N6 [ Z" l0 \** Configure the McASP pins 0 x& `6 Q, L t3 P
** Input - Frame Sync, Clock and Serializer Rx/ ^1 _( X) w/ i/ I! t, c
** Output - Serializer Tx is connected to the input of the codec
) p& Q" Y, T9 d2 ~6 R1 _*/9 ~, L8 B c u5 n* y+ R6 S& ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 L2 j* B3 {4 s' C/ X; QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* S3 a) d! X( S: x+ [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* B; U) G4 X9 S* ~8 |- F| MCASP_PIN_ACLKX
) w5 f" j+ c6 i( G1 C5 x/ w| MCASP_PIN_AHCLKX4 _- \- z( D# l2 Q8 b' G; Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" x/ J' x# Z8 q$ k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - N# k4 O8 p5 }( U6 M
| MCASP_TX_CLKFAIL 2 p1 n$ r Q. G7 S
| MCASP_TX_SYNCERROR
, k) N/ S8 G* ?$ Y9 I; j) I$ C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ z1 J/ v+ V. e1 C| MCASP_RX_CLKFAIL
8 b4 B" y4 @* t. r/ y. ]| MCASP_RX_SYNCERROR
' }5 o7 M9 X5 t1 g4 R9 G| MCASP_RX_OVERRUN);
4 y4 |8 D: M" p* L8 e8 l- A} static void I2SDataTxRxActivate(void): ]; C3 \1 R1 q6 X$ g( D8 P
{
2 E8 o. S; K# D/* Start the clocks */' C+ F3 Q \3 j' y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' b' x( z0 E+ F v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 ]. E, X3 l# X$ Z+ o7 i- f% s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 h0 \1 O( u' R9 i" }: bEDMA3_TRIG_MODE_EVENT);
* G s4 ^9 {1 x+ L% XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# Q$ {% d7 O, a4 E" ?9 [: ~- rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' T! Y/ p) s( ~0 I* ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 T, j3 i/ s0 v3 I8 f ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// Y" z d6 ~8 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. k; w$ g: N( N$ C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 N4 Y! J2 \9 X+ i O* \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 W! G- \0 |3 U& b" ]4 f. b \
}
' F+ c# {0 ]( L/ G. z' N' e1 ?+ w9 w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " X/ h* }& `' V4 T/ `9 r" z( K
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