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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 @7 U) }4 V) V6 K' j1 C, ?
input mcasp_ahclkx,; ], B8 X2 G& T C4 ]- W$ m& s
input mcasp_aclkx,) d B$ I) V h# H: G
input axr0,
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output mcasp_afsr,$ `: j, `4 z9 [1 C# q
output mcasp_ahclkr,: ^ f% r/ c ^# w; T9 P
output mcasp_aclkr,
1 n# p7 Q8 i) b+ \: |/ Loutput axr1,5 b4 a: q2 O0 R/ y7 J0 X! Z v
assign mcasp_afsr = mcasp_afsx;" [- Z2 | S5 K3 J5 |8 b8 B4 t7 R
assign mcasp_aclkr = mcasp_aclkx;
+ o1 x4 u& c9 Tassign mcasp_ahclkr = mcasp_ahclkx;, E0 b8 ^7 H; |
assign axr1 = axr0; + F4 h% j. Y; \8 O; A
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . T; n( V: B6 o$ ^6 |: {: Z7 ]( c* `+ e9 K
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);" g9 j& a, { f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) d' B5 b" U; kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: ~; }6 R& l2 a2 \# P, |8 xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, Z+ O7 I0 \$ K6 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' d) r m) q0 m" c! GMCASP_RX_MODE_DMA);+ S0 s* j% r* k; M& N7 }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 r! S3 R4 y1 J7 E+ |9 Q: wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& Y7 j* W1 z- U9 ^3 K! N7 DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. j/ E" J1 Q1 K U7 W2 O& P3 T7 }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 K! T$ s/ }3 B+ ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! x" P9 O" c8 O% G- D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; p: [! a6 Y6 Y8 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
i. V/ \7 `! {1 R# wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - J, @" V7 ?! B7 S* E; J! V6 _$ f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 f3 q1 m, o; ?9 F6 |0x00, 0xFF); /* configure the clock for transmitter */% M6 L) k) D* a& x2 ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 A; Y& s: _$ q7 c! `% j9 U" CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % [ Z! D6 M1 c; H0 g" u$ V: N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: E- ^0 Y/ H$ Q" B1 Q1 e0x00, 0xFF);
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r+ [& c; N" A. U/* Enable synchronization of RX and TX sections */
7 H: a$ ]4 ~ [! S% RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 z- G9 k" \% Q$ o3 M/ zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ O' N+ K$ J* d3 a, H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( f3 f% m) U+ @# c8 l6 c! a% ~. y
** Set the serializers, Currently only one serializer is set as
& ?: X2 @: S; j& P# U, O" d** transmitter and one serializer as receiver.( a: A4 R* j) M* E* g% U; v. m
*/
$ B' b3 A& f- R2 Z% \; ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. O+ v {% Q4 V0 G, [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ z. H; G: q* {8 j% m
** Configure the McASP pins / e& _7 y( }) e/ P, T# X, M
** Input - Frame Sync, Clock and Serializer Rx% r6 ` d- q, M4 @$ f+ }
** Output - Serializer Tx is connected to the input of the codec - ~! S: x1 d% Z. {( b o
*/$ f& J1 p, n. ~7 a4 ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* I2 {2 x: }6 QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 s$ S0 Z" R3 B; _- OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 b8 A6 q) ?4 Y3 ] B4 ^
| MCASP_PIN_ACLKX
4 Z* @& m1 ~- y/ {| MCASP_PIN_AHCLKX
3 J0 ?, `+ ?9 X/ ], X {: B) s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 v- I/ [7 s2 H+ n, G" e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - h. L9 W! Q/ z, J2 W- z+ Z3 d. v7 J
| MCASP_TX_CLKFAIL * e$ U' C; {/ h9 \9 O; \
| MCASP_TX_SYNCERROR
. ^5 w/ P3 C3 E5 Z8 F2 a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& i% y! o+ b* m- o0 K( ?0 A| MCASP_RX_CLKFAIL
. b: w, n7 Y* V9 W# }; Z* x| MCASP_RX_SYNCERROR
" `2 p+ U' I& p6 D| MCASP_RX_OVERRUN);
. @4 X' A7 f5 v2 T* s7 n' R} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
: t! x* k: ^4 s, yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! A2 Q" j' c9 i' {+ Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( p4 [5 N: j' q1 W ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 O5 P3 V1 r' Q$ ~+ |7 mEDMA3_TRIG_MODE_EVENT);: i9 N8 U9 V1 V3 X: `' S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& H, @, q5 T! P O, DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ M; Q) N* o* nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 L( b( H' u! g3 M% v6 |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& H; E+ N; N+ O' ?" j. I, B& Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 v3 k" o- f p3 R8 k5 K1 E) GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ X9 w3 V0 f; v2 i! C+ \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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! |7 [; J: P1 J- k' V/ a3 s( R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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