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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* f* p- y( `9 \+ j- Ginput mcasp_ahclkx,. W+ i0 k0 K2 }# w1 u" Q6 _( t0 p
input mcasp_aclkx,
5 P; S" n3 v' T! @1 y' t& v" C. winput axr0,
# C: V$ o9 R! Q$ R$ v# U$ z+ L; q
* E. Z2 t* A r. [6 {+ n9 Qoutput mcasp_afsr,
# E5 Y. B; d! R8 R ioutput mcasp_ahclkr,( H0 [0 ^& d8 s: G3 Q! J
output mcasp_aclkr,: x4 a; m1 N* i1 u4 @
output axr1,
7 \$ E/ ]- L: \' k3 p; X( P assign mcasp_afsr = mcasp_afsx;
$ E) `+ J4 [. H, k. E; Passign mcasp_aclkr = mcasp_aclkx;
# W7 \! L( D3 P; sassign mcasp_ahclkr = mcasp_ahclkx;
( o W! r$ z( V! zassign axr1 = axr0;
3 P5 T3 ^. n) q7 O) V' t" v9 _. a. v. H8 T" `/ B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : W1 _) H5 }% }+ F
static void McASPI2SConfigure(void)+ O0 G- K, f( c5 f
{% k/ {4 ~5 v/ R7 C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 Y; G! Z8 Z5 v& B; ]4 U6 M2 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 {, q: ]- K3 y3 v: [7 f% x. x cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' x# y- G3 a/ A) K; o+ N( }, b5 ]7 i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ U! |5 ^1 m A: c MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ N* @! H' [0 `MCASP_RX_MODE_DMA);' g0 r- r1 U+ Q. J0 P4 y, E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. p9 G" l; E) Y/ ?8 E" `: _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, o* h' |9 B2 P1 z) C G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! {' T. |, c3 j" |- W( H2 z: P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" f# q# g+ S- Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- C1 U2 I. \5 g' ~. k2 \6 RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 T( j0 C' C' u( E" f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% G6 n7 S$ E. D# S( LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * Q l+ n' [2 P: x% S; J; t* U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( J% ]3 r0 v$ {4 U% k6 `: E2 P0x00, 0xFF); /* configure the clock for transmitter */
0 U6 E! p4 p0 `; B1 r) f. @$ l0 ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 m% {& |# v4 l& f! @3 Q% N f& MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ N9 w7 A E( M8 D6 G; S6 x% |. n; W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; c- c) V8 }8 Y! ^9 E7 j1 [0x00, 0xFF);6 t! g+ |+ P+ M% J$ H
5 c j& b6 P- m9 f0 q
/* Enable synchronization of RX and TX sections */ ' k2 U7 x. c8 @* D: K& M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" o9 V% C- a( z5 d8 }5 XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! a/ A: Z0 v6 P3 l0 c3 m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 ]- y7 w: R5 f+ u( Y' Y** Set the serializers, Currently only one serializer is set as
# |7 q( J6 B0 c* {7 i$ d** transmitter and one serializer as receiver.% G( a i9 I2 q7 j) q
*/* F4 T( C- m5 x9 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" ]4 G2 f- N# Y, J5 F, I. ?/ ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- P$ {" K( _9 G4 Y1 q' Z# x9 P8 Y: ]** Configure the McASP pins 2 ?! \* g1 U) Y2 Q
** Input - Frame Sync, Clock and Serializer Rx$ b# a) i2 G3 |- s2 x @8 i9 i
** Output - Serializer Tx is connected to the input of the codec
7 K% m7 J# L0 J- H/ {1 v/ u I*/) n& _" J V% g; I" P+ g3 e% o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); G0 x" t/ p0 _; K( W/ h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ K: D! m0 n+ I' d: I- u. A1 cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& p2 b) r" B( T6 S| MCASP_PIN_ACLKX# V0 S# ~4 m9 k1 J0 W& a G5 _
| MCASP_PIN_AHCLKX& w2 d+ Z) y* N) ^& q& A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 {. b, g! W! w4 ~- h( Z' k; K, NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' A. p0 k0 Y" T4 t4 B9 e# K& V x w
| MCASP_TX_CLKFAIL
. b5 Q h+ ?- K z0 L| MCASP_TX_SYNCERROR
! c! |/ F7 f, s6 l, y2 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , z! T2 L2 @6 ?; F5 f: z+ g3 E8 h
| MCASP_RX_CLKFAIL9 X0 ^" }( `( e& [7 P
| MCASP_RX_SYNCERROR
' p# f* c1 U; V+ I% || MCASP_RX_OVERRUN);, r& t7 ?; b1 \# K# p
} static void I2SDataTxRxActivate(void)
# @. J: Y& K$ @+ W1 g- m" r9 ?5 ^{
7 J5 l6 r; a) j, L1 P9 {# c$ k/* Start the clocks */* J! Q K$ j ?" P3 ]! R* r! U( Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* d' `- Z6 M; y% y: j; qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ _. o. p7 Y2 ]; ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- I& F" u7 x3 ~$ j( IEDMA3_TRIG_MODE_EVENT);
% M7 ?; N3 R/ I Y1 Z/ B; @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 Q, a$ N) x' @' Z7 C! G$ v }6 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ I* s& F5 I- Y. e4 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* u5 q4 Y# }& p9 Q9 @$ J' J* j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" `8 d' i/ g! z3 e/ J; R5 Q# c/ Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. b7 S: l6 G: o! C# ?8 M" HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- U9 b& _- Y" _( ?& f& y# y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; P ~' \" r% ~; k) w) j: C
} & I9 {6 H0 v: w/ J# S# e" J7 y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 u$ e; j7 W. v
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