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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' X% S* Y" g+ L5 winput mcasp_ahclkx, k6 s5 C) k+ o9 F' R+ g
input mcasp_aclkx,* J0 H1 u8 T9 ?- [4 W: p
input axr0,
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4 W6 f$ Q6 Y# V* L' D: p; Joutput mcasp_afsr,
! {& f6 `7 _8 T- `output mcasp_ahclkr,
9 a( d9 W9 ^' Y" a( C; ]& koutput mcasp_aclkr,5 ]4 t4 b- I' k7 w: @
output axr1,$ @0 m9 M) U# t; |4 a, ]
assign mcasp_afsr = mcasp_afsx;7 m7 D* l l1 q$ T- G( ~
assign mcasp_aclkr = mcasp_aclkx;% M: d/ J! n" y5 A
assign mcasp_ahclkr = mcasp_ahclkx;4 X8 Q6 n1 K: p8 H
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / ]) R4 ~9 N' n6 u
static void McASPI2SConfigure(void)5 t( i% }% n- H# G9 {
{( B" i. W! B$ m/ M( l) Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ N2 o. a `0 J% \& MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" I5 ^% m' m: A+ LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: {: u( u$ x4 i" {' P1 G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 D9 Y: m* ]0 g! O6 h( D0 i; N1 a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) p. X D0 g ?6 |+ ?+ h" SMCASP_RX_MODE_DMA);
& {" l$ e3 M0 T1 E4 SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 H# f" N' b8 [! d2 \; C) ] ^8 M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 e. S3 K% c9 ^/ s6 f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ o: L" ~% ~8 N) m3 W5 dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ i3 E: T1 V$ r% s0 k8 k9 b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 M) b2 U5 k6 b- xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ t {4 w; t6 Y; ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: P8 o& M$ [2 K" L4 \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 r3 Q# }, C, t. f/ F! KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( m5 O3 g$ J" n4 j' x0x00, 0xFF); /* configure the clock for transmitter */) }5 \+ [+ v6 x% H3 G- Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& `! B1 i$ i, n- s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 Y. n4 F$ j& k* E9 o2 D4 j. M- [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# A! |% _1 f0 H* P4 i! F0x00, 0xFF);8 t( l2 j+ U+ F6 q* I
4 k! x% h8 t& }5 e3 A/ M; U$ [/* Enable synchronization of RX and TX sections */ 4 Z' ~" _, @, D. D1 O9 k8 i+ ]4 D; J0 Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 J$ C$ _7 M4 K$ NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 V& L" c& n7 K. U, @+ b, D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- O2 A. F; w' i( d* o** Set the serializers, Currently only one serializer is set as3 k2 O# }1 M( y2 O
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); u4 `3 \% e' U/ h6 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 }/ D! H1 J' l# z! N
** Configure the McASP pins : E4 u g7 z _
** Input - Frame Sync, Clock and Serializer Rx" u0 S) t- t/ q/ t
** Output - Serializer Tx is connected to the input of the codec
! e0 u: H8 i9 E; e, O*/
W: \% {2 I/ @3 `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 Z* ^; H0 \4 {' X5 hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 E7 H1 H: }( P6 R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 O4 k5 ~& [3 s# F* T x# j( s
| MCASP_PIN_ACLKX P2 Z, D: _+ ~* k4 c
| MCASP_PIN_AHCLKX Y b$ o/ k$ }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* K& I! ~) G( R+ c* rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 O& G M' i) G9 ^3 C: ]! R- z| MCASP_TX_CLKFAIL ! i8 S, R0 x! v) c0 W7 ]0 M
| MCASP_TX_SYNCERROR0 ~) c! q4 W+ I: p. _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- y% t+ d8 h+ o| MCASP_RX_CLKFAIL
" S/ ^. Q# u* Q3 s+ H3 V+ ^1 `| MCASP_RX_SYNCERROR , ~9 F0 B# ^; l V9 d
| MCASP_RX_OVERRUN);
# }9 K( X6 O# `: a! K: w7 C} static void I2SDataTxRxActivate(void): c4 m- O3 k, a( l# w6 ^2 ~" e
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/* Start the clocks */$ ?; P7 c* v# a8 C( z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ {" _5 Z( b9 _, gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- C! t* I( b8 B8 ?. O& s+ J. VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 a4 c: g+ q+ }/ J, aEDMA3_TRIG_MODE_EVENT);
# w& s- A9 n6 w: X; oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 Q3 B" e( Q$ Y1 z+ wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
_% ^% v3 H* ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" x1 B/ k, _: R, g ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 h+ ]3 J9 K2 D3 ?: \2 bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 \+ P2 \4 `5 J; hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 j3 [$ U s7 iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 d& w. T1 {/ q}
( W$ q: W6 S) H( ^; d0 c$ o% M& _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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