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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( `0 F9 l3 @+ Q. J) n# j1 f. Iinput mcasp_ahclkx,
; W6 e) S* g0 U* E6 x% R6 F+ N- \input mcasp_aclkx,
* s, D& y, ?, X( E& z4 pinput axr0,- `/ V! X: f; W) I
5 z b/ N* I6 }2 zoutput mcasp_afsr,
) @, g( @0 @2 I9 j$ ]) voutput mcasp_ahclkr,
2 O# P; z* ~9 N8 ?% J' R/ Koutput mcasp_aclkr,2 Y: G, n3 u8 h$ s3 U1 t+ ~& C8 [5 c
output axr1,! c; O9 x6 r2 \" Q
assign mcasp_afsr = mcasp_afsx;' N; d: u- y: l7 z$ W$ ^& l
assign mcasp_aclkr = mcasp_aclkx;
- m9 q: \4 Y1 O; G0 o, b0 M5 m& massign mcasp_ahclkr = mcasp_ahclkx;
% c1 O8 z3 u$ p' E- z! |; Vassign axr1 = axr0;
+ {: x! s, l( D
" T; b' y$ J/ h0 M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) p0 d& a5 a; I6 m9 m3 u. Istatic void McASPI2SConfigure(void)
/ v8 s: n5 u0 n! @{9 I9 k! ?5 z8 o4 {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 d+ b, \3 V( Z9 s tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 T& r# z- h( v" ]% NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 s- o6 f' n. I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 V9 p9 Y7 w: G. a0 R3 K0 l) ?1 q; uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 m l7 A+ {6 Z6 t2 H0 ?, LMCASP_RX_MODE_DMA);
) s# @1 X& Z+ U1 CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ w8 Z2 k& F) u( GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 W4 l& l- Y7 F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' h. t5 g/ q* L5 \. K* e/ T0 h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 c3 B4 ? d, F4 i: T0 E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + T% J! _1 @: d, K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! b' W7 l. w& x0 g* w+ h: s; @/ C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 l6 w0 E5 o; ~) b8 e( iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ G* g- `7 {* C- ^: u* {. pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 i) u& A4 X! ^6 m' `
0x00, 0xFF); /* configure the clock for transmitter */
3 L" |5 |7 b/ YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) a/ t- f2 Z y2 B8 m& Z5 j6 iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; R' V1 i: Q2 O9 B0 P4 iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 K/ Q$ m7 ^7 p1 i1 [. l" y$ i) ^0x00, 0xFF);
7 e* T7 B8 z4 Z# A% P8 J( X6 n) G* G7 P! N7 b9 f# X7 I4 g. I$ B
/* Enable synchronization of RX and TX sections */ 6 F0 z a4 ]: y& J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) u9 ]7 e8 d$ EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
d7 b* ~( i; l, B# l: MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 g( p7 Y* ~1 {: `
** Set the serializers, Currently only one serializer is set as) G p, ~9 H- C4 D/ O. R2 Q. G8 Q2 _6 h
** transmitter and one serializer as receiver.2 S! t9 p! H+ l* j+ C( ^, k
*/
3 D% C/ T: }2 [2 Z# z' nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" U. j: H3 U: b! p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. F. U$ | F2 U5 O
** Configure the McASP pins ) p, R9 F% E- S' z
** Input - Frame Sync, Clock and Serializer Rx
+ x/ j4 ^3 d. h1 W( y# Q** Output - Serializer Tx is connected to the input of the codec
2 U9 T" Q3 w) N*/
3 b& U [1 i+ e6 R5 |8 z' BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. W8 \: j- G+ C; mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 }6 K$ E) E6 P# F( ~3 o2 SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' A+ S( C: A. | v e| MCASP_PIN_ACLKX
7 o5 p# ]3 u% O% w% l7 a, R| MCASP_PIN_AHCLKX
( T/ R5 a8 P! ]2 a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& v- \* {- ~- X8 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 P' {% b5 Y* N# R| MCASP_TX_CLKFAIL
0 l+ H! J8 W3 h3 {3 \8 y| MCASP_TX_SYNCERROR* a a. X% b4 y, \5 Z8 K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 g" c7 E( v1 V! f| MCASP_RX_CLKFAIL8 ]3 V d# h! E4 k# N2 a5 A
| MCASP_RX_SYNCERROR : ?% ?' j6 ?4 X1 ~ Y
| MCASP_RX_OVERRUN);1 q6 A/ u# ?: E# g" T I
} static void I2SDataTxRxActivate(void). P4 @ S9 `0 g" Z. R, ~% l$ e
{
6 t. ~; K# @9 U( G6 M- ~/* Start the clocks */. U/ `4 a8 q- z5 q$ k+ d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, s! m! `9 D' i, d. ~- n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 C# v9 P9 d# E! ?2 v6 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 b" g. U; ^8 Z! D& u7 G, }
EDMA3_TRIG_MODE_EVENT);
- [ M8 u' Y& m/ p0 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* [* R+ _/ E$ X9 @! NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' O. G6 i b9 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 i! y# E4 B; c+ @8 W' m% o9 w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 c. r" S; O* z8 j- hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) v+ j' \8 ?. CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! v$ z: S. ]4 U' |2 v# M1 e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& d* g- r, k/ F" b
} 0 J% G7 X0 d6 a {: X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; U' Q( ^. V) u8 R* M: l. e6 E
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