|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ F* a+ }8 X) Y4 E) _. K, q& sinput mcasp_ahclkx," s0 f/ A3 `# y" R j
input mcasp_aclkx,9 O: s2 s+ t4 }1 ?5 [7 a0 T5 l
input axr0,9 W' e M2 J) \* d
+ C" D0 x {& z m9 e: c8 _: X# aoutput mcasp_afsr,9 F; T6 Q4 o- }
output mcasp_ahclkr,
7 P% r: E) p( \- G5 o8 ioutput mcasp_aclkr,+ l! V `- @9 \) D' q" Q3 P
output axr1,
$ o) d: c8 P; i. W: j3 B assign mcasp_afsr = mcasp_afsx;
- P3 K, ~1 S3 d( J& j, J! Zassign mcasp_aclkr = mcasp_aclkx;" Q: f: @6 [8 L1 f) P$ L
assign mcasp_ahclkr = mcasp_ahclkx;' i$ ]: x. w# z* G
assign axr1 = axr0;
[9 w* @% }! b8 c
$ C F8 m7 m" _& K/ a4 G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" S: p0 m! {% x' Hstatic void McASPI2SConfigure(void)
4 n: a5 }" H8 g, L& b, P{. Y) U8 q8 o$ y* A+ l- Z# P# P/ K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- x+ x+ b+ I& ]3 X8 x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) N) L! q' n2 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 u8 i. n# Z3 ?9 m: k" w/ X( [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 K8 v j X% @2 s; |! M3 N% ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 D* D' w% q4 p, Z( w7 t
MCASP_RX_MODE_DMA);
2 |: J: v4 \4 i1 h# L! T5 o+ R8 E( W& [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- a2 Y/ u x3 Q6 p$ ?; v. s4 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ K6 P" U" P9 |3 Z% ^7 s. @7 oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 _( A" ^# A4 S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& O7 v1 s7 P- ]( K7 W& j4 {* wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 X, F8 z. u8 G* e+ |% w% Z& G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ Z' T/ y/ a5 Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 ^# _6 s8 i1 f) K) k! lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 D$ Y( I% Q5 M) d; fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 @" R+ I8 }0 q0x00, 0xFF); /* configure the clock for transmitter */
* a+ o/ V# m1 Y- ]2 V0 R4 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& k ^ P* w% O$ zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % y5 n: {# x: M. o3 j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& H, j/ C, l! J8 C3 W+ i0x00, 0xFF);
" ` G0 D D ^* q6 p6 F
+ Q& t: h9 y/ y( ?/* Enable synchronization of RX and TX sections */ ! h2 M7 P: ^4 E; ^2 s+ H. m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// g+ L+ u( T2 n0 v- U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 i- v2 w( C, x# x KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% s$ w' }! w* ~3 G% F# P G
** Set the serializers, Currently only one serializer is set as
: i' ~& ^* X0 a0 ]8 X** transmitter and one serializer as receiver.
% R3 S+ \ Y5 m# O9 p% p3 s*/8 p2 {* `1 W+ _* d$ @* P% J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 j6 l y2 g% {- d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( [! W0 D* C8 e. b- R4 D& O, a** Configure the McASP pins
u" ?0 N7 {% U B" y+ Q** Input - Frame Sync, Clock and Serializer Rx
/ L6 Q- j" Z1 r, r2 B** Output - Serializer Tx is connected to the input of the codec ! O0 B S- H8 O3 T/ E. S" N7 S. C
*/ i8 P1 A# |, D, x- y$ B& J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 N. X* b2 N- e4 V! j8 R: [9 w. c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. O% a4 \; k( s/ L& M) O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. K3 U6 M( K2 a; F& {. L6 }
| MCASP_PIN_ACLKX
8 Q' w. X8 R b' S, N w% ?1 [| MCASP_PIN_AHCLKX, J" [8 _( T# a7 |/ \2 F8 z6 t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# a& ^9 ^% v, k- [% B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' X \9 p3 [/ s. o| MCASP_TX_CLKFAIL
7 J; a$ h; |! a6 [5 j; `! t. L% J| MCASP_TX_SYNCERROR7 b* n( m' B% ^" W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 u; e. c' o9 b, s6 [' D0 x3 o| MCASP_RX_CLKFAIL
, E2 @5 K7 \$ r5 q| MCASP_RX_SYNCERROR
1 a' z7 S% n! q4 [| MCASP_RX_OVERRUN);
4 @7 ^" ?+ a" I8 b} static void I2SDataTxRxActivate(void)
0 i W% A/ s7 h! _0 X r{
0 V8 d V% @& j) P+ w, J/* Start the clocks */
/ V/ X/ e- E5 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, u) y0 B. R8 r& a% g0 [, o) \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 @* A' H$ ^ Z! S( A' n7 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 N# z# k7 m, O- wEDMA3_TRIG_MODE_EVENT);
1 s2 ^& Z) O ^% ?7 Q, _; e+ HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 Y5 U6 k/ w J- ]- S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 p* g& y$ L' a1 O0 P$ x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 w2 z8 M6 s5 |+ S" e) q" ~3 IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) p2 e# j. l4 Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" {( n# ~1 I! M- V7 q& f; ?! uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 C7 c6 }4 W+ e, S& [2 o0 B$ Q3 }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: b. R5 D9 Q3 ]/ W/ \0 b2 F8 `}
" b$ T# K/ u+ W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
T5 W2 x# M K; F: n \ |