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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 \& G) ?9 K( j2 T- `2 z a6 j
input mcasp_ahclkx,! I% {9 @; o9 M/ A" N
input mcasp_aclkx,
; H" Z+ T, R( f$ W& Binput axr0,
1 r/ H( M5 [6 I
5 Y) S0 a8 i) T" z; y4 _$ doutput mcasp_afsr,
1 Z' s2 b) i# ]3 n. l) ?. B* Doutput mcasp_ahclkr,
/ P! k' {% C6 N: q3 {! youtput mcasp_aclkr,' H1 n4 |7 ?- K; X: |+ w
output axr1,0 Q, j5 X8 ^- y7 F
assign mcasp_afsr = mcasp_afsx;3 z# y7 K6 k+ h3 J$ R& y
assign mcasp_aclkr = mcasp_aclkx;
' f9 \1 A0 T# A" T r$ H, ?assign mcasp_ahclkr = mcasp_ahclkx;
& b9 ^3 |8 F! M* j, H6 U R4 z @assign axr1 = axr0;
: [" T9 f; M! v3 ?2 a6 J' [3 b% z8 g1 x3 U; ~ ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 j1 }- o( D4 }$ J+ U: Cstatic void McASPI2SConfigure(void)% @- c# j3 T: @" o
{
3 ]* U8 ^! p- n! r- wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 `& f: P* X' B4 R0 e5 o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" C- N* f5 Z% q7 t) v. U" S" YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 H* @6 d) S9 ^+ K! z9 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# Y, F* S5 Q5 J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 P/ c: A! m+ i+ x6 L8 w1 ]
MCASP_RX_MODE_DMA); _6 P. }% F' y5 R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- m: X$ o( g; A# K6 z4 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& h" ]9 F m0 ^) C) u. r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 D" ?& f0 Z8 P& d8 \8 c$ i+ xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 h# |' l6 H8 D& i0 YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : Z, g' L- f2 ?. o+ v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 \1 I |4 k9 \- T! ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 B0 ]% ?9 S6 I" A% H2 SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- g+ U" b, _& h MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ P5 X" `" g. @& X: A7 H& Y" [
0x00, 0xFF); /* configure the clock for transmitter */1 ]1 Z, ]7 z' M# L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 D8 p- o4 o0 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . S) R2 i8 k& _; B: O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 |/ E, m: S. C0x00, 0xFF);
8 X: Z, [3 {$ q7 f H4 K
( h: {4 Z* G" s$ x8 W/ Q( n/* Enable synchronization of RX and TX sections */
$ N* _: |# H, W( @4 R4 O: yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// b, Q0 c2 q( [" K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 D2 I/ y3 s2 O' f1 G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# H; W) A2 v4 [2 k" |** Set the serializers, Currently only one serializer is set as$ `8 t) N: S; t9 d( S; _( z- g) v
** transmitter and one serializer as receiver.
* U2 ~9 a% [3 w: C" e. P*/. n5 D0 X: b6 ]. u7 m# y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. S) g. k* ?* K2 R& V1 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ Z9 A$ L5 S% a* i** Configure the McASP pins
3 j5 ?3 w3 k5 _** Input - Frame Sync, Clock and Serializer Rx s: q2 J" I6 A+ c l
** Output - Serializer Tx is connected to the input of the codec
; z6 c6 b7 k4 v0 t*/6 l3 Y& t8 P$ `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 x3 k+ A' Q x3 ^& g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( t1 q. V* Y9 S3 o+ g1 p( Z! f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- n1 [! n5 Q+ E. p| MCASP_PIN_ACLKX. d+ F( i" A2 e8 { O4 n$ L
| MCASP_PIN_AHCLKX! D3 l, K, ], T/ s: L$ \$ }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: P9 o8 i7 w2 O LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 R7 M, c- \* z# n: H/ `) n| MCASP_TX_CLKFAIL % h4 I! ]' J9 r3 U
| MCASP_TX_SYNCERROR2 Z6 K. E- m m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 c) [- o- ^- G7 G# E$ W| MCASP_RX_CLKFAIL
& m, A' Q- ~; R" y) d| MCASP_RX_SYNCERROR . R) J- \( Y0 ~3 `. c4 f
| MCASP_RX_OVERRUN);
# f- q8 z0 C/ U Y' c. P} static void I2SDataTxRxActivate(void)
+ T- h/ B- |7 e& q2 \( L' e{) ^" M; m9 D, E. w8 o8 h8 f: ^
/* Start the clocks */2 P2 H' u4 ?4 M) x% q# C4 Y+ W8 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ t6 U9 N( Z$ `- i* i* ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% \% T2 ?* l' B" E7 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ a& c g+ Y+ {8 l3 }7 }; |! v2 X
EDMA3_TRIG_MODE_EVENT);
% K0 O* _% Q1 ?) I/ ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & _) F- i& q- ~2 Z5 _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% u# c/ |5 n1 g( a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. Z& D# j3 z6 a4 T/ L/ B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) ^' D) S/ u7 wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. O- e( ^( T9 j- D3 L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 o; O* X2 `& g1 A, p' xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. _/ \2 V* L7 J7 Q) H- n# C @
}
; v1 P5 B) w5 e! R/ H/ [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 @5 `2 Y* r& a' {; G( ~ |