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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 e2 {/ w8 I1 i/ S/ M3 Sinput mcasp_ahclkx,
4 t% K4 Q* q' Linput mcasp_aclkx,
4 L$ f+ b: l0 ]( p# {input axr0,' Q5 M' o& ?! c) O) i7 a
F$ |8 M4 ~0 ^9 n6 Woutput mcasp_afsr,
6 y6 r; O) h+ z" W& coutput mcasp_ahclkr,
( _( v7 m- o& Soutput mcasp_aclkr,
; B6 a* V. A6 u+ Ooutput axr1,7 z' e" u: _ a# | g* Q5 Z
assign mcasp_afsr = mcasp_afsx;+ V4 f. h, G4 l8 i- {: r9 f
assign mcasp_aclkr = mcasp_aclkx;" x. \/ C6 G* U; ?
assign mcasp_ahclkr = mcasp_ahclkx;& d7 J* s! y7 s( t% q" w+ M
assign axr1 = axr0;
3 R1 V; T' Y) W9 {3 Z+ k8 \% G& Q% q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 d1 B. G4 C' w, H9 M0 E6 W, u
static void McASPI2SConfigure(void)
0 P/ L+ v p) }{
$ d- o4 v7 H% o; a1 OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 c. I0 S" I7 J$ h/ R; {0 X5 F7 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 u9 b5 z1 b& i8 u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 Q3 {; i% T$ j. ^2 {, B. c' b$ mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% K) Y8 ~. D" L0 ], ]( {5 ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# ?1 P; ]4 }2 H( D2 WMCASP_RX_MODE_DMA);
; S [5 e3 `9 MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ o3 T2 X% z6 xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' \' \; s9 M0 \! r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( @' g! R. f8 Y4 y3 ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: y1 J. I {1 @' k% ^" ~2 j. v( VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 s( f8 a" j% P( p- \0 O- u, x% \' a; a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% u& q- K u9 E% W! Q5 ?& WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 }5 y1 t* n, D) ^3 l/ M$ D7 p& m4 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) m# r4 F% K2 g2 L/ HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ B3 S$ ^. p9 S: i
0x00, 0xFF); /* configure the clock for transmitter */: ]9 Q6 ^; p9 ~, j( Y7 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 f( ~* A: s/ y) lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + M9 p1 e+ w! f ^% U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& D0 b |' n! P
0x00, 0xFF);
' X9 b: X) D2 W/ F
' _3 d. v% ?3 w! i- Z/* Enable synchronization of RX and TX sections */
|, J: y) R- PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! P# k. E3 w7 s" Q! b" U. K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 t1 w8 ]5 j0 r# w6 z. e& l' D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: U: P* X X, z** Set the serializers, Currently only one serializer is set as; p, z! I1 D4 m) a
** transmitter and one serializer as receiver.* Q1 ~6 ~# ^# n* \1 D* Q4 c9 Y
*/3 @3 d2 M* b9 v1 l$ K: C* A; ~! r4 _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) R7 }& ~1 t5 R/ c# r& S1 `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: e( D$ h A/ s** Configure the McASP pins
7 M7 ]) @1 ]) Z+ E** Input - Frame Sync, Clock and Serializer Rx
% Z' B/ k8 f) [** Output - Serializer Tx is connected to the input of the codec
2 x1 ^* l6 j5 C2 h: l*/
9 r2 x5 M, t: _4 L( t# ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, @9 f5 a# x2 t* ^8 c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 c i! @2 k! o# Y, Z }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; q# k6 Z; |$ N4 A& E/ j) l
| MCASP_PIN_ACLKX% w9 G- ?9 E" S4 G
| MCASP_PIN_AHCLKX
X+ G/ D" M( |. d& `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! l9 y3 ^! P4 ] N4 ~% J" z7 @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* O; o6 H; F0 I1 h| MCASP_TX_CLKFAIL $ I; `1 ?- F Q- A7 f
| MCASP_TX_SYNCERROR
6 {6 P& K+ z# [8 k6 `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& j$ @$ p) Q: K3 [- g| MCASP_RX_CLKFAIL
0 C5 u( V4 F' r% Q| MCASP_RX_SYNCERROR * o( B s) C' t9 v
| MCASP_RX_OVERRUN);
$ A5 R% h" \' j# o6 c} static void I2SDataTxRxActivate(void)+ K9 e& l. C9 x Z& g
{
+ r8 W) v% F( ~( m/* Start the clocks */
) C+ f- R4 H8 O# C& QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% {& F) p" {1 L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: V) i; Z. U) h1 w2 I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! i6 g8 @7 Y( P
EDMA3_TRIG_MODE_EVENT);0 |7 n4 Y! l) ]( g' |5 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 \$ G! D8 s" a1 O: J0 v9 U; `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 C0 k4 [0 P4 l& X' k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' i8 I9 j" I. o6 C7 G3 u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* J, V" | Q3 R' h$ Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ `8 A9 I) y" _/ e6 k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: z4 [. K+ |8 F9 m9 d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, Y5 b6 ]' z. \6 n7 j. ?5 T: E8 ^
} , v2 |4 T2 l. M3 l V8 q/ w/ x1 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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