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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 U- n% f/ i9 E& N h$ W5 [
input mcasp_ahclkx,
+ ^+ Q2 }! y/ ninput mcasp_aclkx,4 m9 y4 b* W& F/ ]
input axr0,
, b, Y+ S3 \% I! P$ g2 U& Z7 J
; y6 T4 E* D9 j' U; `% J: h) Ooutput mcasp_afsr, G% E( ~' C7 K% x7 Y. \ k' U
output mcasp_ahclkr,6 g' @/ h$ [. |' z; a
output mcasp_aclkr,
7 w3 Y. \0 t8 B7 [! uoutput axr1,
" N) S. x& N( ~* v assign mcasp_afsr = mcasp_afsx;
; g( q- \' V9 O+ z7 j- bassign mcasp_aclkr = mcasp_aclkx;
; I e% X+ O# _* uassign mcasp_ahclkr = mcasp_ahclkx;
5 \% V3 r2 n! N: \* uassign axr1 = axr0; & E2 e- N7 U1 Q- K& W5 G+ X, r
9 d* o; l6 B$ T" _ D0 g3 O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 k8 x; f: A. U6 c
static void McASPI2SConfigure(void)- p% H# t% Z" M( k3 Q
{$ t+ _ U1 T: a1 n1 @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( s4 H$ @5 K% ?) J6 \4 i# H+ M" b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 {9 y( a/ x* i1 U( qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; _& ]4 r- k% [3 f8 o: R4 |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 ~ t! G" c! ?/ y+ ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 ]( G$ D5 X$ PMCASP_RX_MODE_DMA);! ?% V6 y6 u6 r5 _3 Y/ A9 N3 V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 ]$ v# x2 j7 ^- K# D6 d) L1 cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 r' `7 d' V8 W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" H" d- E* ]- y) O& [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 G r9 L2 `, P' S" L8 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ e4 P9 j- u$ ]2 |8 U" ]* FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 B/ B, `3 v9 i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 R( s7 N" K5 |, l9 e. U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! S' @/ e& E& C1 s% y+ N8 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. H5 M6 Q- O& t% L1 J
0x00, 0xFF); /* configure the clock for transmitter */# D3 \9 r; g- f" J; O1 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 `8 J1 ?, C1 V3 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 w( b: g+ a3 T5 M1 ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 Q9 k5 k2 Z- S, U6 [
0x00, 0xFF);0 R( n. ^- l6 c d$ n! C
d* }5 V3 H5 k: j" ?: w' c
/* Enable synchronization of RX and TX sections */ 4 q0 b5 J x6 ?6 z! @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' y+ W4 Y# {7 Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( J: E; u1 U% A( C) y- XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' j/ r9 c* u* d& O- B! _5 Y7 b
** Set the serializers, Currently only one serializer is set as
$ ^- I2 n0 R1 C* x6 c/ B/ U** transmitter and one serializer as receiver.
, n- R1 Z: }5 A! Z" I$ q0 G*/
( G9 b ^8 r0 j5 X# LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, |; Y% {% I# I: EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, D- C+ V( f K- y: j
** Configure the McASP pins . C& c4 R; N2 Z) o6 e6 y
** Input - Frame Sync, Clock and Serializer Rx1 h/ N/ y4 T* D& j
** Output - Serializer Tx is connected to the input of the codec 8 q- ?2 i( c. e! _! X6 q' d" J$ d
*/# z! _: K; j( s. p8 t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- O. z/ R1 P t; U* ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# }, _( {6 _$ l# G2 q* iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 D! N" Z; s; X8 y$ q. `, `
| MCASP_PIN_ACLKX
* |2 U j* C' a+ x- b$ R) ~& g8 q, Y+ l4 c6 K| MCASP_PIN_AHCLKX
2 ^( I% M+ L4 Q+ p. l4 H& z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 g, |1 l0 Z, P' sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 b! g- A" L s+ p+ |7 l| MCASP_TX_CLKFAIL ; P" D* B( `( ?& h( F" U k$ @* G
| MCASP_TX_SYNCERROR
' _+ { t# r, O. v1 V; z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " f6 U/ h C1 G s u
| MCASP_RX_CLKFAIL) t# \8 M) b2 M
| MCASP_RX_SYNCERROR
" a+ ?" z) c; ?| MCASP_RX_OVERRUN);. O7 S( p# U2 H2 ]4 }* A* J. u
} static void I2SDataTxRxActivate(void)
! F. A7 \$ { E{
0 q4 N/ @6 m0 K6 Q/* Start the clocks */& B9 O( T9 E t' [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ [5 P- Y. N. d9 u' ~" _1 k) C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ ?) B" }* V# j$ j( u8 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 d/ h; B6 N; m1 z8 o \0 v- lEDMA3_TRIG_MODE_EVENT);
4 N4 H* P* ?! @9 G- F+ G2 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 m7 [& z" Q9 k3 i3 z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# g" m; x6 L) ~5 f! Y2 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ F/ Q. _* _, K- U4 H7 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. J' d( d4 j# H& ^% h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 ^/ T* S# v" u5 l1 \% P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 b# M5 G$ z$ ~# S5 m: q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! R) L" E4 x- T+ n}
" Z% _; @1 c* P4 }$ W& D& `, k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 u& k7 z+ n# F7 w7 B% u8 D& B
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