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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( B6 J# `" M. q* C
input mcasp_ahclkx," o+ X0 C) {+ g3 R4 d8 ~5 v0 l
input mcasp_aclkx,
' d" ]/ z1 I# ^- Y! Xinput axr0,
& r/ {5 v' U+ }8 @4 L3 L% z4 J( ~2 _4 S5 V8 F
output mcasp_afsr,7 i* N3 N5 f" S5 i( d* f
output mcasp_ahclkr,! G9 P/ }+ @$ t% o" k5 X6 @
output mcasp_aclkr,
* n( B- D1 i% k; zoutput axr1,
4 {6 w+ A0 K$ ^% |! }$ L assign mcasp_afsr = mcasp_afsx;; Z! Z) \2 Z1 f. T2 c1 `( a9 a3 K* v
assign mcasp_aclkr = mcasp_aclkx;
- O4 u! M7 m3 y- ~, Lassign mcasp_ahclkr = mcasp_ahclkx;
, x' c0 t) _! i: d4 x: K3 ^, ~assign axr1 = axr0;
6 `7 q/ @# w! O+ a" a6 c* \% t/ v
2 H, B0 v& U/ g3 K3 X/ \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( B9 }4 _) S' u# p2 R
static void McASPI2SConfigure(void). W- O0 P7 Z6 D- { ]
{: b8 U+ \+ W- ~: n3 Z8 T! D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 d( Q( Y5 E! A( S% J3 [4 a/ s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. _$ w, F0 m# |- g" QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
P: N8 e' O5 Z9 UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 O% i3 t) ~7 u+ G( i: ^1 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 ^! T6 k/ e7 R1 ?- {& PMCASP_RX_MODE_DMA);
3 K7 G% z9 b ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 h C4 b! d; u/ jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! ~# Q T" a# z! _0 h+ L$ B! LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: M3 O" X% w: K5 A+ G1 d$ f) s* lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& u, c( f5 Z& Q: SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! V% n5 ~" f& l2 tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( D' a: g4 v7 z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* c0 d" {/ y4 f0 `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / I4 ~5 V: d N4 i7 ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 k: g0 t" R# F8 [$ d% |& W) x
0x00, 0xFF); /* configure the clock for transmitter */" a- n( |6 p' |4 x0 Y# ]. T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 |* R2 e( v' r9 P( AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # \/ a% T: v1 S$ _/ k" F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 U! q' s, t7 F' u, {; r0x00, 0xFF);$ }( o# f! o" t3 j1 v- j1 E1 U
$ n+ _# Y! g2 \% M4 v5 A/* Enable synchronization of RX and TX sections */
& }3 r( f' K$ Y L: g! A, QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& D4 @; K& w7 w! M9 M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& \9 s* ]! _7 n( Z/ E2 l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 g- u( d1 P% [8 y1 T7 V6 l
** Set the serializers, Currently only one serializer is set as
9 P* T3 V9 e. [) S$ J+ z** transmitter and one serializer as receiver.) s l2 V0 F. v9 [1 H" \! ^ V
*/# Z; \7 f& W& B9 X* X1 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 B7 Z! e R* O" ?$ g: F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- S/ [) X, E+ R \$ |( a( I: @0 v** Configure the McASP pins % T* f: ]. i- i' ?5 k6 ~$ M
** Input - Frame Sync, Clock and Serializer Rx( d( `0 N0 E% `% h
** Output - Serializer Tx is connected to the input of the codec
. A$ ^, j1 k; u*/
/ Y: }" S) P" @8 F+ \9 S' LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" w& D9 W% ^* @$ D2 @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ R: F( c% O2 Z8 G; z6 U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& [2 F$ q: q, g: c! w ^| MCASP_PIN_ACLKX
8 g2 r( @0 t* f/ {5 s! }$ O' W) X| MCASP_PIN_AHCLKX. B7 `1 U; b3 @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 x6 w" T+ S* m- Q' i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: \5 A1 J* I0 }: \( X; |4 A| MCASP_TX_CLKFAIL 3 w5 H' E+ y5 m4 \: H/ g$ t/ W
| MCASP_TX_SYNCERROR/ O' L+ L% `/ E% ]4 _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ t9 O; ?# `' M* h9 {4 W# y| MCASP_RX_CLKFAIL
2 z" X4 S$ I# M$ J7 M! E( m6 k+ z| MCASP_RX_SYNCERROR
& |- G/ S, r. f5 m| MCASP_RX_OVERRUN);# l, h% J( k& M f$ D
} static void I2SDataTxRxActivate(void)* Z3 G6 [) W( k4 p
{
* u" g& E8 V* p, n/* Start the clocks */
' T, U' Q+ g0 {/ Y7 |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 r: e. t5 y/ ]4 T2 w0 m; L" tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- D/ q7 x- J4 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: q. `, g( o9 q2 I
EDMA3_TRIG_MODE_EVENT);& [9 E" r1 t5 y8 d8 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 P8 G- G% k9 D# W2 J8 ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# q6 p9 i# \ g. E! y1 [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 p5 U% \1 K* D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
V9 K) c% e- M8 c, E6 y. v/ U7 Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: C" X' Q/ W3 H# B- }9 _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 a1 W3 _8 w0 b, e/ Z7 zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 J- q0 r; B5 R& R4 Z# v/ Q( w} % t) t. V2 s# g% f1 h, A3 U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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