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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" F4 S7 G$ S& E8 h9 @1 binput mcasp_ahclkx,
% b) O7 e6 p1 V2 e4 U( O. V `input mcasp_aclkx,
- w$ N: b4 g: T( J. @0 H2 ^; |& f/ Kinput axr0,) s: X4 d4 P9 D2 W! x! a2 Z
& a8 t: a3 }7 C) M
output mcasp_afsr,: E( Y# C3 C" R3 \3 o
output mcasp_ahclkr,
/ i, I; K7 x$ S1 Zoutput mcasp_aclkr,5 v C; B8 ]$ W6 d
output axr1,
8 R6 C3 T% l; A0 w assign mcasp_afsr = mcasp_afsx;
; M: b0 g0 x& s0 I+ F- U, d' L8 P4 Massign mcasp_aclkr = mcasp_aclkx;2 i5 w: Y& J1 o4 l6 C! C- e3 l
assign mcasp_ahclkr = mcasp_ahclkx;
: O, _( p) V& `) x6 Lassign axr1 = axr0; ( y+ T+ v: c( ^9 }
O' n; R7 [$ g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' |( t- q/ x5 v- n
static void McASPI2SConfigure(void)
) }# S6 g. a# `1 p+ M- y{
$ C/ K3 @8 @- dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! ^" t! c4 ~- E3 p9 K5 h: e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! o, C1 `. o1 M7 V1 tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 j: U, ?! p! V% ~8 i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 ]5 u8 ~; v1 _* [ Q* @! W; g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% K" H, Z* {+ OMCASP_RX_MODE_DMA);: e4 {, z3 |( {* n% R, p$ L' W, r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% [5 M9 }7 x" k* x& g% P) ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ n% S' q* s/ L: ~" f+ D% `( P' `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# n( J3 U8 I/ Z KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' r# K3 J1 |) m$ D# _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # L4 i! h" ~/ ?+ P2 Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ I3 N$ ?3 k8 r7 e, k, R+ }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) b" a+ L+ e# J, q2 }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 G; E3 U4 D& H( @) {2 [+ F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 D% _. b+ ^4 @6 @- S
0x00, 0xFF); /* configure the clock for transmitter */0 R/ `. g, O5 v: K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! m/ t0 l, q7 N T# SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) W1 \3 x _# q8 U( f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% l/ u3 j1 Q6 J& A- \0x00, 0xFF);- F( p3 w. P7 o, J
" I' e2 W5 T5 z7 \# _5 {4 s) N/* Enable synchronization of RX and TX sections */
( w6 s. v! E, W! [/ QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) L7 z& L( s' a$ }* A5 D# p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ g; y8 y6 b8 y9 {3 w/ yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# G1 ?5 ]) d; k4 e e) y& K** Set the serializers, Currently only one serializer is set as
, G0 ?) B4 ~6 r- ]/ e** transmitter and one serializer as receiver.
% g/ f2 |: r7 q) N* f9 a2 l! n*/' q+ O. Y1 {3 J5 D ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# d, a8 `" e5 R* p8 {6 o7 N% P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- u, y" T6 A' A7 G4 m" W$ G
** Configure the McASP pins + s a5 V6 @ L4 c) Z4 W& ?2 o
** Input - Frame Sync, Clock and Serializer Rx
5 x& J7 P; G' P- s- W** Output - Serializer Tx is connected to the input of the codec
# H7 _ ~. G% y5 d*/
' M+ k; P# m6 W, \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* v4 }& k- p* JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% M# D' p. R! K0 Q! [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( O* Z6 H: ^$ \, ]8 n| MCASP_PIN_ACLKX
/ Q1 o( m( s0 P5 f| MCASP_PIN_AHCLKX
" a# Q9 T0 f3 U- M# ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* d2 q3 `! P- P7 s# b2 V& r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 B9 Z3 r0 a. o0 Y& R
| MCASP_TX_CLKFAIL
. O& y4 o1 T1 L K+ _0 k1 C| MCASP_TX_SYNCERROR, |9 Q( O6 i& n: D$ D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 j3 W! G8 _ W! f" L7 L' n
| MCASP_RX_CLKFAIL, L7 R- x7 N- i+ d1 o$ O
| MCASP_RX_SYNCERROR
' U" W5 j- ?6 R7 a| MCASP_RX_OVERRUN);5 S; [, [6 Q4 S. b# s* s9 W# [
} static void I2SDataTxRxActivate(void)
3 {3 m9 m* z# u( Y{
% O" U0 \$ Y$ x( T' x0 z/* Start the clocks */
5 x. v" W$ b0 l5 [) w. o/ o1 {+ kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 z1 _8 V& D8 R) p6 f( \% |2 p3 y1 h/ }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! m) N# k8 f/ r: g1 K/ w6 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! K2 `$ X2 `8 qEDMA3_TRIG_MODE_EVENT);; B, L2 O1 `: S J* ^" K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, q$ k# f7 P3 j, g }. X$ ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) A- ~" D' i% o+ `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 j, [' b' F2 p+ P# DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// y% [. R7 _: x: \' b& Q$ N5 P* B% r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) ? E0 v/ B0 ]" p' QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) f% ]3 c% a# g) {9 N) s. _5 S, Q/ r8 dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 G1 l, H0 ]( {0 ]( X# u5 u9 m
}
- T S. O& Z* }7 Z, R' s4 s* {7 F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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