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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 I- j- Z# [& D
input mcasp_ahclkx,
% ~4 b" ~9 m3 s8 s6 ?9 d! G3 Finput mcasp_aclkx,
- H6 D0 @! b0 @/ r3 G( Z1 linput axr0,5 Q4 b! ]) K2 Y# V
7 t; r& Z- o( g% I I8 \; Koutput mcasp_afsr,1 g3 P8 f; b3 I: h
output mcasp_ahclkr,
( ?) d1 g2 i7 l$ S: b, Goutput mcasp_aclkr,9 }" O# P$ H" I. w, ?8 c0 @
output axr1,
5 m1 I3 z; h7 Y9 C6 ]# P9 D assign mcasp_afsr = mcasp_afsx;
/ C- W) v6 n. q! R# A8 C; oassign mcasp_aclkr = mcasp_aclkx;1 n. H0 B% P! Q3 y6 \1 ]1 u6 D
assign mcasp_ahclkr = mcasp_ahclkx;
: Y2 O- v9 X8 x$ s; F- Z" `4 W$ qassign axr1 = axr0; u2 r6 k) j. m# D
6 i1 c X) \: T; v/ Z4 D, |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; w6 Q2 i' o$ d+ tstatic void McASPI2SConfigure(void)7 N- x$ ?) A7 y- G
{9 ~$ E, w& U3 u( P! S+ T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( b8 k# V# I, f7 O3 yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 r! j3 k* w) u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 _2 `9 k* ]& I8 @- O* n' v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 j2 f* n4 S9 T! M$ m; Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. M! ?2 u" q* b4 E1 D+ ^ @
MCASP_RX_MODE_DMA);
J4 U, O# d' H0 UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 [5 u6 y6 \. X! D9 g4 ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 r$ @% k5 u2 |; G$ `7 E) ?7 c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, D8 k- m4 B. A, k( w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 W* D! u- [3 W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , B! a1 l" `1 i6 a/ P5 n$ u+ P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& v; f" }+ I! rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# Q$ K1 _0 G' L9 i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " y2 l. E& I6 b9 k- S5 u" K# I% I& u! ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 N) \) ~! Q/ |+ W! W0x00, 0xFF); /* configure the clock for transmitter */# h3 ^; c8 V* T3 X B! Z/ K. o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( z0 {6 I$ X$ h: q, |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 \" K8 S, Z! g* c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
m. B* K, F# V$ V4 L" Z3 c# S0x00, 0xFF);0 g z! J: j* u( ~& t( B
8 x" m% _5 ]* n6 z9 b/* Enable synchronization of RX and TX sections */
% `9 Z2 S" ]+ ~. E% I1 eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 Z8 w8 C# J5 k' p% L( l- |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 I' ^7 ]6 ^% M' Y. M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 t" Y; Z9 K1 |) `# `; Q" ]8 w** Set the serializers, Currently only one serializer is set as$ O6 D4 x+ h$ `, \
** transmitter and one serializer as receiver.1 r. t; ~ T6 y4 }; d
*/0 E5 X! ]8 M0 X4 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& `7 M5 | w5 E+ o! Q! _, W9 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! S+ w* I; M) g* X+ d+ S** Configure the McASP pins ; F5 A( g6 K0 V+ n1 q4 b3 F( K
** Input - Frame Sync, Clock and Serializer Rx
3 C: @# T( q- D2 j' V [( @** Output - Serializer Tx is connected to the input of the codec
8 f4 p1 r$ u8 U3 m. u' \*/8 f" B6 i; c# q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* \1 c" G6 p5 e# }8 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, M0 @# _. B9 t6 K( N2 @& ~0 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* f4 R$ O5 a: q5 G u% U9 k| MCASP_PIN_ACLKX7 S; ?4 o& p* @3 G7 F! j1 x, m
| MCASP_PIN_AHCLKX
9 m4 ?" c' T0 e( f! i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; H1 c, p. G( q2 {1 k8 b* v4 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 ]8 v0 S0 T4 i" ]" S' W/ C6 J| MCASP_TX_CLKFAIL
$ I% J# r* h( k- i: _+ j| MCASP_TX_SYNCERROR
8 D4 h4 g, ^; v% L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% Z p. m) H3 n6 u" p1 `| MCASP_RX_CLKFAIL" ]5 P- U, m8 N- G C1 E
| MCASP_RX_SYNCERROR R+ t+ x/ y( E4 k
| MCASP_RX_OVERRUN);
$ n1 ^6 v2 d$ p) s} static void I2SDataTxRxActivate(void)
" O' H' F* H+ {& c7 m: I{
: {$ e" l) @ Z! |0 F4 r/* Start the clocks */$ K* b7 a8 ^& R' l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) j) J; Y9 p7 Q2 dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) g: L* ~: ? z, XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, _+ r* g8 E) z: L. h% @- d
EDMA3_TRIG_MODE_EVENT); Z3 p3 r) s( y# U, q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ Q. `/ `, U) Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 B' D( T$ z" Q$ c! b6 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: x- S4 y! p% c) l9 g! `2 ?3 L5 ^! I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* [! p5 I$ z# }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- |6 _8 J# Y5 m- Z& c' L7 H, dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- W( b( t' _6 ^, f" X' OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" t! B3 O: P$ f# ]! ~}
, x3 ]& v, X) ^, L& K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / L2 [# u/ s" f: F9 A8 g
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