我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 X% E; Z- s5 B' E" m. S8 C& ainput mcasp_ahclkx,
) ?4 t( ^* N, u* R1 r( Z0 Binput mcasp_aclkx,
+ V6 K5 p6 x) }' finput axr0,$ U) F4 C+ m- V0 l3 b
, _# C8 ]! H6 |$ T/ g' `% noutput mcasp_afsr,
* {; R9 ~# I$ [output mcasp_ahclkr,
T, J& T" U2 D/ y& [8 K3 k* ? n5 v; Aoutput mcasp_aclkr,
) ` C8 a9 G( w% S, q9 Goutput axr1,# b5 m% @# l, Y7 q
assign mcasp_afsr = mcasp_afsx;
! t4 s6 { K- \1 D passign mcasp_aclkr = mcasp_aclkx;
9 ]& N( U1 O$ i `) ?assign mcasp_ahclkr = mcasp_ahclkx;6 }0 W: U, b0 v6 u7 ?& |2 D! L
assign axr1 = axr0; % O1 _0 t4 \; o, {* ^' k2 d9 m
3 K! a; B0 z% P1 |# ]7 x! s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % X l1 e, I, q$ t4 j% G
static void McASPI2SConfigure(void)* B& U0 H/ _8 C+ i( G* q
{
, h! y8 r- K8 T5 JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
q8 p- G8 {3 u+ _' Z jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 p# X$ I8 s, {, o1 m7 j& y: y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& j U1 A4 x C6 q6 k; F7 a+ G- `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' x9 O" K5 V9 j0 W2 C6 w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, |" X+ k* d" M( A+ u% _
MCASP_RX_MODE_DMA);6 h' n9 ?5 k# T' ~3 x1 m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 O+ x" ]1 r9 K; B) l1 P2 Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 s/ [5 c# J# k9 ]3 r+ C1 A. t1 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 q2 P' O) q0 N0 e B* V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 `- v$ O, a& k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * e; u% r) m u4 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; a- }/ `- R; i; ]- n# i1 q$ n8 N5 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 b/ `! y) X4 P+ N6 S% g$ V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& \& T7 p I+ a. N2 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# y7 V2 N- W* n& k0x00, 0xFF); /* configure the clock for transmitter */8 n5 J9 s% P8 Z" | f- O* |: H( R# ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 r+ \/ h% ?7 D; L+ xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 y: u; V8 B0 m0 L8 L% M. Y: I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 T0 {1 Z4 ]$ g0x00, 0xFF);# a- N" v! Y1 I
( ? {6 G3 v8 Q& W! j( z, G/* Enable synchronization of RX and TX sections */
" Y' q0 V. I- @8 z4 t+ LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ g2 e: \0 n I+ Y- |" v8 E) XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* j6 y( v& y0 ]4 u8 h/ O; h [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: Y) H( }. B' ~
** Set the serializers, Currently only one serializer is set as
4 y: E% b2 Q$ a+ s B+ O# [** transmitter and one serializer as receiver.
' b# O+ ~8 s- s5 `2 Z4 S% M*/5 y+ ]+ M. a- o3 ~3 F/ O! _% }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ X8 e# c' ^9 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# B) H. E1 d6 V6 o0 z) V! B, _
** Configure the McASP pins
4 X8 b H& a# q4 d% E& Y% I: Q** Input - Frame Sync, Clock and Serializer Rx
" \+ @9 m8 K* ~" [7 z** Output - Serializer Tx is connected to the input of the codec
2 Y7 V# {. x6 i3 {& |& W*/
/ R& p4 X U6 q4 L* s# p4 SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
b6 \' ?7 L N) Z% xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 e' k6 ^, [' x! UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 i5 P0 v& H" N% H' a* p7 W| MCASP_PIN_ACLKX
: a: }4 A! p. r5 j| MCASP_PIN_AHCLKX
- Q$ N- o+ j& w) ~4 D! k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 b* G5 [ K( P* s$ m2 P1 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ \& `6 f) j1 Z+ Y3 [| MCASP_TX_CLKFAIL
3 H" U4 _& A9 G" g1 G9 X& ~3 D| MCASP_TX_SYNCERROR
3 v7 `; w2 @$ d7 @+ X# Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) c; B8 r! d9 T4 v| MCASP_RX_CLKFAIL3 T" a: z1 n: `
| MCASP_RX_SYNCERROR
9 B' a U( u5 | a" M _2 y| MCASP_RX_OVERRUN);" R- E1 Z2 r9 {1 h* T
} static void I2SDataTxRxActivate(void)
" \" \: Z0 H6 O- ?! I+ _{# A& k# C% S8 y; q. u7 f, {
/* Start the clocks */
+ D* y) K; i) R9 t% VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 T- H& G- V6 D+ u% W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 P6 P! }2 I$ ^/ i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 z6 t+ n% L, A' q! |/ v$ Q+ D
EDMA3_TRIG_MODE_EVENT);/ _6 G+ k* M! X0 W2 b6 K9 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 b& R8 T2 Q3 }3 [ {3 y. `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% i5 j6 R1 p5 j7 ?! u0 C. ^0 T7 M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 Q R& S6 l' A- X# e; zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 g6 h$ h a; w2 wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- r V# ^' s5 o2 n% w7 \2 |# EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 [* j6 s0 L4 L8 N7 u0 f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, t7 V* B. }& e H8 A; W+ T* H5 N}
# p9 y V+ `5 ~1 e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( y3 v1 e8 K, Q; U, k
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