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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 d1 Z' v0 }# O: T( H: [0 f
input mcasp_ahclkx,
- p1 S Q8 l" A9 U* V4 @0 yinput mcasp_aclkx,7 k+ v- O6 d) Z) k2 ]
input axr0,% S# O+ a% `" z* w
+ ]7 |+ i/ U7 g' Z c; d/ U& C" l( K2 @output mcasp_afsr,1 X- c+ o" ~$ B' o, a' e
output mcasp_ahclkr,
" V7 [" D; ]3 o4 i' poutput mcasp_aclkr,
# ?6 A# E; [9 f& w( Poutput axr1,
& ]: T4 l4 t+ k9 ~$ x assign mcasp_afsr = mcasp_afsx;
2 G _* m2 ~1 Z* Vassign mcasp_aclkr = mcasp_aclkx;
$ ^! a; U6 i( S) ]: I) aassign mcasp_ahclkr = mcasp_ahclkx;8 h# |" N3 P0 W5 D, N
assign axr1 = axr0; 2 \; I# U& d: ~2 B+ f& `6 C- n
/ K0 b* j- D& |2 P" ?% L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 z [# @4 D# B( o- qstatic void McASPI2SConfigure(void)# U' @& e( i! M! S* X L
{
, u4 q1 |6 m5 _/ i8 h) BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& m. g4 \2 L7 G! _( g5 @5 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) b% g/ ? h, T& l* i! {9 y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
|4 O5 {& |5 c! O! [8 v- WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 F1 n, z3 `% z/ B$ WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; \- Y: S2 Q/ @- C, j# x
MCASP_RX_MODE_DMA);7 }. T |, x `* o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 v7 s0 r# z+ O+ |! {5 G! iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- a) \# [7 a- y& d% EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # D% w2 S3 i! I# Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& G% a4 V! ^+ g: Q2 jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; P* V4 A, B9 `; _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. X: W6 Y; O1 K2 h- h. W3 T- uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ f" t/ F% `& O- X) dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 C/ c# G7 P, g4 o0 \6 S- KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" @/ {1 s* g- ]0x00, 0xFF); /* configure the clock for transmitter */9 t/ [! e+ @1 E& g; `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 {, g) o) n( P- VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
\' K) ?9 |2 |8 J' P4 N: f. W! lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' n- y4 j2 E$ s; i- v0x00, 0xFF);7 }5 F5 B% x. l5 M% u4 k/ D3 s
7 x5 s) u2 `' |2 }7 ]. `& a( m
/* Enable synchronization of RX and TX sections */
7 t% _% U. o5 n5 B- E2 _) JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! i6 \% F* \+ y" H0 B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 }2 H. H: a# sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" O; w8 o! b$ b
** Set the serializers, Currently only one serializer is set as L, t4 X3 x5 e& r; N7 G& L" G
** transmitter and one serializer as receiver.+ M4 J! S# X% t" W
*/
6 R! u6 c4 I5 Y; A' Z b+ }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); ^' N! k {& o h# i9 s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
R' Q7 c% Y6 x# i6 p** Configure the McASP pins $ Q9 J7 l3 d X1 Z! v2 K5 o! }
** Input - Frame Sync, Clock and Serializer Rx
: D$ M* t/ }) T3 @1 f** Output - Serializer Tx is connected to the input of the codec * \- ]+ h/ P2 a7 }' X* j5 Q
*/
h; j; ]* V0 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: ~. m' a: _9 c$ qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( g" V9 w1 L" w' b+ Y& F4 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 b% _ M' B2 I- F/ h| MCASP_PIN_ACLKX
' G1 U1 X" p K& w2 H| MCASP_PIN_AHCLKX
* A* J9 R3 ^& }+ ^) f2 a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) Y3 l/ f$ [7 y6 n# s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - y5 I0 o1 } R0 h6 X& T. B/ J* z
| MCASP_TX_CLKFAIL
7 ^; l( }$ L' P3 s| MCASP_TX_SYNCERROR
, `3 B1 T! ?7 S2 Y d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( n( M: X' N) [$ T5 ~1 ]9 O' f
| MCASP_RX_CLKFAIL
( Q; ^3 Y5 `( B7 f0 w3 c| MCASP_RX_SYNCERROR
" C# l2 L# F) y/ Y; g9 m) k| MCASP_RX_OVERRUN);4 L1 m/ Z2 M; o
} static void I2SDataTxRxActivate(void)3 y/ N9 A/ p3 R
{
1 y" v$ y) o/ X1 o* s# R! }/* Start the clocks */# [$ t3 j" R8 F, m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 `: D4 f) m5 r' zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: F, P9 W1 }, x4 c& C4 R% m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" a" }. k4 V/ J( n& |) WEDMA3_TRIG_MODE_EVENT);$ v$ F. A3 s; J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ C- }, \+ l# C+ `% wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( K$ A" D1 @) a0 N" ~! G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 y( y7 o, @1 X1 ]/ s7 \& F' ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( ]) h( [7 j. [1 U- D+ I1 p; a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) ~& z8 L2 E( ^- IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! f6 e5 X( _( a: N6 d- pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' u2 F6 Y0 h- m. E}
% G4 L- s- ^+ [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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