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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 H3 B! l! X4 ~5 ~: I# Linput mcasp_ahclkx,
* W9 J! P7 b- X4 j+ binput mcasp_aclkx,, _1 a+ c) N. }0 ^
input axr0,( @8 _: p8 P6 i( N; B- w4 W0 x! s9 y
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output mcasp_afsr,
6 s4 s) N. C2 r) l" d, }output mcasp_ahclkr," D7 r! W. \7 f: s
output mcasp_aclkr,7 M8 {7 U$ D* ?- o0 z: G
output axr1,. B' x2 t* P; k3 U+ v! L9 v ^
assign mcasp_afsr = mcasp_afsx;
$ k9 h r( x8 V6 Nassign mcasp_aclkr = mcasp_aclkx;
' _; K' C7 l# \- ?7 l8 \assign mcasp_ahclkr = mcasp_ahclkx;
$ b) O! Y2 ^3 m5 H# Vassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- c h' g, p. p$ A' A8 a; Q9 jstatic void McASPI2SConfigure(void)
; K1 W* G) m2 h{
$ o; W5 O, r# x5 D+ U, N1 c/ hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 N, T* i% t" ? u! n3 Z8 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ M9 e) `4 u* u. Y; H3 z4 q/ bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; l. t$ z* `7 k3 x0 p0 l' @9 V! m7 k# P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& n0 A- S/ q2 c7 T9 ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, V9 e, e- n1 e- [6 ]. I! DMCASP_RX_MODE_DMA); r( h3 `8 [6 f$ W3 `% z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ z% {: J+ d, `7 a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; [5 R- G, o/ ?% t3 r7 }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' S% P- u( s& _8 D1 H) YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ \: W% e1 E5 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 f2 h% ]: A' p( S3 w& ?. B( C b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 w+ O$ _5 P3 c+ Q; dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 g# {" |- k+ B- R" |9 X+ S+ o; ]* ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# ^$ |, e* U8 z1 c% yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 S, F' o( ?8 C0x00, 0xFF); /* configure the clock for transmitter */0 J7 E1 Y, w; ~1 |2 n# E* ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( R! c5 `# t" C/ G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' |0 x7 V( N( P+ ^/ sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, ]" I4 i. C- Z4 f
0x00, 0xFF);, R& h& R2 \! U8 t+ X6 Y
4 ^7 B- ` X6 h9 o ]
/* Enable synchronization of RX and TX sections */
. A2 x2 K2 B' u* QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 O* @% x) i# b3 h+ IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( t" E9 q0 g2 ]! P7 V. l; rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# w4 N3 _+ l3 y# b- I5 \ A
** Set the serializers, Currently only one serializer is set as3 t* _4 H# k( o6 N( D7 ^
** transmitter and one serializer as receiver.# k: w, |+ k* i) ~* c: V# M
*/
- h, a B5 n1 N# Z( i% FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% K$ |( w4 }) ^5 e; x# p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, p% A. z' b) c% z9 ]
** Configure the McASP pins - ~+ Y7 x' m, ]+ |. m
** Input - Frame Sync, Clock and Serializer Rx6 N- f/ O4 O9 y
** Output - Serializer Tx is connected to the input of the codec + i# V9 P" n& p2 E& }4 Y h
*/
0 n- Z- W0 c J+ ]- oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- F$ i* R9 | U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 j5 T' U( u4 J0 Q" `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 o) D3 u5 P8 ~9 s$ f" o| MCASP_PIN_ACLKX
0 T, Z1 k; u6 d3 w! R$ c| MCASP_PIN_AHCLKX
9 O) \' H( s- Z/ b' p5 T0 w0 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( G/ \" p q; I1 f0 X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, k; @7 y& o% o" T8 |! m| MCASP_TX_CLKFAIL ' _5 d7 i h2 b. M) N
| MCASP_TX_SYNCERROR
) U9 C3 i: [' `# o5 m/ |& [% A/ [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # y9 b) m5 j( H6 Z# V9 y+ s
| MCASP_RX_CLKFAIL
2 j* ?3 D5 J# e; @* Q| MCASP_RX_SYNCERROR
. W8 f9 z1 ]5 D| MCASP_RX_OVERRUN);4 h' a+ }) H+ q/ |" R
} static void I2SDataTxRxActivate(void)
$ W" M L' c [9 _{
; X3 ?5 j; j" x* w& H! j! J! j* z0 Q- u/* Start the clocks */1 y* l' @. i/ I1 m0 O4 Q+ K4 b* w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 P: ^# [4 P2 Q4 U3 n$ J( `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; ` h: _8 ~0 a% m* dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, K/ n" O8 o1 H7 E" m: P; Q8 y# T
EDMA3_TRIG_MODE_EVENT);% t6 G" x, Q+ {5 O" }6 D2 j/ W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' t; H1 I% _1 j) i& R4 b( ^5 \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 q( d. j, o1 U+ F ~+ g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 r7 u* o* {4 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* a) L* e- t& u4 w0 f" f+ r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# Q! o# C& X5 Q* b0 b& j/ ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. m# E0 c7 x% EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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