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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 r8 K. N' l: ?3 I* w: J
input mcasp_ahclkx,# \8 |4 a. k. @( L" v1 D
input mcasp_aclkx,
. T2 S' [: f/ p3 Tinput axr0,
h: L1 G% z! Z" ~
4 r7 N1 U- y% R; k9 w' a9 g, l, W6 Eoutput mcasp_afsr,8 \ W) ?: m! \8 Q
output mcasp_ahclkr,) c0 @- k9 m6 u3 B' g: U9 d/ t
output mcasp_aclkr,
% S" ?2 ]* P% Ioutput axr1,
6 N. g1 D: L- }/ l# o4 |- | assign mcasp_afsr = mcasp_afsx;
/ Y4 W. r; Q. Bassign mcasp_aclkr = mcasp_aclkx;7 s; [0 ]9 f3 f" `
assign mcasp_ahclkr = mcasp_ahclkx;
1 T9 Q% G/ Z7 P, F4 d' l6 s5 Tassign axr1 = axr0; 1 L5 Q8 N; Q7 G! C$ w9 a4 n
- _- N% s) X: f1 R$ [/ k$ {$ |' G/ T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , q8 c& o5 i' \' ~+ L
static void McASPI2SConfigure(void)
+ g8 Y! t% k; ^* b) N4 ?# C+ v{
! j. C; G8 g7 h! E0 q& N" BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 j, i; X8 A8 [& y4 m- h1 E6 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. _4 A8 J* g2 A7 x9 r7 u& d! x. ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 U" B9 D3 R% UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 P# C2 X5 N8 j' @- RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 S# M! z: ?* O$ A% Y- }MCASP_RX_MODE_DMA);% ?' a' k6 T( C l* b$ {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) K1 u+ w" k2 X5 x- y) D' P9 _* t! jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% ]) w0 R4 w9 ^7 i; L6 ^ {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: E2 ~$ H7 O& x# R& E$ ^: T+ a& j+ wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, K% {: F* E# q' n8 {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- p' v; t- {4 T7 j* UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( i( _0 H$ N2 _1 t. b/ y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 V/ w9 s5 ]8 B# B. I# r' gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. P1 V: ~* p4 d8 B; G N! dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) z$ h# M. n. L0 _( Z
0x00, 0xFF); /* configure the clock for transmitter */
! _1 `: I Q+ i7 s( {7 ~ `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 M2 g6 W* N' \+ `& P' o8 |+ o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % s! U) ^; D* {- e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ D ?) g0 Y+ X0x00, 0xFF);# l, r: f' Z/ W. q6 v4 f5 @
( c5 D: r# t) ] T4 `& F/ y/* Enable synchronization of RX and TX sections */
T( G m+ z9 g8 ?3 l: N% C# p7 w$ IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* S" ~9 u, F0 S% V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 r8 c% E4 a5 [8 O7 EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ R; h1 P8 u/ }5 v+ F
** Set the serializers, Currently only one serializer is set as' w8 b5 P- G& @+ D0 [
** transmitter and one serializer as receiver.1 F6 [1 j1 b5 @/ I
*/, P4 q, N" r1 W" Y, G; x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; Y. @# V7 G1 i2 u J. L( `7 s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; F* L# l0 R) ~/ e
** Configure the McASP pins
' i! c/ V1 f) l& B2 U! N** Input - Frame Sync, Clock and Serializer Rx
0 b4 F* L4 m8 Y- m5 X** Output - Serializer Tx is connected to the input of the codec . x; _7 ~! [" W: T/ \
*/
& ^8 n. O* t! j% C" fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! s: y8 n4 s9 ]( |5 R" f. aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 f) I' g @, B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ l4 k, S% t7 O' l& {, L| MCASP_PIN_ACLKX
, H# S1 p D+ k) `! j| MCASP_PIN_AHCLKX& G, |# {/ ]2 v3 z% u- F/ h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 E- M& Z/ N2 L3 e* k% JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 C& A' {5 U0 p
| MCASP_TX_CLKFAIL
# ^! P2 r/ r! N* s| MCASP_TX_SYNCERROR
7 P- [) I1 v% M7 j! J) q. g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / _/ v1 p" i2 h" J: N% i$ K# Q
| MCASP_RX_CLKFAIL4 V$ l0 E1 k* m0 n( b+ B6 b- Y
| MCASP_RX_SYNCERROR 5 ]4 d, @* ~ G) e" c
| MCASP_RX_OVERRUN);
9 m/ v, N9 m k} static void I2SDataTxRxActivate(void)
% p L0 k! l( C1 W& I2 v{% l u2 [! f, E8 f. {% m
/* Start the clocks */
- T2 C& l) U n& i# _' KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 f2 ~3 f8 T a YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 @$ j0 P1 w9 z5 \. [5 Q* Z$ zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* m5 o. ]$ _4 d0 w; @: v' \& AEDMA3_TRIG_MODE_EVENT);
# _% o. h& a6 e' Z; m5 i% vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 `. K1 N/ H- Q6 M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: x: X- ^7 O4 Q( b4 W: C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 X8 S7 y A/ v" r- n: {5 TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
I9 P( N2 t9 {: F" f( V, cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& m( L- c' d* s0 g# U! F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ @ @: t" y# Q" D. AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. `9 @' N3 T# M: L3 Z& V}
/ W% n! k1 o! W$ @6 M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * _' |) v G. G2 p2 |
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