|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# u% X7 v8 ~, e$ M: x$ Q
input mcasp_ahclkx,
3 g2 A/ h: t+ p( s- q5 Winput mcasp_aclkx,
: P A, r5 _: C* e3 ?& qinput axr0,; {+ {/ R5 M9 X( b @
+ u7 j* Q0 U* F! l! M
output mcasp_afsr,
+ A8 T5 l! D9 z) Loutput mcasp_ahclkr,4 p. I) J) t' b0 r
output mcasp_aclkr,
) m3 q) f3 ]; f* N) m1 _output axr1,9 H% m( b7 z* S3 d
assign mcasp_afsr = mcasp_afsx;
( V5 j3 t+ i% Q' massign mcasp_aclkr = mcasp_aclkx;4 t/ v8 ~& j$ v4 y" Q
assign mcasp_ahclkr = mcasp_ahclkx;: P- N8 R0 P: C8 I( i/ n
assign axr1 = axr0; ' {2 P: b! N; J; W" G8 V
# q- `+ b- Q4 [/ m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 k5 S4 n8 H9 ?: K$ b8 x9 _0 Nstatic void McASPI2SConfigure(void)
9 o! f9 e% w) J: V7 B( F, c{/ f% ~% A" w6 P, S8 P' R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ t9 N* ]$ J3 J# S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 R/ ^$ P8 Z. t- O& z% u; d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! O9 V# `8 O4 s! i( ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: u7 p0 o! \4 @+ v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 o$ [4 W' ]3 k5 HMCASP_RX_MODE_DMA);3 q, j9 {; [# P$ w+ B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 q! ^% v5 e+ l( p: K1 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 H6 ^& L7 ?$ R4 v% k; C) ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 ~* |+ N$ T7 \7 w9 d$ N, \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! s3 x! }# |% |9 U- `1 ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. P% Y5 E6 d/ XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! N* r1 o7 ?9 k* [0 LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" g$ e1 K0 j; t% C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & ~" {( P5 S2 Y. ^/ W4 D$ R4 N1 e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# e6 l- `5 n2 I& a0x00, 0xFF); /* configure the clock for transmitter */, M3 F+ `* d' k6 I. f- e7 w. P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 |, y7 g! |' d4 ]9 R) ] U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 e/ B" @5 E8 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 x7 }/ y) C6 K, ]9 R7 s0x00, 0xFF);
5 }1 _6 U$ K! k& w+ G+ a, s% S; J; y% x; U
/* Enable synchronization of RX and TX sections */ / Y0 I+ L# [+ L2 i2 g8 d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& `7 w$ M1 J4 Q% r: Q2 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ z7 ^/ Y( ~) I3 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; v. e7 C: X7 ~" R: f
** Set the serializers, Currently only one serializer is set as4 Q- p' |% L! R
** transmitter and one serializer as receiver." h5 r6 U- ~. F9 |
*/
* X) H. L1 L4 c- j; l4 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: K5 v+ o) G3 D7 ]( RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
w$ S9 H8 s: C+ b9 |** Configure the McASP pins / M- f u% f) J8 l0 b
** Input - Frame Sync, Clock and Serializer Rx; N9 `( m( V3 l
** Output - Serializer Tx is connected to the input of the codec
* c0 n. |7 Y* p7 w% o*/8 L) S( P6 Q N. i& }0 G7 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" ^! v% B U8 ]' V& iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 z5 L% e. I% I5 o# QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" U6 B8 F- q! B: G$ @6 F3 T7 X3 E
| MCASP_PIN_ACLKX
/ _+ N! Z' F0 ~- x7 j- P| MCASP_PIN_AHCLKX8 J8 V3 Q; u+ m& O- W; ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 M/ o G3 c# s9 [. o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * i0 o4 s0 I: ~7 }) a L8 |! [
| MCASP_TX_CLKFAIL
& |) O( i4 R9 L( b7 h| MCASP_TX_SYNCERROR
2 ^! L3 F& Q" G# L! K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 v- m+ e: v4 X8 ?" C| MCASP_RX_CLKFAIL
- S# }7 \# a5 J' \7 Z| MCASP_RX_SYNCERROR
6 j9 T6 u" w+ Y3 G7 {# q! `8 N| MCASP_RX_OVERRUN);
: A2 c2 r G4 C} static void I2SDataTxRxActivate(void)7 o& q+ R* }! v& `4 S+ O
{
; z [3 i5 a) V: J% w N2 M# n/* Start the clocks */
8 u( @7 L+ t. F/ u8 M' r, \# MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) L9 O: I* K' I( P5 D$ J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' M6 ]3 l2 a+ z: E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! t* l* ^8 v W8 w* O" O( f# F
EDMA3_TRIG_MODE_EVENT);7 v7 d1 ~5 U h2 S4 }# E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 p0 f0 U( ?, Y5 YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' h) w8 z: r+ UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 ?9 n5 j5 R, x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ U8 ]: m6 Q8 h! \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) O( J ]) E0 U" n& Y( Y. EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# a; l9 `7 R& [1 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) e1 @3 |" b/ ]} 1 N- J b3 j# r0 }. P, c% b( C( {- T% P8 t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ \5 }; `3 i5 X) |
|