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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. a' n5 e9 K9 [% n; K
input mcasp_ahclkx,
7 W; y2 i" S$ @" K5 ?& w( Cinput mcasp_aclkx,
1 i) ?1 Q& S( m0 oinput axr0,
. b6 d+ n1 F. h |" o
3 }* D# p p& {( voutput mcasp_afsr,) D! a* C: `' e% V( z$ a
output mcasp_ahclkr,! H6 R* r7 F4 K/ o" Y$ y- t: w
output mcasp_aclkr,7 U+ C5 i1 M7 J9 A" `, m
output axr1,
1 J+ I6 L! z# G% Y assign mcasp_afsr = mcasp_afsx;: Q5 @/ ] ~2 b& s! _
assign mcasp_aclkr = mcasp_aclkx;
8 V& S! _6 g9 O- u) D: ~6 q4 I$ \assign mcasp_ahclkr = mcasp_ahclkx;
* r Q# m+ y) R0 A+ p, Eassign axr1 = axr0; 5 j+ R9 i% Q5 v N2 O1 A
; ?. ?; a. |8 \/ V1 E4 P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ k _# Y+ ?# g9 Lstatic void McASPI2SConfigure(void)
; K* A" U6 x0 i8 h% r2 y- X{7 H* A! J6 ~* p7 D0 j$ k3 P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 X* V0 X4 |8 w6 h) {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 h* k M& X$ y4 q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% D6 x* g- h( j& s) a. z; A3 dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( i9 h; |( e% p5 FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 M& w* D- R" x& K \MCASP_RX_MODE_DMA);9 P2 U9 \1 S7 o* b" }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
X3 E+ D, [1 Z9 W, ^8 p+ sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 p: Z( k! h, j2 J4 c* n- `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . e5 l/ v$ u5 ?3 U& e# h7 ~! g5 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" |" r+ A/ }& R0 H- ]; E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ d- Y+ m: C( X6 |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 x9 g& g6 ^& _% z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 E, y7 U9 }+ I. [+ r# ?2 c8 [1 GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' u0 n' ^! x! l. b# i; a& }) [+ Y4 t9 n3 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 T$ e( G' E1 \& R/ O# Y
0x00, 0xFF); /* configure the clock for transmitter */, p$ b- [: U& M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% u+ ~0 q4 e# L4 N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" J, R, @1 h! t* AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' B9 U: d) I/ ]8 S0x00, 0xFF);( G2 i$ j. H# V0 g
+ ]& Y9 f3 j( g5 I/* Enable synchronization of RX and TX sections */
) C5 I- A1 h8 f. E3 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) ^. e8 Y/ ~; H9 V# }& p5 o+ L4 H" H& f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 |; k1 G# Z6 r% M6 E; b4 v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 C, I6 l b- O. K! K
** Set the serializers, Currently only one serializer is set as
9 N5 @$ h( o! ^) C. c/ M** transmitter and one serializer as receiver./ X% r% t% J6 q) g
*/
v" Y1 A \! [( Q5 m2 S: W1 B9 S: BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 D* T9 G8 Z6 F' e$ hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 K* D( n7 f) ~+ i+ T: [** Configure the McASP pins
. _) b0 {+ @1 M( Y) q/ Z** Input - Frame Sync, Clock and Serializer Rx$ y" \1 c" }3 k- r8 O t; D U
** Output - Serializer Tx is connected to the input of the codec * ] }0 n4 S5 m$ Z* ^4 z
*/3 H5 M" |8 w, H% `, C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 D' T7 i* E$ @3 I8 X6 cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 M: Z$ x- I/ d# z6 \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# j1 T: B B" C| MCASP_PIN_ACLKX5 M; Z' i; v u! D/ K- f
| MCASP_PIN_AHCLKX' O! V% X# [. ?' ]; t# ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! `6 R1 S* R$ yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 N! X, W6 I5 s7 a
| MCASP_TX_CLKFAIL
# R" R4 O3 h8 {$ @" _| MCASP_TX_SYNCERROR
' i0 l) {' r2 r( e ]* B1 a4 S# v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; g, R8 e/ `2 N! o( L; H( ]; {
| MCASP_RX_CLKFAIL \- d7 \ `* O5 S& P/ H
| MCASP_RX_SYNCERROR
( U: u( Q1 {: B, Y# T& M| MCASP_RX_OVERRUN);
. ^4 U2 B, g% j9 X; `- \% s} static void I2SDataTxRxActivate(void)" Z; R2 N& |) \5 R- E
{ x3 x/ }# i4 D8 m3 g7 M! F2 c
/* Start the clocks */
- ?' S9 Q8 ]! r: V `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" L' `" G3 \0 j6 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 T7 p' X& `; y* P* h( d, N3 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 K4 F! v% W! D, l
EDMA3_TRIG_MODE_EVENT);; f' X& X/ k+ j: L3 L' k7 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" Z! ~5 f! G3 Q3 S6 kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 p S* x l8 g* D7 q% D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: L2 j/ y/ {$ B8 a4 s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& Q4 S% ^# \4 D5 L& d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ w8 Z, p7 q9 \+ z" c2 A. n, t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" G4 k, d: F9 C2 H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 N5 @% \3 i* ?( e; p
}
! D. ?* ?& H; ?$ p' [* M( G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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