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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: \- G- D1 j: c$ v
input mcasp_ahclkx,& a6 q, V, U" X8 ?3 L- s8 _
input mcasp_aclkx,) P e8 X) g" }
input axr0,
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8 J' @0 k9 z) Y1 ]output mcasp_afsr, f. i: `' @# |
output mcasp_ahclkr,- K; S- o% i. m# R- h
output mcasp_aclkr,
# H8 W6 s9 N2 D$ q+ r4 F! Loutput axr1,# L! B' ~# Q' g, s1 F* U6 h$ F
assign mcasp_afsr = mcasp_afsx;6 ~) T* J$ C5 Y3 y2 q6 w$ l
assign mcasp_aclkr = mcasp_aclkx;0 M* a" x* t# ^* l
assign mcasp_ahclkr = mcasp_ahclkx;3 t6 {' O0 \, q6 g
assign axr1 = axr0;
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7 J$ v" T: U, I8 O8 g2 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - e% J; j" w- {- m
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; V/ X u% q$ A7 H# c' qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) i3 q0 i: E/ w/ b) p: p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! p6 X2 Z( @6 r4 B4 V( [( G& X) XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 T& ^0 D: |( Q6 P$ x9 l0 Z4 C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* Y9 L p/ _/ g1 @& N2 x2 r
MCASP_RX_MODE_DMA);
/ j( x3 q B/ b) q+ XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' s6 R; Y8 K$ ]& _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( |9 h7 ]! r7 U9 AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 [0 H& D. T5 M6 t) {& e9 ~% F+ q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 P3 `% [5 U5 N4 h& u0 ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( J& l8 H/ x% t( v% J8 A2 C4 {7 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: t! \% e) X( N- [7 V( }2 CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ d! p: I$ d6 P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 a3 ]- ^" U9 ~/ n ~" T8 y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" `; P& D n/ Y* h8 x2 o5 g0x00, 0xFF); /* configure the clock for transmitter */
7 ` n% D, ?- G8 d0 C; O2 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 \3 ^) U( m1 v$ F4 N& j7 ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " [& y6 W n0 ~ F- H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! W3 k b* I" z4 q+ S3 \( G+ r3 L
0x00, 0xFF);$ u! W3 B% V' {$ Q+ V
$ ~$ m- i6 I# j0 B/* Enable synchronization of RX and TX sections */ ; P3 x# I# F- X$ j' d+ E& P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 m1 W2 b- ^6 Y2 m! qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! @1 e+ u* U2 A, O4 g' X, Q# dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( H+ F: F0 h I$ F0 Y** Set the serializers, Currently only one serializer is set as
- K, w! \" P6 _) t) W5 K0 E/ F** transmitter and one serializer as receiver.
7 O! f% g3 S& s9 g* m+ W8 H9 v' m*/
; `% E' D6 ^5 M8 U& }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. U6 \( A% m! W4 B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: w7 c" O t! V& b8 y: ?: B$ i** Configure the McASP pins 2 D3 M8 @( u m2 g( n
** Input - Frame Sync, Clock and Serializer Rx& i: k& G3 z3 x/ }
** Output - Serializer Tx is connected to the input of the codec
0 W( Z7 g/ @3 N: V5 ^+ i*/
/ k# x* ?; {! M0 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* N, Q7 P# m, W+ E& e7 N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* ?" X e2 k/ @6 b9 C5 r& l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 l; s# o( a1 n; p1 m. g5 t8 t$ b| MCASP_PIN_ACLKX& t5 T- o, `% n5 B( p# D+ }! M- |/ e
| MCASP_PIN_AHCLKX4 h4 c% s0 l! X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! _2 T5 X" i6 U" ]7 f9 {7 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' d+ K; |9 o, f. W$ A) [# ?; N
| MCASP_TX_CLKFAIL $ M0 _. h2 n# `7 P' G' K
| MCASP_TX_SYNCERROR- j, J. H/ a5 Q5 s: x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 f( X7 i; E( ~+ n b8 E: h| MCASP_RX_CLKFAIL& m% o; b) U) F- }& j( E
| MCASP_RX_SYNCERROR
6 m" j' M& M) H5 L( E% O1 r ?| MCASP_RX_OVERRUN);
9 A* m7 m3 ?1 J0 |6 N: F2 f} static void I2SDataTxRxActivate(void)4 |1 \+ E! `9 |9 A: ^+ Q
{
5 O, |( [2 E& X; X' e' w, o, E/* Start the clocks */
( U$ D- b4 |: F. M9 FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 Z& O$ d8 R( `- a( |5 F7 N) Y1 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ i3 T# `- o: j+ [+ [" w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 }7 F. Q& \1 b! Y" O0 aEDMA3_TRIG_MODE_EVENT);0 N/ A! `) I V/ \8 N$ y' o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : ^0 E! D+ @5 r3 p) r9 n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 V+ l0 R8 U: `1 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 s% N; |, J8 a: Q( t! a" t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# @) K& q% D% hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 ?( {' y0 V9 f3 EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( H: V$ ~# O+ g4 |$ VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% g* P6 L6 I* W; l4 v
} & C" [' B4 {: C% ]% `+ h. p+ h! l* M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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