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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ L9 L. \% x" U6 ]3 E* v
input mcasp_ahclkx,
" q" C, K3 ^, e) n" F! z7 t5 }/ U4 iinput mcasp_aclkx,
' V) c, E2 m1 r" G1 Ginput axr0,
' p/ m X+ M1 Z7 Q$ L" K
+ `3 B/ q9 g* b% E- {output mcasp_afsr,* ?" Q% X! n% v
output mcasp_ahclkr,
; |* f% M, N: U9 q% youtput mcasp_aclkr,
" w% c* {4 G- _9 d5 J; e8 ^output axr1,
& o8 z9 W( }( U$ e. Z& Z. ~1 B assign mcasp_afsr = mcasp_afsx;; m1 F5 X* g* d# j
assign mcasp_aclkr = mcasp_aclkx;
+ ]$ t3 w3 V/ `assign mcasp_ahclkr = mcasp_ahclkx;
1 s+ v8 R) D4 w$ O# |' ]) K+ Rassign axr1 = axr0;
+ b3 g) b# y' ~5 V$ l& ?
8 ~* Q9 Q6 p- m3 N- W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # l1 h4 K: z, E. J
static void McASPI2SConfigure(void)
! ~# m; a `. y( ^9 l/ |7 O{, `1 a* l) H8 s! n0 Y: w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) J# {" m# J l% R8 Q5 w" `6 g4 E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* \% t! Z1 c7 L- B5 d+ w( h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 H5 x2 P- s3 Q/ R. F# ?2 [( q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ m6 ^* X+ O, d! KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( f. { v6 E2 n$ m0 D5 P0 S
MCASP_RX_MODE_DMA);
- w) M, K' _8 y, M: ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, M- r' f0 A# O' `/ _" uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 r: k6 C' y7 _- ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 v6 N- v# {) q6 r2 s0 M# f- A' s/ O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 q& J3 _8 `9 z" O3 \& X9 a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" ^; f& T4 ]' Q. W/ ]3 w' z% L/ BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; F' y5 X g$ R6 A5 QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 Y/ v; y' r* z- {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 Z1 a' \1 I7 N; w8 c( ]1 T& @8 a( X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) m- i/ ?& l X' a
0x00, 0xFF); /* configure the clock for transmitter */% @8 X" ~3 b$ ^+ P8 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ l3 z/ E* U J; E. I+ bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 G" c' F7 c$ t1 `* ^& mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: v( l0 @! A9 N D# |' `
0x00, 0xFF);
; a1 N1 D" m- P( p6 E# x- Y5 r2 L
/* Enable synchronization of RX and TX sections */ 4 P ]6 h! l6 a# H- x: J( t, I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 j2 j3 }! P3 H2 u, B% @5 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" D" r* S: V, a8 E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 T/ s3 `2 n6 t+ X: j* B** Set the serializers, Currently only one serializer is set as
+ v- V# M" s6 l) a t2 A6 p** transmitter and one serializer as receiver.
( N1 ?; l" i. \* L* I*/
* w- f' J8 X+ W% wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: z$ e4 \: g8 n6 ~* W( R6 KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 C) U L3 S7 I8 c/ `! H** Configure the McASP pins 8 c9 D; w% K7 U& [
** Input - Frame Sync, Clock and Serializer Rx5 v( t; X9 L, a U
** Output - Serializer Tx is connected to the input of the codec 6 g2 X) ~, _! q7 S: B V6 b K1 x
*/
9 |6 @( r; D- f0 z2 o# HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# ^- Y4 m& l" P8 o* H& e; Y' L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 x7 o$ _' B" W5 }8 j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" L3 a8 o5 Y6 f
| MCASP_PIN_ACLKX
* p' K8 X3 k8 p0 y) ]| MCASP_PIN_AHCLKX
7 Q6 v4 X b( C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 _, P Q) `+ k1 L% P$ d y5 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 ~4 s1 z5 S" s. P- v# a* k
| MCASP_TX_CLKFAIL
& e) |5 y: k9 a( o- b+ |& l1 c| MCASP_TX_SYNCERROR
0 C) t5 m9 S/ Y' || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' l" g$ R$ A, u$ A0 O4 z' K3 O( u
| MCASP_RX_CLKFAIL' e4 w1 S' H5 @7 M( I- |( J
| MCASP_RX_SYNCERROR 8 y$ s: I$ f$ Z! r! i$ _: t
| MCASP_RX_OVERRUN);) L- B3 p8 ~, L5 }2 E! {5 C
} static void I2SDataTxRxActivate(void)
, z' O! l, ]$ A$ v+ |3 e: d9 H{# k! q7 ~. z1 W. }
/* Start the clocks */( q# d5 O* C& V+ Z$ j% s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ [6 a1 m1 t- V8 e: lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 m7 X' j1 Z. @8 V7 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 p5 x7 K) T9 Y+ |6 nEDMA3_TRIG_MODE_EVENT);
6 y+ A% V1 A$ D8 @3 ?8 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & x. L0 Q( a/ W! U! M a7 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* i* C6 l- Z) Q/ b$ z3 s, C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" X8 V* B3 [. [/ F5 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" ~9 U' {! D: Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" d, d/ v' v2 D/ @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ o( V2 \. A/ N! ^6 M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
l" k4 V- s* J8 R3 d) P& L}
! s* G7 P0 a) {6 @) M3 s% h+ {* [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 }" J: C3 g, O; M4 V
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