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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) ]8 h, R1 H& J w
input mcasp_ahclkx,
# a+ s) ~$ @6 f$ _" Kinput mcasp_aclkx,
3 {9 `. R/ W( s" n! ^: d0 {) ^input axr0,) {, u" O. U$ l( B& f
2 |9 o8 D9 m* M2 n' e! Q# {
output mcasp_afsr,- E$ s8 f) |/ r4 o4 I
output mcasp_ahclkr,* l8 s, j9 N$ d6 t1 t0 o. l
output mcasp_aclkr,
7 D4 N. X5 y5 z4 k; o8 N; Uoutput axr1,
) ]7 r8 E2 a& V! x: P# { assign mcasp_afsr = mcasp_afsx;5 T; n3 X1 F) D' c
assign mcasp_aclkr = mcasp_aclkx;
* C, a7 f1 g1 yassign mcasp_ahclkr = mcasp_ahclkx;6 }. }: M; S a, ^6 \
assign axr1 = axr0;
, a+ Q$ n! `5 L8 H" X" T8 w! k
7 V" t. M& Y9 n2 K) E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, t k$ p1 b0 Q: _static void McASPI2SConfigure(void)
3 S- l. f1 n) @4 h4 A1 ?; ?# l{
1 m2 h5 a7 C+ oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# ]8 |) [. w( S- ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- X" Z9 [7 s, ?5 e) `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' A. E* o7 |8 q7 s' ]. K$ BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& F: k+ g c; ?( ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% Z) j5 U/ |7 N4 [
MCASP_RX_MODE_DMA);
+ f6 n9 l, z3 e0 CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* N& d+ y5 \/ `* g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, h( M7 K$ ^% k7 ^9 W+ u8 l* HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 y* u' ?1 H5 `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ V6 N& o# X/ q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & T+ B, }. x% ?/ j' o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ S- y0 }- E7 U% H/ L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 O" ~# r s! y* k( z; J7 ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ I2 C; ?1 i S) K; U0 M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" @1 o" N$ |: X8 i0x00, 0xFF); /* configure the clock for transmitter */
9 {- ~& o: T: M2 z& x! _7 z+ {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 M5 q( J4 A7 T" j) ?0 v! O1 c4 HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: d( x% z7 F+ lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( q$ m5 {$ w" d% g6 {' A0x00, 0xFF);
0 _! q0 Z' u# G! i1 {& l
) D+ R; ~0 j9 m( X" J7 ?/* Enable synchronization of RX and TX sections */
0 P& \* A- P- {# {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" \+ d6 P7 S9 }8 S5 |1 L3 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# D4 f, i+ y' }1 g, [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* X; A2 e6 [& E3 V** Set the serializers, Currently only one serializer is set as4 G$ Q3 j2 ?3 n6 S; D) _
** transmitter and one serializer as receiver.
# A0 u9 b( [; Y2 R \7 c*/" ]$ }0 A7 ?! ~' F; r2 U9 r- }. i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: q) F+ }# E& K' UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 }: x7 L5 X6 D
** Configure the McASP pins # F! E0 R$ Y; t
** Input - Frame Sync, Clock and Serializer Rx# y6 A( ]* [3 l" A( `
** Output - Serializer Tx is connected to the input of the codec : s- Z# A6 w# \- c4 y
*/7 m! f) @4 z ]) J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 U ?3 p5 k _3 M/ `" X! z6 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) i; h3 h; ^/ ~+ jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ `( G2 O& O, r- G, Q5 c7 U+ [
| MCASP_PIN_ACLKX2 r8 r! P5 n( d* U
| MCASP_PIN_AHCLKX
) a, ]/ u. A4 B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& V0 K/ Z7 G) E! _& A2 }1 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( h6 |4 l% I G4 U0 r% M, `7 ?. F| MCASP_TX_CLKFAIL / F8 [! E/ ^5 k h5 p# P
| MCASP_TX_SYNCERROR
7 l2 f; d% i. q) \7 n9 q. t0 `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! U5 x" y1 E& e
| MCASP_RX_CLKFAIL
[5 d, s, F/ `; X( u7 N2 A| MCASP_RX_SYNCERROR 2 f+ i. {, O6 s6 Y
| MCASP_RX_OVERRUN);
; B; q' M% k# h f} static void I2SDataTxRxActivate(void)- a" R& s5 |$ Q0 h) k* X
{7 T( ^& e5 S: L& v
/* Start the clocks */
, H/ \; _' @8 }3 q7 ?. f: Q- H/ mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) m! h1 P- W! N8 T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, I6 j4 `! F( y T- w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& Q0 j2 h0 a$ |+ W1 h5 d7 ZEDMA3_TRIG_MODE_EVENT);; F( R2 _; Q! c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 @& v) z# D+ e5 Y5 y0 f# REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: F: R( ]6 ]" {" uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. {/ F2 a7 s$ i4 X9 t+ {8 z) @# @* |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& c3 s# {9 B5 r9 \9 ]5 @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 M/ c# |1 ^- Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 U6 Y* b8 `9 Y( }, k2 H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" b5 N9 B% i, A8 U}
/ Y1 f0 W; T$ ^! X# O" A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 z2 k. a2 `5 x: ~' H
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