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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' L1 M' y: V$ a: B2 m. W( Dinput mcasp_ahclkx,0 D% q# J' n6 K+ m: ?6 B
input mcasp_aclkx,2 b! Y' O$ P2 B3 q6 @
input axr0,3 j5 ~4 z9 t. W" a! Z [# h' \/ J( l
- r2 l7 D8 e) b5 r/ A' Koutput mcasp_afsr,& j0 i% ?4 r+ @0 a' w1 I
output mcasp_ahclkr,9 Y$ I: r; C/ K `
output mcasp_aclkr,
/ x2 Q3 E' m% E, Boutput axr1,+ }8 A! i$ E' o1 W
assign mcasp_afsr = mcasp_afsx;
. T2 l$ } [' T! d* c) d: cassign mcasp_aclkr = mcasp_aclkx;
6 Q5 ?3 j, t. w0 uassign mcasp_ahclkr = mcasp_ahclkx;
# a* u; X5 D& Y+ S$ U3 a n: T2 `assign axr1 = axr0; % Q% f/ y; r4 m# _; I* ?
/ w" f% O6 T. S2 k4 e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# v$ w# p; E0 ?* ], D; Bstatic void McASPI2SConfigure(void)
4 [. w) v. U! {$ z' t{
9 B; V5 h" h; l% X7 }1 oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ [7 `/ `; {2 Z( @; Z! }) oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( ?+ w8 S8 ~# {4 _. AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% j/ {7 X( [6 j) f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 P; \. c, o1 v3 Q+ OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( |/ Y! ]* G( {# R2 p. z3 MMCASP_RX_MODE_DMA);
1 ]5 Y2 g" l, C. e2 l+ a( vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. U- }, b! ^' l# {0 HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& |7 Z" n+ [' P% P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * h% H2 U' ~( V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, ^: B* Y, |* P# I/ P" gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 g/ C# n, z% U( l) |! w" n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ b. S8 r+ q" R$ V3 M; uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ f, H0 s7 O; M7 w3 c& Z8 Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ R/ f; u/ p" ?) q* o# N2 v* }7 B: iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 ~$ E( X: k( H* m6 g6 @0x00, 0xFF); /* configure the clock for transmitter */" X7 @* A: J' r" G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 r+ _; d6 o: Z, }: a- K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - Z' @+ I! c8 x! y, f6 l) Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) w! i7 R" r& Z( m4 ?2 T0x00, 0xFF);8 Y6 q- Z/ M% e5 q8 k9 ?( M
. s6 X% r9 U8 u o0 N/* Enable synchronization of RX and TX sections */
6 c& u! ?* M& K" z! _7 N* ?4 Y" fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 X5 y* @. h! L+ p6 H) B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 }. @& H2 v, o/ AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 _: K( R1 c, P l2 k** Set the serializers, Currently only one serializer is set as
8 [! A) t T5 J** transmitter and one serializer as receiver.6 z9 k0 ?; w V
*/
0 F( b( W7 @ j2 d5 u, V* b+ _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 d* e& l; P! B R; r) ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# N' R& S) P X4 m2 h, U0 d
** Configure the McASP pins
, `/ T9 o+ p' j' u# O+ y' ?- T- L** Input - Frame Sync, Clock and Serializer Rx
) K" p: v2 d3 S+ j0 n2 m** Output - Serializer Tx is connected to the input of the codec : o8 k# u, v8 }
*/
2 E8 q8 a0 g4 K3 @2 L- _4 T9 l. rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: h- W& ^! a+ I D4 P1 ~" c* l- R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! [% M- p- z& z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' X& h! D' G1 i1 ?1 E+ z" l| MCASP_PIN_ACLKX
) _' j, o* [. i| MCASP_PIN_AHCLKX( F; k! U# y# K, t6 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& _# S4 H! `2 Q% A! [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 q& ~; ?' ?1 T( l7 i8 L' p| MCASP_TX_CLKFAIL
8 \: r' i4 ?# l( d& @ |3 o| MCASP_TX_SYNCERROR
- m4 s& J: z, ~- w- |# D: W2 E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( Z! H! w2 c# l2 Z R2 M; Y| MCASP_RX_CLKFAIL
: f8 u9 {% r9 C| MCASP_RX_SYNCERROR $ ~. o- }, ?: x9 O, o
| MCASP_RX_OVERRUN);5 p2 }9 c0 s* ] B
} static void I2SDataTxRxActivate(void)
* F/ j0 R" ~* e5 Z; t{
/ M* D0 L8 P0 T9 V8 x; g9 L/* Start the clocks *// |6 ?' f6 K. _; `* X2 h8 E: m$ q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 m' { V, Y( H1 D: ]+ E4 R& {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 b( z' F& n0 e; p, C; g1 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) i( j$ N) Y& C6 Y7 f8 @
EDMA3_TRIG_MODE_EVENT);
( S* n# \( A. c& C) C j+ PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # G6 H: K/ v" G9 g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 y4 z( a/ o% |" F. e5 [. X2 b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: x$ f% E4 {( F" M5 DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& D4 z$ i. I [+ Z I' B4 Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ h: x1 x: o+ m& h. ^3 mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 v) X3 h- J) L& hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ U" g4 g* x# _5 _5 c}
1 i `' G7 \( g, Q8 ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ P/ U! ~; H* F/ f
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