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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ h0 K3 l" L; H4 N% r3 H' @. m' i3 binput mcasp_ahclkx,6 p3 ]: h; `. n1 \7 H! x1 n+ h+ ~; q$ }
input mcasp_aclkx,
6 |8 o5 y/ w& B0 jinput axr0,
/ f; ~% C9 F! U6 ?1 t8 p( v+ {) G/ E/ p7 \4 }6 i; t1 t! Q+ T
output mcasp_afsr,
/ O1 l& j2 {- Q- @. N" c: o ]output mcasp_ahclkr,
1 g5 z; i g1 [! Q' n" Aoutput mcasp_aclkr,5 w: {# b0 E) i% J- d4 _
output axr1,
1 C5 r2 j( n0 _& H4 A$ B4 n assign mcasp_afsr = mcasp_afsx;" ~: L. W, m" Q; ^( R* g7 e' l: S
assign mcasp_aclkr = mcasp_aclkx;& W& E$ v# }2 a, m- K& p0 N
assign mcasp_ahclkr = mcasp_ahclkx;
' y& r& _5 V( w$ a# N& u. |( s- Yassign axr1 = axr0; ! U$ x+ [* l; e/ k& y
; s' O% _' _+ k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : t1 R3 U+ Z$ s0 X9 q
static void McASPI2SConfigure(void)6 P" t/ f! [3 \# v4 n* V
{7 A9 p( r7 b; O- G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- ], g g9 U& n9 V1 _: wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ N$ R5 K: \% F EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 c1 w7 d4 d. d8 r4 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( K, b+ G* h/ A8 D; J7 J. B3 NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; F5 Q: \, M+ H( t6 A) }MCASP_RX_MODE_DMA);9 R* F$ K8 C6 N) k/ L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 z3 t" y" x) {% XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; i2 A! \# k1 _3 d" [/ q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" `6 L& ^0 K7 j% pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 C) }3 O% o+ X, E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, W" |# z; y* bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) t0 b# K2 n) @& X' B7 ~& u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 k, D m% _4 M, WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % H$ n' b5 u. V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- @4 |4 {* E; o. [$ n2 @0x00, 0xFF); /* configure the clock for transmitter */
" k" G: y1 N" EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) k& R, I. i, m/ C8 M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! X! r- w: E6 `% ^8 s V+ c% J) IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 h& g8 d) ?& D* E# F9 E6 G0x00, 0xFF);
2 F) b9 b$ D6 V. d, ~+ K: T2 q
6 g o# q7 s& l' Y; b( E) `+ K/* Enable synchronization of RX and TX sections */ 3 j0 v- Y& P" S3 Z& D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: ^( H6 ~5 M5 _5 K8 T% T7 n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( O: r* g7 L/ Z6 e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ l5 C: b7 }) G
** Set the serializers, Currently only one serializer is set as
8 v1 e* W$ V4 _% G I** transmitter and one serializer as receiver.+ s7 W+ Q5 {0 [4 h+ K# ?
*/5 _) t# c* V" B7 `% V2 g' t' M4 t5 c# A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) O" o- @: s, g" C9 a- k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 U: b$ V3 j& O** Configure the McASP pins 4 s: X/ U( G5 I7 N- L
** Input - Frame Sync, Clock and Serializer Rx+ Q; V% S1 @; B$ K( B
** Output - Serializer Tx is connected to the input of the codec
) R% F! n8 x5 }*/9 ^( e- m6 L. J, G* @0 e; h* X, w
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
_9 i( t# S5 C& e1 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' v R2 U& V' k$ cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' @4 b: |# K; _; c4 ~- w9 |/ e" k5 {
| MCASP_PIN_ACLKX1 G/ \6 i# u6 x- `
| MCASP_PIN_AHCLKX
5 M+ C+ a+ D% B* U G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; ~. [; Z8 t0 V: ]9 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: R" [" A2 Q2 s" E3 z" N6 ]| MCASP_TX_CLKFAIL
2 _( |$ |3 r7 A. O1 S0 S' F| MCASP_TX_SYNCERROR6 Z( S0 J) y3 \ H( s* H6 O; x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 V0 M/ D9 U$ M- S8 k. _| MCASP_RX_CLKFAIL
. q. _+ i. k6 F7 e* G3 F9 z| MCASP_RX_SYNCERROR
9 N$ c; O. `1 U| MCASP_RX_OVERRUN);
0 a* n3 |* J2 u5 q* k; j' W4 N, \} static void I2SDataTxRxActivate(void)& z1 e5 ~8 m- O( V. \
{
, k, k6 O8 ~0 v% G! O' y/* Start the clocks */
& O6 K' U+ j4 o: T- [: VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, V8 G1 V8 N* i' b5 |1 O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 ^2 C% o2 k1 | a) c; d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 C3 C" Y9 o$ r8 d8 AEDMA3_TRIG_MODE_EVENT);+ Q( z1 M% K: {' c1 \' W: z3 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! }* u* f$ }1 X, R2 n7 \2 k4 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 M1 F2 L. H. G7 SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ G9 v* N( j' ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" d& p* Y: F% _% Y! }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ v1 c% ?6 x- ^4 j4 F$ |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ ~& M: _0 `0 [6 |. Y! O" ~: cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 e3 V* ^; o2 F* [6 X) `: M# G% }}
1 L- A) X# b/ b% @; ] i) f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " \& `0 I6 @; j+ m6 l' N% k y
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