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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- o6 E% c% Z& k1 J6 A6 y$ @
input mcasp_ahclkx,
+ ]: a$ h2 B1 P" s7 I7 F) Uinput mcasp_aclkx,
( H# e: {) l% F& V# |8 A0 {( minput axr0,8 D& ]- B: A }, {4 x
) [! h5 D6 P: J! k5 j% O+ i Youtput mcasp_afsr,
% x! L& [, n: p# coutput mcasp_ahclkr,6 Z# N" ~$ o0 m1 W$ t$ k5 S
output mcasp_aclkr,: j3 o3 [& x6 v2 _3 W
output axr1,
8 V9 Q! D- A, W- W7 ` assign mcasp_afsr = mcasp_afsx;
* c# j' X+ d* w ]) K wassign mcasp_aclkr = mcasp_aclkx;4 [' _ F s6 P3 g& b) \
assign mcasp_ahclkr = mcasp_ahclkx;
8 b1 t1 }) l- C3 Passign axr1 = axr0; X! \& R7 n' z L& m
# S5 a; f8 Q% j6 _5 x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . l+ i5 R0 \# p, x: e3 V
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 c% V( v) |( B' Q: Z7 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 s9 X" q2 t0 C D' b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 w" {1 p' ? N( a8 l g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ Y; Z5 G7 }9 |1 f& A7 q6 F. ^6 f3 T, `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) }! {6 q9 i+ L& h( ?9 Q5 lMCASP_RX_MODE_DMA);6 G+ K0 A% a+ m H3 h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, z5 J5 T' o8 q! Y: r+ @3 J4 d- {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 Y6 D+ Z% M# PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) D. p* U) X' U2 N5 R0 LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' A H" I: M+ D# ]1 c' |& T$ ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! X# ~. Q1 G, z% ]$ e8 P8 c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 ^; m* c/ ^' O* x% tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 e1 m$ \& r" n2 S" H- q% t" S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. P9 F9 N- W( F# M! C4 ]! r" }$ RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 v* S z9 @: S; j0x00, 0xFF); /* configure the clock for transmitter */
# h% g% S) Q. }% B4 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 z: s1 ^( ~9 U9 Z' s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' l3 B5 C) |7 }3 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- b3 V6 C7 x0 I. V; C: B$ |; b
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ + e+ r; @9 q# _" }# J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( `1 W* J& S- l/ H1 S. O! z; D6 JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% t; ]/ b5 H6 q) XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. G0 W/ @3 n9 p* C2 l: T4 \7 V
** Set the serializers, Currently only one serializer is set as B+ ]7 V) O2 H! i
** transmitter and one serializer as receiver.& g; X& [6 e1 }! K. Z1 v9 r, V
*/* ]9 I/ R1 @& C" v! u9 b+ `4 @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. e! _% g% P5 I |/ F# j& t t1 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# u! h6 T8 U! l& Z** Configure the McASP pins
. Y( s9 a- v. ~+ P: b** Input - Frame Sync, Clock and Serializer Rx
9 d( I7 {3 F" |* P' T** Output - Serializer Tx is connected to the input of the codec
8 W, [& j% b K7 a1 V4 i. ?# Q y4 H*/
1 |7 ?& [" Q' M+ J& V( d vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 g+ k8 g; z5 H" ], s* N$ U# M) {5 d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 ^* H* F0 a3 A( \) G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 @/ X2 X J9 \' e. C" ~| MCASP_PIN_ACLKX
# P, u9 w5 m/ _" b# T| MCASP_PIN_AHCLKX6 S2 E* p) U- _. l1 J! z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; Z. f- X4 G! \ b! `3 M) B0 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 R6 t, H* }8 B3 N7 o/ Y! @1 f| MCASP_TX_CLKFAIL
9 t7 ?- j3 v; C7 f: y| MCASP_TX_SYNCERROR
6 @ t8 l! [# Q t; S+ [; P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; z# W" Q7 f3 E: a2 x/ i
| MCASP_RX_CLKFAIL( g1 j9 i/ Q$ `1 \; H
| MCASP_RX_SYNCERROR ; b/ ^0 S; p/ h, @. _5 z
| MCASP_RX_OVERRUN);. f. |7 K5 X, e# W
} static void I2SDataTxRxActivate(void)
, F7 V7 J, w7 u& M( ?{
3 @* I9 m& n- Z- Y! x5 ?4 H/* Start the clocks */
, m# }% f( o( X* T& w" h6 OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) M1 z) s& _' I8 T cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 |: Q0 c" G0 [# P& M) KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ y- c& n2 [% w+ ^ J9 d: v
EDMA3_TRIG_MODE_EVENT);7 G: `. U7 V4 K( C3 i3 }* Z1 b6 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! J4 F1 m/ T# U7 d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 ?' q+ ~6 K7 b# Z2 y: d& _) U4 a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( \8 ^- x; u9 {: C$ w5 q+ e2 x, u* d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 N( r, E; U7 x) `" l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) N3 m* K8 B* R, g* Q( }: ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 x: G1 ]. L1 I% L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) r* Z2 y5 {* c) E} 9 h1 E8 M q' T+ G" d- r& D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + ^5 r1 w; V) M% Z2 j/ ]/ [5 x5 g3 \+ g/ N
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