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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& Q% n8 M1 B$ W9 y0 y& k* S
input mcasp_ahclkx,5 w* F1 }: P$ l/ N% h9 T
input mcasp_aclkx,
; u- ~- k; ?3 M9 a. ]input axr0,# j" O/ u( }; ^5 g
( M) t$ s2 \" G! L/ s
output mcasp_afsr,
) Q7 F' ^% h, W9 X; O) Y; o9 X+ qoutput mcasp_ahclkr,
/ A# B% i! |' k: l6 {output mcasp_aclkr,
4 ^# S# o/ Z' G+ q" o" l- Poutput axr1,% }7 u* W0 y. [$ m+ K$ ~5 t
assign mcasp_afsr = mcasp_afsx;
! _; G3 V) J" ?3 y7 aassign mcasp_aclkr = mcasp_aclkx;6 S- I7 u% S A2 b" A
assign mcasp_ahclkr = mcasp_ahclkx;) G; M) \9 h" u/ F: C; g' M y
assign axr1 = axr0; ( s7 o* d/ q1 J( l; Z* r( n7 a
; ^7 x6 X9 x3 I6 C/ P% d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( q" |# l4 h0 i9 ^1 q& v1 v
static void McASPI2SConfigure(void)
; [3 o! q+ `4 d- O{' ]9 `3 H. D8 O' y% B! p, S; W9 C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& a5 l0 z) x' J4 v; {) d8 g* e! ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 [* W- U/ i( N- q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, c( {# D* C5 L- F, e3 MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
e m2 y/ G0 K* D GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! q% O n; z& ?' |' z/ g6 RMCASP_RX_MODE_DMA);2 h# H; v( y7 s# l7 J9 U) k. a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 j/ w/ ]( _! }/ z3 M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 N, S. |+ a6 w3 u; @9 t) N& GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 ^8 j* }' t3 W1 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 u) L, h, V# LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 k& x8 g/ B6 O+ ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 Z5 m+ T. j. @3 \* M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 w9 _! X" G4 p+ x& ? Z! |: f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 D& ?0 q# N$ c7 A: e. ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- d! Z& ~6 G: ~
0x00, 0xFF); /* configure the clock for transmitter */
- u9 V4 o0 G7 l; sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# A: h2 t2 J9 [$ a. S+ }! |! hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 c K0 d) i3 w, B5 B1 y- Z& X3 Q' u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 o7 ^5 |# n/ e9 N3 z$ w
0x00, 0xFF);
$ t2 ?7 y" _+ p1 R5 k3 c3 F1 |! W0 V+ ?8 X1 X; E! ~4 p3 I# e
/* Enable synchronization of RX and TX sections */ - W; z: n, s T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" I b s" I7 z1 m+ K$ w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ t& ]' _2 a+ |5 j+ j: S/ g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; P+ }0 v0 }+ @5 C, K; W3 [: w** Set the serializers, Currently only one serializer is set as- \5 R7 e4 O; l8 j* Z9 O* B3 w9 P
** transmitter and one serializer as receiver.
7 d+ Z, M6 Q5 f- s$ j+ }! Y/ E+ M*/. o9 l# B3 T) {( g. |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 z# |+ A2 n( k- V8 X" c3 H5 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. v8 e/ C# |( E2 h8 C8 k** Configure the McASP pins
$ D j& X1 p @ S! E S- S4 L** Input - Frame Sync, Clock and Serializer Rx
. M+ G. j! F8 ^** Output - Serializer Tx is connected to the input of the codec
% f$ {& ~! T: o& ~' k5 B*/
6 e8 T# L( O2 Z/ _8 {. s$ O# ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 L* h5 p8 T# ]$ T1 XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 ~3 }2 B0 m& }8 w6 K C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# x* ]& g7 c# z* ?" E| MCASP_PIN_ACLKX
0 q2 ?, }7 ~$ m; Q8 r$ _| MCASP_PIN_AHCLKX' s% S& f4 e1 c/ a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 W, j. S" o) X& h- q2 l: s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . L$ f! X0 l$ y7 T. A) f) D
| MCASP_TX_CLKFAIL
: E% z" ^$ }- y) a. o# L| MCASP_TX_SYNCERROR& c# a. z7 ?, j/ f/ j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 }- K- T& M2 z! E" F: B
| MCASP_RX_CLKFAIL8 v4 o% d- ~5 b
| MCASP_RX_SYNCERROR 9 X8 h. M( U3 @1 T4 z; Q9 w
| MCASP_RX_OVERRUN);
/ K( M' K! R" g9 b( J} static void I2SDataTxRxActivate(void)7 t4 z2 ~' ~" L- a2 O4 N* n
{2 S, R$ G: a: }+ {* ^% d3 k
/* Start the clocks */
. T* W5 D9 W, ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' A2 n# V* z0 i8 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 R# |. x ~" ^* @% F" uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; T& \2 z3 z6 B2 B9 C: nEDMA3_TRIG_MODE_EVENT);
# I4 b- k4 {8 Q1 p; `" F; u9 |' ?8 _9 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- q; C8 p3 t- s' Z% V8 G! `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// r) T0 C& e3 J* ]! E7 f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# ?0 Q# o. }% w k1 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 v* H u% {' P0 Y' U; Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 t/ k. y* j: |- tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 H/ k, i5 q! P- ]: \3 r' e% m# s eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* Y- q/ u5 L% k+ L- H6 s' j1 L( b! k
} # t9 }. z: i; L* T- N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! t9 R7 M. ?0 ~/ e4 p: o
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