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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 q! c1 H6 Y- \5 N$ zinput mcasp_ahclkx,2 d; F2 N7 S+ ]
input mcasp_aclkx,( K) M4 i. s8 C6 L( d) {
input axr0,5 Q9 o5 \; w, p) C- s/ [0 k) `
# |- ]5 G1 `6 I9 }) ]
output mcasp_afsr,
, x: K1 w& g9 E2 toutput mcasp_ahclkr,
/ k% }7 ?7 a. e$ @. n: B. houtput mcasp_aclkr,- T: I$ ]0 ~* B; ~* y4 Y
output axr1,
5 h0 A% j7 B; @3 }# c3 k) | assign mcasp_afsr = mcasp_afsx;9 E/ L Q Q7 l# o( Z( L) n
assign mcasp_aclkr = mcasp_aclkx;
" ?' k8 W$ ?2 rassign mcasp_ahclkr = mcasp_ahclkx;6 d& x2 B4 L/ J
assign axr1 = axr0;
7 ]4 V9 ?% r2 B& ^8 y4 X
' T& k7 S3 P8 @# j5 i$ X! [+ v8 l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; L3 g7 J3 w! M1 H% H+ O6 K/ E
static void McASPI2SConfigure(void)
0 \ [* H4 B; ^6 f{
% j7 [' d p; g5 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* I, {/ E$ b+ y$ V; z: R g4 F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( b9 ]5 q& _' b" }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 R$ k' X3 |, g& A8 V4 O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 r& y7 T) c: n. L% g- RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," P: g, g) A) S! d
MCASP_RX_MODE_DMA);# [; Y, j4 i9 T( Q6 e2 [; X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* I4 y, ^+ B; A% H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* x7 z( b- m: D/ ?6 N7 J+ AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; F! L6 C0 f$ r2 S, S! y4 Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& e. W1 a' q d& wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ g3 A0 H4 w$ c% g6 T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. \) M* b7 {% n0 u. {, ]9 b' [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& I* w, ] [/ `- x' U; j0 V3 C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ W0 N; Z/ D7 i% F) Y: j% F6 fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( o' F3 r0 t; l }, F0x00, 0xFF); /* configure the clock for transmitter *// L$ @0 m- x# n0 r; T. v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& Z) Q- @" S P$ n- f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 u+ m; g" J; r; G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 t$ s1 Q* q4 t7 i4 Q2 d; Y
0x00, 0xFF);
E. F, I( {0 q- a" i/ D# h' u+ e" c' @
/* Enable synchronization of RX and TX sections */ {# ?9 i- t3 C% `3 I8 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: X" `: ?. A4 d7 \9 ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ O5 \5 y+ a* s5 }$ Z; f' \( qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 D. K3 b, r7 q9 A- O, H** Set the serializers, Currently only one serializer is set as
D! ^! F1 |3 M6 a7 i** transmitter and one serializer as receiver.
( d8 e# T, S1 I/ ]*/
0 C$ E' \% U) N! J$ P' m+ [+ t& iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 x( J, J: k4 s9 N4 y6 R* h4 W* NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ V4 p9 [- q0 Z- f0 ^0 V
** Configure the McASP pins
6 f% z, I+ q$ `4 u( }. [/ R. X2 N** Input - Frame Sync, Clock and Serializer Rx; q( Q4 K" G0 K1 N
** Output - Serializer Tx is connected to the input of the codec 2 O9 |. G$ t6 |: F
*/% Z4 `8 C! J% a" {& A: G$ Q9 ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& S4 |: b+ v7 L+ ?$ q6 `) W' {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ Z5 M' h( W: p rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 ?$ j- Y6 N3 a; w% L: G$ l| MCASP_PIN_ACLKX! x( @' g! B o# `
| MCASP_PIN_AHCLKX
2 s1 M' `$ g' D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: `% O9 t s+ wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 ], c4 K/ c4 Z0 g% U4 O
| MCASP_TX_CLKFAIL
: `9 J `8 B4 Q9 J% `| MCASP_TX_SYNCERROR2 ^! c$ e! S/ [4 j. F1 e( h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 T$ |# {, D" j# l1 m
| MCASP_RX_CLKFAIL
% T. Y/ l/ T, U3 y! @ K$ l% E| MCASP_RX_SYNCERROR
( l0 v7 b. _' B# [5 x- f| MCASP_RX_OVERRUN);
! L: ]" m8 @' N. w2 o} static void I2SDataTxRxActivate(void)8 f/ n m1 d$ k. j% N b
{
! B$ ?/ n4 X0 j0 m @) O( B/* Start the clocks */6 _" S; \7 I4 E7 O# I4 K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 d, K* Y2 a9 l" jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- _& N) D/ z4 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 `& h% ?9 I! F d( x; K! Q
EDMA3_TRIG_MODE_EVENT);
& e% O! f2 q" r9 K; |6 G3 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 A2 N4 }4 t0 B% lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! T! o/ ^/ j8 Q% b1 c' v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% n! ^" E; L9 }6 U, m# D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ p2 ?: d6 K' _7 Z! V4 M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( f) h- G) i/ t- [; zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! s# d2 E9 Y. ~7 o, `0 ?( h' j6 AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 b/ H2 E+ A; g! @9 H
}
& s& Y8 s. T- C( k* |$ a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " M# ?! s9 X6 g U0 ^
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