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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% u' b% a4 D* j2 L$ Y# e) }0 D
input mcasp_ahclkx,
4 Q) e; s" U) X/ t$ a6 iinput mcasp_aclkx,- p4 \3 }; A2 k# Z! C- v
input axr0,
6 K* B. K* o# H$ Q1 M
3 [' ?/ Z1 l \8 U7 Eoutput mcasp_afsr,# c. h) {' k+ ~
output mcasp_ahclkr,
. z, ? w8 @, K- B- f/ x% loutput mcasp_aclkr,
3 b F( A: \; c) doutput axr1,
8 M$ A: v$ Q& j) [7 c/ ~ assign mcasp_afsr = mcasp_afsx;) T( e8 ?/ A; d9 q$ m
assign mcasp_aclkr = mcasp_aclkx;( C* a V- `* d6 G9 E
assign mcasp_ahclkr = mcasp_ahclkx;3 t, R, p! _! r2 z) d1 Z. m
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , E7 F2 n; P4 f: S0 i3 R
static void McASPI2SConfigure(void)
* R! E: e/ @3 p2 l" A{- u) I9 c: w/ Y) V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 T( v& H" D0 H$ ]" L$ E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 S' b: W8 N# f2 D) w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 d" q) G |; @- g& `0 k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; T2 w( t# Z/ l- w5 y3 ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, {( C0 w# ?! m7 n2 ]3 \
MCASP_RX_MODE_DMA);
8 e+ o: @2 i0 E. w6 l* [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ R- @: f' X0 q4 p0 VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) {/ e6 z! r. t( f/ xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : `, x" W& k% G6 n1 c! t v& A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) e3 H& [8 d0 Y3 ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . v" Y5 b2 G }& j# C) n) W. @- K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* P8 y+ O5 S3 x# q) }6 l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. T+ K7 f$ v9 E4 \2 w& B# }/ tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ T% J! A. ?# q/ M9 ?) o. U2 J% |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; G1 k P+ E" m: C* t0x00, 0xFF); /* configure the clock for transmitter *// g: z3 } e; C1 i" t' |* j9 j- D$ b8 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 E& _3 d) K p% K; b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 Q/ _- N5 f& l' g8 z9 A+ V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 [6 B8 W, X( h
0x00, 0xFF);, ~: _7 M4 q0 ?0 S
. P+ ]. K0 N! s
/* Enable synchronization of RX and TX sections */ $ R% u3 n+ x: Z6 B( l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% a2 C% Z: H! ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) D3 ]4 J( W" J h$ S! jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* c/ w6 W. `* v' h* l( I; T& D** Set the serializers, Currently only one serializer is set as
. j& _2 N- b5 b: ]7 X5 `9 v** transmitter and one serializer as receiver.2 }: b7 j* [, e, k; }' e
*/ ^" j+ x* h- v3 m3 R p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# F5 H# a7 K( o2 c4 L3 p1 R. |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 V# c8 R. P: |( m) g9 G& G
** Configure the McASP pins 2 ^' K/ ]# H& ^8 Q/ z
** Input - Frame Sync, Clock and Serializer Rx
! i; R( |3 D, ?8 p& R+ ^: g8 }** Output - Serializer Tx is connected to the input of the codec / V& i* ^" \0 B9 f# x; h3 [ F$ R
*/( \7 Y/ Z, q6 L1 Z& c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, F9 Q( l7 w T0 wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& d- r6 V: [) r/ M$ c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 y. t' a, P1 ~3 u. Y/ |
| MCASP_PIN_ACLKX4 `0 a$ D6 f4 E5 R, j# _$ N( Y
| MCASP_PIN_AHCLKX- }& R9 L! \- F. j y4 i" q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 p/ W8 D& x* w8 D& x2 g. HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # V* O' k0 ^" p
| MCASP_TX_CLKFAIL
, M$ W0 R% x( ]; B; A3 ]% v| MCASP_TX_SYNCERROR' |8 W! G2 q2 `1 R# Z6 j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 j$ K! l5 O) `| MCASP_RX_CLKFAIL
& T0 P% W7 ?- v" |6 w ]| MCASP_RX_SYNCERROR & j/ L" B! z7 o$ W/ Z
| MCASP_RX_OVERRUN);
% [) \# U% X% c8 }6 \2 \} static void I2SDataTxRxActivate(void)
8 m+ U& t) B8 y) C" I+ i- u0 F{( U \! m( q. g1 T0 }8 T
/* Start the clocks */% P3 w, n. g+ [+ X0 ?9 T2 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ l% p% `% ^* H, [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 s. i; U, _: h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 K, l& b% U& F% S0 U* I6 b
EDMA3_TRIG_MODE_EVENT);
7 Z% h5 I( K0 a2 T1 `9 i+ B" yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ L; w" Q0 ^+ D9 \" J0 k, ]6 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, \8 B. Y2 k2 B* y9 D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, W1 ]0 q) F6 F& [$ W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 X/ k9 J3 m: F' l( O. z* E' k: swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ b9 a$ t$ B$ B% r6 a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" j' h& z0 t9 m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. C" S+ K/ @* m' v+ o& r}
( a- M+ ]! h0 r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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