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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ L3 c) L; Y2 V* einput mcasp_ahclkx,; n" O4 p( r, U! W: M9 g
input mcasp_aclkx,) j: J/ C" b7 F1 W% a3 l, a4 V
input axr0,) c) R" K) y' X- W% G6 ]
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output mcasp_afsr,
% Y4 E1 g8 f! c1 O$ |output mcasp_ahclkr,
4 v. U- r, E0 ^* m3 _4 e6 W, Loutput mcasp_aclkr,) x0 J+ S3 g( b8 z
output axr1,/ B2 q+ E. x+ `" S: }7 I
assign mcasp_afsr = mcasp_afsx;$ c' f6 ] O! ?
assign mcasp_aclkr = mcasp_aclkx;
8 j( s9 `% _! {4 e. |assign mcasp_ahclkr = mcasp_ahclkx; W7 _& G+ C* d, E4 u8 I: s
assign axr1 = axr0;
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/ x' U% y ~ Z- ^; I9 P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! c6 U' ?6 `+ [+ ~static void McASPI2SConfigure(void)9 h1 Y2 w+ x8 C, P0 P; U x
{
2 |6 d/ x& p1 R( _5 \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 w1 C+ l K/ q8 P8 V- l% WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, j. I( r, x; H* D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; C8 P+ K3 F* _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, T+ k; W! k" Z3 y2 N: M+ e( {
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 Q" O9 O. E& A( }- P
MCASP_RX_MODE_DMA);( v: x! M# b1 R1 {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 @! u$ }9 p; x' v9 u* X0 T, T$ c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 M8 y/ H0 q( N% u9 f" aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 n0 `( T# P ^0 m. W1 P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ w& G7 d1 k) H8 `7 E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( m, A7 g& u5 U+ s% B, G) IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! n4 ]* I% ?3 ?" d# NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# j. t/ [) P4 f! r8 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 @$ [9 g- q1 N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 x% G' T: A' x2 |7 ~9 }
0x00, 0xFF); /* configure the clock for transmitter */% s. Z1 a5 ?8 a8 L7 A8 R8 b7 Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ w; O, F+ L% U; e3 L) t! aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # o+ O+ f+ Y* T; p+ `: s, v3 _& N( C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. d9 E& n8 u7 m3 R7 L& z: [/ s
0x00, 0xFF);
7 I( e7 o+ H& |3 i5 y9 K# Z) L' T, D* E2 }
/* Enable synchronization of RX and TX sections */ ! F7 s) e2 y; T% _* g0 ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. a. u- v9 H+ ^$ T7 |- VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 F1 V6 N# _& L' t0 X9 G& x$ O# U! [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. S7 `/ Z& P1 u: m; }
** Set the serializers, Currently only one serializer is set as
9 U# X, Z/ Y5 U# [; d9 `$ P** transmitter and one serializer as receiver.
) [, g8 g3 X+ p- v K4 q: w, M h*/1 L2 |2 p) p! a- t8 q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ }1 ~5 f# r6 Z: J$ mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! V9 v- A% }7 s" b( K
** Configure the McASP pins ' [% v! A7 Y$ N8 [4 b( ~
** Input - Frame Sync, Clock and Serializer Rx$ v- h0 ?. S% d/ I1 } D! X
** Output - Serializer Tx is connected to the input of the codec
' c% W# g$ q( B+ ]5 o& V- o; ?*/; `( U# I/ u4 p$ j( e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) ~) n- ]/ o/ d1 VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; }& s% Q1 N/ R$ }( @ W3 T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX M( Z6 }3 A; g2 w+ a
| MCASP_PIN_ACLKX
- ]" h# o; P) e9 N7 C) a) _/ b| MCASP_PIN_AHCLKX0 A' T' B8 z4 M* H7 q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: ~ B+ Q6 ~; H5 L R7 [- oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * L# Y5 U4 ?. {
| MCASP_TX_CLKFAIL
, m% l: b1 c" w, F6 [/ C2 C7 b| MCASP_TX_SYNCERROR! N' y( R) n9 I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 I j3 }" u; e- z+ j( }* ~# Z
| MCASP_RX_CLKFAIL
( k5 B: P5 Z3 U| MCASP_RX_SYNCERROR $ T+ r9 T2 v' s4 a, }3 T
| MCASP_RX_OVERRUN);
' e' b% v$ z$ E: ~} static void I2SDataTxRxActivate(void)
* o4 |$ T4 E+ O7 L0 o: J# D{
4 e1 H2 z' Z# e& O* s/* Start the clocks */* k; P+ @6 o2 A2 f$ u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 i& k8 y9 F+ h6 a N# Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& N+ @( t* |1 Y9 ^7 ^# f+ XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ e0 {% N$ X" ]& B4 WEDMA3_TRIG_MODE_EVENT);0 J+ s& |: m; c2 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 {- X1 X7 h' _/ N/ aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 I" M+ R4 S" {1 c) x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* d) P) J: t n, g( `; rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 S3 `" t* Z1 Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( S6 g/ q0 o" y2 |' a( z) G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( T) l7 g! v: ?0 g$ Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: X7 R& u! \0 s1 W s}
' R/ O. s% m+ f' _5 U, _/ G9 k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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