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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 N( M' z+ ]! q. hinput mcasp_ahclkx,
`3 P0 ]5 T# Z- r% zinput mcasp_aclkx,$ Z- P$ k3 s7 P; G" t6 z) c
input axr0,
* {% Q) Z. o1 S! W3 Z9 R% Y4 W ]5 m B6 M/ P$ v2 g
output mcasp_afsr,
, D6 `7 ]0 E6 T* f" boutput mcasp_ahclkr,; _6 c8 c* U* a* H
output mcasp_aclkr,) v7 Q) M6 p3 W: t2 v' x
output axr1,
* d2 O# T9 p8 J5 F assign mcasp_afsr = mcasp_afsx;
$ g% i, L7 l& |' Z& Passign mcasp_aclkr = mcasp_aclkx;
( B) ]! }. B% F2 x Xassign mcasp_ahclkr = mcasp_ahclkx;/ l! g7 c2 c. A, `4 c
assign axr1 = axr0; : G1 v9 U" K' m: d
8 T) B3 z/ w, W5 Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * X3 ]& `+ X$ Q8 O& a b
static void McASPI2SConfigure(void)' Z$ `, k: f% P( w" C5 t( g" P
{ W- L* Z' S5 O0 A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& }1 K v8 N& ?' f+ YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- O+ O0 V: L- p* P/ O5 UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" z& b* t7 o Y9 A( j( A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" J$ s* s6 n$ J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# s. j( ~5 m( n7 {! j$ pMCASP_RX_MODE_DMA);
5 x& d0 k+ \" W$ [, ^2 bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, [0 H& Q% R" [- zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; ~. J1 }9 o' l4 `5 r% S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 |8 `# F/ X) D* u N, EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" P" k" p4 q7 k& b, K8 H( Q2 \/ h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; t$ Q4 r4 w3 K/ U6 \' l. ]( MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( I' e& O1 F! A2 }& ~" x6 y1 U* z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) |1 _% V' Q9 LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 H( t" y1 u0 ~! L- v+ c4 o$ g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# J5 n7 ] O, q9 n# ]% o# w r8 G
0x00, 0xFF); /* configure the clock for transmitter */
- X2 k. o1 C; o" x! u# j! A m! R1 V( dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 {2 W: h+ A4 F" H* N& D3 \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# D7 `' B* ~8 z) d5 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
[2 N2 ]0 z" M6 x( d2 c7 n0x00, 0xFF);
3 i7 U1 E, R0 q# W6 L% _, n/ z9 ~1 R
/* Enable synchronization of RX and TX sections */ : ~: U4 w: x/ w D2 x( A4 D/ a C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 @* Y' n% K% v% @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* `* X5 @7 { H% o% TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( _/ O3 N. ]! c+ Q** Set the serializers, Currently only one serializer is set as
( a& F r1 S; U3 n) g: S+ I** transmitter and one serializer as receiver.; k; o$ A0 K( c- l& x5 S
*/
& w# Y% `# P( eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 M, t. V- X5 s2 n, YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* ~: @7 t' u9 \/ N, S9 ^- d
** Configure the McASP pins
* ]( q; I% J. O0 ^; O** Input - Frame Sync, Clock and Serializer Rx
: n' P3 ^* t) A7 Y p) Z7 [$ E** Output - Serializer Tx is connected to the input of the codec ; R* N( d9 H! R6 x( v' {
*/
% r# G; O5 L- i" }+ \" MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) w. e9 v( c! @4 t# F% \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' e4 _7 b, c7 J+ |& P1 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) W y% X; k- q: N
| MCASP_PIN_ACLKX
. A' u7 ^' Y" t| MCASP_PIN_AHCLKX
! D, \. L4 B8 V5 O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ l: h5 @6 H6 w2 A1 m: y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # }. g2 H" S6 H" m8 B( K
| MCASP_TX_CLKFAIL
! ~' F* ^9 W" K ?, c: K4 o& J' U| MCASP_TX_SYNCERROR w" V. }: g3 W; }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 O) b% C5 S* u
| MCASP_RX_CLKFAIL) r- g# `4 y* m8 W0 H
| MCASP_RX_SYNCERROR $ M8 @. S' [& F: q+ h
| MCASP_RX_OVERRUN);
2 D E4 l& y" y} static void I2SDataTxRxActivate(void)+ n( t- J8 V6 @$ A [; W
{* [6 ^% U( O7 J0 L7 q
/* Start the clocks */
& C0 {+ o9 u9 t$ W; xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- M' c! E) a8 L8 j( g8 QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 v1 f3 Z% W, e; bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 G: A" b% p% Y b' t+ ]9 {' P. a: \+ SEDMA3_TRIG_MODE_EVENT);
& {! }# i- [0 [* C( f+ ], uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& t" K% C" E' J' F U8 UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ [) [5 e: P" G `( h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 m( h; ?7 {, W8 c( `- l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 ]( Q' y& G7 S4 ~' t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 A5 E1 J1 Z, y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 I0 ^; Q1 ~. Q3 J3 o+ k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ f; \9 [9 J( ]* z# Z. p1 P- a
} ' y$ g d. M- l4 z1 o# G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , w4 H( O$ p4 P! k4 ], M
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