MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
; y9 E4 L+ W/ p1 {' F" i1 l( b6 ]input mcasp_aclkx,
  j# j: }5 E* o9 A2 w, Tinput axr0,

* e" b; y5 h4 g5 Goutput mcasp_afsr,
! t* c6 f, r' |* X( L& qoutput mcasp_ahclkr,
output mcasp_aclkr,
8 n2 N8 M$ p" ]4 A* }output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

2 f* b1 T& M. }0 G" m, `7 }
8 e8 D5 Q% P2 t& ]$ x+ G3 F3 r. ~/ g

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

( t* l, i0 O7 b

static void McASPI2SConfigure(void)
4 B9 }7 h) Q* Q5 h# B( M4 |% {. G: E{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
3 M, K, n6 Q+ uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) Z( d9 H1 u0 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
# V+ i; t& g8 z/ Q" OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
  G' I) q7 H7 E% w. xMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
0 B. H1 u4 B' I$ g0 C% nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" e& F% F3 h2 QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ {" [. C& U% Q" w% M/ X0x00, 0xFF);

/* configure the clock for transmitter */
" B& \* ^0 W) Z- _. UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 B' @8 _. _9 dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

) ^0 B. j) q, d, ^! [9 l/* Enable synchronization of RX and TX sections */
3 g( k5 G6 [; ]) l' T1 YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
4 Z- }& d( v" b' Y2 r*/
( X& c2 f0 N  a$ C- ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, W. g9 D& _# E) UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
/ }1 [" b- Y# M9 H& H6 V: E** Output - Serializer Tx is connected to the input of the codec
6 d' d3 ?% j# S8 _0 F. j*/
5 b4 d, f) T1 EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 z$ N% |$ h" V" l* ^0 u| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
2 t" r3 `0 N/ o5 f; a| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 [+ Y: ^* L; k; y2 h1 c/ _| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
* ^% \: W$ J, E. ?& Q| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, Y9 Y# |6 E1 {4 o- s% X| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
; q" A' `8 T3 d  ~! n4 z' W| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
1 u3 b/ `5 L) e3 |$ I# k{
  {+ X, k/ e, V, ]& d8 C9 ^/* Start the clocks */
* ~7 \+ d. X! @# pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' O( R$ w) e+ @5 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
- ^* f4 N4 y1 r( x8 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.