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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% a& t. W! v8 k) C$ |+ O$ x0 C; T- |input mcasp_ahclkx,& N* s# j# Q+ l( V- q# S$ Z- W+ ]
input mcasp_aclkx,
% d# V& V- k$ F, f0 _. o; Zinput axr0,5 s7 b1 Y( N1 P% D
* p; H2 r- B; r3 J) v$ T' g" ?
output mcasp_afsr,
. Z) Z1 R, v( t# h9 s0 k4 Qoutput mcasp_ahclkr,
' E7 L- T0 v) _output mcasp_aclkr,
$ h5 l" V/ y- P7 T, \output axr1,+ J5 P: h0 S9 K$ J7 D0 X: z: T
assign mcasp_afsr = mcasp_afsx;
! \8 E: ?6 Y' y/ k6 t1 h$ N. uassign mcasp_aclkr = mcasp_aclkx;
3 b9 w% k* A; V) f$ ]1 c9 Q: j6 wassign mcasp_ahclkr = mcasp_ahclkx;
; x6 `* C/ U& massign axr1 = axr0; % C7 m3 E5 H; B! @6 t, H u, B
' `& [8 [2 C8 g' ~1 y) V L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* o% n. m( {$ t3 T- Jstatic void McASPI2SConfigure(void)
4 {. Z5 B2 ?0 ]4 D7 f( {/ {; w4 M+ Q{
6 \0 F$ ^7 e! T9 D7 XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 K$ K& z5 S5 E c& H- H/ Z3 C; x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( p6 e! @8 r: b. rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# ]. U& C1 C. U% {0 UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* @" L: r. V1 @6 c l/ ~; `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 e+ K) a2 O$ ~" Q0 R$ m
MCASP_RX_MODE_DMA);' \1 `% ^0 o9 j1 E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 u. j( @4 v$ A6 o& ?- j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# _, Y1 t+ w( ~0 E' B4 rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 h }9 Y2 g0 \) j3 [- W& O1 n! A8 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" ^' ]# c4 z) i/ {/ R* o) oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: o7 ?; H, G0 b: `. y2 G" tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 b5 T n3 y2 D/ z% S7 ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- K! s, ?# P1 \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# y( V) A5 w; r. QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! f7 _% P0 h0 j" r& b0x00, 0xFF); /* configure the clock for transmitter */
+ E, Y9 b) {) xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 [/ Z1 ]# o$ |9 ?" r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 N& z5 O- q7 R& X! yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# |: F {, ]. c' z& H# \
0x00, 0xFF);4 ?/ N; D& y7 L! T5 x
% K: a& |8 W- g7 J/* Enable synchronization of RX and TX sections */ + ?1 R; ^( O: L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" _' J. _! l, b9 qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% s* J9 f& v3 v5 n# ]6 K+ A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 F$ t+ k5 c2 S3 T( R
** Set the serializers, Currently only one serializer is set as
3 Q9 q- H# [+ o** transmitter and one serializer as receiver.# _- m# }% K' z7 K
*/- t% W" v. g5 G% O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: K" P& K; p. @, x& fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; E$ b; e& B: a+ ~! H" Q
** Configure the McASP pins 8 J4 W% Q$ P: F
** Input - Frame Sync, Clock and Serializer Rx1 s5 o! E/ c& D) O+ q
** Output - Serializer Tx is connected to the input of the codec
0 u0 X/ q: ^- @; _; j*/
; h/ B) F ?7 Q4 F4 v# sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! M) y1 ^' l3 }$ ~& N0 KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# W4 s8 ~/ \3 ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 C! }9 i" v5 g4 L& T2 a
| MCASP_PIN_ACLKX; P" H. S* j6 p {, H& ~4 J
| MCASP_PIN_AHCLKX
% l# P, N4 h- ~. x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ e2 E+ Q) {6 J3 X! hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& q. l6 J" T5 m+ x3 {| MCASP_TX_CLKFAIL 6 g8 A% u! I2 K, m8 l. p
| MCASP_TX_SYNCERROR9 ^) P, ^' Z. x1 N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; d/ r6 m) e8 P1 X
| MCASP_RX_CLKFAIL! q/ p) A# C L6 [; s/ A) g
| MCASP_RX_SYNCERROR 4 e9 g9 a% r) r6 w4 g; t
| MCASP_RX_OVERRUN);3 E# _" y O: u% O7 G% @' ]) x
} static void I2SDataTxRxActivate(void)9 j# ?% z y$ s$ l7 s1 }+ L
{
& f5 e* A& Q6 D, \! k% h/* Start the clocks */* I, C9 b9 U7 z' n" b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# R8 Q" `1 O# E- N( T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ J1 U1 J1 p% M% s+ h$ ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 c0 i! g5 ^& v$ o1 m& h* l' h$ x
EDMA3_TRIG_MODE_EVENT);
8 Z9 q4 v! U6 y z/ _ L* B, PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) @4 G. G1 J5 I2 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 Y) g2 I7 t1 cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 F- c9 r1 g% ]. X" H& UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- |7 v( U F7 U! }( e! ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: `& r$ K6 M' w* O5 p" m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! [* n' m$ e' O; B0 HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, L( ~( g3 Y; Q' l! v
} & g( `: L) c0 Z! _+ y- f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . {3 l/ m! L7 G+ h* G
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