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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) \' b. Y F3 L5 W) e
input mcasp_ahclkx,1 G5 J7 g% i: C3 m+ U+ a8 f
input mcasp_aclkx,
# q& H/ J) i# ]* h5 p/ |input axr0,+ X9 G" s( l: {0 B$ s A `- l( J, F
) A0 l8 @ S7 }6 P3 Q
output mcasp_afsr,; }7 J1 h. y- G2 M* i+ W( ]
output mcasp_ahclkr,- O1 {6 i4 f# c8 ^; A0 [
output mcasp_aclkr,
" Z* [% K& r5 m9 q. ]% ?7 ] Voutput axr1,
8 m+ U0 K" P( o- X! x/ [; O assign mcasp_afsr = mcasp_afsx;
5 Y3 ^) ^) U" b8 G& zassign mcasp_aclkr = mcasp_aclkx;
V8 @3 G2 `+ Q5 z0 |/ z- \assign mcasp_ahclkr = mcasp_ahclkx;. s8 q: W; s7 n" @4 f5 {- k: S! _
assign axr1 = axr0; % ?- A! }8 R# T( [
3 K* ^4 _$ t. c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; K* H2 |& ~& k
static void McASPI2SConfigure(void)$ N; T g: N+ m2 }6 g
{
2 J2 E, d4 _! r r1 S MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 c* U+ d; O; G! ~$ K, F' {3 c$ f: wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 o" K- j) I( C h6 m% E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 l. {, t0 l i. ~" G- V) |1 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. Z& @0 G' s, \. l. P6 ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- `# ]& j7 M+ S" YMCASP_RX_MODE_DMA);
; U' ^" L. S; \& Q( s. j! r. lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& e# I/ q0 Z; Y7 {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; E( T- X, m/ R6 A' X, S- V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ q! ~! r; h" o3 \6 fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ p$ A, N M) KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, l# ^$ ]' h" G' D9 l: `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ ?8 V7 |3 X! b: S% ? O5 l# }8 AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. K( X a2 [* i; e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( U `3 K8 R0 F4 }4 CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 R8 P& f4 R! t: l% F( V/ w# O
0x00, 0xFF); /* configure the clock for transmitter */- m V( i. V3 ]" |0 I1 l3 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- ~4 Q, w1 E2 `& [& mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 B& o' U3 f+ u2 iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 k( D& @/ F* D3 P0x00, 0xFF);
& n, q, ?3 c6 m, \) o: t. z$ a
, l! K4 U: A, `2 T/* Enable synchronization of RX and TX sections */
' {/ A0 y8 t8 p6 v* R4 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: _% H3 _ N, W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; t( k, d3 W% \. FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. C4 k- O, p3 Z- E/ Y) z* U** Set the serializers, Currently only one serializer is set as" t" z/ L5 {- R
** transmitter and one serializer as receiver. P3 b, X$ l i& R/ ?
*/
/ f3 X8 l5 k4 [+ K" k7 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ Z; y& o, h- }1 M& a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' k+ j4 k& x. }" ?" P5 [
** Configure the McASP pins 6 b7 i( b Q7 H( ]1 l# U
** Input - Frame Sync, Clock and Serializer Rx2 F6 H( ]& J' y4 N) |- y
** Output - Serializer Tx is connected to the input of the codec 3 `5 t6 d1 Q* l: e! |+ u
*/
" K5 ?3 W6 p) x# { F9 @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' s# C2 Q$ _3 A7 a, f" ] k/ U9 ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 I w3 S$ ^/ pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% Y6 F8 ]( n/ [) p' C; T$ R
| MCASP_PIN_ACLKX" F4 K4 l) l$ b7 g, ]) ?" Q6 r
| MCASP_PIN_AHCLKX7 I$ n* Q4 Z2 L/ D4 x3 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 m- a! G; H" `* f, b. n7 P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 {$ a4 ~ [- }) U( O" h# s9 \$ ]
| MCASP_TX_CLKFAIL
! x! G" M) g ~2 l# u% w| MCASP_TX_SYNCERROR+ j" {- K r. Q2 y+ D! E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ z2 A% M' s$ z$ ^, ^. e- u| MCASP_RX_CLKFAIL6 w7 G; L/ N5 i7 z* j
| MCASP_RX_SYNCERROR ; T2 e9 f/ P5 }6 E3 s: g
| MCASP_RX_OVERRUN);
7 B: [8 u0 T: \3 d/ D3 a1 p9 }} static void I2SDataTxRxActivate(void)5 z- g* m( K+ j! @4 e7 V
{" O ?% g Q: T7 q- x4 `- X2 [
/* Start the clocks */
: ?9 e" o5 o OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 f, n6 l; I2 `. v0 c3 ?+ AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 j; t1 m* L4 Z, mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! V: o' u6 i/ K UEDMA3_TRIG_MODE_EVENT);$ K$ J/ n; ]+ A# G# g$ S$ s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& x& G$ R$ v* ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( F( O+ C( U+ B* Q; ~3 QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 p- m* b2 c' S5 F6 m$ j3 L) w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. @7 Y W @6 N, {" S& a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
~/ ^& i* i" D+ RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
E f, u8 @. S8 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- Q: l/ \+ ], ~} 8 Q' r5 F$ h2 {# S8 }! W0 Z% Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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