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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 m/ |* X0 R. s- Q" W" n
input mcasp_ahclkx,% z" b" ?. Y h. _- I7 T
input mcasp_aclkx,6 c5 O+ t' B- m$ {
input axr0,
% [ Q( T; ~; T* r2 R* f8 g1 P( s7 G# I% U
output mcasp_afsr,
: l) _1 n8 U) A. {2 Boutput mcasp_ahclkr,
1 O" s5 [$ s" B6 p/ z6 |output mcasp_aclkr,
8 y+ h6 I% T' G' ?# r* I! A3 ioutput axr1,2 g/ ^8 H: D9 S% h$ w3 d+ |3 s
assign mcasp_afsr = mcasp_afsx;" u2 y% m; O. Q
assign mcasp_aclkr = mcasp_aclkx;, y; M* d% b2 }' K1 l7 \ M
assign mcasp_ahclkr = mcasp_ahclkx;
' I# A6 w( r1 K( Fassign axr1 = axr0; 7 Q( \% ~/ ]( e4 z* E: N
" e# z& \! z# P+ V7 c" }4 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 {6 J5 l2 s" C5 u4 Y8 U3 U/ d
static void McASPI2SConfigure(void)
/ `9 Y) y2 f* c; E" ^1 ?* P{+ z+ D# j+ p4 N/ D3 p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& N+ q" c* s+ @, a( f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 |) r/ C( f6 w& {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! A, P, P0 ?7 K" nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, y9 ~' f% Z* V; o* MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, n( A f1 y+ J8 f$ DMCASP_RX_MODE_DMA);6 g7 |- ~% { p/ B1 Z+ e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. ]! [. \' |/ R. y2 K9 ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* v, F+ w* N: ?, e& g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * {+ s: [! l7 q" v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! j5 O4 r8 Y7 D: L" \* d; C FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! V4 y/ w( e$ O5 a. {+ g5 @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ z/ C& q1 W* fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 _1 [: G8 L+ U! B& ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; r: l7 {0 X% L2 W4 \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 k7 t V' j' T( @: f
0x00, 0xFF); /* configure the clock for transmitter */9 z$ R/ L) H, D- ~3 _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ w- b% p/ y- `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " g# X, b- e) `! u0 x5 s# Z3 ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' r% E; [# m! j) r4 ~) T0x00, 0xFF);/ P' ^: J, H T# w+ x9 B8 w4 W
. U6 q: [9 E- {, c8 ^. s/* Enable synchronization of RX and TX sections */
6 y, P. T" @0 b* vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
V z* \5 R' {) j" ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
e7 i+ |6 a7 Q7 {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** q1 q* E7 q# x
** Set the serializers, Currently only one serializer is set as* o) ~4 B' J$ E/ b3 z3 B
** transmitter and one serializer as receiver.) [) z A% ^2 T5 x5 I+ |3 k6 C5 K
*/
$ m$ K) I6 d! S1 r) w3 r' _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 R) v5 G% b# x9 P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 Y0 ` M' n- ~
** Configure the McASP pins
9 S* q7 N7 B0 P( d- D2 G5 B** Input - Frame Sync, Clock and Serializer Rx
0 ]9 Y/ C5 t( S) a* Q( c** Output - Serializer Tx is connected to the input of the codec
' q4 m# A; [. q2 p*/
2 p" H7 D( a( x; u# lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) \: \8 ~7 E! Q0 |3 T5 l3 \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); f5 e% b7 e5 B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX F( ~! I3 D5 L9 q$ w
| MCASP_PIN_ACLKX
; T- G2 s8 `- X. H| MCASP_PIN_AHCLKX
9 P5 C1 y# {& W D( Y, u& T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: Y( P+ S; q# U# eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% ]% C, r0 {+ b# D2 l7 J/ || MCASP_TX_CLKFAIL 2 A. J; d0 y' l- i# ?& X8 @
| MCASP_TX_SYNCERROR
$ D: K5 d6 C$ k5 q% v! d5 W& || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - o/ t) L2 X& Y; c1 U# f; H# R1 [
| MCASP_RX_CLKFAIL- c4 M% c l% z; z) E+ S
| MCASP_RX_SYNCERROR
% Q% e7 \- |' G, s| MCASP_RX_OVERRUN);! b; ~* l- P E
} static void I2SDataTxRxActivate(void)' r; M- p j3 _% h6 C6 [1 H
{
7 i: i8 `" K0 `. ^* T0 R) R4 K9 l/* Start the clocks */
* n* G1 t8 A3 L& ~' ]; Q! `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 L0 {; @! k7 h3 w- x" rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 U' B3 y* }/ J0 _/ i3 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! B6 L! C9 U8 x4 @' ~, a& @EDMA3_TRIG_MODE_EVENT);
1 c+ r( P2 U( q: X; @, R HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" F0 ]. C4 l' N/ A: L% VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! [7 E6 S O! |% f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# P. c. t6 k( @ BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 u! s. X t, _2 y' C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ y0 w3 G0 X2 e, n1 b4 zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 K& A: ?+ i) Q% m T% UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 Y9 z, f v1 x8 {6 p7 Y' g$ o0 l
}
' {7 ]3 ~3 v8 ?- P( L: O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) e! ?; i3 J+ N9 N
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