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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 i. [+ R0 U/ @/ {) K& u p& {
input mcasp_ahclkx,
3 F+ Q) T' Q5 G: `input mcasp_aclkx,2 g) `7 i2 d# V# q2 o: |/ T: M% U
input axr0,
% d7 G+ r6 x5 j% q: ] D4 E" u5 O% h j4 U$ G
output mcasp_afsr,
0 z' s: y5 N r8 j9 Doutput mcasp_ahclkr,# x4 ^! |6 [( r+ s; X9 h
output mcasp_aclkr,8 G0 K7 i$ K" M% E
output axr1,4 f) h5 e# u- z
assign mcasp_afsr = mcasp_afsx;- }* L9 o% q) J5 u* l& h
assign mcasp_aclkr = mcasp_aclkx;
! t& D! Z/ h5 S8 ^. D+ P+ ?3 rassign mcasp_ahclkr = mcasp_ahclkx;
# N. T, I$ ]4 q$ ~1 \assign axr1 = axr0;
5 v0 u! T3 ~7 o7 r, H4 q
) k) R# M9 e$ e+ w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 E, J( w/ j( `' kstatic void McASPI2SConfigure(void): c, o( X7 p. K, W$ Y; a& b& Y
{
, G. F. A+ Q( G4 ~' `6 a' H$ JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ p& z" x0 F& rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- {) c% q$ z9 ^7 H- I' q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) h# D/ \+ ~2 I) K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; t8 L. a; y2 e x& a& t4 qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 N/ Q* A- X. H' K2 B) B9 l7 T2 N# MMCASP_RX_MODE_DMA);( {0 t8 v% L% b! i# T9 C& b( H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ Z& V" Y$ z0 G' {: lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 W& {5 M) H0 H( z+ K. W# z; nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 P1 A1 ]* i% D4 V( ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# q( C5 N+ W7 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / Y+ E" `0 m0 Q4 j5 n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ q1 I$ [- k# X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# B) F+ q/ j Y1 ~$ P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 z8 c/ ?5 b0 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; Y6 y/ i, M6 ~) y7 @& w0x00, 0xFF); /* configure the clock for transmitter */. I3 n4 f( ^, O" L5 J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 g3 I/ n, p5 D1 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' ?5 A& R" O* P/ Z' m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# ~- h5 e* Q0 ]! G6 F2 z+ S0x00, 0xFF);% `2 ]4 Z/ |( M
N3 B8 Q4 i/ W0 N9 L
/* Enable synchronization of RX and TX sections */ 0 L! m/ Q* \ c) b3 [0 B; S+ |: o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 k( Z7 v& b; e) `1 V W" v8 q7 SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& y( t* w) m3 N8 `) Q; h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( a2 B/ C6 L! ~! d4 B' _
** Set the serializers, Currently only one serializer is set as
8 l$ A+ D% |$ Z1 C0 _1 d** transmitter and one serializer as receiver.
+ k3 N( a# R+ @' [( ?) I*/
) |& K; q8 v1 S3 L" pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) S/ t$ t2 g& d5 @0 u9 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 ?- n% h# j1 d/ N2 E
** Configure the McASP pins
1 g% `: {4 v/ v** Input - Frame Sync, Clock and Serializer Rx% e2 U S8 Y: l0 ?
** Output - Serializer Tx is connected to the input of the codec 4 v% v+ s' T7 _/ s4 y8 X
*/! h) v& H" B" E0 K3 P: h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); r( W$ B2 o, d0 h: z$ I* T. F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 e$ \/ E6 \" M. W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# {! d/ t- j) G8 [' _) U
| MCASP_PIN_ACLKX4 z( \( e2 `8 x- _' j, Q% Z7 P
| MCASP_PIN_AHCLKX- B' ]1 x4 |2 T! I# p& i" \ t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 t9 r0 U+ U. u1 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! R: R9 Z h2 ~6 V7 h| MCASP_TX_CLKFAIL , W, R3 B4 x9 x! R
| MCASP_TX_SYNCERROR- B6 m. O# A9 H$ i9 A7 r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 r. g: j" g3 G a3 M% J
| MCASP_RX_CLKFAIL* s! g/ W# r, M; h; h
| MCASP_RX_SYNCERROR
; R7 |0 [0 U) U: g1 u0 T' t4 l' D1 |7 G| MCASP_RX_OVERRUN);
. D! L1 N6 Q% p} static void I2SDataTxRxActivate(void)
! i8 O( D D H. i: g" K( @/ y{: c( r/ a3 N$ e' Q' e
/* Start the clocks */- J: ]+ l2 q! z! e9 e1 L4 _9 d1 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) E" L% s/ {9 J: u; J3 y: aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 D; s2 ~# E4 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
J& `& m. [( g& [$ g1 Z) KEDMA3_TRIG_MODE_EVENT);
7 k: A" V" `- k/ \9 J0 D; X0 Y: SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) x, i. b: z2 W/ Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# f0 \6 d. i5 b) q4 f7 ~( w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; K/ H( w, c0 D8 u6 }3 \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ {+ t# y. X: [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ c' j, H. v$ V, n* b: {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 l/ Z" ^# p' y# H( oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 S2 h$ y8 f* Y& H* _& p0 ^- t( l( H
} 3 Q& X5 F( j6 p( j- N: r" @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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