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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# U1 b: I3 D% {$ m R" yinput mcasp_ahclkx,
% _! H1 T% u! \3 Ninput mcasp_aclkx,
X7 n4 H: G! q1 n( p# S# ginput axr0, X' x7 J( S1 A$ F0 f
7 v, k9 k" v* D: O1 woutput mcasp_afsr,0 m6 ^& B0 k2 i0 x
output mcasp_ahclkr,
: X1 ]$ h9 [. y5 h, s: boutput mcasp_aclkr,
' o0 r3 @, b) Foutput axr1,7 s/ q6 \) |+ X4 D5 k3 k5 c
assign mcasp_afsr = mcasp_afsx;
0 D* B2 M s& U2 Tassign mcasp_aclkr = mcasp_aclkx;
$ U8 M$ b# p1 T9 a# k7 H! q$ massign mcasp_ahclkr = mcasp_ahclkx;
! _ @/ x2 @! V" A% Iassign axr1 = axr0; 5 o8 }8 ~0 A. f% ?. G
& ]* [- p d1 {& S9 |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 c) G& N, r5 m/ v) _3 Y$ ^. ?static void McASPI2SConfigure(void)6 s4 g0 r; F( c5 M
{- B6 G4 f2 |( J- ^; b6 U# Z( q/ ^! ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 D. h' @* y8 FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 V' O- @$ M4 ?) Y1 Y: ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# v; ]$ `: h: ~% l( BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) m" A5 p" m+ |1 W7 h3 i: YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# x3 w( g" G, G! ^/ W6 jMCASP_RX_MODE_DMA);
4 P5 T2 }: ~" eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; E# T2 j" n" a8 KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, J/ y& X6 q6 O6 d4 }- M! GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: ?7 N( P n# v$ k% K9 I, SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' S! I! p1 {9 H6 D# E, b$ N P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , T9 Q% b; z. R7 g/ {6 Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ z( C' Y. C9 Y3 E# c2 Z3 TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 `# M! w/ v0 A) PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + d% R* V& ?& F3 u$ `! y, R3 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* ^+ G. c" E& o- X( n0x00, 0xFF); /* configure the clock for transmitter */' g) g. |/ j2 w! V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 p' S: {3 Z E1 d, t7 o5 f0 M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , T/ S3 L, ]5 n6 O. W" f8 O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( s' d& H9 s- W5 u7 N3 d9 v3 Y0x00, 0xFF);! w# J# |8 ` R m- t! T8 }) d% N
: `* t. ?+ U4 R) g! C- |' H( ~
/* Enable synchronization of RX and TX sections */
* s3 \" N1 s! h' E% ?. R; t$ MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ N0 ?" v* D$ u. o9 T. [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. x+ C+ U3 h7 x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 O' L5 T1 q! P' a! I; L
** Set the serializers, Currently only one serializer is set as
/ ~' g1 O3 n5 b5 f: [* K5 L7 u** transmitter and one serializer as receiver.) d* N8 J& Y7 u" F+ ?) d( {
*/
: @# w, b( U9 a1 k3 T0 E+ GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 x% m; b& a% K7 n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 D8 G9 J/ T1 Y- t# s0 Y+ o& G
** Configure the McASP pins
( K8 u1 C, Z! R) f8 U** Input - Frame Sync, Clock and Serializer Rx% A) v5 ]- u. ?4 {
** Output - Serializer Tx is connected to the input of the codec 9 r7 G$ b% L5 Q$ _
*/
8 c0 J& M5 v2 k) ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( S& C9 F% b' S/ ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 n, H: p4 d. P9 g: P7 uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. _# r5 u0 s3 ~# ~" o' P2 H
| MCASP_PIN_ACLKX
/ z2 c3 M: [6 h! B+ ~| MCASP_PIN_AHCLKX& ]6 A) t0 e! T. x1 F- |1 n& A6 x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- D6 Y( O# e: z. a* \. ?5 p; Z/ [3 q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / Z* n4 }# [& y) Q8 K( p* h( V
| MCASP_TX_CLKFAIL & Q" i- U4 L/ o4 C
| MCASP_TX_SYNCERROR
3 m/ l: V; W) P# O6 d( _3 x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 C" f& Z( q) I4 t# z
| MCASP_RX_CLKFAIL
" o# p3 }- M' v! b7 ]8 f \: a# ^| MCASP_RX_SYNCERROR
' z5 P* w6 Z+ M5 q* X" h! @$ || MCASP_RX_OVERRUN);
. o1 @: k K7 O3 v! F} static void I2SDataTxRxActivate(void)
1 C. z, S% l2 Z0 g' r0 t3 b ?8 ]9 I{* {9 Y$ ^! k: `5 q
/* Start the clocks */
0 z- e! F( T% n# YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 G: S! h- U t# q/ s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! E8 \( j, u; B; Q, lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% O4 f- ~( {3 R1 m2 s0 ^
EDMA3_TRIG_MODE_EVENT);( W4 I3 }# _( e2 m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * ` I, R& t. e3 l P$ S3 J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 J# N6 ?- u+ p/ [, n0 I% W0 {* z1 \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* }1 Q+ w7 a' b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. C+ Z7 J/ e/ i( B5 ~" ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! K1 p/ ]$ i* R) N* J" z l) d. u1 AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- Z4 H" i) w0 ^) I7 x ?: V8 R7 n6 ~% N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ N- p' y" m6 |3 A1 R Q8 r7 ]}
& |$ W' U- H. e, Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - ^& f) U' L# v9 c& n
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