MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
( L9 H) m- D& R! M1 i1 ninput mcasp_aclkx,
input axr0,
2 Y5 Y& ~% j( R. Y0 B
- X0 T* ?. o( O0 C1 g" \+ Y/ z) |output mcasp_afsr,
& N3 X5 r8 Q$ X9 D3 E) y. A5 D  Noutput mcasp_ahclkr,
/ D7 ]& w$ I, Soutput mcasp_aclkr,
output axr1,
$ r. i' @) x5 h8 y& Q: }

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
/ x1 X9 R9 `( U& ^assign mcasp_ahclkr = mcasp_ahclkx;
" ?( g% g- g. m5 Massign axr1 = axr0;

6 O# v, }, I+ X! A
4 z* r! F; v+ e! V; C

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 m+ `# C$ F8 PMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
3 g0 o2 n4 F( R) Z! A; mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 A9 L7 W8 w. }; y2 @& x0 OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
+ b# V" j' c$ d5 I$ f) vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- r4 l' D  X/ ?MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- n4 I; p5 L, lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& O" }5 |) Y4 Y% g4 B0 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 [" F8 A6 `" U% wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% i3 K* k( J0 |0 `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
" @2 O1 Q) _# W; `0 K! PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" H9 S0 t  [$ P1 |4 J' X5 }4 i0 [) _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 ~  Z4 o+ z3 E: K2 X( S" V0x00, 0xFF);

/* configure the clock for transmitter */
6 g3 Y# `0 s! G  x  z: EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 O5 i9 f; a8 d* s  {/ UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 K/ b; q) ]% _0 b  |# |0x00, 0xFF);
8 Q) p. }# c5 M) S) a
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) j9 [% N$ I( EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
* |% `: z( c0 l** transmitter and one serializer as receiver.
*/
( {1 ~/ a( s% d! F& K! ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. n% x2 X/ ~) _! b4 r" J4 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
; e* x/ n; {5 V; H** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
+ q. y  o- T0 D** Output - Serializer Tx is connected to the input of the codec
*/
. S' i( q1 p# @/ hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 G# x; n* M# H- J  ^3 ^& zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 m& @) \, ]" e0 J# h: dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- K5 G( G# }( }2 _& K* I| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
  D: n; [. w$ w1 G| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
0 H, ]9 e) l+ m0 A6 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
2 D) [; N( D' _- n. o| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" L9 k  e% H* q| MCASP_RX_CLKFAIL
; q/ O( j- a, b, b1 n| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
! J% v: L( l& v% T3 l/ iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" O2 l1 K8 p! H# u5 P; TEDMA3_TRIG_MODE_EVENT);
3 \# ]6 D& N7 r5 L: REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
6 |% J# k( w6 u" P3 G1 m8 K% W( Q) }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
5 d8 t+ D9 {: O1 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

+ J, f& H0 Z: ^8 W' M9 x