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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ e9 ~ S! C- b D# B, E
input mcasp_ahclkx,/ P8 u$ ]2 v+ u& Y h
input mcasp_aclkx,2 s& V8 e: V2 e# {2 M9 E/ b0 `
input axr0,- o" D; \ P/ C
0 w/ F, n* F; A8 h; i* z; N* d, \output mcasp_afsr,
' N- K; F/ I" Noutput mcasp_ahclkr,
2 p& h! E, ^' p3 d) R0 o' j9 loutput mcasp_aclkr,
$ Q/ k9 W7 [6 z& G+ |output axr1,
! B x3 u4 O) i$ \- H0 a assign mcasp_afsr = mcasp_afsx;% w* X p! h1 x
assign mcasp_aclkr = mcasp_aclkx;
3 I( |: c( m" H# H6 ~assign mcasp_ahclkr = mcasp_ahclkx;- ]& ]/ B, K9 Y% d6 C( y* w
assign axr1 = axr0; # L5 ?$ ]7 Z; F
_/ J8 Y& Y7 H4 v) `+ n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 ^9 ]. e, D' u- P, e. K* V
static void McASPI2SConfigure(void)
6 X8 j: F: v7 ^1 y{
- m) E1 t+ z, O$ A1 x7 aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ d( P6 a3 q& ]4 d! }/ F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// V- M7 O8 ~, Y+ O" \" e8 E( N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; c+ y8 U; l& k- f# |$ D( NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; t9 \* ^% U; z. Z$ I; v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# i* O2 M1 C: H4 S8 l7 P2 G, d
MCASP_RX_MODE_DMA);
1 \$ Z) F7 z& `* uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ ^& }8 t8 _( s% l. P- z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 R% z. T" @, v- GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 i$ D {7 R) O" KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* \& I! N: }! N6 g% pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 w$ y+ F' ]+ P7 ?5 @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! C3 u- g$ C0 K& E3 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 g: B5 p% g- o2 Z3 [5 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! T8 u6 J$ m& x$ zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& t! b1 g) i6 k X$ h
0x00, 0xFF); /* configure the clock for transmitter */
4 N# \: M9 p) H8 XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) C2 ~) Z9 g' P9 G$ m/ s6 S$ ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * d% F& L2 t" }' b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- q) F, Y- `* v" q8 L N7 \0x00, 0xFF);
g7 K L8 W% k* @. |/ ]
/ m# |0 y7 T: N/* Enable synchronization of RX and TX sections */ # {/ m, R; _+ w2 C( g# N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; v# W1 f7 h- f) z& j& ? n% Y) Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: ]% v- |3 N# _' k( O, z# {8 f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; j% b# |+ L8 D8 Y) ~5 `** Set the serializers, Currently only one serializer is set as
/ G2 _' g2 { f2 h3 s+ i** transmitter and one serializer as receiver.) r( ^% [+ V; t' T% ~1 T
*/
7 u* f2 i+ ~, R' p4 s# j/ @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ K: A8 L; g$ t0 i8 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, R: i1 i9 E; s+ y** Configure the McASP pins
* }3 f$ U8 ?* t0 U% i E( S** Input - Frame Sync, Clock and Serializer Rx0 q$ |4 z0 j3 ?$ i% D n: \
** Output - Serializer Tx is connected to the input of the codec
6 c" P" O" C5 \. `! P*/
* Y* @$ y8 m8 `0 |& e. r! `/ fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" r3 b) X7 c5 E1 rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' n4 Q2 q7 Q, r& p' xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! s2 C9 n- G3 N( C
| MCASP_PIN_ACLKX
. ~# D6 D' |( g4 ^* G& D. p| MCASP_PIN_AHCLKX
8 B2 i1 y0 H; I% W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* ~: F3 f, M1 y: C6 [% oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# `2 U: o7 h" f0 ]! y3 D| MCASP_TX_CLKFAIL * l9 t1 q2 ?! V( k; V
| MCASP_TX_SYNCERROR
. l( G. N; `/ e d+ || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: M' _% F5 v5 i. t. b| MCASP_RX_CLKFAIL0 O; T3 f2 w6 @5 L/ g- j* s% X8 ~
| MCASP_RX_SYNCERROR
: K9 H2 H8 J% j# c' N| MCASP_RX_OVERRUN);7 o* ^$ G; N4 P/ M% t
} static void I2SDataTxRxActivate(void)
0 V; x- q$ k9 R& _6 A{( s1 }5 {6 O' W7 j5 m) n/ ?: G, n4 J
/* Start the clocks */- c ^6 k* X7 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; t) {0 e! M2 P( N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 s3 I) d( n% `! ]2 ]9 e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: x, L8 s0 P' V" S
EDMA3_TRIG_MODE_EVENT);
: L& K3 k! v& T- x ]. I x; ~6 t) WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 o- q& S2 L7 e0 X# a* r2 y' G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 \5 O2 c+ l/ E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! v" k) z. {, B6 `. f! iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 \" F2 D( V9 N' K- x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. v% h% K% a: a |; @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 N. \9 {5 H5 e* X# b/ u' T' BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: V- a% [' g% d6 u0 x% B8 V* \
}
7 [' p6 Z* ?) X/ z0 S5 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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