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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 o: t( Z- j: U% q2 D! ?: L- Ginput mcasp_ahclkx,( y/ M& O- u- M. y
input mcasp_aclkx,7 q# o: N. {- @; Q
input axr0,/ O' n3 S2 I$ c& x+ U$ c% B
8 ]) r$ Q) _' A! F. b: Z. Y2 z
output mcasp_afsr,5 @, V; s& M% `
output mcasp_ahclkr,
' r. O8 r( X/ n( Y+ Y0 voutput mcasp_aclkr,
6 u u" h0 l- a* eoutput axr1,, P7 U: X' U7 R* n: T1 ]
assign mcasp_afsr = mcasp_afsx;. e. ]1 j' Z$ Z0 }
assign mcasp_aclkr = mcasp_aclkx;
0 i" v7 _. K/ nassign mcasp_ahclkr = mcasp_ahclkx;
$ D$ W; ?; _6 r* rassign axr1 = axr0; 3 L2 b, E5 [' e/ F+ |0 E7 l8 K
8 S$ A u; t; r% {' T8 a, m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & L8 U! Z1 i, e1 F- ?. w H% d
static void McASPI2SConfigure(void)
& X6 o, \2 Q* T2 L{5 S+ n& n7 b* p7 y( P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; _" q D" C% DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ P8 M: q$ E7 a6 p& QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' k! f9 g- Y W. j1 i# q& o4 \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 W" d( P, E' g/ b* q( H: u! n# \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 e! y t5 D- j# x" k! G, s0 R, CMCASP_RX_MODE_DMA);
( b" b( V' C7 l6 W* J0 F4 nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
N2 o; X$ I% b4 `! DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! L; {. d. [4 x* A0 C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! ]$ `* [* s! \# A" UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 Y' ]# h' t9 V& j$ i" d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
~8 J: z Q* m" S* A5 M1 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 @1 z5 d7 z' ^0 L6 [0 O6 b: @( `& bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' |5 m6 Z" R; L) @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; V2 F; a, { z% ^9 F- Y; Y7 E2 mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ }# R/ U' k& Z0x00, 0xFF); /* configure the clock for transmitter */" W' U0 I9 h$ W+ Q. a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; d% G9 y v8 s0 `- _9 E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! F& H ^7 U9 g A4 j3 U; L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) p! E6 L: W- \# s/ N: \
0x00, 0xFF);
4 j( Q% G+ t( o) t
( ?& m4 T- b( Y3 `5 v+ T) J; h, R/* Enable synchronization of RX and TX sections */
8 d, v) }6 J5 r \: E9 S- rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: \$ k) Q) |, ~8 o/ ^9 h& l1 I2 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 ~! u# f* e( ?" c- K Q- I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; k5 y) i& i5 I8 L** Set the serializers, Currently only one serializer is set as4 H; C" |5 W5 o
** transmitter and one serializer as receiver.& h8 i- E" {( ]; h* B% {) o: q: ~* X5 M
*/
0 O8 o5 _8 \; q4 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 Q+ m/ s. Y! H: O% Y+ C, H, a9 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** Y( H* t+ B" `0 N; e% b2 w9 X ]
** Configure the McASP pins
1 D+ i- k/ q& u3 K** Input - Frame Sync, Clock and Serializer Rx
# r2 l. b6 k$ E! ]# ^, {6 x** Output - Serializer Tx is connected to the input of the codec
& d( u8 k" ~( i( g+ J1 h8 `*/
2 N% }. _$ S5 C, M! BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; y4 m/ E1 M O; c& _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, q n, @! \: }8 `2 f8 B7 E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 o. d! a% @; U3 C5 J
| MCASP_PIN_ACLKX
6 c' ?- w, r `( N7 T| MCASP_PIN_AHCLKX
0 K7 v2 [. w4 }2 ~& @1 Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 m O3 F% h; G; O7 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 W4 p. z' I1 D R! J6 O2 x/ K
| MCASP_TX_CLKFAIL
* R/ g! g" x) }! R- k| MCASP_TX_SYNCERROR# T; H# [3 y: D( X7 C* n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 l; X0 ~, }; ^( O" c) P
| MCASP_RX_CLKFAIL
% v% n, q) K( C' F. r! O2 t) U| MCASP_RX_SYNCERROR & @, ]7 [* D' y( m0 R. t
| MCASP_RX_OVERRUN);
! {7 ]5 B# K; O+ |} static void I2SDataTxRxActivate(void)3 A! d" G4 ?" Z
{
8 c* d5 {' e( `. N2 L, R/* Start the clocks */
& N4 a( \) G+ X0 {, r( h3 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( j) `" N. W5 A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 _. O! q* X/ \& e6 b# o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# {/ T2 \ d9 W( Z% m$ bEDMA3_TRIG_MODE_EVENT);
5 K* _! x# e% NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 T7 B- C, t; W, g! }1 i5 K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% m5 A) |+ F- \$ A; w6 z G9 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 g D$ d9 m6 t' S1 _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// l9 d) x5 b+ D* l( s8 q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, F& l0 [3 H6 X) n* p' A! O3 j, _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 S2 p+ ~3 N. W" [2 r6 U4 p& n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ w' o7 c$ Z+ H; N}
# s. i6 H- Y3 }$ w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * p/ a; l( ?6 i4 X
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