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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 T) v2 p! @, ~! m( U. ^4 iinput mcasp_ahclkx,
" x# y+ w3 ~5 Ninput mcasp_aclkx,. u, B' C7 H. E. Z4 F; r
input axr0,9 ?- [4 `/ T6 M* O3 v+ @
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output mcasp_afsr,) H9 [6 O0 q+ X# p ^; q
output mcasp_ahclkr,
9 B3 M, X7 C8 F' y# _* _2 U1 {! moutput mcasp_aclkr,
7 v4 Q) b1 A$ }9 }( W* J2 doutput axr1,
4 }( C" z/ k) Q assign mcasp_afsr = mcasp_afsx;
' w( \* F! ], z" K- \% Rassign mcasp_aclkr = mcasp_aclkx;
1 E$ ]4 _6 K$ Q) N; J+ J1 M% Nassign mcasp_ahclkr = mcasp_ahclkx;
* p$ J: ]3 k: j$ U6 Xassign axr1 = axr0; " X5 }3 G' ]& D. `5 ]6 B
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 n* m! {7 T( mstatic void McASPI2SConfigure(void)
, W+ n$ {! ~& H1 J% f4 j{) ^& A" L( K3 Y2 j1 d) c) e8 N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 @+ j% t+ u( l! p9 ?* T' T" d5 d! `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% ^; X$ W+ s6 x2 h5 @4 TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 n0 G# c# ^- C! d6 {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
^1 |: D d& ]* v6 _3 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) F, q6 V1 ]3 i: ~9 t& G+ M% u
MCASP_RX_MODE_DMA);
# F1 W9 } s) {: l4 S- V! { y9 {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! ~3 W+ Q0 Q: H& y2 K/ [$ a5 O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# l* Z- @& j3 @$ r7 z5 r7 Z* x! U7 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, I6 R" J, w7 o3 L* [+ f' k) g& UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# Q* Z" V7 O) U" d4 X6 p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * X+ ~% b7 x3 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 a4 o7 }+ g, ] s" r3 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 w6 u% k) J$ X. K: B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& d5 ?% a* C: E- B' n$ XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# c9 O# r8 B7 l, u4 Q
0x00, 0xFF); /* configure the clock for transmitter */ }7 c3 Y/ E6 E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 P; @2 H, c8 Z4 h4 f: qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : _4 R( F$ x* c! Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 g7 K1 J( T* C& ^! D, x0x00, 0xFF);& B$ ]% g9 y5 ]" ^' o" c0 E
* s$ T) J i/ _; e- N/* Enable synchronization of RX and TX sections */ d) v( V5 t- t; b% L W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 n* |: I7 X6 w+ @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. M4 X6 Y6 L/ vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* \$ t9 L0 ^! j( y1 Z7 |
** Set the serializers, Currently only one serializer is set as6 @$ L6 R4 ?0 V
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: j& b2 S5 Z( o7 m6 Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 c5 w0 |0 H. c. l3 ]! Y$ G** Configure the McASP pins {/ w/ E- C( ]% s% l$ |
** Input - Frame Sync, Clock and Serializer Rx
/ J1 Q: y8 b: z) g4 M3 a- s; S** Output - Serializer Tx is connected to the input of the codec
) f. j L7 g% Q" x; D* g*/5 u1 w6 X) A7 K# a6 m& E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 C9 w1 g/ M. g* M Q8 @+ _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 u$ @; y# T: w5 s, j9 o4 SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 s& Q6 q K; h: r7 s$ C| MCASP_PIN_ACLKX6 ]+ z) ]- q4 b7 p3 Z; M2 Y; c
| MCASP_PIN_AHCLKX
# x! ?7 S5 \' s; }/ E0 u8 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- R, \5 N% x* [/ i' AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # W9 G1 B: C8 T( O
| MCASP_TX_CLKFAIL
# _- \: _9 W" F ^% w| MCASP_TX_SYNCERROR
& {+ a' _( O" L! A0 _+ C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 J }/ F2 q( Y- v- [- P5 p# ~7 s| MCASP_RX_CLKFAIL& K% `0 `. M5 X2 G7 i4 l. [- \
| MCASP_RX_SYNCERROR % q. B3 T" H1 N8 L% w1 r
| MCASP_RX_OVERRUN);8 V2 s! s3 |( F( P5 x
} static void I2SDataTxRxActivate(void)
7 |( s) t" A, s( W N{
6 b) x. C5 i# `4 x/* Start the clocks */
. c+ ?0 {2 f' jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 V+ J: V8 b% f: e3 J8 G1 U3 T# FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, t7 b/ U% x5 n' `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
Z6 v7 ?9 }% @$ T7 U% G* DEDMA3_TRIG_MODE_EVENT);/ J3 ?; K }! Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 Q) [9 E* u+ m) VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" ^% t+ L) v0 V; h+ K! QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. k b1 Q# K: j* {) g4 s; O- K" ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, e# G. D. N. N: k; F9 x: n, e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 X L$ n" [3 b n4 }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 r7 e/ f, ], Q, z- a+ `/ Z5 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! F! L5 K/ o: @* I T! H# _
} ) ~# P# d+ U2 m0 N5 x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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