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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 [" C6 i2 `) ~; B" h
input mcasp_ahclkx,. X9 v0 ~, `4 ?0 ^" C
input mcasp_aclkx,
5 p" J4 p7 Z+ @* p5 cinput axr0,
2 H, J5 o+ h8 G& g# N* J1 [8 c/ z, W5 a' q3 G! ?! S
output mcasp_afsr,
( V6 B- ~8 Z3 youtput mcasp_ahclkr,
+ S, S5 N2 l9 D F' d: ^' E: g+ `* @4 Joutput mcasp_aclkr,
/ o$ r# ?) a+ E4 v! E* Q) Voutput axr1,) S, |5 O9 x! G) F$ X Z% @
assign mcasp_afsr = mcasp_afsx;
* n( |: F) z& b. L. X0 xassign mcasp_aclkr = mcasp_aclkx;' A& V% t0 V1 b* Y4 v9 Y9 }
assign mcasp_ahclkr = mcasp_ahclkx;
# L7 `. K5 [( kassign axr1 = axr0; 6 o" h2 A/ q$ ~. _
$ A( A' b. i5 r; j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% ?$ a) \+ I' |- G' kstatic void McASPI2SConfigure(void)9 {, f9 Z% X+ l! y
{
* Q2 C# m/ {4 j1 Q' SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& i. x! ?5 x- L2 B, S, X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 p. w+ A" C8 w" |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. D- H' m: W) a' A& F$ g5 y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 ~3 ]; V5 d/ O6 q1 o \! t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 J7 Y. b: o/ z8 x e+ P
MCASP_RX_MODE_DMA);
" a5 \, b* u+ t0 F# m7 X/ dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- c7 _: `1 x6 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* c" j/ T0 M& J) v; Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! r& m& V2 v' o4 }+ _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. o# Y. r0 m7 N8 K6 E4 `! A: d( dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 @# ]4 k( F4 ^; H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; H1 V I( @; `$ m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 r+ ] J ]7 N' _) [4 n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! f( k. i6 q, A7 cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 s i0 y$ i! |6 X! S0x00, 0xFF); /* configure the clock for transmitter */0 Y1 a% W( o- _1 j9 I9 K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' \% Z9 K, i/ ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& J, s0 p2 ]7 u# a- c# u! GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, i$ V' g" l1 q# K1 @
0x00, 0xFF);0 E; }* O: o+ X# }. Y
9 u1 N8 Q; i# u1 g; _5 ^# Q( q
/* Enable synchronization of RX and TX sections */ 5 Z0 j+ p) D) d5 z! j% {# T# q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 V; Y( M8 m! B( n2 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: ~/ K5 _" T, E, wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 a5 L% R" j: u( M ^4 W** Set the serializers, Currently only one serializer is set as
4 o2 ~( w. O o3 \( _2 ^- U8 c: O2 b- c** transmitter and one serializer as receiver.
; `- O- [, q/ i) Y0 z, C' q*/
( l! i3 B& R: q8 f% bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); J4 F/ F+ ~% i* y5 o. T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" V5 G3 ]% O7 N! o
** Configure the McASP pins 8 S- v2 u/ z4 A( y3 V$ d# x, C
** Input - Frame Sync, Clock and Serializer Rx
x3 b) U0 C, j6 i; I1 L5 s** Output - Serializer Tx is connected to the input of the codec 2 R: f8 o' h/ b a
*/
2 k0 T) A+ |9 j( v0 ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; X! @8 R( A4 d, x: pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 L" ?' X; m' L6 n: D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ v! c( o* r* ?- h5 G4 [( G. I| MCASP_PIN_ACLKX
( P e4 X: Q2 i* c0 x| MCASP_PIN_AHCLKX" f+ t4 I" S5 F3 f1 B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 a9 I1 Y* R% K) p) D" R1 N( ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - D* W* K ?- H+ D1 ?7 B8 W' j
| MCASP_TX_CLKFAIL " a+ |! x; ^% s
| MCASP_TX_SYNCERROR
! @- `4 F0 B3 q5 D" c( ^1 r) H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + C& z# Y, v/ q8 K: @* q
| MCASP_RX_CLKFAIL; B" Q6 x( D; a% }
| MCASP_RX_SYNCERROR 8 {' _2 m9 I( u
| MCASP_RX_OVERRUN);
/ T7 ]% j7 K6 e& K} static void I2SDataTxRxActivate(void)+ C/ O d/ D4 P" _, u
{
- [: f9 Q8 L) b6 M/* Start the clocks */
4 O/ L+ y0 V6 G$ o. N \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) I& i: }/ y2 \/ r; KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, g/ v1 o n1 P! `) B8 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* `3 {4 {- w* V9 x" G7 K7 BEDMA3_TRIG_MODE_EVENT);3 [: G# A4 B. I' A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 p+ V$ ]8 S1 c# N! `* vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ x: W) ^ A0 G p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
D- _: p9 Y) g' V3 ~( a# K; C, EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 R) Z" e0 f1 {4 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# S w# G8 {" Z; _+ C1 v7 }$ GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& p7 ^& a" \# |6 T+ D. VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) Q) J. f: b5 C8 U+ C: [3 ]} # N% P3 ^: n! V7 Y: k' F' v& x: @- Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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