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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 X2 Y- T6 f: I3 Q$ e6 n
input mcasp_ahclkx,+ C2 q2 g; e, |) W% p0 O
input mcasp_aclkx,
1 \8 V. d N, O! u, H" F0 F5 ?input axr0,8 ]6 ?9 ?/ R% |/ W' p" A
, _) F1 A; M# @3 q1 T
output mcasp_afsr,4 ]& s7 h ~$ s! z
output mcasp_ahclkr,
; q% M7 {8 R0 `output mcasp_aclkr,
/ _; R e; }- a* z4 S/ U1 Ooutput axr1,* j( `1 L/ v0 `0 F9 g
assign mcasp_afsr = mcasp_afsx;$ ]( T/ J3 _0 [8 m+ j8 y3 u2 h
assign mcasp_aclkr = mcasp_aclkx;4 s* c( e% X9 X+ {! E8 \$ D
assign mcasp_ahclkr = mcasp_ahclkx;
3 W4 @& D8 a% z$ ]2 P# {) dassign axr1 = axr0; ) h/ l3 q) ^% @2 ]
4 H9 d9 N+ `* I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ I& R# q* ~- f: e* J! Fstatic void McASPI2SConfigure(void) j5 ^+ v; L* o* `* A9 ~
{! @' k, S `0 G+ T: y* Z8 `/ }- I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 U/ A, ]- a' O* ~5 |6 e* o& {7 U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! ]9 a: |" E8 t/ @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" N1 K5 _1 e3 U8 h3 wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& c' d2 ?% b+ E0 Y$ y& e9 R7 z7 @2 f qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% x# E* u& G( c( z
MCASP_RX_MODE_DMA);* u# k; F( \! a) w& |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- D1 c% x% i+ V! J! iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 I( F0 o% V6 B+ W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
h- U# }9 U W YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 U. l$ T: T% z2 I+ z. _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' r" s* [9 |0 M. FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* ?2 ^# u6 `0 a. GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 l" W n4 ?' _! u8 H6 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' h2 u- m o! D l! rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% f3 y9 i% P0 T% ?+ c
0x00, 0xFF); /* configure the clock for transmitter */1 F0 [. _9 C) P1 P" e: j2 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. o( q; H4 E$ ]1 ^# c+ u6 ^, NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 l; H" }. B* \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," h/ f: {% ?( P* a5 z
0x00, 0xFF);
: P' L; S/ ^9 |* Y
5 g% P- l, c8 I% p, D5 A/* Enable synchronization of RX and TX sections */
" E4 X# A8 Q5 }2 V2 |4 u+ G# zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- S3 _2 [3 S( {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ \7 q/ n3 `0 U3 W& B6 G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 X( s* \) o) @5 C+ v: X- b$ K Y
** Set the serializers, Currently only one serializer is set as2 q3 S! c& I! J
** transmitter and one serializer as receiver., q. I4 C1 K: _1 @4 [7 m
*/; h' f0 b% A* s) q. u: ~4 K* {9 S6 Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: ~7 K- V: s: z; t" A' M: UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% `# B" i. u: i5 Q$ B** Configure the McASP pins - ^- c6 L0 b+ h, C( f% {
** Input - Frame Sync, Clock and Serializer Rx* }) C" J0 b3 z- N0 U" }
** Output - Serializer Tx is connected to the input of the codec 6 U; A5 P3 w' e+ i- W
*/
6 \5 w) ]0 @; |( SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 y! h# `1 O+ t( ^+ e. C1 |+ ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 }7 Q* [8 }. Z" Y# O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. X# u# Q0 c+ k+ J H4 I| MCASP_PIN_ACLKX' J/ w @7 W# g& s3 W
| MCASP_PIN_AHCLKX! y: k0 @. p& i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" n/ Y5 M1 N8 E& @8 m0 i9 Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% D8 B5 l& c+ P| MCASP_TX_CLKFAIL 1 Y3 g3 U7 U% }7 N' G3 J/ l* Q7 T
| MCASP_TX_SYNCERROR/ Z: K5 ]2 Q9 C; _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 u- S& i. n0 v% r2 X- o: z! ?
| MCASP_RX_CLKFAIL
" I% _0 @+ A" A9 E2 q| MCASP_RX_SYNCERROR 2 g( h; s# f; [# N5 |) o2 T4 z
| MCASP_RX_OVERRUN);$ [2 _, X/ B7 A0 Q$ b' ~9 A3 i; N
} static void I2SDataTxRxActivate(void)
% x+ `7 d$ y5 V E6 |2 Z/ I{
4 P. ?; m9 Z" c4 Z/* Start the clocks *// w e, @ g: {; X! l5 o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 K$ v- B3 Y) l; E9 }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ c7 }; m& t; }8 @; `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. u/ N8 Y5 o( {8 bEDMA3_TRIG_MODE_EVENT);- m, r/ H1 g: J! ~. K! M3 x5 Q; \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 G/ {& }7 {+ r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. o- {" @8 j) y$ y5 b+ A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ `* K; e" B4 ^( _" C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 S# v7 q! |. c" T& B6 Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 H. R+ h: _+ VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, B. u) W# L+ X8 v- ^9 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& z1 U6 M. W( a1 t
}
( G1 r( i3 ^* e( V/ `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 W _, w6 v& y5 ^# f8 f
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