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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 k; B2 b0 y6 F2 G& c: m/ c% Q
input mcasp_ahclkx,+ w; z, M7 V0 [; V9 S1 E' K" k
input mcasp_aclkx,
& k- z+ U1 h: _ J! j+ Xinput axr0,
$ }7 ?5 G* y' H; t4 n1 A6 b, A) f, g. T" o. Z8 q. S
output mcasp_afsr,+ d- V' Z+ g7 f) @
output mcasp_ahclkr,
6 w! Q& Q% d% xoutput mcasp_aclkr,
% V7 y5 s8 ^7 l/ ? Toutput axr1,% s) ?( t: F8 \: L% ^8 b4 Y7 P
assign mcasp_afsr = mcasp_afsx;; y4 u1 m" S0 v. h# T: E' t
assign mcasp_aclkr = mcasp_aclkx;
8 b. t2 o, r5 aassign mcasp_ahclkr = mcasp_ahclkx;
5 a! ~3 w1 }% Rassign axr1 = axr0;
( z: |# h! W' P4 v( t. y
, x5 \( v4 H P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* K7 { V' Z$ ~8 d+ R1 dstatic void McASPI2SConfigure(void)4 n0 M' _6 u1 s+ x+ U( E9 F
{; ^8 d& P# P) m- [( a- Z/ h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 B& H! t" n- v9 F9 T! i1 qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 K3 v* ~, E9 ~) o% oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 b- J! R% Z/ N& V0 u: R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, k$ S: s' B4 Z+ D& k) Q, SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. \9 V) l5 b( H& Y. L$ _' B! t+ A
MCASP_RX_MODE_DMA);
4 W: u. l* Q2 {; zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- p0 w, b: u; }) iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& v& q/ h* Z& |! t- g* ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 C4 @+ o/ I, u& u* E4 Z7 p/ L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ k& w# I9 h: M4 a+ A+ V* W3 o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 M: q# [8 _, E% uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 Y S% e7 f/ M l4 C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ |+ z5 G x" ?( ^$ N" FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 L- M' E, I9 e/ nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 x v" ^9 }" v& Y
0x00, 0xFF); /* configure the clock for transmitter */* }4 O. v) m, f9 L; d, o3 E- V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# |' A' U0 H3 J6 m; w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & A/ s! `, H* t# y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 u6 V' G3 @) D3 e# d, i0x00, 0xFF);7 o( V" |9 H; w' Q
( t5 I5 J, @ R. _3 V/* Enable synchronization of RX and TX sections */
9 t/ @" c* }' f/ zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ x; r* t; v9 _1 E: O0 ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: F9 u5 ~! S& KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 ~2 O8 C" c0 C1 Z
** Set the serializers, Currently only one serializer is set as
2 U- ]' \6 M7 m$ I** transmitter and one serializer as receiver.
. z- T3 D% h6 e*/
1 G( A d& q6 X5 E( ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 |# ~# B3 j' u% b! rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ A8 _1 X1 j: t
** Configure the McASP pins
5 \9 v0 V0 t/ [" x- L4 U** Input - Frame Sync, Clock and Serializer Rx
1 {4 v$ l9 A! L- Z, \9 k# X** Output - Serializer Tx is connected to the input of the codec - P' ~' x6 F: Q8 o5 e
*/
9 z+ t, U( x$ b' y/ s& Y0 |3 p- q; YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* r% e5 ^, Z. B3 MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% q, `/ |- D& ?7 |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: p& M& T2 ]' X) ?6 z5 }# ?| MCASP_PIN_ACLKX
! a& d# P x1 o( z, z0 F/ a7 B% R| MCASP_PIN_AHCLKX" g4 H3 [) {% |* m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 s7 ?3 Z1 x a! sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 E. t! s$ [, w `& Q| MCASP_TX_CLKFAIL
, I0 Q7 Z, r7 Q" W0 V5 Q| MCASP_TX_SYNCERROR
. {# f: j2 d# j( {7 K5 V, Y4 g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; r- I+ T# J3 h
| MCASP_RX_CLKFAIL
, C1 u* j7 g, A/ k; P| MCASP_RX_SYNCERROR 8 E. H2 M; z$ K( z: `2 O
| MCASP_RX_OVERRUN);% O: C$ J4 _- n3 _
} static void I2SDataTxRxActivate(void)
- [& K) d9 h1 D7 z{
5 R: D: L% F' v" a* ?+ w# k; Z5 a/* Start the clocks */
7 ?& C9 I2 ~& YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 u0 n- ?2 j2 W; m/ L: qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 e* R$ S l# g1 I# n# {- `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
\" ^7 g. N/ B- |- U0 MEDMA3_TRIG_MODE_EVENT);* y( S- f6 }: f' c% N _# B# n3 b$ e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 U' H; H4 Q: f8 }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 B- f: x4 D# B( R9 p5 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 `) l9 x0 p8 r+ l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, e8 X" C6 U% ~2 n* }6 Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' S j5 _* h5 j8 x5 W$ i( O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 Y3 p( F. c+ H# O% V$ i# z8 jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 C( n7 q3 j; \. {( X/ W0 j
}
/ I7 X% s# \( O s' {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 S5 x I7 E% V. F6 W
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