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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" L' y* w! x+ I) L8 ?3 [/ Finput mcasp_ahclkx,5 s+ m# \' d0 q6 _
input mcasp_aclkx,
2 T; x# u8 c! E" D1 c* @9 z) Qinput axr0,
9 }8 p5 N% |' y H3 @: ?+ [1 _
1 b: F) V7 D- s Foutput mcasp_afsr,
% E6 V- w6 u1 W; koutput mcasp_ahclkr,: }- _( C$ V/ K: k- I: O. h
output mcasp_aclkr," m$ a$ i7 ^' N l- A8 y
output axr1,5 c2 @" F1 F2 M3 d
assign mcasp_afsr = mcasp_afsx;
- L- d3 s7 k5 B# J5 `' R$ Nassign mcasp_aclkr = mcasp_aclkx;- m$ d2 i) d# e# r" A3 o' G; b
assign mcasp_ahclkr = mcasp_ahclkx;
, j6 E* N# e, E* Rassign axr1 = axr0; $ b/ h. \: q9 G& M9 b2 r8 l) H
1 u$ g0 j4 x. r& b% h, l' g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! l* Q( g1 c0 f4 x' y' X
static void McASPI2SConfigure(void)
) P6 u: N6 x7 I6 P' ?8 @2 K2 e{
/ M# k) N0 ~: ]9 B+ @2 c" G1 i1 ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 z2 I. V2 b. U+ N' d9 w' k* j# j" [- n9 Q9 U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- T9 A8 k8 D; q" L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 y4 L( x+ R( q! d. T$ [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 Z+ K9 W! |) t* J. B( bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! S, B. U5 N9 m3 {. y) \" }
MCASP_RX_MODE_DMA);
) Q. g3 ~6 |. iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 x y. r v" uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" k' A# U4 D0 t5 @% z; n& l# nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 `: m; Z7 [) ^0 _5 R% }8 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- U* V* T8 o( @, e' s8 ?; \# J( K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% B, R5 `) D$ b! X# WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ Y g; z5 W7 x; j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 R0 R4 b& }2 ^5 g, J2 j* Z/ x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* U2 T+ `. ^; I/ M5 bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- T+ m% P7 o4 k$ r* u4 B0x00, 0xFF); /* configure the clock for transmitter */' v( g* D" R0 s3 e, w+ u, D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- \8 ^: }7 r7 j, AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 _3 Y- ]- B* c$ H" u3 r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) v) T5 Q+ F8 f6 q
0x00, 0xFF);4 S+ J- E/ c2 Z8 o$ t: h- B
6 k5 y3 _! \: w& C
/* Enable synchronization of RX and TX sections */
6 E! z# f% G9 f; LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: w, |' f, U4 s& A: a: yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
R6 \7 R! m0 f& r+ p; w# ^8 CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ t! ~9 G8 r& Y! N4 T% S1 Y J v2 o** Set the serializers, Currently only one serializer is set as4 s: w( _% C2 d8 D2 z
** transmitter and one serializer as receiver.
% \9 a, f( W& L: N*/
0 w( ]" W+ M' y5 W9 c' E' d _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* N9 p3 p8 U# U- _+ _- NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. O, O1 D& H) Z4 n/ D& `& C
** Configure the McASP pins 2 U9 y3 m0 n7 v% r1 z
** Input - Frame Sync, Clock and Serializer Rx
. u# A' ~& N) ^- L4 G) I. A& i** Output - Serializer Tx is connected to the input of the codec
. k8 b! z5 D+ Z9 {0 Z% I*/
# T1 j+ N1 @5 wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ q* e! F* n! A. M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 s( ^; |# V7 u8 i3 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, B4 T& y* @- j# b: c9 r2 l
| MCASP_PIN_ACLKX
) N6 m( F# ~9 i- ~/ v+ j" r2 `| MCASP_PIN_AHCLKX
! ^# E4 k$ @7 J4 B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: v# f3 N: q9 O/ }1 z/ n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 n% X# U3 c# Z$ U* ]
| MCASP_TX_CLKFAIL # t) S \! y3 `
| MCASP_TX_SYNCERROR
}* o. K' k4 d) e6 y3 ]3 h9 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( d1 { U( I9 J, r
| MCASP_RX_CLKFAIL# k5 o! P1 w1 `0 l
| MCASP_RX_SYNCERROR ) Z2 P/ a6 j6 f W2 [
| MCASP_RX_OVERRUN);
& I- e. d! Z, ^* t% w- [' C' S- N# B} static void I2SDataTxRxActivate(void): x0 v, p+ B, P# v2 y2 Y/ r
{
3 W% _2 X' ]. w* w/* Start the clocks */) t0 s5 n) [2 z( e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 P0 B6 N. ]: E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 ]/ F: {* `( g& CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- `/ G6 s3 p! D5 h ^. r" H+ oEDMA3_TRIG_MODE_EVENT);
/ r/ N. F4 i5 m( l% L- \: C7 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 o |6 s i% [% y5 Z0 r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ r5 m5 F0 H: n& y( K' q1 l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 b8 Z1 _% S9 { J9 B& HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 \ }5 j: ^6 X# N3 |+ J! v7 swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- [! @" d' l' S f. G0 _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) A( D. f/ e; t' N9 f: J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ C% S8 P: E- ]9 j. ^
}
, }0 M7 L$ W0 _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. h; x- _# S U- V$ }6 Q: k% M4 d
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