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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 _( p9 i0 B# Q! jinput mcasp_ahclkx,' w+ U- v' S/ V, e
input mcasp_aclkx,
% _; C+ D- @+ N- R" }0 |input axr0,4 a% Y8 J- {5 ~: m# g) n
) g3 Q( v$ J/ L2 h; Koutput mcasp_afsr,
7 c" l$ `- h9 W8 S, @- e. D! Xoutput mcasp_ahclkr,
" s7 l0 J. i$ c$ c% P3 d! V+ _output mcasp_aclkr,. Q R2 r7 e3 R6 o
output axr1,: Q1 ]* S; H4 ^
assign mcasp_afsr = mcasp_afsx;
* y, }0 R; E- ^; B5 R/ hassign mcasp_aclkr = mcasp_aclkx;
- }" a/ s9 } M' _4 Q/ cassign mcasp_ahclkr = mcasp_ahclkx;
, y0 B$ S% ~' Eassign axr1 = axr0; / R1 x4 J4 E! F" H" b0 M4 I
h; c4 `1 z( y' V* o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& \* S9 L" e9 q$ h0 o1 f9 F: s/ Mstatic void McASPI2SConfigure(void)! F: M W$ u! E
{
, ]4 Y& k# [- x( z$ l! l" C8 jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! ^7 n. R: S- |5 Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& i$ Q! V" g4 k2 [2 e6 LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* R- Q9 _9 b5 G2 Y% @% ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 d( V5 t* X, I) PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: p5 Q/ T. O* i6 n( S0 n
MCASP_RX_MODE_DMA);
% C/ W- a2 R* y% ~/ _# NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
s4 H* P# [% r, d% w YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- }! @7 Q- P, \0 f. B& c TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; j5 u- J" A& a) TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 a5 X5 a, Y* W7 I* F% d: XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& {+ I; H/ ?8 O# r) T0 e/ XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, ^4 M2 d2 ?8 z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( y e6 _' r9 y! b: M9 pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: k+ P1 r; q/ r$ t/ uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: H5 \( m7 M- I4 Q9 t0x00, 0xFF); /* configure the clock for transmitter */
' l' \; v! f& {$ \: zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 _1 p& g/ J# a$ s3 \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. {2 y7 c7 {# K/ m W' I# ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. A' @, R0 [0 V& E
0x00, 0xFF);
q% A H9 X/ x+ g$ A* E1 I0 `- F: W* {
/* Enable synchronization of RX and TX sections */ 0 f0 B* o, M* v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% l) N+ U. T; L/ s$ G* C! vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( P. u# V( s' d8 c1 t# f1 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** n& h) \, E% W9 R7 C4 z
** Set the serializers, Currently only one serializer is set as/ ]6 l* J$ G4 m9 k
** transmitter and one serializer as receiver.
/ l3 B2 K, N- U- }) u*/* f P Z; f$ n2 D# h( [- {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ k0 G7 w$ w) S, L! j- o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! n( f! f t/ q) }+ X2 f# P7 j
** Configure the McASP pins / A9 e4 `; B3 H, C# k
** Input - Frame Sync, Clock and Serializer Rx! w' e. u9 q* i/ g
** Output - Serializer Tx is connected to the input of the codec
) d' z$ ]+ w' `" t% W# m" T*/
: y6 ?7 s2 c& m( u3 g5 x' R3 C4 dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ U6 [% h- S) f& bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 L: E; J+ l0 v5 T- T; qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 r4 b7 f( [% p- \3 l' z l
| MCASP_PIN_ACLKX
% n/ h6 j4 `; d* O6 y8 f2 ]$ ]| MCASP_PIN_AHCLKX
8 O8 D: w7 j0 a, N( M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ _& F( Q3 s: E# |, S0 NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " d+ O$ z9 v6 V$ s; j. T1 [8 w9 C
| MCASP_TX_CLKFAIL
l2 [/ ?3 ]5 u( S/ r| MCASP_TX_SYNCERROR7 O$ M0 X/ b8 v0 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
f' b! A* t( w t7 g| MCASP_RX_CLKFAIL
* k; J( ?2 A* L: ~& m( Z| MCASP_RX_SYNCERROR
# E/ C. {, J* K% W3 z4 ^0 B| MCASP_RX_OVERRUN);
3 L0 e3 N( W h+ O0 W} static void I2SDataTxRxActivate(void)
% I# i( v' m6 _9 G. V+ v{% J" h' x$ ~$ p( H- ?& O* G
/* Start the clocks */
1 l6 {, U! z1 A4 C/ W; AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; L# q8 u1 h( L; w E; H; l$ ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 V) K; m/ A) Y6 s! p- L% H: o% v, KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 R* d- I3 E7 Y+ X F5 X
EDMA3_TRIG_MODE_EVENT);
4 }: ]6 C( j; J; Y) jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 a4 l) C n6 Y1 K$ v" {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" w4 \0 l% G0 m5 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, I3 ~9 M& s+ D3 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& p7 x) p) ]! `! ?9 {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 P$ n: E. s( r+ G) MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 u( v, x! v: v8 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; x7 S9 A/ p0 r s0 H3 j}
2 `; Y4 @/ P& w9 K* d+ G v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 w( V, i& w( G4 p
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