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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 @4 x( b1 Y0 k' f* ?
input mcasp_ahclkx,
H* ?" S0 Y/ E- V3 Cinput mcasp_aclkx, H1 x3 p( l# {7 Y
input axr0,3 f7 f' ^) j, M: O
0 {! s7 W* x( b
output mcasp_afsr,* u8 s9 A- w. K% L U3 X+ W# ^
output mcasp_ahclkr,
' j2 E( a$ }' v7 _7 ^. Foutput mcasp_aclkr,( S) V1 O$ o) z- V9 o6 n
output axr1,' X7 d9 ]" j8 o: }! i8 B9 X
assign mcasp_afsr = mcasp_afsx;! n' ^4 O: t6 F) g8 H
assign mcasp_aclkr = mcasp_aclkx;" }1 F: f& i( O2 J. R
assign mcasp_ahclkr = mcasp_ahclkx;* [8 X/ l( A) g0 X% ]
assign axr1 = axr0; ( L7 B7 Y# k* T' L% e. Y% r
& h$ v. K4 V" F3 q% i- S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 [0 _2 Z, p" |1 y9 F0 _
static void McASPI2SConfigure(void)' J6 E6 \: l; B6 q
{" i, P9 d" Q& I; {1 {6 H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
\5 s& L! e6 \5 h0 x' k }# x5 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 K4 m+ W% @" a# q* E2 H! T% J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 C2 _4 ^: D: f' F/ J: \4 lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: G6 o8 w6 K5 s: P0 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 B. d) T+ b: ]7 j, E* F% Q
MCASP_RX_MODE_DMA);
; W3 x5 U8 G& g2 qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: I. ^- A' W! q( f+ p/ S; u+ U' F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 E" }' ^4 i( w- b& G1 HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 n P# R$ L+ [- s7 EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 ]1 A- \+ x8 t' D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 t0 {9 H& u8 e+ ]' }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# N6 I; _6 U0 z% q# r$ ?) ~" QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ I5 k9 l" C( N& V, m' q4 jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 }6 g0 M' s+ R! ^8 ]9 b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
H/ @. M* P4 e! D0x00, 0xFF); /* configure the clock for transmitter */- m* P+ t$ O0 p; D$ K5 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 b6 @$ B2 ~" zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) L& B/ g! t8 a) n: B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 N5 {6 Z; }2 P. i! o$ J
0x00, 0xFF);7 j& ^( f+ z2 j; F
6 g1 @# Y+ T" J
/* Enable synchronization of RX and TX sections */
+ U m2 q2 q$ N5 ?4 TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 u' C& j2 }$ P( Y0 G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 I! Y4 b0 ]% [. u3 t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: ]" F2 W# @4 I/ y/ c5 y** Set the serializers, Currently only one serializer is set as& i/ U2 \1 \6 O3 `3 Y3 n) e! e
** transmitter and one serializer as receiver.
; }0 c8 B+ u. |' J4 b1 [( Z8 v$ ?*/- C* B0 W3 C6 S" [ z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: n+ a' s/ W R3 P7 m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- @' O% [; y/ L5 n7 d
** Configure the McASP pins
; N& q" z( A- g! Q$ |** Input - Frame Sync, Clock and Serializer Rx0 m; ~3 C/ }0 C/ e0 P) n! ]' n
** Output - Serializer Tx is connected to the input of the codec 2 G1 u( J4 D7 n5 P5 f1 t
*/
2 F/ a+ ?, T4 M: lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; P4 A' j! z* k0 |/ u* x2 w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 | a1 L5 ?" t1 cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& {. k' j% W/ c( G| MCASP_PIN_ACLKX
1 p3 S' N# d/ Z" { N+ M. y| MCASP_PIN_AHCLKX4 K ?/ w) q5 O& C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& e& j6 O+ E+ o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* a0 D7 _6 o+ a5 T| MCASP_TX_CLKFAIL
0 h2 V5 x# G- k& H$ Q| MCASP_TX_SYNCERROR
) [, L/ Y$ D# K, g7 u i: I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * C+ F t. P4 D2 o4 g5 c2 z
| MCASP_RX_CLKFAIL
* G8 C; ]* |+ x" K| MCASP_RX_SYNCERROR " l+ b# O. w, _
| MCASP_RX_OVERRUN);
5 J2 B, _' `9 k" O} static void I2SDataTxRxActivate(void)0 } Z" h. d, q. A5 A
{# h( H/ D% {! _0 c7 Z( w
/* Start the clocks */
* t8 Q' H7 O' q7 V* bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. F# L* i2 ~, n" w) w4 AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, V$ I$ M+ g& I& n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 e, `3 i* a/ x" ~8 o* X' cEDMA3_TRIG_MODE_EVENT);
4 G9 r2 y, K4 o! G) sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 D7 E6 f: F. x4 i; c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) k5 N/ f, z3 r$ ~; V" P. N/ @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 ^4 O$ Q- i3 \4 L* g6 ?1 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 @$ Q$ i; H7 R2 v$ Y$ O/ rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
x8 `7 Z. ^' ?0 X7 S; H0 A6 ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 M7 O w+ Y5 E0 n! o E8 X0 d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 x: l5 F9 Z3 {0 J. p4 ~6 M
} , Z$ v$ q/ p7 A7 x) e' ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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