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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, L0 u' _& Y- Q( W. tinput mcasp_ahclkx,0 `8 H% P( R& p' `0 A* }( l3 V
input mcasp_aclkx,% J% v: X3 E& C- w; s2 Y% ^
input axr0,
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! A9 t( u( \1 f0 C' o( \output mcasp_afsr,
' t4 C4 ^ _! l3 E* N$ doutput mcasp_ahclkr,
; F5 p( a6 v Coutput mcasp_aclkr,
( V& z, Z- [* ?3 k) houtput axr1,
1 a8 S9 D: u0 k- ]* n assign mcasp_afsr = mcasp_afsx;
9 U8 ]: l; u; P2 I% j# W+ Cassign mcasp_aclkr = mcasp_aclkx;0 d" X; Q+ g: u2 D' Q N$ R s
assign mcasp_ahclkr = mcasp_ahclkx;
# l' \+ a4 L3 M: Yassign axr1 = axr0;
8 C7 ~# h" j( u5 D' o1 E" z5 G
: G7 e* y. {2 k3 {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 [* h `& I! f; x9 Q
static void McASPI2SConfigure(void)
# e E$ j) t6 o7 m* ]6 E{
9 B$ E" @& C7 d+ H4 W! cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* Q/ @9 m* V9 T$ B: f. t7 }% }) G9 v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 N8 S+ `+ P9 \* e1 g C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ M# X$ ]+ [+ m- U0 U+ m7 Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 B0 A0 B( p0 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' L. O1 t% i* E9 L) {# u$ Y+ fMCASP_RX_MODE_DMA);9 S: N1 Z: K6 G5 g3 F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; ^5 g9 A3 s# y- v" s/ `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# |) U; T, r. B( T. f, }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, \# G# N6 J$ SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* c' @3 i0 U/ P( H+ q+ p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; M$ |# L7 r* @, {! n3 e& z- B2 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- A. [) B5 q& c/ f+ J" L+ u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 [2 k& [) @4 X) L1 r4 p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 @) V$ Q' D/ H2 S3 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 q! b+ O& J' E! ^* b" F: H
0x00, 0xFF); /* configure the clock for transmitter */
F9 I, O7 n9 bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ Q) e9 \" U. t" S( o# F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % M5 |' M7 e$ D c" m7 x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ a/ @ B7 R! N; ~+ t' m8 S0x00, 0xFF);3 m) t& Q! P5 G' t1 G& w9 e
+ g" K0 A' L& h! L% z/* Enable synchronization of RX and TX sections */ ; x1 _1 T4 k/ J' @0 B3 P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# Y# }/ c, Y- k4 P f- A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 n$ R; y$ J2 z N1 s0 S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* W# C% g c8 f
** Set the serializers, Currently only one serializer is set as: T+ _. W* p9 k4 i% K0 }
** transmitter and one serializer as receiver.
$ M3 E: \: s0 W# {" W9 ~. M! V' h6 a*/
1 N, k' e+ s& W/ Z3 q; x$ KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ r2 Y. _/ o& e/ n4 cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 g: {; K6 Y1 k6 u) b6 b
** Configure the McASP pins
0 ~) q8 w8 c7 K9 _** Input - Frame Sync, Clock and Serializer Rx- h) \8 K- _; p; T3 x: X
** Output - Serializer Tx is connected to the input of the codec
1 ^* C: D6 Z2 F: Z1 g*/
$ ]- G4 V! d0 v5 E% ?- GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ k2 Q( U9 E, `0 p0 N0 C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: I, w* O9 e U( D t6 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 L Q8 y5 U+ x3 M- P! L" z6 i| MCASP_PIN_ACLKX
4 I. `4 g+ K m# ]| MCASP_PIN_AHCLKX' h8 T3 g8 ~" `3 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& M- ^/ U7 G% j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( X5 E) m* e0 \5 _7 `| MCASP_TX_CLKFAIL
3 E3 a/ k3 J0 u& |5 q7 w B| MCASP_TX_SYNCERROR2 y- s; I. F* B7 X! J: ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 i- [# a3 n+ E2 M: G0 N| MCASP_RX_CLKFAIL3 t% M/ y6 g' q1 ]! O" D6 n/ a) U% T
| MCASP_RX_SYNCERROR
" U) d" ~6 n; m5 y) V| MCASP_RX_OVERRUN);
2 p4 p6 ?' }" A0 v3 }} static void I2SDataTxRxActivate(void)9 x* O. z( S ^( |: h( k
{. {8 K4 T8 F6 t
/* Start the clocks */3 J9 r% k0 W* D" U( j8 k0 e8 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* k y8 v: O: jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, l$ E o' p" ?0 Z; T% H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 q8 M; z% u" j* b4 i
EDMA3_TRIG_MODE_EVENT);
, n7 A4 O6 M5 B4 e( [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! H, H3 _ W+ Q* V, C0 S0 A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' L; `; O& C9 ^6 o! @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: u/ f* p) a+ B; X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' C( k) S9 H( O5 Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 r7 `) \ i/ X& _% h. O1 \1 R5 s; _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, O& U9 A% k5 i) r3 F3 s; u1 a6 g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, [" I/ _+ E% I. q: Z0 R/ \4 k}
8 `2 I) P2 O: N- D' k1 k7 B; h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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