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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" w8 O% k7 h* ~, N. E* j8 [& g; ?input mcasp_ahclkx,# r: G) X0 p0 \0 |
input mcasp_aclkx,
5 K _; r' J/ B1 N, m; p2 zinput axr0,
( Y6 ?+ C* ]" @9 K" f0 @' w; B6 E) A* J
output mcasp_afsr,
F' U' e, c& A" y4 woutput mcasp_ahclkr,
9 G+ @8 G. h# I8 W, U toutput mcasp_aclkr,
2 q5 C& M+ l. C* e% F; V. goutput axr1,
# S' B! ^3 `4 {" d assign mcasp_afsr = mcasp_afsx;% _( z+ k: _7 @. z) R6 @
assign mcasp_aclkr = mcasp_aclkx;1 `7 r5 B2 ^; ?( {
assign mcasp_ahclkr = mcasp_ahclkx;- [6 c/ v, S* y$ |7 u/ {$ U8 M
assign axr1 = axr0;
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" v: z2 j1 b# v; [! E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' t# a# F2 b' P! h5 y- w, [( v, ^
static void McASPI2SConfigure(void)0 V+ z" S. h% Y& h$ w% C6 H9 A( R
{+ P! M5 J: y- a" |* U: U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) W, I& p0 K/ f& O6 o" x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 ]- C* j4 F. O: {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ Z; E; ^& i3 U k& qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// o! d/ s; t% \$ ?) z$ ]& G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 M7 I8 B2 I1 @- m0 D) jMCASP_RX_MODE_DMA);
i( f4 l! F# M2 EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# ?6 _0 @/ u, x& ^& B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( B8 { c* h; l8 L2 I- ]6 J% |! }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 V( _" {$ `3 A* ^+ r- p+ t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" h, l3 h: j5 s6 n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 ]0 }) B+ m8 WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ E7 B/ i( c" L+ i. D8 r; \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, v4 ^) A# d6 q1 o4 i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* f+ ]/ W( T) i: |+ L- C9 P" U, KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 p0 u& T1 N+ P, X0x00, 0xFF); /* configure the clock for transmitter */, X3 Y1 g7 s/ ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ B. M3 k( S% s) ^2 b4 ^. p, P; ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) K/ }! l4 g9 o h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& l3 p0 G# ]+ n* ^$ a
0x00, 0xFF);
: x8 ?! q$ F5 e1 D1 \. p* z& O. w' ?! M$ j: y( y- ?) b
/* Enable synchronization of RX and TX sections */ 4 a% y% T# j" k F/ Z3 H, i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 e0 n o- }4 n; u7 N& B: c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 y c l! W% N/ QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ \2 y: P$ n3 B6 Z$ I** Set the serializers, Currently only one serializer is set as
) k+ T% F: b+ K* E/ x6 M2 s" t** transmitter and one serializer as receiver.
1 U8 x! \2 M) k) ]- ^* ]$ r( g- x! v*/$ v% P# D5 \- {* |, L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); b) k7 U2 X* e# l% u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 G+ G* M0 J5 w0 j
** Configure the McASP pins 9 f; i! P, m4 J3 t5 A5 \3 o
** Input - Frame Sync, Clock and Serializer Rx
8 s) d9 L, G. Y# K, L0 m** Output - Serializer Tx is connected to the input of the codec
/ b& O2 {3 {* S. J6 R) [$ E9 P*/
4 ?$ x W% ]8 |/ u7 ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. f+ {7 ], f( ]) N/ b( Y) \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; w/ d' I, I0 [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 \) c+ M q _% N2 ]3 g& T' ]
| MCASP_PIN_ACLKX4 c, U; @: m' N& i: e7 _4 f. F0 ]7 K9 s
| MCASP_PIN_AHCLKX4 T# T! n! Y1 N7 M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 J$ |/ h( r. O/ AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & @2 u0 f, \6 I! o( f
| MCASP_TX_CLKFAIL ) r1 ?1 v% [5 p' K
| MCASP_TX_SYNCERROR7 l: w# O# ^9 c1 p K3 m$ r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 |5 ?4 ^/ p8 e1 F, o| MCASP_RX_CLKFAIL
1 H- N/ r3 ~5 _- l$ b| MCASP_RX_SYNCERROR
`9 m* N9 l, f: r: p0 a) E| MCASP_RX_OVERRUN);
6 P0 A% B5 G5 u0 o! O, [. @7 ^7 R} static void I2SDataTxRxActivate(void): s! T+ f. }- D5 J
{
4 u8 K2 M& w. E8 Z& c: Y% X/* Start the clocks */, O( S+ ^1 L6 `4 c7 u0 t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); B$ T8 G/ J, G( e- d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 d5 g% H, J+ o6 O. T. m# b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) C: z. b8 x) l; j1 g; w8 tEDMA3_TRIG_MODE_EVENT);
- ^6 F$ _" d+ C5 N* T& T0 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 } V" u x8 X8 ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# @+ C& {9 ~' N3 M, N5 GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" m7 g# e+ m! S. B& A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ z! Y* R/ N' @ e( B5 jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ s7 O" P' G3 h! |, R- [# r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 P+ S6 R5 a0 S$ x, E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 ?3 S0 u) y" k! j) _. M+ a
}
( [" }, z2 r3 ^' e' c' C. @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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