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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 q+ @ n& o+ D5 {* @; U. k/ U. einput mcasp_ahclkx,
0 ~9 v/ M, r; sinput mcasp_aclkx,
4 ~5 A% c( a) r2 f+ rinput axr0,
4 S" J% }$ b# }6 w! A' S! T/ z0 a( I3 c
output mcasp_afsr," [% N. ^8 [) [) P: c
output mcasp_ahclkr,
, W M" Q; T0 C" }' @output mcasp_aclkr,* q- {7 u2 j% N" m5 F
output axr1,
0 M6 Q/ ]& C3 w% }* L" a" l, _ assign mcasp_afsr = mcasp_afsx;4 k$ t& C3 e2 {9 U
assign mcasp_aclkr = mcasp_aclkx;
- ~- C @) }5 ?# d% e, _/ eassign mcasp_ahclkr = mcasp_ahclkx;
1 Q @. r, {- M# \1 H) uassign axr1 = axr0; # S/ n' o9 l6 @0 U
& a- ?) k D& X9 K- D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ }* _" T; k. O# Wstatic void McASPI2SConfigure(void)
1 }$ _: W/ E* M* J7 J3 K{
1 u* z! f6 {. ]7 AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# _. u' x9 U" A5 a/ S) F4 ]0 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# ]+ W. T3 S, fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: P* X% _% p- h9 S; P8 e! W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- g6 ^( J* ^/ D# `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
~! ^. s. |1 S. {1 y0 RMCASP_RX_MODE_DMA);
- b# P% G9 c! u$ G W+ a* FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% w/ I& S8 h# K- f8 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 r6 Q4 B' P) M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 h) p7 B; `( A4 a! [( u0 MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 t7 h! e1 P" f U q5 A/ u" `. s+ sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, F4 ]+ t o1 Y+ _4 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( d+ t$ s$ }( F! c3 g V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, X: C1 a& @4 g; w" f& f: vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 v3 ]" S( p O3 `; _* v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 c) M. s' s6 T" {. n7 s0x00, 0xFF); /* configure the clock for transmitter */* s( J/ [! w: \0 \7 c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 @ v: Z! O9 x/ y3 l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 T# F- c' H) r/ G9 K# z9 p! d. W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, U) R& k* L# Z7 Z4 v
0x00, 0xFF);
% o# [5 n" L5 H; n$ A8 E3 [$ t' u# v, o* Q u6 `0 S
/* Enable synchronization of RX and TX sections */ ' g" R; K, n- [ m3 c' Y$ P5 J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) v4 b, V/ n3 Y3 |, h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 m8 W/ d- M7 }* o1 a3 D! O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! c6 }" f' Y: H ?( u3 A5 G
** Set the serializers, Currently only one serializer is set as8 J) Q' M$ L2 j, K7 C" Z
** transmitter and one serializer as receiver.
& _+ T! V$ i7 y0 t: S' W4 C*/- J; K) @$ j( }( a2 e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 l2 O3 z' ]: ~6 a! U" e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& ?! n. g/ `$ U4 Q7 s) R8 W' \
** Configure the McASP pins
v. {8 A+ G7 j; t: ]5 \5 a5 q' b4 ]** Input - Frame Sync, Clock and Serializer Rx
6 J, e8 P, V) p$ u) ?1 b** Output - Serializer Tx is connected to the input of the codec
% j4 K) |& M) A2 f*/5 I% F: x" Y2 O0 U' N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ k1 [ U$ A: k* _5 O: _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 w9 B! r: F+ b- kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% ^/ ], e& \4 i
| MCASP_PIN_ACLKX
4 f" X! S2 @( l7 p. ]. r| MCASP_PIN_AHCLKX' O& X8 V( p7 M, \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 j8 J& x8 K- `7 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # Z' n* H+ w8 i; \) `& [8 }
| MCASP_TX_CLKFAIL 0 i5 W6 J4 e* R% t$ v' n
| MCASP_TX_SYNCERROR
( m) G9 b" Q- ^8 ]5 D _. W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
`( @; Z# B8 _3 U| MCASP_RX_CLKFAIL {5 x5 Q n3 [% u# N; K
| MCASP_RX_SYNCERROR
2 s# u! @" q- K| MCASP_RX_OVERRUN);6 m) f. o2 z: Y* {7 L# J
} static void I2SDataTxRxActivate(void)
8 u |- W6 i. G* z{8 t) X- t6 m% ^2 M
/* Start the clocks */
* O9 @# \) _- j" z2 U ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. k0 x2 a w& O8 q) j/ p. ]1 ]7 t8 NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 G+ D$ w$ Q V' NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 L: S: Y7 P9 k, n3 `; D |. s; c9 i2 fEDMA3_TRIG_MODE_EVENT);
6 N5 r/ [8 P$ Q6 O/ EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # n# k, i Y7 \5 b; D4 c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ [8 J$ T6 y. Z8 u6 l" H$ BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' M1 ^9 h E) P" p. A' k: IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% R$ a2 |& |1 F3 W/ S/ T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! A ? y9 M U9 a' `# v( S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' U' a! k! I4 O2 mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 u& y% F0 _, A( b/ a
} 7 X7 ^$ u5 c( K: d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & P6 t- V6 z ]* t& o) v
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