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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: G$ `6 V' {3 o- Q
input mcasp_ahclkx,
6 |! D/ z0 g- h+ ~* p- hinput mcasp_aclkx,' B( d$ i6 f: D3 }7 }* r2 d- i; I
input axr0,
2 C5 y( v; O' v, g. Z5 G3 s; _7 Y
" ?6 M: s8 a, noutput mcasp_afsr,0 e: B# c1 I) k
output mcasp_ahclkr,9 B g! E2 C7 d x
output mcasp_aclkr,7 n& i" b/ v4 H/ t0 H# o) ]
output axr1,
& o9 e' v7 Y; w8 `- T assign mcasp_afsr = mcasp_afsx;
- M. @: _" C3 Zassign mcasp_aclkr = mcasp_aclkx;. S+ A6 @3 X ~4 _
assign mcasp_ahclkr = mcasp_ahclkx;$ e3 x, V$ ?4 j T: e& ^9 N4 |
assign axr1 = axr0;
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3 F( o% _7 l+ c3 q! z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, \4 A, |8 T3 {! r8 Bstatic void McASPI2SConfigure(void)
5 A* t, j6 G0 e ` S. Y{
- x# Q2 W+ \1 n4 m3 RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* Q. [" z& c2 b3 g% e8 b/ M& t) a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- R+ R, I* a v% P/ Y2 o" |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) X5 U- u: u1 ]/ U5 BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* R( j' Q- W, A( b- _# M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 m; T5 v- g0 V' YMCASP_RX_MODE_DMA);
9 M) I% y( e5 q# n/ rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 \7 _% T; k Z7 @& H. y; D5 HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& l% D6 `9 u) g( M8 w$ c) h, ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 K" T- C+ }3 k' ~, R, WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ M4 y6 X: g% H: \5 q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; |3 X- C7 D8 ^( n$ g: r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ t9 _& ]7 _( t- IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: V: Y. V' s, Y& HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 Y6 K2 u2 x- f; o2 r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 T8 q7 Z" L7 f( u9 [
0x00, 0xFF); /* configure the clock for transmitter */
/ }+ H& I/ a) v3 F0 w( eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ {" k/ _# N! C! U3 @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
^) W. S8 U# `3 i, u: P* _$ sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% u7 V1 j: Z( ?6 _0 F: w5 `0x00, 0xFF);
4 E, L0 m2 u! R/ k$ U" A5 r6 P r
, c9 Z& B% D# N1 ~ k0 |/* Enable synchronization of RX and TX sections */ . r* z! j9 ~* K/ u" l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 t8 I& z0 F" A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) L) Z' g% @ q) A1 D' j1 X1 jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* L R" C: w- G6 s** Set the serializers, Currently only one serializer is set as( i% D; E% g- O0 u& J3 [0 E3 T
** transmitter and one serializer as receiver.( I; D: z' I- S' b
*/
* |' N: x% K( J. n: q; wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# W! R' y# n6 h. ~ xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 ], y7 T, x; Y. M** Configure the McASP pins 8 {$ X% h8 @1 U
** Input - Frame Sync, Clock and Serializer Rx
0 q* `6 k8 t( d, A6 ?** Output - Serializer Tx is connected to the input of the codec : u% @, l7 C- V8 j `% H$ u
*/
1 A8 M: T; X! L% t4 O8 OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% @* \+ k1 v3 W: S# o; Z8 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 y! t8 O! V; b: Z8 W, @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ h8 x4 f* E, W7 w
| MCASP_PIN_ACLKX
. {. U& v% p7 X' G" y: a, y| MCASP_PIN_AHCLKX: ?- F+ \* ]# _+ E0 w S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 {6 {7 [& k" X& l; M6 D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % z, E& U; `; g7 @0 H1 W9 M- B' j
| MCASP_TX_CLKFAIL ; \: C o: x* H
| MCASP_TX_SYNCERROR% z5 h8 L+ w3 \/ _- i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 B4 J7 e; U/ T$ T| MCASP_RX_CLKFAIL9 Q6 P* ^1 P' l3 ^% e6 [. _' u2 }
| MCASP_RX_SYNCERROR
3 n( |8 J2 ?% L" T( f| MCASP_RX_OVERRUN);
3 C& R" d& @3 X8 T' O} static void I2SDataTxRxActivate(void)' M$ t$ u; b0 ^
{
+ d3 x5 m2 s. `3 L( I3 W" R5 G1 @/* Start the clocks */% o. ], @6 p) ]/ n, x, C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( \/ l5 X* w) _" T. Q0 @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* A+ _: i" ]+ N+ C, Q4 {! A6 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* H( h& {- w3 ?- B' O1 p$ QEDMA3_TRIG_MODE_EVENT);
8 W# w+ ~* L, F* iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , W& j& e* A1 D7 f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 k1 J# S! n/ e7 V. R# ?) `, dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 X }5 f! l4 E2 B/ A4 a) }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) `7 P9 Y7 W& ]. L, D: Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 H' }& a: ~$ f+ j- i) ^1 vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 a! S% L- k+ A9 sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 v6 V a- E1 r/ D} 3 m9 R! q+ c5 h) s0 ]3 U, G+ ]# ?0 B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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