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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 S$ I% @7 s9 n# `+ o: p) u, Ginput mcasp_ahclkx,2 g& G8 Q/ d; U) u$ k
input mcasp_aclkx,
/ L; k, Z8 t- `( C! M8 Ainput axr0,) I7 _* b1 N( D9 u3 m
7 g9 t( I+ \+ m2 u& N! y8 l- M/ Xoutput mcasp_afsr,' i/ M4 Q+ E' o
output mcasp_ahclkr,
) Z# R$ ~. m& Aoutput mcasp_aclkr,% a2 w; k1 g8 x
output axr1,
! t% i( b/ z+ P/ I7 k assign mcasp_afsr = mcasp_afsx;
. I2 T+ ?. w9 m2 D" g; A) aassign mcasp_aclkr = mcasp_aclkx;
6 I0 K. G1 h5 Fassign mcasp_ahclkr = mcasp_ahclkx;5 \/ C& o3 _' ^6 [( E: X0 e
assign axr1 = axr0; / S! B: K) d0 F/ M) ~ n5 `
" W0 G2 l; M, j/ u+ q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! k L+ U4 B/ i% W( Cstatic void McASPI2SConfigure(void), T- p H) D k5 w9 y1 v- e
{3 B- p# |! h; v+ u/ j% N1 v
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 P" o/ k2 R& ?/ E2 IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 X' \8 d( }4 d# v1 k8 R8 {# B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# E! I3 p* {% L0 ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' b/ K( r1 m! n) [& l; H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; Y* N4 I F% u1 [, p+ _, u
MCASP_RX_MODE_DMA);
7 h4 W* @0 T* C# k% H1 e4 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 a# B: {4 }2 W- Y+ I. D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 G' E: z, \( qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / Q5 a& n+ j2 w0 i6 o. J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" G- ] o8 `& K2 @4 n9 b! eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : G+ k0 r* |3 Q4 N8 U* w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' k" ?, P' d1 b: O3 }: n" CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. x5 u, H/ \4 E8 U1 U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # D3 a* }& ]' g7 G" Q7 O; T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ [9 L- A9 [9 y, D
0x00, 0xFF); /* configure the clock for transmitter */
& A" _4 D* n) S jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 j& K; @5 U1 V3 JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 O6 W+ r7 e9 c7 Y' p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ H3 Y. ~8 z' ]% q3 a, z* W$ o0x00, 0xFF);
$ j3 ], h- x E9 |) v" a; x* P& ], Y) }+ q" E
/* Enable synchronization of RX and TX sections */
6 @& V- o9 y' v& EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( S! c; T4 }2 i D& @5 J7 T8 J. `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& U5 J* c/ t$ e" }: }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; G' W. K+ `5 t
** Set the serializers, Currently only one serializer is set as
9 T3 @% h: C% G4 X; q q2 S9 F** transmitter and one serializer as receiver.
3 M' ?( i# q0 Y. R& A0 x3 |*/- D) n- K' v' a4 ?1 g7 _) N; @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' K8 O. |& ?, `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. h/ A! h# l2 b, B C2 x1 |+ T
** Configure the McASP pins
7 P5 O4 Q' K, N** Input - Frame Sync, Clock and Serializer Rx" V( N1 H) u& N' V0 b
** Output - Serializer Tx is connected to the input of the codec 7 s* I, F5 i5 A9 M
*// N4 {9 o X/ i* H ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 M. M. T/ [% J( ?- TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; [6 a0 S2 q# x- D4 _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' {! D% J( z$ J| MCASP_PIN_ACLKX
& q0 @0 B' w; j a8 n3 X# I| MCASP_PIN_AHCLKX
; F/ U* r. w% f8 {& u" v+ x% R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 h$ l3 ^. A. H A3 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + F9 F3 a0 D) N2 r j# o
| MCASP_TX_CLKFAIL 1 I4 b" r7 w& D7 R, l d$ f! H
| MCASP_TX_SYNCERROR- T- s1 h1 l: Y. C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & `2 H1 g# x) R& M
| MCASP_RX_CLKFAIL
% U6 Y% V2 s; N) I- L| MCASP_RX_SYNCERROR ; Z+ [, b! f" w5 L$ ~
| MCASP_RX_OVERRUN);1 ~; M [& v/ b! r( B" x
} static void I2SDataTxRxActivate(void)1 `; K& D' ^6 u6 ?: B
{
' _6 n) N& K& V/* Start the clocks */
6 p1 p$ N( I9 Y d% j2 L1 DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 z' L3 Q! g' T- Y6 I1 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. T! c2 k% J( P- \' t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 W( ]& s6 }+ R! ]6 G) I/ _. j# ]
EDMA3_TRIG_MODE_EVENT);
4 s3 k8 ^0 \+ ]" }7 _" eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 Z1 ~' b% L4 }( l' q/ Y+ J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% G* `- H/ A$ I' m$ M) O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 m3 {0 P: f$ G/ z8 @9 q0 \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 s4 a2 _+ K+ v- C( ]3 m" V6 u# M* n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 d# j+ c1 X7 L' bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 {4 S4 v! |" J I) T6 EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 _8 h) f( S8 y1 m$ o4 o1 K
}
2 d8 {1 f. Z$ d7 k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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