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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! _$ q. x8 H6 {7 `" n1 J/ y+ Vinput mcasp_ahclkx,6 f- d" u, h& x7 j6 _( Y
input mcasp_aclkx,
/ Z- N* ]3 u; h) K% D; U4 [" linput axr0,1 V! S. L+ @8 U4 Q4 ?% U
4 |3 d, j/ M4 C2 E$ }4 s
output mcasp_afsr,
8 R2 d3 k+ u4 M; Uoutput mcasp_ahclkr,
& F: j! r8 j! L" i3 q& g1 H& [output mcasp_aclkr,
, J) {& v7 Q0 M# l5 }$ o8 Ooutput axr1,
& @( M4 k; w4 b assign mcasp_afsr = mcasp_afsx;
, ?! C6 e3 U+ c; J+ cassign mcasp_aclkr = mcasp_aclkx; u8 n9 T+ o" s" V& F3 W
assign mcasp_ahclkr = mcasp_ahclkx;
& ^4 c9 A3 m; V! Eassign axr1 = axr0;
: O# l& v% ?) c: |1 J$ n. R; a, r# E& U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : D( m5 Y8 G! ?4 V" w
static void McASPI2SConfigure(void), @! z; \7 K$ }/ n' F4 p# `" C; x
{
0 D' K `' P9 ~1 u+ BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 I5 M, b$ k* U1 m3 c; {5 ~, _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ G1 a U0 \! b# ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; [8 @7 n- {: h7 @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# Z; i9 v, V" a: xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 W# l* n( R$ P. o1 {MCASP_RX_MODE_DMA);
6 r5 N v/ C4 V! `% c7 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 E& |2 u" d0 `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
u6 K8 _, l4 T$ cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" ]) l1 p. s7 E# E8 s8 oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" A$ K1 }8 s6 ?5 nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , ^) k9 Q4 B8 n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 Q* x& ]5 t3 {* Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, v: @) |* E" m* T/ N9 t& U4 AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 i a8 U$ {' c" C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# L# q+ j# w& @+ N& k) Y0x00, 0xFF); /* configure the clock for transmitter */6 N' B5 N1 a3 [3 f5 }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
~& E+ {; v2 `" L6 KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. {; z3 A7 S9 q& o+ rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: k t& n* _6 v' ?0x00, 0xFF);
4 k" _# W+ U$ Z, {) c
! s( z; D; z2 R5 `! D/* Enable synchronization of RX and TX sections */
% K* _( r6 ~, f/ TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" J1 o7 e' V/ h% g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 x. C1 b3 w4 Q* a; IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 r$ }7 g( E3 F& G) v$ r: \, h$ {** Set the serializers, Currently only one serializer is set as/ x9 }1 s8 H' N: d0 c
** transmitter and one serializer as receiver.
% p8 m! K9 k8 F3 A*/$ P4 X& N2 T9 n% e1 E; D+ W* W( b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: P' L5 f3 \! ?8 n1 i& \! e9 x+ gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 g8 H( P2 y% N2 P; O" S** Configure the McASP pins
1 k) ^. P6 _! y! e" G5 U) P: p0 M** Input - Frame Sync, Clock and Serializer Rx
) x4 I$ h% k" e! z# \% f P** Output - Serializer Tx is connected to the input of the codec
. B O& E/ G! u- A*/) A$ L1 a% @/ {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 ?* S8 H/ _9 u9 H, U) Z- vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 ^8 U( s/ z' Q& |: i! F) \9 BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 N9 d# |1 a2 | k9 t| MCASP_PIN_ACLKX4 y$ S% y; L' E4 b8 @
| MCASP_PIN_AHCLKX
& d7 B, h2 [( D* \# S7 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 {5 v- w% R9 K. eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, y7 L8 M; z; S6 E+ f| MCASP_TX_CLKFAIL 3 b5 T8 w! N9 G) i: x
| MCASP_TX_SYNCERROR
: L8 l+ a& r& ], \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 W. a% F/ p' h6 X5 \0 p| MCASP_RX_CLKFAIL
7 [5 [1 @$ y e4 z; b| MCASP_RX_SYNCERROR 9 F" r- v, L; N W9 k3 x% F
| MCASP_RX_OVERRUN);
. ?' N9 X" ~" T( G} static void I2SDataTxRxActivate(void)
0 I n& ]: `2 ?0 L. B9 n: Z6 _# m+ |{( I6 O$ n+ A0 i3 C
/* Start the clocks */
" c7 B6 p" v9 qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( e) L" k& s) P- AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* K' l& e1 u* P1 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% h1 E9 {5 G* e v4 i
EDMA3_TRIG_MODE_EVENT);
; A2 i9 m& h% z; ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( g7 g" L$ d, C( C0 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 s) k2 M, S y1 }/ |- L* aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) p' \( G- h; M7 N0 K1 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 y: \) j7 p0 H6 l/ C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 X- R8 p8 c, p0 d6 J8 _" ^% Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 X$ @5 i$ s6 a6 z; } L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" C H+ c/ T. O: O3 X% b! R5 S}
: X3 ?4 Q3 ?1 u0 |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 r/ R( s3 e* }+ Z+ m9 r; L
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