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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 U! K- R7 Q* c% f. B; F* hinput mcasp_ahclkx,+ T* }: v, |3 Y
input mcasp_aclkx,
5 d9 J0 g4 H3 y4 m; [! [+ ?& Y5 Ainput axr0,7 p G ]- B! {2 x( Y O
7 X( U) [6 ? b! _7 Goutput mcasp_afsr,3 s) \1 i0 ~: o/ q5 K, a
output mcasp_ahclkr,
" b) \8 E: z% a9 Eoutput mcasp_aclkr,
/ ^& J! C2 F2 t ?. Q1 Poutput axr1,
. ^% Z; V9 u8 y assign mcasp_afsr = mcasp_afsx;( l* P7 _& J9 [: z% N' v% A
assign mcasp_aclkr = mcasp_aclkx;
5 }1 l1 Q: T7 h0 B7 A( gassign mcasp_ahclkr = mcasp_ahclkx;
$ @' s c8 A. S' H0 l0 Vassign axr1 = axr0;
3 A$ X) m% A0 `* H8 u$ ~9 G! S: L! A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 Y$ G* S4 U; f; H
static void McASPI2SConfigure(void)+ U" E* @7 F4 U1 T2 I; x
{- i& h4 f: h1 h# [+ M! e/ i: m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* a: B# ~7 e8 t, H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% T9 w1 v: r, i) x( y* `; m0 Y. V& RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ S3 Z- N% h) b5 y3 ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" \. _! u; B' {. ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( O" T+ [8 G8 ^# W) c9 d7 `& ~
MCASP_RX_MODE_DMA);( P1 q2 ^. f3 U, h5 G; W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( n, U, d3 u7 W1 _6 J4 j' x: [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 `$ g. m# y# W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! H, ]1 W: d- e \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: F. A; [' C+ Q' [% x, j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : X. M; Y* z: }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: f P9 Q, E& s5 j6 yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 x3 v7 D+ m8 u" d* X& P0 GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' `; h, P3 U. b m( f, k% TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 N& e4 b$ C3 `- Z8 a; P5 ~
0x00, 0xFF); /* configure the clock for transmitter */
# f H' \; k4 Y8 H2 W; S/ f' ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 C9 T7 q5 r1 x( l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 ?: h6 `' |9 q: v. k8 x' N3 p+ f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( I* t1 @0 M3 P8 l4 c f0x00, 0xFF);' \8 u- u: v) A: p
* X; W6 l, n( ~& H- f$ c3 M
/* Enable synchronization of RX and TX sections */ 1 _* o" l: q. ]+ Q2 U7 E: T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 ]# R& C+ j4 u# x* e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; T$ h; r$ p8 z( x5 [6 B. {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" a) t. o0 G9 c& p$ Z4 ]
** Set the serializers, Currently only one serializer is set as
+ e, C7 e& n: L# C* K) M9 j( ^** transmitter and one serializer as receiver.
, }/ X c2 r# N' h' S+ z*/+ H7 C' @/ J; L v: X2 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ A. ]6 {" n) I1 @2 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" B+ ]1 z8 D( C, K
** Configure the McASP pins
; q# L& k- V+ m y** Input - Frame Sync, Clock and Serializer Rx) r$ I$ B/ N+ r- K# y. I$ M# z
** Output - Serializer Tx is connected to the input of the codec & C4 Z+ p$ k' p# q% ^
*/* m. j" r' _; I, W% d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 R: W9 Z7 U, G) l6 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& m! I: @* \7 _8 ^7 {# MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 s! b: b3 m- I e% I0 K
| MCASP_PIN_ACLKX9 a! n# o3 F+ ?* F
| MCASP_PIN_AHCLKX
w' G J4 C/ @" ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 f$ g# v3 f7 k" hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' [$ s+ o P; [) q- O8 m- _| MCASP_TX_CLKFAIL
6 M" U. i/ U3 z: C ^| MCASP_TX_SYNCERROR
4 H6 L" s% J2 M* B- r$ J( f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ ?3 z9 Q. [# _- `2 X| MCASP_RX_CLKFAIL
5 F0 {$ i' [" Q| MCASP_RX_SYNCERROR - O7 o; ]* h; J& W4 p
| MCASP_RX_OVERRUN);" u9 n$ K6 O1 D5 }
} static void I2SDataTxRxActivate(void)
! S9 S- r$ A; ]0 m+ f{
1 N5 d4 ], V6 B1 D% j6 {/* Start the clocks */
/ f! Z! _3 t& o2 c! c' d. D) U" H* o8 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 S, k5 L+ ]0 f8 n# kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, [* l! b' L% O) V; K4 @0 ^- lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* t% V, ~& t' e. i/ w5 [* Z kEDMA3_TRIG_MODE_EVENT);6 R% L0 U- q" W- l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 M7 z @6 c* ~' _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 }3 P) ?0 \& A' t a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 C ] c! `1 n7 i% I4 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ ^6 `9 d- ?8 [) N! a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 m+ j3 n' H! ^7 x" N6 q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* o' @8 U* ]7 }% ~+ P; [, tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 b6 D7 g8 H! V/ I( d}
7 f; m$ h; z, H1 `& @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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