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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 V5 E' g7 {5 w1 \input mcasp_ahclkx,1 W# p H( t4 E
input mcasp_aclkx,
# b. {2 O9 y5 R+ U, q. iinput axr0,. ^; A1 F& }6 p! I
* Z" ?3 ]: s e1 y0 W% Z2 U8 [9 Xoutput mcasp_afsr,
( L3 H# u' G+ s" Ooutput mcasp_ahclkr,
" p, {( x9 z% G) e# [+ \output mcasp_aclkr,( N0 w' ] N2 W. e1 W
output axr1,, v# A; N1 }# J! R4 J$ ~; n
assign mcasp_afsr = mcasp_afsx;
+ N1 i2 l7 V2 i+ {* _# bassign mcasp_aclkr = mcasp_aclkx;' w9 y1 h2 l' {/ e3 e9 E" j
assign mcasp_ahclkr = mcasp_ahclkx;
; o. E6 y2 @2 o/ Z2 j* [assign axr1 = axr0;
, }! ^7 u9 F4 ~- w
, M" l, N0 @4 \! Q, \' J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) u4 {6 Y8 q; ~
static void McASPI2SConfigure(void)
/ j$ i/ \1 `* G6 \, ?{
. G- [6 v4 C4 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% f# h- i2 H" p2 _% I* DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 G9 h/ S6 D ?' z l# _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; l5 H! K4 |8 n/ h2 T. s' j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" Q- F/ D! ]: K% zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 G6 a; t0 N; s
MCASP_RX_MODE_DMA);0 U/ V& t! p$ {9 |6 f( k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 F5 `5 w" z# K* L+ D# w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, |$ j* J. w3 v: W7 v; WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 m ^( o. ~% p5 R c& {9 m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 M' h+ S4 O5 p) {: T* DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) I7 u* v$ D \; n' P6 r! x6 K- \6 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 J2 A2 {. l6 O. L c1 n& T" j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; C0 x$ E. L q n4 [8 g% W! f7 gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, T+ w, o5 g* zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 p% x9 U! i" ~6 C( \3 f( p) |4 o
0x00, 0xFF); /* configure the clock for transmitter */( \7 u+ k1 m) ~- n3 i8 g9 s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: F& b2 ]. M1 d) `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' o4 h1 V( ?2 b, JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( V- ]: s1 Q5 l6 I1 q' g1 c9 O$ d0x00, 0xFF);
' c# y% ]3 y1 H# j4 k: r9 y% ?1 M9 V1 {" [) N' d
/* Enable synchronization of RX and TX sections */
# d: M9 }8 x, mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ m b; e* a$ \. u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ [/ a- e" y4 Y: c+ N2 `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. s& a/ g; B& r f8 t3 g6 c* f9 z
** Set the serializers, Currently only one serializer is set as; N9 [& ^# l* M' i9 I5 o0 S
** transmitter and one serializer as receiver.. T7 X7 ?% Y. }! I
*/, u0 l& p( C b K! X3 r, L" z1 Z( K6 y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* w/ Z% }) A) ?7 s, d7 Q" L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ e: v- _' T$ i6 K* o9 |** Configure the McASP pins
/ Q1 a& ^+ |/ m' X0 e6 B* w** Input - Frame Sync, Clock and Serializer Rx6 S Q9 s2 L% A& x
** Output - Serializer Tx is connected to the input of the codec
1 ^9 B' q/ Y9 L' [$ `1 @ G3 H*/
/ B: C8 ~6 f* M$ m+ m2 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 M9 S: Y7 y) j1 x4 u. x/ o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; X; W- Z" a9 z$ u: R9 hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% T7 v% l5 n, Y' ]| MCASP_PIN_ACLKX$ B3 W% s" \. h9 N- ?9 {
| MCASP_PIN_AHCLKX
8 S N8 z. ^ `5 Q3 Z+ t$ Q$ v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 N# X: |. \# X a, t+ w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
?& \6 z, V- o$ T3 p| MCASP_TX_CLKFAIL . V4 n0 s; Z# F: O
| MCASP_TX_SYNCERROR
5 A. [4 O* q5 K2 `: f. M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + `" m# k0 I9 \& h( Q5 T
| MCASP_RX_CLKFAIL
* B& J. a* I! o; z| MCASP_RX_SYNCERROR
+ p8 V9 x) e4 |9 S$ v. I4 l7 o| MCASP_RX_OVERRUN);
; A! W0 T& \3 t/ A/ n. Z( G} static void I2SDataTxRxActivate(void)* [2 T) `) i: I6 ]4 Z! h) B+ \
{+ @; c) ~. ~1 D6 @9 c# d
/* Start the clocks */6 q5 @- s, n! f. _$ s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
Y' T' I& |4 _% b" uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 E: j0 ?* \; B, k: j) VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( q" e. g& o" g. p; d. r
EDMA3_TRIG_MODE_EVENT);
. `9 x1 @7 Z( U) ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; \$ h- D1 N4 k+ ]& m) V' ^9 g# B9 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 h1 a2 @# Y4 Z# s" Q6 R. A: l; ^7 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# c3 ?4 i7 J$ S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% X+ G8 ]- L9 H/ twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' y7 j0 f! ]- F o$ A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 E4 R. i6 A9 c Q5 C7 X+ `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- P" }2 n4 L9 c) F1 X' x}
U! Y. p$ w* Z6 o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / q. E: H) e; D% w+ R3 V$ S
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