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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ V; f r5 b: H1 x$ }input mcasp_ahclkx,! h9 W. d% B3 K) X6 k
input mcasp_aclkx,0 j) ~, O" ?* Z8 m# O0 i, C* w, X; c
input axr0,) o6 H# O! `$ P O u8 s, J
% F# b8 k5 }+ n. V t/ n, U
output mcasp_afsr,
6 o0 @4 A. `) _output mcasp_ahclkr,
( a" ~5 _9 _/ s3 ]. O/ z4 m: qoutput mcasp_aclkr,
. b" b; t' u5 }! @# T; Q+ `) X- joutput axr1,
& K* {* A, T: U. a' P" t: b# _5 z assign mcasp_afsr = mcasp_afsx;
# \% e/ C" R- x9 F( qassign mcasp_aclkr = mcasp_aclkx;
; \/ {: \8 V- A' F5 o7 qassign mcasp_ahclkr = mcasp_ahclkx;: B5 t6 S: o6 y) f3 k
assign axr1 = axr0; 4 S' u- N( Z2 A# Y3 h, Y2 ]
: c) a ]' d/ a, [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , `8 ^5 u( |, c+ d
static void McASPI2SConfigure(void)2 x# D3 [, _" [* P3 ^! N
{
7 p! b! m$ O# j' {2 PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 Q- Z' \* ]1 ?1 }' J3 F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 D5 j" o) M' q2 _6 X% l4 c, y9 a7 FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' x1 l1 h# T4 HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( @' D# T$ L" w2 P) J6 h! e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; |* ?0 G7 {- y7 `- h" {
MCASP_RX_MODE_DMA);
1 I7 v6 y3 \1 v- a; G' B1 tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& x$ g6 n8 p0 I) O9 \* q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 C% H" a% z3 o( G! O8 J, C% A0 U6 Z, Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 d6 v& ~$ d: R) P" N$ I# {2 U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 Y% x0 o1 p+ X( k; z* vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) U) g6 A t; N7 L7 |) m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( Z+ }, E, G5 f! m# R9 i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, A7 M9 h1 J) w$ @9 H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
[/ s& n) i+ x' V/ ~" OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; Q' @8 O) k& Z( ?5 U/ y0x00, 0xFF); /* configure the clock for transmitter */6 U8 y2 q; @. _* B) K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# s9 I" ]: d9 b1 `. X8 o7 ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
Y3 X& [; ^( Z! @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 q) }, x% `: d; K# S9 A0x00, 0xFF);# h! R) Y: G, N+ L
' u# J- p" ]4 ?1 h, T, j) {
/* Enable synchronization of RX and TX sections */ 2 J/ i% H8 E: [2 T4 S+ k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: _4 L. g2 A( L/ ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" k6 A) T V# C9 H8 `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( \* I2 d9 R! N** Set the serializers, Currently only one serializer is set as7 h/ O6 L6 g+ w/ i3 m
** transmitter and one serializer as receiver.
6 l7 e# Q$ F0 L( L& F; I3 U! W*/% d, U) b" Y3 f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- g4 |# V1 N( ~+ Z6 z3 ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 Q, m/ x+ \/ U
** Configure the McASP pins * J9 z! _) c. J0 d; A( j: k- n! ?
** Input - Frame Sync, Clock and Serializer Rx8 c2 o7 l$ ]+ e' C6 M. b4 ]6 j
** Output - Serializer Tx is connected to the input of the codec 2 L. E' e: Q9 _
*/
+ b8 @/ _$ A! E4 i- {4 P# FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' i) q4 p0 I1 w/ \) b B4 }' I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; a4 W& I3 Z2 f6 P5 e+ [9 S# e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
x! f5 ~( o. k0 ~( \# B! K6 x| MCASP_PIN_ACLKX
( X8 I0 }8 m6 ]2 z( k$ N- D| MCASP_PIN_AHCLKX
6 X# D* I$ a1 U+ ^& M1 r' ^) ~' U. @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ h$ Q1 l+ K* ~0 G( r4 I# m* X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; n1 H: c$ E% t# R2 \% L( ?
| MCASP_TX_CLKFAIL ) N& K* C( @" S8 P# M
| MCASP_TX_SYNCERROR
% i, d2 v% t2 A! @$ y" m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) n, _: C( S6 j% w( ]9 W; q| MCASP_RX_CLKFAIL
8 c' z' G0 T. g- Q| MCASP_RX_SYNCERROR $ j7 H7 `! M+ Y* Q& a6 U
| MCASP_RX_OVERRUN);4 a+ M7 m3 G' G2 @+ W. o. [
} static void I2SDataTxRxActivate(void)6 r* ^+ r% u+ W8 f3 N
{6 j/ x" \) _* O) j4 X4 R
/* Start the clocks */
/ [- d" h! e/ oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 y- T3 q" r9 U% JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 F u/ F0 Z2 j/ ]# }/ @' ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 w1 {/ a" v+ H D
EDMA3_TRIG_MODE_EVENT);
, O2 j5 z. T: @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, j( [, a7 G7 a1 Q; ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& w/ N K( F0 E4 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% {7 \0 c9 l: O* Y8 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, z: k: q3 L' q5 G# O. C, ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& u* [1 d3 s+ BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 k% M4 M# W( ~1 {2 I- X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# \( X- n e6 N. z
} ! l% `6 U. i; l' i5 s0 `1 C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! U$ I4 |3 C, b0 C* y7 s
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