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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ I% z; { u. }+ H! y
input mcasp_ahclkx,
2 o# n6 ~. u4 B% V8 Tinput mcasp_aclkx,
2 N; @( D! `8 v8 X! h0 G- d; f1 a# Rinput axr0,
) w$ t; o9 d+ s+ d
M7 Z7 j9 V4 e" U! D* Routput mcasp_afsr,
/ R# v: j" d# I. Z: O4 ^, M- U& `output mcasp_ahclkr,( t+ A( ^: F+ z$ R8 Y: F3 t
output mcasp_aclkr,
; g" m- h/ Z1 F0 Poutput axr1,
$ W; _3 `/ P9 q6 a assign mcasp_afsr = mcasp_afsx;3 b4 \. n. y! p+ Y" H
assign mcasp_aclkr = mcasp_aclkx;
$ n0 h7 P0 P7 u! N# ~assign mcasp_ahclkr = mcasp_ahclkx;
. d8 Q; |+ ]% a. b% Massign axr1 = axr0; , T' ~, j& K# X6 a5 F
[, c4 W( c8 B+ Z6 h. t4 j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! d0 F9 b, V2 |% `* p
static void McASPI2SConfigure(void)- m# w- e0 o, k( F1 D
{
) \" U T- j& j/ o* d& R# }) j; nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. L, \1 D5 o' C" G1 g1 {8 t' o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 ~& b; t9 n x! I X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 v( k8 v8 W1 D; L8 eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 J) W5 I; h s1 k( U% I( w- \" yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, v( {! N. R2 U* W5 J; X
MCASP_RX_MODE_DMA);2 Q1 d3 |% Z; d8 S0 K) M9 v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ L5 g1 g5 W' [' OMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# L' X- Z- t9 {5 S6 [3 GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. y" A8 N$ K7 d* g/ r( Q# ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' q; i: [. @4 V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 r$ v6 _! A; G. a+ Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; N$ _! j, k$ o) c# J. K' ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 q0 z& t9 i. ~4 d. z* a7 f0 eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% l! x+ V: Z4 m. K! J: KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 j8 W7 e- {6 m$ e! _9 d# g: `8 b0x00, 0xFF); /* configure the clock for transmitter */
# j1 O8 P( u$ m) _& m K) e4 v$ p# |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ o! R2 o5 b9 F& F4 N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); x: S) G q* k) H$ y/ f+ v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, A8 ~6 _9 e# Q4 |/ X0x00, 0xFF);+ V- C8 j6 r) P1 T: C7 V
8 b0 a2 n& u# J3 a
/* Enable synchronization of RX and TX sections */
2 ~, J3 T8 Z7 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& b- t) Z0 J$ w, y% o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% i" a0 ]) ?6 U% v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, s! {, u5 S( |" N
** Set the serializers, Currently only one serializer is set as& {! y+ ?7 E) T+ a2 S5 s
** transmitter and one serializer as receiver.
* e& d( c, v/ @+ x L*/
/ d! _$ G$ @; xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, d/ R$ J& B$ g% i* \: r' [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ F! d0 i1 j- v! ~5 P* F** Configure the McASP pins & p0 ]4 z2 b, m0 v$ z, J
** Input - Frame Sync, Clock and Serializer Rx6 L# |( Q6 z2 h/ K/ [* ]: m% H
** Output - Serializer Tx is connected to the input of the codec
; p* v) \, I$ R% [+ I*/2 e2 O( K# _8 h/ v% p- G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 ~1 Y$ N [4 `5 ~: s! {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& L6 G. Q" H+ u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: F( c& L' E' U2 K/ o- v. R" m! r
| MCASP_PIN_ACLKX* I! F% I8 b9 J% k
| MCASP_PIN_AHCLKX
' i. Y- \6 S0 k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 [% x6 b4 K& A$ Y& A, C8 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 [4 H1 R. Z! [5 r
| MCASP_TX_CLKFAIL
, |1 r j! N/ g3 N, o$ r| MCASP_TX_SYNCERROR
3 A* z Z, r9 E! p9 G+ M& }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : ^ V5 |, j n" Q5 L* Z
| MCASP_RX_CLKFAIL3 K- q* s- H6 F/ u
| MCASP_RX_SYNCERROR
+ ?9 v6 K0 m. U: u y9 b| MCASP_RX_OVERRUN);
4 M3 m# K/ O7 w} static void I2SDataTxRxActivate(void)$ H& x+ P1 @4 R) m5 u. ]- J
{
. p& u( [' C) j2 ?/* Start the clocks */
' f# M8 W _! B1 ~0 _+ I" z4 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% E! f9 ^" |; {' A* ^% ^1 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) U" m2 y7 J* y% } c$ DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 Z( V0 x7 ?7 T* u+ s: ]EDMA3_TRIG_MODE_EVENT);
7 {9 w9 d" k# F( O7 h! q+ G8 G7 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * Z: ?4 ]" a* L9 R- \( Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; I J; t5 N: F( Q3 S" c/ X) }7 ?* a" q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 k1 v6 Z8 I' {9 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( p# t8 M1 o# v: @0 H" l/ l3 B; G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) M+ u/ l3 E+ Y; p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: c8 ]) h0 G5 h2 c3 F2 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); |" u; F! e0 x0 x! r0 T6 Y* ]- e0 t& i5 f
} 1 A8 g! @9 u; K: T/ h2 }& w0 m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; h2 I: t7 H/ Y* q# r" g- \: {
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