|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. c- `0 l( p2 L" ]( einput mcasp_ahclkx, D0 a2 s" }: C: ^3 P
input mcasp_aclkx,
J: g1 V/ Q( G D5 ]input axr0,
* R7 F9 Z& M; c [' x9 G- l* t2 U
output mcasp_afsr,
1 I( P' b/ A: L6 Q- k. h' P. z/ {output mcasp_ahclkr,
5 F5 c9 p& E: I3 M6 f0 poutput mcasp_aclkr,. o8 ?3 a k( y3 q9 j
output axr1,
' j. |& p/ r0 S$ Q6 \ assign mcasp_afsr = mcasp_afsx;
" R8 e. ]' g) u4 Q4 Nassign mcasp_aclkr = mcasp_aclkx;; _# z* X; e l( {2 ?! G" }$ p
assign mcasp_ahclkr = mcasp_ahclkx;0 j: A+ a" `2 [% z8 c3 Y
assign axr1 = axr0;
, ]* O A" e5 A7 x$ I
* k' h( ^, z: _$ |7 e n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 M D% Y6 T% _; R! s7 S& A
static void McASPI2SConfigure(void)1 E5 n* p% }3 l; n3 A3 _$ r
{& N1 B p5 \# }; v% h. _, x4 f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 }6 G1 r8 ~& l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% f" k3 J. e, m$ qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' J# F$ \9 z) E. }9 ~/ O7 U, w/ G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 G: C+ G* E+ q* o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 Z4 N2 ~1 _( O6 l* L9 h, N
MCASP_RX_MODE_DMA);$ O8 l0 D, h5 N2 O; Y5 K: |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 F3 }' j3 ^4 n x# J% ?5 ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- h8 m# ^$ u# V! F" L" m3 wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 H1 r. b0 G7 S3 v% V( F" d) ?6 kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 u! `/ G) O# R4 CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 M V7 B; S, O" t7 v# [" PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 @. Y6 s* |8 n4 [# cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; [6 d: l |" h6 e/ J. i7 m( B+ cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 S& ]9 q) G4 a: ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 N4 {) z {6 [ y/ D0x00, 0xFF); /* configure the clock for transmitter */# ?* u% P0 f/ n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ ^. ^- ~* J5 V4 h2 B2 EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ C6 q3 I- Q, X, }4 x* v QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 o5 D- l5 g' Y; G8 k
0x00, 0xFF);) w/ l0 g* }, h! f
( d# Q. l9 g/ n! f1 S& n; f [/* Enable synchronization of RX and TX sections */
4 h- b7 {: ^: h( ^# CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 H* W( O, B4 P& O, ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 _" |' s0 i, X; i k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# m6 a- m, J: t2 m4 k* W7 Y** Set the serializers, Currently only one serializer is set as( y3 G L! a" Q/ J3 I0 |0 p* |% l
** transmitter and one serializer as receiver.3 T* q5 x6 i: x, Y+ c
*/1 i0 G; O4 v/ k- D E& F8 K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( ]% a$ _2 E! sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 F* q9 }0 e+ Z4 B: Q" L** Configure the McASP pins
: y* ?, C8 y) H( O** Input - Frame Sync, Clock and Serializer Rx
3 p$ l/ _* R* V( ^8 ~** Output - Serializer Tx is connected to the input of the codec
7 t5 N( l% [5 S: O8 N) S*/. g2 n/ I+ B) Y) q; \3 ] v! d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! m7 ]' {. d2 l! }2 O& i5 U! }/ `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ t+ J% O8 c. r! D4 H$ pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 O" o6 Z7 O$ G2 I) C| MCASP_PIN_ACLKX
9 K1 C4 L$ v( J1 f1 R- K3 x7 x| MCASP_PIN_AHCLKX
9 ?5 y; d9 N1 ^* I4 r- y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ o- M, \, o5 M kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % S# H& |% A% _ j+ S; g
| MCASP_TX_CLKFAIL
/ S+ B# N$ T9 Z! R8 t5 W| MCASP_TX_SYNCERROR4 e. f H% ^5 U- D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 ]1 t" x0 R S1 q& s* f1 O| MCASP_RX_CLKFAIL
5 J& o$ g9 U! [+ y| MCASP_RX_SYNCERROR
* J" m- Q3 s; c2 z2 || MCASP_RX_OVERRUN);
! Q- h" T. u. ^* H Q3 i3 o2 z: G" R} static void I2SDataTxRxActivate(void)
7 R+ b" b8 _( @{5 Z% Y8 P& R" S/ f0 q3 a2 g, H
/* Start the clocks */4 R" g; U' T% g# O. Q& Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. q' J, w% C% H: O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* A& v$ E2 A0 [0 \# U4 d# uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% c7 V* g7 e- m H: }) p( nEDMA3_TRIG_MODE_EVENT);
0 V2 t' t x' d9 A$ T4 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) D' b- d! {3 k# |0 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ n- z9 d1 ^# v: r: d: M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 m) I! v0 H. ]" t2 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 L+ _8 Z2 w0 O5 A7 k9 r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 e( W/ h, a) }$ wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 i# x- f0 Q4 _' L: s' s E4 C# o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 C3 O/ N. D0 }! x
}
1 m' Z- j" ]8 D( l. _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & G/ u3 D; C8 V
|