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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: o6 z; Z4 z$ n) J+ T {8 C
input mcasp_ahclkx,5 z7 N6 e. M; g# e& b
input mcasp_aclkx,
/ N% O& Q% O7 o7 vinput axr0,! d/ y/ F" b( J) M; V2 ~
" y( v- P2 S) a9 g* f9 B* X
output mcasp_afsr,8 X; w2 u1 ?0 r h2 M
output mcasp_ahclkr,- U4 z8 ?: g1 ~ Q. J. P. E* x% s
output mcasp_aclkr,3 j8 {8 \# R D' V) H5 u6 D
output axr1,- L F! F9 U5 p# h
assign mcasp_afsr = mcasp_afsx;: A2 \/ p5 G" k0 f
assign mcasp_aclkr = mcasp_aclkx;- c! t1 W V/ T' D5 i+ N
assign mcasp_ahclkr = mcasp_ahclkx;
* D$ ^% P$ g$ Qassign axr1 = axr0; / V9 t8 n% m9 w" c; g: Y
6 K+ {- V. w1 x0 d7 ~: R( W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' R- X* P& Y5 v, d6 E2 ystatic void McASPI2SConfigure(void)
7 U" _& s9 S( n; T' T1 Z{
$ ^/ Q& A" j0 N: X, Y- k: m8 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! S3 K w0 v% _" f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 h8 f( X# S5 x' l9 T6 Z9 p( M% [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 l: v3 D* f: O% J' k# r3 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 S9 x! D2 T- t" `/ U: TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# A$ r+ H6 F ` ~7 h, }8 d
MCASP_RX_MODE_DMA);
6 z2 i# L- j+ R- i! RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) {( u R& i, O2 N' {, z8 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# r$ @& w- E- m8 w: J: v% _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! p( ?% z% k& u- W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& Y$ ?/ |* S; I# q; t) |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # o$ W. W$ s" V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 V& T9 ^4 n+ M! O- L1 K, h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 f0 f: i0 c6 {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( n2 E0 O2 s @/ h2 U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' w: v) U- `' Y, F+ d. R0 Z& [8 Z
0x00, 0xFF); /* configure the clock for transmitter */4 Z+ [+ J# j5 W6 r" Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 J7 A4 [ w/ m, q% g: }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 X& _* S- X5 s. MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, a& M; `/ z+ ?2 ?. \0x00, 0xFF);: \5 ~0 e' I1 V8 b" ]
5 N- Y) `0 z) I' ~
/* Enable synchronization of RX and TX sections */
% t5 @- f, S' m, `7 r' MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 F1 i( w% [7 Q1 vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' ~) W" d% Z8 Q4 W# |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# n) H# d; \+ u6 ~8 @8 e3 }** Set the serializers, Currently only one serializer is set as
. B: w* x, R# S; J% K1 O4 o** transmitter and one serializer as receiver.3 l$ s- H# n c4 S' c
*/
" a8 ]5 l v# D, c. U, P; AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% _# y' I7 z4 D/ V- F4 W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" C. d! j& ?4 g! H** Configure the McASP pins . K, @) U7 X: x* k5 Z% N
** Input - Frame Sync, Clock and Serializer Rx* o4 E, |$ i! N( v4 ~7 `* L! M
** Output - Serializer Tx is connected to the input of the codec 4 m- x# A* T( d/ b( W: Y
*/0 w8 D0 W! h- j# n2 d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
|( s* T+ t \& y# B2 z4 u! q. ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- F& l3 o/ H7 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 G# l* e. D( K3 t' J3 c* A$ M| MCASP_PIN_ACLKX8 D% f. R* L1 b/ j- P; O
| MCASP_PIN_AHCLKX
7 X; U3 {9 y- W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, e% l9 E* N5 k' yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) j) V; ]: ?* y9 G9 c
| MCASP_TX_CLKFAIL - @* g: H4 C- F$ q
| MCASP_TX_SYNCERROR
% ]' ~/ Q0 e5 P) G4 E- Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 I, b* f1 ?" _
| MCASP_RX_CLKFAIL
+ w, i" o: s$ T$ \( j0 w( X| MCASP_RX_SYNCERROR
1 f- c( L1 D# d' D0 b5 @| MCASP_RX_OVERRUN);
8 F) ?* {2 i! U; b; H} static void I2SDataTxRxActivate(void)
: T3 ?1 S+ P @: q% x{
2 Q! g" T+ d+ F; U: N* Y+ `/* Start the clocks */7 Q f* R" M% b$ [3 c) x5 n9 ^, l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( X3 B. a. Q/ J y% ?7 E% M3 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( b( B* a1 P. {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 \ r- ^0 n; D# R+ ?
EDMA3_TRIG_MODE_EVENT);
+ N) j# X$ q- r( c/ `- ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 a+ r' C. i5 e' J# x# c/ hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( u8 s8 s* j6 ]* X( x: ^& d" UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ r) p ?1 ?% FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" q) ]& U) `7 l* O0 g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; v/ Q$ _% I5 }1 f3 IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! ?0 S& O, S4 n+ L' hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, @. }, b' S' t3 g) z
}
( i9 [- c) l0 X& [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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