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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ V7 E- k* A7 q3 P( E! e9 [1 Jinput mcasp_ahclkx,
+ j1 Z! w: S" i% O7 A6 linput mcasp_aclkx,
! s; M$ V8 B4 s0 ], R6 c/ Cinput axr0,; m6 \( m( @1 i" J0 ?0 y" W1 ], r$ ]
& O' J+ |7 h a* C eoutput mcasp_afsr,
# u& u) c, ]( j U7 @: ooutput mcasp_ahclkr,9 r# z4 n% L. N
output mcasp_aclkr,
& x, Y; }: a5 j7 Joutput axr1," ~2 h8 o4 s0 P, D# v0 y; c
assign mcasp_afsr = mcasp_afsx;- m6 {# J/ V1 x2 x! w) C; \
assign mcasp_aclkr = mcasp_aclkx;
+ u. s# A4 q$ J D2 cassign mcasp_ahclkr = mcasp_ahclkx;
4 q7 L* |! z" S9 a; b; Z0 Qassign axr1 = axr0; 6 S* b: V( \! G1 a ]. p: s
& L7 ^4 w5 g. I- Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 }$ c! ~" O9 ]2 M8 Bstatic void McASPI2SConfigure(void)# g. X A( y/ s; F
{
$ A: b- V( g* e# E4 b3 y: |) kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 Y# o; y. u* a; j$ Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 E E2 ~! c# H$ f) |) B$ eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! q; u& c' }* P% d, {3 w3 `8 DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 ?" A/ D, |% K, G3 l `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( m ]: \; k; w+ VMCASP_RX_MODE_DMA);. B# `$ Q, D' |9 P8 | T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 f& f( a7 Z5 oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) g p5 K9 |. X$ e: M( ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% q* I9 I/ v* f; PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' q. i5 h5 ?$ S1 E3 ~/ F0 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. O1 a! ?" \. e. R& Q. N* vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# j" D& f# ^5 a: ^$ `9 vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! {2 m9 ?' ], h7 N0 G0 V1 Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 B0 n$ K' F4 R7 P6 u$ M4 m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) ~* M- n2 ?, i5 S1 X: [- M
0x00, 0xFF); /* configure the clock for transmitter */
# k) i+ [+ l) n- B1 I3 KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ j6 ?; {( a' C5 @' N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ A& ~* @) N' J6 S W. U' jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 \) T6 [. p) ?' X% I1 B3 r
0x00, 0xFF);
3 e1 D7 e X' G& H4 Q- ]& t+ P/ v c D0 D# x; C
/* Enable synchronization of RX and TX sections */ * U; T, [' k! L1 a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ m2 E8 j" _ [: b |. r- x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 L. q4 N7 ~5 [* }2 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! p! n' x9 ?! f- S7 w8 k1 g** Set the serializers, Currently only one serializer is set as: N( ]7 |9 b& M
** transmitter and one serializer as receiver.
. Y( ~, `, _* ?/ x5 b ]*/5 [( x5 c; i W2 c* I: D6 V6 h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
w4 J' k: x1 H P, s' m4 eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ \; A" D8 A( r6 f- _4 z! Y+ w** Configure the McASP pins $ {" \, E. r3 {, d- [ ?& o
** Input - Frame Sync, Clock and Serializer Rx7 {0 v) v1 i, ?$ U! c7 Q
** Output - Serializer Tx is connected to the input of the codec + M# l1 h+ g; H7 R, B2 J3 t' @* M2 A
*/7 r. _/ X+ A3 H* N: ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
Z* S/ ~, m: D. _- C9 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 S" I$ X/ [" O+ {: ~- @/ qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. W0 \0 U3 i2 I4 m6 M5 L. b
| MCASP_PIN_ACLKX
* B2 E! S% @ n% t& k| MCASP_PIN_AHCLKX* @5 Q; S: ]; Y- V' l9 K7 Q/ o! Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 V7 Z& A# s: A) S# P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* {7 n6 C" U) Q7 G e5 h, w9 d# L( a| MCASP_TX_CLKFAIL : M' C3 q8 e7 I7 c
| MCASP_TX_SYNCERROR3 W9 y/ {7 k7 h* H3 R) a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 n0 ~% K8 q4 \| MCASP_RX_CLKFAIL5 B" V* x9 m: K6 |3 M% J4 ^: r" Z" d
| MCASP_RX_SYNCERROR 6 R7 b% a, ?. I3 [4 O* C
| MCASP_RX_OVERRUN);
2 J5 t0 Y7 t- `) q} static void I2SDataTxRxActivate(void)
- A: N) E6 p5 k' X{3 e6 Y$ Z- k% E/ q
/* Start the clocks */5 W$ m! w8 x/ `0 q7 w7 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
r& S/ b* J$ s# PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- v' B7 c+ [" U8 ~. |8 l3 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' @0 o9 g, M8 ~9 q2 ^EDMA3_TRIG_MODE_EVENT);
! ~; m; V" A8 B' uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 f s; n ^" ~- DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& m I7 R5 a/ M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ z) J" @7 q! d7 d9 Q, {1 z! K1 qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# ?8 E' t! w2 f _. |( @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: y N7 A" W9 c: G4 W* m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 H9 C* A8 U% r$ A% U! T L7 KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( e/ X) L z2 [( b' Q( r} ( b" ]8 I2 u! W4 Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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