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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 a: [7 ]0 Y9 B# |# i: finput mcasp_ahclkx,
$ D+ R M; g0 A# ginput mcasp_aclkx,/ _; x2 M* q4 p3 v+ E6 W7 ^& S$ n
input axr0,1 j9 c2 R0 x) E! R
+ S6 l/ S6 u P4 f- {
output mcasp_afsr,
# N& j$ L/ I. ^; e9 ?9 H0 Uoutput mcasp_ahclkr,
Q, i$ Q& {' X: voutput mcasp_aclkr,& X+ l9 S X6 }- Q
output axr1,! E& q0 q% g2 g( o& j b5 e
assign mcasp_afsr = mcasp_afsx;
* A4 p$ P4 B1 R2 eassign mcasp_aclkr = mcasp_aclkx;' r3 f$ K6 g; ^! Q* V
assign mcasp_ahclkr = mcasp_ahclkx;) ?; S, m. s( x( }( G1 Z1 V9 b: F0 s
assign axr1 = axr0; + r0 T2 |# b! r3 U/ B: v) D/ M! Q
1 @5 ?2 A+ ?- u4 a/ E2 Q" }- ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 g' k/ t5 E% T. ^ c" Qstatic void McASPI2SConfigure(void)1 O: E; a2 k' r( w
{" o& {- _7 ] c8 w s, j: [6 ]2 T7 B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" s) i% }9 y; F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 P6 I/ B, n; ^0 y$ ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( d% m- f1 y0 ?# j4 f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( [1 p. _- I6 E7 Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; r ?$ ?- P+ c6 t* h. [
MCASP_RX_MODE_DMA);
! |4 _& n. l ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 }9 h4 V. ^ v- h8 x: S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 F2 V" E# N0 R9 i/ WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * s! _' T7 F1 n# _4 y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 u8 f8 m( W+ l# Q- fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ Q S7 g& R7 J* X U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- \6 L% F9 T2 }5 W8 X+ M. _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ l& t2 z ^ BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); W% r' a& ~& `( @7 B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ n+ k' V' z; t% j* R0x00, 0xFF); /* configure the clock for transmitter */
% M* h* Y* m- {! ?+ Y9 X5 o/ hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( l, a/ f2 t" H+ j, Q0 [' }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( ?4 @: A! ^+ e# f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; R) l# s" l! _
0x00, 0xFF);
' t' Z, S# S3 @9 b. j; J1 `
, {! u6 k6 J$ H7 Z5 R8 T. p/* Enable synchronization of RX and TX sections */ 3 \6 P B- A H9 y' d7 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) j1 u0 \2 p% s# A2 i6 Z2 m' yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ d: d( m$ D; `5 X: H, \0 n3 o1 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 X' }% ?; W* j, X: Q! u
** Set the serializers, Currently only one serializer is set as
6 g8 v* L* U& T5 X! i** transmitter and one serializer as receiver.
3 f7 |! t7 _9 {. {! D! P*/7 o* }3 ^' W! v8 Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ L: |- [0 j1 u3 e4 TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" t7 l& H' K0 G# Z4 i( c** Configure the McASP pins
# ?! G4 P! i! U/ ?7 T. z** Input - Frame Sync, Clock and Serializer Rx5 B4 ` s: A+ K( G! q' s
** Output - Serializer Tx is connected to the input of the codec T; T* J0 M; W, P
*/
1 V3 r% P2 W5 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- r$ ~# l2 { i U% }( [% g" dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 j+ {4 h' T& O% q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 S" h* n0 ^* N6 o- e+ h6 S* I) k. V* K
| MCASP_PIN_ACLKX
$ B! ^3 \# _" u y| MCASP_PIN_AHCLKX0 N5 a6 F/ H; N, J \0 |4 W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! u8 I) v1 n& Q# A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 }! D+ p5 I, ~% D" A
| MCASP_TX_CLKFAIL
+ |3 C, f' R1 L, z7 X b| MCASP_TX_SYNCERROR( N5 Q W' U/ Y* i4 X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* D1 q" G" s: @0 X| MCASP_RX_CLKFAIL5 R# V) h6 }: e8 v& B
| MCASP_RX_SYNCERROR
9 q! ?6 {: k: C' O| MCASP_RX_OVERRUN);' y; F1 s" x& k f2 g; N7 N8 r* a
} static void I2SDataTxRxActivate(void)
# N; @ N# E1 N0 L{4 W* m# Z! Z+ s8 e1 f* Q- P" j1 D
/* Start the clocks */
3 d: q; u+ x: z6 _% _* \/ FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; Z# \8 C9 B c; h2 i( zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% ?. x1 u& Z4 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 I7 W1 z) [2 q! U+ L' F/ yEDMA3_TRIG_MODE_EVENT);
8 x3 b" G& j5 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 f. k$ ~4 S" q3 fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 A2 x! ^: R; d) lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; U, S4 ~) I) z$ V1 XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* J) ~$ P$ b. y! Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. {6 A& {( A& FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; _/ q' }6 N' P- M# B4 T' ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 Z" l; v& f- C M: P% X}
- G% Y; t( y, U" P1 T9 E, s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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