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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) C o6 a Z- h a1 w) c% n
input mcasp_ahclkx,5 V. l! T* n% ]! r
input mcasp_aclkx,5 v! F1 R1 r5 U( ^% y2 P
input axr0,1 W) V) f2 ]* m3 @# Z
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output mcasp_afsr,
. h- |9 _8 l. b7 v3 e4 Uoutput mcasp_ahclkr,' a6 E, \# t7 p; Q. h9 _
output mcasp_aclkr,
; G) x. w' j3 E* Q" t. l Houtput axr1,: y( K( Z5 v2 y0 ]. r
assign mcasp_afsr = mcasp_afsx;& ~1 n, Y/ \1 r, U) M3 x h* _
assign mcasp_aclkr = mcasp_aclkx;
7 q9 l) G; I0 q5 Cassign mcasp_ahclkr = mcasp_ahclkx;
) I- T8 M! p `2 e$ K9 r+ Cassign axr1 = axr0; 5 s- M0 Y* C5 G
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 a" Q' |8 T- r5 B. T0 fstatic void McASPI2SConfigure(void)2 B1 b7 d+ E+ P6 e
{
0 m2 u# R4 K1 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ x/ T) x! I/ ^0 f t5 D z7 `' M/ b% V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// P# n, u3 S& U$ Y8 G8 H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% }0 C& {: ~7 {4 |+ l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 C {+ E5 F4 e$ }/ IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ z( e @+ T9 P$ _1 ~+ N
MCASP_RX_MODE_DMA);$ J4 n7 M! R9 Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 Q& d Z" T+ p* B3 t/ G& h+ J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 \2 s5 v8 p. B: V1 Z9 s. B( f/ m$ \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / o; K6 l1 i S; ^$ l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' E' K3 ^$ r5 [* Z& u4 R5 m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 s' Z4 u' S& o( O; P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; _$ R- b& P# Q4 u& C0 _# ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ e2 m. B0 l) d0 w; E) ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 v3 O: K- Q1 a; F$ {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# E6 ?# w2 K3 q* J' |
0x00, 0xFF); /* configure the clock for transmitter */, X( m* _7 e8 ~; l, j" o( W U2 `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 `8 s' c2 Y5 I" A8 vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& M& B+ R) Z0 i4 y# k( dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' z% r( Q" J- o) A, ^1 m* U
0x00, 0xFF);. f5 O k* b# j/ J5 O. |
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/* Enable synchronization of RX and TX sections */
( P; F3 w- @0 yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! w7 @7 m9 M, B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- e) h1 B0 y' m& hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; l `! \: k. h F& m** Set the serializers, Currently only one serializer is set as4 O8 p2 v7 y! v& E# _! u+ H
** transmitter and one serializer as receiver., ]1 B6 Q0 s+ ~
*/1 ]2 N! i2 ?+ B. C9 _1 T! s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 A" Q( c/ U& D; g; A2 Q: A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 G4 J/ I' M6 S' d7 i
** Configure the McASP pins
, X( D1 `- ^' a; j7 a; e6 t. K5 m** Input - Frame Sync, Clock and Serializer Rx L; a+ e: c3 y* X
** Output - Serializer Tx is connected to the input of the codec 3 U! U1 z# C) o
*/
3 V3 m' V& O7 }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); @9 x u4 h: Z1 j' G% }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- K8 r" F) n h; R: [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; Q! c( k& R/ y) b| MCASP_PIN_ACLKX- o! C/ F2 u6 p# V; o; B
| MCASP_PIN_AHCLKX
% I4 r% [% u" E$ D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 v# W- v, ?8 A7 W& SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 R- J2 _: K; Q( g4 K- Y7 H; c| MCASP_TX_CLKFAIL / Y9 |/ h8 ^ J0 y, S6 r P
| MCASP_TX_SYNCERROR
2 B# g' x2 c0 f, {0 |% G |" j1 l4 D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + v& ]( D; A+ R/ Y
| MCASP_RX_CLKFAIL, C/ E5 Z4 U7 T
| MCASP_RX_SYNCERROR
8 ~/ }; h3 J- G! q| MCASP_RX_OVERRUN);4 e# h8 Y! W8 \$ D
} static void I2SDataTxRxActivate(void)' |7 M" g4 B1 v, j! ?4 y8 Y
{
; M( n, [) S! M5 }0 @. v& K/* Start the clocks */. B9 {0 r5 V4 _2 Y1 l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 `4 a4 L( T9 ]. b; v$ iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 s$ K# ?0 Z6 x0 }8 k" s; {9 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) J7 R8 ?1 {. k- `
EDMA3_TRIG_MODE_EVENT);
; `7 ^! w t- F9 n9 m. z, p! X1 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 o- k- N1 }/ U/ V: z. R$ ^7 u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- `+ O0 s: V) s/ N& ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' i/ d; }( D" @; }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( n6 s, W+ U. _ `7 E% [0 Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 f+ J% B3 ]% b2 EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- m1 t5 _* m5 q! z" o) v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! r+ M" u; |2 |: e: q$ y
}
* }4 h1 Y& p9 w @0 H+ V0 m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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