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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* p7 e" c6 U6 winput mcasp_ahclkx,
5 P1 v5 \: q* J' n' o0 E' L1 Z% w* xinput mcasp_aclkx,
% k x: q& K! ^) ?input axr0,
0 E" F( U- j. s- j$ b: {& P. ]& a) L9 h" t3 n$ H# G: G
output mcasp_afsr,, M+ b3 n2 v) Y" A- g: Q
output mcasp_ahclkr,* O) F9 N3 J# F0 o
output mcasp_aclkr,7 U8 E% F! }. q$ `* r' {1 D
output axr1,0 N7 G/ u6 M/ f: u5 r3 a
assign mcasp_afsr = mcasp_afsx;; m M3 ?9 m. x0 h8 q
assign mcasp_aclkr = mcasp_aclkx; f4 m7 R% i% t# j
assign mcasp_ahclkr = mcasp_ahclkx;; O* a2 G( y8 a* C
assign axr1 = axr0;
: C5 B7 s ?9 i0 R7 \% P$ R( L; y( u# N3 `4 U% I+ F: J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% g0 V2 `# M; g: d' R8 d( nstatic void McASPI2SConfigure(void)5 ^# m; N; z6 E8 R
{5 L% K1 a/ N& o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" b7 N9 l n- Y& ^1 g, U& z( a7 d# H3 _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- ^: e# _/ J" kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% q! p& G( `7 V1 W7 a# h; [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 ?7 m, U+ V$ b- G0 ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 \; }* y% W! @' p1 H4 ~5 BMCASP_RX_MODE_DMA);
7 a! a( x! h9 d5 fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 w9 V' q* R$ ]4 kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: \: P! M- `+ A. y1 J3 L( o' r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( K* E' u2 x' a3 Y- E" q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, F9 X( i, W5 g- f7 b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 k9 T; J0 K d, N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ U( M* ]' t% D8 Y7 Q( [/ `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) G- U3 [5 \+ b" Z5 i' N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. S" g3 k& d( M! M" A8 a- `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% _7 ^9 [5 B/ j3 h
0x00, 0xFF); /* configure the clock for transmitter */5 n9 U' ^! V2 _7 `0 B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 v8 @- H/ P* Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( A! L8 G# ]& T, h/ `" d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 G7 y& J1 W6 v
0x00, 0xFF);: W6 D' M( z$ _: Y8 B0 _
( R+ K- E) W+ e7 q! }7 G8 C/* Enable synchronization of RX and TX sections */
2 [0 n+ Q0 O1 ~( S: l+ kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. s- Y) M# @# L4 S; N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 u1 a4 M8 R. _+ rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 j7 a/ S7 `& v9 G& S0 D% {** Set the serializers, Currently only one serializer is set as
- r+ C6 q1 E2 m7 o8 E/ v5 v** transmitter and one serializer as receiver.# H% m4 |) P; q9 I9 X5 s; Z
*/
1 x( V" c' A- p2 E1 d$ HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 B7 ~7 N) ?. h3 M2 d4 E" G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' b Q% d1 _5 A T** Configure the McASP pins / Z# D7 h/ k8 ~; O4 G4 x5 U
** Input - Frame Sync, Clock and Serializer Rx2 e: V, X# E: t4 h7 v# x
** Output - Serializer Tx is connected to the input of the codec 8 W e/ ^6 B3 @1 [
*/
- d+ D/ R4 E: k: s- q+ a3 M s+ PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) ]! b! I# x( \% s- D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# B. L1 S+ x% S1 j. z5 ~- L% Y! P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. R$ Z6 }( b4 @) {; t6 v/ [: J1 K
| MCASP_PIN_ACLKX
; k( K9 w* Z: T/ @| MCASP_PIN_AHCLKX: W3 F: Z$ b( q2 D: b9 U8 F) _, y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) m7 W. Y X' ^( J& _* X* J. ~2 ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( X1 U- i7 J' T4 S* d, J! H9 E
| MCASP_TX_CLKFAIL
9 B) z1 A7 ^6 M, O, L8 y% O| MCASP_TX_SYNCERROR, J$ k! } B F' ]; n0 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& P1 L. ^, @5 p' g| MCASP_RX_CLKFAIL/ p! H$ F9 j7 U6 L6 W
| MCASP_RX_SYNCERROR
; C" i0 c* l3 @5 p| MCASP_RX_OVERRUN);; o4 e" s8 d$ X) v- p
} static void I2SDataTxRxActivate(void)
0 H9 D+ ^5 J ~8 I# ]2 Z{
1 u( r& M1 H6 W# z1 S9 V8 A/* Start the clocks */
+ m- ^) |$ x7 t8 z/ O1 f/ dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* a: J' W' D4 A4 P" x7 s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# j; I( I; P$ o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 e' Z" \1 O9 r( | E' f
EDMA3_TRIG_MODE_EVENT);& Z6 R8 z+ T* N& e4 S& E' H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 E; F" I" p& R2 ?7 B6 c* ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ x5 V: v/ p7 q: n0 K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ Y6 `& s! \- ?1 L p5 N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
V/ Y0 M% F5 `6 t4 a% i' owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 x }( `( L; W( b/ n* n% ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* |9 e! E/ D/ |, } ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # w% U, e' T2 o+ f
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