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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' W2 ]4 D; S6 @! ^. F& K! ]input mcasp_ahclkx,) }" l @( _- Q& o1 v I! |6 p
input mcasp_aclkx,+ n& d6 _$ g0 w' y+ e
input axr0,5 ]$ p) y+ v" A6 N' X) b/ i
7 U) X6 I6 O U. j6 X1 V5 `; Coutput mcasp_afsr,
' X; J2 w; p- _& r# Qoutput mcasp_ahclkr,
( M$ y* x( m( }, N5 M4 Noutput mcasp_aclkr,$ d) m5 H3 J; N8 u
output axr1,
. C* \& i5 V, N' n" ]# E assign mcasp_afsr = mcasp_afsx;) W2 s. ^" ]% n7 W& F$ Z
assign mcasp_aclkr = mcasp_aclkx;
( o$ w- t3 _2 k [( R; \assign mcasp_ahclkr = mcasp_ahclkx;! s4 t x: j0 P7 p7 M
assign axr1 = axr0;
& Q1 ]" k( u. W) |2 p" n7 ~
; u2 P& E4 m) B' L1 X+ q$ R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & [; U6 f1 {/ E! C k
static void McASPI2SConfigure(void)
. o1 U9 s, Y% o' F0 `{
1 l, Q0 _. {/ p3 zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 x+ ]. z+ C, R( L0 P9 }, j+ x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
P; L- ^3 }& s; E: J$ i/ L6 pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% q& B( l1 |' R% _: c/ s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ m5 y3 Y: l1 U* x$ cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 G, y( `; f7 l3 Z% w1 V9 C- Y
MCASP_RX_MODE_DMA); `7 U# N' C. H0 e. {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; r% Y: P+ v4 _- l) _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ [! G- W K. w# x* e3 m* CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 v+ O5 f# }+ \4 ^: C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 d* u8 t- Z- @" B- {# C2 cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ n& b6 p5 N! p8 |+ s7 t- v+ UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( H% P% D0 Z' s# YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ h4 z8 g D9 Y+ i$ LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & c6 Z# R" g6 U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 Z4 h* M: S8 ^; b- ?. i0x00, 0xFF); /* configure the clock for transmitter */8 h. N0 E# K' j* z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
^0 U8 j+ ~" ?& i. e- f0 E- k) dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 V6 \0 ~, U; g) G$ [, T4 N/ n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 \& a% B: o% X) N
0x00, 0xFF);. I- p1 v/ h! e! X w9 s* ^6 U4 @
( m! t2 ] ?+ a2 J( c# [
/* Enable synchronization of RX and TX sections */
% X. m2 q5 g- T0 n/ i. `" zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' K: b& e8 p# |$ Z0 m3 r- y; R9 k8 H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! |' [: j5 O1 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ m' I( ]2 B# L** Set the serializers, Currently only one serializer is set as
, [$ p6 P5 i0 J** transmitter and one serializer as receiver.
8 k) s \/ c5 i8 Z9 K*/( U R+ H/ P7 ?- C' B9 u* N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# x( u$ H( c( g' t8 X! L4 y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, f' w! ~' r) g
** Configure the McASP pins
- t0 K% Y Z l& O* y** Input - Frame Sync, Clock and Serializer Rx
; v' N! ]0 O V0 k** Output - Serializer Tx is connected to the input of the codec & ~0 ?+ x- i/ L* @, z
*/6 M& s) W6 O& N* R \) T, t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- _- [4 u# N( P4 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: Q) B1 }, `9 p+ LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; |6 Q2 E& P7 B| MCASP_PIN_ACLKX
8 @( ?: u8 M. v# e8 Y3 F$ I" G| MCASP_PIN_AHCLKX+ \2 v: M- @4 w- W% q- U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 G$ M1 @0 E. n7 t) xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 V3 k" z$ p/ ?- \+ P) U
| MCASP_TX_CLKFAIL & A. \9 \ u O7 g2 `' X$ @
| MCASP_TX_SYNCERROR8 N$ f" j8 n* D' g& a( X P. z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # R4 `/ ^' K1 n) p
| MCASP_RX_CLKFAIL3 q& D# |. E0 z) @
| MCASP_RX_SYNCERROR
b9 h2 P" D9 H| MCASP_RX_OVERRUN); ^0 j' R" Z* l& I* x5 F j" v
} static void I2SDataTxRxActivate(void)
8 J" y% t: w: `) Q+ P( L7 M{2 V9 J+ v3 G) K4 C, M5 B' q% ]) f3 y
/* Start the clocks */
' t8 W5 l" @. R9 J5 m: ?9 s2 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 N- m2 r7 T- E# x$ x5 T( W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- X9 h7 n/ o3 g: T1 L) N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- w" A$ N* q9 ?: g, }( f+ ~' GEDMA3_TRIG_MODE_EVENT);% o [$ o" R: ~8 u9 g& K) x" B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 C. _* }4 W) ?0 S9 C3 k# p: \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 @& s x2 }' ~ ^( D* GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- G' X; L) t" f& w3 l; b8 k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# L; N6 C% S3 b! V) K$ [! s8 [9 t5 w! ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( J" k; m* F G* r& U2 b& a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& A* W% \; S" U" O, |, {* bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% V/ ]$ {# \# ]) L( N
}
2 R l/ O- e# l( B; R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + G0 I4 N6 |! ^$ z% K+ ?/ i; _ [' O+ w
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