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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 ]# H' Z; n4 ?3 d8 z# o
input mcasp_ahclkx,
4 z+ D! Z. N$ F4 v# einput mcasp_aclkx,
+ j" d5 h Y& ~8 i& p8 }+ u( Vinput axr0,
$ v) s2 _7 S7 _
9 k! }9 m' Z# s! s) c1 T' uoutput mcasp_afsr,
?* ^& Q5 C% Y: J1 f" [output mcasp_ahclkr,$ [& S' r) q$ M
output mcasp_aclkr,
Q3 d; X: E' \* Zoutput axr1,
; H% B6 |# W4 r! x) x R assign mcasp_afsr = mcasp_afsx;
5 f' n( q+ B) I- D! i) Lassign mcasp_aclkr = mcasp_aclkx;
5 C, f$ ^/ _( W( y! Z% Q! T; vassign mcasp_ahclkr = mcasp_ahclkx;; d) Z- D4 g/ P) s
assign axr1 = axr0;
5 R; a1 x8 t! l4 m
: H1 E$ h) G; o0 u' w1 C, f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' h: r3 f" \7 `, sstatic void McASPI2SConfigure(void)
. M2 }% g( y7 ]{
' C+ M; g- E$ x% C/ Y) v U& [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, t* R. M q5 \; @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ b% \! l) B% Y( ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ ?2 Q. R% V& a2 V; yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) V+ {1 `/ b1 l9 Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ l! ?3 V+ `9 R- |8 ~+ l6 U
MCASP_RX_MODE_DMA);3 {! P ~+ E3 X. W0 ]/ n3 V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 S9 y% E1 p7 n' ], o& a6 |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ o3 A8 G7 \& C0 ^2 l3 H- s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" a- K( X# P: D/ j1 r8 EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: ?) n6 Y% G q+ uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% w! z. E! W( |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 t: C# L4 h$ z# UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 F9 s! r$ |) Z9 x' r3 W/ rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " J$ Y( B$ D! e0 O0 X0 y: g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* V3 o0 n5 w0 N3 C! l/ f0x00, 0xFF); /* configure the clock for transmitter */- O5 Y @# [! ]! _6 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" f% L9 g$ K p; RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & M( O W1 j+ m( z8 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 N- Y# y+ n/ x9 K2 E1 [0x00, 0xFF);
/ g' m" d( e1 z8 V) p
1 [3 O) o4 s# R5 W3 ~/* Enable synchronization of RX and TX sections */ * A& I& X0 q- B) Y/ I# ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ q3 j2 E, D9 w4 G- P' _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' e4 e g0 c1 W' `/ ^6 P) K4 WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: H9 O4 D' r& V: p** Set the serializers, Currently only one serializer is set as
) Z5 P9 | o, V% e5 X' n** transmitter and one serializer as receiver.
: o+ c1 g3 m1 i: x' c*/$ O7 l' s; ^: p, q4 R8 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" `$ V1 C- i: i4 ?( o$ Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 {: e: Z6 m* } {# I5 q: Y$ c** Configure the McASP pins
- p$ t. Z& Z% E5 b** Input - Frame Sync, Clock and Serializer Rx( V' y+ s! i# h& j7 y# `) v: \# {
** Output - Serializer Tx is connected to the input of the codec
: H7 D, I' x1 R0 Y2 i) \*/# F% o+ f4 N( O& H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 v* R3 ~# b* }5 l9 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. a* C+ C3 e% T3 W) ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
l5 k& M# P7 {1 y8 Z' r| MCASP_PIN_ACLKX
) h, g: M9 ^+ \) y; P| MCASP_PIN_AHCLKX/ K8 P' S/ I+ V2 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. [. k0 D3 n4 O+ j% u3 C; q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . b' V, v. b' ]# k( Z
| MCASP_TX_CLKFAIL
6 a! B$ \7 |; ]+ l| MCASP_TX_SYNCERROR" S. }9 H2 ?6 i- R7 ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. g$ C7 j3 o5 y2 m" M| MCASP_RX_CLKFAIL
1 A0 |# g5 w; f2 V% g" e| MCASP_RX_SYNCERROR 5 `5 T9 M8 f5 W7 m) d' z
| MCASP_RX_OVERRUN);
7 T' P# S K5 K) d} static void I2SDataTxRxActivate(void)* w1 c( \$ x2 n. C' @" q: u$ s
{1 s6 P9 [: h0 \. p4 s% A2 P% G
/* Start the clocks */
0 F. a9 C; X7 v$ w1 \' X/ t. sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 g+ c! `0 `5 b7 E. }3 E$ l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 f$ O4 A* P7 r9 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 |; C" W7 x+ m# d& J/ S2 A: ]1 ]EDMA3_TRIG_MODE_EVENT);9 z+ U. t3 M ^, N2 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # L! S& N7 r# _6 Y# W( H/ E0 i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 @8 D* C1 \8 @: J( jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 P5 k8 ]' ^# Y: m& LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 c* A# ~! R! X0 O+ P1 d3 Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 S9 h/ w7 V4 U3 D& G- p$ C: PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. G* G) q: g1 V8 W2 OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, d: @0 Y! {5 m0 S" l& I1 v2 S}
& ?& y8 q3 r* h: o* A6 v3 M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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