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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 M7 u/ b: A$ H: v5 t
input mcasp_ahclkx,
+ b/ b2 V4 V* x$ Y; uinput mcasp_aclkx,
$ F5 ~- O3 r- j8 {input axr0,( O6 i5 I: {9 d& Q# a! C
5 [$ P2 O: I2 w2 goutput mcasp_afsr,, `; r0 w+ ]8 m
output mcasp_ahclkr,
) k$ T1 x( `0 o5 W( W) i qoutput mcasp_aclkr,
! |. T }9 w. [3 }5 ^8 ~; x! d0 p+ goutput axr1,
" I! P& u! e! c/ C4 z2 I assign mcasp_afsr = mcasp_afsx;& f* a" @* f: @
assign mcasp_aclkr = mcasp_aclkx;. E2 ?% R! J: Z( L+ X) K; ^2 ?8 u
assign mcasp_ahclkr = mcasp_ahclkx;
; e9 H/ |! R/ \0 |3 O0 [assign axr1 = axr0;
; e) W, a2 T2 n9 o9 q( e: l6 R; a" }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 o5 @8 b o4 I
static void McASPI2SConfigure(void)
* W2 e, d) F8 I* X9 R4 [: J: c{3 @3 ~1 I( [) E( ~) J e) |7 @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% C1 N) M4 {& m& n. g8 ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( F9 Z1 {& Y$ l* D ^( }6 N2 T# P% X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 B8 B5 D* A3 x9 s2 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 R, F, Z3 L; {' qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, h, J d7 [ n3 T% @
MCASP_RX_MODE_DMA);
0 Y+ J8 J+ x4 _) IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 q" n5 ~& [! V, R+ n) {1 Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 c- X! m9 n; b" BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 H5 K$ E8 o3 E1 v1 Q/ `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: ~) P; n9 ~% ^) x8 M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : O( V' P. w2 w% h; `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ a' e/ |/ Z* y" R5 Y- u1 O/ L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 Q5 @# Z# P# G7 t/ VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ }* g7 Z' ~( g+ B, A& S% h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( K% n8 m( g' Y8 [0 Y4 ]4 t
0x00, 0xFF); /* configure the clock for transmitter */3 L7 i2 t1 T S/ E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 j' e8 C: I7 o. T: T" r" V1 k8 oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( d2 R% U: k8 ]# J5 l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% Z3 O% P' y! d. M% l0 q& v `0x00, 0xFF);8 h$ G, L4 g2 X& U" C( X( l/ ^
* a9 ]) \) R; |6 w. T) |1 D
/* Enable synchronization of RX and TX sections */ ! n% C: E* _8 h+ @: R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 Y* ]6 d+ f# u* t5 ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, g) f% l# q+ z4 RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 H! E# J* N- u4 Y7 @4 E** Set the serializers, Currently only one serializer is set as" I; a/ D4 K; Q: @6 j% {5 V' D
** transmitter and one serializer as receiver.
7 F) T& I' A; ?: H3 s*/
. k" S4 e# a( }0 l; BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' X7 t/ _. V; {5 S) S5 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* O8 n, X& M6 a3 V: y3 ]$ v
** Configure the McASP pins
- E" E) l; Z' L9 \$ ]7 {% c! |** Input - Frame Sync, Clock and Serializer Rx" Y: E0 l0 x2 R9 n, s+ t8 A
** Output - Serializer Tx is connected to the input of the codec
* ~! N" D3 d4 f* H! N/ N*/
5 n* U5 G5 F' V( y+ S; EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( o6 q: q5 C. g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* U( t/ G( L& p, K/ h1 @- vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: F2 D$ l& k+ Z2 M5 g5 S| MCASP_PIN_ACLKX/ w, M" \' D4 z# D. _( M
| MCASP_PIN_AHCLKX
3 ]1 O4 m f0 j8 t' J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: k/ B5 w' Y- u4 V: Y6 a4 NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 L( \7 D8 @5 W F6 |6 g| MCASP_TX_CLKFAIL
0 s- G" i! M n9 v; \5 V" ?! c| MCASP_TX_SYNCERROR2 Q8 \- S }4 J9 x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% l# q- Z9 d/ p4 Y$ X. e& p/ g' J| MCASP_RX_CLKFAIL9 F9 [3 K% d% m" a
| MCASP_RX_SYNCERROR 4 G( T. z% R' {- N6 a. B+ t
| MCASP_RX_OVERRUN);
* q6 P2 r1 s5 D: [" L} static void I2SDataTxRxActivate(void)1 L- Z$ C5 F0 |& O( Q# c% q
{7 Y( S$ p4 |3 y' ?
/* Start the clocks */& E p' U6 f; r9 V3 K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. \. C! P9 Q$ l4 M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; b0 l8 X! K5 G r- h4 w8 S+ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( t4 q6 d- S- v8 @1 V BEDMA3_TRIG_MODE_EVENT);7 ?& K- b% V# U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% x8 W e3 O% b" fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 I( ?1 I! \ m7 j( [/ }! n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ _ S: Y: z. k# C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, W1 k* @+ K, B3 Q1 `5 l6 e. Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. Q. b, b& Y' i, kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 [- T7 k; O1 }0 q( U1 d7 FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
P, _9 J& [- m: \7 f3 {: v7 @} , _1 _8 R$ q2 ?. L1 |1 l" u7 m" w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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