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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ b9 I6 O9 c- i3 t
input mcasp_ahclkx,# X% g) E( Q5 f8 B: [! G* K* f
input mcasp_aclkx,4 Z/ y! l0 Y+ g
input axr0,
: Q3 t- ^( h3 n) b+ ^* l" j# Y
# l7 ]! m. I% W+ ?# Youtput mcasp_afsr,
+ U2 z/ t" B8 M+ N$ n0 Moutput mcasp_ahclkr,
# i, R. `! u# P5 o1 t1 k+ moutput mcasp_aclkr,
, a) @+ C4 u$ h$ Aoutput axr1,
9 b0 T0 R0 Z1 @, P+ k! \8 d assign mcasp_afsr = mcasp_afsx;" |1 j1 a9 Y* a
assign mcasp_aclkr = mcasp_aclkx;; b% I P+ W+ r \1 F0 [% N
assign mcasp_ahclkr = mcasp_ahclkx;3 | m q* B- g
assign axr1 = axr0; 8 f% c+ W! u" o1 J, h
1 z- Z, S( U6 K! O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 v' n G+ e) R/ d/ c0 V9 f, |
static void McASPI2SConfigure(void)1 p9 M5 T3 r6 r/ D
{+ d% c1 u7 l8 V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- L J1 [/ M/ x! m9 B1 Y1 x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# G9 {* [& o/ v Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 C1 h& k7 w6 {- HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, E5 J! Q5 {/ @! k# B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," T; L6 ]3 y1 u; W! S" j
MCASP_RX_MODE_DMA);. j6 n4 O M1 m$ Q1 r# r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 M1 a$ j9 V8 ^7 X5 ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: ], b/ K! q2 e6 j# i& F! E# X9 zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! ~3 i7 X7 K. a: g& Y, n4 R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ E% Y4 B9 m$ s) Z: g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 B+ N! o+ f9 h {& Q5 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 [7 B/ A) w4 o9 v7 E" | b# c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& q- |; Y3 i* ~" I0 h7 G, Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# t6 |8 Z, ?3 N9 o' EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ ]% ^, Y6 ~+ }) H- u1 E3 A
0x00, 0xFF); /* configure the clock for transmitter */% h0 g; B. f' E0 G+ v8 \8 h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 t1 }4 S8 j4 }8 SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 v- Q# M& T! ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, J/ F( C; W4 T. h0x00, 0xFF);
; G: C# p! i! l! X- u1 ~
5 S# Z# }/ B, Q/* Enable synchronization of RX and TX sections */
3 t9 L2 m0 A! L" A |- H" SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 C" g5 M2 @' F% \& UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* X4 b9 I% O/ }6 jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 h5 B+ I$ K" G5 _9 r) S0 z** Set the serializers, Currently only one serializer is set as
6 o3 d# H+ C. n; Q2 L5 j+ P** transmitter and one serializer as receiver.
/ A6 c- ]2 W ~*/
8 g' M* q9 S( {" QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' I% @- G! ~9 r/ M1 \# i& MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 n% N8 E7 |: y o0 m; C** Configure the McASP pins
# b q4 H0 Z0 S$ t% Z* }** Input - Frame Sync, Clock and Serializer Rx. w& ^. |7 `) y, |1 W/ d' F: l3 o
** Output - Serializer Tx is connected to the input of the codec # E' t* G2 m( ~: M; Q' p0 ~1 c/ W/ j
*/
$ p' L+ O0 I/ g7 y3 w( ]) pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. h! x) s$ g. T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* V2 ?7 j; m$ K, n. j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ a2 a. _& ^; Z( A, O1 u| MCASP_PIN_ACLKX# H U- y3 Z7 M- o% p
| MCASP_PIN_AHCLKX
: v3 ]6 M( P/ Q) K5 E0 d+ y# N5 z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( ]' }. I" o: n! VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . c) j5 X! v8 b3 e* {1 A
| MCASP_TX_CLKFAIL
: n9 h- ?9 N8 l* q% M3 b| MCASP_TX_SYNCERROR
: n5 }2 d( W, ?' j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 g5 F% D# Y' D! g
| MCASP_RX_CLKFAIL6 y& M1 R5 ]3 {. l& G! X8 M
| MCASP_RX_SYNCERROR
! k6 X, @) G5 e: @- E| MCASP_RX_OVERRUN);2 _ P. F$ U0 y
} static void I2SDataTxRxActivate(void)
9 o1 V6 I: K! `- T{# W9 A" _! q% I
/* Start the clocks */; ]) v4 g( v, H! S* e/ P) _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( W, m9 Y1 [! S7 C% N% m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 [/ o; H& k+ x) b; TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 O* [. t9 Y" Z; c
EDMA3_TRIG_MODE_EVENT);
* q9 E% p! P) L. g6 Y JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : @) y# v0 O8 ?2 ~; `: }) L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 }' z) v. d$ u1 R' Q/ b8 f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; q- [6 h* V0 X' k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* Q4 a% |3 R Q& X* A6 A) A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% {# {3 ^! U- e8 }! N( uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) t6 E% i9 C% q$ t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- _& t7 ~, r: ?$ V
} . G+ _% {* K9 v, |2 z1 U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( ~% w- K( v. h# S4 K4 _6 S
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