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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; v! h% H7 D3 q& D, p( J. y
input mcasp_ahclkx,# N1 L8 ~' K$ Q; w' W
input mcasp_aclkx,8 E/ ]/ T Y" ?7 l* z! G
input axr0,
+ q# x/ d! J3 |- v- V
$ H7 f3 p9 v, M: Eoutput mcasp_afsr,
1 h, y9 H0 B" W. Zoutput mcasp_ahclkr,
7 [% V$ ?% I! m+ Y# O! u: Boutput mcasp_aclkr,
6 k: B- o* f' h% Koutput axr1,
+ C8 s( ^' y/ A1 b$ y$ C assign mcasp_afsr = mcasp_afsx;
7 X% E' u$ A/ |assign mcasp_aclkr = mcasp_aclkx;+ x! S$ p, O* B- V/ v
assign mcasp_ahclkr = mcasp_ahclkx;7 d2 l! x( u2 G& ?
assign axr1 = axr0;
6 t% d$ j; k: {2 U; O+ W9 _* T+ X3 [% R2 q( i' x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + D( r" B" ? j- M& F% c
static void McASPI2SConfigure(void)
9 k' j b/ h/ Y: n. ^{
7 V3 `1 h/ e3 S; d0 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS); Z7 m# e3 {) ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, n+ z! S6 t" J$ y$ r# O5 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% \+ r$ j- J& {+ Q& `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 [1 X& N/ a2 jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- L% l, N9 {/ x0 F
MCASP_RX_MODE_DMA);
4 d( j f% R [; I- bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( q D Y$ u2 I! p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; t2 K( {1 f+ I0 p% `' ~% R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! T: K5 `/ J! [. TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& I- e |2 g' C. H3 x. A- W( H% v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' H4 Y0 ?' K! C. gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 E+ m' H! m; f9 `/ ~ qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) q3 G$ a# I9 x0 G' x/ x* d3 |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ j: o/ c' u/ C0 c$ T( B' M1 a NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, O) s$ l# _3 d
0x00, 0xFF); /* configure the clock for transmitter */
( h/ y$ ]. @: RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 m1 S4 w$ p0 Q; J$ U, [8 p+ }' i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* x' d4 G- S" \0 h, oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 ?+ B G; @$ Q6 l6 q
0x00, 0xFF);$ m% k. \. e$ f; c
0 p( s# [ m" K1 Y
/* Enable synchronization of RX and TX sections */ ( X8 T4 d4 N1 Z' d9 j. D' ?, C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ _: M% H8 \7 x5 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; g: \9 y7 t0 ? v% L1 RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 w6 i6 \- [+ Q0 k** Set the serializers, Currently only one serializer is set as; T. X8 t* P9 |% B& b% O+ D" T. Q" {
** transmitter and one serializer as receiver.
, k3 r3 V# X) W+ X5 K6 G9 ]6 q*/5 @( O9 c+ R& i2 i. H- T+ m& Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' @* @4 j3 c* w( y) a& O8 k7 [ o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 m% f. ]2 U9 b) }
** Configure the McASP pins
. _7 O7 O5 x1 q) G** Input - Frame Sync, Clock and Serializer Rx, U k' X5 a' ^3 ]8 h7 ?
** Output - Serializer Tx is connected to the input of the codec 1 p+ Z3 q) Z/ Q) F, j- m* S, r' u
*/5 X" O" h B0 t0 x( _# S! E) Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 w. e( Y% f6 L/ }: j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* N: d# c7 a/ ?* L1 x: f6 j7 AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% {8 T v P( H& A# m/ `2 q| MCASP_PIN_ACLKX1 D {0 i( d/ K& z; A
| MCASP_PIN_AHCLKX
|9 Z3 t6 J$ v5 V8 P' n. s# N' \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 D. J$ a; U5 E! CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # U, V1 J2 x7 m7 ^
| MCASP_TX_CLKFAIL 2 T/ k1 H9 _+ P# B
| MCASP_TX_SYNCERROR: o$ p2 k' x6 J4 e* g. p( i: {& X2 k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 n. y; V, X' w/ ^; c
| MCASP_RX_CLKFAIL
: L: p( R" l2 i, p j) _| MCASP_RX_SYNCERROR / o, K, I5 a& @/ |
| MCASP_RX_OVERRUN);. }0 P. x, R! o/ h3 x
} static void I2SDataTxRxActivate(void)
Y: b q7 k; A{3 K* n8 Z" L+ g, f: k7 @
/* Start the clocks */
' I8 f/ ]1 Y( D7 h0 V! d5 \' qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# ^6 M" b( [$ d5 j5 d" C& j" x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ W/ W( R* i7 l- j/ U3 T% y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; @0 y3 G, r, Y6 YEDMA3_TRIG_MODE_EVENT);; |8 K% W( K4 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 Q% b; Z5 A3 [1 I+ mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 S* k7 i, ^2 `) d9 g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); Q/ A4 l* s$ G& k7 o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. i# j+ a9 u8 y7 z7 w. `) s! swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! Z% i) Q, D# B. g' K; n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 R% b, X- Y3 H' N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. u5 u! P% H8 U+ Q
} 7 m2 w4 b9 u9 U+ ]5 F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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