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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ t4 ^; y! n! R7 r/ l+ V
input mcasp_ahclkx,7 q) [/ m5 X% X$ J
input mcasp_aclkx,/ u% q- h& k- ?
input axr0,
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output mcasp_afsr,
4 L8 S# K, I# ]* T! _6 s: {- soutput mcasp_ahclkr,
* W* I6 t/ _' Y1 ]2 f; n# soutput mcasp_aclkr,1 w z) I/ Z% ^, \' P0 v
output axr1,& b0 g0 h; U2 i) q. W& y$ r
assign mcasp_afsr = mcasp_afsx;; F# R3 N* ~7 n, G1 L Q0 ?4 d
assign mcasp_aclkr = mcasp_aclkx;( c8 H3 b" |% G0 E
assign mcasp_ahclkr = mcasp_ahclkx;
1 r+ t8 h; N% n8 [assign axr1 = axr0; ) y% a4 z# N0 N/ P% W- A
' T5 K5 J! V, x1 ~0 V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) c( |7 H$ R: t. R# T
static void McASPI2SConfigure(void)
' i2 ^5 }6 s4 C% M{/ B% f5 A# O" E( u+ @0 V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 @( J& X- S( ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& ?3 ^+ L8 S7 `0 _% vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 w2 T* }9 P- G* WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' [% q1 h |/ M, }; hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 W& H$ ^ E* X9 b* i4 O4 a9 lMCASP_RX_MODE_DMA);
2 h" ?+ N6 p P3 b2 B! r' }: I9 d2 SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) l1 B1 r' R2 A* T. FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 Z( [( ?: R f% d) C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " F1 @$ X' l6 W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& w) O+ q, N$ K' W. D7 K9 |) l) EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ O1 a/ |. Y ~2 l& L' K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: \1 ^# R- V6 J% m nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 b& k& P( x5 n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 ?8 M, }; M( f8 ^3 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ q" h0 G! f9 `9 h/ b# \
0x00, 0xFF); /* configure the clock for transmitter */; U U* N& f8 A5 m! {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 z) u& @; D% M! m3 m( s# Q5 U" u# b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / y3 L( p2 c9 Y R1 Y. ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& M* V. {$ T: t) Z4 }2 p
0x00, 0xFF);! o% f, v$ a, r. j
& i3 _5 T( c, Q4 `9 C
/* Enable synchronization of RX and TX sections */ ! P! {- v% m) s" I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 c/ @1 J! E, |% E- hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 z: \) R, {/ | \% n# u7 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 w* j3 @1 ?+ x: G; K4 a
** Set the serializers, Currently only one serializer is set as
5 T# e2 B; I8 K** transmitter and one serializer as receiver., c- Z* i6 L7 b) M4 R# F! e7 z r' D
*/
3 ^" {% j# m) i! QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 S* Z# x# y; h4 e7 ~) nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) n. h8 [. r; X$ A. W** Configure the McASP pins
! L5 q( C% p6 ^. f** Input - Frame Sync, Clock and Serializer Rx
* u" z# B% L4 W$ r! ]9 E% ?4 q** Output - Serializer Tx is connected to the input of the codec
5 ^1 \. D5 i; h; i*/
- v0 I5 E9 w6 H: [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. ~' X; ~7 e. ?; h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 i) W, m' c6 v0 G T0 o, H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; ^2 ?" q" t: I| MCASP_PIN_ACLKX
w* I( w7 F: n* T9 J, V| MCASP_PIN_AHCLKX
4 Y: S$ Z i0 h' H2 R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. w# b# Q# p. X1 ]- L; {- R2 n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( Y2 ~( x% G% @5 U1 P| MCASP_TX_CLKFAIL 8 v4 F. w6 R3 p; ?( { A
| MCASP_TX_SYNCERROR
N' i8 w% f( a8 C# S; K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 a, v9 J q J3 Y! A4 ], i& w
| MCASP_RX_CLKFAIL
5 U$ d! s& A8 T. v5 g| MCASP_RX_SYNCERROR / w) p$ G: C' [/ T, O- {
| MCASP_RX_OVERRUN);* B* {1 v9 ?/ T9 T& B
} static void I2SDataTxRxActivate(void)& ]2 O% x- p' A( I8 V r
{1 b. _' X4 }0 d8 b
/* Start the clocks */( x4 f6 I v) i. Q# G) @! c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 s* M$ {! O( M3 p9 P; |5 pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# q$ I2 W% [0 e1 ?% O* U8 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 j0 x9 r, L$ R) P+ l2 F* j6 d" y* Y
EDMA3_TRIG_MODE_EVENT);
1 A, j- I3 J5 H0 \# X0 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% Q& ?9 ^6 A" R1 u/ k. Y- WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// e6 p: |) D9 r# W3 e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: Y4 G# f s% |: x5 P7 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 ?- P+ |. o2 Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, B! x4 S- K; z0 j U8 A. Y1 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 V0 l1 v1 m& y/ c& J; W6 }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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