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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ }3 O$ a0 m, c* Linput mcasp_ahclkx,
" R+ T- f& |( ] f- i0 qinput mcasp_aclkx,
! m8 W/ n p/ a- R" ]7 x4 Dinput axr0,
; L# e/ ~* J, K2 g2 \, }1 A1 w X4 k8 ?# c: x% b
output mcasp_afsr, W2 j8 U1 |1 v
output mcasp_ahclkr,
$ d4 G, C7 _+ V* S# noutput mcasp_aclkr,
4 R# e% H2 _3 i5 t, Y ]/ \: zoutput axr1,
/ ^! P4 \# }$ o4 y Q assign mcasp_afsr = mcasp_afsx;
. i* f# d1 m) Y4 ?) _3 u$ A Eassign mcasp_aclkr = mcasp_aclkx;
1 \! z1 I4 K& T: K: i. ^assign mcasp_ahclkr = mcasp_ahclkx;. }; j9 q0 S9 N5 \" H
assign axr1 = axr0; ; k ^2 h7 g" G; Z" U2 B0 D7 U
i+ N, }' T) m/ p7 ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / u$ g v0 I9 S! J w. u. ^3 M
static void McASPI2SConfigure(void)1 L$ {# [3 ]7 X& K6 w) p
{" t1 J. f7 s+ D6 Q! p" i2 c, K6 E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 Y. {: @& s4 q' ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 M" ?% N5 I6 hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& J# S1 I# e4 e+ b3 x0 E4 u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. L9 e+ [+ j9 \* b8 O( p8 E' `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! E5 k/ ]% Q0 Q8 L0 O4 A3 V4 v2 XMCASP_RX_MODE_DMA);" H6 P) {' y+ G( Y" `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ m8 M0 Y1 Q" j' qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 s, K! N( H* ]* BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# [8 b) ?6 C$ T& k$ ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 c5 h5 P+ m2 k7 x6 ^; f7 o qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# @0 ?, ]$ O- A: N& r8 a' MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ K6 T3 a9 p8 o0 n8 s7 `9 R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 m; `! ~( l2 g, _: A/ F( `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , p4 t9 r& C4 {- \% {! M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 o; y5 \1 B: r ~4 p0x00, 0xFF); /* configure the clock for transmitter */
' S( M7 O7 Y8 Q& Y6 F& _$ rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" ?9 s. H5 a3 v/ A" }* m DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 r" p3 H# R) V1 ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 B7 E. \$ |" U' y5 i: i0x00, 0xFF);9 n$ u- I/ A' G% e7 b
( r* d) R0 E. u. K' X
/* Enable synchronization of RX and TX sections */ 4 U' r+ [3 l; M6 _3 J- u! p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# P. d- @9 f8 K3 M f$ ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& |' H+ A- E" c4 ^! I I" ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 b0 G M. G; F- F1 h- _+ ?- @3 I
** Set the serializers, Currently only one serializer is set as9 \5 f* u% \4 `" M- g* N
** transmitter and one serializer as receiver.9 h% ?$ y; C+ j& z G
*/, j* `7 {2 E7 p. Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 L+ T K& \9 n% m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 N" q* _" D! d& e+ J P7 y- O- C** Configure the McASP pins ! V, A6 d4 [* s
** Input - Frame Sync, Clock and Serializer Rx3 u' [: L# b8 R8 }
** Output - Serializer Tx is connected to the input of the codec 0 @# W& V0 Z7 b
*/
- i; ?& H6 f. ]" d6 g8 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 r- X, v% P- ^, Y% h, K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; S2 S. }0 l- ?( z6 }. @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 I+ ~; f; E1 P8 \| MCASP_PIN_ACLKX1 Q3 S, v3 q @/ |% |0 e+ h$ p
| MCASP_PIN_AHCLKX
0 @) C( X8 [: j8 B: `6 U# p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ g% N- m5 i9 H- f% QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 p2 d* k( C i/ G( _| MCASP_TX_CLKFAIL 7 H9 U$ q% @' V- O: |
| MCASP_TX_SYNCERROR6 D# L7 ]- U( m3 Y9 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
e8 j. o2 |( c" |' }6 t, d/ v| MCASP_RX_CLKFAIL- G" ?; ^$ U& o7 v2 t, k
| MCASP_RX_SYNCERROR
" @2 }, r& C. e" q| MCASP_RX_OVERRUN);
) Z. t; b4 C4 {} static void I2SDataTxRxActivate(void)
5 w) B" K- q8 A. n* C{& Z" L- `5 p O5 q a- n. [' i
/* Start the clocks */7 v* j/ ^, i& V8 h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- z! u% J% ]) [2 e S8 t) T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 s6 K4 j$ W# mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 Y% Z- ^) K0 W; N- Y; M! r
EDMA3_TRIG_MODE_EVENT);$ d C! ?* \& H1 t/ W$ J$ ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # [0 y2 ]2 @. Z2 M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# T; o8 \. U) ?) @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: x* b+ l" v4 V7 YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; z9 a9 ^5 Z) R% U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% u& ~: }- R+ q2 F6 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- C! X& X; f$ M0 N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% {4 }5 ?8 q1 {1 M, G}
u8 D- l+ @4 t/ H+ s$ i+ m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; _3 j' u' Y& A
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