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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 i' X9 z( _5 i ]input mcasp_ahclkx,
' _4 i- d/ `% d0 W4 W# Z7 A5 finput mcasp_aclkx,' M% |; s% Y, r+ z: @5 ] M" g$ F
input axr0,
8 \ n& j% ]$ s/ E6 z) Z! h% A5 G# P- Q/ S3 g
output mcasp_afsr,
; e! i7 O, S& f& s! j: P4 Doutput mcasp_ahclkr,
( U% C/ Q; s7 _* G! u1 O! ?( Foutput mcasp_aclkr,
4 w0 \: V* ]% T# w" p1 Houtput axr1,/ R% c& y+ j9 y+ F. J) x. \( d+ m
assign mcasp_afsr = mcasp_afsx;( M: j3 u, `$ D- X$ x! r! O) m
assign mcasp_aclkr = mcasp_aclkx;
4 A) q( _1 t; r& V, {assign mcasp_ahclkr = mcasp_ahclkx;: S; N. @5 U$ i- K
assign axr1 = axr0; 0 o8 K" {9 c6 a' o
+ ?6 J& l1 J1 L. H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ Y8 |8 I, Q9 nstatic void McASPI2SConfigure(void)6 y6 E1 I) |. a4 }, _' L6 H: b7 ?( N
{
" i1 _$ Z( l! L: X, S/ O5 I/ vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) }- z# o7 M- X( f8 k; qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' |2 f J8 ~% S4 b ^# H# a2 L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ m D3 D" a/ M1 ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" t8 J6 X/ a7 D! h4 u8 D o) eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) T3 F% F$ i9 L* T4 }" Q
MCASP_RX_MODE_DMA);' I O$ [; h2 l5 l( x) T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ }( ~1 l8 _9 X5 U- XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& |- `9 U: P }/ Y, a S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , s+ T, v8 l' X/ J: E# J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 J: B- Y: @1 H9 k- `# h+ G/ }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , U6 S+ q3 n% b c: j" W3 u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 u! r. \5 u! g) S h' V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. X) h" K& [- b" T: A( {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . L! {3 ?! K! {+ D, `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 S% F- a! o% q! d
0x00, 0xFF); /* configure the clock for transmitter */) p8 Z0 |$ ~ a: {" b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# u% L0 J& y- f7 N9 [' p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ C3 {+ L! u" \) a3 l; nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; l+ z( ]! l: K$ X: f0 W% y/ a
0x00, 0xFF);- k& b4 c' @2 W- r3 l
+ f# u/ u* E. X8 R! | {' I/* Enable synchronization of RX and TX sections */ ! \# M( c2 u( P! V4 D+ V6 I5 P: p! G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. X- w. \" \0 u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* G' n6 M- t- E0 k+ a8 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. h. ?* m% `8 d** Set the serializers, Currently only one serializer is set as; k& i1 B% E% B$ l" j4 i+ V- N
** transmitter and one serializer as receiver.
: L4 ?! F* ^7 F*/
1 [8 c: G4 Z" W" f- ~4 vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! h- D: ~, t+ R2 P0 @+ m" d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' W$ w2 {1 l! I** Configure the McASP pins
& a6 [# h" x1 I" g** Input - Frame Sync, Clock and Serializer Rx
3 }9 I3 h7 L5 m# H0 L** Output - Serializer Tx is connected to the input of the codec
& p O8 i6 V' o9 E1 _*/3 L# ^- |9 M4 y: r% p. t. n U6 E% f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 F. I+ j5 P1 Y" l9 @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! q' w$ q7 V/ GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, [% B1 w. h' F0 n0 z| MCASP_PIN_ACLKX; V1 J6 D% [9 U2 u7 I# R+ _
| MCASP_PIN_AHCLKX# i3 j5 y2 U* i4 b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, K9 ^& J, v& ~3 t( |- FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! K* I t3 a7 j, p
| MCASP_TX_CLKFAIL
/ f2 B' S9 G' p* f3 ~9 I| MCASP_TX_SYNCERROR
0 H0 x+ C3 p+ r, ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 _' U7 G0 o5 t3 U$ R& G" o
| MCASP_RX_CLKFAIL w$ ]* d- ?+ W5 P0 v; O
| MCASP_RX_SYNCERROR 4 A8 s0 M0 } t$ L- y2 @
| MCASP_RX_OVERRUN);
( o q& Q+ R2 T. P% d G} static void I2SDataTxRxActivate(void)
) N2 |- m, M3 N; A& |3 @. k o& X! |{1 X, l& f/ T2 I
/* Start the clocks */
6 T# ?! p4 ]0 y" `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 o! v6 l7 A8 x+ _/ JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% X: }2 D2 n% p% w1 v1 p6 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- ^6 k" Q7 s5 x
EDMA3_TRIG_MODE_EVENT);; D! ?' a8 A. \9 \4 F5 t* I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, s. O$ F& P9 b1 l1 a9 K$ oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 z" R/ f; N6 E( O9 m/ V/ v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, u( m) o" _/ [- f6 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 v' r: t2 {7 Y" ?6 E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 \: D" }) z3 D' b; s& F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* g# t- C. o# F, pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, c/ m/ [/ K! s% m- ?} ( `5 T& r n( V( z! v! M0 ]/ }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : c3 K- p% R1 l; p1 J+ U1 J1 G
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