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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, W1 H, f) F3 w7 t2 k) b- n
input mcasp_ahclkx,
& G: ~1 O- R+ l' V% g8 Linput mcasp_aclkx,' q7 O3 Q& W0 J8 ]. b9 ^
input axr0,6 I- `7 l" U0 V. T/ O( {
9 q6 Q! p# h) T( ]6 O$ F( A9 k+ ]
output mcasp_afsr,
9 q9 B" s0 n1 Poutput mcasp_ahclkr,: p) T! T6 R% l; ^5 Y- C- g
output mcasp_aclkr,8 @. W2 o6 m+ K. M. ?
output axr1,* s$ f( }" T0 C" H
assign mcasp_afsr = mcasp_afsx; K" `1 j" t" E$ f" T/ V1 k4 b7 d
assign mcasp_aclkr = mcasp_aclkx;
+ s+ u8 F. k; c# Y4 l! Uassign mcasp_ahclkr = mcasp_ahclkx;3 P# _6 O) q- B" {* J1 H' Q/ ]* x: w# u
assign axr1 = axr0; " j: e- z. h c/ p1 X
- c) W) v6 E/ w: _0 X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 l2 u! H% k# R: i: Estatic void McASPI2SConfigure(void) W& a; S& G% U V+ a% q
{1 r, o; g+ @ l* v2 o2 B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 R Z: b, h2 v3 K3 z: Y+ `- E, Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ ~2 x3 M8 k" j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ C- ]0 K3 O- s7 T# f" |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! v% Q h3 n! A2 O4 O0 F. Y- g! g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# h, ^$ R' c: I! t0 s! b% a+ V
MCASP_RX_MODE_DMA);
' n4 I- s, E: iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 L4 l- G, X D! C: e/ B+ v0 L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- ]! @$ ~' z& g$ ]2 ]/ ?" V/ g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ N* ]8 s0 }9 R$ u/ D* C, J' j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" I i+ c4 f1 e, |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 R) R. ?! y8 m1 l' ?2 ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ e, M) W6 x: |" C4 hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ F' w; y' ?0 ^; s. ~( G+ qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); b1 u7 y; S( U3 ^% s: E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! S8 g( \& G! Z" A" h" O+ Q0x00, 0xFF); /* configure the clock for transmitter */$ T% B9 o$ q3 Y# C" n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. j6 H# Y, W P7 a8 d( u" ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% T" H& U1 W n5 I# X( d4 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' p: q& n7 y7 x. [+ I6 k+ [ m' I* G0x00, 0xFF);2 e8 h; S. f$ m' e
4 a U9 F3 N9 Y2 o& q! G9 x
/* Enable synchronization of RX and TX sections */
* X# X6 Z# A, w# \% j" KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: V' e j, N" {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! W. @0 O+ U! z s: H4 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 `! C/ }, q5 U# ^/ _** Set the serializers, Currently only one serializer is set as& R' X9 B$ n, j6 ?- r* Z
** transmitter and one serializer as receiver.
$ H* w* [+ O: ~0 B. {*/
/ W7 @- f' r5 v+ l# o2 X; h/ @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 [4 D% k1 ?$ @* J# f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 ~( K$ s" K n8 l** Configure the McASP pins
& N, B9 p, `# `# m, L) d9 R$ E** Input - Frame Sync, Clock and Serializer Rx
+ F- Z! B5 P, T1 \3 n" f** Output - Serializer Tx is connected to the input of the codec
( E. ]& W1 e3 _5 ]: g3 F! L*/3 Z A3 `9 G" l( K; S" I$ i4 K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 o# j4 F2 j* p/ e6 }* P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' B2 J6 U( Q5 }; G& e4 j$ y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 O# r- Z4 u" M2 a# R9 F" ^- y
| MCASP_PIN_ACLKX4 @, X) A6 T% m" n& y& }' N1 c& [! f6 r
| MCASP_PIN_AHCLKX7 R+ q2 c l. V6 t0 \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% a. [" I8 S( j% g7 [; [/ eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " ?( `4 w: W( f6 B" W8 Z5 G
| MCASP_TX_CLKFAIL / Q( {. s, J1 [/ Z5 n9 t% d
| MCASP_TX_SYNCERROR
7 s3 ]$ ~# [7 @& Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 I: t* c' x4 Z7 a6 y5 }| MCASP_RX_CLKFAIL, `) l8 y. S/ z `5 A8 a- }
| MCASP_RX_SYNCERROR : l5 R0 ^2 g* m- n: W
| MCASP_RX_OVERRUN);
' q2 f j: H e6 M$ o. u} static void I2SDataTxRxActivate(void)0 S1 ^8 g& A) r& {6 o3 w
{2 P+ {, W" [0 Y G7 C! n$ N
/* Start the clocks */3 V2 O0 {6 H6 [: O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 [; o* z+ B+ p* |1 S" X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// f/ ?' H1 t0 l9 ~2 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 l+ n# L7 D, w5 S9 FEDMA3_TRIG_MODE_EVENT);
5 T$ b9 Y; N+ t! U9 W4 }, vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% i1 p4 x& T& C) b# u( l5 S: G! REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 w1 j% `/ _1 K$ ~5 F. B6 Y5 b: [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' g+ a) C9 C" ]' i, mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 q- P8 {( ~" B7 C& B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) t8 o5 Q! V5 r5 S1 d$ J7 l1 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 t) z* s. ]8 Z% g% w: YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) O6 K% i% Q+ v5 `9 E7 y: X$ E
} 5 Q! ^" M8 z+ g( V7 \( ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + Z, I" g" o% d* @
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