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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 X) a& B6 \$ m. Qinput mcasp_ahclkx,
) U- D) N/ {9 { s2 _1 |& z) ^- Qinput mcasp_aclkx,/ [ p( _; s; u; d% D
input axr0,$ L2 Y! q- r C# Z) b
o' F' m: A' x9 {$ \+ s6 Toutput mcasp_afsr,+ `; x1 j6 C3 a1 m1 U! B* K% {
output mcasp_ahclkr,* ]( _9 ~! }0 }+ h
output mcasp_aclkr,
8 P0 W/ \! E+ f+ {0 J% O1 k. Aoutput axr1,
1 e* p% }- [/ }. } assign mcasp_afsr = mcasp_afsx;
# J& D; w4 K5 Hassign mcasp_aclkr = mcasp_aclkx;3 [; K$ h0 T, t$ F" S* C
assign mcasp_ahclkr = mcasp_ahclkx;$ e* r! _' K# Z5 X
assign axr1 = axr0; $ ?8 k8 H' v% l+ H+ f
& z3 ^" l# a, P3 t5 C5 ~* ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 d: {6 J0 ]0 M% b; J
static void McASPI2SConfigure(void)! s. g3 T' O0 Q; P
{
9 L9 E. v* t% c! ~3 H3 b: iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 e9 N$ V3 ]5 x( a5 OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// `2 J9 m8 F# w1 |# w3 S7 ?* z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 Q. {$ m# A) E: |( D) i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! `8 f& j$ |. r8 o) Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ g) Z& e$ p4 L0 y rMCASP_RX_MODE_DMA);" u) ^9 G7 |' v- l5 q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: m- a$ k2 S9 F/ J T; JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ k/ {) C9 U* U1 A8 x+ y; Q. [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( X' l6 t5 m" Z! l; f3 L7 f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# g' m1 N6 n. [" S/ a3 |" s" O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 _9 {4 ]1 F( L, s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& i* s4 @0 h6 \. p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" ~& q8 t- w7 P1 k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ H" i5 [' `- K6 |" }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% h7 T# k) H; h, X0x00, 0xFF); /* configure the clock for transmitter */# L0 b* h+ K- r5 E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( A' P: u" N/ v( Y+ N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); K- }, Y1 Z, x9 l0 E" p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ C2 A. N! i1 u6 ~3 x% Z
0x00, 0xFF);
" x4 V2 O, h+ K5 B9 x8 M( y9 H: v- z) _1 y. d: @8 N
/* Enable synchronization of RX and TX sections */ 0 O+ n- g! y9 q0 q1 X1 [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 H3 I+ {6 K3 [$ H' [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ d- q2 f& U" z9 q+ h8 b6 G' nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 {$ J) o7 B; p** Set the serializers, Currently only one serializer is set as
1 e! N e+ Z- p9 E6 L& X** transmitter and one serializer as receiver. Q# V1 b$ ^. Q; Q
*/
# u* Y& B% ?2 x/ OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 W7 B( q5 j1 [& u9 ~# ]5 f/ s3 V& [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 r7 h; N, \2 Y$ u/ ~** Configure the McASP pins
/ G8 r- F# B- z: X! [. Y3 ^** Input - Frame Sync, Clock and Serializer Rx
& V' H9 W$ [( C J1 p. x+ [** Output - Serializer Tx is connected to the input of the codec
( x4 |! V! m- q& ?, O*/
% \" o8 W; J4 s+ uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! I; Q/ Q0 p3 E2 I" j1 M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- ?" j0 y' o B0 R) `' _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- j7 c. r- J# M( J4 N& Y. Q/ [| MCASP_PIN_ACLKX
) D3 f% G9 ?5 e; u| MCASP_PIN_AHCLKX
D' B" l( ?4 n' h/ w- g, @% Q6 @& O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: Y* n6 F" Y4 V2 M1 H& I5 rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % \) w+ Q. |5 h. h
| MCASP_TX_CLKFAIL
T; u( U9 r! d| MCASP_TX_SYNCERROR
/ H8 d* b- b+ \: T) U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 G* l9 e& ^$ b$ A0 T| MCASP_RX_CLKFAIL
0 t- M$ Z B# A* A1 r' || MCASP_RX_SYNCERROR * q$ S" c; w) H q; J
| MCASP_RX_OVERRUN);! @5 w6 e) K/ e' S) g1 K# a
} static void I2SDataTxRxActivate(void)3 X% ]6 S' [" p( L$ H7 w
{4 u2 |, p1 P3 O( C, F8 _( g/ O
/* Start the clocks */
0 E" U# F1 Q- T5 c+ AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ r3 P* U9 x/ b' S4 E& K, |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 v! x5 X- @6 i: qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 O$ I. W1 C$ S& s
EDMA3_TRIG_MODE_EVENT);
! m4 L/ o' q4 E/ N* BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* y O4 [* |1 p' n$ ]+ hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% ^5 W& b. T# SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( L7 D& q- v- C: k+ E* U: RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. i5 N, O2 f5 B& ^2 L- _ H. O) zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# Y: r3 T0 [: g; i) s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* A% c+ }( X# m" V, z, ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- k! ~, Q. b& Y$ F' @}
2 a$ a: {; l5 }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 g5 ]# S& B$ d) j9 s5 \( b8 y |