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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- s* Y( e1 l$ s$ |/ Y
input mcasp_ahclkx,: e6 o2 |; _1 v+ P
input mcasp_aclkx,
! R9 B( y& V, x8 H4 Q! dinput axr0,1 s& ]2 p' H% [8 C/ _
0 e- A" W, L( g" {7 aoutput mcasp_afsr,
8 k6 ^+ t" n) a& |& n7 u6 Koutput mcasp_ahclkr,
& I7 j% h. N" b; N+ q+ Ooutput mcasp_aclkr,! B* _0 p: }' D; }% g0 Y/ ?
output axr1,0 T6 d9 k9 |' T9 }. l
assign mcasp_afsr = mcasp_afsx;
' J* G& Y& I* b6 B* zassign mcasp_aclkr = mcasp_aclkx;
, B6 |9 e- H3 B, ^) ~/ ]' tassign mcasp_ahclkr = mcasp_ahclkx;7 |* |; H: y% n! }
assign axr1 = axr0;
# n; @9 J0 Z$ J$ L
- i3 W1 [: }$ S. \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 q2 b) d; w; u1 Q9 mstatic void McASPI2SConfigure(void)* v) |) e: P6 R
{4 I2 p2 }" |# v* w+ ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! N& L9 i0 a/ y* X6 yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ q5 G. ]0 ?" m3 `7 Z0 c3 X, W' Y1 MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, V6 E0 X M% Z7 B4 u( q# M$ KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ d; D) ~ j: E& A# W, y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% l3 \. [& H, s3 f
MCASP_RX_MODE_DMA);
! ^9 G0 f, F5 |9 D3 PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' {; E0 W' w' j, C% |2 u4 I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
K& x: `* U( @9 xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 l( R6 H: E( k) FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 T0 S! F, e ~/ XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 ]' W2 l& C5 e$ pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; V: \2 m6 L X6 VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 ^7 y" P8 M' kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 P& F: p; P: k: D" g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# u! _" E" b' w2 W3 r( Z9 Y* a" I0x00, 0xFF); /* configure the clock for transmitter */. ]2 D( }2 l' O: M4 A+ Y1 B# _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* J( p2 Z ^1 X* t SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % D* r0 k' j# G# V1 R" `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) J3 S6 X* ]9 d$ ]
0x00, 0xFF);& T3 v; O+ A$ K% N, S% ~( p
9 K/ n: I& @# b) a, ]; y7 z
/* Enable synchronization of RX and TX sections */ # W* C3 c5 R" w3 q1 d4 V7 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 c9 V0 c% ]9 }8 L% f2 L' }( M6 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* ?' v9 k# E4 v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
m$ v1 ^# }9 Y! S! B+ a** Set the serializers, Currently only one serializer is set as
( \1 M: q, Z. z# X i" }3 T** transmitter and one serializer as receiver.% v. T& A; v9 `1 [: c
*/2 |6 g8 X ^+ k% h' n0 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); d( R7 a- t+ Q9 R( l) X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ g- @: l2 n; g$ K, }** Configure the McASP pins 2 _% V) `9 @7 K! C" s7 L
** Input - Frame Sync, Clock and Serializer Rx* Q- r8 j/ W7 A0 `; o
** Output - Serializer Tx is connected to the input of the codec ; w9 B6 ^" x+ U: a$ g7 N2 g+ ?
*/. C% \9 x: o8 B" n8 K( N( \1 @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 C J( h6 R9 B4 @, I; ?3 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 s! i2 D# K5 \8 G% @# L- [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 r1 Z: o6 I8 E| MCASP_PIN_ACLKX! Q3 E3 F' Q3 Q, t+ C
| MCASP_PIN_AHCLKX3 X. R9 s: H5 z4 f9 b- B" W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ y$ i. ^5 o! Z% f) s! [7 f8 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 u& f' d: I; |- K
| MCASP_TX_CLKFAIL 2 |$ C; M/ D# e. s( T& O
| MCASP_TX_SYNCERROR! M' G( h! _5 G6 H- U# l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 @7 y) ^# Q) d! T+ S' ^
| MCASP_RX_CLKFAIL
. a, S6 S6 E+ D, @( b| MCASP_RX_SYNCERROR ; E" ?. T. A- p8 P, H M0 R
| MCASP_RX_OVERRUN);0 I+ F/ C3 \( W) c1 B2 x% B# ?( `- j8 d
} static void I2SDataTxRxActivate(void)& U& r6 ]0 W3 R3 }
{! O0 S) z; g4 N# q0 g! _* a3 Q
/* Start the clocks */1 v Q- I/ \& n8 b3 H6 e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 R( d8 y0 c6 ~7 ^- S' \0 @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ v% w P2 H- I: [4 x% l8 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) `4 ~ Y7 p. h
EDMA3_TRIG_MODE_EVENT);
) X9 u9 ` Q% yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / Q t5 z& n, j8 G7 y% k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- @. _" U7 O. v* W* ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 R$ U5 P) \# W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 X5 }& ^* P1 u" Y( Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. s% ~; a X- R* M; S \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# ]3 o2 r2 l5 H0 y& ~: ]$ c7 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( [; b3 A/ v; J1 ~" A b9 w9 J} ! ~9 A& e6 ]( k/ ^7 _7 M" z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 z+ b P* N& W9 `. q- B8 U( K
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