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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- v2 x, t) D; i5 Y
input mcasp_ahclkx,
" T* x$ c2 w( g( D7 _1 einput mcasp_aclkx,
1 B L0 a/ P) Qinput axr0,
' j; n) J i6 q6 e- Y0 p/ `0 B( Y. Q, F2 a9 {9 @
output mcasp_afsr,9 C* ?" {" R# d' X; u. p" R
output mcasp_ahclkr,* z( V, L6 v1 \) t
output mcasp_aclkr,
2 w7 t8 }; v( u6 {: Uoutput axr1,: j! O. A8 o% M0 {- L7 q& N! p* j
assign mcasp_afsr = mcasp_afsx;
, [5 g- [, c: a K/ zassign mcasp_aclkr = mcasp_aclkx;0 p; D9 X; t# f r
assign mcasp_ahclkr = mcasp_ahclkx;
* U3 _7 I5 N4 Z5 c8 N: z2 m- W) G/ ?- Lassign axr1 = axr0; 5 g: t* j; I5 g
" C4 U( p- P$ Q4 J7 G- x5 N/ y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " B9 M \% Y/ E( y; s* p: q \- y
static void McASPI2SConfigure(void)
% j! }' J' G4 I{
& h9 {8 n1 l* j: D3 i9 w/ t U+ [* vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ x8 G# i3 v1 @1 TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& `" d' Z% T+ t7 o% BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- p" v) G& S% X1 E5 D- @$ S0 OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 p7 ]: h6 y/ hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* }" i. W, r, I& hMCASP_RX_MODE_DMA);
& ~" g" N) W8 J0 _4 E3 aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" v9 e+ F' F/ |: [$ NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 M" E/ G5 Y- n: y8 b' [; R& o3 MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 I: C7 h1 \; {7 h FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 k7 j0 h' b2 ]2 {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! a$ Y" Y6 w% \7 Z& X6 }" K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ k* Q, B( x' pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: T' n" Y# E9 Y" cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; e0 s2 t9 o% J2 {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 Z1 [ o% g" c- H
0x00, 0xFF); /* configure the clock for transmitter */ Y/ h% {7 ^2 H. P8 d( g$ l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: t$ r+ n Y: \* ^. @0 hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# |. G- \* p' l6 C* l7 q0 b4 J, EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 J' [5 p" x9 ]6 Q
0x00, 0xFF);
# N! `3 r; f1 _- p
: ~# @! E% }5 K* F0 C/* Enable synchronization of RX and TX sections */ : D8 t! `" e% {4 k+ R% ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; o8 @1 b; f* u" `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 C% x% a. e5 I( hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 d3 c: D- V( e** Set the serializers, Currently only one serializer is set as
2 y: B D e9 u: O& ]** transmitter and one serializer as receiver.
. g2 M9 v$ [& s7 X*/
2 ^5 q2 O8 c, JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( b* t& m" `* p- @5 w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; `- e7 j( k8 x/ T6 v** Configure the McASP pins
' p% O/ X8 ]6 Q# g6 O c3 s** Input - Frame Sync, Clock and Serializer Rx; U/ k: d' k+ `- b7 T
** Output - Serializer Tx is connected to the input of the codec 4 T1 S+ n$ `7 Y7 _1 V7 n
*/
7 K1 @% w4 ?% K2 \. P1 wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, `4 {* H$ y& K$ l; |9 jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 b+ h! K4 ~9 @' d' \9 Z% r! z+ l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! |- [4 y9 ? o| MCASP_PIN_ACLKX( l. A# z/ e9 C6 A8 S7 b
| MCASP_PIN_AHCLKX6 f/ `# X* G. d& u" d; _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 L C* Y, X5 C7 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! n) _8 L; h' x3 G
| MCASP_TX_CLKFAIL
; g$ k! H4 B* h/ p0 d| MCASP_TX_SYNCERROR
, j! C# j0 d* y% l- ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( A6 e. h0 W7 ~ |4 Z" U4 O+ Q
| MCASP_RX_CLKFAIL
5 \) ^1 t" n% e7 F% ^; m| MCASP_RX_SYNCERROR
& F: R8 Y5 ^& E! _8 y/ K& [& y, m$ l5 x| MCASP_RX_OVERRUN);
# }' ~6 y6 d' L* m1 ^4 j4 A2 h} static void I2SDataTxRxActivate(void)
" J* A/ S: e1 w/ @{
- u. p/ h$ x' |/ g: W; G2 o/* Start the clocks */
4 Q; B& J4 N/ ?$ ?4 g4 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" a9 q+ F2 q. n9 S$ Z% X$ Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; X, C6 c+ M) N8 `2 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' @6 J% M+ |5 W* D
EDMA3_TRIG_MODE_EVENT);
) e: X/ E' K+ f( M/ f; G. e2 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, x8 p$ m; D- d: X( O; PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ w* J8 u/ {% _( y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 ]$ g0 D0 w+ a# r" o. \9 I" NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 M3 i7 k4 j6 S3 K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 m \. P% q6 f- ]9 `* U( FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 N3 W9 y' R# D3 F# p& t: P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# f# s, @* x" D6 T7 ?4 T}
( A2 [" @( K" A7 T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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