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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) r B H1 B% Ginput mcasp_ahclkx,
/ C2 Z- l6 x/ `/ _input mcasp_aclkx,
! i. \/ G2 }8 ~4 d b8 d @input axr0,0 o1 e; ^% {0 J. C+ P G: I; G6 ^
# Q- t4 n/ m$ K
output mcasp_afsr," _, t; s+ w2 u( b$ P+ A: O- U
output mcasp_ahclkr,
5 h: j+ j( M7 l+ Koutput mcasp_aclkr,
0 J3 F1 N5 p# z7 }( ]* q9 l" V; Zoutput axr1,
3 Z1 e. h' v6 P4 w$ l* u+ C# | assign mcasp_afsr = mcasp_afsx;+ A `/ k( C M; P5 i, Q5 z$ N E
assign mcasp_aclkr = mcasp_aclkx; e7 x' g0 l6 e7 d2 [6 `
assign mcasp_ahclkr = mcasp_ahclkx;- H: H2 G: r* I/ G4 T" ^3 L
assign axr1 = axr0;
% Z% ^- k- A7 v1 a6 }4 d- a0 f+ |
: h6 g1 y/ v) W% }& x" Z) c; J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , s: }4 o7 S3 e9 K
static void McASPI2SConfigure(void)
2 B- a$ N) C' M9 H" w- N& W4 { I{
D& ]7 N$ f+ xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 Y, ~( }) F: q0 AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 Q/ M' K% a* z6 ]8 I: o; R6 M; [6 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! `0 W5 P3 f$ [4 f6 k, q7 z9 k% xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// j9 ]1 l9 U* q9 E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* c5 [" y; }' @2 M5 f3 i
MCASP_RX_MODE_DMA);+ x7 o9 i+ C, z0 f9 }! O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) P$ C" m% G* TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( R: M. M/ Y7 o v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* }9 o% V3 v- tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' b* Q. {8 D Y1 C5 Y1 b. mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: X8 k" Z% L$ M; N5 oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- J& I/ g8 ?7 w6 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* U. M M8 M: u& S* kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: j. ?% `2 D+ I* |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ G+ Z! f- q% a1 |) y0x00, 0xFF); /* configure the clock for transmitter */
9 E. Q' o/ c9 I- b1 }, wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, H9 W" L2 ~( C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : Z9 `# U1 z6 L5 B% L: k2 V# j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" m M! B( N. ?3 U3 h4 C0x00, 0xFF);
! @" p& ^( F9 {5 x1 `- H9 w$ F9 C0 l6 s+ T7 \( V4 P
/* Enable synchronization of RX and TX sections */ 5 ?9 \( K0 k& E( }* T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ e, {# v8 Y/ ?$ P$ H6 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: h# F2 t, h3 j) o1 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ h/ q$ h/ k" @# Y** Set the serializers, Currently only one serializer is set as
% D7 D6 U$ V, g4 q** transmitter and one serializer as receiver.
' ]4 t7 C: K' R9 j+ }# q0 J0 q& o*/
}8 _; a3 b/ K! }+ a& n8 G3 n. O3 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 I' N$ W& H/ W* D* j# U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: I2 d* }9 w9 k; a' B( q** Configure the McASP pins
( j2 ~" Y# t4 Y6 }4 s s7 H** Input - Frame Sync, Clock and Serializer Rx* U" F3 b6 Q& x% T( c
** Output - Serializer Tx is connected to the input of the codec - H8 q( r& y+ s* v- Q5 r/ N/ X
*/
0 p! ]% Y9 s, j6 R, hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- U1 t; g A. _" I( ?9 ?. U2 F0 z F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
F# M! X6 x* _; [1 TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ u. f8 b& k6 y0 K
| MCASP_PIN_ACLKX
( l. b; J8 p3 C2 C3 n; j- Y/ H% u| MCASP_PIN_AHCLKX
2 a n+ S4 ^+ q# O; q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% k6 Z8 S7 R! j& Y2 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 @. Q( I% u6 c; Q1 Q/ o; F
| MCASP_TX_CLKFAIL 9 U) b: L8 o. Q& R1 p
| MCASP_TX_SYNCERROR" d9 i* s5 T4 C' `/ \$ N8 A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 v! w- e) N4 k
| MCASP_RX_CLKFAIL/ |( @1 N) S! X' n
| MCASP_RX_SYNCERROR 5 c& z$ ]3 l: ]+ m4 n" {
| MCASP_RX_OVERRUN);
, c9 I, w$ r: C' L0 i F} static void I2SDataTxRxActivate(void)+ j8 i, @2 p( o* l8 g1 \
{
2 ?$ q5 M. u5 s; |: `6 f/* Start the clocks */+ B# L: y! }& o* p% ]9 @+ g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) @8 V4 p/ I0 _9 l+ y. S* L6 kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 m, Q% B; B' gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 Y: y5 a6 X: ~/ r7 t
EDMA3_TRIG_MODE_EVENT);' w( J: ?( i! ~3 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 M. Y+ U) j8 G! x" MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' r4 h# F; x0 K* \5 ]) D0 h. hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: P4 a5 d( K# T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- A$ X D# k1 o% c! vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& F. B8 N* W7 e7 f3 y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" W( U2 _* B' g& S5 i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 [& W' Z. U- p' K2 N0 X1 m
} 3 F/ p. i2 t/ K, l, f6 h2 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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