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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' b6 s- C- B, h6 ?& s
input mcasp_ahclkx,
. M) A* e3 H/ j0 O q9 vinput mcasp_aclkx,
! z5 Z! Y! ^: o2 h$ c! hinput axr0,
0 U- m j0 y$ U. D
0 X; t0 [; E2 |. x4 ioutput mcasp_afsr," [) Z. g$ r2 ~% A& Q5 ~; k4 E5 ^9 [
output mcasp_ahclkr,3 F v3 W$ l3 g+ ^
output mcasp_aclkr,
( R* A/ y+ |! S, Q+ E3 Routput axr1,
2 X2 j# U. ?" B/ ? assign mcasp_afsr = mcasp_afsx;
' J) ]; x$ N2 q/ E) passign mcasp_aclkr = mcasp_aclkx;
% @/ { t- _, Y5 Qassign mcasp_ahclkr = mcasp_ahclkx;
8 f; g( {% B' k5 m6 v7 c& n+ E* Gassign axr1 = axr0;
) Z" R6 {2 L/ r( j9 h9 s3 s; o* B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + f" f8 Y5 z& K. s1 O
static void McASPI2SConfigure(void)' `: `* d" i v1 I! o0 X# {
{3 G1 j' Y; c6 q1 G2 a
McASPRxReset(SOC_MCASP_0_CTRL_REGS); t. D3 O8 d& M$ A8 l7 [7 _; L$ t0 J1 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 Z) e4 e6 }/ cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ ]* [" X+ M+ @2 g4 k( [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
^) t }0 ~& @, _ vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 K' n6 ^6 e/ _4 ^
MCASP_RX_MODE_DMA);
9 H- w9 V+ W$ c# c- q$ w$ AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 ?9 m% D' f; k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ O' y- \( Q# [7 D8 _% s# JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 C/ U. A9 B- \+ w/ E$ eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: V% s! N( p, Z# N7 n8 Q8 l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + p# K: Q6 \# ?" w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 H* `3 j4 W H1 t# h% e! D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* @# t& K: u* ?& I7 i; m, }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) _& N5 l) W! S2 D6 }# M2 E% X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 i# k% l g" B8 }1 Y$ ]0x00, 0xFF); /* configure the clock for transmitter */: A; ?$ ?" P- ^6 ?& Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) ?" S6 o4 y- I- v2 ?+ QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. f+ S( r6 S2 O I5 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 l, T7 g: C" D$ q
0x00, 0xFF);
9 ~+ U* b3 I% [$ H& I+ e. x$ C: ^0 A# U
/* Enable synchronization of RX and TX sections */
6 w1 I8 k3 b5 C3 pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 h. L0 m7 H2 d6 s1 I( S/ ]: @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, Y- Y d0 G% ^0 tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- U; x' o& F0 s! q! L7 g** Set the serializers, Currently only one serializer is set as
9 g- S! [' _! J8 @0 X** transmitter and one serializer as receiver.
" A5 J/ u( |+ G4 f*/) b! ~( P* |2 e" \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) w' R3 D+ p8 X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 y* i2 u, l% J
** Configure the McASP pins
! k6 f1 J& j8 M: ?/ P2 ]2 X8 l** Input - Frame Sync, Clock and Serializer Rx! t7 b3 y6 y+ ^* o
** Output - Serializer Tx is connected to the input of the codec E/ u7 h- U9 Y8 U
*/
; G$ Z* I( }' b- i' k5 M& nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, x. J, e0 Y$ ?, j2 T, I+ [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& r) y3 C) Y" a% BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 u% ~4 t& H$ G" E8 I
| MCASP_PIN_ACLKX' ?7 s* I7 C# P- @; B$ f& C' K
| MCASP_PIN_AHCLKX
# w4 i' l6 b$ c- y2 C' H. n' a) r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& m" b: x, Z7 o& yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : A: g" Q* Y* X' I2 A9 h- e( T
| MCASP_TX_CLKFAIL
3 Q; r5 P& C4 a/ B- c% B9 J. s6 N6 s| MCASP_TX_SYNCERROR, {7 G6 ]3 E4 }: _+ \1 l) a" k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" I+ o" A9 W: U0 e0 j6 O4 T3 K+ G| MCASP_RX_CLKFAIL2 }7 c& B1 `" C) w: w2 n: x
| MCASP_RX_SYNCERROR ( j7 T7 |9 e7 p) J2 b* V- J: P
| MCASP_RX_OVERRUN);
- h' b0 v8 X4 p/ j} static void I2SDataTxRxActivate(void)6 j" P' S$ S9 @: I
{( x4 n b$ v- S, @+ ?4 {
/* Start the clocks */
0 q2 S, E( n! g& c, H. nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ F9 ^8 Q( y8 S- |# E( TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. u h4 ]1 Q8 Z B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- G7 `. a& i8 D2 e' ~. ~6 d
EDMA3_TRIG_MODE_EVENT);- k. J" Q( y3 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . K: ]! X* V7 p& l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 l9 L6 Z" J u3 w/ E0 A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 X$ s) B6 A* F) j; NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. [' \: c7 v. F8 @8 F$ X" a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 @ b+ s1 r# Y# D$ U8 ~+ {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 ~0 a$ X7 v8 e7 y6 ]* s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# z* U/ @3 @8 s, ]* j8 J/ H} 3 K& z* b, l4 A' H- B& E; N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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