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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 [) f& l( ~8 a/ o. P9 h6 g
input mcasp_ahclkx,
+ b) M( I6 K2 z1 P- C1 U, `input mcasp_aclkx,
# \% C" C' r3 N& yinput axr0,; f" g4 ~8 Y( l% P) J, L
2 [5 P+ Y( T6 Z2 ^output mcasp_afsr,
( }* L1 i* K* u0 j* l2 toutput mcasp_ahclkr,
# T5 P& M; b4 _output mcasp_aclkr,
( j4 `" f% N" f+ houtput axr1,: z6 p+ p& Q" G$ f1 k& J6 k
assign mcasp_afsr = mcasp_afsx;9 g: N: e* C3 H# |
assign mcasp_aclkr = mcasp_aclkx;
0 T: W, W, B6 f/ Z4 xassign mcasp_ahclkr = mcasp_ahclkx;
" @+ u/ ]6 z5 j" {" Eassign axr1 = axr0;
& d/ P5 ^% a" ?5 |5 _% M2 I+ U8 O* f% K# P K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * ]& J* Q1 u$ ?1 k
static void McASPI2SConfigure(void)/ K- a2 V+ T: r% M* M, T( v
{
0 s% D1 D- c% `; d# F) y/ z) `McASPRxReset(SOC_MCASP_0_CTRL_REGS);: \* V* R% ]) O3 W) R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 ?* T8 a# ]/ `5 o6 o5 l, {2 x" uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& i& \3 D; u r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! ^) d/ W& ?" R7 s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! M3 p1 A. o/ Z5 y7 t
MCASP_RX_MODE_DMA);
' L+ l$ {; E/ E: x3 L' {; DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 [. l0 {5 p& {; k/ O1 BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* y# b' X7 t4 D7 k1 y2 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % y# J- j: L0 C/ H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 F, G: g: n0 t! h8 V4 o+ |* w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # V1 z& d+ W! B) h; U a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 m, k! H' |2 S8 P7 |- _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 n$ I. A, S9 c2 Z4 O) m9 Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& J& O8 |' X. \8 f- H0 MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- ]' E, W1 \ Q
0x00, 0xFF); /* configure the clock for transmitter */+ p) T5 |3 i9 I- F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
g8 X( t, w4 s6 ^* d6 q# oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . K; s* O6 k% |" J; F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, {: ^0 R1 M4 |' r- ^$ _
0x00, 0xFF);
: Y1 @& P! [) V2 a4 k3 u( C( o. F( c: O
/* Enable synchronization of RX and TX sections */
. t Q1 @/ t& a- i; ~' QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" G- y# o9 j: ~* B& p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
L' c5 l0 V& K9 GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ U: D. O7 i' V2 Y n a0 Z
** Set the serializers, Currently only one serializer is set as1 M8 s* m6 M2 S S1 m- B! s$ s
** transmitter and one serializer as receiver.
, }! f! t& d# y' J*/
0 u% z O% ]+ |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 ? Q- g) U# d; x6 Q1 }5 Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ E% u1 d. D, F; }" O2 S" v
** Configure the McASP pins 4 |/ c) I) e3 l) K! k& A, t9 B! k( q
** Input - Frame Sync, Clock and Serializer Rx
* @0 z% H* q: Q** Output - Serializer Tx is connected to the input of the codec $ s( W! q( d) l6 I1 ?& s
*/
1 x5 x' k B( oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( |% D$ B1 I. A8 R$ BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ r/ Y% w) E) X! V6 K- hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX ~. j( y f+ g0 q# q; b- D
| MCASP_PIN_ACLKX
6 ~3 i; X+ [5 || MCASP_PIN_AHCLKX
# n( R2 }, z/ s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! X7 G6 r/ B) j* [7 p! S# Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ M2 T& T4 `( U8 L| MCASP_TX_CLKFAIL
: b- z/ v2 `3 e" [7 H( ~; v| MCASP_TX_SYNCERROR' d$ }& s2 S% _& t L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) J6 Z. j0 I+ b. p- j
| MCASP_RX_CLKFAIL1 @; S. m; |4 L8 n) a7 y( ?5 P
| MCASP_RX_SYNCERROR
X1 {1 _' G- k) x: B| MCASP_RX_OVERRUN);% z9 n/ A9 S/ m$ X- E
} static void I2SDataTxRxActivate(void)
- o, w8 S. k0 c$ T{
" ^- o% ?: p- `( a- K& ?% B& e/* Start the clocks */
( c2 T) Z: w- }8 W7 CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 ]# g7 g# X$ A, gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 w& b; t" w+ C, @! M: |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ u4 @) |( b m/ _/ N# NEDMA3_TRIG_MODE_EVENT);( {2 ^& g5 _7 n1 p/ _* K& K% n& y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / Z6 I/ r8 B6 O9 |3 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! s5 p% a* R' O- KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: V8 |2 p0 ~+ C) z, g4 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: n, h) v7 W/ L% f: Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- v$ ]: p/ C* f3 A: n3 w( ~3 M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) q0 W5 S! g7 k* Q6 fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 \+ s2 @4 W" `( _9 _/ {0 [% w8 E
} 1 t( j5 ]1 ]. ^6 S/ M7 R8 R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - e! r t/ j! g
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