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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" B7 R* `" B/ ?8 Winput mcasp_ahclkx,
- L- Q Y, W# F5 m. L q: Uinput mcasp_aclkx,
& s; c, u0 H" G% L0 q' Linput axr0,
, @, T; b3 T, ]0 |1 M6 ^/ A3 Y% X( d R
output mcasp_afsr, {" l" i2 I& L
output mcasp_ahclkr,
& t( N1 K' y* Y ioutput mcasp_aclkr,# l- g3 C0 I7 ? N, Z/ l
output axr1,
2 g- m/ S3 T+ c/ O* v. T assign mcasp_afsr = mcasp_afsx;
/ g% A5 i8 F9 a/ ^* qassign mcasp_aclkr = mcasp_aclkx;; E/ W* L& M/ F+ ]4 g
assign mcasp_ahclkr = mcasp_ahclkx;# I8 w- v, k, O' E) F
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % R/ G" b8 j4 k2 [
static void McASPI2SConfigure(void)' |* L8 S6 w i, J* z
{. i) ~! S. r8 x2 x0 N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 c8 O1 L; P$ |$ X. _7 uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 f$ y3 T- b) W% kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
y" S6 P% ?3 E; NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 j7 V" b. A; e, X# x5 m9 i! ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, g/ ]( n; q. O" c' w2 QMCASP_RX_MODE_DMA);
6 _2 @1 K9 Q+ CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! ]/ r! ?9 _( D: C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 x+ U8 T3 C$ N. L+ V: U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 l- w, N" U/ d# J! T7 o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; c- B6 i7 z* @2 M& JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 m( |# ~# C9 }& }3 U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# a: G* N6 B5 W* V7 FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ [; y" Y% `, H) T* E% G, yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & g6 e( i5 V) x9 y: J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& A. L j3 U/ @# f- a
0x00, 0xFF); /* configure the clock for transmitter */) ~2 C0 }# j# c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 N' f7 H% z# D* u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ B0 E* G2 V u2 _* D, U& x* I- s: fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, p/ `3 b8 v7 c2 w+ A% P
0x00, 0xFF);3 L3 e; h" Q$ ]$ q" n" U* F) S2 q
) _! X0 d) ~; Q$ R9 ^, c/* Enable synchronization of RX and TX sections */
; @: L/ W N. IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; _' b2 K: O' T; c+ vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 a7 a* Q& {/ h0 m5 Z3 F7 G6 |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" k y8 C: k$ V5 H! `
** Set the serializers, Currently only one serializer is set as$ e5 R0 _, S0 @ {. E
** transmitter and one serializer as receiver.; A. w- R& W8 n2 p$ q
*/
5 O' B0 m2 V* M; J& H3 U. kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, s; I4 z3 V, C. {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 C; Q! h$ h% m: ^' L9 d5 l
** Configure the McASP pins
, I2 _+ e z4 r" l9 Y7 g! `** Input - Frame Sync, Clock and Serializer Rx8 j" ~$ ?$ x! B/ @, B# a
** Output - Serializer Tx is connected to the input of the codec ' e" ^4 d# n( f, ?$ V: h- }- [: G
*/& w' w" ?! z# `) j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: h* h$ E& X3 SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# N& \- _: B* V! zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 ^* ^( i6 P8 E3 ]% Z
| MCASP_PIN_ACLKX
2 e' W: C# `* t! l| MCASP_PIN_AHCLKX
% W3 w) ]9 C6 W1 T. h! e% B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& K9 r& \. D& l! S! A( i) F& T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 n; t6 g6 {5 V* Q
| MCASP_TX_CLKFAIL 6 o0 J \& u2 Q5 T# N
| MCASP_TX_SYNCERROR1 x3 G. }6 x+ p6 T0 l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 J# I; O0 \% X% e5 E7 W| MCASP_RX_CLKFAIL
) ?" i! l+ e. k2 k4 q; u| MCASP_RX_SYNCERROR
( o5 \9 o! d- f: j9 S2 U# Q| MCASP_RX_OVERRUN);0 ]+ o7 e1 P) t$ D' T1 D
} static void I2SDataTxRxActivate(void)
& Y; _8 _: O4 n1 a# w: e6 D' V" ?{7 ^2 u1 F+ u% C7 Z6 K
/* Start the clocks */3 J, G! j/ R( [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: ]( H: B5 `3 \7 Q' k' n( xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, `+ p8 f# \7 X; Q) z$ c# zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ N1 M8 {; v- L. P5 ZEDMA3_TRIG_MODE_EVENT);$ f5 K Y0 c: N0 m. |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 v1 p/ X1 p/ H2 g UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. }$ q1 ^* t' c0 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 K4 R8 G& L7 D8 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) U1 [8 f" M( g' c" ~" c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ `' A |2 U( {: B; l& I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ t9 ?- b" ^& ?, @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 }% n0 j8 u( p. y* n' |2 {
} 9 k8 d5 s) ?0 v' p% @0 S% T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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