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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- r: T7 o# j E/ x: Y+ }/ cinput mcasp_ahclkx,
# U5 P6 p0 s$ w6 Ninput mcasp_aclkx,8 S" E" i5 ^/ F/ G
input axr0,4 }) u: T/ e, D e! f
2 l; j# I8 ^% k f0 l) Uoutput mcasp_afsr,% s1 r1 L2 g3 F/ C2 b2 \. w* m# O) K8 C8 U
output mcasp_ahclkr,. G2 A. m3 q* y. X
output mcasp_aclkr,. \! u* a. u# R! C; m1 [5 j; B
output axr1,
" b0 s. U) D9 A) F+ U/ } i assign mcasp_afsr = mcasp_afsx;5 y6 L8 P5 O& K1 P% L# g
assign mcasp_aclkr = mcasp_aclkx;5 K" [% V7 r0 F( e0 O
assign mcasp_ahclkr = mcasp_ahclkx;$ x, J; _) \. b! G: [4 x
assign axr1 = axr0; 8 H8 n5 R+ W' s1 V# l3 O; g/ k& N3 B
8 S+ o. k" |5 |8 H! y% o1 F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( g! ~4 T1 j4 H l6 O# N( n0 istatic void McASPI2SConfigure(void): O& I0 V6 o1 L2 c* |. G) O2 k( f
{) {2 J- r( V2 g1 g' Y: V7 B2 H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 ^2 o$ c0 x! T* \" |2 ^, Y0 r- m" OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" {0 ~* O% I! Q4 t+ v' J. \( tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 H! @2 E8 y* N5 W6 y) IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ h6 {/ ^6 B$ `2 C3 q. @( e8 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' d9 x) F3 b$ r# L* sMCASP_RX_MODE_DMA);: f' H4 b! Y; ]& [) c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ t: s5 U4 K- E( @! j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 @: J0 r7 h8 }: H# H% U7 O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; Z9 ]% c$ P4 X$ r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) |. f4 z7 ]; z4 SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ d: C# N* R) \9 Q( PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 `. P R! n7 f0 o. A, j) \) Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ x) B0 V. C* U. @& R, P- Y9 d/ F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 @' j* b! }9 G: @! G: P9 \4 V. W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 T3 M# ]) b4 B0x00, 0xFF); /* configure the clock for transmitter */
4 \7 u# f8 h. Y( ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 n# q1 U- k3 y! UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : [5 S$ A5 ~% x. m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& j$ S3 d! n1 o. M, S, u0x00, 0xFF);! w$ x; Q! ^; r3 i, n
" m+ b$ p, ? Y G% o. Z: f
/* Enable synchronization of RX and TX sections */ 4 Y! P4 } l k- v0 D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" e/ b& @7 Q. S1 B3 m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 N9 o h8 b# { S3 _5 cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! s) O- ^% t# G, I6 r) q2 z** Set the serializers, Currently only one serializer is set as
. q, V, C/ U4 ]- @/ w' x& m5 B** transmitter and one serializer as receiver.
8 A2 W( W: @7 ~: g, P- ?+ @/ J*/
( y. s, _- s( w; z% nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ ~) [" E: q( b+ sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! N0 u! k' @+ m7 C. u( g
** Configure the McASP pins
) N& j$ k0 H+ q8 H! |% v** Input - Frame Sync, Clock and Serializer Rx
1 O7 [4 A4 ?0 O" Q) }& B** Output - Serializer Tx is connected to the input of the codec
% b' S: ]8 {6 U$ M. N% o E*/
3 r1 L& X5 Y. ]) s& P" JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 {! E- _6 G6 L" R2 ~5 }9 S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 Z+ D1 M& e/ w" qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 L6 e I# Z4 U| MCASP_PIN_ACLKX5 E( y( V) V9 [( M
| MCASP_PIN_AHCLKX( e: [9 d B8 b9 P8 s3 [7 {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 I% `$ V+ C M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 Y0 D4 D' H0 K8 I1 \
| MCASP_TX_CLKFAIL % b, \8 G& H; K0 L, r a; X. {
| MCASP_TX_SYNCERROR2 T! |! d+ H: Z3 |, N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 A' l, e. j8 N& `% U8 F| MCASP_RX_CLKFAIL% q% I4 C( o; _( S/ P+ E* ]
| MCASP_RX_SYNCERROR , W, e4 r, o" G9 }# ^* F' W
| MCASP_RX_OVERRUN);" w& J6 c- y7 y, z% w! C
} static void I2SDataTxRxActivate(void)
9 U: |/ D6 g. ? K* X{
9 J8 Z# `: h. E4 L$ T8 p/* Start the clocks */, e. k. H! x5 i: ?: f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 ~# c7 ]4 {2 {+ j0 |* E0 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 I6 E4 k: n1 O/ |( j6 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," I! x9 a8 F2 I3 B) h" `5 o4 s- P
EDMA3_TRIG_MODE_EVENT);
3 B2 T8 K$ N1 s: V }5 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' r5 m1 G9 v- E+ {: I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 W) a+ r0 @- B- K; S7 `9 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" n: O. p1 p( T6 Y( o+ F. w* t# y& TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; L U" Y% v3 Z8 s( a K, h* X- \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; m6 p' {4 F( a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 F0 O9 G" E# ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- s7 o( ?* {! j5 s
} + d, O$ r( A4 c! c) R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 O# H# H( q! W, [9 X x
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