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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 @* q; v1 x: f* S4 d& Ainput mcasp_ahclkx,2 j) I& d' k; j% J- q8 Q5 b
input mcasp_aclkx,
$ f# X7 h- R5 kinput axr0,
& w9 \% O& C6 n3 I: l
9 j: g8 h9 l& G9 @output mcasp_afsr,
+ ]! b& S* L2 D- a1 \output mcasp_ahclkr,. |! ^ S7 X3 `! L
output mcasp_aclkr,' J A( v; b1 `9 [' p* H7 D
output axr1,6 ` d4 u$ b8 Z/ n6 y& F
assign mcasp_afsr = mcasp_afsx;6 T: i7 E/ D- z. M- o* r
assign mcasp_aclkr = mcasp_aclkx;
g1 ?. S9 Z+ u# R8 Rassign mcasp_ahclkr = mcasp_ahclkx;% z: d. b% |% l; \
assign axr1 = axr0; $ x1 c& L1 i( A
- }' V! k3 S/ H9 k0 Y4 P+ C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 k: ]2 ^6 o4 x6 T2 }- j, Y- qstatic void McASPI2SConfigure(void)
: t5 k% X, ~4 w! H{
4 |+ Y6 K! d: I8 [0 }& t) AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
I- p# z+ W2 b! `8 b. }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 p: W7 d; j1 _% B m# h4 q- yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 V9 c9 B# D" w0 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 U' e8 d1 ^, _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 D& i5 s, p& N% x: U6 `/ tMCASP_RX_MODE_DMA);
/ x9 p. ?) F kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! J' O/ a4 |! H' ?9 }7 hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& f* f2 _1 S: V) e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# W" F; f1 F* E$ IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, Y5 B& p8 g9 \* CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( f! t, h6 V6 W: ?( }1 b4 m1 t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 s0 j- D. ?2 |, RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& Q% G' X' f7 {( v% J. ]& a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* i# ~/ B. L( m9 Y% }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; l2 S* P* E: | n$ Z2 ?& K2 O' O6 j0x00, 0xFF); /* configure the clock for transmitter */
$ L( j9 l$ Q. [2 _. x) w% ]$ iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- n0 j3 Z* j) ]* x1 A" e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ H( }. \- G u$ {5 L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. u7 k" s4 E, B3 p0x00, 0xFF);5 i* f( I5 I% E4 A
! V9 t. O! T* V9 }/* Enable synchronization of RX and TX sections */
+ W# {1 z* ]4 F Q. ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- P6 O/ f( H1 q( m2 [' zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) i f: V2 @3 ?! o2 H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: Q- k0 v4 t2 Z# T1 m1 z# y** Set the serializers, Currently only one serializer is set as
+ q7 i4 L9 k1 }0 c! |- ~** transmitter and one serializer as receiver.
, m1 I4 w8 e/ Z+ D6 r+ y0 b*/
7 b9 i# f1 D! J9 V0 Z$ dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; ]- K$ z5 U- H. J% J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ _+ Y! ^+ r0 t6 Y# ]
** Configure the McASP pins 6 }& G+ y8 N9 Q0 h# b% M1 N% L
** Input - Frame Sync, Clock and Serializer Rx
, k/ k# U; \ ~3 @** Output - Serializer Tx is connected to the input of the codec
# q5 H$ {* H& Y Z; i2 P1 T*/
- {0 r. `% f' J( E8 s; c NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- b, ~5 U: @! q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! B. @" S# a' {8 R% e- vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ H- w) j$ I L) ]) f% e
| MCASP_PIN_ACLKX
, U4 y( `4 n* E9 o6 z/ e+ |. K| MCASP_PIN_AHCLKX
' Q( W- p4 O2 o. g5 l6 I& D3 m* J3 F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* p$ L' ~1 |" O- }4 u2 p! y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) l% I4 I9 P& u9 d' \/ \) Y; X- A
| MCASP_TX_CLKFAIL
! O: {7 t$ Y# O+ M& r# j" C| MCASP_TX_SYNCERROR
+ `& T8 v* m9 U$ ]" B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 A9 T1 u3 M7 y2 U& {: j/ {| MCASP_RX_CLKFAIL. F( W( P: ~0 R" i& h1 {4 h" \1 I
| MCASP_RX_SYNCERROR . W' x9 M. ]- u! D! o
| MCASP_RX_OVERRUN);
t( p2 Q$ s' e {, y; p} static void I2SDataTxRxActivate(void)- M/ o; S$ x3 X
{3 u/ r$ {4 s! [. q0 O( R2 v a- x6 J
/* Start the clocks */
0 I0 Z2 K" H; {& ~$ c I3 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ ?8 L' N. _# H1 C& M/ h8 pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 ^# o: i) H9 u8 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 L! e: _. Q& I/ T: G& B2 \EDMA3_TRIG_MODE_EVENT);: r! m3 {* ?: e, @$ }( R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " r+ a" E b8 D' Z K* t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; p& D. U, M1 A# h+ `/ v* `4 h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 Q2 i3 u) ]# X" F+ J/ Z3 W/ c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 J, {" H4 @; _. T: pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; N% E% g9 u6 D gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 p/ L% a4 U( y7 G f; t/ ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 v2 Z, Q; R: K. ^& P& H8 o+ Y
} s% C. I2 {6 o3 s- p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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