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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 T# j9 |( ?. x$ X8 j/ b+ k
input mcasp_ahclkx,* W. l0 M2 q; U2 s/ o9 f* u
input mcasp_aclkx,
: h) m3 ]9 G5 I; E, t6 j: q1 Einput axr0,/ u: `7 m! b; m
8 \$ j4 N5 Z9 eoutput mcasp_afsr, w9 Q- E3 S: ^ Z! ^0 b
output mcasp_ahclkr,
% D4 u7 k# \% X* r$ `0 aoutput mcasp_aclkr,
7 G$ d+ x- A9 s& Y4 Houtput axr1,
; a- M1 P2 F& G' G assign mcasp_afsr = mcasp_afsx;" g. l3 X3 ~3 n2 ]. U& o; G! S P
assign mcasp_aclkr = mcasp_aclkx;; w& b; x5 h6 z" O
assign mcasp_ahclkr = mcasp_ahclkx;& R7 u% Z( c4 E/ F5 {. m
assign axr1 = axr0;
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' y! D/ K6 W0 A% s& F P+ p% G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / O& E8 g3 c4 h( U/ j6 t3 N! r
static void McASPI2SConfigure(void)
3 i! m3 T1 w. ^* ^* _+ J5 g{
; V/ N" u, I( u: \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 |3 @' A* a. ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 v) k2 d- Q1 G" q0 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 _- |. `# Y4 [6 Q5 f4 {/ f! z0 \5 FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, J |; P5 m: L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 Z2 J$ l& p% y7 s- ?1 T( b& L
MCASP_RX_MODE_DMA);
! e( h* t- j% k' ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; Q, |' U* O! D6 w8 g {& s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! S/ |' E5 W. i/ F# \$ Z" m% |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ H9 z+ \. X4 k6 DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. C! N! n' p, M. g3 b) e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* S$ J1 R+ ~7 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) S0 Y* V/ J# V- F9 S4 Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* `* B: n( N0 K% Z, C1 j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 n% ~3 p: N1 e. }( `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. G. `5 l6 Y( w' @2 m8 x# o( F
0x00, 0xFF); /* configure the clock for transmitter */. r$ `9 J% h" S w5 L: W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 q/ N9 i% e' y9 B I: l1 J+ T3 J# N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
G0 X7 q/ T! J, {2 X( vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' X; |% o; ~% [: O; D7 B( N# Y
0x00, 0xFF);% R3 Z4 Y' `3 C( i, y
' W5 ~, z2 z6 J& i0 {% {7 z
/* Enable synchronization of RX and TX sections */
* [9 I. N# Z- b- ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 |0 y o& b2 O/ _. G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 j, } t1 T, ~. D& ]7 U; h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( j, q4 v9 e: p* D
** Set the serializers, Currently only one serializer is set as' o5 A! ~4 P+ `
** transmitter and one serializer as receiver.
" g% Q4 C' X) I% D' S*/0 {, \7 [: @9 r5 E+ T9 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, d' j% H" p; I: O* U7 l4 x' t0 e* t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ k1 \0 c. l) r! q E! D3 d/ X
** Configure the McASP pins ; Q" Q' }. c( o6 \
** Input - Frame Sync, Clock and Serializer Rx! v$ C2 H+ G g$ S( h
** Output - Serializer Tx is connected to the input of the codec - }3 B# K: c6 W& ], i! I
*/
' Q, }" g L+ q/ @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) C2 r% s' D' |. @% M% a- WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" C5 e% F6 x& H3 A3 MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 f! ~* j7 F# P/ o* `| MCASP_PIN_ACLKX% J5 u8 N. t- u1 L1 g3 L1 I
| MCASP_PIN_AHCLKX8 V d6 C) L# @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 v3 K: n4 ^) r/ ?9 V& v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) v0 [, h6 A! n' {, k) M5 i) b% z| MCASP_TX_CLKFAIL % R" h& |0 d# U, A6 o4 Z. V
| MCASP_TX_SYNCERROR: J+ K; i7 v1 t/ N9 |# V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - p/ B: G4 w! h6 J/ b0 [
| MCASP_RX_CLKFAIL! g. R Q t5 ], H4 c7 i3 r& X% |! [; e
| MCASP_RX_SYNCERROR # k3 R4 a1 p! n& N# }
| MCASP_RX_OVERRUN);
2 v+ G, G8 H: K9 P/ c+ A+ ^8 f% r5 t} static void I2SDataTxRxActivate(void), {( a. w4 {/ J: c
{
* }- n! ^3 {# Z9 z4 ^2 O/* Start the clocks */2 Z; f. a4 I. E3 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# {+ k7 M6 W3 W+ A2 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ T& x, M: U0 t0 _* LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 f* g5 ?! e% I Z( {
EDMA3_TRIG_MODE_EVENT);
9 `- j- i* l w( J/ I# LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 c$ a, K- G' J" a, ]. k: _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 C1 X6 x7 h1 M6 F' p9 X. B% ^; b& E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 Q: I& W" C# f$ pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) u- j0 [! P/ q2 k, V3 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 f, L1 I* [; N) r5 ]6 A/ P M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* s4 E# n& _. L/ o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, w4 Y& v% A' J# B
} 4 u6 S) v8 v' o- J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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