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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; B" d. z9 {5 ]4 ninput mcasp_ahclkx,
/ }3 ? q' e" Y& I' Qinput mcasp_aclkx,
R+ d C3 T9 m) w5 H* x; }6 S, N( pinput axr0,- b9 m. W6 _3 Z
0 f: t) \1 X5 C- f. soutput mcasp_afsr,
5 O( V5 k; \; Koutput mcasp_ahclkr,7 N, M: z3 N7 q+ ]9 B- Q
output mcasp_aclkr,
9 z% C6 I( w. U8 s7 P. a5 L& Voutput axr1,
6 q9 O; V: n% X# B+ ?$ P" x: K+ j assign mcasp_afsr = mcasp_afsx;7 Y& O8 \$ v1 @" a- R4 |
assign mcasp_aclkr = mcasp_aclkx;- E/ h: ~0 q0 M
assign mcasp_ahclkr = mcasp_ahclkx;# O, L2 L/ W% v5 w
assign axr1 = axr0; 3 c8 U7 |- Y5 i* |5 Z( ~5 |
7 P8 _, y' c' e6 o7 f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * m8 E8 }' C8 E' M5 k& J, A
static void McASPI2SConfigure(void)5 _0 [& _3 ^- m% W2 W* F
{( K, Z# s) Z6 B$ a4 Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 H0 Q( i% F/ s$ K2 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. n, V7 p( ^3 u8 r1 \- m5 FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. d$ j& _' @( l8 ]- r! O+ e5 u. R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 T* T2 S6 A% @1 m5 K+ JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& S, V1 m- l2 jMCASP_RX_MODE_DMA);6 X) R7 G. Y0 J. i. F9 |# D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ K1 C) w5 R% D+ c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: i1 f, w3 g- h: D# S8 w7 b0 p7 n5 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* M9 f) R2 w, d1 w! y: _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 y5 f$ W* w5 Q! v f5 @& W2 A: d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! {+ J7 z3 H4 c* H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( I, n0 H% f0 s8 C% HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) w3 Y/ n1 ], q- l6 r# f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ H( m6 W( V2 m ^" x. z; hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ t, l9 |1 r% K8 I3 H1 f7 v. o0x00, 0xFF); /* configure the clock for transmitter */
/ T* E. F. X) u% GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 |: ?1 N# f4 A5 B' y# oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 J* `# D9 d3 V+ r7 f$ ^ R! m: h5 u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# {7 Q$ k. T0 x6 G$ ^& w1 y
0x00, 0xFF);
: w2 a5 ?# F6 ]/ U8 H; w, J* P' o
& h( ~3 m% P6 o/* Enable synchronization of RX and TX sections */
# n! u# u' ^5 [8 A4 ^' TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ f" _7 ^* h! F/ [( XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 @- c) E) `8 C: G0 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ h7 Q: O! W0 g9 p
** Set the serializers, Currently only one serializer is set as2 [1 A: `' F- k8 }
** transmitter and one serializer as receiver.
2 j8 [$ Z2 N0 @3 [4 T8 ~1 ~8 \*/2 z7 P& F9 o1 ~' o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* o+ ~" i1 R: ^, o/ t, t1 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) w( w/ C% ` y' G& R
** Configure the McASP pins
2 U0 }. E3 ]) q** Input - Frame Sync, Clock and Serializer Rx$ ^- N" c# F. W" Y1 ~
** Output - Serializer Tx is connected to the input of the codec
$ w4 q3 Z! {) o0 H8 K& K*/
0 V4 |5 k' [$ ? v& @4 K8 @0 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ f7 t1 _( e# ?7 i6 `1 [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: Q7 \7 i7 J: @9 V% I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ B! K. T! r- V7 d" i1 j) d3 s( i| MCASP_PIN_ACLKX0 b2 ~3 M5 }: [8 v0 [% A( o
| MCASP_PIN_AHCLKX
, b. ?! i O( L; L# v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# R1 Z& |$ R5 j H% f2 V4 ?# P4 J4 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- j# S$ k8 r& [! l: e( l: Y- k8 K| MCASP_TX_CLKFAIL
7 S4 x5 y) }; l, W0 O- w2 S6 ~7 [| MCASP_TX_SYNCERROR$ U$ x ?: m* e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 J: v' O- _) D P* c& J| MCASP_RX_CLKFAIL
7 v7 `2 M3 g6 O+ t| MCASP_RX_SYNCERROR , S: k% z/ O* x
| MCASP_RX_OVERRUN);
% }8 ]: A4 o& h3 Y7 \} static void I2SDataTxRxActivate(void)
9 \- f2 X' L" D2 b4 T( c{
- Z- _" J& b! ]+ u+ a/* Start the clocks */2 U' U. y/ _6 a) Q% c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) f3 p) x& G' T- }( EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 j) B" V7 Q e- h* fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ C2 L% T6 t0 V% A: \
EDMA3_TRIG_MODE_EVENT);
7 Q {# t5 G) \: y2 a% REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' h' Z; ] ]# m* y3 G W; @9 E% I/ DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ S8 A4 U$ O; e$ C( uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; p$ Z8 p& s3 sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# t% n6 ]$ d7 V0 b) A3 |! A( owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 G# B3 J# l! R7 Q) \ q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 ?8 q1 o8 ~" v4 {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; B% P: Q, G% _; F! \$ y B7 z$ G/ T
} ) b0 z8 D! A. |! h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
2 e" o7 C; Z4 ?* o! N9 \. `+ A2 ^ |