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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ y9 `" Y6 M2 ]% c
input mcasp_ahclkx,' ^: c) i4 q6 m6 d6 }% t/ B1 _
input mcasp_aclkx,( F5 b/ p, k! X
input axr0,
; d; ~% \2 p5 q$ d8 _( F; ~# H* m$ a
output mcasp_afsr,/ @7 Q& ]* w! t1 @2 H4 R ^, ?
output mcasp_ahclkr,3 W6 t. G) o& R8 d5 ^ p( Y
output mcasp_aclkr," C: N/ o8 x* M. {' w) }1 R# A4 y
output axr1,, Y; m V7 P/ ]. h5 e7 ^$ ?
assign mcasp_afsr = mcasp_afsx;
: \4 B* k: K* Y2 J/ Eassign mcasp_aclkr = mcasp_aclkx;: L& U& q0 b+ }
assign mcasp_ahclkr = mcasp_ahclkx;+ f6 T; g5 @$ o0 h
assign axr1 = axr0;
* N+ l3 I8 \' Y; [
: D8 S# u+ t7 n- N7 Q: l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : |; n1 ?6 K8 a: x" l, a
static void McASPI2SConfigure(void)$ G+ L! r* y) W" K3 i" ~
{' t& }' N2 A3 J+ o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" y- j8 T* G1 W- O% G& i/ ~; _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 i. g5 q" o( J" AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" O. c* v) ~9 E+ W4 q* n. A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 h# M8 b6 F5 z! r4 F6 _9 X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 z) k: j( i0 i7 h1 S7 @& rMCASP_RX_MODE_DMA);
0 A2 ~9 v/ k6 Y d$ e0 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, ^' c4 \. |: k8 c* LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 p# w# A/ D$ K0 C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* l$ Z0 C- J! C& M t2 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! m7 H$ }/ x$ L5 P9 [. h. ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' O6 h2 Z# l; @1 p, |, w0 `' zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! ]- \4 [+ g/ F* q( ]# VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* d/ e( b( w9 I8 M& l7 h) c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& b4 W( K- t& t2 J; m$ h: ~4 ]5 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 c6 K2 }: i. R X
0x00, 0xFF); /* configure the clock for transmitter */
4 ?* K: A! U3 s2 p5 v- O! vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! H: m9 [* R; C1 Z; w" m/ P# P) SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" h G* ^. {( s) ]) Z0 g; iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# _0 k# M. y7 M6 t' |. H M3 j/ ]0x00, 0xFF);' U3 K, W) F+ O' W3 V4 F
! S; z. q0 j: G4 D/* Enable synchronization of RX and TX sections */ 4 e4 S2 e& H# }" w6 x7 t' M1 p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 [! i/ Q1 C- hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 R4 q* ^6 Z2 W$ F' S8 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" \% M! O1 k( ?, I& `& M2 ]** Set the serializers, Currently only one serializer is set as
$ y) [' U) E3 u- [7 Y** transmitter and one serializer as receiver.
2 a& w- Z( X, ?( G; |% D*/
8 q4 p% c- l6 N/ ^2 x0 l0 pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 U6 ?; ^$ Q+ i4 b0 Q4 Q% ^; M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 i2 W+ D+ R# q3 i( _** Configure the McASP pins
& {' b& Z3 Z7 }, p4 r C/ o** Input - Frame Sync, Clock and Serializer Rx: @+ _) B( v( d* |( X: [5 e5 j
** Output - Serializer Tx is connected to the input of the codec
$ ?' A0 a' f% a8 H*/
+ u5 q. o1 m' l8 E" d/ i$ OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' _6 r( V7 C) \; C; I7 dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 q, Q: U1 u; o9 fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' P* Y5 V8 r0 V0 P' v
| MCASP_PIN_ACLKX! j' ]2 ]' O. X$ k3 [& e
| MCASP_PIN_AHCLKX7 ?# o/ _/ N% g1 h0 D2 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 y ~2 @: q1 t8 @+ h' |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' B) r$ }) b1 E( }, f5 H4 }
| MCASP_TX_CLKFAIL 2 h1 i0 h2 O, x) [: z3 O2 L) }* w3 U
| MCASP_TX_SYNCERROR; W+ B- e% A3 P' W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 ?$ P$ a5 O$ c- n| MCASP_RX_CLKFAIL5 J% [0 T6 l* o4 A8 _
| MCASP_RX_SYNCERROR
. G& u# l: _4 ?1 x8 V| MCASP_RX_OVERRUN);0 i* a% P* T7 [
} static void I2SDataTxRxActivate(void)9 u* n( L4 x- l, a
{% {* g. m3 w4 S- l
/* Start the clocks */; S2 V" C; { E$ _% M% Y. N- `; R4 r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 u% @' n& n) R4 R0 G$ zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: u: }. [" n# Q+ Z' K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( q) }; B6 R$ ]' w4 {( M: ~
EDMA3_TRIG_MODE_EVENT);
2 `! `; u1 V* p: X9 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 y# m7 f4 C' m4 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' i9 \% W2 @( \$ \9 \) \0 ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 u( U2 ?5 d6 k; h0 X7 f. h% H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 ]+ H3 a+ d6 T1 uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 O: H1 Q: |. r" Y0 i" n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. ^; H7 B$ h B/ h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 R. `( G X4 c- g5 ]7 n, Y6 Q8 L( Q
}
8 m' K+ y4 O/ N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 v9 H3 O5 u5 T) r
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