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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# n) E% [1 l& `; m8 I5 U/ r; Binput mcasp_ahclkx,
\0 m5 b! ?( U- y. r5 ^input mcasp_aclkx,
( o- {% a) }4 s( W V1 N1 ^) Hinput axr0,3 E/ l# [) a- @/ B& _
5 h' S$ v8 H. L8 H
output mcasp_afsr,
s1 D: n e- B/ `' ?4 ^$ V1 noutput mcasp_ahclkr,
4 X3 U X; Q; @1 ?( C+ }4 B- g T a: ]output mcasp_aclkr,. _5 l! m. `5 {4 L5 |4 y
output axr1,- l( x2 Y# i$ A' ~, L6 m. J
assign mcasp_afsr = mcasp_afsx;
. V. M8 N- j, F7 g. q* U9 @: Z) Rassign mcasp_aclkr = mcasp_aclkx;
( ?3 z& K, r6 C- B0 Y8 Q4 fassign mcasp_ahclkr = mcasp_ahclkx;
5 J/ S; h# t: Massign axr1 = axr0; 5 G. V Y7 |( G
" Y! h1 @7 y8 F, E( b" I1 a0 n% Z/ t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + D$ t/ m6 _* I3 Y& W9 d8 v# P
static void McASPI2SConfigure(void)0 }% k. e( g: E1 z3 H5 k1 ?+ ?
{: c/ L! D p* {, I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( Q" e( K, C8 y+ X x# `- z: }5 m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 O* G% O! R) H! m: ~% }# g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- ]" y: y% D" k5 P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 H# o" T! a, ^! M7 I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( h- C# ]9 W& _9 gMCASP_RX_MODE_DMA);
! y: H4 c4 }2 u: \0 o# t. iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 @- X7 f5 p& {5 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 e# w3 ?1 j: V, `! ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- C, V/ E5 P# r" t' L ~# g* NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( I8 _! {/ X# b1 M B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ M _! p3 E& ~: d8 X8 O" Q q3 ^ mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: H0 Y8 }9 z9 j) \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* s/ {: ^5 U9 e* _' M1 H9 n' w) N. uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; N# m$ \6 J: z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 q* }" p7 I6 ]1 t8 y6 ^: s7 k3 v
0x00, 0xFF); /* configure the clock for transmitter */2 e9 }3 Z. L3 o' A, _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 ?1 K. X0 \4 N4 bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 ~; z: }" N" i; V: e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 g3 I4 M: i8 F1 v: H6 l0x00, 0xFF);/ `# X! J9 p7 a0 Q K3 L
0 T/ q0 {$ E5 H" C1 ~+ M' C/* Enable synchronization of RX and TX sections */ & U+ w! U* ?, Z6 A5 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 E, Z# u7 J8 N s4 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* a: z3 c0 s hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( F; S$ V* P( G' `0 ~( h** Set the serializers, Currently only one serializer is set as
8 g: q, _6 T, n8 S& E** transmitter and one serializer as receiver.: i# Y3 c, J2 O! f
*/, _2 o& T- E- A$ Z2 R* W; G3 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ z9 w0 N, E" O4 z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 O* C- G+ l0 k$ ~** Configure the McASP pins
& _' G1 l* C& N7 P2 y** Input - Frame Sync, Clock and Serializer Rx
% m0 ^7 K! P' q4 Q: i** Output - Serializer Tx is connected to the input of the codec 4 R) @6 I$ o2 t$ K4 [* S! T
*/+ f4 P, V" M3 |6 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& x! p# P% A# J7 F, m9 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 k0 [- l4 l5 `/ H( bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! F5 @# U, ]# F: _$ ~4 M8 k
| MCASP_PIN_ACLKX
$ @' M4 o3 |$ \: R* u| MCASP_PIN_AHCLKX
0 P5 v5 l2 F$ I1 }* }; p/ a- A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ @0 h# a* W2 o, kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" `7 R- Y7 l" [- S3 w6 ]$ c5 \| MCASP_TX_CLKFAIL
: O3 r$ i5 ]! w% f* Z+ v| MCASP_TX_SYNCERROR
# w: }; B" W5 D) D+ f' w2 [6 X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % o s( q2 O% N
| MCASP_RX_CLKFAIL" Q- T& d- b/ b! c0 i. J9 x# n
| MCASP_RX_SYNCERROR
* [+ P7 o/ U6 j7 V5 m; W| MCASP_RX_OVERRUN);8 J0 \# G2 U, p
} static void I2SDataTxRxActivate(void)
- N# J7 o4 ]0 H% w5 _9 m$ P y{& A- {& D: h: ]8 L2 l1 Y
/* Start the clocks */
+ }3 A. o9 T g/ `2 H7 ^$ {( gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 j" o( c1 e3 }. o* h7 L; K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) Q9 g8 U1 F( D* i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 X* ^, _/ D6 B8 E& {' P% t
EDMA3_TRIG_MODE_EVENT);6 H N0 c( y5 \1 ^; q5 q; d8 u# C0 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- x- l+ B! ^ o) R, U. TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 Q: j' p: [' N, Q3 j$ H1 EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ E; M# |8 g" n& M% z1 H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 o* H8 s: g, }, |( G8 o9 ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% Y5 X1 { c* @% w. V8 S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 `7 V7 i, P( c$ c/ f8 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 l& |6 H: o' i
}
h) I+ o- F; ? b5 _; ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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