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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" ^* s- o5 P! Linput mcasp_ahclkx,% e4 c. w: C& O& e& g# h& l! x
input mcasp_aclkx,
+ D6 c" ?: P' H2 rinput axr0,* s& e' P6 o% {+ _6 I
$ ]5 K/ D5 w- E' z/ J/ b) Doutput mcasp_afsr,. z0 ]5 y& Z' c' Q' T
output mcasp_ahclkr,* |' }5 `1 V0 P9 k O; Q
output mcasp_aclkr,
' `4 V4 [: k& J" ]+ R% woutput axr1,
+ ?' j# _# E: a assign mcasp_afsr = mcasp_afsx;
: T) U; D" g! {8 Zassign mcasp_aclkr = mcasp_aclkx;
2 v% K9 X- T4 w. L4 |3 qassign mcasp_ahclkr = mcasp_ahclkx;; F8 R" K1 n' D o! X( K8 p
assign axr1 = axr0; $ Z9 Z. F2 A6 B4 T: l2 l( R
# v* o0 G% ]) u V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' r) |6 J/ c$ Hstatic void McASPI2SConfigure(void)
. J8 B c2 u6 D8 N/ q{8 t, m1 M1 c) G# A$ A/ O' U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 j, g% `0 u' \8 G* PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' U+ y- j; m* }9 o/ U7 H0 R8 W9 NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 P F3 M& W1 a" t2 d+ j8 F9 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( ~2 l: {% Y" C2 F3 B, aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% ^5 p" k8 h! B7 M tMCASP_RX_MODE_DMA);1 r. I5 B+ j: M% P5 u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 g7 n. y# }+ k h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. n$ \# M& l3 k8 y8 R' tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
c, h! i4 n/ J! `* Z- Q! z$ l) y7 yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 x+ O/ T( [: R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , R8 O. F: R- G7 c, g {1 q2 H: y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; q; T: H G4 h2 y& S7 v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; _" @* b5 O; d+ [- C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* g6 i A7 r2 ?5 n7 @# sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& J; i& T# o8 L% O
0x00, 0xFF); /* configure the clock for transmitter */2 f( \% G1 q0 b0 n$ g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 q6 C, O5 ?6 }* F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 U/ _, _7 D. e, E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, P! M# \" M4 y$ d5 g5 w
0x00, 0xFF);1 h6 O! K( M: {
: T3 N) m# E3 N, B- v+ S$ A0 P5 j: C/* Enable synchronization of RX and TX sections */ 8 O* q7 y1 P/ k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' L2 C# S$ a" K0 b0 ^& V' v/ t- P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 K( ] W3 `, I- y u# K/ MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 z) U& n2 Q W
** Set the serializers, Currently only one serializer is set as1 b3 E) ?! f. F3 h! f- _2 E' s
** transmitter and one serializer as receiver.
" X; ~$ H9 E) t+ ^" t" e*/
5 w6 u+ T: l! h* r5 DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" e: N4 Z! j" S2 ]' `/ ]( `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 }! g2 a; x, q2 [7 m, E
** Configure the McASP pins
; m. Z: C) @' {' n* o5 i; D8 ~** Input - Frame Sync, Clock and Serializer Rx( Y/ ~ f& h. N) P+ L1 W
** Output - Serializer Tx is connected to the input of the codec $ z5 V, s& H/ o% F7 [
*/+ h$ O+ u. e% ^1 ?8 x( q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ O6 q0 d. m* B3 y( v; M3 ?9 H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: i% U3 m1 h' d' P4 H4 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# B; _$ @7 \- j2 p& e- C: L
| MCASP_PIN_ACLKX* ^- L* N0 i; p3 P2 h* o8 Z# t
| MCASP_PIN_AHCLKX% Z$ |) |$ D) B5 D$ z! r7 H6 p4 @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 T% d. D" }# x5 n2 rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 ~, ?% Q9 ]$ @% S( h/ w) L0 A* y| MCASP_TX_CLKFAIL
5 p4 ]: W1 a3 U9 k, C' m \5 v| MCASP_TX_SYNCERROR3 ^; r* I4 ]4 t4 i+ G ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# s2 ?) Y6 Y# M/ t| MCASP_RX_CLKFAIL- {( F3 ? k$ N8 p% }/ z
| MCASP_RX_SYNCERROR
- p q% |. N# E; L6 A" L* g| MCASP_RX_OVERRUN);8 `/ \% w8 b( b! y: v
} static void I2SDataTxRxActivate(void)6 a( |/ @& c1 Y! R" \. e1 I1 I
{
; W/ B7 m4 i, |0 T7 n- c" {/* Start the clocks */* O; c2 ]$ D) V* l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, e3 y# u1 P/ \" a4 Y2 K3 OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: i2 U8 |- W [; X& |/ g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* F2 x: B' _0 ^$ H
EDMA3_TRIG_MODE_EVENT);
6 U0 A/ S0 c. Y- N0 E$ y1 i' GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 \; G0 X5 l8 h; @9 v, J9 I0 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( h R+ t" ]) F% S. o$ a& V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ `) {( Q2 U' b* D& aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& ]0 j$ X( T4 B' D0 f6 {1 Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 F" {; S1 I ?' P0 @, d! v* l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* [5 `5 I' ~% \: x( }9 i* ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% w1 h7 J9 _9 \}
y+ ~$ O# p# g& `* Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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