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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% |3 [# J7 f2 g, binput mcasp_ahclkx,
9 j( o8 J" ]$ U% n) S' `input mcasp_aclkx,2 M5 L$ \( M5 C3 r; n) ~
input axr0,8 \* f! E( t9 r+ Y" ?- N1 `
5 L( z& g. \7 j9 L& U E
output mcasp_afsr," c" D; I9 T, w# z7 f8 ~$ w9 N
output mcasp_ahclkr,
C: V9 m: j1 ^& U2 l$ [9 @( Toutput mcasp_aclkr," V5 }: ]. A! W; P6 ?' @* H
output axr1,4 i, d; e) C, T; p: X8 w8 x
assign mcasp_afsr = mcasp_afsx;
/ x1 B$ c3 P) Yassign mcasp_aclkr = mcasp_aclkx;
, k* ~8 D9 e( k# O* h2 \! Nassign mcasp_ahclkr = mcasp_ahclkx;
" N/ J/ [; C: m& f! @9 Fassign axr1 = axr0;
/ Z1 Z7 `& U4 W/ A+ H
0 [- I" I; K1 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) w) z. M& S6 A$ }$ z8 F
static void McASPI2SConfigure(void)- f" b6 e6 U% a& L. D8 c. n
{9 O- A/ c' z( O: z Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- Z3 G" r# n& |* n. c/ ?( hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 d- R% b% A8 wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 a' ]; g9 R, x* ]" J' j9 T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 p; U: d1 ^% ]6 DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 B: G# E+ G1 a; E! Y# j; pMCASP_RX_MODE_DMA);8 R; W) p6 U$ u; i4 i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% Z( Y/ Y! }- v" H# mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 t8 U8 ~, y' g" {0 h. C3 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 m7 ]9 O" i! L$ e3 }* y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 U* T( N8 o% ^4 t3 iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% e$ v( w' D+ dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 V9 t9 ?6 w! rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ j& x ~+ E4 b. q, z) k7 H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" |5 ~; M: ]. _" R4 x7 p: b% z8 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 Q; S h! ] [) V( n) N/ D0x00, 0xFF); /* configure the clock for transmitter */
; }. i/ v0 m, s- s/ |! r/ \% uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) X; r& F( L9 s) y# E# J' P8 k% @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 ~% i" }; L$ g- K0 v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' o Z( B) Y; T. Q
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
3 A$ D& ]$ E$ Y( YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& Y+ o, ]' Z v3 e* b* [; Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! m& X N9 ?; l7 m5 W- z# Y% Z* k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% K* v5 k$ m9 G5 a7 L
** Set the serializers, Currently only one serializer is set as
& w$ x8 G& b. P- C2 d** transmitter and one serializer as receiver.0 ^& v" U5 E1 i5 T6 M9 B
*/
- g/ r' o2 `% o) rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; e, S8 J0 d9 r4 g" wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 C" ]: s; q7 x- E** Configure the McASP pins . V& ~! L% I4 i! D
** Input - Frame Sync, Clock and Serializer Rx
& `7 W4 H/ S! `' E2 {** Output - Serializer Tx is connected to the input of the codec 1 ]) {* P3 p( V3 e9 ?
*/
. _% A& v5 n: M) p) B/ [: fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" w) N* L. o5 z& h+ lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 _! {& u9 j7 s2 K( y: d. l0 bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 S; q9 j7 j' ]5 X! A# n
| MCASP_PIN_ACLKX
) G, A% N3 F5 x8 ^: g" f| MCASP_PIN_AHCLKX
. L% o6 Z+ V' J$ h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- Y* w6 O! ]! ]: XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" R& b. [/ |; }" y5 s& Z2 ]8 q| MCASP_TX_CLKFAIL ) q6 _* l. M9 v/ c1 q+ c+ t
| MCASP_TX_SYNCERROR
) {6 ~# y6 N d& ?8 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 S( r. U! o) \+ `8 V& @| MCASP_RX_CLKFAIL; X G2 o/ Q) e& [' t+ W4 }
| MCASP_RX_SYNCERROR
. D- c0 @5 n6 l. z% W| MCASP_RX_OVERRUN);
& m, ]4 A- i) D1 R2 q6 r( ^} static void I2SDataTxRxActivate(void); f9 U2 P+ Y3 h1 G7 q5 l
{: O9 d( h- o- h! k! ^$ n! T
/* Start the clocks */4 W2 ^: t9 b0 F: o; U3 M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 ^) t6 D- j* ]: W& m b6 H: Y6 G3 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 R) B4 Y6 Q5 h$ x: |$ ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! U) t% C/ S' ?EDMA3_TRIG_MODE_EVENT);: k* D+ v8 O* d, O9 \" s/ v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 f; A0 `+ G1 p9 `' A3 o+ uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ m6 T9 O" } A' z! @1 rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 Y: M8 e, x' @# fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) Z9 x- g# O, p1 M6 Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" T# w, r2 ^5 [. @; dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" b9 \/ J( i3 v' y, PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# I& H' Y. C: t$ k
}
1 g, q0 `/ P. ]8 {' [, L) k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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