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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 E3 N5 c0 n3 B- r: B# |* Minput mcasp_ahclkx,7 P. u! N7 A1 [& u n7 ~- d
input mcasp_aclkx,
1 u6 x: v% S/ ^$ D% i' N0 h8 ]input axr0,
. \: x i& Z b( G
3 n7 p; W" d2 C, Zoutput mcasp_afsr,
3 Q* j0 O. R% u7 S& f$ boutput mcasp_ahclkr,$ Z0 [+ U" y- x# B& I' L; @2 ~
output mcasp_aclkr,
6 {. n1 ]5 w6 B/ F# Y8 ?+ G/ poutput axr1,3 S0 t: p9 x3 ^3 ?% a( `9 q
assign mcasp_afsr = mcasp_afsx;
! f0 N3 X* }9 J0 n9 oassign mcasp_aclkr = mcasp_aclkx;
7 e& B, `5 S0 Sassign mcasp_ahclkr = mcasp_ahclkx;# k7 r) q: K7 N+ J, b
assign axr1 = axr0; ' _* q3 s4 [# ]; L: F8 y# g1 ^
' N \3 @7 v0 k6 s# L r( P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 E& R/ K; W* s `
static void McASPI2SConfigure(void)% O9 r6 I! I* |9 g Q' b
{( d4 f5 g3 y: y6 {; C; a% j; f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! }. M# E2 y2 m/ _) h/ \1 j+ k2 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// J5 A7 O2 J% d* Y7 a, u7 T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
R0 W$ s; z+ U* cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% S; x) {! H' ^3 _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( R* [0 m# Q9 h( M8 n: D9 kMCASP_RX_MODE_DMA);. n, V8 b% g7 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ U9 {* ~# y8 B3 y/ t- x/ I6 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- A& _4 ]( X8 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & J: C% u& u& l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 H) V/ X$ n8 x. BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! S/ ?+ k% J8 E) Y* b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 }( R4 P- \0 \+ {, hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ Q" z; B0 ]4 Z0 n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . x8 L/ ?* N, U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& ]: A) f0 I' D
0x00, 0xFF); /* configure the clock for transmitter */
1 j1 ~% v. F8 O6 l) a5 d# hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
T* j+ N4 w* y: o- n: x- w' BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 p4 `) r, h3 m$ P2 tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 s9 m- Z) {- C9 Y4 g; [7 l0x00, 0xFF);
6 v5 p6 N( X! t! |' h# g* o5 B1 d- a+ S5 p
/* Enable synchronization of RX and TX sections */ 4 i$ v' {$ \$ S5 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# f, K i( O* i; f$ XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; K) ]4 F2 q" X4 m+ RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ z; \9 @4 u% f( F) E** Set the serializers, Currently only one serializer is set as; o/ A5 [: p3 } Q; |+ d- w
** transmitter and one serializer as receiver.
/ v7 {( N7 S5 m: R" K7 g*/
) u0 } r* {8 \. ]) U7 Q, q- hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: j# X; Z: L" T6 q; R' Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) o% z( u# a! t+ c+ r- |( [* o** Configure the McASP pins
+ x! `' k2 N0 u9 ~/ y8 L** Input - Frame Sync, Clock and Serializer Rx
+ {" m! a! `& V# [" j** Output - Serializer Tx is connected to the input of the codec
, Z- i. S" Z; p. }! `*/: m. k7 o, D3 x/ _+ C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& B* m9 R( f8 t: n' V6 z2 W0 mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" _: n5 x! F5 F( [) t9 W& V; |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ m( o$ D0 {) g& [* f" e. \
| MCASP_PIN_ACLKX [, O) z' L/ ^! O9 A: G6 X7 o4 A
| MCASP_PIN_AHCLKX/ V* A! x# l% }+ w7 \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 t* t) ]7 k8 oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 N& L2 ] Y0 T$ G4 K* r
| MCASP_TX_CLKFAIL
( B4 {& k0 {0 y1 Y4 @$ j5 J| MCASP_TX_SYNCERROR1 |3 v( X; ^1 z3 K# Q0 }2 W8 B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 X' J2 }" [2 j" Z/ a3 l| MCASP_RX_CLKFAIL
# H0 Q7 B, b0 k( R' v| MCASP_RX_SYNCERROR |. X! A* {8 R! X3 I
| MCASP_RX_OVERRUN);" N2 P. Z9 P3 \5 @
} static void I2SDataTxRxActivate(void)9 V8 z/ y5 w' Y7 w4 b
{
, G# t; d1 o: u( i6 E/* Start the clocks */3 D7 K, Q5 d& Q2 }* ~4 M7 J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( \3 A$ i3 @ Q4 i9 ?$ FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" |1 w* o5 X9 D, m5 I# x$ l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ w, u5 G; }& k- B; [ G4 hEDMA3_TRIG_MODE_EVENT);( Z- ?& b. ]$ W# E. H+ Z7 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 [/ F0 A# Y+ j# l6 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 K! H' }+ m3 t: I0 E6 g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: C- X" G0 I' H! }7 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" Q& ?- E* z. ?! `9 i: y. R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) Z; g: z- z/ J9 A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ p+ x7 D# J, |8 C% o2 J7 U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 |% M* p# `6 w, K) Y0 |( f
} . l2 o% ~" x, U" g$ M5 c" Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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