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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' q" O$ q% _" ], vinput mcasp_ahclkx,* f: r ], A- v/ L* _4 D* e
input mcasp_aclkx,6 p# {) s: z" G2 c* P( N
input axr0,
% a# m$ C% B. ~4 ~" D% S- t8 n
( R \% z6 Q2 P3 D5 W3 zoutput mcasp_afsr,
) f1 x: ]0 u0 p2 _% h% Coutput mcasp_ahclkr,
# o* h' f; e" d. Soutput mcasp_aclkr,
k7 A9 z+ p5 Q* Zoutput axr1,# k: f% p% a3 Y! r
assign mcasp_afsr = mcasp_afsx;1 Z- Z c# ?! O, q* D) L
assign mcasp_aclkr = mcasp_aclkx;5 f S& G/ h) h$ S! F# {3 `
assign mcasp_ahclkr = mcasp_ahclkx;2 v" \6 y6 X; D# ?+ y- B" o
assign axr1 = axr0; / ?8 V# p- N! B1 _! g) r
6 ?1 Q" E! O( Q- b( g) W' e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : _+ F/ ^ V6 T' r* U
static void McASPI2SConfigure(void)
9 p+ ]: J y6 i6 b{
) V% ~" a, H) fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# v' `2 v8 |: H+ I3 c, g1 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 n* n: x+ L5 O- o" L3 GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ ?1 S) ~( g" K. o& B; Z+ iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( ]& g- a, K& d9 V& n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" h" c* v# v4 v2 j8 tMCASP_RX_MODE_DMA);+ t: |" Z9 ~8 N" c1 }5 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, D3 ?8 S* c5 A3 g* VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; ?' j0 h8 A! ~8 w6 S* j& [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- \8 i1 w! i. T9 m5 c8 `6 L! QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 ~* {7 O2 C8 C' X3 A8 K4 XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 h2 @% [! D0 I2 uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 A) W$ J; C: _* @# Q0 Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. \/ P3 X w% HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 l, q$ E1 ]) t' d$ R. N5 i% }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 |- f- S: t) R0x00, 0xFF); /* configure the clock for transmitter */: O6 p+ c9 M: D# [! A, N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& B4 v" Y+ L. ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* J" ? ]' E' I$ r, [" B9 B! cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* Q5 p% O5 i9 \+ L( D# y) h
0x00, 0xFF);; p# M# Q( x8 f# r) B) C' e
* O' e o. D7 a# A* Q/* Enable synchronization of RX and TX sections */ i6 ?& o1 J" h R6 n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ R5 o( d [! I6 `9 u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% B4 }3 D/ Q9 J/ c7 ^. NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 F) @+ Z" [) a7 T( r# c( w** Set the serializers, Currently only one serializer is set as: Y" i! X0 K" Q0 y
** transmitter and one serializer as receiver.
; y* }4 j* M A/ W! }5 h2 C* `*/( [9 w7 T7 `, h$ K$ J0 b/ l$ I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 d$ B; a$ n/ n* z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: A/ p+ b, {: X. `
** Configure the McASP pins 9 `* G- I- A( T: J- w/ l
** Input - Frame Sync, Clock and Serializer Rx
) X8 Y0 b' V( T) ~, _** Output - Serializer Tx is connected to the input of the codec 5 d3 j& I! a1 R' U U
*/ }& T! v1 ^' E9 p" n8 h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: M' k* z2 F' b+ kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 d! x, W4 _7 D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, l; {( f4 H2 B
| MCASP_PIN_ACLKX
3 _( E6 S6 Q& h2 n/ @| MCASP_PIN_AHCLKX3 X6 `, P: M, H& b$ \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ @- R9 V1 c) u1 P8 P$ S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' |6 y! G: k; x3 o. ]) W; [| MCASP_TX_CLKFAIL * u: ^/ Z( s- c2 @, e+ G
| MCASP_TX_SYNCERROR' j H: ]1 J, N3 f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! _7 Z3 `1 S' t) f9 R) D8 }" j# z
| MCASP_RX_CLKFAIL9 E, r e: P) R; Q, e
| MCASP_RX_SYNCERROR ( ]! o2 h# \' ?8 B- [
| MCASP_RX_OVERRUN);5 L. v9 N" L* J1 F* [1 t, s
} static void I2SDataTxRxActivate(void)
$ u2 g6 u# U6 D# o{+ o1 f6 h+ h5 I! {) o5 ^) m, p7 f
/* Start the clocks */; U4 ]+ B I6 b8 D, O8 ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 h6 r) i. f/ u5 S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 [% D8 Q7 y; a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 Z5 o$ P V% \' H$ k0 C
EDMA3_TRIG_MODE_EVENT);, A$ M y, u4 ^" K! r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # o" h3 ~! u( }$ M; @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
L* T+ Q1 a3 J3 M1 o9 RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 b U4 x) s) K6 M4 Y- `6 r5 aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ g5 c- F1 d8 H& {6 t: w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- ?; \1 X- J8 C# T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ j2 x3 a/ t0 j! e ^( z! IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 m+ s* g% t1 g3 d4 X}
7 T' H9 ^0 N/ u; Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 Z. f5 @' J5 o7 C6 ] e2 f
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