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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 h6 U/ j2 |; I% `9 Y0 sinput mcasp_ahclkx,, E+ S/ q ~4 n2 i. N0 l
input mcasp_aclkx,
0 n/ g5 p) I# v+ r1 B" |input axr0,# E/ g" k9 j4 ?! Q
+ i( w4 W6 d0 k) @- I- Z5 [0 v
output mcasp_afsr,
$ @# L8 `" h2 I! {$ Y. Ioutput mcasp_ahclkr,
) U }& a! p2 z+ Qoutput mcasp_aclkr,
: j/ {. U( l" K6 N( \/ P2 |output axr1,
' J. K( l- B' }% q assign mcasp_afsr = mcasp_afsx;
X% w# }9 c. {8 X6 W) Uassign mcasp_aclkr = mcasp_aclkx;8 L9 v3 s. J/ n, B5 m
assign mcasp_ahclkr = mcasp_ahclkx;. g' U0 L0 K6 Y% d6 d! r" `* b
assign axr1 = axr0;
9 a! U3 ]* e' i- B, a
; k$ w1 Z9 n* _) @# a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 o) ?$ q1 N* sstatic void McASPI2SConfigure(void)
" g! `8 ^! I* G5 z" C- R{
) {6 a: \" z: Y3 LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" W" |$ v7 \3 ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. D7 t9 o: n1 d% H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, P: g7 g l: V" v# p* Q7 h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ b6 \. |% ^- L" ^0 i" h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 d: m( R" i( S/ G9 G# D/ f9 ZMCASP_RX_MODE_DMA);0 K% k. _1 m, n. U' V$ J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 ]: F. O6 [% ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- Q" `; n+ ~ O7 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & d" V: W9 G/ v/ F3 v+ N9 z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: D0 d0 \; ]( S& ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % S) s! a$ l: J ?( w% Z" c, `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ N# F- @4 X/ |5 x J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) o4 b7 F4 z @; n. _: W: }5 FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ c1 g8 S( {8 o) a9 N* o/ Y- GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ L& q% P9 p7 n0x00, 0xFF); /* configure the clock for transmitter */
- m7 v, Z* ~2 b8 p5 s8 jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" B7 C S2 }: r. Q- W+ D- G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! n" H; q' `9 f$ h6 K+ ?1 \5 {; x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: K+ d$ v8 | {5 l0x00, 0xFF);& E2 Y- E; B! w, U" {% u5 o) V
9 s9 ^7 j3 I+ ^6 D
/* Enable synchronization of RX and TX sections */ : q( f: O8 Q: U( [3 \' N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
H$ N9 H$ m# r: x3 }1 N4 ] ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 [) L! {9 p3 v% [. [7 e; KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 W$ F8 {: f0 k9 R
** Set the serializers, Currently only one serializer is set as
1 ?* Z! P+ _( E; ]** transmitter and one serializer as receiver.
: F* X! i6 @9 B! I*/
0 ]2 }% J% B! F% h% l' dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% b D" K1 K: p( f: u& x, k( pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 l' ?: a* o2 o' Z** Configure the McASP pins
+ C$ g s: e+ T5 \. d8 |) K! Z** Input - Frame Sync, Clock and Serializer Rx
; U; g* P( @2 R# |4 b** Output - Serializer Tx is connected to the input of the codec
0 H2 {0 H+ r2 f6 d- d( V8 x+ K% |*/* g; H. G3 k% O/ r/ G0 J3 E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- y+ H. @. ]9 U A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% k( H4 Y# S+ R+ S+ M8 l' o% X EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) r; ^' G' m* h. o
| MCASP_PIN_ACLKX
& m6 l/ @: l; c- e# b8 V| MCASP_PIN_AHCLKX
+ t5 G6 A a, Y" W) s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// P1 ~. j- J" } _) q& V1 n1 E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % Z! U/ D7 j, h& Q }9 l
| MCASP_TX_CLKFAIL
) ]1 c) G6 X; `+ S| MCASP_TX_SYNCERROR
M( \- Z7 v- Y1 N+ ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , O2 {' |! g6 |* ^# v& n ?
| MCASP_RX_CLKFAIL
+ C) z$ N5 ~0 e| MCASP_RX_SYNCERROR
* y5 ?( ~6 n" E4 K% B! Y| MCASP_RX_OVERRUN);( A6 V" X! @7 Z: j. Z7 M
} static void I2SDataTxRxActivate(void)
9 j; N) J( Z0 d3 J{
. @7 A# D8 d7 y; r9 v$ D- S! C/* Start the clocks */
3 @; |5 G& s9 ^ ?7 ]2 j+ N4 `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 X F) I# q5 ` C- Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' a. g4 x% k# Q& e0 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 y9 X K, s4 _3 |9 ?: h" VEDMA3_TRIG_MODE_EVENT);
2 R' h g% B& G" C4 c- }9 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& a- d1 u, P: v0 O& v, o, |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, B$ e6 u) J( }4 H& S* @( c+ L5 j1 ]! P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" M f) `( h* Y( H' Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 E8 k% b5 w6 k8 J5 D/ Y+ E' m5 w6 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. m \5 \$ V O; sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ [: f5 u5 I: b$ N2 @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& U k4 S# s6 \9 M7 Y# F
} 8 h5 H- w5 N6 A) T. l5 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / o" B+ b, W/ ^/ N$ C" y! x0 c- K
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