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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 k+ m! {- h/ ]( Q' uinput mcasp_ahclkx,+ G& u- r4 y5 S+ N: ^/ r
input mcasp_aclkx,8 |7 O/ w. f3 i$ a) Z" v: f+ T* h
input axr0,, ~3 p7 m. d" u1 L
/ `" f k& Q) toutput mcasp_afsr,
8 r- H9 }0 Z" P9 Q$ L( g6 ?1 n& Ioutput mcasp_ahclkr,
" U6 W! O/ Q! J# f3 f3 Eoutput mcasp_aclkr,
+ }3 \# \, f& Xoutput axr1,
. b2 G( n6 @8 x3 @4 V assign mcasp_afsr = mcasp_afsx;+ j7 R3 k( R6 R. M8 O" U
assign mcasp_aclkr = mcasp_aclkx;
# M! t4 O, t8 a8 a+ E0 h- ^) uassign mcasp_ahclkr = mcasp_ahclkx;# f! D& `7 F3 e- V; }$ \' ]0 {
assign axr1 = axr0;
* ]' d2 ^1 `. R* N+ a
4 a) m- t* a, s, X( K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 Y- }3 n, c4 O1 Q# Z! l9 `
static void McASPI2SConfigure(void). J8 Z& i+ I8 {. F* a! A/ n
{! U: Z! x2 O+ [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; X: P$ c& A$ j/ K- j3 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 H5 p6 j1 V. j U% z- XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); u( A: O5 i) F4 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, ^4 H/ y8 T4 p9 z" A2 o; nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 W9 B2 C. s1 y g! y' y5 E7 vMCASP_RX_MODE_DMA);
) x, F% {. l1 j* {; X5 I; p) ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; n- t4 q# z, v" z5 D' q6 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% c$ X8 q8 V1 p. N4 k( ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
~6 p- G2 F4 U. v, G* {& a$ l w4 E) kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: ?. t4 V" g1 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - t! A1 O6 n2 t/ m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 ]/ e. O5 O B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ L. x8 V. U6 }2 }2 M2 l7 cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # r; m1 ^1 t" Q& |- _# O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; a# p6 e8 d( d L& U: W, Z. u0x00, 0xFF); /* configure the clock for transmitter */
" s" a' u# V2 p5 N" W6 TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 H3 ?3 X3 \3 UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" b0 J" d$ S' X+ uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 h8 r3 Q' z& Y: @; }0x00, 0xFF);& t6 p& x7 A2 V3 V7 \1 I
3 ]- z8 |# U$ l7 I2 H4 Y( @/* Enable synchronization of RX and TX sections */
3 _& b* P1 `) f: E1 j2 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" ?- q3 u: f7 ^3 e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 y( n2 V: c. y: F0 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' d% D8 j* P% g- z6 |** Set the serializers, Currently only one serializer is set as
# \- R/ n1 |" v& D: e9 V8 t, z** transmitter and one serializer as receiver.9 K3 J! u+ `2 y: G
*/5 s- {. n2 n: T! I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 U' i; c% X5 c/ N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& {% n* |' B% @' h/ C; |** Configure the McASP pins * d4 G' N7 F Q& H
** Input - Frame Sync, Clock and Serializer Rx
' Z& i4 U- }" P( C/ V/ l0 @** Output - Serializer Tx is connected to the input of the codec
9 X6 F' M+ `2 ]*/
, p# ^; o( @! i- sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# t# Z% \% N2 S7 ]. W iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 P/ b$ `, l5 ^" K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 d" F: `: G/ }9 w| MCASP_PIN_ACLKX
]- {/ K- o9 P1 Z| MCASP_PIN_AHCLKX' D" Z8 F! p# L @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( @2 C, h" c. j- z& sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , C3 a- p9 J. L- i
| MCASP_TX_CLKFAIL 8 T3 z+ H& W& y7 l4 M( v
| MCASP_TX_SYNCERROR& W. I% D7 K( v8 K* J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" {4 q7 p% A, o3 i3 {| MCASP_RX_CLKFAIL/ M N2 [$ Y& o$ Y
| MCASP_RX_SYNCERROR 2 g4 h5 Z w- h" E: U
| MCASP_RX_OVERRUN);
6 d, \ e( u1 h, B; G k} static void I2SDataTxRxActivate(void)/ }: P- s" b! M3 T8 M
{
" H; w, f* E0 e# e/* Start the clocks */
: y( t- p( ~% O! _2 a; GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# h) C: }. `+ v- A' ]/ r* W' GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 |# F& p* f- r( r, b9 B* R4 p$ v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; f( d$ ~5 H' D9 k( N+ C2 z& iEDMA3_TRIG_MODE_EVENT);
( V# U1 B! J9 C9 ^, A, R8 L, `/ w6 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 G1 ]# g0 Z5 Y/ v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 W3 X: }3 O- Z* `+ t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, w$ j: E, I. i: Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 x3 }. n2 }8 K* G. V4 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* ] h, A4 D1 Q) _, w! |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, D5 L3 u5 s6 S3 U6 q; s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 W+ Q+ ]+ ]4 W& Q} % d7 D$ \$ f' X* A3 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 {' U1 |0 C* Z) f* b1 d. [
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