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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 I7 ?/ A/ K, `9 D+ V
input mcasp_ahclkx,9 E0 U; e0 f; [% P/ f
input mcasp_aclkx,
+ j" W( R) N) b4 x, Xinput axr0,
% @- G/ U9 z6 U f$ ]' I+ a8 p2 r/ ~+ X9 |0 f6 ]% ]9 ]( U8 Q
output mcasp_afsr,! D- Z k+ R3 r3 ?9 V5 H
output mcasp_ahclkr,
; ]7 ^; K5 H& M% Toutput mcasp_aclkr,
" L+ x) k8 i, F u2 U' b' N, V% eoutput axr1,/ u2 I7 f$ w+ X- }
assign mcasp_afsr = mcasp_afsx;4 q/ R* u9 t& S& v0 b. B' n) U9 ]0 \
assign mcasp_aclkr = mcasp_aclkx;3 Z5 R' r% A2 B( {
assign mcasp_ahclkr = mcasp_ahclkx;
6 d, _' n5 W( X. i1 v+ ~assign axr1 = axr0; 8 D; v( T9 Q6 l* \0 d
3 I+ ?2 K6 K# G4 s4 ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ E3 K: F9 @, C2 @static void McASPI2SConfigure(void)1 d. X6 E; Y& c l9 Z8 z% y& a z
{
) I) c. z0 E2 s3 aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# i& b+ j9 R, E5 K! U" DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 L7 I1 n/ Y6 v6 x* n7 x% T3 o. UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- F- v0 Z: ?2 ~. m3 _- U+ n3 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 o5 v# i" u9 y5 T1 W& E0 |) s/ xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ P" R0 L" v+ I( @6 V
MCASP_RX_MODE_DMA);/ V0 H% q, _, m* M% L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 V9 j, K8 o* P- E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- O8 I. T! @" q0 r% {$ I5 ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & v$ |: g9 n |8 S( [& P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 Z2 \2 m; j0 YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 [; k" @/ V" p5 {0 xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 B; f' I/ C- g% s; x% GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ e7 v8 X( J2 I# QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ ?" w3 v+ w! v/ N; [' V/ PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ y4 \9 T+ X5 S0x00, 0xFF); /* configure the clock for transmitter *// A7 L3 ?& N, G# P) g" K0 l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 @: i. Y8 a) \' W9 ~9 J/ [9 Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# r. w5 ^! Z1 KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& \* x. c: g6 n, k0 R* F! ?. B% }& H9 ?0x00, 0xFF);' x/ M4 i: O* K1 \6 u4 ?8 l; i2 t
& B. M& f, u+ Y1 G- K8 g/* Enable synchronization of RX and TX sections */ 1 Y9 e( M1 K8 r) f2 T0 [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 V( w* \' [ [- g) M( V4 W; Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 w" B; Q; g# K3 [. i: z N! ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- D* T6 n- q* p5 b
** Set the serializers, Currently only one serializer is set as
& Q+ U G, Z1 X- ^+ b5 O J0 P** transmitter and one serializer as receiver., `' F# ^& ~+ r) n* \3 k/ N
*/
% U$ f& ?* F0 u, ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 ~9 t2 i" t% Z2 M8 V! t, U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' m0 z7 D( d, d/ R
** Configure the McASP pins - X3 a2 Q: `$ Q6 V8 c$ ]3 a
** Input - Frame Sync, Clock and Serializer Rx+ [: t7 X+ v# g B: J8 b$ D% B9 b
** Output - Serializer Tx is connected to the input of the codec
6 j I3 J! z% Y0 [+ n*/' F, H! p$ F( n! o0 L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
m( Q4 Z2 B& lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: w9 o0 L3 z! k( {- yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ ~7 @: ?7 v, k) @# K| MCASP_PIN_ACLKX
, b( i: ^& a3 A% U( D0 D| MCASP_PIN_AHCLKX
. ^# w, @$ J# o" M/ B2 u9 y( a! s, z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 g" _) r' Q% |: ~6 b- b+ i( T, V# H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& n; O/ R9 b0 b' c4 a% v! B| MCASP_TX_CLKFAIL
' m6 @8 Y. V" L1 Z6 H& E2 R| MCASP_TX_SYNCERROR$ U( J: u' { E$ a$ w* Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ V2 w; [* [7 h: |) U1 L" H( l
| MCASP_RX_CLKFAIL
3 q/ Y O8 m2 N% h$ u" V* u9 n8 M| MCASP_RX_SYNCERROR
0 b5 F9 c! C7 ^. S. F% F; x' \ G( `| MCASP_RX_OVERRUN);
/ f) u) ` B( n, Y( H} static void I2SDataTxRxActivate(void)' O7 r- q7 D7 O! x6 b3 b' g* \
{
0 k6 y, y& X" l1 _) G) V/* Start the clocks */
! i" j$ c0 r: [$ g2 M, Q6 uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 _' Y" @, _( Z* G: W/ jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: q- I. t+ p" A% P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 ]. q( B& x1 p; c4 M# hEDMA3_TRIG_MODE_EVENT);# Z( @( ~$ M j7 G9 d0 i- G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, f' p# s9 f' [9 x* i; J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 v6 F. R' L1 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- V5 K0 K W3 Z' oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 e0 P! j! k; o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% @, O, q. v4 ?8 o8 f4 l9 r8 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 _0 ?7 H& V0 n0 @+ Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 n5 G2 o$ F( n5 G( i- H- i' b
}
6 M6 C- h" H4 W8 q$ U( a8 C+ e: ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. a" I! }" m" n; c7 n% b! n9 ]
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