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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 R" Q# i) Y2 ^! q' Dinput mcasp_ahclkx,
; J2 G2 `9 i8 ], q* e4 | einput mcasp_aclkx,. ^$ l% W5 F+ ?0 p7 `
input axr0,
9 @' r. c8 I' A4 w- P! ^ f+ U+ w) J- t- U& L0 |. G, Y
output mcasp_afsr,+ C D( `4 J$ V5 J
output mcasp_ahclkr,
5 [! @* Z6 S3 [2 q1 P, K \output mcasp_aclkr,. y) S) R5 o0 M5 M6 ~ Y# |
output axr1,
$ {8 u8 I8 ~. A6 d* V3 _. d assign mcasp_afsr = mcasp_afsx;" i# |$ X! w: U/ [
assign mcasp_aclkr = mcasp_aclkx;. \/ M: k+ A6 C5 ^
assign mcasp_ahclkr = mcasp_ahclkx;
0 a$ E$ M0 k! g& j8 nassign axr1 = axr0;
1 W m6 D: D, e+ Z. w/ S
_- l. | I X5 X7 r+ E( f4 l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
i( [% s9 A! m" ~( s5 @6 Istatic void McASPI2SConfigure(void)$ B9 Y. V$ p5 N) E9 _
{
G1 _/ a2 g+ S6 h d$ l. WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
R4 T. M. p, ]" }( v2 oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% |; R( x( Z7 c0 ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# `1 s# b7 G; H c, P, iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 n8 S. `- X1 v; e9 |7 K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 c, B" ~3 o, L1 @
MCASP_RX_MODE_DMA);5 X! r A/ i# `) q G! w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: Z; d% T! ?# `) V T" s. T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; W, ]0 }( ~5 o* r! |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. ?- u& h1 y: i; dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 [; V4 h# C% X. T% [7 \2 M# IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 T& t) _$ a. N) \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 A2 Q: p' N; _; r* f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 R! W8 n1 @9 s" K% \& S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 b- T$ Q% [* O- h: W) i( g) r- l# ]8 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 G6 v$ I: R8 E
0x00, 0xFF); /* configure the clock for transmitter */
3 g, X9 U9 |6 C) JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# \1 l7 k' h6 G/ T* F& H3 C- UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / L, ]* O4 U+ J9 ~9 c9 c4 P! S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 r0 S* V( q. D, J
0x00, 0xFF);" U+ i% P/ I8 K0 |
2 r5 M' }+ I6 ~$ ]9 y; S, i( v+ a/* Enable synchronization of RX and TX sections */
9 ^7 p' X+ I/ M$ q( c4 n5 @2 cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# H3 y* y! W1 E) J# AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: h5 G% T# L1 T2 pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ b/ ?+ r- f _; Q** Set the serializers, Currently only one serializer is set as# g9 {/ ]( Y: q1 P1 y
** transmitter and one serializer as receiver.
+ \ Y" Z3 _$ {" q7 Q*/
0 `* D6 Q% c* J' }. S8 SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- }( d4 }, e5 b' P5 jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ ]6 r1 i T7 e b; o- t** Configure the McASP pins / [# M R$ m% n
** Input - Frame Sync, Clock and Serializer Rx9 U- R5 I" B5 u+ h; F9 T
** Output - Serializer Tx is connected to the input of the codec
' E' @ \% Q! @ C( e; S*/* N/ I y# W; W3 a; S' j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! l( j/ D& ^6 g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. j$ M% k6 r& R$ n$ u( m2 ^4 v$ {! B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' @% G$ T2 _- K5 N| MCASP_PIN_ACLKX2 o! T0 ^, c5 v8 @- E# f" Y6 K
| MCASP_PIN_AHCLKX
I4 t& n) r8 k! U" W" g2 s* }6 `5 m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 L$ w- I) i- s8 ]/ ^1 z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ U$ f+ h$ l q T" w; ~
| MCASP_TX_CLKFAIL
2 g' L5 b5 ^% G* A! j2 m| MCASP_TX_SYNCERROR
* D+ h5 C& K3 r7 k; }7 `! s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 H+ U3 {1 N& G" w5 `# ?) `" E| MCASP_RX_CLKFAIL5 b( [8 E% R) C% ^6 s9 J
| MCASP_RX_SYNCERROR . U6 A' g' l$ z6 v) }
| MCASP_RX_OVERRUN);
9 _1 k& A+ ^- V; U} static void I2SDataTxRxActivate(void), t: U/ S* Z7 N1 p' J9 K: ^* _
{& e3 y3 x# J5 l2 x1 b" H
/* Start the clocks */
7 y+ l. W$ g, \8 j* i2 SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 T- v! Q% w0 h4 Y: D7 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" s% g& H2 m# E- T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 ^# O6 s( ~( u6 j( Q# P- vEDMA3_TRIG_MODE_EVENT);( [2 Y1 m( ?! z/ }3 B; c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & H- p& u w0 p, x8 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: q5 G, |/ x8 R2 C- X+ IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ W; K' {8 n8 e c8 `) W, s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" p G9 \6 r7 Q1 I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 g, ^9 C# |. t$ c) X( y# gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 w% `9 ~* A# l% z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. |/ z6 ^* s9 D! e8 \9 ~
} % E& c v d2 A% p6 W0 a, t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + V, M! I+ K6 d
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