|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 L7 j3 C* r& \+ P9 rinput mcasp_ahclkx,0 G7 c7 r7 m7 f# n, G1 E
input mcasp_aclkx,5 U& N2 J: k6 e/ s5 c: z
input axr0,
. @8 T0 l! I$ c4 R9 R* W! o$ ?& r, t' S& D5 b9 `4 q& R1 F8 o
output mcasp_afsr,
) z' S2 O. @; Q( }output mcasp_ahclkr,
/ }9 _- t. f$ _4 woutput mcasp_aclkr,
5 ?8 \ _3 y R! Foutput axr1,1 r$ c: ^; G I; b
assign mcasp_afsr = mcasp_afsx;9 W% V0 [& v. k0 X# Y0 o' y
assign mcasp_aclkr = mcasp_aclkx;
0 U! J) a' l, |; [4 vassign mcasp_ahclkr = mcasp_ahclkx;
7 E9 j+ e5 U/ z( T+ G4 c: qassign axr1 = axr0;
# N0 q" @9 P2 h1 h' G# }. D. z! N3 B# _/ T& s# r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 M( P' ~5 x9 e9 ?2 X
static void McASPI2SConfigure(void)) N- e4 s/ c8 w$ C7 x) P
{
' g7 T+ j8 e @McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 r8 F F/ P$ ?! O! a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ j0 A7 W1 S9 I0 A! rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% E$ ?& Y( B& ^* ^* jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, |- Q. {5 o. ~ u# dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% b( o; V% `8 O5 f! ^MCASP_RX_MODE_DMA);
( K+ ^! i& z' Z! v" b0 iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 u- s. x5 w ~& L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 f6 y7 ~& K3 N3 V( u5 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ Y' W5 E/ g" xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* S% N0 |* s7 q' C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
}1 N J) K9 l4 _6 ?' xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& p/ U- r) H1 r: N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 J- C0 m3 X0 b1 k V1 iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ y! Y: S9 N/ k( z# u2 E1 KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* j3 c1 d- G i f0x00, 0xFF); /* configure the clock for transmitter */
6 Q7 V! f8 d6 B) q1 LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" V5 O2 ]0 z; i, r8 j5 y+ ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, n& j3 ]. B( f3 E$ fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 w( W) N- D0 l1 s" C5 V* z
0x00, 0xFF);
) A3 t8 m# ?9 n, G" g8 t4 t# x5 y, {, S9 X G D X# N" R. p1 [
/* Enable synchronization of RX and TX sections */ ' X, k8 j- V$ b3 G. M U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 n$ B" [& K$ Y4 q0 [* hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 B! N7 L1 @4 R" b! |* f# h$ b0 P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( s7 \+ U3 Q9 d( F** Set the serializers, Currently only one serializer is set as! ~5 Z L( M3 m$ Z% ]( p& ?
** transmitter and one serializer as receiver.$ u7 Y1 Y- ]. Z) m# Q V
*/
; Y6 h* [6 g QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, ^/ f+ X* ^8 [; p6 ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 C8 Q9 f, c/ A- l* h
** Configure the McASP pins
2 q: v% Q2 `! T. ~8 U4 H& P7 p** Input - Frame Sync, Clock and Serializer Rx
1 R/ s$ g5 Z: }5 v** Output - Serializer Tx is connected to the input of the codec 7 W3 j, z5 W& `0 b0 b
*/
6 ~) T* L- r: `! @: H' {* IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 R# G* i9 h1 ~0 t" RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ ? j- C- I9 M% o# a" h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; U" K; n. E% S0 q' a G& h
| MCASP_PIN_ACLKX! n* g0 u0 R+ p' V& o8 o+ [
| MCASP_PIN_AHCLKX
3 ^& z, Z8 i+ r! S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% ^) m H& @& B) H$ z+ v* [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( a6 y0 k5 f1 z* U: o9 w| MCASP_TX_CLKFAIL
5 X2 w0 K! ~7 e9 e0 D+ k" _0 Q| MCASP_TX_SYNCERROR% x$ a9 A( P& W/ I1 _* B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ ?# w% j0 f' c$ e
| MCASP_RX_CLKFAIL8 P6 e* A' ^* h0 \
| MCASP_RX_SYNCERROR 9 M! p' O, Z; W: k, l2 D
| MCASP_RX_OVERRUN);# ]1 I$ a9 C q
} static void I2SDataTxRxActivate(void)% j$ |8 V+ u# b) g L2 p; k
{" t% T' `4 h6 z/ W# s; {: ]7 K
/* Start the clocks */4 D6 `7 i* u$ i. ?* p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 `( R9 R2 s# zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: h' L) N) O: i1 H x: Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 m, [( ^4 A" F' d* Q2 W9 m4 o
EDMA3_TRIG_MODE_EVENT);
: o! i% v9 G; a3 `) j, _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( c; ]* f* C( M4 C% rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 a" Y5 g7 _ i& B7 ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 |$ C" ]. p( @! d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" H4 R) O/ `; F4 t0 L" V/ zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( H% \" U4 u/ |# q! nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% o: C, y% N0 N$ y4 G$ B4 f, _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' _% w7 a2 |; B( p: o} 9 J( J3 N) Z1 v! M C7 @6 ?. i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
( w9 t% e4 G0 c- ^, B. G |