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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 j, h. o5 I# N) ^, s6 N
input mcasp_ahclkx,
) i6 t9 L+ Y+ a9 [input mcasp_aclkx," ?! L1 o2 q( k6 z2 j3 z4 [
input axr0,
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* D6 c: `8 g3 F6 i& K8 ^output mcasp_afsr,
: C1 i: ~8 E6 ]3 Goutput mcasp_ahclkr,
% C, n% j* {& d. U6 Uoutput mcasp_aclkr,
' k8 X2 \2 U9 h' P o+ ^+ A* ^output axr1,' {2 {! W0 e6 A+ z9 f( b
assign mcasp_afsr = mcasp_afsx;2 T* C; G- t+ `, b' e' u
assign mcasp_aclkr = mcasp_aclkx;1 ~4 d A4 _8 [8 d$ |1 t
assign mcasp_ahclkr = mcasp_ahclkx;7 ]: ]- v+ g# C% o' J% W
assign axr1 = axr0; + Z; c" p0 k- d) Z, z
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 p3 l) [; L! O$ M% g2 W" ^static void McASPI2SConfigure(void); ]* [( s1 K% x" c0 O$ \! |
{
. u. X( L7 ^3 J7 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);) A8 S: ?5 `+ s4 z5 W4 v4 n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- I: a! }8 q8 Z* S+ ^5 S/ x+ @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 |& r/ N- {$ o, e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ ?" ?: {. _) XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# m, y. w% E1 n+ O: d J' O: f" h
MCASP_RX_MODE_DMA);
9 d* f( Z' Q0 u5 NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, |' d& ^ |9 N/ \2 B4 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! ?- r, O# M) d, H3 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 j# E1 D3 l0 \! }2 m3 B2 @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# A r* ]* J% b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 o# e) c- O! L( ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 Z- a) A- L: |$ D" BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, `7 ?' ^- ~" gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 W$ ?. p) M( p" g9 l' x" Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 K$ j) r: R' A9 U1 d0x00, 0xFF); /* configure the clock for transmitter */
1 s! W c) r3 ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 K5 l0 e( e5 x1 v+ s* e2 G" w( NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 e6 b( ^3 P- v% R4 c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. y& b4 M+ o: E
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ & K7 r4 h% \7 o! A7 e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) @: K) y0 r1 t3 r8 {3 X0 FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 }0 q8 Y: G- D4 H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) Y7 x5 O( V+ n+ }
** Set the serializers, Currently only one serializer is set as
D. p6 x/ T8 \** transmitter and one serializer as receiver.3 ]4 Q2 c4 R2 |( U/ {1 c X7 ~
*/8 Q' u& y4 d: m$ Y& n, i5 X; \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 X6 F$ m# i& x/ p4 E2 O: XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 V/ Y/ h7 n( K3 m7 ~1 A+ Z** Configure the McASP pins - q Q# A: W+ g+ j) v
** Input - Frame Sync, Clock and Serializer Rx0 l3 p/ k2 v3 w2 b# h' P
** Output - Serializer Tx is connected to the input of the codec
" z, M! Z7 ]' ] x; b0 B0 j- Q+ T*/
. m3 \0 H$ l" W' A9 j$ nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ V K/ }( {1 F4 `0 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 _- A* i2 q7 ?8 Q! Z& O! L- Q4 j: }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; U& m. }* ?! ^$ H+ w| MCASP_PIN_ACLKX
% q7 A$ z" Y! L4 s$ A7 }| MCASP_PIN_AHCLKX
4 }& o# Q7 o% l! z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' _1 s5 t, q& w0 K4 Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 E% m- B3 L; A, b. ?
| MCASP_TX_CLKFAIL
% L$ ]% b' K! `* o; p| MCASP_TX_SYNCERROR
. q( a, d3 C% z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % [: K8 O* a" q' @. I2 A
| MCASP_RX_CLKFAIL
/ ~+ B" b, x) @# ]0 e* W& H| MCASP_RX_SYNCERROR
8 o( w0 M; M# P7 U- b S6 V! u# W| MCASP_RX_OVERRUN);3 C6 ]9 T4 w; G) i+ n/ `
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */& d9 g7 |0 p3 h+ S! S. q' I# _( ` F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% ]7 ~/ ~5 C0 }3 C- ^1 U6 s: w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 E0 ?7 f, P6 q& FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ R; s- K a& T* R1 G) _. @
EDMA3_TRIG_MODE_EVENT);
: `; p- m6 H: VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( ~+ K, z4 R2 Y! S$ a$ bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 ?- Q) u. Z: X" H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) @7 }$ |0 L% J6 y! o G& e. GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; ?; M/ O$ Z: N7 Y& S0 l$ cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( j& z+ F; e; Q: e ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" }9 _0 s8 M/ h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
B& X0 [% i1 |: v" h- c}
4 s" m6 S0 D; [6 C0 m: j7 v6 {/ K) G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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