|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# w2 ?6 z) U9 e3 H* L
input mcasp_ahclkx,
! l, s$ c% P! }input mcasp_aclkx,9 ?% ?& k4 I- G+ D7 m0 {
input axr0,7 m% C# P1 u% c4 P, v% @! n4 q
! q! f/ Y# |4 ]/ _+ A& V) B
output mcasp_afsr,
9 [+ r" N; i5 f- j( J, A0 Qoutput mcasp_ahclkr,
- f j% t" B, C, a* W3 youtput mcasp_aclkr,! }- d! m2 O) P& d7 I* O
output axr1,$ ]5 Q2 K$ H* Q0 m; j
assign mcasp_afsr = mcasp_afsx;; _& q! H. ?) O
assign mcasp_aclkr = mcasp_aclkx;
. b( B7 Z I4 ^; c3 \8 _( x3 B' ~assign mcasp_ahclkr = mcasp_ahclkx;5 h1 ?/ q9 v: t- f" }$ f6 y9 m
assign axr1 = axr0;
4 V' k* z- Y* P- l/ P1 j1 J- S7 G* w4 t# V/ w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 g. L P2 Z2 Y: D
static void McASPI2SConfigure(void)
" u# d& K! b; D: v. P{
: e/ x$ ^( O. X' `* ^) a/ TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 j7 M& @2 N1 e1 U3 Y; ~/ e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* e' c: i$ v7 ?' l8 ^) u; K" A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ k; ~9 Y5 i& o; ?3 JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 N5 c. ]! a. o( a4 F; i% VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 f" W; {; R* a- ~1 m
MCASP_RX_MODE_DMA);
l K Y+ v2 E; l7 z& nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 @$ `! o+ a, m) G2 tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- C2 w4 M9 I$ W9 lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : ^. x* V' E! X; y& l! B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
X% c, I4 m! k; qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 N3 z: P& D! e7 q# ~. `& Q5 T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* p' A/ n$ y2 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ F% N5 _2 f; p; q+ @. fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
U- Y* v5 [+ ]5 _7 w6 @9 O+ [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% K+ \2 O! [& }' u1 a+ T3 _- h0x00, 0xFF); /* configure the clock for transmitter */. z( ^0 q( R/ W" l* Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; ~3 }$ m7 t' P! R. GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, ~- W+ w x7 z) DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: ?4 ~6 [ Q9 }+ p0 [ [0x00, 0xFF);& M. ^( I# k1 U( y5 A
5 F0 N" w) h5 n
/* Enable synchronization of RX and TX sections */ # X5 M4 z+ ?$ B' M9 p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% q% G7 p5 l( ]& N. w0 N5 f3 MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 Y# J- i9 k, j z2 i( u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 a; v+ b6 x! P** Set the serializers, Currently only one serializer is set as9 S! b8 i3 w, G* x) b
** transmitter and one serializer as receiver.& ?" j9 k0 K; d" R3 T- ^
*/
/ t. N( u7 ]3 X rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# L$ t) u1 D' t& E, t% j- B! E, u2 DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) U$ @2 I# z. M** Configure the McASP pins
9 [( ?8 a8 n) d: j5 ^( T1 {" D** Input - Frame Sync, Clock and Serializer Rx8 J, h+ |+ v% O2 K# Y8 _& `$ H( `
** Output - Serializer Tx is connected to the input of the codec M: W/ L+ @# F$ U0 V! g1 g" E
*/. e. \3 W4 t$ X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ d- {. N; N! l: u/ h) Z" ^* A$ D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; l3 L& |# Z8 }6 w4 V; Y$ R& BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 l) v& k( L! U# g5 Z| MCASP_PIN_ACLKX. i/ L' C4 o7 v0 M: Q8 V, r: S
| MCASP_PIN_AHCLKX
) S4 P9 G6 L4 R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) T% o! C0 ^! x5 f& QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 v5 K- Z1 f8 f' S6 X( j; T. a| MCASP_TX_CLKFAIL , v: I3 u. K0 f: e. |4 U) @
| MCASP_TX_SYNCERROR
9 F( m$ K& G/ ~) h' a; c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 K- T$ y( E/ ~3 ~/ o0 L, A }! ^| MCASP_RX_CLKFAIL
" ^* ?; U$ `% K3 ?( h| MCASP_RX_SYNCERROR
3 p. O+ q0 a/ c3 t' u5 E| MCASP_RX_OVERRUN);
& j1 @8 b/ e( ]0 M0 Q3 J! Z0 B} static void I2SDataTxRxActivate(void)6 Y4 T/ w t8 u/ M: m
{4 h9 V. N4 Z* _( M) \' _
/* Start the clocks */) t" t0 U% V# T. L: o; ]1 C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 o) B% j7 n9 I0 f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 p0 Z2 O: E) W X7 B8 _: x1 F' D4 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& u/ s' T/ M0 O3 \5 i) ]
EDMA3_TRIG_MODE_EVENT);
: A7 R3 N6 u/ HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) R; g6 O, I. y* e7 q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ r# ?/ q4 B/ M; V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 T2 P5 h$ K- [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ P1 ~$ J" b" ?/ V. N7 y) S1 Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' g/ Z9 C% k3 n; KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 j' b: w; u% R6 e" eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 o: D+ c3 R1 R; ^0 }+ l0 z} 3 C& U7 U' c- y4 d" s% n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
8 G$ o. k1 g5 f! z; x |