MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
& A2 R1 D/ j0 k" P0 K$ ~input mcasp_aclkx,
( \" c9 q) n4 N, @/ C: h& \input axr0,
# w5 i7 H/ I; ?' I: b$ I
output mcasp_afsr,
output mcasp_ahclkr,
9 v5 q& E3 K1 C: _' S+ T( goutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
3 j+ ?# E: m7 D. G% w8 n; m$ xassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
: ?2 F) N: g1 p; |6 {+ r6 j2 Oassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

4 \) v, ~+ E" e; w' u) E

static void McASPI2SConfigure(void)
2 W$ q0 P. H$ E7 Z7 M{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ r( z8 h! g- `McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, W  S4 @( z, L' kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 a+ O+ d% v! KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ x7 b- r& ^% l3 S& p- eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
+ `! S! ]) C5 e6 J$ ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 G; o- `9 H: n7 J. c" O% a- uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* i4 Z, w3 Y% p" K0x00, 0xFF);

/* configure the clock for transmitter */
3 I# P; s; }: F  YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
7 J9 j' _8 T" I9 k
1 t+ t: L" Y) N" F, ~9 i( D/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
' T* T3 p* @% \& C) n* T7 i** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ _* x' y* s) m, {! ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
/ R% c! P( T; `- ^, ^3 T** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
. A! b$ g8 t8 Q( M  l2 R+ w** Output - Serializer Tx is connected to the input of the codec
( G. M) V) Z0 V( a; k8 t*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 L$ n6 y, F* X2 KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# z; K; T2 t" M5 c| MCASP_PIN_ACLKX
! Q, Z5 D% @; l& s8 ?| MCASP_PIN_AHCLKX
( Y. n0 ]0 n* `| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
+ @1 V5 Y; x0 U- ^, U2 E6 S- |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 t0 {2 p0 S0 E% g, h| MCASP_TX_CLKFAIL
$ {* x0 A% N' D& \! @| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 W) z! M: p# M. ^, _" w| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
, A) ?  s8 p0 a5 H| MCASP_RX_OVERRUN);
# Z1 @7 }) h. ^3 a}

static void I2SDataTxRxActivate(void)
  }8 r8 s: i" P, i1 o2 {, ~{
3 X( f8 M/ ]. t9 A/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
' ^8 x$ ?: r4 _- W- ~( aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
  s3 N5 S4 l* g+ iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# n' {, Y4 y" w4 j1 _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

! n; u$ v" P; R* ?

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.