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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, b1 `( r t5 G6 C
input mcasp_ahclkx,6 D( T m2 h L j& M
input mcasp_aclkx,& ?5 F, p* z. w7 ^. J( _
input axr0,6 k2 Z6 f# {9 T& ~' |# O+ e: T
. G% E/ A: M. V& z! Moutput mcasp_afsr,# G* Z: }0 Q/ ~# U
output mcasp_ahclkr,
+ M! S& U! S2 Z+ Qoutput mcasp_aclkr,* h$ ?+ _4 h' H* @$ n X! b
output axr1,
" N- d7 ]& X. i& y$ C7 J! [: E& M5 Y% _ assign mcasp_afsr = mcasp_afsx;: u' n+ Y1 A6 `3 P
assign mcasp_aclkr = mcasp_aclkx;
7 _: I9 Y5 r+ p0 P) R1 Z5 passign mcasp_ahclkr = mcasp_ahclkx;
* y6 ^& N& e4 V. f5 Fassign axr1 = axr0; 4 L+ E; q% w6 |( F
3 f5 t$ }% [% d$ G+ k4 k( J) f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . d' t2 L- `) r8 |" t6 R
static void McASPI2SConfigure(void)
- {5 T1 n9 }' {/ C9 E Y{/ f. G( D+ i8 G. ?% ^" c1 a3 _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ A0 U( ?9 s5 Q* G4 D o& I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 W. p8 r& H: P# B/ _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( n+ t! e, A" f$ oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# f1 a2 ] a+ gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* K. A+ Z( ~+ o/ z; }
MCASP_RX_MODE_DMA);
, F1 ~2 m& |- R1 T& UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 j8 |" V, ` b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. Y: `, X' e4 z- H# u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 @/ r. ] _% j$ m9 F5 x( }% \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
B6 @) M) {; C/ [ V' gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' c# g* `3 R! SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' C h0 Z! x8 s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 j4 L. m( }& f# ~' W7 O5 KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - T/ D7 d* ?0 ~: E$ g1 E9 E5 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, M3 S3 X1 A& Q9 ~& J
0x00, 0xFF); /* configure the clock for transmitter */
# O4 u* S* k, c. K4 r& q0 }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. G4 k1 ~7 B' G* }2 HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# m ^) j( A" t8 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 j- O; _( v% e0x00, 0xFF);
, W# f, h H# T7 V9 F
* Y+ f, P( d* l6 V+ x/ U8 Y0 Q/* Enable synchronization of RX and TX sections */ 6 E8 H' Z( f/ l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 T- b3 `/ L x8 ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 x- g2 n2 R9 X. {$ g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ D7 \- Z! p( F) f3 j
** Set the serializers, Currently only one serializer is set as
1 m7 H7 B" E. s4 v** transmitter and one serializer as receiver.& x9 O7 |, _: q! d) X" [
*/
2 T& \2 |( q3 L; Z/ N( FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' Z% k2 y) Z+ C. }2 h* oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 Y/ {. Y/ K; p1 f8 H$ X** Configure the McASP pins
# p; g, a" u6 T$ R" c" b** Input - Frame Sync, Clock and Serializer Rx
9 g& V* X6 \# Z1 v8 l9 v** Output - Serializer Tx is connected to the input of the codec 3 s+ J2 l2 k4 ^" F' q
*/5 m% d! M8 R2 k6 M; q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 b- a H+ g4 Y6 u3 ? m- QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' d, r) h+ g6 ` k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 A5 y$ w2 b% E5 L| MCASP_PIN_ACLKX6 W8 w* X! l& O* B
| MCASP_PIN_AHCLKX
0 J1 t* p6 i6 |- o7 g7 z0 m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; C" Y/ g, ?; gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) o4 W$ i# j7 j# E| MCASP_TX_CLKFAIL
" B. ?5 P0 {& I) |# p1 G| MCASP_TX_SYNCERROR
. O( l. i6 ]( V! i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" S3 H. U. h; [8 l9 [( Y| MCASP_RX_CLKFAIL
8 ]5 i& z3 a0 z( p| MCASP_RX_SYNCERROR 0 U- P5 |. P8 J+ g+ h
| MCASP_RX_OVERRUN);) p; w2 Y+ ^% N0 U5 `7 j
} static void I2SDataTxRxActivate(void)
" L6 a! Z/ @1 d7 i5 G{- X+ d2 p% i. h5 y. r* k/ T
/* Start the clocks */
% R( E5 Q% H' N, r: ]4 y3 x6 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, M) S: H7 T3 p: c+ E: E% E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ j1 b6 g" q+ ]5 P" `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 E6 M- s& T' V0 U. D! |/ D! Y
EDMA3_TRIG_MODE_EVENT);" [/ h3 m5 `0 H! K0 ~3 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 A- I+ T4 y0 Q' o0 [1 L# \" J# R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; }; ?* m( I: a. T4 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# V8 ~/ b/ ?* P8 F u# O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
`; x2 B' g: pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ U) i+ s/ G/ _# l. e2 I$ Q# XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& J; l+ G, v0 j, @5 `. g- k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" f5 f9 k: C( ^' H! S. g} ! r% i5 ` P+ q4 L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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