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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% l0 W* j5 {- v) vinput mcasp_ahclkx,
( C* Z: W( T/ f6 h) z C% `( _input mcasp_aclkx,( e% F8 V: h8 B: [8 x
input axr0,
- Q3 d0 d. M* r6 j
7 E! _; C( P4 X9 Ioutput mcasp_afsr,
: X+ J) ]1 f7 P6 a1 coutput mcasp_ahclkr,1 ]+ h- V5 v9 }
output mcasp_aclkr,
" O# t- k; o$ @, h& ioutput axr1,
6 U0 Y' B3 T$ n; a assign mcasp_afsr = mcasp_afsx;% v8 a7 S& s7 x8 p l
assign mcasp_aclkr = mcasp_aclkx;
7 y$ p! {" P8 l) |! q: X& ?assign mcasp_ahclkr = mcasp_ahclkx;
) O; {0 E( h& D8 T' m: p1 yassign axr1 = axr0; / f7 |1 X# f( q! \( u4 m
6 Q' Z9 J1 A: U0 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* o; S3 { H8 s3 Q `0 F+ i$ @static void McASPI2SConfigure(void)& J, b) W* O& H. P! ~/ f
{* M- r( b: Z+ J$ c4 B D$ m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, C" b. M) L6 y# E! c' C: r; u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% S5 A7 v* y+ R) z9 r- u' ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 O F5 w; u( ^' @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 h: o# L/ U# t+ K: TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, j; p: |3 K8 K
MCASP_RX_MODE_DMA);
g0 c) F7 f; d# Q0 z5 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' e: p0 G$ N* ~( T+ R+ s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 F4 k( P6 s! X& G% w& R) ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 k0 o$ C: i* ]8 ^4 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 Q6 Y2 }0 F% P/ @! ~; fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 O) P1 k: D4 _9 T& }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 o+ e0 h: l9 D5 V: l+ IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, N {" B7 m0 y" }8 ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& N- q. a. M4 D& C0 j9 X/ I4 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& r, t7 o, T+ \! v' S1 V9 n5 s) ^# {0x00, 0xFF); /* configure the clock for transmitter */
$ G! j9 `: c( R, m7 x( uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. O) C) p: u: ]# n) r% m" @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* O" n$ a( K5 B0 A* r3 LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 C0 t9 B/ A% ^1 i0 U
0x00, 0xFF);5 P$ Q" @& T& Z
: C9 D0 m$ y, e8 K5 @1 h/* Enable synchronization of RX and TX sections */ % t" j+ @ D, h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ C7 o& V# `. |+ e" I$ BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! b1 g7 [+ q( O- i2 B fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: ]# o q1 _# {$ s& m3 P- P+ y" B** Set the serializers, Currently only one serializer is set as
$ I& G4 U. E J9 |% b: U** transmitter and one serializer as receiver.3 [# _4 y% [. G: J1 S* M* L9 Y
*/' c( S% S! V& C; r0 _. Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 o5 T$ D+ d4 j6 E! _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 ^5 c- B# V8 c5 N9 |( C3 r7 F** Configure the McASP pins
W) v) z) }/ V% t: G. ]: x! T** Input - Frame Sync, Clock and Serializer Rx
* i- D. q' w" T) p9 f7 t) `** Output - Serializer Tx is connected to the input of the codec
# y- m( C! N( G1 ]/ w*/ |2 |3 m1 U7 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. J! c' d9 r+ u+ o8 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 Y1 p8 b) |% C) K: }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ Q2 \+ z: Y2 p
| MCASP_PIN_ACLKX
$ H7 x6 N3 n& D9 u/ w6 J1 c( v| MCASP_PIN_AHCLKX
# h* j G7 {0 d2 _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 a/ |- f6 O3 _: Z$ Z. L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & Y5 S+ M, u: ?
| MCASP_TX_CLKFAIL
2 e1 Q. c5 v$ y: H, F4 B4 c| MCASP_TX_SYNCERROR
/ P+ _9 a6 I& S5 C4 x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR Y) ?9 f9 q: v( P& E" G. ^. x
| MCASP_RX_CLKFAIL. d, _8 { m; I5 D
| MCASP_RX_SYNCERROR
& V! F0 t5 M$ m7 @' l0 B) h| MCASP_RX_OVERRUN); {1 T2 J# i9 ` ^# }
} static void I2SDataTxRxActivate(void)
+ w; S0 h3 ^ L! `- G& ], N{ U4 s2 p6 ]# D% U5 G" O
/* Start the clocks */% W3 m4 D* b- w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 `8 L0 r4 u: ?, p9 i0 s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 \9 `$ |, h) K# y; |! K, m QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( o& O, ]: j, a0 E$ G" F$ h2 G$ tEDMA3_TRIG_MODE_EVENT);
6 Q* b, q! X- }0 u) `, v" ^; n. CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. ?5 n/ Y. R# c e, d2 O4 y3 G k; oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, D! l. M1 f, A( U. P7 \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( y, T `" G( F) S# }! i3 {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* [- G$ B D% j. I9 x) v/ G8 ^7 cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! f$ j e" L/ d/ q5 oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% g2 ~! q+ s; s0 |, o- \, R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( v6 P8 i- r$ s1 Z7 [/ y g9 Z5 G}
3 B* H# p7 H7 E V* i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / {# k3 v5 O$ l/ |: q G
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