MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
# q$ H. L, |8 C7 L: v. {; iinput mcasp_ahclkx,
input mcasp_aclkx,
% h0 O3 z+ x9 Binput axr0,
# [3 R; c# b8 O* J
output mcasp_afsr,
# n! \, v  p$ A' h) j" Poutput mcasp_ahclkr,
output mcasp_aclkr,
3 T5 m! i7 p" I, y2 doutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
5 h6 E4 h0 f. N2 ]" y  Gassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

# M( X$ g' T) p$ }5 v; t* {* g

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

" {- b* y9 T+ a$ t8 v0 ~; k3 L7 E

static void McASPI2SConfigure(void)
" {6 |9 X- }: S" w* [{
. E7 z3 X+ w2 @1 K' J1 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% z4 Y0 H( _( p& v) ]McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' P  L( a9 b: _4 F* FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
5 ]5 n3 p- ?2 x% ^1 O5 ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 O; c. ], S* t* @5 {MCASP_RX_MODE_DMA);
5 p9 F0 ~5 _# g5 wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: _3 |: g& S- \# b8 f7 |+ v; K5 c0 `" pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( {. [. z/ J& J' XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
$ Q( n1 E" ~4 A, Q( l4 ~2 aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& c2 X; s4 P/ \$ o% h7 Y: d0x00, 0xFF);

/* configure the clock for transmitter */
9 Q0 y/ ^  [. i1 c+ A- BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* q6 P7 N8 n* a4 W0 zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

* j- K4 ]8 o3 h2 V" S* M& ?/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
" u  Z& v- R$ z2 R, n2 B# QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% W5 G) V" ~5 r3 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
+ J" e5 H8 C/ s) [) D6 h** transmitter and one serializer as receiver.
7 w" O7 N6 ^7 G8 r6 ?*/
$ ?9 [. c& ~. Z9 f7 w) Z: iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. F3 x. G* L5 a- Q( MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
1 j3 U* \' t* Z* I0 a( _** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
) w/ D4 x5 E0 f$ @* t* k*/
+ w5 O% q  A& A- ~2 C3 ]9 x$ N# o3 DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 U1 v4 A: w2 l: w0 ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 W2 N0 X. z0 o: G+ C  d# DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) [0 _$ T. k2 m0 A8 o| MCASP_PIN_ACLKX
5 e2 r* h7 N! o5 Y| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
# }# P4 O, m. z6 T# E* O! O% sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* P+ i+ [" {# W7 \6 F+ i9 ~9 A| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
+ x; g. }! D! {) d2 O& Z* C| MCASP_RX_SYNCERROR
0 }* w' m& t$ w' a$ i| MCASP_RX_OVERRUN);
! k0 _1 X: K: k8 E" U}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
$ y2 Q& o9 N/ E8 J1 A2 e* u: u2 TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ }" R: ]( V9 K( y% ~) p+ ^: TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
& J4 v/ h- j4 m  X- HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
4 m0 q. F( ^0 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
3 t; j% @0 L5 zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
& l) ^6 }1 c9 Y# q( m  aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ T; Y% h; U7 N3 V* iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.