|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' [. p5 r5 }# T8 H) p- u
input mcasp_ahclkx,. U& G3 |1 w# U( K
input mcasp_aclkx,
* O# I1 v+ I- u5 yinput axr0,
# r8 |% z" ~6 p* s; v: L
/ N% O$ U! d9 M- I1 N# j! ~6 _/ A& woutput mcasp_afsr,
5 {9 Z) o/ X3 t5 }! P2 ]* X% a! Zoutput mcasp_ahclkr,6 M9 ? N2 H. A! B" B2 d$ T
output mcasp_aclkr,2 ?, N0 z( a7 e; p' s+ C) y
output axr1,
4 E& B4 q* [8 q! H2 E" G assign mcasp_afsr = mcasp_afsx;
( H8 \9 q1 j! K O/ @assign mcasp_aclkr = mcasp_aclkx;& _& h4 V& f, T
assign mcasp_ahclkr = mcasp_ahclkx;
$ W+ ^6 c) ^5 {1 `9 `0 G$ p; Dassign axr1 = axr0; ( v+ L4 }% T) E
& r6 O9 N3 m+ q3 F" o) |, M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; @& k0 q, m! S* ?: }
static void McASPI2SConfigure(void)
# K% C# u# r* i1 G# a6 }0 b{
8 n- a, _) U eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! G- M7 u. `5 p* r O/ ]% d0 r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: [! \0 o5 |" ^$ g/ SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 M6 i$ q5 d O5 s- T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" H, m# M' E9 BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! U, J' d! f A- c6 u( g8 W
MCASP_RX_MODE_DMA);
! Z+ \+ s- X( e4 yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 S5 V/ _9 {1 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, C% _ O+ R; q4 k/ ?3 ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 o L* ?1 g. B" |+ }: H4 @) y- G! ^+ q( LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 j0 G; e4 Z7 y# r7 D' W% r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ P; `6 r4 W$ s3 BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# S2 }6 M' i! f& w$ x6 A5 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ `# `! q* i' p! Y2 Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % ` {, T9 A4 O' u, k2 E1 b d" ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& V* E+ o2 q; q Y' I
0x00, 0xFF); /* configure the clock for transmitter */) C1 G( @: C1 L0 `4 {8 }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 W/ f' J! @+ I3 Y/ QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 L8 ]' s6 B& ~- n2 P0 y9 p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 t# o$ T4 U' ^! L0x00, 0xFF);) i. h/ [+ z7 l6 e3 m
# `: r% t! e* R0 D- A8 d$ i8 k9 z0 g
/* Enable synchronization of RX and TX sections */
5 I$ z1 {3 w z, E& w7 bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' \0 R# I8 T* e. z7 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! q# z+ m3 y" M* v. NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, w' p' R% s; F% r C) A( q** Set the serializers, Currently only one serializer is set as
- t$ I8 G! B( R z& Y. E3 o** transmitter and one serializer as receiver.
]; Q6 ?1 R) \. g0 O) L5 W*/- Y) Q+ B4 A3 }9 S: p. o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& R& c1 g) u: ^1 k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! h& ^' e |+ O: s+ d
** Configure the McASP pins : m A7 I9 @, R6 p3 ]$ b
** Input - Frame Sync, Clock and Serializer Rx
/ y+ N4 U4 B' x+ v/ r** Output - Serializer Tx is connected to the input of the codec
- F) [% L) r0 |- [*/
$ _0 t9 _+ y6 I' x5 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 y, v U {& d; h7 E" f4 {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 z* C! Q. q; A3 u1 s2 S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) t6 a8 a6 v3 K7 n2 @" Q# K: y
| MCASP_PIN_ACLKX' X" Y% O- p' p: w( D3 N! g" e7 B
| MCASP_PIN_AHCLKX$ K' P6 {1 m' o& q/ ^0 R6 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 B' O# V8 f0 o- YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 y0 @! C- ?( Y+ H# f9 H, y# _| MCASP_TX_CLKFAIL / z: J# y# y- E+ p1 R7 m
| MCASP_TX_SYNCERROR
9 c3 u; Z" g$ W- D+ f" x b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR I0 ~2 E; v+ h9 j- n6 e
| MCASP_RX_CLKFAIL0 }: D8 {0 [$ {
| MCASP_RX_SYNCERROR
- W9 T7 [8 z( a| MCASP_RX_OVERRUN);
; W: i& M; Y- i, o} static void I2SDataTxRxActivate(void)
7 D% F+ p. T- a2 e4 x* X/ i) r* o- M: s{& R3 Y: Z& X( s: }3 U0 w3 N; P
/* Start the clocks */
7 A+ N2 ? A$ T* d) g- G5 qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' x# Z. m7 T4 j& Z2 p' W/ Z ~( dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! [2 i! H# h& X; x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," s1 \; c+ h3 O( _6 }3 a. p7 d
EDMA3_TRIG_MODE_EVENT);
0 h" y$ Z$ W& L; s$ }) YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 G9 N6 P' E k% r8 C" U' [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 I5 m ? @* r! }4 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. @( M R0 D7 X( S' ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. U* Z- A, z* u3 Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; f- K& f, {) E; H& Z! GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ D$ ^+ x- s' x- x, }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% S- W7 a b% F# E} # c0 q8 V" O' c+ ^5 u# E7 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . o1 y4 N& Z0 }. I
|