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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: T. m9 \$ H6 Y) S. O6 F6 t* _1 A4 T; _
input mcasp_ahclkx,
0 R; @) ^+ E) c6 Zinput mcasp_aclkx,+ i: J! D9 }2 v6 F5 t5 T
input axr0,, [) X+ F0 D3 w5 ^+ l
: o$ g( s+ s' T2 |2 ^/ Boutput mcasp_afsr,
! B% E/ u! k! ?$ d) F/ Ooutput mcasp_ahclkr,
& i4 A# |. ~; j. @output mcasp_aclkr,' B* R! J2 |( K m/ l# w- R+ j
output axr1,
3 b X' C9 M4 p/ S# e& q: L assign mcasp_afsr = mcasp_afsx;
' Y& F' s3 a! J0 O) L5 _& O. sassign mcasp_aclkr = mcasp_aclkx; Q0 t( J' ]& n3 }: ?
assign mcasp_ahclkr = mcasp_ahclkx;
/ B; L# l- w9 P2 }- F# i2 A: Bassign axr1 = axr0;
: S7 G, d5 X; K+ e
; F- J2 w8 H! H$ G' n- e5 G' N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 H' G% o, H/ f5 m3 ustatic void McASPI2SConfigure(void)
5 M+ j9 G8 `2 `3 f' F{5 f+ u3 I( G+ @) d3 V) H- j
McASPRxReset(SOC_MCASP_0_CTRL_REGS); k& ]) F9 W$ P) C2 x7 X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ p7 K& X2 f; u. G0 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 m5 \3 F) N' [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 \7 ^5 k5 D1 d$ j {/ Y' }: b$ `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( b: T+ B) N( G% p! qMCASP_RX_MODE_DMA);
1 l( Q0 C; P' {$ X# |8 L; O! xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" ?% s4 M9 x/ J/ @1 fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 m) S- b& j4 o8 m) F2 S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. E6 r4 f9 z2 j' V* X' KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. Z2 H$ R! y. f* o- p" K/ DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 {' `1 s) y' n7 x. f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ Y- Y: @, a3 i+ k) [3 ]5 z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( U0 F) P K, A# fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" Z- p0 j) x' u2 I$ P+ B, Y" bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% v3 y G( f# C" L6 ?
0x00, 0xFF); /* configure the clock for transmitter */6 x' U: R2 c- I; ?4 f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' Z' x5 s6 b% d" ^& j! j! gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 k# l3 M2 N5 c9 E7 e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 O* u I% t$ i, I0x00, 0xFF);
E8 f6 Q- Y0 b3 {3 u0 f, k- a9 D( T# Y& Z) w) [5 q, ?$ J+ u- I
/* Enable synchronization of RX and TX sections */
& W" J+ L3 \ K& e3 M8 u* AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ ^: [& L: ~7 i! p8 q2 F; h0 KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* z' Q& K* x r- x* {8 O0 W" A' n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; c4 X* s. i1 v4 l** Set the serializers, Currently only one serializer is set as. b A9 y$ x2 c+ ~% R( G
** transmitter and one serializer as receiver.
R+ ]' E3 x2 J5 ~& C3 N2 k b*/ `3 z: j% P9 h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 L/ E) w" b1 F( H/ |& U$ NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( V4 ]: i( J' Z2 P: b& F: T7 H3 ` Q$ p** Configure the McASP pins 4 ?$ y: ~0 O; A6 B
** Input - Frame Sync, Clock and Serializer Rx
! {5 Q& B+ Q, z p** Output - Serializer Tx is connected to the input of the codec
- m( m7 X, d9 |/ Q: T# }*/* ^& G# ~! g/ c0 B1 N1 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 c! L3 j! j8 NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; P5 l6 q) Z* Z6 E! ~! n( v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) Y. _9 z; R' U* q( z) r. w, s. f/ K| MCASP_PIN_ACLKX9 ~8 ~$ R3 a, Y5 A
| MCASP_PIN_AHCLKX5 A+ z, [) n7 P1 Y4 b( S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% ?% O' u" r0 Q$ i6 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' G, _3 k% a" |- w9 t( P5 u, T
| MCASP_TX_CLKFAIL
) O& D* A) z" N1 [1 }9 q5 h7 {0 u0 @| MCASP_TX_SYNCERROR
) Y9 B3 B" W1 X# f: r! e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: |: L: M1 y# ^- s# q| MCASP_RX_CLKFAIL
; V: J/ t( _- V6 l6 _1 V& K| MCASP_RX_SYNCERROR
5 q. P6 ]; }" r) [| MCASP_RX_OVERRUN);
, J7 o1 X1 e+ m5 y# G} static void I2SDataTxRxActivate(void)4 }8 y) e( f/ y1 s2 Y- H) _
{& e5 D) n# p) c7 Q
/* Start the clocks */
7 z/ S" V: A5 o0 u: N/ oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# Z+ u2 }# s. }, rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 `3 }0 S. z, C+ {+ ?* `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 [' g$ [. b( Y3 e" y2 ]
EDMA3_TRIG_MODE_EVENT);
+ }( M: N3 d' w# `: P) sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / f5 M* B5 K0 ] u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. Y$ S# ]5 J) f$ o' K1 [0 BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& N7 E# b* U2 Z7 HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 ]! f S: }) O+ y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 P& r: T% t3 P; ~- j. OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 ? B0 i# K9 `, `, I8 { vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 ^& y; u. z$ J, Q6 d( p$ {
} , J* h( y6 C) e0 J0 L3 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * T3 G8 n- v: A3 W
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