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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 q& L E" \- U9 Oinput mcasp_ahclkx,/ c/ l1 u; H9 A; X
input mcasp_aclkx,
( [/ e' |* |3 C0 g( cinput axr0,/ t9 D4 H+ [# U5 l$ N! Q
% \/ G0 V- L+ d F W! e
output mcasp_afsr,9 X+ Y/ k- s7 k: W6 y# B
output mcasp_ahclkr," k/ G- R7 R' T8 E4 @
output mcasp_aclkr,$ k2 U3 ^5 u6 V
output axr1,
7 ?! Y6 s) M, I9 p, V: x assign mcasp_afsr = mcasp_afsx;3 f, C4 Z6 ]% n; W5 g0 _4 z0 r
assign mcasp_aclkr = mcasp_aclkx;
A. [$ ]/ L0 R) {: oassign mcasp_ahclkr = mcasp_ahclkx;- q$ d- n2 l& ?0 }
assign axr1 = axr0;
+ m' Q @0 S2 q- \ _: w8 P0 v
- S! ~5 w$ {1 Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' S8 a" o n+ G8 u! Ystatic void McASPI2SConfigure(void)
/ A& `* D s: m% c* {{" T0 \/ ~( J& ~# @4 k; }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ P! q1 \3 x# x4 L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ r B. G. H6 ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) H( J6 ^/ e- U0 u1 ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& h, ?% X9 a1 U/ p0 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 n9 N+ s2 {' e/ K m
MCASP_RX_MODE_DMA);. Z3 n5 \4 S, j$ y3 S* Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( Y8 c6 O6 J" ~5 [6 K8 PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& v$ L* v, D, t+ VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 R) Z O& x0 M7 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 @# W5 `. Y9 O. V& B( q: N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 x5 d& u" U x5 {) E! c/ D8 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; L4 b( I" n0 M2 X3 H1 w) M. h A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: V3 T8 V% ?& j# i3 d9 \* RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 w& H" d4 R* G% A- r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: ?( I. p' R0 a4 M) z6 k$ C' S0x00, 0xFF); /* configure the clock for transmitter */
" Q$ {5 L | z. j, D- r% qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* n, _7 U, X6 c# K( `# A. X/ h% d3 ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , c. D. [8 w: V! P" ]; H+ {4 y9 B, J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) n2 n2 J0 }2 P1 d9 [& m) o+ X0x00, 0xFF);) H, Z& K# X. L; l( G# H4 x
x/ j: T4 m- o- H& p+ \! k$ u/* Enable synchronization of RX and TX sections */ - u7 V& ^, [, I" M* _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- [* ^; F$ b- J* Y% i) [$ ]& aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 X& f1 y3 V( g% R9 h0 JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! x4 s5 M4 \2 }8 E8 t** Set the serializers, Currently only one serializer is set as" q0 w) s8 p- ~ s( k0 `
** transmitter and one serializer as receiver.
& Y* E9 z' V% d/ O2 M*/
P% X/ |3 m# q! u6 b X# C* TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' F' F6 r! D) K& ?0 a0 @8 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( k$ J1 C& e1 G& U9 V9 }
** Configure the McASP pins 4 X4 `' B8 i! m# f9 w' m3 V
** Input - Frame Sync, Clock and Serializer Rx: ^3 c& q/ \1 v4 |
** Output - Serializer Tx is connected to the input of the codec , o, `; N9 W# v, @) o; K! f; n" I( v
*/
5 C2 d9 P! E; V+ W: X1 ^, GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! e% Q- Z, w: M! C8 k$ V, a+ c$ S; WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; u( z) J1 X Y9 z' n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- P7 J8 A" z- r2 O- h4 v| MCASP_PIN_ACLKX% _- i1 {! Q4 U, Y5 s) P
| MCASP_PIN_AHCLKX6 s# d7 Z. W9 E( O, R6 z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# l+ i1 {1 @% [! h, Q8 c- W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 p$ s/ T" M5 r7 v$ d| MCASP_TX_CLKFAIL
T( \$ p; [$ t7 e| MCASP_TX_SYNCERROR
% _) B" P( k F( R. {( T% @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 z6 x3 T2 o: W3 S| MCASP_RX_CLKFAIL# |* H1 U) ?( C! K
| MCASP_RX_SYNCERROR ' h r" a$ l( V8 q+ I, V" Z
| MCASP_RX_OVERRUN);4 w' m4 _+ ] p6 E, T
} static void I2SDataTxRxActivate(void); `$ H# l$ S% j# `8 C! m: v
{
# K4 m- H3 n: `5 l6 L6 x- U8 b0 F/* Start the clocks */
7 W5 w% F# E- pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" _8 Q; a/ L6 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// `1 e3 G$ A1 c+ M7 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," M' Q' Z* F7 ?0 W# [) d7 F
EDMA3_TRIG_MODE_EVENT);/ Q7 Q" p5 q9 N: s, E$ b( l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 S: @" @; ` m7 d6 c# @- _& a9 D- G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" _7 M. T. }8 X5 nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* \7 R( e; k; C0 R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% `; o4 l _9 {0 q% P l7 C/ w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 O8 _: `( l3 y2 r/ P: \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 A3 K) ^9 L( YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 E2 {& ~. q% V6 X) c# q$ w* B; n}
: C9 C" c9 H5 N% W4 r3 n. H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 O7 Z: z# b: @8 @$ l% S& Z
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