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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# }% Y" @3 h1 _7 }8 Y3 ]# t! h. I
input mcasp_ahclkx,
; J" D7 T- O, Hinput mcasp_aclkx,4 I$ b% V3 C2 q2 I1 T6 u4 k
input axr0,
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6 f% |0 c s& {$ ?3 `8 Uoutput mcasp_afsr,0 i: u& ~! C: v
output mcasp_ahclkr,
6 P9 m3 R6 H; o0 k; \4 D2 Aoutput mcasp_aclkr,
% O+ a1 {9 t! F8 O7 koutput axr1,
4 ^' l! m; E! g8 k assign mcasp_afsr = mcasp_afsx;: F. q; U; r# G7 H9 N; q% y
assign mcasp_aclkr = mcasp_aclkx;
. w* Q. ]/ o8 U' ?assign mcasp_ahclkr = mcasp_ahclkx;' r8 V: B2 ^: u, B8 b
assign axr1 = axr0; + _* A1 U( c, B
( j2 e6 T& q) y# w# F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% z/ d+ G- T8 u) m! a' _static void McASPI2SConfigure(void)7 ^; ]+ _, @1 ]! O4 D8 E
{( T" Q9 Z/ ]$ |* |1 ^, k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ M+ C, V' `1 g0 b7 g5 r- o7 c4 U' @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 M- _. p* O" q9 B3 U! u6 y1 E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 w8 U: B9 M3 }. T$ N( jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" o1 p+ F# c4 @5 X! @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 |% h& j+ C1 d1 e @MCASP_RX_MODE_DMA);
6 }1 n0 E4 U: V+ IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' S, p" o' G: v6 _0 O2 tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 G; x) x$ A4 l6 `4 E7 FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. G$ k$ F. ~' F3 l) U$ p- D3 y4 a2 IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 @* z5 j# J: i% aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ H* J6 y9 Q6 i+ w; {9 y4 `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 S; c* @, |7 d4 X7 m1 u/ q OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 q0 X3 L" ]. ^0 [0 }' oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* `' o& Y, K) I$ k! x* Z4 X7 cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 @6 C( z( J ~- r) ]
0x00, 0xFF); /* configure the clock for transmitter */& ?% Y2 Z# d2 O5 ] }6 x% o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ W9 m: p) F6 Q( S+ m6 K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - N8 ~5 z) S" }6 _5 ^5 p. q% I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) ?+ q8 x# t+ X* R, J2 e4 X4 g$ x7 e' W
0x00, 0xFF);9 N* _& M: V( O" v3 H
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/* Enable synchronization of RX and TX sections */
, K% a1 p& N, V- [3 o/ UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ q( f k$ W1 `+ `# c, i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 h+ G; k2 n3 H+ E$ D4 r+ l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: q, X* ]4 S' S
** Set the serializers, Currently only one serializer is set as
, V [! M- Y Z) ^** transmitter and one serializer as receiver.
% G `* I' B+ w8 c! P, |*/0 S( _, `/ w& d6 s5 A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ n9 \& i' T0 F) `/ S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. W4 J& @, T1 k8 B** Configure the McASP pins
$ T# W* W P0 E3 y** Input - Frame Sync, Clock and Serializer Rx% e. P K* E- Q( }
** Output - Serializer Tx is connected to the input of the codec
1 t3 I# Q( R" T*/7 t5 ?( u5 R0 y, J+ t4 R7 q5 w+ u8 ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; p& U" J, q' P% X0 x- [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 x" R6 C2 T. [9 l7 ?, K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 p7 L# k" H! i- W| MCASP_PIN_ACLKX4 ], n$ Q* L: i) S; s, L' k/ I
| MCASP_PIN_AHCLKX2 f. s; ^$ O6 W# z/ O) v. B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. b( X0 f; A- j3 @% ^7 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 k. m4 P! u9 E8 n! L: F" t2 e| MCASP_TX_CLKFAIL
. Q5 \' @9 X) x0 i8 F u| MCASP_TX_SYNCERROR
0 V: T7 {$ o2 T/ y" I6 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 h) w& J6 m4 _( j& M+ G+ h5 i& C
| MCASP_RX_CLKFAIL
7 k8 {% f8 P' f5 n0 i| MCASP_RX_SYNCERROR $ c: \ V% b4 P2 X
| MCASP_RX_OVERRUN);9 J! Q# H% l% }7 V
} static void I2SDataTxRxActivate(void)
8 a3 V& D+ ?! ~" ^{: ^* k% N; Z5 R% x% `
/* Start the clocks */
+ ]0 _. A6 e5 T; s$ p/ Y1 ?) B8 dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 q6 t8 ^/ k9 Y: V* H7 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// a0 p% ?8 i C, f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& y% [+ k& r' ~- h1 k6 ZEDMA3_TRIG_MODE_EVENT);
: w) \6 r- w% M6 L5 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 l$ c3 R2 J" [; V& q% hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 q. a; z) }- m# [! c0 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! Y. T# E5 _. T# IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: a2 W9 o. ?8 u6 v! R6 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; Y% W+ U; N% OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ \/ m4 E1 c. |5 KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ @9 ~8 r$ S+ \( G$ C! [} ' N/ T8 H. _( i2 G& Z3 N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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