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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 e' `/ |* z+ rinput mcasp_ahclkx,2 N% {. O9 {/ L, C' ~
input mcasp_aclkx,* y* A8 ?0 X- k' {/ [
input axr0,% n5 D$ p1 S. B
* R% y0 x$ N& x7 U q' qoutput mcasp_afsr,. ~' C8 T; H; r5 }8 r& o$ x7 h
output mcasp_ahclkr,
# J& a. k' n% x( b8 T2 _3 f) y Aoutput mcasp_aclkr,
, z* O5 [) D# r# f1 m poutput axr1,
: r8 Y x3 k# F) Y( z5 _& V5 Z5 G assign mcasp_afsr = mcasp_afsx;
# ^6 r( B6 B# \) Vassign mcasp_aclkr = mcasp_aclkx;$ E- U3 n' a& ]) ^: m7 D; m
assign mcasp_ahclkr = mcasp_ahclkx;% f$ M3 ^# E# W6 b
assign axr1 = axr0; 4 H+ J' D+ c& L8 T" H: J! ~& g0 U" y
5 i. m) Z1 e8 r9 ^7 f5 |0 N5 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
W7 g# n& w. z9 X8 @+ g: Nstatic void McASPI2SConfigure(void)
# o( @. i) H9 D: c1 c) F( w: E! G{
, T$ F9 ~3 c- M: @6 C3 qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ C3 q7 k( F6 c" s. tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( D) n" m+ l+ b6 m0 v* n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 s7 R/ ]3 _. W1 t' v0 e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
|" X5 w$ m* z9 x, O, lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 ?1 o; i8 \5 X0 }- l2 eMCASP_RX_MODE_DMA);
& q5 _/ k2 t/ j' K4 Y X2 AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! F6 @6 ]7 h* {9 v3 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 o) w) I4 `" G- g9 J! o6 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ i$ G; |) b. g' p9 a; PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; U- c, n, y0 _& f1 _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! m" |% l, `( @# I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 q2 z5 E, r9 I( u2 V- N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# r: b/ x' A' s! t1 r; o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 Q; ^# x; f) h+ q! Q% bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. W. `7 p! D* `7 S i0 ^
0x00, 0xFF); /* configure the clock for transmitter */' ]1 \9 }) G( f! n/ f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" Z# R" A, ^3 U; ^' R, UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 C( G/ T0 z5 l5 o7 y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 u! X0 X! m0 K% d( H9 |
0x00, 0xFF);& s: @! j, w$ @; U
& |" O; b+ F9 n* ^8 K7 v- [/* Enable synchronization of RX and TX sections */
0 W4 d# p# m/ N" G" M8 s4 S" fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ Y4 z! S- K8 S7 V) zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 ~2 L5 G+ `* V* w: N+ r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# |8 E) Q% g* C% y$ U8 J: `5 R
** Set the serializers, Currently only one serializer is set as6 o: e" k/ u0 ^5 |/ P
** transmitter and one serializer as receiver./ z8 i( b) e6 ~3 k3 L( y% F
*/! e* ~" u H* E3 x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 e2 a: Q' w, A" k6 bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( ~% F9 C& m+ U! z+ P) F2 ~
** Configure the McASP pins
% f2 W6 m) q. p% @ u1 i** Input - Frame Sync, Clock and Serializer Rx
3 m3 ^# r, g! R7 [- N, [; A5 n3 E. j** Output - Serializer Tx is connected to the input of the codec
' ]0 a* t6 s9 O$ {; ~*/
) m+ e$ {- x/ O* e8 R* Q0 ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 ~" I3 P; A$ ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 ?4 X! ~& h+ A5 x1 P- h' u3 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ I. v& z# ^4 y, w+ T- _/ t| MCASP_PIN_ACLKX$ o# o# t" M& r9 {. e8 v
| MCASP_PIN_AHCLKX
3 Z9 B7 w, T) O! {2 a9 G" C! \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 L K; l" W/ \ }5 ~- J) G6 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 B8 `2 `" f3 b| MCASP_TX_CLKFAIL
8 Z9 O/ X6 c6 o! _+ n0 s| MCASP_TX_SYNCERROR. f# [0 ^3 k1 u- E" u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 @) G# ^$ P6 N+ { n) K
| MCASP_RX_CLKFAIL
& W& f; X# `/ u, g$ K) m| MCASP_RX_SYNCERROR . L' B) a: T1 N) t, i2 {
| MCASP_RX_OVERRUN);
; r8 R! ?) N/ j} static void I2SDataTxRxActivate(void)0 o4 C: j2 ?2 c( b5 {/ N9 q6 U
{
& w: j$ W& C. E1 S' w! W/* Start the clocks */
0 t- c3 f- g2 L5 c5 @5 {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& n: J1 q$ N7 r3 c/ S2 r+ @" j- vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// H3 b, Q9 h# ?# D& O" |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ l @. W, P/ n
EDMA3_TRIG_MODE_EVENT);* [' j) |+ ^8 k' T! N p9 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 G$ {# N+ R7 K3 Y/ H* sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 w+ Q8 H/ @2 r5 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( v; W I! V; v# h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& h0 c% k+ N d7 G5 U- Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 Y; a7 i* I, w/ A9 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! g* x( S% @/ q `7 i" s3 @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); i a4 O% v) o5 R
}
/ ~) O* W# e `. F9 z2 u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
% ?0 X( n, _* n |