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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ y$ q4 P, ?& @' i9 f0 ^input mcasp_ahclkx,
) q1 q6 \2 v$ Q, Y( e- Uinput mcasp_aclkx,
* y/ [5 @0 e Q9 @, sinput axr0,4 W4 X. k0 t, \+ K
& t8 C! T: p E$ k2 w7 a
output mcasp_afsr,
& i$ @1 i4 I" ^0 q1 ]output mcasp_ahclkr,
3 R6 J. F( d* ~( C7 i! k2 Aoutput mcasp_aclkr,# Y% W5 T ~7 O C [' O3 l+ ?- m2 n
output axr1,9 q" T( }, r, {- ?6 m
assign mcasp_afsr = mcasp_afsx;( p6 \. `% D( X' U
assign mcasp_aclkr = mcasp_aclkx;
$ Z- o& _6 l! }/ H) Yassign mcasp_ahclkr = mcasp_ahclkx;: S/ t7 z% c4 F' `8 M* a6 b
assign axr1 = axr0; 0 o& R; ~9 S$ M% r: r( J
: s1 V6 Y! `6 {( o! n: ]" |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 c! H4 M2 [5 f) B0 l
static void McASPI2SConfigure(void)- h9 H, ~% x. z! C
{ L% T( M5 Q9 r' _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. i- O* O/ n1 ?4 }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 c2 X [5 r/ _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; K, K4 ^5 b1 M' o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 _ Y- R8 N% H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ {+ c& t& }9 F$ @MCASP_RX_MODE_DMA);# ?: ~8 ?+ ^5 K k7 x* s) M. L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* S& n) g6 Q8 C% IMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 l2 J, }3 g+ r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , v ~& j' Y$ w+ m' H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 h4 @/ }) k" g1 C2 N& g8 g- g, ~& LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 C1 j, a* \0 F% e4 U, KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ p5 ^# A5 g1 q, J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 c0 T( {8 X4 J, C2 D7 n' ^" nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , z" m/ v9 k. p/ X- F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: x% i% i/ t J6 w/ g- q
0x00, 0xFF); /* configure the clock for transmitter */+ d8 p" A8 i" V* r# R5 p6 T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 S* Q- w$ j! `" t: u' J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 I* x6 H2 r$ G) D3 D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# k: {" S* _& v: B. e
0x00, 0xFF);* ` D) z; a8 g' }
0 b* N5 V; [* c/ y- ?& G, E9 W/* Enable synchronization of RX and TX sections */ 7 p1 {$ X# Y8 L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 ]% {" _0 v4 J# J9 |) R! ?% L9 i/ IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: M5 n6 B: D# D! ]! P6 w u4 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 q) [$ T4 w- y x2 t** Set the serializers, Currently only one serializer is set as- j. l, G k/ o& _5 e2 B3 f
** transmitter and one serializer as receiver.8 E3 T: z; q' v6 \% Y9 M# v
*/
$ X9 [ I7 N/ I2 |; K2 n* hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* j3 S% Y7 t1 u% N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! x$ V$ a. Y9 F( u- Z** Configure the McASP pins & z5 u) C& A: F5 Z6 z
** Input - Frame Sync, Clock and Serializer Rx
7 J2 ~' ~" J7 h* p- F** Output - Serializer Tx is connected to the input of the codec
4 [; J. |2 N& l. [4 V: N# \: d*/# p* w" G1 D- j: }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# P6 w( g2 V9 G2 T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 k; R6 J" c; W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: q1 z/ y) s, X j! t) A# h/ m4 R
| MCASP_PIN_ACLKX' w! K; ?1 n, j9 @2 H- _2 q
| MCASP_PIN_AHCLKX, w8 Q- o+ J! n e& q6 ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% a; T8 B8 p8 @8 c6 J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! U1 u; _4 [7 A% q( {# S/ _4 f, @
| MCASP_TX_CLKFAIL / ^ k" N [! |1 s
| MCASP_TX_SYNCERROR
- ^/ m7 G1 o" W2 }# e+ J$ [3 q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + _! g1 F$ w" ~2 u" v* y
| MCASP_RX_CLKFAIL( y9 l/ Z9 ?1 ~. \
| MCASP_RX_SYNCERROR 0 O" X7 X' T m# @' x* L6 \
| MCASP_RX_OVERRUN);+ b4 C& k# C) b$ i3 u" G% X
} static void I2SDataTxRxActivate(void)
& O$ j' \1 ? ^+ q{
- P3 e, X' K9 |/* Start the clocks */9 I" M; t& n5 @9 z: L' r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); _# ? @) o+ L& j" f' l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* N8 A% k4 @: h9 Y g4 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
{3 `; r! z6 kEDMA3_TRIG_MODE_EVENT);" m5 I7 o9 s8 D8 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; c+ f0 U+ N. Q) A' m6 r7 \9 @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: y/ p! c6 b9 W$ l1 A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ |# E9 w8 G- m. t& b/ D eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ o/ [/ f+ s/ Y7 y0 r5 s. |% F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' G& x5 W" E; P) R3 E$ ?8 K& T$ _7 g4 FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 u- |8 Y/ r/ [) v; EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- L3 z6 Q# e) _" \. h} " G" a3 c/ \" Z7 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / [1 X, u7 W1 q Q
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