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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' Q8 ^" C& U1 X: j8 B" Y
input mcasp_ahclkx,
9 h" ^1 n' C# l/ _& V. n; J. Dinput mcasp_aclkx,
) F7 Q8 Y/ s" m8 }5 ^" H' c8 Cinput axr0,
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output mcasp_afsr," M" u: m- R7 q: F
output mcasp_ahclkr,/ s( p+ [8 R# V2 ^3 x
output mcasp_aclkr,3 m" _8 B `% f3 A. o0 [
output axr1,' I- m/ j1 r3 a1 o6 _
assign mcasp_afsr = mcasp_afsx;
' A# d, L) S3 ~4 o) z& i3 Aassign mcasp_aclkr = mcasp_aclkx;1 p( }$ E, e4 {: E2 n4 J
assign mcasp_ahclkr = mcasp_ahclkx;
9 F) r5 {8 |' E- R- D) p2 Bassign axr1 = axr0; 5 C) w. b. \; @6 c. ?7 x
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 N$ ]- Z @4 L$ V) ~ \2 T" ]static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);& n% V; R. D( K N' |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! B- U2 T4 t( Z& v6 ^9 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! f# w3 e! |, {* n/ P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 N# Q o! L: C5 [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 z& o6 U3 X0 v; E# Q( j
MCASP_RX_MODE_DMA);& K1 n' s& ~ t. A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, K' x0 H. s, p9 w/ Y& i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 b1 m' {$ G2 R! L4 \# @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * l$ s- d# N, e5 v/ ~/ o1 @) u/ C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; n1 A$ }; n0 kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ \/ ~' B3 ?2 [' D/ g1 O) \- hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* i o$ }! c$ ]* U& v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% Y. U, D2 s4 {, E. s; t' c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( A% L1 S/ D' C9 t, O1 _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 q a$ i" c1 R5 ]% U0x00, 0xFF); /* configure the clock for transmitter */, E0 L1 ?& v3 X4 b5 \+ U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 Z) `: t- Z/ `6 |, r' wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' @% e' V; [# {. o) t9 U# ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 T$ `5 ~! b; \2 A" G. T7 X6 a/ c
0x00, 0xFF);) O' H. u' O8 x4 P2 R( n) w
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/* Enable synchronization of RX and TX sections */
: e c, N6 X o/ I, X& D1 ~ n- aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ y& \+ R4 g6 F s) `4 d* X: zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 D' q- k7 t( I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ C" W, q9 ~) z. L6 c
** Set the serializers, Currently only one serializer is set as
/ a( e1 N9 k" f$ ?** transmitter and one serializer as receiver.. B% l3 p0 c4 v/ c
*/
6 y+ h1 E8 ^" ?7 Y. Z6 f5 KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 f N" _6 I) Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 z5 b/ M: n8 t, Q( L3 I2 g- I** Configure the McASP pins
_$ ]. u& Y1 d9 a, E5 A** Input - Frame Sync, Clock and Serializer Rx
( n" g$ H% j" e g6 B3 w** Output - Serializer Tx is connected to the input of the codec $ C! X) j: b# K
*/) `" o. F/ T }) w# n' r2 F7 }% n2 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( S4 f8 z8 |- y3 G+ NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 ^3 B3 C, {7 @/ d R# C# sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 G: ] J3 c9 k8 F, R2 q7 R" k- e
| MCASP_PIN_ACLKX- {/ h% H, F* W) O b
| MCASP_PIN_AHCLKX
, _- j7 U' Y2 U$ ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 S( ^2 q0 i4 M9 f) T4 Q( A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 B9 d4 o" R% {! ]| MCASP_TX_CLKFAIL
4 p ^% c2 S& V| MCASP_TX_SYNCERROR- ~/ }6 K* ~7 o9 q6 j2 U# H& I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# o" {: o2 i8 a: D# `* l| MCASP_RX_CLKFAIL
" s% r5 |5 ^3 c5 b. X| MCASP_RX_SYNCERROR
+ d7 c) B# u6 ?5 S6 |/ h9 P| MCASP_RX_OVERRUN); m/ s0 y* o5 s- r2 }- }
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
# @- ^+ U' P/ S/ T7 wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ a( L n L. \+ ~' m: h* OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ C+ j. J- C, |) H5 j4 C; fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 w! N) N- `0 h: t
EDMA3_TRIG_MODE_EVENT);$ c }/ L) { E6 U* p2 e6 j8 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 f# p4 R9 P4 L8 `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 f/ X/ A. `3 X* z: s3 V1 LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! C* J9 h ~; G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" k1 P6 X+ g* K, x( f% ^+ ^' wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. x, U6 y" z: U$ N0 oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( Y' J* X! U$ g- F+ @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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( w# X* F$ x. p- Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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