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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- }" ?9 c; n# z7 t- H1 D
input mcasp_ahclkx,) I' C6 t4 O1 P
input mcasp_aclkx,$ C, T& d8 |9 X# |5 T7 N' g
input axr0,
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output mcasp_afsr,
: @: [& B4 E3 r: W: p# x6 Uoutput mcasp_ahclkr," S* A& c9 l2 Z. Q. w, J
output mcasp_aclkr,
# A* ^4 \/ ~8 j4 i1 zoutput axr1,& r" j8 F" r( r) |1 _
assign mcasp_afsr = mcasp_afsx;
- r X" @0 Q% yassign mcasp_aclkr = mcasp_aclkx;" u6 ~# b+ _8 `4 ]! K" }
assign mcasp_ahclkr = mcasp_ahclkx;" u2 y; Y! I& c
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 _% ]" E3 H0 L4 o; c' R; Q
static void McASPI2SConfigure(void)
1 s- k, g& d4 k6 f{; M) N+ H7 ?; m3 Y, r. a+ e& O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# M9 R: o) O* Q0 q( {0 b# m$ xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; ]: F' o% Q+ Z( I/ e; ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( G4 w% ]) I& u) _7 NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 J; Q* D1 Y* z. OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% ~. |' c% n; S4 v5 xMCASP_RX_MODE_DMA);) j1 [- @9 H5 c" U+ O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, w! I3 R! ^+ P/ I. `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 |! G7 }) u9 K. m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( s: p# S9 V( u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: P3 O4 @% s: t- ?. z4 O# zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . N) Z& [! _# N8 J6 Y) j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 T: m7 C# N0 r, a P3 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 K: |/ l i5 j. `/ I* bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 {0 b) x: ?: c1 m0 U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 V' k+ ?" I2 ?: A* A" S0x00, 0xFF); /* configure the clock for transmitter */
0 ?, i7 c2 V- H' f7 hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ x* ^; {' I* \1 ] fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / \& G. ?' W" `! E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- x1 s8 x' C, }) m8 D2 C# r c+ z0 ]
0x00, 0xFF);
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' R7 W- Z2 j( A1 `- x6 k: K3 D/* Enable synchronization of RX and TX sections */ 3 z8 O; b: W V5 w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 T, \) r0 q K& Y: {7 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- p* G5 E. R* T2 U. W; WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" z( p" f9 ]; A
** Set the serializers, Currently only one serializer is set as1 x7 _9 d/ q2 M5 r; o
** transmitter and one serializer as receiver.
% p' _2 K* \3 s% y* D f*/ j1 A, p. T" q a8 v/ ]! { h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 o! v- d1 ^8 j8 E7 b6 p3 C% q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 R; v+ \. @7 |** Configure the McASP pins
8 M3 C6 D7 w) e6 u0 b( D# E** Input - Frame Sync, Clock and Serializer Rx+ g3 E5 x- p: f) ?# l/ I5 p6 U
** Output - Serializer Tx is connected to the input of the codec
) N6 z6 I/ q9 t* U*/
0 W c3 G9 N0 Z. ~* D. X! a: w4 r4 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 p, a6 X/ l7 V3 p+ ]0 ?3 q: z* IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 Z: n$ a/ q% v9 ?* X; ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 r! T% o2 U! F: `: ]! {% ~| MCASP_PIN_ACLKX
4 M8 ^ Z& q1 I9 l| MCASP_PIN_AHCLKX
/ N6 u* S# ?2 l; O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 }) g' k& {5 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! x/ P5 M2 F) w0 y0 e
| MCASP_TX_CLKFAIL + w8 q% H& r9 z( e2 x. U! ?5 @! \
| MCASP_TX_SYNCERROR' r# [( v* y! j/ u' K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& A5 C4 G3 @; T ]| MCASP_RX_CLKFAIL# F! z1 N& d4 ^; R
| MCASP_RX_SYNCERROR " L4 X4 P" f% x
| MCASP_RX_OVERRUN);
1 d f. }3 @3 s, |! f3 ^# E} static void I2SDataTxRxActivate(void)
7 L+ l" ?' r3 g) k' Q{
+ ^# ?6 s( Q9 f0 w0 x2 _/* Start the clocks */1 X; I( @0 Q+ Q8 V6 M: e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& j6 V9 Q' ^- }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! I5 R2 L$ y9 N' L$ w ~* wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# n8 V9 R4 w: d! S$ L0 lEDMA3_TRIG_MODE_EVENT);% m4 N }$ [) y- x. S# j6 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 Q9 G: L* [& b8 D# }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- E5 g5 q3 i# e2 u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( `) f8 m1 C& Y8 m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 v5 p/ X; k" }& Z9 p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ u: A% @8 S4 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% |; n' J0 `! h6 `$ L- t8 I3 V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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2 t' d9 z z: G9 i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 |4 O( A) C2 b! o2 q+ \, r' k' n
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