|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ G6 I( c: w" ]2 ~+ c$ F7 W
input mcasp_ahclkx,
5 u" I- p: _0 v" tinput mcasp_aclkx, d# t. I3 x3 Q7 W; O1 m6 M
input axr0,
4 M, l" o" [7 L% r7 ^5 a, A
+ d6 R5 m! q, A. ]; J! @output mcasp_afsr,, f; @/ u) m: ?8 X
output mcasp_ahclkr,5 b7 i& \5 R7 u) ]9 V
output mcasp_aclkr,& \* _$ n( M4 c# q" U b' g$ D5 k
output axr1,2 ?. R- C& ^' {; R; T6 C
assign mcasp_afsr = mcasp_afsx;; ?/ ?& e' e( W4 J
assign mcasp_aclkr = mcasp_aclkx;5 N s2 W: ^6 K6 b
assign mcasp_ahclkr = mcasp_ahclkx;
& t5 J2 Q$ I" ?+ a( ]5 j# Sassign axr1 = axr0;
3 ^9 o! v9 i; S( S0 }# B: A5 ~9 e5 G7 H1 b1 y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # ^' C& y* `2 j) e4 D+ d) C
static void McASPI2SConfigure(void)9 r) Y' [# U+ m; p w# R
{
; b+ R1 o3 [- u# ~9 T: SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ s6 I" [2 R, d8 f. J2 Z9 `4 rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 g5 y' J% d" t( f! d) r% g `& O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 O# f; [7 \" r' Z' B, `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 D! \& {" N- P( f0 w" pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; J, S, t0 @0 {6 WMCASP_RX_MODE_DMA);
7 B8 b7 o: ^) o9 V, `+ xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- i Z, v. B1 D3 t0 B0 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. O6 m* c8 F* B1 H# nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( C/ k/ G! Z$ x- Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: W/ ^7 { l, i5 ^; H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 b2 F3 ~4 x( g/ [. o) W) QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 Q2 Y0 A, i$ c3 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# M. I y3 R8 J$ i9 g" x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 E9 }$ C0 n) Q. q( }" f7 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 t3 S1 Y! d) l% G x- N0x00, 0xFF); /* configure the clock for transmitter */2 O! B6 J T4 U! C# k a- i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" p0 N: g$ ~9 j; d4 Z( t- O- y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % Z a% ?. J2 v3 \3 t- }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' j1 I- |" R& A/ K8 j. @
0x00, 0xFF);1 h8 O" P5 O! d |% H4 h
( u2 R; v3 Z, Z N) g; \* j/* Enable synchronization of RX and TX sections */ " a8 E$ ~( L+ M7 ?3 n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 @7 z' C8 T/ V1 Z: h; E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ b3 P5 \/ T. tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ d) t# l& l( H& C# W+ M** Set the serializers, Currently only one serializer is set as- M% U. F- D; D0 u% W3 f
** transmitter and one serializer as receiver.7 j; z2 F# S( E- J, q! l6 M
*/$ m! v W/ K4 b1 G9 J+ y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; z% L1 k9 `# h3 k+ Z" x; m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: u& V( N; E$ A' H
** Configure the McASP pins , s) \" k7 u! T1 `5 H# K$ \
** Input - Frame Sync, Clock and Serializer Rx
# h9 @. W7 w/ H& e: \2 y: j# O** Output - Serializer Tx is connected to the input of the codec ) B3 Z3 m& a4 J4 ]
*/4 H! I: V, ~2 E A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* Z+ Y4 w3 A3 P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( a* i1 h, C4 A* IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 [0 w: N/ _/ H# m6 D, }! w; t8 W& u( M
| MCASP_PIN_ACLKX: T* X7 \: s _/ W. `
| MCASP_PIN_AHCLKX' p, H; L" r. A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& Q$ B. N O2 k: F2 w% e, cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. a- o. G% u( w+ B! ~| MCASP_TX_CLKFAIL
2 }* S/ E* b F" X3 O P' h| MCASP_TX_SYNCERROR
+ q( b6 w7 J) H" Z; T! }1 ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 i. e% J2 `9 {* c% y: E
| MCASP_RX_CLKFAIL
: m/ ]# B$ X: V9 ~( J| MCASP_RX_SYNCERROR
6 n6 ^, I. U% t0 n) u| MCASP_RX_OVERRUN);
1 s/ U2 N/ Z6 C} static void I2SDataTxRxActivate(void)( I, I9 V7 L& c7 T. R( d
{
" t. ~) q* ?, q: o/ A/* Start the clocks */ R9 r; U" l6 @) K# S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 }7 v7 L& t# Y( j+ gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. d; g/ x3 m2 ? [3 i* h4 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 y9 A1 ?. v' P5 W! b" lEDMA3_TRIG_MODE_EVENT);
) o3 S7 m3 z) t0 J, bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* a- y3 _8 v( @- Y2 w' f$ g& a2 aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, F ?, L8 V' r" s2 [* T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
~: V) z7 L6 E- F6 f" m! vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 c& g9 C9 h7 [2 C/ D$ C" u: Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" |" j" K( y2 o0 v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# q" Y. x& H% }2 w1 K7 l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 y/ G% O% N) f Q
} ! ~8 F' Y& b& S2 m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & e y+ _3 B# h0 y+ T+ G- M( F1 K
|