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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! z" F& g3 d, u$ \. v2 g
input mcasp_ahclkx,1 V: M! p/ a2 {$ T5 i! t% ?: p
input mcasp_aclkx,( U9 `1 h9 G% t4 i$ {+ P7 ~( p
input axr0,( Y1 w1 t7 E F, O' ]8 X
# U) c1 I S; g7 E7 l' ]* Koutput mcasp_afsr,+ I# e9 u0 g$ |9 ^5 x+ I
output mcasp_ahclkr,# D8 Q0 @9 {* r$ N
output mcasp_aclkr,$ M0 b1 h5 A" m3 z( r5 r& `7 _
output axr1,( f4 s6 O- ~" m' v
assign mcasp_afsr = mcasp_afsx;
3 b1 }2 L0 V: j: B8 @4 _5 z. R2 Cassign mcasp_aclkr = mcasp_aclkx;7 m* ?7 ]6 r. h8 F
assign mcasp_ahclkr = mcasp_ahclkx;
3 s d5 R, t% U. N) Sassign axr1 = axr0;
: I5 J6 M! `( P4 Q" p: f g0 e4 g7 u* B% ~) ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
w+ d0 z0 M& t( B' V+ zstatic void McASPI2SConfigure(void)
* Z3 O$ @% O; z8 C2 _% w{- @' g( U9 A4 I% Q2 l1 Z( y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 v. }) Q) l/ t3 x' hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 _$ L* P; n8 t5 T( Z) S* xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) m P Y( K0 W8 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) S: I7 n V9 ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 y! A% s( _) b) S
MCASP_RX_MODE_DMA);
0 e7 M, v5 G0 I0 i" x* q+ F+ |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& ?6 G/ x8 o0 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; ]3 q, o7 c1 O$ |8 l( U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* s+ x( ^: w3 i- zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 d' o; K( g$ B' v6 L" c: _0 q! HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* p, C( _; c" YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 x4 v! a) g! U5 C; Q* o/ {" xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 z# S: c) ?( Y! wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. z* |4 I! Y3 J. F' j( R3 aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 N9 G9 x5 h0 A2 K2 Y7 o0x00, 0xFF); /* configure the clock for transmitter */
" ]6 F9 \ v q+ k- d3 O& t" iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! `' v" c4 _! o8 i. J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 e! [/ a3 ` M' t# g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- I0 p% A5 }$ _0x00, 0xFF);2 B" o% t! P% h
0 Z! c. I4 r: S/ E' K1 a% n& p
/* Enable synchronization of RX and TX sections */ ( e' s$ y8 Q, Z1 S" e' W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ h* z4 ^, q3 u: Y7 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 c* v2 ]% ?% X# o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** @* m, Y8 b* x$ u* R3 x" s7 ~
** Set the serializers, Currently only one serializer is set as1 I2 r+ P% p' ~/ D1 L1 @$ l
** transmitter and one serializer as receiver.
$ }& u% V# W& ?5 W0 `2 A*/0 ^7 X7 P3 |9 R, y4 M8 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* K4 I4 O8 \4 @6 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ k; U7 @2 g( B6 h7 Z
** Configure the McASP pins
" D5 f% j& c+ b+ e7 Z** Input - Frame Sync, Clock and Serializer Rx" Y( e6 |" G* e3 S0 K! u0 S
** Output - Serializer Tx is connected to the input of the codec w; i0 @ r0 Q5 U
*/
7 L N$ ~3 |' Q' _7 F5 [0 RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# K/ ]5 M& p. G) M0 Y3 z5 y& [& i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 G' U- {, \ B2 uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 w+ X+ i/ A# U" r! }' K k
| MCASP_PIN_ACLKX3 `) b8 A( ]8 D$ N* ?; U7 h: B
| MCASP_PIN_AHCLKX0 }+ D! W y, O* g+ }; S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* g: x+ T7 X& r" L+ b) D [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! w4 s" B: b' M
| MCASP_TX_CLKFAIL , q9 D' C% S2 p
| MCASP_TX_SYNCERROR
6 ]* H$ `# H) b6 ^4 q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 A( d! I' z9 D( r o1 b8 O| MCASP_RX_CLKFAIL
0 l+ ^& r# |& W0 K| MCASP_RX_SYNCERROR
5 a& i3 G, a$ A% z9 q| MCASP_RX_OVERRUN);1 w6 ^7 x; i6 c1 l/ w9 x
} static void I2SDataTxRxActivate(void): T2 t1 x. q. H% g$ q8 z1 `
{' q2 b0 N: c, [& k
/* Start the clocks */' P7 X1 N% L+ j' Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 x* v8 ?+ |; s7 y# G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 l; v- t5 I: ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ s, a- ]" u* `3 J& t# LEDMA3_TRIG_MODE_EVENT);+ e0 M9 d3 n8 H( }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # B$ H6 O( X' @1 j: i; z0 v! v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* ^3 z ~% H5 p* ~2 ]) k) d0 XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% C1 t5 }9 W6 ^" j1 _4 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 U" w) L2 `! s, qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% z P( b6 X) W; p4 x k' `: q A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- `% a, H$ U( Z! k- h. j3 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ p2 ~7 O3 S* B7 H
} , ~/ i! A: S" q/ |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. g+ G' O, l5 y: C( j/ L2 l* E+ D
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