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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ Q- J |- w6 b+ p4 o9 U) qinput mcasp_ahclkx," G/ J" l0 w* z
input mcasp_aclkx,
4 W% @; b* R8 N# Ainput axr0,+ o9 o, B' t) C. D" x# l
% I# Z7 p4 Y: N1 ^
output mcasp_afsr,7 d- c- B1 ^* V! \ w
output mcasp_ahclkr,
; o1 |9 j" G) A4 y/ Moutput mcasp_aclkr,
. ^& Y4 o$ C+ e$ ]# p4 i6 H: [output axr1,
+ y1 z8 R3 {5 M5 @ assign mcasp_afsr = mcasp_afsx;
' [3 \% Y& b3 e* s4 g9 R( E# H) j$ rassign mcasp_aclkr = mcasp_aclkx;
! O) v, ^5 _' w2 ~( Tassign mcasp_ahclkr = mcasp_ahclkx;9 G8 U# l, H$ l
assign axr1 = axr0;
$ i7 y$ |* A/ |' Y3 T' P7 l4 S$ l; c V* \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( b! T& a/ j) y" e. }( |3 Zstatic void McASPI2SConfigure(void)) {! H: ?" W; `1 f
{
/ |" R& W |) a5 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: v) \; I8 Q( Q4 h f4 p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& I5 H* k+ A6 z' T* i# mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" v$ L. L- s0 W: m6 V" [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 E7 l1 i' y' z7 C6 tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 f! b& m( ~8 B" t5 r2 q& N0 F E
MCASP_RX_MODE_DMA);
2 f" a7 W# U! t# mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: W- j3 U5 f ^1 i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. c, ?, U, Y% W! z* S! \2 fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * t% ?' z& M0 B; k7 X3 c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, |$ y- P1 u9 W! P3 o3 m7 hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' ]9 \" r q: M; I, i( YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, M+ l+ M# {- h0 ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 J0 o# O1 x" l8 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( W$ d( m9 @ L* {7 V* A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 d" W' b ^3 ]# z: p0x00, 0xFF); /* configure the clock for transmitter *// K3 h2 `/ L& C, b. i) P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: T0 d$ E' u; L( V/ {# [- M; j2 CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 `9 [/ Z* }! H! \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' _# E6 L3 N' d' f
0x00, 0xFF);
5 c; q; t5 i: y0 F. ~ y# ~' V" A1 o0 s# J" O7 _
/* Enable synchronization of RX and TX sections */ ( o% M$ B" o# a* A' ]1 X0 B1 L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 _! n0 Y; d2 \* N/ B2 ^* e" OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 m$ |( y1 |8 t7 d6 {4 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 Z3 f; D9 g( U4 m+ Y- m) o+ t4 B** Set the serializers, Currently only one serializer is set as& r: i8 F7 K) \# m: U4 y
** transmitter and one serializer as receiver.
* b) F/ f3 h) N* i" v& d*/, [& S; d. ^+ e" t$ F. d- [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 O7 e8 d0 H& K# I" zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 p3 \& q* y+ A7 Y** Configure the McASP pins # K2 r' f& ^$ i
** Input - Frame Sync, Clock and Serializer Rx7 D {" M( x. r3 W
** Output - Serializer Tx is connected to the input of the codec
: F) J# o) U! x6 o*/- T" J6 s/ l( x- ]5 [) u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) {8 l5 e$ T' K2 [+ z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' ?, Y& v7 k- Q9 r: Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 K* k. u1 d4 Z. |9 H. c" V| MCASP_PIN_ACLKX* ?4 p" X$ M* g, P9 I! c2 @' l
| MCASP_PIN_AHCLKX5 Y+ M# o) y. y) @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! O% i3 P; J6 J, o# C) [) A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 k# g0 B$ B2 r7 |. _
| MCASP_TX_CLKFAIL 2 k, Q3 U! E) c+ n; E$ ~" Z8 \
| MCASP_TX_SYNCERROR
% T5 S* ]& v7 a9 I7 @" z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 i6 v; c% Z, Q4 D4 B. D| MCASP_RX_CLKFAIL5 ], v% S' E4 k% r, M
| MCASP_RX_SYNCERROR
! t0 Z% p4 N. N6 W9 q/ `" [| MCASP_RX_OVERRUN);& X# L. Y/ Q+ i- Y
} static void I2SDataTxRxActivate(void)
# n7 I1 H& P4 M! @, U{- n$ ~; u* E+ p7 h, r7 o7 }
/* Start the clocks */& U, h5 w9 s6 R6 ]. M- `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ _, D4 B2 r0 ]6 p) Q: iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ `5 \$ \& K2 |+ f" q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* x5 ?# j; Z5 e4 }- JEDMA3_TRIG_MODE_EVENT);9 v. |0 _, \4 D- e7 D4 e. c. W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 B2 n6 z) j/ c# @3 e% g8 H o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 E2 u, S3 o& [. A7 @& ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; g6 R8 Z; T; t# r# Q0 E, A" h& E9 F7 [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; i. O. t0 Z" ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 ]" Y# V# |1 \: f+ X2 [# h/ |. sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& j9 V% Y' i. PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& Z$ K- q+ l4 @4 t4 C, o} + e8 \% C. B; B1 d9 k+ ^7 {. B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " b, X' ^$ i" J- t z
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