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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! ^7 }- C( k3 S( q+ F+ A/ pinput mcasp_ahclkx,$ \' e2 Y y" m2 p4 @8 _/ Z9 s& j
input mcasp_aclkx,3 v& A& V0 q9 s4 g8 ^7 r( Z ]
input axr0,
7 O" S, O6 G, O; l
7 @$ ^ i' a6 Q4 b6 l! goutput mcasp_afsr,3 D) T% A6 h$ R4 {1 c& e' g
output mcasp_ahclkr,9 U. z% N2 [ N/ ]8 ?6 W) d: A
output mcasp_aclkr,$ }9 E; ]" ^: ?; s! G6 t
output axr1,
5 o! v; H: d+ ?( } assign mcasp_afsr = mcasp_afsx;+ o7 l; w. _& u) m5 C
assign mcasp_aclkr = mcasp_aclkx;" d7 F9 d3 g$ q6 x4 q+ Y
assign mcasp_ahclkr = mcasp_ahclkx;0 z3 x1 y# K! Q1 _
assign axr1 = axr0;
. L. m( q9 r9 i, p4 S j% X4 d) f1 v8 ]9 R# H% h" _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + w" K s& u2 k$ m% F. T' Q
static void McASPI2SConfigure(void)
3 A, p% ]$ H% m5 i# b6 B+ a{
9 O. d# X9 @! Q5 J5 E) J1 t( TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ T I: X& E, y" k6 SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# Q8 S: w. V0 A7 x3 C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ d/ Y. g) w4 g; w- DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 @6 H3 K* M3 j( C( W0 BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 x" L* _4 x% YMCASP_RX_MODE_DMA);# J7 b3 o6 A/ _+ a# R- ?' @- n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 }7 Z% J# c& gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" L* R( H" q: S$ j" e" e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & X. t2 B$ [* L4 b1 h2 `; n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. [4 l1 D5 ^" Q6 D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( P" g. G+ k; m" n& J* X' c$ B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# [8 q8 v; d5 ]: l( V' u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# m+ J5 o% w+ P+ cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. j" S: X( f9 fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 @0 \+ o1 p9 C% c
0x00, 0xFF); /* configure the clock for transmitter */* r8 M/ ]) U7 |* {$ R, w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& e$ Y5 L$ i: \, B9 f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) Z% L6 h! F' ^% b5 L+ N+ Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ d3 t& t* [" ?3 x7 y) W0x00, 0xFF);
) n- H9 t$ }+ V4 ?- P/ j, C U/ r" L L+ y5 H4 b" Y4 f
/* Enable synchronization of RX and TX sections */
- L- ]: @- M3 M4 h. vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ F. U! b5 f7 [$ h1 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) A$ L2 h* P9 R" ]: h* R3 z1 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 ~ s1 u; ]: K2 @, @2 N** Set the serializers, Currently only one serializer is set as
) G1 V2 G3 q# |0 ~) p/ {** transmitter and one serializer as receiver./ n7 k" k1 Q8 D. m8 Z+ q
*/+ G& R/ } \5 _2 J& z* V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 ~; b( S1 `/ I: qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( Z# y) B8 E% r+ K; }/ Q** Configure the McASP pins , l1 {; h+ g: c. C0 o9 [6 a
** Input - Frame Sync, Clock and Serializer Rx
/ p( p7 C; H) A* e; V** Output - Serializer Tx is connected to the input of the codec
" G/ }- b0 R! v3 n) \0 \3 U*/
* |' k9 S8 H2 wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* I' X! O! ~4 UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 `: N- y8 B7 _" S. {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) @! P$ I; i4 U+ i
| MCASP_PIN_ACLKX% m1 j% r- A. S& F1 ~) d
| MCASP_PIN_AHCLKX
4 L" f" f! Z: ] o& g* T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 H. e/ a2 X) I n1 Y% w: kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) b, g0 l3 t& `, c( S2 b, y+ u, Y9 ^: K3 }
| MCASP_TX_CLKFAIL
6 `0 T/ M0 f/ ^ A3 T4 r| MCASP_TX_SYNCERROR
+ x, G1 P4 ~7 @4 i% z `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : I3 f3 y2 \) ?2 M% s1 c: ^
| MCASP_RX_CLKFAIL! K3 B0 }& Y9 V. \$ `
| MCASP_RX_SYNCERROR
4 {4 g0 s- P4 L; f v| MCASP_RX_OVERRUN);
! M, G4 c! w6 B; r# w, ~8 T. A" ]} static void I2SDataTxRxActivate(void)
9 { F! E8 N0 A{/ V5 @. W) \6 ^% [) D1 |1 u2 [
/* Start the clocks */
" @% v8 k- `2 b4 IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ [) o$ W t0 ?+ e$ gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ r, O. O3 y7 e2 S- H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& U: N% N% U# O, N: @' Y. r
EDMA3_TRIG_MODE_EVENT);7 g/ h* v; U2 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ L1 Z- b }7 r/ PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: A3 {7 r( ]; n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 g7 I% f5 n8 H; z vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; o! j9 @- f+ r2 w0 l- l; G8 q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! ?$ l4 Z& {5 t4 R# h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ k* ~* F8 Z4 N' }7 m1 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% M6 O% Y3 j+ k! `" M5 \" f
} ! F% W& h) X4 t" X" L/ Z) A
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . P1 G* F v) i' p- w4 w( s; m2 B
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