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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. C$ l( E' F: q ainput mcasp_ahclkx, ~5 c% H: V+ D
input mcasp_aclkx,- \6 w) o8 |# L) l* Y
input axr0,
& A8 j' q) `& ?' V5 a4 @! y1 c1 A! ]/ N7 S" c) r. q0 x- R
output mcasp_afsr,0 M4 i5 G1 r. b z4 S6 x% |
output mcasp_ahclkr,
# n! H: u# ?* o" v) M( Woutput mcasp_aclkr,6 [3 E7 R1 k k( _
output axr1,! k: r; s0 d/ P! q, J
assign mcasp_afsr = mcasp_afsx;+ p; A! X1 h2 w) s2 N+ K- _3 `
assign mcasp_aclkr = mcasp_aclkx;0 H3 m+ B. Z" B8 C! [
assign mcasp_ahclkr = mcasp_ahclkx;9 H% Q, L/ }& r8 |. I! I
assign axr1 = axr0;
, A. @ X5 a5 |! x0 N
' D1 v% Z$ ^- E+ I# g0 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 c; j8 ?4 h; m9 y* Z5 ^
static void McASPI2SConfigure(void), ]$ `' S" D4 H3 }7 A; s2 F
{
- Q; L% R+ g; n4 v y9 \: jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ j! E- q$ s& q; H) H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 O# P) K; U" a6 ?# K; Z9 p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# ]- P8 }% B3 u& L; O' Y9 x2 Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 U+ m7 C7 e) D6 v# ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 ]# W7 p7 R; Q9 A) rMCASP_RX_MODE_DMA); L6 i. M# h; T& E2 e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. ~2 Z3 {8 L/ ^# a' I9 k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& E9 J# C! P* V1 WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; U+ g; l# g% R, A/ {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); i# z% M# y* A) B% n3 L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / P' W, F- [8 I9 g7 _; H2 O, D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' N b6 v5 I9 i7 w/ W/ l+ hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# P7 ?3 E* `/ O# ~/ \- y. `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# M: X- }' w% ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 V' v5 o* e+ s1 n$ |, e
0x00, 0xFF); /* configure the clock for transmitter */
6 J. B a, C/ W1 pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 z4 V' r8 \& K$ y1 j/ DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 {% ?0 o! z3 m I' j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) Z0 K% R0 ?" _% U; }0x00, 0xFF);
+ ^$ L) G& _% @- p; C: Y8 D6 w S) M
/* Enable synchronization of RX and TX sections */
+ ]4 Y) Q& T6 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 j; \$ ?4 [5 E" f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 o5 s! \& |+ Y) m: a/ e! r0 W+ x& F0 t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 |! n9 e, a' ^# K% L** Set the serializers, Currently only one serializer is set as
0 y; }5 A; i) a6 L** transmitter and one serializer as receiver.
8 Z8 f* m+ Z# Z*/
9 j6 q# K P* Q$ s0 l! \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 x& r' v. j: u4 J$ A) g! `: i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& c( R. i! p) d0 E! x" v
** Configure the McASP pins 8 Y4 J' M! `) F
** Input - Frame Sync, Clock and Serializer Rx
6 k1 C. x) t$ m& h8 n: C** Output - Serializer Tx is connected to the input of the codec
! D' d2 s; ]' k" ^; |1 a% K*/8 v7 s4 m6 A2 J% d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 p, ~3 N4 l8 C' N p1 c4 e: \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* ]- ^+ d7 u, E; }, RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( O! _9 n$ t: L4 X+ z) Q| MCASP_PIN_ACLKX
. a1 X. T3 x5 n" h| MCASP_PIN_AHCLKX
/ k& Q, l$ P: }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& }1 Q. L2 h; [# B1 cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 X& q' h7 c. }, @5 _
| MCASP_TX_CLKFAIL ; s* Y! b: D! l
| MCASP_TX_SYNCERROR5 l8 U9 U9 _/ g/ A- G* C% t% K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ `) @1 R1 }8 F) w+ h* C# s| MCASP_RX_CLKFAIL6 X" _. C8 }+ V0 _: P# z1 s N
| MCASP_RX_SYNCERROR
0 B+ t% X$ D, h0 ?; a# Y| MCASP_RX_OVERRUN);
V* a1 ^; a8 P( t! ^" b$ j3 f. X} static void I2SDataTxRxActivate(void)6 A P& O: F$ S" b! q# R$ b( S
{: T6 F0 i R0 R+ B, g
/* Start the clocks */
. a4 \2 I% E8 L: [: B: Q/ l! ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 i1 t# @1 c5 d7 x- z' HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 u( Z6 s0 R4 H% C# E/ D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, g2 n% j/ N% F1 b9 L5 ~
EDMA3_TRIG_MODE_EVENT);6 P, D! Z5 l9 Y" b* C. a; G' h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 }% R1 K, J5 {: U# v& d9 wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 k$ b/ `7 { V- y2 L: k" lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) V+ i" g1 p# ~% p1 K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 \/ y& ~, ~8 i* _( f# C% @9 Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; s2 ]2 ~8 i2 k9 w" r, d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 f1 v! c/ F7 D8 o9 d0 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 _/ o3 ?3 u8 O0 k) k, j7 ]8 S1 s
}
/ p& ~' H$ v" r% V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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