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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% l. A0 _. h2 ]/ q9 X
input mcasp_ahclkx,8 |, k* Y& J6 G& v, G
input mcasp_aclkx,
3 z' {' Z8 O+ Ninput axr0,
+ F' _4 A$ F3 M: _- r/ N9 g1 L% \& X5 o
output mcasp_afsr,5 B" M/ ]2 }/ d1 K. B, G
output mcasp_ahclkr,0 X* b. `8 @ F' }! p) K( N. F
output mcasp_aclkr,
& x- i1 d' [( woutput axr1,
/ o" {& `; U- I' A+ l. h: A assign mcasp_afsr = mcasp_afsx;
8 @" F* l8 `( p3 O% Passign mcasp_aclkr = mcasp_aclkx;4 n+ v6 o5 C4 r3 c( K; P# h5 g) @2 Y1 K
assign mcasp_ahclkr = mcasp_ahclkx;3 s% _. Z& t" T6 M1 n, q! ?% f7 r
assign axr1 = axr0; * o! [+ ?0 M9 i, H, G2 Q& I, X" I
4 C) c6 W ]+ I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 \4 {) v# }9 F, s( _static void McASPI2SConfigure(void)
# {, i. `4 U9 i0 L$ c{
2 `+ i8 ?' _* n$ e( k" }McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- P. F; r& M: vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ `, W+ s. I% M9 R: K% N2 F, l6 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ I9 G8 }- `( K' H; P) ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ F+ B/ s. b6 H- s- }+ ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 q' `# j, i3 [) d- y" R: `
MCASP_RX_MODE_DMA);7 @9 D" _9 \* n% _7 e. A @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 v; G& B; o) t% V4 r9 [& q4 F1 w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 ?+ R& K2 E4 p5 e& x+ s: wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# a$ ]* L! Y7 K) y3 fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( e4 v7 Y1 ]2 V" E: j3 q8 }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& [, { E) {1 |1 ?% c" s; hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) H9 x- e3 z6 J) K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 e+ F1 d) h( {" P6 R, w2 tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 |5 z2 e2 d; O* m+ T& D& K5 a& SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' O( d7 ]* @6 s7 H, }% O
0x00, 0xFF); /* configure the clock for transmitter */* ~+ ?+ @4 v9 t0 J' @* h+ X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
W3 i/ D; P! n: Y' o/ ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% r* C. `/ i0 [7 _ p. nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% n. x1 e7 ~$ V; A6 [0x00, 0xFF);1 x) t9 q) D! \
& `$ Y) O4 J( I6 F/ f/* Enable synchronization of RX and TX sections */
: P. i: d2 P7 K% a0 w- j2 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ ]( Z' V% O) S* c N- N0 J" k$ o6 KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 ^" f* ~: t$ d7 [/ XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' i% ~% X$ e3 L) u ?
** Set the serializers, Currently only one serializer is set as
5 c9 `2 g. e/ @2 p. Y: [** transmitter and one serializer as receiver.
# h2 E9 |0 q' M- J: o*/
( r9 p9 C* y$ c' s0 r* [3 Z( [& KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- R9 d# o. w" `; o" G7 B" V3 C' S8 S3 }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ a+ m; E- r" y/ D
** Configure the McASP pins
9 C) z! I# s- w' i& I** Input - Frame Sync, Clock and Serializer Rx
: M# n7 }" A; m ]** Output - Serializer Tx is connected to the input of the codec
: @4 v) h! v( V P( k2 ?4 F*/$ L" J, Z# @6 @4 p$ v; b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# p; {2 e( x" }( ?( `# e: z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 C' t2 t' n( }6 L( H' E2 Z+ YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" x5 _. j0 W2 E
| MCASP_PIN_ACLKX8 n1 h. z+ e3 v+ v" P7 ]
| MCASP_PIN_AHCLKX4 z% d3 Q6 b5 \8 Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 h9 }/ d" L# o: K( B7 ^8 M( C; XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # _9 \* W- W* J% W- |8 g
| MCASP_TX_CLKFAIL 6 @2 M5 z$ b* q- M4 U
| MCASP_TX_SYNCERROR: u( _* z' r8 M2 K8 I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + X: V) R: M h
| MCASP_RX_CLKFAIL" [/ }7 a5 d- [' J8 F: _ _1 \) R! p
| MCASP_RX_SYNCERROR . |" w1 T- t8 \1 T# B& `
| MCASP_RX_OVERRUN);# ^5 Y* t* M$ S
} static void I2SDataTxRxActivate(void)
. F* J" |- O' }# J{6 f i& D, U* b
/* Start the clocks */
. }9 Z" R- c! q1 H8 e! XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 [6 y' K2 |, _, K3 D7 lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( C8 S/ o" C+ u# F6 }8 l. @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* f) H4 g! c9 `) V" |7 m, w y0 g4 H3 K" a
EDMA3_TRIG_MODE_EVENT);7 c n- b; q- b3 M; D0 s! ]' n' {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : X7 R9 F9 { a; f; p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. W0 U$ `$ t! f+ v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; X" \3 ~& E3 u1 h, G: e' r OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 Q# ]2 j! L7 N- e ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 ?8 a4 o, l: l7 D: S! bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 `2 u8 e/ e% wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: w" h2 x7 p+ E} + M# i2 Y! G& _9 Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : _$ ~- n1 ]' V. H
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