|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% g Q* U" C, \3 M0 C" X1 ?input mcasp_ahclkx,
; F1 u* @) e- m5 Finput mcasp_aclkx,2 c' D/ _4 {+ j5 X4 S6 I' P, i5 Y$ @
input axr0,6 s' Q: U& T+ t" I/ `1 G! \4 ^3 C
8 V2 W0 c W) V A& U
output mcasp_afsr,
* E6 m* v' {3 Z. L1 ^2 b% H+ ^, toutput mcasp_ahclkr,
( X+ D9 L$ B7 m$ `* _2 xoutput mcasp_aclkr,5 C* X2 j$ \# b6 h/ m% w5 t
output axr1," O( N7 E: ]2 m% v
assign mcasp_afsr = mcasp_afsx;& e: x% ]: }" Z5 l; o. d& E) B( K
assign mcasp_aclkr = mcasp_aclkx;
$ C5 l6 `# o( Q/ t3 m; x: \assign mcasp_ahclkr = mcasp_ahclkx;, I, x8 |- x4 O, W1 [8 N7 S+ }
assign axr1 = axr0;
6 |" M1 s2 V2 k: F% l
2 B0 f: i8 b* U( g! i2 P8 C! ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, L; Z j1 @+ c; istatic void McASPI2SConfigure(void)$ X- l( G; o8 t- z/ e @& \6 d8 r9 b
{) n& d7 _" a O0 u1 n! a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 s8 z# B n6 }6 `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 ]6 x' ]- b0 O& X) k$ t
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. j* s' F& q$ K1 U# |' L. j. e2 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" h: k% t3 C) F% y! Z4 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# L- ?7 S# B% Q$ z, d5 M, |; KMCASP_RX_MODE_DMA);& w' t8 @( y* L* z3 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, m! o k1 P) d4 b! q$ `/ L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 J' \+ l' r4 K6 B0 ]7 }5 oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 F$ s8 K2 C9 w. a8 t" D+ sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 _6 {# ?# |3 J0 a/ g. J; t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % k2 X6 q) @ \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 b/ {. R Z- H" U$ t9 M. xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 c9 h2 q8 Z1 w! i: jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 n6 e- [- `1 s4 d$ zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, [6 ~' \4 Z& Q0x00, 0xFF); /* configure the clock for transmitter */8 T5 m6 ~( I# k+ I2 z" x* T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# a) c1 }! q" Z3 k" r. z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! e# w0 f6 v5 m/ A' {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- I. m( t0 I6 ]: ^. w; B. O0x00, 0xFF);
d0 }$ U! n% I
4 K1 B& d3 S* M5 D+ a/* Enable synchronization of RX and TX sections */
7 d; F7 [: o- x J4 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) ~) K5 \. \! n3 C& @8 N8 Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( v4 a7 @+ a h+ O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& u& |; V: w$ N** Set the serializers, Currently only one serializer is set as
8 \ P* d. n8 V* L3 I9 E! S** transmitter and one serializer as receiver.
% Z# ?6 w8 O6 a+ \# w: E$ Z*/0 g3 x0 j6 Y0 L: v7 L- M: F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 o! G5 l1 R2 _6 ~1 Z) w( A" {" MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 d7 m! p" U! k% L" ^7 K- m+ o** Configure the McASP pins
; W D9 Z, A7 P& Z) d** Input - Frame Sync, Clock and Serializer Rx) L5 u: s4 k. y9 l6 K* i- h
** Output - Serializer Tx is connected to the input of the codec & w6 X. X: W2 v+ ]- o# M" F4 N
*/9 s4 |& r' }, B# b( n6 C, P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" B6 s0 W7 a( D uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& m& q8 J* Z4 T4 u6 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 U7 c. B# v2 m- A- o0 z; F( w( X| MCASP_PIN_ACLKX1 {8 \$ e7 D: I" R
| MCASP_PIN_AHCLKX" T/ d6 h# I1 E0 V: }2 l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 H8 e: f. M6 B* e8 `6 v/ }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* @9 ?9 z" ^; m2 x, I| MCASP_TX_CLKFAIL
) U" ?$ l, A# {| MCASP_TX_SYNCERROR
6 O* ]0 T% l- G% ]' F' N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! [/ {' t8 I& M
| MCASP_RX_CLKFAIL
{* v5 c' T2 L( R6 t7 u| MCASP_RX_SYNCERROR % {( k% A* r z4 L8 y2 }
| MCASP_RX_OVERRUN); c* O) a. K+ @* ~3 X
} static void I2SDataTxRxActivate(void)3 H& i, q' l6 p, R- E1 `$ B
{" [0 q, W) Y. Y$ a
/* Start the clocks */# s9 y/ x. {, X/ W5 f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' T: x1 F/ [( }- H7 Y0 N Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- ?! z6 [( {1 l9 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* ?* X& n: j+ G6 y( _
EDMA3_TRIG_MODE_EVENT);! z) G, b! s$ P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 y z5 X5 V! G- Y& uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ j) k5 W$ t7 z: s# T8 b, tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
t( U I# ]8 d [$ ]& b5 ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& _$ d/ w r+ {$ [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 K2 i! x4 m$ }8 G% t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) X# T6 |( s# o! p1 DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 X5 a+ d0 P0 I0 g" S! M8 [
}
4 B, }7 f" Y9 Y! n5 x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - Q8 T: [# X2 |! o
|