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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- o/ m- Z% ^) A% e* q3 K
input mcasp_ahclkx,
: L: a5 W7 [2 L8 D6 O* n5 ^input mcasp_aclkx,. r2 S) W6 l t: ~2 I2 v; G
input axr0,
0 m ?+ |9 d: |; U8 Y0 S( ~; H, F# Y. Y2 V4 T7 D. T" d/ x
output mcasp_afsr,7 X& m8 G9 u2 n. |
output mcasp_ahclkr,! c6 S8 t" _ i% s% ^
output mcasp_aclkr,1 c( k* V1 p' d5 I, ~; ?# t8 V' \
output axr1,4 T! [+ T' k1 } A: ]5 {* \& u) G
assign mcasp_afsr = mcasp_afsx;# x! u1 G' c- y4 }3 i/ X' O* s
assign mcasp_aclkr = mcasp_aclkx;" v; t& w7 ^. c: p( [" |$ W
assign mcasp_ahclkr = mcasp_ahclkx;0 X6 k( a/ u0 ?& i9 {6 U7 f
assign axr1 = axr0;
& L I# q4 X- o( R) {3 t' O5 ~# V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , H+ {5 L! L1 h, g
static void McASPI2SConfigure(void)3 e: }& k; Z9 N1 H7 H
{
/ R$ ~7 q3 A4 L/ Y# wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 @* J2 r2 ~7 K {, P' o8 Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 X* ?% g7 E+ U) i0 o; K' @" LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ @5 ]1 l5 L2 }8 r9 G4 ?! D+ L* ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& R B3 V N- @4 I0 K5 N3 uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# p* u! l1 j- DMCASP_RX_MODE_DMA);
' R- F4 m( u" h6 W$ z* u7 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 v8 z) E! ] E! z- fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' f/ [# } h) i. F) PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# T- H4 e, L/ ^/ RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 E3 |% n7 T( u0 ]- @% g3 b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % R& M7 x& A7 U: Y. h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: V# {4 y$ l; ^ a' J4 D0 x+ F% o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 ~/ Q9 m0 Y" x: h4 _$ t! X8 U. R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
A1 } A; ?- t. w5 x! AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) |6 j+ k. n7 R1 E3 d& t
0x00, 0xFF); /* configure the clock for transmitter */
& K. c/ A' \# |, k2 B. aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 a+ f6 I* p5 r7 V' s& q, G% {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ C; O! q3 ]+ V7 {' Z: H1 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! B! D' Y, }, [( j3 D4 o U
0x00, 0xFF);
7 G4 u3 g5 C; d3 d2 j; \- W8 `% H, A+ L0 ^% D: S0 F- Y% q1 T+ U
/* Enable synchronization of RX and TX sections */
! P4 l" y7 [+ JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( t4 D8 ?: J$ M. v/ n, G) eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! a5 d2 d5 Z6 aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& d# w( X0 A% F** Set the serializers, Currently only one serializer is set as
: l/ c1 s6 U3 |** transmitter and one serializer as receiver.
3 N: F' J s. c/ s2 r: x( G*/
) k% A" A: `! OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 }) R1 z4 k+ J0 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' `% {% `. T: c% ^7 a* O** Configure the McASP pins
1 S5 R* i8 D5 w; V$ m** Input - Frame Sync, Clock and Serializer Rx: c* {7 t+ U0 V6 b; C/ S
** Output - Serializer Tx is connected to the input of the codec
4 c4 I. w! f2 F* z4 o*/# I. L6 Y9 L9 |4 C# f6 i% \3 D/ \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: N9 D: r- L! v5 e; k. d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; C0 i) Z! J9 \8 f8 _5 B2 b% I0 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 ?* N$ @- L9 M9 r
| MCASP_PIN_ACLKX
' g" G( e3 v3 C3 b% m0 f* z# X| MCASP_PIN_AHCLKX
% `, `9 l& z. P" N6 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 {: ]% K: i- G' B" q7 j" b. g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 X. X+ J* B$ h9 f; w7 ~& G& j
| MCASP_TX_CLKFAIL
1 x% G, F, q P- O }5 x| MCASP_TX_SYNCERROR: u5 Z9 a+ t" F- ~9 a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 J8 }) m, j& I6 ]$ a
| MCASP_RX_CLKFAIL# M9 P6 {' ~# n+ d/ B
| MCASP_RX_SYNCERROR 7 r% ]+ g* ~. Z2 K$ v7 R8 r. J
| MCASP_RX_OVERRUN);
( }7 a0 E$ ^6 I} static void I2SDataTxRxActivate(void)
' ~1 z/ W+ D U{+ k3 H! s9 G# `
/* Start the clocks */( _: o c w, k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ S4 |5 h2 S# `6 n& |2 M7 X( a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ U3 U- Q9 ?0 s7 q' i; H% f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 U( w6 v( h5 R
EDMA3_TRIG_MODE_EVENT);
5 `7 w4 o+ a8 T& N/ V) V) t/ I( ~$ |' kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, x; G! O0 R) _) y2 l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 C7 `4 |8 H7 S2 @+ hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 [# J+ S1 X& j* g% P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* n, J% U) ^8 d2 y6 S3 [9 Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% F# O; W7 f0 {" ]# g3 ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: y1 }) a( ~$ T* T" h: B/ f) {5 gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 J; Z' q2 d: T* h) I3 B( U
} 1 }" N+ U+ }* F, m- k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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