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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; _& X* y4 F, m0 Q
input mcasp_ahclkx,! m: v; t* z# G! L& R, {
input mcasp_aclkx,5 N% k" n3 P! s* z& j
input axr0,
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output mcasp_afsr,1 L7 Y9 g$ p% }" J
output mcasp_ahclkr,
6 e4 y" F1 F' K0 }5 [( aoutput mcasp_aclkr,
) K! e7 b9 l8 p# I* U9 u6 Qoutput axr1,5 {! K, E" R; B2 _
assign mcasp_afsr = mcasp_afsx;
' Z" v5 \0 P5 ` t* K! N3 ?) r2 Q# bassign mcasp_aclkr = mcasp_aclkx;8 ?4 n+ Z" C6 V, n" K8 r; l+ Q
assign mcasp_ahclkr = mcasp_ahclkx;
+ ]: q; I' u7 Q% ~assign axr1 = axr0; % h! s$ O: I! S
+ ?6 ~ h9 @0 D" F% g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / @3 m' v: a2 W. E. B1 B9 o; C
static void McASPI2SConfigure(void)/ Y6 S0 q7 U8 G( f: s
{/ H& P1 `# E L# L. s, R3 O8 b* a! E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! o1 p, e- R4 \6 |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 H. H6 D$ d( [6 F3 ?! zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, f+ y" u, J7 i3 F! r4 s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- Z2 T2 y8 o* @- T, ^% k, B* i' PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 O+ k) r8 r; a) Q5 s, ?1 ?! B, @
MCASP_RX_MODE_DMA);3 A! K2 R% \4 b1 `: D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& W+ b/ i8 j' O! T1 L! R( w, |# O& mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, V$ O) U0 ]% l1 c' qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* Y5 W! ?- Q# M% R, ^5 DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& X5 b1 ?4 g' M; \( n; j' M) b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. B4 ^8 j& Q. U. z0 n2 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; v& r5 J% S7 Y9 [2 Y7 p w7 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! q' j7 t6 V& t' p: g- [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ ~8 O. s. t: D; a) z4 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& V, l7 G( T! _6 q0x00, 0xFF); /* configure the clock for transmitter */+ k" l# O' {* N8 o. u5 v0 z1 s% o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 M7 e4 ?, _% m" t7 N! Q# g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 Z) g( V+ K: A! D0 r+ S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' A, Z9 h0 a7 {$ O* ^5 {
0x00, 0xFF);( W9 Q3 V* K2 ], c
. j: B6 }- |* O& U* _- h& `+ v/* Enable synchronization of RX and TX sections */ ' ?+ F4 F( Z$ W q1 A; P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 w, c! [5 {0 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% Y2 y! y3 T. N# WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 Z! E |: |8 f$ S# L# b' F
** Set the serializers, Currently only one serializer is set as! o5 W/ p& ~8 T% Z: R" V
** transmitter and one serializer as receiver.5 j1 D# S5 A1 [ j7 A
*/
; g3 |. B, @% A) A( }/ d9 WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' ^, ]! e: E: l+ H" I+ v; R% I: u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# B4 t s! A/ ^** Configure the McASP pins 0 M: s! W) P1 i ~7 W
** Input - Frame Sync, Clock and Serializer Rx; z! ?, l% S9 m& Z8 e3 c
** Output - Serializer Tx is connected to the input of the codec
8 g) S, T v' k8 ~" K1 N$ q*/0 e- W }& ^! m/ d' c$ i! z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 ~5 p/ v/ ?0 i5 J3 @' i4 N1 e( s( zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 c& o `# Y; H8 @! m, vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 N- Y6 j# J" m* G| MCASP_PIN_ACLKX2 N/ f ?- K2 [8 O w* @
| MCASP_PIN_AHCLKX
# u9 y1 Q0 [" D6 I: r) F1 I0 V6 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# I1 G7 o3 e$ v {5 G5 w0 BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; p. d+ I2 z! q9 J
| MCASP_TX_CLKFAIL
6 z ?9 a+ _: B4 j* X| MCASP_TX_SYNCERROR4 t& ^2 g- w7 z x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& ^3 Q. Y' E( H! r& h8 ^| MCASP_RX_CLKFAIL
6 A* w) j' m* e$ |* v" G6 E3 \| MCASP_RX_SYNCERROR
. J9 }, ~' q% k+ R7 b3 ?$ }| MCASP_RX_OVERRUN);
- z3 M+ C+ p' y1 _& g4 O+ X" O+ b |} static void I2SDataTxRxActivate(void). j5 Y: C$ I5 T* b( U Q$ t
{
: M) V# ^+ Z2 c3 j" h- t/* Start the clocks */' |+ I7 |4 F) a0 Z6 x. W/ }* \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 }5 |0 U4 t1 _1 ?% G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# q" E Z0 d @4 B% m* o( WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) I- ^1 j: ^% C: q9 y' q5 F5 A+ U
EDMA3_TRIG_MODE_EVENT);
# X+ a3 U) i9 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( G5 G. h$ a! Z& D
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- N( _# A' j' j8 `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 [" S: { y- Y* {; ], I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// P. O- O4 K1 S1 D0 ]" E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 M1 L2 a+ u7 Y2 g- ?; ?; QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ c% K' F$ F# RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# n" {/ K! o0 b( ]6 v
} 0 r4 d; p) k6 u% H0 {% P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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