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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 I% H( s9 `) S- a* P/ b
input mcasp_ahclkx,
" {4 G0 H( b3 Q3 vinput mcasp_aclkx,
$ N0 J ?8 ], H* V5 c5 Kinput axr0,
& f) ] V: q* [9 t7 z# e/ \6 o7 T
" R+ q) _ v: r5 e d$ goutput mcasp_afsr,& K2 o- F6 Q$ C2 Y" l) q
output mcasp_ahclkr,
# l* `. V* i+ O* G% |output mcasp_aclkr,* ?; t( V1 }1 C2 W( g9 o# B% b# T* v
output axr1,
- x! Y, }6 q0 D' ^9 b, p! w assign mcasp_afsr = mcasp_afsx; Q, t) C! ~0 a' |
assign mcasp_aclkr = mcasp_aclkx;3 v6 m. W; g' E6 y2 f+ \! \
assign mcasp_ahclkr = mcasp_ahclkx;# l) N$ I% r9 u
assign axr1 = axr0; - F' [7 D8 c6 [. n* ^! }% q) W
' q% U1 [! Q5 \- h3 e+ E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: I% I8 T8 @" b0 |: tstatic void McASPI2SConfigure(void)1 r6 u/ u, `0 a+ d: |
{/ V: A: n' k9 x& R. X( d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 A9 v( R1 q' c. VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, w8 h; q; ` \+ rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 M9 w& S6 J/ Z, D h6 f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 }. h' ?) Y, g* X$ O8 p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( y t$ W, t; p2 ^
MCASP_RX_MODE_DMA);
# N5 u: R+ }1 I9 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( Y+ c/ D1 N( X" t8 ] I& @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 a8 v" S8 s3 F9 A v9 EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
q+ j, O: P- B8 x. }! {- m0 aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# j0 E" T* B4 R; {; Q4 q* u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 b/ [1 G/ I6 r; k+ F- @" B5 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ B/ K" h$ v1 y/ O: E8 g0 ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 t& y, y% |+ W. `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. U/ s& s: Y( ~7 ]& lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* Y3 a4 J4 Y' K0x00, 0xFF); /* configure the clock for transmitter */7 G5 R g( y) @+ a' f* M9 v' J6 I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% G/ u# K/ m% A* C+ F8 `/ e( R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 A8 [8 L S- D% l Y" L: p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ ~1 e# N8 @% ]1 F7 v0x00, 0xFF);3 Q f; w" t T' H. c
8 Q! L4 m' C! M' W
/* Enable synchronization of RX and TX sections */
U, j: u Q2 z& U a. ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 l) S5 B( u9 t" ^5 M( D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- Y; w2 c. H/ V4 EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 N b) E6 N% |- M9 w' P
** Set the serializers, Currently only one serializer is set as, s3 b, y, o) J) {# ]
** transmitter and one serializer as receiver.
4 x4 D% e* L3 y6 u' b*/( x" M y3 F5 e7 k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ y6 [+ G! V8 w. _9 @, r/ AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 X1 `' E2 g0 {9 A# U
** Configure the McASP pins
5 F' ^- B; T9 P8 [9 l8 }** Input - Frame Sync, Clock and Serializer Rx2 I" O, w: Y/ Y+ I
** Output - Serializer Tx is connected to the input of the codec
. D( ^9 k' z# w2 M*// W6 d7 V2 L& V# T: I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 [1 L5 s( Z. T x/ X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 k; K1 T, L2 _% N# @: iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 k% ~ s2 f. k
| MCASP_PIN_ACLKX
3 [3 N% G" E+ F; ?| MCASP_PIN_AHCLKX: q- j# a* \ D5 Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ l) C. j' P, F* q- uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ n, N; p2 V; u1 j9 H5 ~* q| MCASP_TX_CLKFAIL
9 M! T5 x) `. q% l* Y| MCASP_TX_SYNCERROR x4 `4 `! l- i8 \3 _; Y* H) |: a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : p3 C1 G4 M2 |
| MCASP_RX_CLKFAIL
3 c% M. [" e! k% x4 t; F. b' u0 k$ u| MCASP_RX_SYNCERROR 6 h5 i" V2 H S& c9 \, e
| MCASP_RX_OVERRUN);9 G1 i$ |2 I8 i1 m1 |
} static void I2SDataTxRxActivate(void)
* G% o7 U4 h1 t# O{- ^" o! S3 p9 {% i
/* Start the clocks *// X9 b" l0 d6 H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! a7 ?! l" |% j2 G7 x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; k$ O: Q; w( KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 M2 R+ x& D! b7 y) d" MEDMA3_TRIG_MODE_EVENT);
9 p5 o$ D' g8 j+ dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! N: A$ z: f# y, o2 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 r$ u# c4 z5 J; _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 S# y9 J ~2 `: Q" p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 q0 Z7 m: B" i- Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- c5 A8 Z! @7 n" \& c: iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 P- C& ]* ^, @2 s4 DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 {) p1 }( \1 T, T8 |}
% \- [, ]% T( a- I8 Y$ L+ x5 a, W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . k1 q+ u! w1 X; C6 b, e+ t; H
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