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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," _& R( b6 Y8 R
input mcasp_ahclkx,% D" h8 M' j& T' a: e
input mcasp_aclkx,
6 m% \; l9 y" s* G, O# N# |+ x% Ginput axr0, D$ A1 C J! Z; _! Z- m
% g& [9 B: C% U/ ~* T. X8 Joutput mcasp_afsr,
0 t) A. ~& a4 poutput mcasp_ahclkr,# F: f) l2 e" j# _! ]# n
output mcasp_aclkr,
5 m; s O1 a& P5 |! I/ `; Q: doutput axr1,
: x# z. H+ f# t# B6 _ assign mcasp_afsr = mcasp_afsx;
) A* R, G6 f0 n( _; E1 fassign mcasp_aclkr = mcasp_aclkx;. v- G9 ~" K" t
assign mcasp_ahclkr = mcasp_ahclkx;
- Y$ G4 j# b3 Q; Iassign axr1 = axr0;
# {" N7 a/ v' W7 w% m1 [( Q0 x& {5 W% t/ X5 p8 D1 L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 l o7 K) e) j* X9 ostatic void McASPI2SConfigure(void)
3 n5 q" d c/ g. y3 S& Q6 F- b, M{3 k8 x6 n8 |; m" ?8 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. G! k3 N+ o: e$ T/ b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 S6 r( q+ ?; s5 U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. V& e+ b) }& K1 k' I. }, g5 m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 l. z4 i5 @0 d5 h6 qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 I0 o* ? \3 L/ S" q! pMCASP_RX_MODE_DMA);
0 h& Z* z5 I& O5 x3 d" @ ]/ KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. P- I; D) n `/ ^; K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! m: O3 d! c! c* F6 V! R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 r8 X ^9 G H1 k' y0 cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 B1 i7 T( g' p& |. mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 s5 W! z5 D& q8 W% E( QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ [) D2 P+ d0 q/ ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" \. @ b8 j; S' J C; [" y! `5 |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 [0 g+ k9 i2 F$ ]- S7 G' K( J; r7 hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 x! y& P0 Q4 s+ D, [
0x00, 0xFF); /* configure the clock for transmitter */* ^; u2 W5 l3 V* h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" w/ A5 @. N6 v5 E3 N1 NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
R1 y* ^- _" n) Z5 j oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 {% u2 o. j% x2 N. N9 s: |. W0x00, 0xFF);" N1 ]* d2 D9 g# k/ d7 k
8 ~' x! R8 o) l0 b5 H$ ]/* Enable synchronization of RX and TX sections */
# A5 [/ ]5 P8 d% }' y% GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* c# O0 j: o( A2 ^/ m E7 \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, Q, |' g# n+ p& X8 P9 l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 I4 q7 \' w. |; d6 p** Set the serializers, Currently only one serializer is set as
5 i# b8 c) h6 P0 ~+ s% L** transmitter and one serializer as receiver.
1 p1 k: p8 h6 y. g: q3 x! p*/
2 w8 r$ g% Y+ _1 H9 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 q9 O" O( n% v7 i: c$ e5 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 A+ m: _" a8 S7 @, A: Z9 p
** Configure the McASP pins
" f7 T) M9 y r/ W8 x0 G1 m, m& Y** Input - Frame Sync, Clock and Serializer Rx3 g! K* s4 N, V5 I. h8 V
** Output - Serializer Tx is connected to the input of the codec 6 ^" C: k* i& i( H. @2 ]
*/
2 e8 A1 c$ c; P( }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- l9 E" ]( z) y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; u* {: R/ w$ QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 b3 U5 O8 G, H$ h
| MCASP_PIN_ACLKX2 q9 X: @9 j! `2 q; F6 j
| MCASP_PIN_AHCLKX
& p) l+ n. v0 l; G9 {% u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& @/ L7 K: S! X+ @7 M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! i; Y. }, M+ X0 S! z
| MCASP_TX_CLKFAIL 1 o' l* K5 K+ K
| MCASP_TX_SYNCERROR6 {1 p+ j0 B# s3 l" R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - l6 F5 ?+ x0 Y4 m2 p
| MCASP_RX_CLKFAIL" Q1 V( Z& }6 W4 x) ]) o- {" w. V
| MCASP_RX_SYNCERROR
+ y; V* O# s: h- ^) j| MCASP_RX_OVERRUN);
+ u& t( x6 {0 e3 C/ k7 {. q} static void I2SDataTxRxActivate(void)) N8 F7 f H* `* p# l6 V5 U9 b( z' n
{: ]1 R* y3 V, p' K
/* Start the clocks *// |3 b, ?. M+ j3 O9 l& w% e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 n C* V3 C, N- A2 a6 ~$ S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. V9 @6 k, Z3 _: x0 A/ r. d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 y9 x5 h' f% @3 J, d/ ~
EDMA3_TRIG_MODE_EVENT);
# ]7 U% X. ` K9 I2 B$ B# ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 w# l3 M5 O& R( P! d, o7 S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 t/ N2 t/ ]8 g0 H4 H# }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 l n5 ]3 V1 W* }' ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" s% s; ?7 z3 g7 w* o' j9 T/ Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 o7 L0 i& z% ~" ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" s# F* B6 A$ ?" ?$ i, dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% q) o& W2 O+ T$ O4 v1 }$ l} * M& w9 p$ z2 B0 B& t3 _/ D; D/ s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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