|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( R ]1 s) P- K2 `) D+ n+ \
input mcasp_ahclkx,
8 l) h; U* F) ~+ o# u: N/ [7 q; H% m) G* Linput mcasp_aclkx,# ^1 Z% E' Q# O2 Z
input axr0,
! ]7 B: {, i6 m: I$ `% R3 D0 T) z6 Y9 [+ I+ g, Y& n
output mcasp_afsr,
5 ]8 p5 K, ^. H7 e6 \& boutput mcasp_ahclkr,6 K4 A; D8 k K# D
output mcasp_aclkr,
" `( K6 T- W5 _) [output axr1,
/ ]3 Q2 N; @7 H# @ assign mcasp_afsr = mcasp_afsx;
0 }$ c- J- d* o- b6 Tassign mcasp_aclkr = mcasp_aclkx; ]1 B$ w$ z& _9 E; J
assign mcasp_ahclkr = mcasp_ahclkx;
# g' F9 a2 @+ b# A, W; R8 gassign axr1 = axr0;
4 E) A! y! [! [" p3 n
% r; m9 l: N: S2 ?7 e5 l+ {4 e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 L% H- z1 ?7 B8 R% h
static void McASPI2SConfigure(void)! Z9 x6 }* C B, z+ r$ i
{7 Z3 r$ K+ k+ Q0 o1 ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 K% |+ |+ I' N: X8 Z4 x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, k0 N* V- z* |2 s4 ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ @6 H7 G) @; x! M1 W7 U# _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 H1 B; p7 b& N9 s1 I) E2 T% XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ z6 B' r; R* k; K
MCASP_RX_MODE_DMA);; N% ^3 d: \8 r+ ]/ x. h( i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, V K" i$ _' ]# ?3 q) `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! D U" Z, g1 G, M* X2 f& Y, tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 _$ p1 g0 ^& x: H2 j7 A1 BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 L: @5 p+ N: y0 f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ |% Q5 V8 I* [/ O9 M7 \. u. w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) e/ M) E9 p2 k/ I8 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 J7 X4 Z2 f: u" V/ h8 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 Q# D& y& u8 t2 |5 I* }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ U6 V3 C' ^1 T' B2 B$ Z* k- r6 f! [
0x00, 0xFF); /* configure the clock for transmitter */* q1 D+ N4 t9 U1 T3 o6 V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ S5 z) J- H! c* I' B1 u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " c5 A( F- f, a& U$ a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 S' @1 o; X% _- d7 d# ?
0x00, 0xFF);
. K! T5 J5 B9 z5 X' {4 K$ Q* d; i9 e4 r: D) |& c
/* Enable synchronization of RX and TX sections */
. U1 W; D7 {) T7 R0 PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; g, y6 z- p& f- W2 _) b7 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' U) s1 D* a* x2 A" ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' B' v1 l6 L: j( W; s) v
** Set the serializers, Currently only one serializer is set as7 ]1 U; ]8 n# L
** transmitter and one serializer as receiver.1 P, j. A/ Q5 F/ v+ t
*/% ]$ K8 a- |: f( p' a) N/ w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! Z+ L. R- B0 A, t& y' n+ t0 t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 X3 D. x! T d, U0 ^
** Configure the McASP pins
$ N" P) Y' [1 t: V/ v** Input - Frame Sync, Clock and Serializer Rx" C, G6 _! i/ U( u( f/ }6 _7 Q
** Output - Serializer Tx is connected to the input of the codec
7 i' z( p6 H. m+ D" c: i1 c+ a*/
' A" ?& n5 [- X3 ?1 W1 B' g' zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
{4 I' w9 X' y% m- B/ q& [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 j W$ M$ H4 A0 E# W" ?' U. HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- L9 K/ D3 w1 O$ E; C| MCASP_PIN_ACLKX
2 x9 z, g: H1 f| MCASP_PIN_AHCLKX
, \, i+ c) Q7 D9 Y. ?( C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( v- m0 F2 h- j+ e( J) k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / j+ ~! [3 G0 p. p& q
| MCASP_TX_CLKFAIL
; J) }/ x1 [5 q, C| MCASP_TX_SYNCERROR
8 @% [! h$ E% \, u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , h N4 P3 i: R) A4 q( z8 k
| MCASP_RX_CLKFAIL
0 Y! m/ C: u8 \| MCASP_RX_SYNCERROR
4 A6 a2 B( V- l% F| MCASP_RX_OVERRUN);& r) S6 x$ b1 |2 [+ u
} static void I2SDataTxRxActivate(void)
: v3 [0 |' c8 _- U9 P{
6 ]' ^) d/ x* Q. O! b# h+ t) C# [/* Start the clocks */
0 z5 `" b( y, m, b: GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 Z5 [$ W D) PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 t5 A1 q+ H, [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 M1 d1 r* u% r7 d" H
EDMA3_TRIG_MODE_EVENT);
" t- S0 ^6 Z& a1 h9 @$ ^7 k% WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; V7 t3 y; T5 F$ w/ E2 [& [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" c$ J6 g6 E$ M. FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, B8 l8 f8 e( N2 `$ @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; n ^/ O( Y" Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ h e& T# U) B9 V& v) j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) m) n4 P0 v' d, w# ^( W$ vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ v- L) t3 r5 n; h' I$ O}
6 q' s9 u- g% ]: i- L6 ^0 z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
3 o9 {( j9 C1 i9 v Z! R3 O0 q |