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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 p9 D/ b. |6 S) h6 \
input mcasp_ahclkx,
( Y R0 l. q2 i g4 \' yinput mcasp_aclkx,+ R& ^) @3 S/ B9 W+ S) h0 T9 e* G* |
input axr0,: F. O* [/ w4 I) w# _* }
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output mcasp_afsr,, t0 Q0 }1 q( {: Q+ s/ b
output mcasp_ahclkr,
! p3 q& z; C2 Y' x( V+ Zoutput mcasp_aclkr,3 f( z$ |/ G# t- _7 o- E2 n
output axr1,1 w8 y/ y! k3 L
assign mcasp_afsr = mcasp_afsx;
* \& W5 ~% N$ D6 ?" h. u! `assign mcasp_aclkr = mcasp_aclkx;1 n( g/ E4 g1 A8 c, f: ~) ?
assign mcasp_ahclkr = mcasp_ahclkx;" q0 ~1 z7 m- C( Q# R+ V# m: ^) a
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 v5 s. O1 z; @" E+ A7 c
static void McASPI2SConfigure(void)' c5 H. l9 @! s1 f% e( i
{) S; U% T" r, E9 o3 T0 X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* ]9 W! l7 H; H+ |9 P( B6 L# b! e3 ^. ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. ^$ w. P' R! U7 FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 j& o3 j* o2 S* S: B) \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# U4 s5 f/ o- ^% Z- t2 W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 P p. P2 o3 @( M
MCASP_RX_MODE_DMA);: L, ]2 e# T6 d2 g- D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
M. l; n- d ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 Q9 b2 t& y3 ], m4 K: E$ S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 g0 z7 M- L3 t& \9 R/ V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. H+ l5 f0 E% H% YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + T" k- W1 w1 k! n W, y6 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ O6 _1 P5 f# e! [, C; ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 }" ^% P, d. }- Y6 K9 DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- j8 @1 N" ]3 mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" {& a" x \% b+ `2 i! R4 x0x00, 0xFF); /* configure the clock for transmitter */
& T, E) M" v8 n9 ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); Z8 [' H- _/ Y4 e2 l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : _ t. R' C7 w, @2 D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. W8 |/ z( w& x7 L9 H: N) x. _1 x' X
0x00, 0xFF);
! ^0 p5 M& R- j; V* W3 S) @
3 F# N2 d) Y# P2 H* B$ B4 m/* Enable synchronization of RX and TX sections */
/ f0 P) F1 R H6 zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, W- c% n2 S; a: dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; w5 Z$ @1 G0 i! Q$ \3 k" n# K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; e) h0 c4 y& ]** Set the serializers, Currently only one serializer is set as
0 G. Z. _- w J4 M' E4 i** transmitter and one serializer as receiver.. I* G0 o: F$ c$ g" o) \% L1 p
*/
9 ~7 m8 D9 X2 H) e& ]% eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( D! W# q; Y2 e" y1 G( y nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! i5 @& o: H; x3 h
** Configure the McASP pins
a u% @. d4 h- ?** Input - Frame Sync, Clock and Serializer Rx6 ^, k+ i+ O) _% ~' F. p1 X6 X
** Output - Serializer Tx is connected to the input of the codec ' I8 V2 F, g6 H. S
*/) F( B# d9 @6 m4 ^$ q7 Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" g. J6 S6 J: `0 B' }1 J: AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* o9 g5 }( M. C% r. q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 R- f; C; p1 e! h% I P
| MCASP_PIN_ACLKX
5 p C& F A: _; Y) ?* m) X* `| MCASP_PIN_AHCLKX3 r1 z$ e" Y( m% C" q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 w+ y( f( W: k7 g4 SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 V& h; d# [$ g* m7 q; I
| MCASP_TX_CLKFAIL
$ y. p5 t5 s# i! p) C| MCASP_TX_SYNCERROR
6 V: D; V5 p" m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 K5 `1 v/ h* U" O6 {
| MCASP_RX_CLKFAIL; a2 V+ w8 J3 w B: t
| MCASP_RX_SYNCERROR
9 l5 p/ \- m( o* d# e/ e h| MCASP_RX_OVERRUN); z7 v6 {. @- E8 |
} static void I2SDataTxRxActivate(void)
* h6 x" b9 N7 p- d{
" F" u1 u4 p2 }/* Start the clocks */
+ x( r8 a, a. ]+ w7 KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' Q" F# J1 c- a: B4 r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ R+ o0 Z2 P" x0 F1 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 B. V6 {2 c5 w
EDMA3_TRIG_MODE_EVENT);
& F( d, ~# I# K( V! fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " ?6 _: K' T) h0 ]3 P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ a! z. n/ `& L$ W! p+ t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ y; E. b$ w7 UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& b2 u9 [8 }; ]! {; ~) x/ iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 E. X& p/ I6 l; [3 P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ |. M; R, W" Q1 r5 QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ `0 R% `4 y. {' \, y: {' ?}
2 s# y! Q6 o( p2 W4 `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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