MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
) W5 q( [' i1 j0 T' k. \input mcasp_ahclkx,
5 o* W' \* m/ o" S$ ^* pinput mcasp_aclkx,
. i8 z4 J4 G; j! Finput axr0,
( `" Z: T& p1 r  |+ X% }
( f9 p' u: X3 R2 Eoutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
% n) N* T, ^( L0 m' n# v5 [output axr1,
/ p2 m( I% {" o- x  C

assign mcasp_afsr = mcasp_afsx;
% l" \3 [+ q! _& ^) E+ I; V4 @assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
; m# x1 o% }' i9 [" V: t{
. a. i6 H( @2 p5 {8 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& a6 m* O) K8 x# r4 B; L  n2 ~McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
* E8 W# j6 ?; _2 O6 O9 aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 P! N2 W; L# c' w9 \2 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
. k2 }% H0 u( P/ x1 I& }6 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
- v* U# c! r6 [0 a* H1 P) E) N' L0 _; iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. c2 }7 b- M! \  @5 qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, F. w, M) x5 }8 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# R: r4 t5 `! P$ B- K0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! s/ K2 Y5 {5 Y* t* W* r7 [& ?0 G! HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! m5 ?2 y6 n# ?$ A, e0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
( G9 c1 t: v7 b6 XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 c& c# N5 ^4 X: p( I" f# V7 kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' ^6 q! Z5 {# N" gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
% U; ]" Z5 `/ J: }% N, C  p** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
2 o( `! k. o$ B4 G; v2 Z*/
( G! S. D. g4 eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
% c, W8 I+ d% m** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
8 D9 S: Z+ K5 `$ P% G. ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
* Z( k6 \& z4 h, a, Q$ }8 m| MCASP_PIN_AHCLKX
$ W- q6 a) g; m- w| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) U, t) \9 J9 i+ M. `| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: ^/ h9 J+ i4 K! k8 }; b& B) l| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
$ {% c2 a8 K9 `; y3 N5 n# _$ P| MCASP_RX_OVERRUN);
4 g$ b6 `+ v& \$ ]- f" t3 Y}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- Z! Z; J& G' ]7 y( R$ |7 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
, ^5 K2 g& E0 `+ Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% A* K4 ~0 _" KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 `, Q; Y1 D2 t- _}

) Q' {' g& \8 L. P3 _3 z5 G

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

/ M: V$ A) Y- O0 X0 U( c