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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 _6 k( o7 }' g; a( U0 xinput mcasp_ahclkx,# f; ^8 @% A; Y( s
input mcasp_aclkx,- |- ~4 y: n5 T( {- i* t/ R' S4 O/ Q1 u
input axr0,
- J, y& p, [+ I. ^" I# F! j/ [: @1 z1 P- Y- B+ ]$ v- [$ g$ N
output mcasp_afsr,
& h l. E' h; q( Zoutput mcasp_ahclkr,
8 ]. p: |# `: e8 }output mcasp_aclkr,8 r6 a& n3 M! m. h- E7 z! K
output axr1,$ @5 J5 `. ^, j- n
assign mcasp_afsr = mcasp_afsx;& v: b% ], }3 j
assign mcasp_aclkr = mcasp_aclkx;6 M: U! C! @# C4 O0 g# r3 u5 r2 ]+ e
assign mcasp_ahclkr = mcasp_ahclkx;$ H7 R. q9 t x
assign axr1 = axr0; 6 m' B, Y. x( r0 G j
3 @1 l/ ~8 ~2 P' \. `1 R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( X# R, G6 _: w: X' G* Vstatic void McASPI2SConfigure(void), M8 |/ n7 P$ j& }5 y' p: j) ?% ?# r
{7 U/ c& b/ W! s# B2 |" R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 B! o+ L1 d+ F. Y- I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& y9 q) s; y3 W( C1 G! ~# w" h# rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 D7 n2 f3 ^5 ~4 Z7 e {, c( R! rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ W" w7 ^* \6 L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" i" T6 ?$ ^1 M0 e- t$ P- L5 W8 fMCASP_RX_MODE_DMA);
/ M- \4 @6 D: n) s2 SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) Z' q+ V! Z" M: E, Y7 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 @, t5 F* I+ @( M" f1 t# m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) j" R: z& ~# L9 E. YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% c+ j5 y! G/ |9 l# L7 R* ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& d& Z( {+ r% `9 L& ~* fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ Z! I/ e5 R, J" `! O3 {9 C% p5 gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: N" b- k* f3 v2 @9 i5 N" U1 CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ]2 [1 K3 j2 m" C7 r; M+ U5 KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) B+ M! @, Q8 y5 t0x00, 0xFF); /* configure the clock for transmitter */
' f* J& H( Y: M) H1 E3 l: D2 DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: P& l8 _3 W4 @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 w! }4 R- ]- }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: j$ x: G2 x, ?) v( W' }% e
0x00, 0xFF);
5 U P. f, U! G- m6 L: x5 a9 j [
+ q" N: H$ J) R; ]+ }5 r/* Enable synchronization of RX and TX sections */
* P; }' M" F" d) e6 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 f- F8 W! S1 ]# `4 i: L7 |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% b3 z' d/ `! x1 ^7 }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 J. {" `# A. M+ b" x9 [** Set the serializers, Currently only one serializer is set as: d5 S9 w& |, z' ^( C) A+ v
** transmitter and one serializer as receiver.
' u# ~8 ]6 p- l+ o2 ?( d* q*/0 P, A# j# e7 {& c3 l, g; T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! P. l1 w; p+ a0 S* t XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 ~( m9 y" d: z: E2 a
** Configure the McASP pins 3 w1 U1 V5 k1 n$ K! O% U8 t d5 L- ]
** Input - Frame Sync, Clock and Serializer Rx
6 h m+ p6 H0 ~1 w; c8 O" u" z** Output - Serializer Tx is connected to the input of the codec . d, j) D/ x1 V2 }
*/
/ a0 j- u2 |# V0 a, a: wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 o& W4 o8 j' I7 F+ Z1 V/ n5 g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ V/ j4 P4 R6 r1 p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 }; r4 H, E/ ^5 C9 D$ `
| MCASP_PIN_ACLKX
# ]$ d: b: n ]: S9 z: h: a: || MCASP_PIN_AHCLKX
) N: O8 H& }$ E/ _! p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- v3 g# R$ o( @. N9 UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 ]9 D' p9 {: H' f| MCASP_TX_CLKFAIL
$ F5 T3 J" _5 i A8 i| MCASP_TX_SYNCERROR
" G' W7 A+ H6 ]8 d7 q& W/ Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % _. s( |& x8 i+ l
| MCASP_RX_CLKFAIL
; n7 A2 ^; i, z: X5 U| MCASP_RX_SYNCERROR , e5 ]$ ]. z6 m
| MCASP_RX_OVERRUN);
, l! ^' f) U% @3 L) { u1 T} static void I2SDataTxRxActivate(void)
* O) m; Y8 P1 D/ `{
- Q6 [$ B# P4 w; \: }1 K6 {6 C/* Start the clocks */& h0 B/ P; \8 p2 ~/ g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 @4 Q, V8 r! _- r# m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% s: N* U3 l" }: \' T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. }# z# A O# Z+ S, Q$ f/ d$ G
EDMA3_TRIG_MODE_EVENT);: z8 p6 _) W7 Y! d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 a& ^+ X7 |# \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 r w4 C; o; w: J, Z; aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 U7 w t* c" x. E0 J% ?! J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 c1 e; ]$ m' ]$ ~4 W+ w6 x1 z" twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: F* `7 p1 l. ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) o# Z# i% k( c+ C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ Q4 R j9 e. r8 v}
t% e1 R0 X$ v) T- v$ M Q, z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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