|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ e% _# S' K4 J3 V# R/ ~% linput mcasp_ahclkx,+ Q$ K+ P- n9 z5 ~9 J
input mcasp_aclkx,5 u8 B$ B- o" H# I5 ~* C( Z8 N8 q, x
input axr0,
- N& r) J- R( v, N
' T! R$ W# l! ~- O: goutput mcasp_afsr,
8 z0 T% e/ D8 p }0 | H Xoutput mcasp_ahclkr,
f; m, X) O+ C: n$ E2 loutput mcasp_aclkr,! [& P x1 p# [& P! E2 l5 @
output axr1,
8 H }0 t7 h& H2 b assign mcasp_afsr = mcasp_afsx;
8 `1 m& g( W+ j, sassign mcasp_aclkr = mcasp_aclkx;) g( C* a5 q+ o+ X2 S
assign mcasp_ahclkr = mcasp_ahclkx;# w* w- p, f2 u" T
assign axr1 = axr0;
8 y/ K! `' c+ I6 W5 w
1 X, W) f; c" s8 G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( X6 T% ]( ^& C# M$ F2 ?$ E$ jstatic void McASPI2SConfigure(void)
; G) i4 P, S0 @) k# V2 P+ ~; T. y{6 U! L8 y4 V; D+ K7 t3 w% W; N/ j" |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 n7 ?7 X; W, R. pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 s) G' h) G( B& c1 f4 J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' r9 R6 T% t& @8 [. ]) d6 i4 aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ `5 Y' {( e3 G+ `7 j# dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 f, ^1 V# k# M6 A! F; d
MCASP_RX_MODE_DMA);6 C! E& t" M* L. W; [/ P$ j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, G! {3 \& Q. r& \6 q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; U; ^0 W# E4 v F& E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 @1 B& b2 i& |1 K* s% @, o/ XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ B" L* [& N8 U2 i' w* a3 i( `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" d: o; ~, M# a" y1 { R. X" l$ yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 k5 c' W1 i/ c3 b' FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 a- O$ Z: Z4 T8 q' `. q0 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 M0 J, T9 U' H8 W( _! e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 U: O6 k* r9 |3 i& A1 X- D6 z7 u
0x00, 0xFF); /* configure the clock for transmitter */% W* ?# z' H/ n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 ~( h) e4 i# r2 A) Q% o( _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & G4 `/ J) [# Q Q+ |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; s' {( |* ]$ P
0x00, 0xFF);' z7 E2 @9 y9 z) `8 M9 C1 O
+ p3 m; n, f+ U1 o; a3 g5 Q
/* Enable synchronization of RX and TX sections */ 2 R- O' G3 X& `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# F: @' M/ x0 T* z4 o' X( o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; i8 b; B: z/ _: {3 X: AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' I- r ?* a+ @+ N2 O8 h3 K** Set the serializers, Currently only one serializer is set as
d E, [0 p4 E1 L** transmitter and one serializer as receiver." @; u9 Y0 h6 X. \
*/
- G# v$ z0 H1 L# |3 AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# V+ M+ W% s# H; ]# C. nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! A5 F9 w1 r0 m3 b
** Configure the McASP pins
- m, _8 T1 Q& Z& G& e2 e; G) }** Input - Frame Sync, Clock and Serializer Rx3 v3 d, B ?7 `1 [* {+ Q
** Output - Serializer Tx is connected to the input of the codec * K& F1 X* \' r8 D1 b9 C V1 W* m
*/- C; d G" n! t4 g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; O6 x" s- b7 n6 jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% Z- `& M6 j. O$ |* w* fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) R1 i; S. q! S0 i6 R| MCASP_PIN_ACLKX
$ n% L+ w$ M3 O$ s7 l; J| MCASP_PIN_AHCLKX" Z9 F* U m, L' _" M5 V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ s# ?3 @1 E* @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* T/ l2 t% `! b+ k4 o8 _+ v" Q| MCASP_TX_CLKFAIL
5 s$ R1 q! ]/ C$ t1 k# z# w( s0 || MCASP_TX_SYNCERROR; V# p+ i+ s' a# m% M4 W9 I# B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - S0 X5 V0 u+ U" Z* b1 i t; x7 w
| MCASP_RX_CLKFAIL
* y& X' ^' ^+ u1 f| MCASP_RX_SYNCERROR
1 l/ t# k# X- l# v| MCASP_RX_OVERRUN);1 ^/ J; _' }0 U, W$ `$ \
} static void I2SDataTxRxActivate(void)
5 p8 m6 r d, h5 R{
( k2 B. E, _+ L9 o3 l* Y( P3 M* X/* Start the clocks */& } a6 r" J! K4 M8 E9 s8 y5 K3 D ?0 f6 f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! ~ @( _/ C" @5 c2 b4 h: ]: A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" e! A- o3 R- pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* c5 \, L" \5 W0 P. g; jEDMA3_TRIG_MODE_EVENT);
?6 M$ j. @( j) PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 z+ o$ I4 b8 y% I. a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 a4 V+ w' y8 o; M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* p7 o t" B0 E( F* ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ G$ X: I. G- u/ [) V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: u& ]1 S6 A& ?2 h+ N! qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 n: ^+ V9 w3 }$ [" l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 t0 s/ g. R% }2 ]7 f} : H$ I9 W1 w- f) o" \7 r, T( S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 {3 p/ F; H" o7 I, t* W6 t
|