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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% X/ T% K& n: W @input mcasp_ahclkx,
' V1 A5 v" m+ w5 Linput mcasp_aclkx,
) h1 F% G2 k( E* F6 Binput axr0,7 H j, l9 U' t% z( j- ]- R( D/ D
3 Q/ d0 @8 x9 G1 eoutput mcasp_afsr,
# @* W' |9 E7 P2 r5 d1 ^* Poutput mcasp_ahclkr,
$ D0 w) D0 u8 e6 K9 zoutput mcasp_aclkr,2 l" O* G1 I. r3 |% D) j
output axr1,
9 X( }+ C, ^& L2 _" [! J V) _ assign mcasp_afsr = mcasp_afsx;4 a. Y( J# ~, H/ k; }
assign mcasp_aclkr = mcasp_aclkx;
' p; d. {3 K! {: E9 u) R. `assign mcasp_ahclkr = mcasp_ahclkx;! D% k* Z' e) |3 U! e
assign axr1 = axr0; # O% B. ^) I2 B! {1 h
# S- p7 T/ s4 E1 K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # } H! h$ i( H1 c/ m! S) Z
static void McASPI2SConfigure(void)+ V0 _6 n- ?! e) I1 O
{
* c6 w- K" g b, ~8 uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
C" b. }) W9 i, K; f, IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 e, G$ N% x+ V9 _- HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) D# q! d. e) iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# C0 Z$ R9 R4 k3 G/ Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 n, e( D1 M& f
MCASP_RX_MODE_DMA);
1 I8 p- g8 E. k; |: S: A5 E* [- W: I; s9 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 U8 ^- \- v* Q% h2 BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 h" I, Z4 W" u; K" F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( q" Y) d- M- Z. RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# T2 ` }- U# c! }, I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . V- u( y0 k5 r- V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 d! H3 e" W, n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% h' \4 f3 b) U! T- M" H- B6 hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! T& J S; y& [& E' o5 r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 Z y! i- L( [. H5 t; J0x00, 0xFF); /* configure the clock for transmitter */ M; M+ c$ S! G. y5 E7 `3 _6 R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 z+ N: b4 m4 O. Z* |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 i7 K# r6 q( k5 I+ }% y9 vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* q4 d6 j; G8 r5 A: L9 W2 |
0x00, 0xFF);: | Y$ l% c, v* a4 y
$ R8 M6 B, g! H1 U" `
/* Enable synchronization of RX and TX sections */
# v2 \# `4 h2 Z/ TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* T6 u* [- j! A4 kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ z' k7 P2 m$ o8 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** F; K) m/ a, o( [& e6 g1 F
** Set the serializers, Currently only one serializer is set as
' u+ T) J$ a! `) C0 k** transmitter and one serializer as receiver.
" K# l* x' ]8 O- B4 h( B" b*/6 w& k, \% _. i5 I' @; y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' A2 |' [: g( ]5 `% y" H2 e, D" oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** C- [4 O4 n1 |! p9 H
** Configure the McASP pins / u2 K: G' T: Y0 i6 n6 J: }
** Input - Frame Sync, Clock and Serializer Rx
% j3 {9 y( o1 H** Output - Serializer Tx is connected to the input of the codec
0 S& g- S/ t/ r6 O*/9 c1 k" b% m) K( |- I9 s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 L/ P8 t9 s9 G6 a# \( X" r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 L5 @, C; {6 u& a- t+ [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& E* r: |) @: C& `| MCASP_PIN_ACLKX
( Q$ |7 d o. f& j| MCASP_PIN_AHCLKX
k3 l2 \4 J: a$ J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' z: Q- r# @1 f# H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 Q/ j2 `' i+ m4 ?$ F" w
| MCASP_TX_CLKFAIL 9 a' G. }, V, `% T/ F9 b3 X: t
| MCASP_TX_SYNCERROR6 o4 f* q4 x3 H) c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 {; ?1 k! X5 A; I! u
| MCASP_RX_CLKFAIL
: l* r2 F, g8 E2 |4 y; k+ i| MCASP_RX_SYNCERROR
1 P1 p6 P( B% B7 }! U8 I; m' o| MCASP_RX_OVERRUN);
" k2 }( P+ A7 w* T2 X} static void I2SDataTxRxActivate(void)
% w' z5 E8 w$ F1 U* E{) b* m$ P/ J/ A
/* Start the clocks */
# S5 \: l+ z+ J3 dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- Y: T0 z7 ~$ U: v8 j' a2 S1 g5 IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' {) `" F: L$ a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 _' E5 J! e6 y/ s( ?EDMA3_TRIG_MODE_EVENT);. N1 v1 E5 F: r1 t" O3 x- o) j$ _5 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, B' N9 o# C g- a! G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ K% B' W7 `% o J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 b0 [4 e: w8 @2 e" b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" t% l6 v$ v" U1 p3 w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" y+ c$ s" n9 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 h# u; q% M5 Z$ N4 W& ~3 z( rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( D8 M [4 B- Q' L2 _: {}
1 s6 x( H9 G% X, \4 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ i9 E, u, S" g2 v
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