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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. l: ~! b/ a# oinput mcasp_ahclkx,
, y' l3 V" v1 c; Ainput mcasp_aclkx,7 g z4 f5 ^ z+ b2 B$ P
input axr0,
7 `6 l: S/ b& P X6 _" O: z) j$ E
5 {& S; l- a' Q4 ? D( ~4 A0 goutput mcasp_afsr,
8 T; C' F3 a5 c+ Qoutput mcasp_ahclkr,0 a0 t# A7 R; S% R+ P. r0 z7 K
output mcasp_aclkr,
3 Q1 S& b, E- _$ M/ s3 l/ Zoutput axr1,$ W4 G3 w; v9 C! ^0 D
assign mcasp_afsr = mcasp_afsx;
' m) E# O- ~7 f2 b# d3 kassign mcasp_aclkr = mcasp_aclkx;
; N! O' C. K' lassign mcasp_ahclkr = mcasp_ahclkx;
8 h% T5 l/ i% z# @6 G! Wassign axr1 = axr0; 0 i, m+ q) U1 h% _2 C
3 }; V. L+ z5 {6 R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( j* Z/ R. {, U2 Pstatic void McASPI2SConfigure(void)1 B/ z d: e5 |$ Q
{2 m) K* y! q- L! v7 _7 O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( E" V/ J, R% j- V: P: I) |# g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ o1 o7 G2 c B5 Z; ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( y: r3 R2 ~0 q4 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. h; K) ?6 R, d6 g8 m6 K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# Y/ q4 o2 a( _7 {& }8 d9 V0 D/ A
MCASP_RX_MODE_DMA);* f# v9 y; D! D' b& R! y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ L4 ?1 T) ]+ x6 Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( M; P' S2 V3 m3 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % u# `6 G6 ]: `; @& l; G# T6 \! D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 P; R/ x6 P! K) `7 N4 e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 s* [7 n0 t. WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// F _$ F9 W$ Z/ S( z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' N& H; S; g, [( m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 ?' s! N( U# A5 B* a; |# I; v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- L( E1 j7 a7 U5 d7 N9 g/ [0x00, 0xFF); /* configure the clock for transmitter */
" U: _+ O( ]* g; ~+ q( z1 DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, L/ k4 Z- A6 `1 s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 |$ h; y+ p; k0 s! ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* J' L9 G8 W% T0 z$ M0x00, 0xFF);( L. {" o; Q- \/ L& P8 E
4 |* X2 p7 d5 R3 V$ t
/* Enable synchronization of RX and TX sections */ 2 _6 K) F* v5 ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 H$ S6 v+ ]! d+ D/ T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, J8 S; J. c) o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 Y5 l$ v& @; y$ {- V$ l; n3 Q2 o** Set the serializers, Currently only one serializer is set as
2 Y" E/ J" N$ \% c, h** transmitter and one serializer as receiver.: V4 t# ?5 g. L) R- n" G: L' ]+ B
*/
u- m8 g, X6 {4 K6 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 q! z7 d1 O6 h" n/ t9 o# a8 ^& s. c( Q/ a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 C; Z- P8 T% b$ x$ g( A+ Z7 o
** Configure the McASP pins ; ^2 j1 }' }/ F" e; P
** Input - Frame Sync, Clock and Serializer Rx$ o, G) e* I# I& `7 ~: x0 {, R/ |
** Output - Serializer Tx is connected to the input of the codec
- Y3 o, z& D. V/ a( S, k*/+ V% ~* e4 B; s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# D) U7 r$ M S+ |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- d( G2 k# t3 |0 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( i1 W; @9 p) K6 ~
| MCASP_PIN_ACLKX
( T1 L( j+ x1 |- t* i2 H| MCASP_PIN_AHCLKX5 l/ f0 S: X- S; @1 C% I4 U0 T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# t U2 Q2 m2 n XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : N: f- t& G! d+ k1 c
| MCASP_TX_CLKFAIL
3 [9 @3 q% H" P3 A. d( ~9 f| MCASP_TX_SYNCERROR
0 I& |5 S8 w, q% \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) d6 D) K, G9 O" k _/ V: s
| MCASP_RX_CLKFAIL6 O8 X' E6 N# V2 E* R0 I6 v& m
| MCASP_RX_SYNCERROR 5 ^ Q- w+ o4 z4 V% b
| MCASP_RX_OVERRUN);3 E: [2 L H( G9 V% p7 I
} static void I2SDataTxRxActivate(void)
6 ~8 I8 G; d/ z6 h{
2 u) m- b0 U2 }* f: U6 O2 ^/* Start the clocks */
7 @6 D& M3 a3 ?! `0 r4 J8 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: q k& [- r$ m9 X# yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: `3 q- I7 p* i' V+ pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' s8 f- t/ p% U. Y! e. a) e+ iEDMA3_TRIG_MODE_EVENT);
/ [& u. ^8 u$ W6 c6 `9 [3 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / p6 Q/ i4 ? O% W! j( Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- A6 H5 S# h9 G9 V* X, l1 t3 u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" X, ?7 a# M$ g5 I; S1 }) \$ kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 p; z Y; A( w1 ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ Z' ^2 Q6 G( u v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) k# j0 q5 c D( LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 L! O; q8 @ t
}
. n5 z8 e! A% ]3 v8 m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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