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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* G+ T7 g& A" F
input mcasp_ahclkx,
3 [0 O$ L3 g9 c! m& i; I: [3 e" Oinput mcasp_aclkx,
" B2 k I7 l% k% V+ E5 ninput axr0,' k/ \! }+ Z/ `7 m
) i( X) J5 B$ N9 M% n! T; F& L. Uoutput mcasp_afsr,3 O' E4 D) f4 ~$ I
output mcasp_ahclkr,$ J5 N/ y" M2 O. k# g/ e3 G0 m
output mcasp_aclkr,: ]- `- ]( ?* B1 S- N5 d. E7 q
output axr1,
5 g8 f; h4 z ^8 a% v assign mcasp_afsr = mcasp_afsx;
* C# D6 m7 t: k# y- ~7 x7 oassign mcasp_aclkr = mcasp_aclkx;
6 m1 B* H8 d# O1 B, x1 b3 ]assign mcasp_ahclkr = mcasp_ahclkx;
; q; T0 Z" H5 Rassign axr1 = axr0;
1 R7 \' B+ ?5 w" D Q+ j
4 D6 Z/ Z5 s$ K+ q6 a4 _: |) ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" _% Y# I- O+ ?% Y9 zstatic void McASPI2SConfigure(void)
' A* R; W& T) W: p8 |3 h{
) B% d+ L0 q& JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ S) ]4 R+ g! SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% P5 J2 i0 X5 d) j' Q# O% s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 m2 R% p7 F0 S0 R" l: vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' z" | ?# j9 N4 F! b" d# T8 `5 ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 J! r; [+ [5 N) J: E
MCASP_RX_MODE_DMA);) I* H& V; c3 n6 j9 J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 w$ } ?" A) P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 m! _; A- t' [% x, PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 A; `7 C1 T9 i! kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. L: }7 o) | S& J. pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: W N8 K4 N) I( r; }+ lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( ^* v2 E1 b8 w$ `1 M" ^; L: NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( p( ]" K' u- Q4 [+ j7 L% Y& Q# U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); E7 i6 w! p1 c4 T# F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: J; |/ z0 t* T) y. v0x00, 0xFF); /* configure the clock for transmitter */- v$ E9 T7 T7 M4 J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) L0 C2 W! \7 X& [) ^2 m" s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 e4 c0 X, r6 O% G# D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," g% E2 u9 L; S' q7 h: y2 U7 q
0x00, 0xFF);
, A- q- X$ K1 H5 c* m
' _$ ]5 k9 A$ `* n' G8 t/* Enable synchronization of RX and TX sections */ , a! q- y: g! f; ]+ E: O7 R/ I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 r8 M; g8 S. P. z$ l: b# yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# \, K' f& b) w1 F; L- d# IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- ?: _" s+ Q z$ \# H
** Set the serializers, Currently only one serializer is set as3 A- |7 I, u9 Z9 H1 Z8 V
** transmitter and one serializer as receiver.
! |0 k8 N/ n2 `$ S" u6 N9 \*/
5 ], v, @& R) F/ lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 \6 P5 L8 R7 R) @. D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; x7 @# F3 O g( x& x8 m# z
** Configure the McASP pins
, ^) K% \1 L2 Z7 }) C** Input - Frame Sync, Clock and Serializer Rx) D5 N6 P. ?8 `
** Output - Serializer Tx is connected to the input of the codec
/ K# ^0 h9 R& Y/ B6 ?: B+ @*/% x1 [( X( t/ k4 x9 ^# G, j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ Z) v+ r- \7 @" V8 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ e0 R1 W" J/ B. GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* B* \' ^: ^- r3 d. G) S- {) j& u| MCASP_PIN_ACLKX9 r H T7 _4 r9 H) |2 {, B' c
| MCASP_PIN_AHCLKX
4 I& s% X5 b$ ~, F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 T% g/ z3 Z5 _: G8 rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: X5 b) D _% H! R3 R+ n3 G6 H4 [. q| MCASP_TX_CLKFAIL
* ?) I# ~: H% u- l| MCASP_TX_SYNCERROR* y- U8 L2 Q+ I+ h" m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 J5 b8 B" M+ j) S
| MCASP_RX_CLKFAIL
( S$ Q) ~9 ]1 _| MCASP_RX_SYNCERROR ' d3 W. {5 n# ]2 _: g
| MCASP_RX_OVERRUN);: a# F2 V* N! |2 O3 L6 b- _9 u+ J9 |
} static void I2SDataTxRxActivate(void)
2 l: V% I- s3 U- a; D t{6 o! ~; c" ~: e+ Z6 q% s
/* Start the clocks */: [; _ [% n- i/ B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 e0 J. u" Z. X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 i! ^. r o3 O" X9 x7 N) o' U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ Q1 o+ |5 O/ K6 D% \$ `, B' D
EDMA3_TRIG_MODE_EVENT);8 C* |& l3 Q+ C1 b7 E: [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / o ^) U; j g0 q% _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 r1 j3 S" j7 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- Q2 C5 X0 u! j+ x4 y! Y& r0 p- ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 v& g1 r. |! d: A: k( J4 zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' s& g8 y% X9 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); D( Y8 K6 |0 c4 ~7 s$ x9 t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) l3 U! E) V" J}
& A I* w& D0 o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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