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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ @ \8 R, F9 U) |5 Z
input mcasp_ahclkx,6 \& o9 p$ B6 s3 ?: k# Q( A0 }
input mcasp_aclkx,
! A4 G$ P/ u9 `) }( j2 v" uinput axr0,
+ s- j# l) S. ?7 u3 W( _' b J' b+ m! \9 o, o! e
output mcasp_afsr,
' O# z0 E1 i1 routput mcasp_ahclkr,
8 k c1 P/ M/ woutput mcasp_aclkr,
0 B" R8 D) {' ioutput axr1,& Q! b4 `+ p) s# r7 e4 `# z4 h1 O
assign mcasp_afsr = mcasp_afsx;
3 h+ V8 P$ R6 c" F/ Zassign mcasp_aclkr = mcasp_aclkx;( B( Y- a6 P, j
assign mcasp_ahclkr = mcasp_ahclkx;
% r+ i' b' B; l/ ^8 ~assign axr1 = axr0;
% H; M3 J) m3 K; I0 e) z
7 ~' P# G* [( I/ u0 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , @ m9 i$ P8 L W8 U5 i
static void McASPI2SConfigure(void)
7 }/ m. H+ X ~ x2 h! e! C! t{. c2 D4 b- |8 _8 x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( e& R8 G2 q6 m/ Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 I0 [8 A- ?' i! L! n# `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" R& X X! V7 j2 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* e0 o8 ]# L, G' b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' B" ]2 ^, y3 ]) I7 V+ _( D
MCASP_RX_MODE_DMA);
( J. x3 a% o& K; [3 {, mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& J! u' J+ \( V8 f# p, D$ HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. E2 g) E$ P9 T9 K" U( u4 m+ P% D( ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: _( ]5 D5 c& A. XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ j4 t! A6 o8 K i/ z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) |& S& K1 x! m2 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ s+ n0 z) W9 F1 }& ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& E+ h; |6 e* g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " I* t1 `/ a' C# z+ v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* x+ |, `# q8 J6 V( L g5 u
0x00, 0xFF); /* configure the clock for transmitter */
$ @# ~8 q. S/ v! yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 V, r; V% l" S+ U5 ]) a/ DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) [7 `0 n/ N6 C7 `: q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* u9 a) o2 ~2 g8 w+ k D
0x00, 0xFF);
' r2 y& t# @3 X7 w& w6 c6 c! T7 m$ {: z( J( x. M
/* Enable synchronization of RX and TX sections */ % F6 O! K, b5 ?$ d4 K" c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 s; I: N- n/ UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ L5 j2 B. C, c, _; w7 b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( x9 u7 N8 X& t: t$ a W- A h
** Set the serializers, Currently only one serializer is set as4 k' I2 Z* X. T
** transmitter and one serializer as receiver.. h" e1 p9 o( N. D$ p
*/+ M# V$ E- I* P4 \9 Y2 g9 y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 j8 v0 H3 i4 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. C5 o2 O( v6 Y** Configure the McASP pins
" p) j6 z2 `# B" t4 q** Input - Frame Sync, Clock and Serializer Rx
- t+ P9 u/ j& p2 {) ^: f; B: E3 J** Output - Serializer Tx is connected to the input of the codec
1 {# Y& E: N ]*/' [( {5 M# o) t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& z* l+ ?' f+ u1 _$ L, s. u3 vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- M0 w0 r& b2 f9 f; ~0 O4 q- |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 O2 ^( [7 p2 ]" @2 Z$ A# V| MCASP_PIN_ACLKX
+ r/ v, h/ B6 _- B1 |! I; k| MCASP_PIN_AHCLKX: p F* S$ k' t( o/ L0 a1 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 W, m3 Y. D k, K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& }: M" v) U0 m* v- K; ?2 l| MCASP_TX_CLKFAIL
4 i$ t2 T! Q8 s4 |# d| MCASP_TX_SYNCERROR6 j8 o4 w& |- _# C1 j I0 U) f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 V7 k# D7 X5 I* Q4 i* K* B! |
| MCASP_RX_CLKFAIL4 c, Z: F$ e' k' U
| MCASP_RX_SYNCERROR , J: o. C" L2 D
| MCASP_RX_OVERRUN);8 d! [: k- @% c1 P% U
} static void I2SDataTxRxActivate(void)9 W: Z, G7 b0 M0 L* M# l5 n: R' S
{
5 t1 V; H) F" U! [0 r/* Start the clocks */. R9 H: P+ n4 I, q5 U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ d- t$ ^& I3 B' m& q' S( H+ {- R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 O. w: M5 ?9 U: REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
^, W7 S7 E z: {/ VEDMA3_TRIG_MODE_EVENT);
! M+ W4 D* p5 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' l5 N' Y: t5 z$ @/ D/ P9 z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 ^! m+ E8 D3 |! y: hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 c! c& j4 i- y# C/ h) i- o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" k. a1 A# _& R2 u) |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# G \& N' z! P# E6 I7 Q, ^1 Y" iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 q4 v$ u. y! ~" t) {1 W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 O+ I& f! o8 U `% ^4 l/ x
} " ^ `! G' ~. \9 C; ~; w! f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 C# q0 p/ K; }+ }1 E) o
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