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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& ~, l% {. q. }* d
input mcasp_ahclkx,. T$ J) r, f! a5 `. H( c
input mcasp_aclkx,4 k4 q' u# D5 k8 N$ A8 L: t
input axr0,: K, E- ^ ?! n; q# q2 a* [
- a+ ~% H6 w" n( y* \output mcasp_afsr,
- U$ b7 `) g2 A5 t- O& Youtput mcasp_ahclkr,
: s7 E8 a/ D5 a' goutput mcasp_aclkr,$ i# A) O) X: b, w
output axr1,; I! n+ T$ } E. l+ }
assign mcasp_afsr = mcasp_afsx;
, ? v5 d( Y! W& ]& v" t# [) `assign mcasp_aclkr = mcasp_aclkx;! ]( F$ a1 \' L* u( r d1 G
assign mcasp_ahclkr = mcasp_ahclkx;6 L+ h( N+ ^+ m( o+ q: ]) s
assign axr1 = axr0; - V# V: r" \) p/ q/ b: ^( d
* v+ A& ?, C8 ^9 s! t2 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. L( y$ e% _$ R: b- W! Xstatic void McASPI2SConfigure(void)" f% |+ r8 Z2 f/ L1 z
{
+ Y4 u. M8 F7 k! uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 G2 s- j3 c Q! F' W5 c; T+ dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 c* i- W5 H6 L* D) w i/ _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, r# Z* j% I+ H' ~6 }) w& g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ F3 G% y _6 v/ J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. ~6 a% l- `2 a$ C2 N
MCASP_RX_MODE_DMA);
. f: m$ e6 Q5 ~( o( {" `$ X( _/ ?- hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ c. J: ]. ^' @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* m, m: g! B, X, h, i4 h# y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
x2 ?9 a/ l" a' L& C; JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) V+ y& ^$ n- ` v) }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* L# Z v" @$ z( ]& N: Y: RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( a5 c& h1 h9 f2 o/ ]+ n0 LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ N1 m2 E0 q/ G; |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 Q& l0 A+ B/ t6 J# |) [8 |5 t/ v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 Z# }0 E+ M A& V0x00, 0xFF); /* configure the clock for transmitter */( A T$ |. ~1 g% T/ P6 D7 {+ p+ E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 W- y% D: \; T: t {* b, W: sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . D0 t/ [. o1 z& {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, \) I: b3 e& u/ k/ K6 ]
0x00, 0xFF);$ U8 U6 T, b7 j* y0 k( h
$ I% z. X9 B' A9 t9 n/* Enable synchronization of RX and TX sections */ ! x" c) _3 s, O) e9 { _7 `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
m; g# z- [8 v: ~# h! ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 S. B5 s5 a! n) T0 e- i5 v( z( q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
^. V7 M/ M U _** Set the serializers, Currently only one serializer is set as( U$ |* V& O" f* b0 ?: z8 G
** transmitter and one serializer as receiver.
0 t* G! w1 ]: d' c1 p*/
5 @1 W3 d X& t0 ^) b) O* `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
K% a% v/ x" g; QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( q' g( e i7 f/ N& m** Configure the McASP pins # ?! D9 ^8 _' u3 G/ V+ B& {4 m2 B
** Input - Frame Sync, Clock and Serializer Rx6 M. s8 m2 K% z* `
** Output - Serializer Tx is connected to the input of the codec 4 { I( [3 [7 J
*/3 Z3 \0 M I7 C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ h& r% ?, Z8 w! }. yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
] f7 b( s* P7 L& f: ^- K( AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 t5 o1 Z: k8 a# s5 m
| MCASP_PIN_ACLKX; R" |# n; p2 F: P, M: p0 }
| MCASP_PIN_AHCLKX
- P. B0 f4 Z# M- m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# K( |7 S" o' ~. @1 q5 B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, h) O0 r7 O6 z| MCASP_TX_CLKFAIL
5 }& p( l, k: F$ V| MCASP_TX_SYNCERROR
/ T( u4 s2 d+ C; T% d* ~/ e! _" @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & G& F1 ?! q% Z& {' A# Q
| MCASP_RX_CLKFAIL6 I$ i, b6 O2 t' J) ]9 l+ [
| MCASP_RX_SYNCERROR ; a; n' ~7 B' M% }, m2 X
| MCASP_RX_OVERRUN);4 M. E9 Z4 Q! V( H) _, a5 b/ p
} static void I2SDataTxRxActivate(void): H" z9 e& c8 i( Y
{
; @- L+ q0 n0 T0 ]2 b/* Start the clocks */9 W5 O, S7 V4 J* q2 q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 l% F8 y: S8 i2 p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// P3 Q3 N' h$ B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# b2 N0 n8 ?1 v2 H( U7 ^6 qEDMA3_TRIG_MODE_EVENT);, p/ e3 ^! a+ T2 o! P7 t- x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 ? W; C/ k8 I) v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 z% [' u/ D2 i/ U# _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ s( n/ I& g) j' Q8 O$ hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) E) B M& p' A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) f3 K( q$ T& B5 A# Q$ X% \- E5 c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 J( F9 x) @ a, c! C$ K0 i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* ~+ o) p, c6 V' d' j* p3 p
} 2 H7 l) n f1 e( g, E( N2 }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 A- X* ]- _; h7 w7 D4 K5 X* ?
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