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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- }. |$ Q% W8 { L- k
input mcasp_ahclkx,
6 l& U3 b( h2 n4 u0 M0 b7 D2 Pinput mcasp_aclkx,$ R% {1 f7 X% L0 q$ \
input axr0,( F8 z8 B6 Y, q$ C g {
& t: g% Z) G7 u
output mcasp_afsr,
! K8 @3 a* g$ l0 @& koutput mcasp_ahclkr,
9 t/ ]9 N9 Q) a; x; zoutput mcasp_aclkr,
& M4 b0 |, h" D' Z1 Y9 Ooutput axr1,. q- H$ ?2 o+ w! b# C1 R/ f5 E* W
assign mcasp_afsr = mcasp_afsx;
3 t ~+ ?/ Y5 } fassign mcasp_aclkr = mcasp_aclkx;8 ?3 L. n$ u7 f6 l2 S, N5 i
assign mcasp_ahclkr = mcasp_ahclkx;* K& n- y0 z. V. R
assign axr1 = axr0; , A& `, V' Y+ f: J2 n
! s P' \& X3 }1 x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 [. f9 B. n q0 d3 a6 z$ Z
static void McASPI2SConfigure(void)
; F! z) C5 H2 V3 d9 Q( R! I{
- T, N0 n+ B. @& BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 m( E0 D& g+ L+ z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ p+ |: Y" \+ u& XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ @' ? k7 i+ s8 O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& b" h$ B/ S- o) j# ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( S, n# f& A8 u# eMCASP_RX_MODE_DMA);' G0 s l }4 f& x# B3 N& j `' O, z4 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 D$ `4 T( Q7 P! w, B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' {" n/ I2 b( a. m- F6 t- L8 Z. ^% i9 {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 n# n6 f0 q! w6 U; d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: ]/ R6 ?6 t6 F( y! G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) f1 ^* Q1 n5 x/ b; p, D0 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 g g" P/ h; B$ Z$ Q& HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ J1 B# t) o$ ]& Q R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 z+ Q, e9 S% X0 `: [# T. e A( sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 G0 ?3 t% r9 a. I
0x00, 0xFF); /* configure the clock for transmitter */) x3 U' \6 T6 ^$ D: }2 x0 W5 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 k$ u0 D. @( c* ^8 K) `# n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( I; a* _1 F$ U0 F, P1 ^# }8 \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: g6 n. `! L; I' Q5 r& ]9 _% f0 T' G: m0x00, 0xFF);
: y0 j, h( L6 W) Y/ j9 ?/ g# C( j6 k2 r3 C6 |
/* Enable synchronization of RX and TX sections */ 3 C1 w. P8 k2 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" t% h- p' x7 f/ ?3 PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' a- F) `0 T" ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" a+ X% q: C: K' a) z6 C
** Set the serializers, Currently only one serializer is set as( Z" V; k7 ~0 ?
** transmitter and one serializer as receiver.
1 }3 L4 y$ y& W$ [1 f1 ?*/: O' B0 Q) a/ q u& |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) E5 }6 `0 X) @0 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! S# n6 R8 n8 v; K' y** Configure the McASP pins
( H& A" z4 c' I1 P0 k" k P** Input - Frame Sync, Clock and Serializer Rx$ }3 L% z5 M$ F5 n( ~$ E" q" [2 F
** Output - Serializer Tx is connected to the input of the codec ! D c: U& r. g! X& L; S
*/
4 i. B* T% p0 ~" O" p+ sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 f* a. ? x, I6 `4 \: e! {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 }9 f: z% m2 Z# Q1 `+ U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* J. a$ l7 F' o$ V: R
| MCASP_PIN_ACLKX
7 C' Q z- G% H" x( {/ z| MCASP_PIN_AHCLKX
) S$ j" N6 `9 p+ |. P7 m) V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: k7 U" D2 u3 b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 W7 q. l" P' ^1 S/ g1 K1 v| MCASP_TX_CLKFAIL 6 l3 r8 N' u: G. a6 Z) w1 k/ y6 i- e
| MCASP_TX_SYNCERROR
. J7 c0 G, Q1 t- x5 p2 \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ a. ?* _9 |/ X8 k) O0 D
| MCASP_RX_CLKFAIL
" }! \ T$ C# i# _: ]# ?| MCASP_RX_SYNCERROR * z* J4 u6 a7 D* I3 b
| MCASP_RX_OVERRUN);; @' b; m8 S; J% U
} static void I2SDataTxRxActivate(void)
4 e. v( g. r! d) U1 E) n{ C; _* |- G9 }8 @3 g
/* Start the clocks */ H% k' s, [, j9 P3 ]; [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 d1 ]* G4 X6 E. t2 A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 }/ y5 ~/ j }" i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 [3 |$ {6 d3 |
EDMA3_TRIG_MODE_EVENT);# k3 D5 x* L( ^) m9 t3 \, m- p0 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! @% C$ e8 n$ O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; P% w- {8 K4 ?' HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 J7 |9 [, N% b0 Q* E& M2 C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 l- W8 T. X7 G: ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 }6 s5 s/ U9 D# |% l4 U5 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* @4 e" D$ p4 H: ?9 b' }& @) |2 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, P/ h( C2 o. m6 t( l: n; M
}
3 f/ }9 u4 H. X9 \( I+ [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # n+ f! z6 N4 W; r1 i! ?
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