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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& ?; r& _# B( |
input mcasp_ahclkx,
A6 G; l8 ]/ Q2 }9 yinput mcasp_aclkx,4 s" d) ^$ @- A" z; L2 @: }
input axr0,+ ?6 A1 Y+ J4 r2 L' L# t- i& U- H/ V
9 o! W8 T: x+ U; i9 }
output mcasp_afsr,# F* U1 w% l- T, `7 {
output mcasp_ahclkr,# S3 Y* e4 s0 p" k) @- z
output mcasp_aclkr,
% t8 l( T3 q2 p" {output axr1,7 J5 \' s, w: H" |- T3 A
assign mcasp_afsr = mcasp_afsx; s( ~+ w# W4 f; h8 v
assign mcasp_aclkr = mcasp_aclkx;
' G" G7 k8 ^" Hassign mcasp_ahclkr = mcasp_ahclkx;
' r) m# y( T. X# D. d7 v- @5 V+ Xassign axr1 = axr0;
8 G5 o! o3 g+ j" ~6 N% p6 E4 @- y6 l- X! E& |& t* R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 s* ~/ B ?8 h8 T" \static void McASPI2SConfigure(void)0 M C% R7 J+ a9 z8 |$ `: w
{# `" ^) A, ~* p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ ?& Z# {" c( V* Z2 d6 D2 GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, _- B3 O" n* v8 Z8 e. N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: I& \/ O4 D( o9 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* \3 u% w& N' Z5 o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- W$ {( `6 m1 t8 F& ~MCASP_RX_MODE_DMA);7 `3 s, `4 T: U* a; Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- R4 E( C( i8 C: f% ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# o3 V# N/ I0 h; V8 ~$ Q3 U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 d% S( x9 Y3 c( d4 Z4 \$ t) f0 G# U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 O% [2 v5 ]: u4 c; mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 M( T1 B x6 @0 ]; R3 b$ d& t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% b/ u0 K; }5 Q1 d+ z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; ~9 O2 u( E. K9 BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! `; B# ^/ r0 T' R" ~( `3 a0 g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& x$ \7 e% s5 l C2 U8 x7 d4 y0x00, 0xFF); /* configure the clock for transmitter */. [. `/ G: g2 H5 M! I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
q; I7 F# U4 ^# J0 U/ q: R1 G, C5 JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 ~* H6 v4 a8 A( q$ ~ h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& B- r5 y' x& |; x% Q* N0x00, 0xFF);" O% q4 A* T) j3 D8 V
# ~! i! @5 v2 f5 p
/* Enable synchronization of RX and TX sections */
" p4 A. o8 E4 E# A) S7 s2 I/ X& CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 P' |% y. H0 I; W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' k/ Z" Y; l: t/ v! g3 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 V" R) b$ S) K, R
** Set the serializers, Currently only one serializer is set as7 A5 e& g- y: ]' c) R$ |. @5 ~
** transmitter and one serializer as receiver.9 ^! ~5 t+ m8 b: h
*/7 u" v# |4 I5 K$ i; A" Z, Y" z: L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& ]! H# }# r6 ]- C2 DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( B6 ?. x8 E$ l8 V0 \! f+ [
** Configure the McASP pins
4 e+ \# _2 f' |# J** Input - Frame Sync, Clock and Serializer Rx
& |. `/ _$ I! D S** Output - Serializer Tx is connected to the input of the codec 9 }8 k9 f; P \0 r: a* B5 z
*/
k5 w$ j% a Y; v& e: v# n. {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" s% W; J" z/ L$ uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 Z, b. P) g" U" r2 o/ W! C( G7 p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 |8 _3 g4 j2 p4 p
| MCASP_PIN_ACLKX
T8 k* S5 D. j9 R| MCASP_PIN_AHCLKX
/ B( ]* ]: `1 Y b, N+ n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' g1 s4 Y' F2 o$ z* C. I2 w- {9 Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 q1 u: r7 z7 O w# F1 T
| MCASP_TX_CLKFAIL , Z6 H+ z {1 A6 h
| MCASP_TX_SYNCERROR1 ?3 E# |5 x/ W0 N$ J* L+ W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / |* Q; ~1 O$ U0 s1 S5 _; m
| MCASP_RX_CLKFAIL
: Q9 h9 i; e4 o2 m| MCASP_RX_SYNCERROR
8 w5 J9 z8 W& k| MCASP_RX_OVERRUN);
6 a! c4 r1 f/ ~: P. b} static void I2SDataTxRxActivate(void): _* [# e" ?" Y' K
{) F! V. |5 L5 _ c
/* Start the clocks */
6 P: H% v; I2 Y$ D# M% ~: PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 M, t3 v% o8 _5 k8 s6 c7 h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. z; ^ Q3 A+ ?# @! o6 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; P) y" Z" Q1 c4 [4 h' h
EDMA3_TRIG_MODE_EVENT);7 j8 ?+ P5 b7 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( B/ A9 c$ c* N5 n' P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 D1 h! E$ y0 [3 k! H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. W' H0 r4 @$ y( q- V% Y5 g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 Z9 ? H( N A" S7 `- w- ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) |- @4 a- b3 I% R! p( G1 m4 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 y* N. g7 M) KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% z0 S* e- M5 y* T}
- U: t' p- F6 j7 b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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