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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% I- ~: v1 X3 rinput mcasp_ahclkx," Q1 i+ \! `% f( A
input mcasp_aclkx,, Y5 m+ ~& _) Z
input axr0, j+ Z- n. l- ~9 @" G4 p
3 g: W# l; H! f! g' T' G( c5 {
output mcasp_afsr,
) T6 ~* e; C( u* Qoutput mcasp_ahclkr,
7 ]: X c: f. m8 g8 V5 j1 ]" w- H# ioutput mcasp_aclkr,1 e3 B$ Q: [% ?5 i
output axr1,
. N1 f6 C/ v, h) V assign mcasp_afsr = mcasp_afsx;
1 f0 i* H5 A& {& t( P6 N5 Dassign mcasp_aclkr = mcasp_aclkx;
1 E( y, {7 |! J: q, g9 X7 B tassign mcasp_ahclkr = mcasp_ahclkx;3 C1 `) F9 I" e
assign axr1 = axr0; 6 P* ]+ \& a* f% C8 E m: h7 f
5 } c. o. B0 j" E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 @- ~. |& h& q0 l) Qstatic void McASPI2SConfigure(void)9 H4 P$ c$ U. i2 j, e/ n0 i o: d6 |
{
* G' K V! U/ g" f: X, C" lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 m5 u5 A, e, k- E4 W0 }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; b8 X$ [& T. y# g: [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' m9 P) J" }1 M- _% } BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( i: Z' W/ n! \" d* U3 ]- s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* r3 f" G8 b; L8 [MCASP_RX_MODE_DMA);
2 [. F4 ]. ~$ v/ ~. ^* wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, e7 K3 Y" f7 R5 @0 c; }' HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' L9 B. B! G0 S9 g9 i2 a. JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 N0 b) V7 W. x8 g P: w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# h) F2 v! ^' ^, M5 m4 HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; L9 b8 P" ~- V5 T* y3 x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ P2 P" l% w$ V' @* N; s' T3 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( Q, s' v6 y; k$ k- W( E/ CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / [8 ^$ B' |' O' y, ?" i6 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 Y2 N: X0 _- |+ A8 M6 x
0x00, 0xFF); /* configure the clock for transmitter */
# I- V: E. T; uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* p5 W, d% U+ U+ ~8 T* r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # b/ B, d" V G# Q9 @1 W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 F$ B, N, |- C l4 [
0x00, 0xFF);
* [- Z6 @9 d3 [1 `8 g! `7 X A+ {: _5 G+ U8 V, T
/* Enable synchronization of RX and TX sections */
; m% K7 @0 f! g! U7 _6 i0 qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; C" t3 ~! `. S5 }4 ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# D$ C, C- z! A: e! ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' \, a+ U# e/ \4 L& ] `( p2 m** Set the serializers, Currently only one serializer is set as6 H* |/ W8 x6 x4 M& B. W3 b
** transmitter and one serializer as receiver.
/ }5 a9 U( R1 w' m, x/ I3 y4 L*/
! E; Z, s9 u$ z* x5 K4 A3 wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" I6 @1 R' S$ z" X# jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- T- s: [! o1 ?/ J7 L& v0 K6 Z** Configure the McASP pins
+ D% K+ z* ]. T- `5 Z** Input - Frame Sync, Clock and Serializer Rx% C! R9 }, d) M: w4 U/ ]
** Output - Serializer Tx is connected to the input of the codec
- {& w( ^: h; B S$ o*/
. P/ E: t6 {$ _# {% YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% R( w, y/ ?/ Q1 S0 @1 Y0 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( N8 ? }4 d% |8 A# R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 h& |( `) N$ Z% i3 o }| MCASP_PIN_ACLKX
, M& m; M! R0 F% a| MCASP_PIN_AHCLKX) w+ m6 [' V3 x9 i/ {- }6 }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
e a y0 k$ ~9 @: ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 k* K- V4 J6 @. [| MCASP_TX_CLKFAIL
) z/ {% v% ^' Q/ v6 c. V& X| MCASP_TX_SYNCERROR
) @6 E: S$ r5 [8 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. ~' z* E/ u s; A1 |1 Y| MCASP_RX_CLKFAIL) v- O2 M2 H# y* y& f$ `! _
| MCASP_RX_SYNCERROR
/ u6 t& `& U" ^9 R N| MCASP_RX_OVERRUN);
; K ~8 D) d+ S. H. z* y% q+ `} static void I2SDataTxRxActivate(void)2 y: P" E3 ?3 C9 g5 }2 i, `! ~
{
! ^0 L* b" G' m/ G. @/* Start the clocks */: `( g8 U8 b& Y% E* R4 L3 N7 o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 [% k5 X; ^# h P4 K$ N* @0 eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 A0 m1 r! L9 b' ^4 O2 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% ?* a9 \. d* l' DEDMA3_TRIG_MODE_EVENT);
' B/ N, C; w1 c; e; YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& l% _2 L+ y* f/ O: J) _1 UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( F4 s7 K) u7 D) f# \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. N9 A4 V1 b2 m' VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
t1 n$ h$ C# Z# Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 D4 F. l( O' b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 |; K9 X* ]4 G2 {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, R0 O6 u. d- Y; l! ]2 K* F4 d}
k, x" w4 q' H% H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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