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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ @* f n$ S4 \7 V# O) k! o: h' `
input mcasp_ahclkx,+ n; h: a8 Z. l- f
input mcasp_aclkx,5 T: Z- n. l* |1 {# Y; ^3 u) [
input axr0,+ j" z" t! H( l$ P& ^) \& c
) u; C% e. j; N$ h
output mcasp_afsr,
+ [ I1 U* B% f3 \5 [* y, M6 youtput mcasp_ahclkr,
; w* V) z3 N4 v y% V2 Routput mcasp_aclkr,
) Z+ z) o4 M$ a' h/ Y% ?output axr1,
4 h1 V) J9 H/ \2 S" o assign mcasp_afsr = mcasp_afsx;" L8 s; E- f7 I2 z
assign mcasp_aclkr = mcasp_aclkx;* p3 c: S7 e; i8 j' @" B8 S: p1 M2 E" k
assign mcasp_ahclkr = mcasp_ahclkx;
q7 P K8 z" Cassign axr1 = axr0;
8 T E9 b- M* j! k
+ g4 G& {" W! j- K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # _ h( c$ q/ s( G- w
static void McASPI2SConfigure(void)0 ^3 {+ E7 R% g
{
9 n# U2 }7 Z. N/ NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% G5 H% n( t3 @ E0 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// g; A+ X: a3 h% }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 Y+ D' ]9 `& ^! O% u# O, e cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 }6 I2 \/ ^3 q) Z! i8 l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' F+ k% Q7 ?; aMCASP_RX_MODE_DMA);
$ |" v1 g* m# u& e8 m; T/ [! ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ b9 D. ], ^$ [/ b% {. J1 j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 j' z5 V/ F) v' P! A( |1 F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# c% J, z& J) h2 jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ h) ~& D, f; `6 P; {' y s* J4 NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# e' l5 k. g3 h/ |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' n5 j) s4 |' {5 k# O) y1 qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( j: D% o/ m6 N) p: ^0 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 Z+ N- r$ S# \, E, [9 R9 ?! Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- ^3 b0 r. I" k3 [2 U) e& y8 U- V8 ]0x00, 0xFF); /* configure the clock for transmitter */$ i n5 \3 g3 a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% D! J- }( d, M6 j; ^& Z# G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ U# G/ u; J$ T) TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 M4 k5 ~! z% s, k* _: O( |
0x00, 0xFF);
& f* a; ^3 l$ Y$ t; m: C: Q+ S8 j& |) H* z, }( G
/* Enable synchronization of RX and TX sections */ 3 _0 ]) b% f( l' e/ ?( K* K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 _% H' _5 S$ Q: C" ^# D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ _1 K, W2 e4 e# L& CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: O# U: S5 u& @# I9 R** Set the serializers, Currently only one serializer is set as
# F& r6 e( i% ]+ E! s$ }7 j' m** transmitter and one serializer as receiver.
3 N A1 Z* O% G9 s+ l5 D1 |4 @9 z*/+ {* F& |5 P0 g* O' e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 ` P/ F5 x \# J4 K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. s' ~$ e4 y! Z( N4 N** Configure the McASP pins {3 C* \% z* ]
** Input - Frame Sync, Clock and Serializer Rx
( i- q6 R* r3 w** Output - Serializer Tx is connected to the input of the codec # @; P( z' E" f2 ]1 h
*/) o: A& s/ Q% l: U1 L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 {+ W( i( k3 n/ @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) E$ X" F7 q: ^- d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& g4 }8 Z( G: C| MCASP_PIN_ACLKX! B) o; j- N7 f' b% I4 C4 o. P6 I
| MCASP_PIN_AHCLKX
4 v6 R, i0 w3 T/ Y% ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% T6 G7 Z) t. F; d. WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) _( [7 W! F2 U
| MCASP_TX_CLKFAIL $ @' v1 K' F( X; @
| MCASP_TX_SYNCERROR7 s& `7 F- [: v& m3 x1 o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% e/ {1 Y1 ^4 l" e( u| MCASP_RX_CLKFAIL3 Y$ p3 u$ I) l$ p2 i6 Q
| MCASP_RX_SYNCERROR 3 D# @6 Y6 Z. c2 n3 x8 h- H6 w
| MCASP_RX_OVERRUN);4 Y; o N5 m# k# V, W. N
} static void I2SDataTxRxActivate(void)2 Y# L) H5 u8 y& T
{
$ R: M6 U# T; `. h/ g/* Start the clocks */7 J; A3 I. d, M1 B) E% A) r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 `6 d4 _' t- U; M2 {3 r1 y: QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ D7 a& C$ j3 k+ a5 H0 ~7 U8 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) r8 r+ v2 l' k5 z( ^+ K9 e: Y+ Y
EDMA3_TRIG_MODE_EVENT); M4 {8 c$ _: p, }3 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( w6 j& H) V3 o2 IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. l3 C2 h7 G2 ~" N& sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 [3 }# G6 q: `- e# K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- e$ U7 x& C7 \3 B6 {: Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ f* _/ p( m+ K: Q+ {! P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; `' B) t- [( f+ Y4 q, AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 c% I6 L6 D+ l. r4 F0 O} $ o, X$ `6 \" c& n; Z$ o& Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 ?/ q' _+ L! j: l
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