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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; m1 I+ N ^6 ]3 ~! |
input mcasp_ahclkx,9 @4 X0 M2 x8 b( Q6 M8 G& g8 U# E
input mcasp_aclkx,
2 I1 Y5 ^: y" p; }" tinput axr0,' H/ V7 J6 s4 T5 d
5 t+ W' G \& t6 y
output mcasp_afsr,
7 B6 P- t: q' O+ W; _5 N2 w! moutput mcasp_ahclkr,% T* v9 N, S, s8 J- e
output mcasp_aclkr,; _( n/ X9 A- x9 ~# `6 v
output axr1,
$ g) |& M2 ~$ @* ^; u assign mcasp_afsr = mcasp_afsx;- B7 ?& [, t9 D
assign mcasp_aclkr = mcasp_aclkx;+ b( d, N& J0 C5 u
assign mcasp_ahclkr = mcasp_ahclkx;
! U" _" u3 x# M: J5 c! m7 b. p7 lassign axr1 = axr0;
0 w+ Z- |( c! f
c7 Z" J# B- a( w8 e# p2 ?) D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ V" p% s; Y) Z4 p6 L4 ^static void McASPI2SConfigure(void)
% K' e4 X0 W" _7 |5 l{# ^, D4 X3 ~& w; e/ o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" K) z/ D" }' g' P) cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! x! ~% C) N9 S4 e7 |: L7 XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: G. F, ~8 A, h8 ]" ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 _8 `# b4 t+ u8 G5 E" \8 sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% q( z# P+ a. x- |; S4 qMCASP_RX_MODE_DMA);9 f- h: U& }1 U T$ @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ {5 @8 n/ Z! {2 O: m7 t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( N+ U# M8 S, h8 ]( P& i5 ]! k& bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * c& o+ `# ?, |; a0 F' w- ^8 i1 d; J, i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* N, n+ g5 u s$ L3 w2 D s4 T8 }' k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 S; ^0 z6 x3 s% j0 T1 ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& t+ [2 a% y2 f- p& p' L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. h5 @* b8 f" E7 w; M9 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . z1 A' K2 {4 @5 F" ~% K% e: O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% |1 S) D* K: @0x00, 0xFF); /* configure the clock for transmitter */& Y7 F( j" k7 H/ n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% e8 `, Q- Q. ?$ x1 ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & u" V t( h& U* b; P+ Z Y" A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, I$ a% w& c8 g& X( r* q
0x00, 0xFF);
- m9 H1 k6 |$ ]: N+ z" i: s+ J1 R1 a" C# m' y* z
/* Enable synchronization of RX and TX sections */
4 @' y2 E5 w O$ `8 M1 gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- l( `$ R& y( @4 @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# E5 V& d# M4 A, {$ ?. `3 ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- m* `, I/ \" w- O$ |4 X** Set the serializers, Currently only one serializer is set as7 j2 i" c. O7 a( g
** transmitter and one serializer as receiver.0 b) { Z2 A8 m6 G; | L$ |
*/9 x' I/ z) z8 Y- T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% p* [8 o: ^9 Y8 z4 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 I: v& {. G# J0 u$ A
** Configure the McASP pins
" |3 x8 p- D* b0 V u** Input - Frame Sync, Clock and Serializer Rx# I1 R+ V2 c. r! V
** Output - Serializer Tx is connected to the input of the codec ! ~; K# F: `+ q$ t
*/8 ]3 T+ t7 R0 f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* r$ n, k" A' C2 c5 EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# e# J7 H& ^" P- z) t7 G& ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. H1 j7 l6 O2 E0 t/ U| MCASP_PIN_ACLKX: @5 ^0 d. O% U# I
| MCASP_PIN_AHCLKX
, Y, E* i4 ^( y2 g! E2 N1 V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 W) @' {9 i6 OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 W9 _. m, p( g* U. s- m& f/ }
| MCASP_TX_CLKFAIL ) W/ T1 K9 [: J% t0 H2 e
| MCASP_TX_SYNCERROR% f- s+ s- W2 R( q$ E. p
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / P6 |. i2 l- l+ |) w
| MCASP_RX_CLKFAIL
* P; x6 e3 U. z+ D| MCASP_RX_SYNCERROR
# S* ^7 Y3 L! G5 T% J& b q| MCASP_RX_OVERRUN);
" j/ ~9 _( n+ f$ K2 [6 H} static void I2SDataTxRxActivate(void)9 b3 \/ O3 e0 u* V. X
{
9 s; \/ l9 g# P$ B- |( j* X/* Start the clocks */; k. m' t1 _# J4 ~0 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 m8 A7 J6 k, }6 }" R/ L: t& B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' y& S1 @5 E: `" ?$ u/ H$ I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 O" t5 t B3 `- q( UEDMA3_TRIG_MODE_EVENT);
1 t" o5 L; Z& p9 v/ Z0 }$ F) l$ BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , C3 i% z- M1 h- {- N6 r3 t2 K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 Y" ~" r6 ]. b7 _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' f, U. O5 B, b& o5 I/ rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ i. v% u0 O% |+ i! d! p3 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 u x# X" ?* ^$ ]3 \3 j0 Z7 a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! q4 C; \0 | U, f) a3 GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) t4 |; I: e. _4 Z+ P* ~9 p$ D
}
: w7 w5 _8 L0 Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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