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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, r% p; U9 s; Jinput mcasp_ahclkx,
9 _, i# f9 L9 [" p0 D" Pinput mcasp_aclkx,, f4 U' H2 d, O$ s- S+ i6 H) `
input axr0,/ E: l: l/ T0 P1 s8 A1 O `5 u
: s- p! p: ^! M6 c5 ]
output mcasp_afsr,: h0 r5 x/ L% E: U" K, Z: e
output mcasp_ahclkr,
9 l! R, q( |- [, f r$ { youtput mcasp_aclkr,) {& {& W& `! v7 ], X& t: v
output axr1,) @& t) [: C8 t8 I$ O" t
assign mcasp_afsr = mcasp_afsx;. R6 F3 D0 e& B
assign mcasp_aclkr = mcasp_aclkx;
. `. K' R" A' f$ P) O: M% ]assign mcasp_ahclkr = mcasp_ahclkx;
( D# I, }* d4 Z9 P- x) Dassign axr1 = axr0;
. Z! m0 m* z. I# f
/ m8 M: E+ H4 M( Z2 S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # R1 r6 m. @( d, C/ _
static void McASPI2SConfigure(void)
6 O) {9 j# [) g9 M{' _' d) k) f- j8 x! V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 G' F, x" g0 g9 p9 DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( B1 |( k. z# o0 D/ S' J3 B6 N! KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 s" E" K( H4 }* x+ U% R$ Z0 c3 U$ {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ k- \: m+ ?. M, r/ E+ D" C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 o& T$ U7 s# U% i% g x1 F8 BMCASP_RX_MODE_DMA);6 M6 ~- w2 h" x1 Y7 O- \$ k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# |" A1 h! {+ s' }0 g( ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ O( l- l& Y' YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + f% c& I. |- i$ c3 ^1 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# x! j* k. D# F8 n( }6 O p1 ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & V# a, C1 _% l( W6 f4 s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 d. u5 c+ X; I% U: _, r; ?, o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 P; b( r L" z7 r' ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' D$ w" P! U: d1 U. O7 v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 k% A2 c+ {1 q) T }0x00, 0xFF); /* configure the clock for transmitter */
2 r* B& }! W% _( dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# {( e* A) R/ T4 h ~% e) GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! Q, q7 k6 y6 } u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; H U, p3 S& q6 K6 h8 _: V
0x00, 0xFF);
& g6 @6 A3 b/ T) L
1 z, g% c; A. @: l& `+ _/* Enable synchronization of RX and TX sections */
8 s& U% `" c, b1 _/ T9 U2 P& OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) x; r+ N! H+ Z3 Q6 P8 e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 c/ v' ]6 S; i. m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 N: [+ s U- m* h/ W1 r** Set the serializers, Currently only one serializer is set as
6 \+ o& T6 Z N** transmitter and one serializer as receiver.
" p1 _; |4 R6 O2 x# k*/2 O1 ?: ]8 a& c9 f5 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 ^% \/ N& L9 x, |8 B9 c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& J4 }8 s% K* {4 J. M** Configure the McASP pins
; w2 T7 `6 M+ y" [! T- ?3 N: K! j** Input - Frame Sync, Clock and Serializer Rx7 k Q) [ n9 ^2 U+ g/ d5 X: P
** Output - Serializer Tx is connected to the input of the codec
0 a/ X* Q# e |6 U( ^# `" L*/
. U# I7 t2 G6 f& r" R7 u& @6 {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 r! J t% g5 x" v+ E1 ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# U9 `9 k& ~2 z: a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX B% G) A+ A! [
| MCASP_PIN_ACLKX
& ~' q$ T0 Y' v| MCASP_PIN_AHCLKX& N4 ~2 I+ T9 @: I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 J1 h1 O( S, r6 K. ~- t3 FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! A$ E" b1 L4 ]$ f2 T
| MCASP_TX_CLKFAIL 8 {" m+ v* g2 V
| MCASP_TX_SYNCERROR4 X+ ^( j) y3 Y6 a3 q+ c- }, H9 u( n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: a! b4 p, d5 R- d4 f| MCASP_RX_CLKFAIL! I- O3 z6 e" `: w
| MCASP_RX_SYNCERROR 4 n$ E) E3 z8 L( }4 }, A& c
| MCASP_RX_OVERRUN);
! k ]8 y4 c* T3 m. V} static void I2SDataTxRxActivate(void)
5 [9 }$ q# G6 j9 y) U. y y* m) b{0 K( d* G# N4 ?7 v: e
/* Start the clocks */
) R% m5 \' w3 R0 `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 Q/ k2 G* l. E! K3 c: bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% |; _. w+ g2 R k& s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' F$ }8 F$ W$ A5 A6 n/ a
EDMA3_TRIG_MODE_EVENT);
( l# J+ p# }, K. n/ zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# H$ D* q; M6 Z+ M5 NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
], d; ?# I1 z- M- ~, V/ D; i7 J! R3 VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 q# o* r C$ L2 W( FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- V% O" F( ~6 L* u8 n% _; O) t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ W- |4 l% m5 U! ], A) XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 f+ g) ?: [. l% S, z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, y3 A- x, i+ B$ T; o7 |} , A; B( b" d) ~- ?: _' N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 i7 Y5 `8 U6 t' h# ~7 O1 W
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