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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 f+ ]$ M! X" u, `. A) ~
input mcasp_ahclkx,( J0 ~* H" d/ ~" o2 f
input mcasp_aclkx,5 y% |9 a! Z3 B# P2 X
input axr0,
, \* g* t3 }- q3 Z0 O7 `. z6 ?0 V3 T' E. J3 E; b) e
output mcasp_afsr,3 F8 o/ u( P b+ `- A# L) u0 q
output mcasp_ahclkr,; R5 F7 Y1 P( _- K& ?1 V7 [
output mcasp_aclkr,
6 ]" S4 M1 r% b# J, X' ?output axr1,
; I0 I" y/ [* V5 Q assign mcasp_afsr = mcasp_afsx;
3 @# J& n2 l3 iassign mcasp_aclkr = mcasp_aclkx;1 d# o" E1 o7 |- \2 ~8 N
assign mcasp_ahclkr = mcasp_ahclkx;
( V, H3 r- v( b/ k R2 O t: vassign axr1 = axr0; . Z9 S$ q4 g# ^" G {
/ Z4 u6 J' _/ Z5 T* n* q' f7 k. @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 o2 K4 t- ]# N7 J* r- B- kstatic void McASPI2SConfigure(void)
* Z2 F9 B: t5 K9 O0 n. f{
8 ]. E+ o. [' g. q/ {1 l0 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ \: @9 T& L1 s1 p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) a( }) K' G3 qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, U: }5 i' U8 z0 x+ @% h9 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 \: `2 }+ x! L% I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( h5 {: X3 @6 u I
MCASP_RX_MODE_DMA);6 t) |7 p+ g+ O. X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( d- ~$ g' @ }: h" p. W; O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
v3 ?% a3 e& L( m) @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% f& C$ K1 b; H! }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* O. v g$ A9 S6 `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - P! w; k0 n9 Y. t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 t' l2 `+ \$ q( q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; q" j# h& e$ j) _- EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 [' Z3 h' Q d( O- t4 KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! @$ m3 U6 i2 {& J" v$ H0x00, 0xFF); /* configure the clock for transmitter */
2 V. w; {! E% b, c/ F5 ~! ?3 L" [) G3 IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 g7 |0 t0 q) C6 e% V: S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' g1 h2 Y( @% G# o/ t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: j; u S" Q- W1 }! P
0x00, 0xFF);- O. \( R# C. l; q: @3 |4 f
7 \& a& Q" w _! f
/* Enable synchronization of RX and TX sections */
. Z/ S5 a* m/ A# c1 O' w2 ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' I+ v8 J- K {! z2 B! YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 |' o. R8 S: v: C7 f; u3 HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# ^7 |3 y* G, k6 M** Set the serializers, Currently only one serializer is set as
, A) ^5 U! t* T* i. f% q1 V4 R( Q** transmitter and one serializer as receiver.
6 e L; }' s' S4 W*/
, u; `$ M( V" @4 h/ RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; [# w' T7 o: Q; t* T$ \! r" R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# @1 T: w! Y( h
** Configure the McASP pins 8 ^- p# A4 K' j; y! ?$ h
** Input - Frame Sync, Clock and Serializer Rx! g4 h" e: M Q$ _/ ?% Q5 K! F
** Output - Serializer Tx is connected to the input of the codec
+ u) Y9 _" i6 X' Y. q*/
" N+ e+ x8 P$ }. N5 Z9 e) VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 \# X4 o' J& a, G( yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( J# z$ _' O1 ? s# T6 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 y1 r6 g2 t" F+ P+ q| MCASP_PIN_ACLKX. C* D4 \6 R( R( ]0 q$ q
| MCASP_PIN_AHCLKX
, X4 `* a- k& I9 \, R0 d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 u; p5 c) _& C/ _0 O# y( U: L( lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 ]6 H( z& z" Z% t5 B9 G c| MCASP_TX_CLKFAIL 6 h( ~( o8 x; r7 t/ I
| MCASP_TX_SYNCERROR
t, g8 p. ` y/ G ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# ^6 J' G- n# }) t7 ]3 ]| MCASP_RX_CLKFAIL
+ K% N! \5 Q" n) ~3 d6 ~0 h. ^| MCASP_RX_SYNCERROR
* l! j, p# j: `5 h| MCASP_RX_OVERRUN);
+ M( R7 K" E, m2 Z5 }3 M) N" K( `} static void I2SDataTxRxActivate(void)& D; Q8 W8 S* o" }( r* s9 ?
{
9 l. N2 K. C: |- h V! g/* Start the clocks */
( g1 S% {+ B5 w" s( o# `7 RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ x2 b" N" P3 f5 R' ?! [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 o- ~' y8 i( I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 V# i3 r+ X, F; G' n I+ C" zEDMA3_TRIG_MODE_EVENT);
- E5 v* D! z' ?% G* d% g6 r: sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' f, [4 f$ H H1 R! p( I$ w; ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) u! R6 P" M; }8 ^; K: U rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ [* b' X4 C V+ \4 eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 \. U$ s- L' W3 y& t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 W$ R, C, b( M, y- d+ i% }8 n j+ zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) N* W: D$ m. e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; z, i! u0 L. Z' x}
$ J% }# S) f8 y0 `- ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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