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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' v2 b) P) G7 X7 e' E! Kinput mcasp_ahclkx,
' x4 Q' K5 W) k3 Iinput mcasp_aclkx,
6 S+ \" a' u; ^8 V; yinput axr0,
; ]# N8 n6 |0 V0 r3 Q, K: d: Z% t F
, [3 m: J" Z& F: A: z' ]output mcasp_afsr,) S: a. \- p5 e% O" r* g2 j+ p3 G9 _
output mcasp_ahclkr,
6 Q$ D' Z. ~1 ~output mcasp_aclkr,
8 p( R/ F. y2 U# L, N. coutput axr1,2 @$ g; H1 g/ w8 ^
assign mcasp_afsr = mcasp_afsx;
% g8 j# I! E# @) k! _+ aassign mcasp_aclkr = mcasp_aclkx;
4 F k# U( s' d) Z0 ^4 `assign mcasp_ahclkr = mcasp_ahclkx;* k: k0 M7 y+ J1 ^3 E3 ]4 P
assign axr1 = axr0; 0 U0 ]( I1 L X) b6 y' @% R
/ e! I g+ [, R: `8 K4 X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
M) ^/ ^* `: |! b$ M1 s/ e5 G% l: G8 fstatic void McASPI2SConfigure(void)+ {+ k, e+ _9 a Y
{% f' g5 m8 q8 z4 Y& f- h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. j, Y: s4 m. w1 }, Q2 z5 H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 G0 T/ L0 H, N+ pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, Y1 U, Z# a! c4 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 ~: U: C2 P+ _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 w6 x( h5 {, vMCASP_RX_MODE_DMA);. U9 z" U* f& _1 C u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 d5 u" H! b! g" f' U, u# y* NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ Q* M- W0 o. E, U% f' _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; C( a7 E6 p7 _7 }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ a( G0 D C& c1 O: W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 u) K7 j6 W* Z' ]3 W6 e; |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' ~, |; e( {# Q8 K* w1 g+ @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% a+ V; x I# K8 I; ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # t7 E/ `# ~. X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ @( e+ z4 Z9 \/ x/ e4 s: C0x00, 0xFF); /* configure the clock for transmitter */1 n& [' _* f$ w9 @! W* b7 x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 y |7 b. S0 S% h0 k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ r( F! `6 y8 qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ L" a+ t3 z9 M' V0x00, 0xFF);
6 `* }% R' v* K8 _" z+ i! F7 X f; n, D1 b+ v
/* Enable synchronization of RX and TX sections */ ) g! M6 {9 P. }2 V0 `, z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
l/ _0 t/ @( z) V7 ^7 lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 t) p6 m% ?: A' o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! @; ~2 I5 H5 `% R) v0 s
** Set the serializers, Currently only one serializer is set as
3 j9 P1 x, C- G# Y- F9 W& D; m** transmitter and one serializer as receiver.# L V2 M9 g4 t8 e
*/
5 b6 V+ ^7 t' Y; b# |- D+ fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 E( S! M3 P/ S! J( _2 y5 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" i! F# Z# q& W
** Configure the McASP pins % f3 P! R6 P$ N
** Input - Frame Sync, Clock and Serializer Rx
2 G* W% p5 s4 L; r+ B** Output - Serializer Tx is connected to the input of the codec . n1 b6 G8 K3 n# ]9 r- _
*/
: p+ d8 w" Z: {' s' @9 S6 U, kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& v7 T3 n4 f5 `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 E/ D [/ N2 m( p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 L3 B( ^0 ~3 E' D+ Y
| MCASP_PIN_ACLKX
$ {; v4 Z: }; B3 }0 |& o! }| MCASP_PIN_AHCLKX7 ]- k2 a$ o+ N4 @2 f2 ?( B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! a! \5 A: _" y* u, b. P* W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 }" r: N8 X* H% A: `! T
| MCASP_TX_CLKFAIL $ V, B/ J" \2 ~$ a
| MCASP_TX_SYNCERROR
8 m- j6 D6 F% z: R0 u* p, F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ [1 s% }2 O( m/ e3 ` M| MCASP_RX_CLKFAIL
2 l: |. U# L, g& h$ V| MCASP_RX_SYNCERROR $ f. ~8 C* A) U3 d9 n, K' c
| MCASP_RX_OVERRUN);
+ }# D( `0 m# V% A2 |} static void I2SDataTxRxActivate(void)5 p( w( R1 k6 k, u M' v: x: a
{
6 H* q/ W1 S+ l: r! m8 b# O/* Start the clocks */
2 Q3 A& v6 j6 oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; v) W& e2 {' _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ ^( i7 `9 C4 S. w5 O- TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 r) V7 x" \# {/ z, j+ T
EDMA3_TRIG_MODE_EVENT);
- J$ {1 o, B( C1 g( _" aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ ^' |7 P& w W7 C6 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ [% H$ i; p# e7 q( n0 ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) d- u" c9 j9 S( ~1 W2 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: _" o; e$ U6 Z- V( _1 A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// w0 C/ o4 F$ }& \! @* y1 `$ I+ m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 l$ B6 t; A9 o k- R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# D" N6 a& l4 k) @} ) }" P _4 f( O; n5 T h' \( i5 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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