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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 b7 j' l# R1 v* |: {* pinput mcasp_ahclkx,
* ?4 @( j* Y9 `7 w5 _, [input mcasp_aclkx,
) Q j0 u* w( O5 N" _input axr0,
4 Y1 c; l4 X2 A R; H# r$ P
1 Z! L; G, M+ R1 B% aoutput mcasp_afsr," x, E' d* l( V/ @2 e
output mcasp_ahclkr,
0 Z% i7 n5 H1 D& p5 u8 Loutput mcasp_aclkr,5 {* |) v0 y- ], c
output axr1,
9 m- @9 ?" z% m. O# e assign mcasp_afsr = mcasp_afsx;& Q6 H& U9 [, [0 r5 {) V
assign mcasp_aclkr = mcasp_aclkx;; Y# u1 V; A* |3 R7 h
assign mcasp_ahclkr = mcasp_ahclkx;
9 ~% a5 p/ j. g2 {- vassign axr1 = axr0; , ~5 q8 T. v* Y6 @
* f- [- @. b c+ I e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 n2 f$ k" ^% V3 S1 F( g L
static void McASPI2SConfigure(void)& p7 W6 o8 n( N
{
4 B* s/ X) A) C1 k U, DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, z$ K: m# H! {- p' M! g5 S9 i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 ^& b. l7 Z" _( g6 }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. d/ n9 F5 [( Y* }: AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# S4 ~: M( K5 j3 z- `4 P- vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 d* N# v5 n% `1 W7 MMCASP_RX_MODE_DMA);- X( r c3 X6 m7 y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& x) w. i) s' x1 c G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% B" |$ a. w% x: a+ uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 D' e7 r& e9 Z; P& q5 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: P/ O# D& X' X! s) j i6 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 D9 |' H) l1 c6 c2 a% MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 Q! D Y8 S( l2 ^# y% XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 ~$ A, p& m% o& }% iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! i1 g" N4 L4 t8 \( gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' Y2 j+ a: I7 V! i0 Z0x00, 0xFF); /* configure the clock for transmitter *// \0 H1 P6 _8 u1 x0 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 [( ^( e3 Y( S' t8 _3 o/ Y$ ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 r, ]& j0 p5 U- t- z+ mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ L6 K$ i1 o" u% E! B: t& [' |0x00, 0xFF);
6 z5 w3 j: M) p* h$ y
+ n% ^& R) M, g3 d$ I, j/* Enable synchronization of RX and TX sections */
" H; Q/ H! X0 m( j! A( q, Y5 u: PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, q9 k8 K) S2 Y" F; j3 {1 CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# i" o- I* u8 F4 J: ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! h) y* D; `/ [) A$ P** Set the serializers, Currently only one serializer is set as( b, r' ]; u, x$ ]9 Q
** transmitter and one serializer as receiver.
w7 z R- h9 G) o5 J' Q8 `*/
6 A* O) m/ J; m0 OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" v5 N- ]$ b3 Y$ D) NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; f% Q+ e- y: t1 R9 [7 ]
** Configure the McASP pins
; u3 r. j/ V" z/ ?** Input - Frame Sync, Clock and Serializer Rx0 f% L6 ?1 d7 ?1 D- T% S/ ^+ q: D. N
** Output - Serializer Tx is connected to the input of the codec
+ a, a0 {% S9 y0 Z, H% L# l/ N*/- ` [! s/ k$ B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& ]) ?5 R1 B, n# x, m# \" D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 f2 v) O7 @2 ]" mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 Q- }) h: }" D1 B5 Y7 i9 w| MCASP_PIN_ACLKX% Q* S- Z- w- i, w7 R0 N
| MCASP_PIN_AHCLKX( r1 a/ x0 E' j1 |( {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) J) n% M: E( |. F$ X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 z, V! S3 F1 x3 s* S- F0 @
| MCASP_TX_CLKFAIL
% c" d5 f: P+ K6 D4 ?| MCASP_TX_SYNCERROR
$ Y7 W% ?5 x8 E% V$ j" D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + X7 e; O) ?1 `! V
| MCASP_RX_CLKFAIL
& ~/ t3 F6 ^9 b; @# a5 s| MCASP_RX_SYNCERROR ) V9 m* ~0 P: X$ Y7 v: v+ e D( M
| MCASP_RX_OVERRUN);0 i& `9 P, L. X; w7 {9 w
} static void I2SDataTxRxActivate(void)/ u$ m2 j {, ^: A7 f& d) {
{
6 Q) w( ^2 x! U$ s! q- D' A7 L. S* _7 N/* Start the clocks */
) n9 Y Z1 x6 L* u# GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 i& Z# q, X+ s2 ]6 [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 x( q; T q/ p. u7 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: d# n, Q) e' y3 h
EDMA3_TRIG_MODE_EVENT);
1 p; `" J4 Q% {$ I) J! w: `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) W, o `' c% t& x! rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, H& c( g" Z4 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 ~% ^' E2 \. b, ?; h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. A3 N) Q2 [: l) a8 C3 I6 Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// [9 a5 c% {. ]% K$ S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 m. M1 e+ j" p; I4 FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. C1 `7 z- m- u6 B0 X} 3 Q8 J. o/ ?( X/ x8 @! N8 X% f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 r) G/ e. g c; e
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