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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* Z9 t. X3 |3 y4 Rinput mcasp_ahclkx,
+ o7 M0 z! a; x" \% V$ Z( ~input mcasp_aclkx,9 S2 o; f5 |( O A! C0 E
input axr0,; c; U0 G2 i$ C( j) f. b, s0 y. k
: }0 { @4 @7 l. t! s: a
output mcasp_afsr,
! F: ]" j5 U4 O; k! | y; h$ ~0 Uoutput mcasp_ahclkr,
+ l9 {1 D9 d) a2 ?output mcasp_aclkr,
- q& @ _. I3 u# }1 j( j8 t8 Houtput axr1,! {% ~+ L& T* _' x
assign mcasp_afsr = mcasp_afsx;
; D5 W" \9 q; ^! p' u+ q, Lassign mcasp_aclkr = mcasp_aclkx;
& }7 d7 O7 f. k7 u1 i4 jassign mcasp_ahclkr = mcasp_ahclkx;1 c9 z3 I2 W- F$ Z/ V* u
assign axr1 = axr0; 5 A8 q% T0 [0 g; t1 A" x, `% J
0 u0 |$ z% k$ `& f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 r8 f/ ^0 s& K! hstatic void McASPI2SConfigure(void)2 s, C( |) u, ~9 A5 O2 M* a
{- p/ {4 Z; y" M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! A4 n5 P" W+ A! b$ D+ _7 |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# t ~4 e/ H; d0 X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: S# ^, C% B% K% c# ?0 eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* |: _/ r9 r" f" Y/ p! gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," T! W f( L4 x3 J: `+ r7 _. h
MCASP_RX_MODE_DMA);+ I/ {; K5 W# {& c( D' V, N* W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! @0 M- x+ [8 u. e ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, S* i: ~1 s n0 sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 |4 k2 l# A$ Q r% Z" W4 d/ ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( ?# ?6 M, d( d5 @0 x+ Y* M& Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( Z1 _$ A9 x; J1 E' AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: o9 [, o ]" HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ y1 l" g1 v# R" @" v$ w, q' pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. m* M" x A+ P) b1 }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 x) c7 u& O( @, `( D" R; W. @; X
0x00, 0xFF); /* configure the clock for transmitter */8 I: y. P7 P* D N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& i" A% K1 S2 T% ?( A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 X2 r. u# Z% y4 O& \/ V {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 {# N9 M2 J1 Y' q1 ?; {0x00, 0xFF);
1 p2 I: `$ n0 v# n4 ^
6 Q" f9 F' Q' _* i* x8 @6 P- I/* Enable synchronization of RX and TX sections */ . O, @8 U# X7 g3 [3 ^ F3 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) |6 Q- P! T$ `, @" DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ s+ d. f" ]: h6 {* L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 M, I$ E& S3 {0 j! c6 f/ |: E7 B
** Set the serializers, Currently only one serializer is set as. N' n' [+ [2 O# k8 m% U9 v
** transmitter and one serializer as receiver." @- L5 I, d) K% ~
*/& v3 z, E: |0 n0 @, }9 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 u- P( m* N1 i6 kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 z1 z1 H! M9 I% Q+ x3 I
** Configure the McASP pins ! i- M9 a: }; d% U0 O% T
** Input - Frame Sync, Clock and Serializer Rx
6 i! z' l- Q0 \# }** Output - Serializer Tx is connected to the input of the codec
! V/ H5 ?/ n3 W+ B x4 f*/
7 s: a/ z: |8 V* i; E3 g# F+ C2 _1 xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& x: v/ D! B/ O( Y3 b+ N |3 p* ]/ c- u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; r! n3 D, P4 j4 Y9 f* D; i0 wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, k' X/ ^" R$ I- z$ B| MCASP_PIN_ACLKX* }" I7 [4 ?/ k% X: }0 Z9 G
| MCASP_PIN_AHCLKX
1 `" ~. F8 a1 _( U8 H3 z# _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 ]. S5 e# w# {5 OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - ?, w, w, C' z/ d4 p' A
| MCASP_TX_CLKFAIL % x! _9 {" |9 o
| MCASP_TX_SYNCERROR0 U4 S4 S1 l7 ^- H" y5 i) }* M( P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * w+ B3 q: c6 B7 Y6 H
| MCASP_RX_CLKFAIL
, z8 k6 T8 H# X( U8 d+ y| MCASP_RX_SYNCERROR
% n8 \! k! a, w; G& K1 Q2 h z| MCASP_RX_OVERRUN);" v3 g7 m- Z5 }: h N0 c2 x, y0 Z
} static void I2SDataTxRxActivate(void)
1 a/ o! I4 Q7 J7 x3 F' [{4 F- b2 R; D! }" B9 g. z
/* Start the clocks */
& v L, A! k# I( F6 M) H4 U5 x9 q. B- fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& M _' v5 G; z# I8 d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
D" l9 ]' J; Q" C/ ~0 I0 y& PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 q) B. d6 f2 L4 |9 L. F# b
EDMA3_TRIG_MODE_EVENT);
* P1 v4 z1 V V* eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# A% }! E' b5 l( C6 w1 ?: FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ d* I+ U7 c9 T4 L9 i/ g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- q4 `6 D7 ~& b! {9 {, p, ~, fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 ]+ Z% N5 W# Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 H" \0 y( C" `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 @3 O$ Q7 e0 V+ Z# d# {/ H5 W1 \2 PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: k+ A, a6 k/ I+ ^! Z: E: L( ^} ( m8 g' B9 r7 m( c8 Y) `4 z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ~3 w2 H! Y) C& j& z
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