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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 |& O6 X' A/ u5 ^) x# ^input mcasp_ahclkx,5 v* j, e$ ~0 i k
input mcasp_aclkx,' x( t, m: b5 q# q, v
input axr0,
& h( F$ A7 K! B9 ?
/ [+ I# A. ^: |* F5 i9 }5 ooutput mcasp_afsr,
+ l4 i' q; M1 v7 `+ goutput mcasp_ahclkr,& g. V+ X8 S+ r( X6 D, n! Z
output mcasp_aclkr,
, R7 A4 j$ @5 Z+ e7 Woutput axr1,4 r; r+ a# {2 D
assign mcasp_afsr = mcasp_afsx;) C* w* D! z" E" C
assign mcasp_aclkr = mcasp_aclkx;) s3 A. q( |" y& M) |/ y3 q
assign mcasp_ahclkr = mcasp_ahclkx;
8 C! D% |. T1 e7 }assign axr1 = axr0;
) N) ~& W! J9 Y( O' m- ~& b+ z
! O1 X: f/ H: U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # |$ U! K2 j/ S' G3 v* O
static void McASPI2SConfigure(void)& q" x0 N. k( d! V3 L/ K, j
{" J0 Q1 e4 F( c. A2 i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 e: T9 Y9 \4 R/ HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) J1 T7 y% C& |) C* W: c$ K y+ MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( n6 Y; x% i4 l SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// @/ C- X: w; Q+ F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' @8 h" o5 Z, QMCASP_RX_MODE_DMA);. ~" R5 _" [' i z; V) v9 p5 J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 c+ z6 k' H! _: E# M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# p* M# l4 z0 }: G" G9 ? v5 A; i. PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ B9 g' R& w) B2 U* BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ C: b5 n1 }6 T# A. v4 `- UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . Q6 I! p, R, q7 V5 ]1 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. m4 Q/ { y2 _+ ~. ]# E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 D# B, D: [/ s% o- P2 C# l/ tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 {7 @ v+ E2 e' T: m# ]8 |0 P# B/ FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ ~4 D" j: r5 D. c7 ?5 g0x00, 0xFF); /* configure the clock for transmitter */! m( b+ e+ k. K# S9 w2 [! f$ j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) Z" L% D+ V5 l' h. f# F* C- U3 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 ]+ X7 a% Y9 X- d' ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, M/ n2 }% R9 A' e
0x00, 0xFF);
, d* V1 j5 j) }$ Y, `6 l/ A! l
) u' e5 ?8 S# m4 V1 E/* Enable synchronization of RX and TX sections */ / `" K& T2 ~9 q& h8 x+ l1 G: j* U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* L5 H- ]8 l" p: _/ M: oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" w; O# l" ~& c5 D3 Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& c! {( j) K- i5 {! C( ~. S: C# y
** Set the serializers, Currently only one serializer is set as0 S' C x2 y7 s8 z
** transmitter and one serializer as receiver.
9 K% r+ k5 l- s, L; z" E) I*/
9 E: F" B z. t: \- {, ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 q9 ~. P! I1 W7 B1 p" V. ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. k3 J- P& h0 B! C2 l# ^$ _! T
** Configure the McASP pins
" w9 [1 v: D$ [) R** Input - Frame Sync, Clock and Serializer Rx3 l+ y9 m3 s3 `$ G, w/ N$ {
** Output - Serializer Tx is connected to the input of the codec ( d6 d3 }0 R; F8 J( t& W
*/( U, f. a& i2 O, v0 o; a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ ], e! P) m# m6 b# zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! S: p! o- W+ f& @7 ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- t+ Y g! H: g5 C) Y/ H5 \: t7 N
| MCASP_PIN_ACLKX
, F& c6 g4 w s: M% O9 v- x& H| MCASP_PIN_AHCLKX2 P4 `+ L$ j( A5 d! |4 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& M% X& v% R9 ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 ^' d0 Y9 i" n2 \% O| MCASP_TX_CLKFAIL
; H6 B, q! D, ~, M| MCASP_TX_SYNCERROR
) j6 w# k$ i7 j+ K5 B$ {+ G1 o8 a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) g4 i; Y0 E! G% _5 d
| MCASP_RX_CLKFAIL
6 H, v3 T2 f; Y: [3 v; y| MCASP_RX_SYNCERROR
/ }- K8 c+ p' V! `| MCASP_RX_OVERRUN);
# v& H4 R- {3 `9 y2 r3 \} static void I2SDataTxRxActivate(void)$ U/ Z4 T: w- k/ g
{" @! u; u5 `- L, o' r, {, ?8 v
/* Start the clocks */5 p- C; E% X4 y6 k O% v3 v+ _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" b+ q/ H4 X$ B! L+ Z. uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, W' |! V; W. Z* k& n+ d s% GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% D) q0 `5 K' ^
EDMA3_TRIG_MODE_EVENT);
1 S7 z% o" x6 |* H- IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # k4 g* j" k2 D. b( R& B N0 h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" t5 H0 K" M6 s/ \. y3 e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, a- h( F: U; T8 u: x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 d6 ~0 [4 j! l& t) ^2 }: `- a, j" X' q8 |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 @) A2 V9 J& C# Y+ [- J% D3 ^9 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 [) Q& G9 V& s9 u' J; O4 ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 l7 x" c' P( J" y} 4 H) R2 X* Q E7 x* i* ~- u4 G, A6 y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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