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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* s7 ]% o( G6 `! x9 ]2 U! Iinput mcasp_ahclkx,
: [0 P, F# y0 k% l8 _' d! xinput mcasp_aclkx,
# M( E1 J$ P' V! s. ~input axr0,
# w* f4 w ]6 S" y
/ w9 ^2 s3 @# W. @output mcasp_afsr,
5 l5 _* h3 K* |output mcasp_ahclkr,
4 t2 j$ ^( B9 ~0 }$ Zoutput mcasp_aclkr,
9 v3 N" j4 \& o6 y1 Moutput axr1,) a2 F- s: q% @" c9 `
assign mcasp_afsr = mcasp_afsx;
" I- ~/ E* E5 ?! bassign mcasp_aclkr = mcasp_aclkx;
4 O Y' {0 Y% }. F- R* lassign mcasp_ahclkr = mcasp_ahclkx;
- E2 n y. p+ w D. z: Massign axr1 = axr0; , t' ]% I1 _6 b0 B- e& {( Q
3 V% [# O. F* h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; m8 g( n$ u- r: L
static void McASPI2SConfigure(void)
9 V$ w/ z+ a7 p; v! i# c{
# m: W4 f6 v8 o2 `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! r' s$ y/ N6 E9 K: @: Z4 SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 \* S9 R4 V( WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: X# L9 b6 g+ G2 D4 e$ fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& K1 l) X$ W% W* \# D) G7 B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 |% w0 u6 G& s) t- t! dMCASP_RX_MODE_DMA);
+ ]$ `" ], K. n- Q7 N0 m! {; R6 q8 KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ v- G# w6 q2 V- k* c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 F0 ]# R( p* Q+ R! G4 J0 MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% ]$ i A" n( L+ @- }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 E4 n3 S) E/ O* c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 u6 \) s5 I/ E% b) v& \8 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* T" [) D* V* l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 F W% d8 ^) v; M1 t8 l. H) E9 SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , C! I9 D: ^; g9 j% y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 w/ S$ I2 T6 E" u9 A0x00, 0xFF); /* configure the clock for transmitter */$ ^2 c+ R, a; U! N! A* y0 r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' t: r- r9 O. ^4 HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * ]8 S% N* O/ o2 l. M- U$ ~" t4 h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) f+ c' p$ Q1 O/ v; _0x00, 0xFF);
% K: q* f# U1 q' h
7 P" x3 @8 H+ |0 l# }/* Enable synchronization of RX and TX sections */ ( N; B2 i1 p4 \; h- X$ C+ M2 L3 b: k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: H2 v# n& f- F1 O/ R0 n, [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); U* ]9 N0 R. `* b% g/ B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: H0 m \* w4 r. J1 }
** Set the serializers, Currently only one serializer is set as: O( q' h# U, s( P, f8 u
** transmitter and one serializer as receiver.) r' V& i# M4 z' A! x
*/# N+ f% n4 a: @3 j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 J# g# ~( O$ E+ d3 `4 z% Z6 hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
e. w9 `4 }5 f: C** Configure the McASP pins 6 `" \( A7 z- g3 E2 |0 b! J
** Input - Frame Sync, Clock and Serializer Rx
a% d. L' k: @( v, J3 f** Output - Serializer Tx is connected to the input of the codec
t+ H* t5 e. R0 G- @*/
! ]: E+ Y; \ d pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: E* B! g5 \! {$ ~* ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ K9 j g- f* o: p9 d( M! ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' N" ]' s0 b" n, y; h
| MCASP_PIN_ACLKX/ ~8 `9 n& x$ s# O1 N$ a
| MCASP_PIN_AHCLKX
: _: K8 B4 I3 ^) @6 d& y8 q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: D+ A, `& i1 v" x; b9 Q+ b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. w: c- q7 y5 ^& P3 K* r% F+ U| MCASP_TX_CLKFAIL + \/ r# r w* W% f S7 B( y% l
| MCASP_TX_SYNCERROR! u' W M. i8 H7 c7 _* ?& g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( l$ v, j$ R7 U9 S! M| MCASP_RX_CLKFAIL: t' C, Q9 ]2 L' x/ {
| MCASP_RX_SYNCERROR * t. o0 r. c! o7 ?: m# ~5 n+ z/ s
| MCASP_RX_OVERRUN);6 ^) l7 p6 D3 W/ C7 D1 q4 d
} static void I2SDataTxRxActivate(void)# o# ^/ B! J6 `
{
" A! m' U5 Z9 o: g" _% _8 g/* Start the clocks */+ v* ]& Z- g/ ^- Y% H: X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 d/ r& ?# |4 X' A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& c) Q+ {7 M$ A& }8 e3 o3 j3 w2 B' AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, E7 y4 v5 v9 u8 R
EDMA3_TRIG_MODE_EVENT);' y1 E+ ]% v2 e# _) z" J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 |, R6 w# i0 |+ H. N# P- h& kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: ?; t$ p, a( Y* d( o! z9 c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ b, e$ P8 b* ~+ j J8 M2 q% }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 V) c- m* i* rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% q5 m' y2 V/ ]7 Q# ^- N; @ Q1 ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! R# `- @5 Z* t# a7 x; k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' `, T$ `$ l0 e; H}
* }) a. W! V5 v' q7 S# J1 ?* |5 e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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