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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- y' r- C$ ~# M# E$ [input mcasp_ahclkx,) G- C6 A- U+ v! b. j) `, E
input mcasp_aclkx,
4 V7 e9 O6 G) r. p3 w9 Ainput axr0,
. v5 S! V8 b2 B! \: x3 _2 G5 t8 |0 J, v
output mcasp_afsr,; C0 D$ z8 X+ y9 t
output mcasp_ahclkr,
$ } u `3 i, J& youtput mcasp_aclkr,: |8 W, S0 |& R ~" h
output axr1,
+ m7 P3 j! X* Z/ K. U, c$ ^9 Y; ` assign mcasp_afsr = mcasp_afsx;$ n, [2 Y& K% }9 W) G6 d
assign mcasp_aclkr = mcasp_aclkx;
8 K. U e2 a+ g' v- {+ Lassign mcasp_ahclkr = mcasp_ahclkx;
0 y! n* |; f2 k+ P5 ]6 `8 B, massign axr1 = axr0; % h. z1 b1 q% [7 `# p
) ]1 e1 _: J3 B" e# k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 w) Z/ c/ |1 C h( f% |5 G9 a& astatic void McASPI2SConfigure(void)" R! ^$ ~) E$ D: T+ f" v
{/ p$ K# K% U' k) G& l( y0 d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 ~" J- s0 y2 T# N2 LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, ? E/ W6 ], g- e& JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, o3 ^- b* F* X! J7 W6 m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 N( ~. v8 g4 X t9 L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) B8 \/ a9 Z& x: e- AMCASP_RX_MODE_DMA);
* }+ Y9 ~+ a$ wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. Y% w# V$ u# P) zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 F5 [; r, D6 a9 S' KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 V- N# z& `" [4 z. eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ q( Y' C8 a' B9 a8 oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: B. C2 N& |- ?( wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' v L+ x& P( o' o* d% D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 y9 e* L* J& s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 o. D/ E1 ?9 {0 ~8 v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* S/ T1 g+ D0 S( t- ^0x00, 0xFF); /* configure the clock for transmitter */7 \8 B r( h0 a& x7 I( d4 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- I# s7 o9 ]5 r6 F4 c. @9 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 W/ S0 [4 u! F( u2 } h6 H" E4 e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* j) p4 j* y, [0x00, 0xFF);
: ^* d& Q# W$ N+ M; f4 h
1 M: {3 X( J- V/ F/ \2 x, E/* Enable synchronization of RX and TX sections */
' p( X. y5 ~. s* w2 |( M8 ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. Y' b! B' h3 ~) J5 b G1 l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 B* f- v. h8 s- l5 b$ x% K( R& v0 `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 U! w/ K$ c# u; |/ Y, D+ {8 f d** Set the serializers, Currently only one serializer is set as _8 L& ?/ q3 q% U
** transmitter and one serializer as receiver.
3 x% Z9 T- N1 m, M! F" {* u*/. M, C6 ~5 t* c8 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& O( h8 v3 S6 P- V. {+ ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 z( O: c5 G) ?; F) r
** Configure the McASP pins
3 w/ c5 L. F" G( j** Input - Frame Sync, Clock and Serializer Rx* q' s3 d) n- t" |
** Output - Serializer Tx is connected to the input of the codec
2 I; t) _) ~8 ]# H7 a; h*/# v$ z! C. t( \7 R# ?" x: d O P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 g6 ]# }9 o6 EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 X* Y: X" G. L! j% ^3 HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; b7 e0 O. i' E/ G: b; `
| MCASP_PIN_ACLKX& C3 v0 y3 w0 M8 q
| MCASP_PIN_AHCLKX" d3 Y V, g* z W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& K+ p: k, S- f+ O2 }/ c2 SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 o0 `. E( Z. S' x| MCASP_TX_CLKFAIL
# v. V* i+ D1 w/ p: y- _7 {| MCASP_TX_SYNCERROR* a* N0 n0 D" @3 {4 T, J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 N7 [/ y: H$ i! ]3 \( [2 m
| MCASP_RX_CLKFAIL* G% ?4 h) ?: `7 c3 c+ ^
| MCASP_RX_SYNCERROR * B" L' X3 m M5 A T
| MCASP_RX_OVERRUN);2 L8 b, j/ u9 w0 R& }
} static void I2SDataTxRxActivate(void)9 G( b4 L. K2 Q
{; o& J. ^0 X0 H+ k- r
/* Start the clocks */
! k+ @- H6 S8 c% `; Z' VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) u" I- f2 i6 r1 C% L3 ]1 x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' s$ G7 ^' I/ G4 m! M5 t% |6 a0 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 \. u2 Z% o! }/ |2 `& iEDMA3_TRIG_MODE_EVENT);
3 q1 g* J' U9 W6 f1 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 Y$ ]- z; k4 `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 r9 R8 g* b* l. N$ u ` I# i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% q+ D/ E& m$ \& |# L/ w' J C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 ?7 c3 |2 t, @4 A% t) |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 S! P/ x9 z3 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* J1 g* R0 W2 E& `6 D) BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 S* Z& I9 k9 N% o/ s( z
} }4 {6 a+ \$ M4 S4 z- |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 l& A' t, k* \
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