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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, |# X9 S& l) r: ~& c( Dinput mcasp_ahclkx,4 @9 ^# V2 n! S. n: ]7 X o
input mcasp_aclkx,
( Q' e c/ i3 Tinput axr0, L9 M( S: p; t! z8 a3 }
" Z% a; Q8 z. X& \( goutput mcasp_afsr,- [6 H. X: p7 a2 l" a9 K: ^
output mcasp_ahclkr,3 @& [- X! j( f+ N c
output mcasp_aclkr,6 Q: q- Z9 _! n/ h* T& s
output axr1,
" c: w9 v, \- N$ }+ f assign mcasp_afsr = mcasp_afsx;. d# R( p- D* \. N& ~6 D2 [
assign mcasp_aclkr = mcasp_aclkx;" L# ~& s" g. r# B6 s( j4 l% }
assign mcasp_ahclkr = mcasp_ahclkx;7 s+ D. {' ^1 E) `1 U0 L
assign axr1 = axr0; ) i) [, I7 |$ I1 y
& _, @2 v" c: Z3 E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " i. p: ~. l# i) a; _8 u
static void McASPI2SConfigure(void), B7 L& f3 Y5 A1 ~0 b! K
{
7 h7 R5 j0 i6 oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 J/ ~7 o" g7 N! P0 c$ S5 n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 _+ o* f+ E% h3 ~# }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* ~! j# s% |, M, n+ Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: W& q* }" L! A9 N; M& S: d: v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 [# v* ]+ b) W( k6 H
MCASP_RX_MODE_DMA);. b9 i D0 ]% E: J$ X7 I4 G$ N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 I; N$ t' N) y1 C- }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 B+ W: w2 t5 r- a& T ]- `2 f) |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 h A. U3 h, _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( }* I2 L f; c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ a/ x2 c( t) o" MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& E* c. o. b$ L" ] AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& C; Y' ^" N& ^+ j, K0 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; E. }% E7 s" y& s3 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 ^- U0 A/ i0 v' R0x00, 0xFF); /* configure the clock for transmitter */) ^% P) ^' \* Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- v- @4 L+ e) S' @# d0 N! j0 L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. ?+ i% x9 b, R( e+ jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* Z3 r+ h+ v: f5 ~& m0x00, 0xFF);
; [9 q# S3 o4 J- I ?9 j7 ?
1 g8 S& X2 s( }: |' Q/* Enable synchronization of RX and TX sections */
: B. D; Q* e6 ^% j0 d' L6 O; _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 S# o" D1 _: h. N& R+ Y' v9 Z/ A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 _: q* g' g* j& ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 S! W$ K, s+ r1 s+ V2 n** Set the serializers, Currently only one serializer is set as1 p, W$ X$ H4 Q
** transmitter and one serializer as receiver.
$ ]; m0 s5 Q( @*// B+ ~( c% s+ v9 ^; ] S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 ^ g# K: F8 x& _/ M$ w8 w# g+ NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; K8 p! c+ }3 a' ]
** Configure the McASP pins
- s/ L) \7 w% J" l. |! G** Input - Frame Sync, Clock and Serializer Rx
2 l, g* f+ ~! z9 A& |8 j** Output - Serializer Tx is connected to the input of the codec ' b* a. ]9 D. [3 ]! H
*/& w& ?) q. w. O; G- D1 t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 I0 D$ P8 w# @" ?+ {+ o: D" y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* z4 U' y2 k; {# X5 k, ?& }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) V' ?+ u7 Z" b% ^) n& s Q, n
| MCASP_PIN_ACLKX
. t5 S0 P# i: p7 q7 G: A! ]| MCASP_PIN_AHCLKX9 B( y+ G% ?0 ?- H, r' Z0 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' _" X! \! L* [$ h5 d. AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * u/ h K# y T3 i" q2 b1 r2 g6 r& ?& P
| MCASP_TX_CLKFAIL + H. I2 |4 z" Y. M9 \
| MCASP_TX_SYNCERROR1 \& ~! n; x7 w6 M/ ?+ h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 P# I/ k2 x* S$ N Q7 V| MCASP_RX_CLKFAIL
5 ]7 v! I, A& y2 i- c; z$ Y| MCASP_RX_SYNCERROR 1 G" {$ P/ w" Q ~# ]1 R
| MCASP_RX_OVERRUN);
( h/ p% M/ u+ y6 T+ M. s9 q' x} static void I2SDataTxRxActivate(void)/ w3 P x) L& ?0 L/ I7 O
{2 b) H* c7 _8 s6 B+ ?
/* Start the clocks */" ]* `( q+ N- w' {/ u8 W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 ~) I- V- i/ L' B5 |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 J6 y s8 c" H T6 l# sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( h5 P1 _" O8 ?' w7 T! i
EDMA3_TRIG_MODE_EVENT);% j$ S& _+ S8 G, [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 L8 y. n1 [% z" PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 @! D! I% t" [% \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 R/ {+ T- H1 Q6 z9 @" t9 y# |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! I: A. W$ o7 ~2 I" Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- Z! ~: k2 O; C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 ]* X7 ]+ L' \1 x; I- f4 `: S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' X+ n, \) }! J}
# {9 F2 W8 J! e9 E% @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 a- q v. K7 I4 d1 P" q+ n( {1 M- Y
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