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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% d' V; q2 ?. l9 k+ `& P
input mcasp_ahclkx,
u$ W3 p, ?4 U4 W. ~8 z0 V; s+ rinput mcasp_aclkx," w, k) j8 D; z. T
input axr0,
' J6 Y: N8 i! h; j7 h
+ b0 n; J9 {, \output mcasp_afsr,# w- j7 \* e4 m0 Q
output mcasp_ahclkr,
9 e& a' p- j Z$ `. j8 [. e9 B/ @output mcasp_aclkr,3 W% c4 I3 M6 p" U+ H' q' {* T
output axr1,% e: ]$ o# Y: V- \0 t1 V" R3 w# i
assign mcasp_afsr = mcasp_afsx;+ i0 ]4 S8 n% c* D0 H% N6 B
assign mcasp_aclkr = mcasp_aclkx;7 z( Q" J- G5 N7 q
assign mcasp_ahclkr = mcasp_ahclkx;! ^: B( w0 d! H; X* D
assign axr1 = axr0;
% K# o* \- r' J( I; G/ ?2 B3 ]# F8 n) f1 U0 z6 n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: e: ^' s, {# N) K# n6 p- Nstatic void McASPI2SConfigure(void)8 Z+ f- _+ j0 u/ H. ~$ K
{
" X/ \/ T; c1 t4 e# U9 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! j1 d0 Z1 {8 g) p7 Z" k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 U b/ @4 |( \* bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 V7 }& k, [9 K; q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 Q8 c' p1 B" w6 G" B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ J0 D' ~. y5 y4 p7 A6 ^MCASP_RX_MODE_DMA);* M d3 H; S* N! c* b5 j& K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ l [* {" q v# R$ \9 n3 jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! g I+ Q* P) f: H! j2 A. x* ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- F2 k1 A! _$ q% _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ v# y/ N% d1 k9 j1 f8 y' SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 [& d2 B8 j6 S7 G. C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, U9 e- W+ s8 v! D( \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! _' {* c% A+ ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( R: R. s6 O( T' {/ qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' [% s8 E, Z$ e0x00, 0xFF); /* configure the clock for transmitter */. j3 `4 o& s$ y U) G! ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 {7 Y8 ^, j+ d$ F5 U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 b, `6 J, B2 a; D( ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! C; Y2 U) o5 Q" T, a1 e' g% N! ^0x00, 0xFF);
6 x# o. x1 e0 @* l# B* u8 V# U: |5 D& `9 G8 \+ F
/* Enable synchronization of RX and TX sections */ : S+ X2 u* k4 k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 R: ]* C- Y& G1 s9 Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 `4 e$ Q, N" c0 J4 E0 |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 A! A: J) Z) U7 ^, e6 k4 R3 v
** Set the serializers, Currently only one serializer is set as" ]4 \9 h* o7 Y% |# N3 t- E
** transmitter and one serializer as receiver./ x/ e4 y) s- s- {! |
*/$ Y: [* X. D" P! q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: n3 k3 P+ d: p ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: j4 y0 v9 ?/ [% @) F( M** Configure the McASP pins 5 D& P3 n+ |5 H' e" Q% v+ Y
** Input - Frame Sync, Clock and Serializer Rx
& w8 S- [* A3 {5 p% W3 l# U** Output - Serializer Tx is connected to the input of the codec
& V1 v4 L8 s* C$ |8 A& G) ~*/
% |+ `8 Q1 i+ {( P4 c2 I/ d5 MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 V$ _% i. z/ G$ J; P: K9 Q$ hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ k5 `5 e0 P/ l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# q) k) C9 x3 D% [4 }/ e: L
| MCASP_PIN_ACLKX
* Z, q+ x: [ u6 b| MCASP_PIN_AHCLKX
' k% \2 r3 ]5 n, h) ]7 k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ o5 t( Z @5 B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 S) K# `7 T' R5 \| MCASP_TX_CLKFAIL
8 k8 P: i* z1 |) A| MCASP_TX_SYNCERROR
. n5 [; Y8 _/ z8 h4 M6 P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' J# R; W; P$ A; a
| MCASP_RX_CLKFAIL
; s# O/ ~( x5 A- ?7 v| MCASP_RX_SYNCERROR
4 l" J. v5 w( ]1 |' f$ r% O| MCASP_RX_OVERRUN);0 d6 q8 W2 B6 N* m7 q# B" `
} static void I2SDataTxRxActivate(void)
4 r( J, ^/ L, W* g" i+ g{
' f+ ]; R, p/ H1 L) Q) G/* Start the clocks */' s' @! k( u) Z/ K7 t/ j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 z* W2 G: Y$ j7 ]) EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& }, ]1 O( d' ~5 o) ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 L! k( ^ T9 ~8 o, tEDMA3_TRIG_MODE_EVENT);) c" u7 l: w6 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 x7 N% t; M6 }* b7 x1 f: \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 ]1 i3 @1 ~5 ^2 Z: L% C4 dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 G4 N/ |" ~6 j2 g/ K2 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) n, X/ n. q. L% Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; h9 ~7 y. b$ F l# W* Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" Z+ @! |* z( S- M" CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 X' A& k! C" V6 ^8 J
} % N$ r2 e1 ?' k( X+ U. n) J. C+ `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 t" }6 R! W5 P% |
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