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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' k. g& Y5 A4 t* f
input mcasp_ahclkx,
' i* d% \. a- u$ ~. pinput mcasp_aclkx,4 `8 c3 K9 H* F( {
input axr0,0 O6 x0 `) w; Z! e; e4 X* N1 Q
8 {! R# \$ s p8 h: G
output mcasp_afsr,
|0 L$ H3 w/ H8 r2 A: uoutput mcasp_ahclkr,. j# Y* _' h$ E7 J: N9 d' r
output mcasp_aclkr,
' h6 y" f5 G: H& V4 M$ b! routput axr1,
& \9 W5 C# F7 G assign mcasp_afsr = mcasp_afsx;6 y$ G# j6 j% Z! Y
assign mcasp_aclkr = mcasp_aclkx;
/ H5 l& o9 g# E @' V$ q( ^& Qassign mcasp_ahclkr = mcasp_ahclkx;
. [7 N' O6 k3 d. i0 {5 Gassign axr1 = axr0; & w. a8 _% H l* \ n- i
6 x' A7 K% z$ S6 |5 Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 n0 {4 i. R1 a9 a2 G/ ]) F
static void McASPI2SConfigure(void)
* `& a& c* O9 i2 F{; p5 ]( \2 \, w& f/ ?+ v5 \1 c0 j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- S) y1 e4 f" B7 F. JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# N6 C! D1 }5 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 h. j* x1 n. }: v5 _: [% \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 y% S1 h9 ?% ^# U4 O9 ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ M& `, d0 ^& S' v4 ]9 aMCASP_RX_MODE_DMA);) v7 k8 m* n1 e% J1 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ D: j6 l; a. J7 _% D/ U9 [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% z9 O+ G4 K+ D q% ?* w# l: U9 hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 U& I- o: J! e' Q5 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# i; C0 X. m1 q* E( M" N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ R4 N- p( {/ f! G& R' U1 VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( D' C3 U1 Z/ I$ s' @7 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# u" l; B' c% E! s) y, aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( c. t5 Z* }* u5 t; \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 g, Y+ {0 Q0 R% ^ c* S0x00, 0xFF); /* configure the clock for transmitter */; O! _4 `0 \, d5 C* s. a0 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# j) K' G6 y$ G; x% M. Z5 ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' R6 _ h9 ~8 O% U5 S& @, b: V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ O1 N! E* r4 }3 l' [! U* f- D0x00, 0xFF);
! I! m( A+ ]2 a- P/ |# y7 W( s. X* {( s, x$ O o
/* Enable synchronization of RX and TX sections */ . C2 E0 S" }; Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ D4 Z3 f/ w4 D3 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 B2 K+ I0 }+ z/ a# e- C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ U, j4 t" E8 \9 l) e* q** Set the serializers, Currently only one serializer is set as6 B! D: {7 E1 o @+ y0 j1 Y
** transmitter and one serializer as receiver.. G+ J3 o6 @/ m' F
*// {/ o% @0 j. b. j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 }1 [9 }+ U: }6 R9 l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( T, ? W# t- r7 X8 b
** Configure the McASP pins
. }3 \# m# H' _8 A6 m+ c9 d** Input - Frame Sync, Clock and Serializer Rx
7 r" C8 V8 p# N! A** Output - Serializer Tx is connected to the input of the codec % s; A$ e/ J/ ~6 V$ A4 K2 {8 e
*/1 `* S" u, Q% V/ d8 {: K) F! C3 Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( _8 L- ~. D% |/ i: v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. o/ _1 R6 G' Z# h2 @" HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 Z. c, X( z6 I, h: i Q| MCASP_PIN_ACLKX
/ b" K' U& R. | M/ f- ~| MCASP_PIN_AHCLKX- g; J" F$ c. {* T2 N' s" A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 u L7 K) Q% {2 ^4 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 ]8 C$ i3 l0 S. u. q
| MCASP_TX_CLKFAIL
8 ]$ ^7 ~0 f" ~# r0 b| MCASP_TX_SYNCERROR k9 |" i ]4 p
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( {! Q6 m; X9 w$ ^| MCASP_RX_CLKFAIL+ D" B4 ~. N( x3 ~# b
| MCASP_RX_SYNCERROR
- e) h, x- {' J/ j( K9 A, l| MCASP_RX_OVERRUN);/ Z6 C- O! N1 [% ~& z+ E- Y$ a- h
} static void I2SDataTxRxActivate(void); Z# V5 Y1 W! s4 X% l
{+ G( V; d* F' T& ^2 h
/* Start the clocks */
( E) U4 R+ b4 h3 e5 |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 ^# }0 A' l) _2 b {2 b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% N$ o1 r" V4 N2 I/ M+ y9 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 z: a' [3 Z" |/ y9 f! IEDMA3_TRIG_MODE_EVENT);/ u4 b ^- \8 m. H2 v6 c9 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. { O8 ? b+ ~& i7 ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 c9 |& e9 U1 c, @8 D" \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# ?; Q9 a) w5 X7 U( L$ w7 r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& ]; {$ N2 @ Z1 L7 k/ r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ P, a; h% C0 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
~: c8 T x4 u$ ]) \0 E. a$ R9 HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 U( b+ U6 S3 M+ R/ |
}
! a( b; ?, p g3 K0 }/ U" D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + n3 ] ?) P) ?* H& }# k
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