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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, h1 g9 j# i+ E, ]4 jinput mcasp_ahclkx,
- l. F3 J! F. D+ y5 x( Y8 g7 ]& qinput mcasp_aclkx,% g" S2 w, a6 o5 N/ f5 S* `
input axr0,
. t# a# o1 p( {0 F j: E2 @: C N: ~& ]
output mcasp_afsr,$ u0 \4 {& ?1 m h" f) {, e4 M
output mcasp_ahclkr,/ R* C# E5 N/ ]
output mcasp_aclkr,
) R* r. T, b" `! h- voutput axr1,% n+ z1 J1 C& [, @
assign mcasp_afsr = mcasp_afsx;
- H6 A6 f2 R' G+ l5 I4 L8 U1 kassign mcasp_aclkr = mcasp_aclkx;
6 c3 R2 }+ ]$ u$ D" B: jassign mcasp_ahclkr = mcasp_ahclkx;% |" @3 ?% M6 B
assign axr1 = axr0; - h- _) Z3 Q7 B2 p% y) k
3 ]' V8 C$ v0 v# M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! M" y' d. w, ]' f; z' O
static void McASPI2SConfigure(void)6 X% ~ `; b. Y0 Q2 R
{
7 Z& n3 |5 k& W& a2 X# XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 q( U2 U1 ]7 U1 i% Q; A# E RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! p# u/ \9 Y/ S0 K8 @+ y: lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! J0 h& d( ]0 X) {; m. _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: S+ ?4 L$ ~9 ~" rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' P4 E2 T( H7 \ mMCASP_RX_MODE_DMA);1 O5 U- Y6 B- Q. B8 |/ Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% E2 t$ G. Q' [% C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ p$ T" v: {' b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * I- Y" @2 `& a' r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 P( v$ ]- g) `+ r) v$ }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( f" k, m% w: {, CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, a3 ]+ C) [& `4 F( L; e7 oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. R& {* M0 M. `# W' yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , G0 R% {, V6 V0 ~+ Z& @( l) K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
Q$ z! x. P+ u7 e: O0x00, 0xFF); /* configure the clock for transmitter */9 [& K$ g8 G4 ?. y' g6 s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 v( y/ Y* w% A& ?' S8 hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) j3 d9 m% D" i$ DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 ^8 F2 A1 n2 @& I. E% T% m+ f
0x00, 0xFF);" T3 r$ k( ]& L- G
0 d i4 s9 j. n; M2 y
/* Enable synchronization of RX and TX sections */ ' ]) _1 ~1 D0 z% C4 o. i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( P; @; }: ~, I, H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 v) x1 g! L" n6 w& k( wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ Z+ A/ K& c' q5 o8 K# Z** Set the serializers, Currently only one serializer is set as
5 ]) @( \; I4 P" @; o" n** transmitter and one serializer as receiver.! p% n! b, m9 H; C+ t3 x$ h
*/9 F# n; `3 j/ I- j8 Q, Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 t( ~# u7 X# N# f; W9 Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 O- V7 Y' Z0 H F2 G6 n
** Configure the McASP pins ) e% J6 L- x- W# l
** Input - Frame Sync, Clock and Serializer Rx ^* R8 C+ P9 R# W
** Output - Serializer Tx is connected to the input of the codec ) `) ]6 l1 C: k* G6 x
*/
2 [; a: `$ Q- g U% O' CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ R) _$ M! {% U, ?' e9 ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
g% M( s) R2 L; u( p; kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! s$ G0 D; p6 Y$ k| MCASP_PIN_ACLKX
- Z4 c- H& u F6 r% l| MCASP_PIN_AHCLKX) X4 O/ L. M" n, A# r' {) i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 {" V% ~9 n* L: o4 M4 i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : F7 s6 H; W& L2 p
| MCASP_TX_CLKFAIL
5 b" g. Q0 J& y4 a8 ~6 d( W| MCASP_TX_SYNCERROR
- f/ ^; t9 C3 w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, ], Y4 \6 `3 C0 `| MCASP_RX_CLKFAIL) g3 M" l2 ?& f
| MCASP_RX_SYNCERROR & g8 t+ M& d8 ?' t/ j. l
| MCASP_RX_OVERRUN);9 i: [: ~ `! Q' |6 z( x
} static void I2SDataTxRxActivate(void)2 i) p5 W- ^( [* _3 x, C; q
{
T: c( Q: m5 @. A* V/ D. Z. ^/* Start the clocks */
& s1 m9 A- F: yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% G2 ~4 b* B5 H1 M3 _5 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- D- f7 E: P; x9 `- ]6 r5 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 |& W! H2 ]1 n3 U& C8 x
EDMA3_TRIG_MODE_EVENT);: w" L7 x: o4 F" o0 D' C- P* d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 k1 X8 }6 M. C \( M7 b: N& q4 uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* Z/ H7 x' Y% D3 B: t$ R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# Z! y, N$ S2 g j6 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* D: A/ R7 v" O+ K3 w* O; L9 f0 P/ M* P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* r- g" ?/ j N* @! ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 \! d% q6 A! d3 l' X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ w0 F% e" q$ J% x: e; R" @
} }% W# W+ ]% k+ [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 _! P1 M8 N( E
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