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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 ?3 t: Q: U* Q$ einput mcasp_ahclkx,
3 ~$ u5 ~! e2 i1 hinput mcasp_aclkx,
; Q7 z6 Q# I& r& C' A, _ Tinput axr0,
5 i2 @ P9 \5 x$ @0 g6 C# w6 G/ f
' \+ W' A6 Z& | E" X2 `$ noutput mcasp_afsr,
/ X) k3 Q: N: ?7 I* H. Loutput mcasp_ahclkr,/ G% ~7 |% \" Z' j
output mcasp_aclkr,# X* P: P% P& T8 R8 Q) n. D( g
output axr1,5 q, b+ K. E8 U$ ~
assign mcasp_afsr = mcasp_afsx;2 Z3 U% {2 N5 o' v2 b
assign mcasp_aclkr = mcasp_aclkx;
, t) |& E3 l! s6 Yassign mcasp_ahclkr = mcasp_ahclkx;8 ?" e4 K& E, M7 v# ]' G
assign axr1 = axr0;
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3 A. M! S/ z j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 K/ v9 H2 b n k8 I3 rstatic void McASPI2SConfigure(void)
r* _& z; C3 }{" B, p, d% ~: A" M1 x0 Q2 ]) Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, X8 r _& U( N6 [4 e dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' u5 k9 t( v$ D% R' }) @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 l0 W N8 F5 U& d+ v- A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" f, U1 K( B \1 _/ OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. d S0 Z1 i9 C& D, {: `
MCASP_RX_MODE_DMA);! n, e; f3 d: m3 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 q. [" s& f j' G4 H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 X! ]2 q! q, z! j# f' D- E0 y* T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ u7 L r) c3 BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 Z! v7 n. }; A/ |! X& ?& t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, [* _- I' u. G. k0 i4 O0 NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) R% v% s w$ i6 M1 F( aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 Z6 n" V* h9 p7 ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) R, [) U, f7 N# u, H( E# L( z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' u- K" B% \& x6 {& o
0x00, 0xFF); /* configure the clock for transmitter */
" l! R% ^6 Q/ ? e: A! ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' }- _$ `+ N/ C/ T% }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: g! v7 N: n3 j a' KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 N7 Q1 \& p. @: b0x00, 0xFF);
: E4 g# D0 Y) N7 l4 P
$ o# |+ f) d4 z4 f" c/* Enable synchronization of RX and TX sections */ : E, V* M) z3 T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& P8 W* U) T& N% d8 d( G! U. R! Q6 ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ A* ?& _$ ~( Z4 N3 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 P. B6 V, y3 c+ ?" Y: P* I
** Set the serializers, Currently only one serializer is set as% f& b( Y6 n9 ?3 |7 n# W
** transmitter and one serializer as receiver.
2 \. E4 S: n: f( y' R. J*/
- j- n. D7 ~+ @3 ]* i5 \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( W+ u# e, R9 K0 M9 fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. \0 x* k' ]5 V6 R2 ^3 K** Configure the McASP pins
% _2 b3 N( S s7 `/ [** Input - Frame Sync, Clock and Serializer Rx
$ N% W( T$ O9 j+ A& H** Output - Serializer Tx is connected to the input of the codec 8 _. t% n/ g3 O, D
*/- d$ n, f' e$ J& W Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 G% U' n W; Y2 F, j, b! A* S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ E% r: Q* @& |9 m# c; x6 \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; X2 o! o% `! y, q9 p- [6 K5 j3 v| MCASP_PIN_ACLKX/ h+ ?; ~+ M* J/ ?+ q$ E- b
| MCASP_PIN_AHCLKX
4 u# g8 D9 K- n& I/ w4 D/ \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ ?3 q k* |' }4 [8 W# e$ N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 r# @. @/ f% q# ]9 T| MCASP_TX_CLKFAIL
# P( s5 s5 K* n" f, ~$ V5 I| MCASP_TX_SYNCERROR
/ E8 q4 f1 n L9 ^) [1 m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) @+ k# O& ^. g' w6 L) ]6 U
| MCASP_RX_CLKFAIL
8 l' a0 t: \4 K% ~| MCASP_RX_SYNCERROR
3 }( Z# g6 `9 V| MCASP_RX_OVERRUN);/ H. i L6 b" @; E
} static void I2SDataTxRxActivate(void)
8 l% j: M7 I0 u{
! t. o7 n% C; w9 s* }6 k/* Start the clocks */; w7 N" h2 ?( Z$ H: ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& ] u' `0 r6 U& F! j9 jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% ^/ x% i8 J$ [' J# U4 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 A3 e. p0 p8 E6 s, gEDMA3_TRIG_MODE_EVENT);9 H" M- z" \% G8 V* ?) }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 x3 \! }1 _' E1 O5 Y6 Q: zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
C- k3 `8 U1 {6 R- C/ N# x! nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% P6 `3 |4 a! F v! f- n/ JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ c8 H- }! d2 R4 v4 q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 k4 C7 u$ }7 x* ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( l0 z8 B( S' d/ T/ p, L; aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 U" _+ p2 K8 C2 r* i. V}
2 l; f. C& K h8 A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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