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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# [* I. w3 `3 ^' l# s4 e* s% X& t: tinput mcasp_ahclkx,
/ e `+ \+ d7 Q6 |0 Q* r6 R$ y* pinput mcasp_aclkx,) p. u1 ]$ d* t3 P
input axr0,
" W' D- {1 z1 i7 o- r! F" j7 Y
7 ^" j/ }- [! G! J7 x Foutput mcasp_afsr,
# U2 F, [, `, _2 i7 G Coutput mcasp_ahclkr,
! P" ~/ J1 k. O' H& g j, D3 [output mcasp_aclkr,2 g' n. E5 M7 `% A% j
output axr1,
, j3 b. v+ g* _% n+ c, k assign mcasp_afsr = mcasp_afsx; k* I1 X: |9 i! K) m/ M
assign mcasp_aclkr = mcasp_aclkx;; ?* V8 ?! F2 U W; }) V
assign mcasp_ahclkr = mcasp_ahclkx;
5 ]3 D; J% L. K6 ]7 vassign axr1 = axr0;
, v: z# o: b# B. C/ b8 W, [! B( {. o |$ [& G% D. i8 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
S4 B5 I( i6 xstatic void McASPI2SConfigure(void)
1 W6 h. a! I- y' e! o{: e' l2 ^" R4 k$ m/ s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 _: \, Y" M3 n- u% l) P8 d: V- Y8 }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 [1 L* z$ ]. ?' I& T/ n2 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 s" W& b+ q9 Z. _* ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 N' ]# I' ~% i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; u! @/ T+ v* S$ N5 ^5 f. EMCASP_RX_MODE_DMA);/ P: v: q6 {' D9 D* d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! \5 z4 A, Y: _% ]# mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# i, |7 G, J/ ?) T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " I& d$ X, o! U( x$ t: A9 ]* I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" h) E |4 j& z: m1 HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, H3 G) a, m$ _9 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 G {9 }4 ]; K: }0 V, ~: A' k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! |4 o3 x, g" hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % B9 Y" f: X y6 F7 ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( U+ }) T+ X# g3 Z i. m* r. [
0x00, 0xFF); /* configure the clock for transmitter */0 H( X9 U3 ~0 w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
V& n# j+ V3 i+ zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' S3 ~' z3 u; p( {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ n3 e& f! e3 y" T* C# @
0x00, 0xFF);% S$ }7 t9 D# v- F9 y
- V1 z0 m8 K. j1 w1 Q, g I P4 s2 |/* Enable synchronization of RX and TX sections */
2 c; w& O$ a$ KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. X; _7 U3 A) h$ D6 j$ b; w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 B/ E! B1 \' S% }. ?9 S8 P( V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 v% s9 W6 \+ ?, y8 u( o
** Set the serializers, Currently only one serializer is set as
2 g9 u i9 o% N. z* s' v( T** transmitter and one serializer as receiver." l8 o! M2 R3 e
*/% ?* |5 N5 @, J. Y1 @+ |" \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* V* G; q7 f& C3 [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 v$ k1 W# [& U** Configure the McASP pins . g; f- @. ]! g' I
** Input - Frame Sync, Clock and Serializer Rx
+ U! x: A% V! b! c/ \/ T2 t** Output - Serializer Tx is connected to the input of the codec & m) Y1 v2 c! G: u$ z
*/+ {. H! H2 N2 P& x# w! a0 k; Y: n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 S- H# r9 Y* u U G9 B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. u; _/ O$ a! g& A; q* c8 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 }, m7 N' g2 R6 R4 ~* [! c
| MCASP_PIN_ACLKX
& o' C% _* B8 E, B" A2 i| MCASP_PIN_AHCLKX
7 |( f/ b8 F2 k, t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- ?3 `, w7 K; ?; BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 O% s. t' X% H# a% _1 o' W B| MCASP_TX_CLKFAIL
& i8 S) Q% }6 s' [2 n |) X' Y. J| MCASP_TX_SYNCERROR' m7 m0 b* f$ U9 Z5 U, A! r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & ^5 _$ A( t0 P% \% D
| MCASP_RX_CLKFAIL+ z$ n: L( p J- w4 d
| MCASP_RX_SYNCERROR , G; S; [4 P% x+ E5 H: g
| MCASP_RX_OVERRUN);
, o0 c' ~. n: Y2 C} static void I2SDataTxRxActivate(void)8 W! e! z K7 M4 ^
{
3 }' a+ q" ^8 G& B5 N2 {/* Start the clocks */, X, u4 f& }# @6 n- z9 \* f; A0 t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% [, v5 ]- U+ k) b& ]$ U+ A1 ^* g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 \ @3 U8 _5 m- |& K; j9 @7 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; k3 O W% ^' v
EDMA3_TRIG_MODE_EVENT);
& V. B: f5 s1 t; D1 j# P0 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 |! d' D$ [" I* D! K7 ?4 S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 C" J" C A: i% p" K; L4 y" z) v, N% Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) k' G1 M+ P1 [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 a1 q8 ]- v5 s5 C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 U/ N& t% T) jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ v& l9 ?$ |* r* l) X G" o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! x& Q, s' J- Q: c; Q! g} 4 O- B( P2 Z5 m' W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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