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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# n0 y6 \+ Y4 }5 J0 i$ Ginput mcasp_ahclkx,
. I1 M5 c& V6 w2 h4 cinput mcasp_aclkx,
5 h9 a; R3 }2 V1 e+ Qinput axr0,* k1 o% V5 H2 H$ g' O2 a9 h
% h) ]0 s% J( t- c. O0 Goutput mcasp_afsr,
9 o m/ [1 D" N) S woutput mcasp_ahclkr,
7 n8 Z' u5 _' ^; H! ]) F( {output mcasp_aclkr,4 ~; N, O g1 ]% x7 t& K7 A4 e
output axr1,
7 L; X8 T6 h/ }) Q3 F/ p& B. G assign mcasp_afsr = mcasp_afsx;
6 ?3 D8 X1 X) b' j4 X% Bassign mcasp_aclkr = mcasp_aclkx;
3 M! L, N+ x+ \. Bassign mcasp_ahclkr = mcasp_ahclkx;% L# B8 X8 Z+ U) j9 J9 W7 }. O4 H
assign axr1 = axr0;
. o" W2 p/ A+ J' P. {$ o
& a9 W B5 A, z3 o) B" n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ u Z6 ^7 V- ^static void McASPI2SConfigure(void)
8 q4 u E" I! E' [$ I8 I{
1 k' C; T, p6 O8 X- [5 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ x N7 G/ A a; f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# Q/ e7 E* V, p* k/ E" oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) }, c2 G& i! w+ v: G+ y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( I* S: M( ^: Z7 L9 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ p: {. z# E8 e. J; o/ ^
MCASP_RX_MODE_DMA);
3 j- k3 O" B. R; P/ ?( _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 u/ N8 n* Y# |' b$ HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ D, g) t5 H2 I' i. O% S$ dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 E, f' X* p6 e! c, S) n& m3 KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 t& w7 j0 t+ }" ~: I. RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % S' X9 E7 A% @7 V6 f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) d4 _8 X" }. k' n1 d: X4 T$ k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- y- B* n9 M' H* [& m7 g5 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& _9 z% n- e7 D8 |4 \" KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& h/ [$ _! i7 ^1 G3 i+ ?0 N# [
0x00, 0xFF); /* configure the clock for transmitter */! G/ Q6 `6 e5 f/ x* ?' t% `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( R d$ @9 a: H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& M8 Q% C' X1 F4 G6 J* k, i7 fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, O+ M |1 s3 N# r0 r- W% y* Q0x00, 0xFF);
- ]# A' \2 ^- l/ E$ [' o g8 r" o7 u. U' {6 W( m
/* Enable synchronization of RX and TX sections */
9 [( ^3 C) ~( }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 U& x; @- x+ B9 K, n7 `, N) F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; Y) P) B2 w/ W/ @' ?9 w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 L5 m( Y* `* d4 L; B8 w! w** Set the serializers, Currently only one serializer is set as9 v2 j3 b7 V4 O$ M1 ~
** transmitter and one serializer as receiver.
( F" J! f, b* O) Y* W5 B! }# ?*/5 Y! o5 S! N+ z1 S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ p# ^/ ?( n G/ e3 \3 U* {1 p5 w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) Z2 S6 z/ b: A; C% }** Configure the McASP pins & ]* v0 `; X' ]
** Input - Frame Sync, Clock and Serializer Rx
2 L1 n9 A" m. y** Output - Serializer Tx is connected to the input of the codec + W$ Z0 c8 K6 O+ j: k- K+ n) k' k
*// w; | C) E7 ?0 V) c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ X6 ^1 z& V8 I7 q3 e0 R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 n. c. D4 O, f3 Y; n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 E2 f e' B, b1 \+ `" z0 E| MCASP_PIN_ACLKX
" |' x9 Q6 l2 u| MCASP_PIN_AHCLKX
. U3 [% }0 `2 G$ Q$ n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 i9 o1 J" w4 N" k d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - S1 K, a! H# t& H* @& V
| MCASP_TX_CLKFAIL # k, ]% n# t: j0 `* a) ]5 Q
| MCASP_TX_SYNCERROR
& A. V2 G- i/ f& W, k3 r$ T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - M4 q4 ]: e! S. K! k* {
| MCASP_RX_CLKFAIL
, _/ s: o+ F* j8 r2 R9 c| MCASP_RX_SYNCERROR 7 H% d! H% m& X4 }
| MCASP_RX_OVERRUN);
& Z1 u9 w8 E) [% G J9 X( N} static void I2SDataTxRxActivate(void)( E$ w2 S1 P9 B) U; w2 u6 x9 n0 }
{
# `% Q# v2 ?: `5 I, p& `/* Start the clocks */8 U( ]/ f3 U8 K; u: {) p& P7 L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 S& W! z5 }: |9 R5 }2 p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 I4 h1 B" I6 I' V% h6 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ g& _# ^5 Y% y* D2 e/ q! j
EDMA3_TRIG_MODE_EVENT);
- L) L& ?, I, \! ^' {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( S3 v3 F4 M8 J6 W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 ]; [% {0 |; G4 c- Z& }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ c, {& a k, Y8 ?) v% i6 R0 WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 s* b$ t* i6 d6 J0 D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' q2 `* j& O: G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* R5 V: J, @% ^9 j) cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ o2 {$ t( T, _; R
} 9 F4 K8 b' ^; r3 u( D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 y8 v$ I/ B$ r l4 R7 e: i6 V
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