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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ ~2 h% s% K( S5 H( G
input mcasp_ahclkx,+ D3 j9 E" s2 e6 v% Z, G( S
input mcasp_aclkx,! q) r! Q" Y& S; d; q7 a$ Y
input axr0,' o9 n( c( V: v5 `4 {% `9 Q7 l: w' Z
1 L" r% n" `0 d. a
output mcasp_afsr,+ G/ W8 N# O' v+ G) L3 Z0 H
output mcasp_ahclkr,
$ ~0 z% `: T3 h8 q8 E8 S6 Goutput mcasp_aclkr,
# U* X" D) d- E7 |) `" J2 R9 Goutput axr1,
% b0 P/ c3 _ ~ assign mcasp_afsr = mcasp_afsx;2 r* V+ `" H# J7 O) w: H9 R2 f
assign mcasp_aclkr = mcasp_aclkx;. L$ g: V, d* `- U! b4 A0 ~
assign mcasp_ahclkr = mcasp_ahclkx;$ ^+ L# ]- I% ]9 A' I
assign axr1 = axr0; - H) R6 p5 W8 U1 ~' |$ }# `
( x: ?) Q" ^2 H# ~. R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ w% h, s5 q% A1 E, L$ _static void McASPI2SConfigure(void)( V' x& Z; N- j4 P
{
- y4 F4 Q+ Q( z t) [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 n3 M4 e! r4 W4 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 ]% m* h6 L* T- C2 y1 `- I, kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 e: H8 q$ N) g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" H. _8 j q9 f! {; I& o0 y+ L4 ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! b7 r* C0 ^9 m3 dMCASP_RX_MODE_DMA);% q' A& j4 S x: K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: X9 v4 a. l- VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
r9 n6 j: w" OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' }( m7 o" ^9 _" [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: |; q$ s" u8 v8 I5 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) O' L8 b& [5 oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! m2 I/ p: |6 g5 uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 ]# L! T& i7 k- I6 z% Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & ]! o. O. O8 B; S& t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 K6 Q0 b9 J1 k% j
0x00, 0xFF); /* configure the clock for transmitter */2 X$ E" a: I( C/ h8 H+ \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ \- w4 y% k O5 [( aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% e, x6 l* n9 SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
h B1 D$ }4 {6 m( k0x00, 0xFF);
& m( ?) l% ?+ \# s4 ]
5 E& Q1 H- X5 ?6 X" ^/* Enable synchronization of RX and TX sections */ + ?5 G. ^$ a+ K7 A% _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* `1 K, K( i5 P. t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); h! Y6 h1 I& ]1 C D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% ~' }4 Y$ K6 n* e2 x
** Set the serializers, Currently only one serializer is set as* k& N! w) e; B# H K" o! Z
** transmitter and one serializer as receiver.
3 x# M4 [7 H1 U j& m*/) G. |: S7 r0 M% z# }8 z% E2 q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ @2 n' U6 C1 S, p2 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* k* ]# k7 X; M* k7 M5 }+ `+ U
** Configure the McASP pins 9 l0 Z! F- |5 F1 ^: p% f! J# k+ N/ O
** Input - Frame Sync, Clock and Serializer Rx
6 V- ^ D. \5 S: u; ?** Output - Serializer Tx is connected to the input of the codec . g( I% M& l) A7 E
*/
# \2 _3 L3 N( X9 b1 kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 p' K2 ~; c h) n g3 L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* O6 \' b s* F# `! ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* L6 N# @' L" W/ n& J! B% s) t, f| MCASP_PIN_ACLKX) @1 D- ~ V8 p6 Z- X: Z, F( y4 v
| MCASP_PIN_AHCLKX
- c; H3 H/ V* F% z- u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
A5 ~! j6 C) l1 L% A' X' |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 p# @ F7 }& Z# O| MCASP_TX_CLKFAIL ' c" A |+ ^$ L
| MCASP_TX_SYNCERROR3 t/ b) ~6 A9 L I' N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 I0 }/ p/ d) F- v& ^0 `$ W4 `) W
| MCASP_RX_CLKFAIL
, ], G' R: g: `, T6 ]4 I| MCASP_RX_SYNCERROR , f; T; |0 k0 a1 n9 @
| MCASP_RX_OVERRUN);4 h# O4 J! |2 i7 {1 r4 h
} static void I2SDataTxRxActivate(void)
4 y3 u! A* y2 C+ o# Z* v! I& R{
C; M3 z4 m0 |7 W& e: t/* Start the clocks */
; k; I; M! v1 B2 \" z1 N7 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) _3 j2 @" r: F" z0 ^" iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; u. l: F' k4 u+ ^; L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, ]0 O4 q+ R9 c, C! ^
EDMA3_TRIG_MODE_EVENT);+ Y! P' L3 C! e2 W0 S& b8 h" S) J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 k9 o% r# u6 ^$ c$ bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 D& T( p$ A9 L& K9 ~* n/ oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& ~1 S0 R% U# l0 @$ s" l& V9 E- XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ b' f# t. _5 n. }: D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- P0 y7 m$ J- e Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- w/ S' `! i4 M% M/ VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% n s- z3 f0 G7 `) b c# x0 y# E}
( S0 B+ G7 y. ^0 p9 Y& [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ u; i! i4 M, e
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