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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ P8 E& c8 } v% F a# n
input mcasp_ahclkx,
- d* {# t l; g5 v) _+ ]1 dinput mcasp_aclkx,/ U, c# f8 z2 f( O* T9 q% D: G
input axr0,
9 |% b9 f1 a$ V7 K# q' ?+ b) [) Y+ J# F" s F8 Y
output mcasp_afsr,
0 C* e4 C6 y6 f |9 e$ g$ Aoutput mcasp_ahclkr, J0 k3 v3 O: R2 r* @/ w
output mcasp_aclkr,
5 K; @) b. k9 F9 B! eoutput axr1,; n( ^1 k: M8 n
assign mcasp_afsr = mcasp_afsx;
R/ ^ x& e* [9 ?8 ]$ i: passign mcasp_aclkr = mcasp_aclkx;- e) f1 x) W# \$ {
assign mcasp_ahclkr = mcasp_ahclkx;
9 q9 G" b i3 {0 e6 r# q7 A4 x" Eassign axr1 = axr0;
7 @5 b+ X2 r9 \: F+ ^& Z( R+ M
9 x. m: v9 ~' h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; I. n/ ]6 Q4 T; [( X
static void McASPI2SConfigure(void)
' K [' x( C1 ?{- ?4 d P0 ]) ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 r g* Y. w6 _$ i F; `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! a9 u+ {/ ~+ e% I0 Z: u9 |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 g' L7 w- ?. C7 oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& f4 K6 ?9 v# U0 J0 I( Q( Z1 TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' B" V0 [: c- L0 s
MCASP_RX_MODE_DMA);
) U; B+ J) b m% y( p9 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& j0 x Q! x. Y F+ ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% P( G0 ~* p# s& K5 k+ iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: f. ^- U8 `9 F1 t& VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: J+ ~( S C0 ?" O7 n+ lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - e! {4 z# p7 U- A+ H6 x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" F5 s( ^3 n% @ ^8 `$ A2 bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- V2 r) |7 J$ g& z+ p1 e3 a, gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; U/ H! ~( ~8 m3 b' W$ y0 H5 gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 p# C# [' h3 z
0x00, 0xFF); /* configure the clock for transmitter */# M5 j4 ^3 I0 O$ |3 `7 W& K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- B+ t P8 d( KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , K$ Z: u! Z. H8 e h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# R$ L% q, _0 E2 l: G
0x00, 0xFF);# M( h# v+ L V. l% b
7 g* k3 S( Z& \5 v6 G! b% @/* Enable synchronization of RX and TX sections */
! Y) |% d+ m* @6 v; W! n2 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- w+ _, K# u, ~. R t) r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 T K* n6 g7 M% u2 ?" m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" X1 n9 p7 q! z- l+ p** Set the serializers, Currently only one serializer is set as0 Q; k7 Y$ `# b' }
** transmitter and one serializer as receiver./ X& @% m6 W, l0 W' C$ H
*/
3 m, J0 A3 q$ {9 }) D+ F0 P: m" LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 Q) B& M6 o! Q# YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
w; X3 ^. t: t6 R** Configure the McASP pins 6 z" [5 E8 a7 j) B* f1 `
** Input - Frame Sync, Clock and Serializer Rx6 n* s1 z6 L0 M, ~7 A2 a8 v
** Output - Serializer Tx is connected to the input of the codec
/ V6 L& K6 {% w( N V*/5 E' n4 O, p a$ N: W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; C& H# d0 c% J4 u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, g" O2 o, X6 J z( J, a: \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% ] a8 ^+ O0 y$ d9 E| MCASP_PIN_ACLKX5 G- D. w% I8 ?- D, f
| MCASP_PIN_AHCLKX6 X9 {, g) ^/ w& l9 a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// ?1 |0 D. {5 Q# Y1 R8 o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% l; @$ Z) b' l/ I+ U3 U| MCASP_TX_CLKFAIL 1 Q$ w9 [! M( G' V
| MCASP_TX_SYNCERROR
6 k$ f0 I* @6 p6 Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ x9 X( r0 i2 b0 f; c# T| MCASP_RX_CLKFAIL
- t) x$ ^; x( d4 f| MCASP_RX_SYNCERROR
: R5 a3 R; X: b* S2 V$ B- x| MCASP_RX_OVERRUN);
3 z9 F; g6 ]( ?& b0 C} static void I2SDataTxRxActivate(void)
. C' I6 f8 C/ ^. [; p9 S{3 q) j2 b- o2 A p7 D- U% X& e
/* Start the clocks */
- ^, j0 @& f9 X& [/ e8 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: M: {9 h1 `6 B* H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( D6 |6 V+ ^! c: q7 p7 u! K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% }" D: ^6 s9 @2 ~3 ]EDMA3_TRIG_MODE_EVENT);
3 M' S8 ?. z; XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 s: V9 f. U+ N2 K6 a6 D0 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ S# e# C" f2 ^* MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 d' L T& U: c+ a& @: G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 T. x7 U/ Q; Z( a& A5 t3 twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 K- C7 }: I- @. y( ~! H9 ~9 \McASPRxEnable(SOC_MCASP_0_CTRL_REGS); w+ y% T! o0 P P8 e3 e# j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& x# Q3 T% O# l( b8 e
}
2 t( A1 @* |, U- T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' {" x& w" {/ |8 k a% a
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