|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. D; X# d7 w- p! L
input mcasp_ahclkx,' K. i' X! L: [* z! j+ e4 a
input mcasp_aclkx,
0 A/ v* Y( ?2 J1 Dinput axr0,* O" W2 P8 C! c: g( f
- I! H9 T8 J I) [
output mcasp_afsr,
- [) a+ C f* M/ f- @4 Moutput mcasp_ahclkr,
8 O* |$ T, k+ |1 U1 g- Y8 @* poutput mcasp_aclkr,1 {; ?8 h9 C, V) T- `* t3 l( Q
output axr1,. v, A' A3 N0 }# f U) {9 ^
assign mcasp_afsr = mcasp_afsx;
5 `, O& t8 B" iassign mcasp_aclkr = mcasp_aclkx;& ]. H ]8 J5 Q6 X
assign mcasp_ahclkr = mcasp_ahclkx;( ?9 i, j. }6 N' ^- W) c
assign axr1 = axr0;
! C4 `+ T1 v- d8 |2 h
; _2 a5 }; g2 M- q# m' m9 m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* s& Z; y% `( }static void McASPI2SConfigure(void)
6 t- \+ y, q' }8 g" m$ R% Z{( i, f3 X# v, W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
q( \* g+ k3 J% y! \) B7 Y p( w! DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( X8 T$ J* a M- d! z1 T% i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! u: k5 j/ B4 D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 @, H% |+ v# Z1 G0 Z' j9 J! tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! h+ q6 b# E9 q% }4 q3 N( L7 W) nMCASP_RX_MODE_DMA);
$ s9 L2 t9 `! S; Q+ g# ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 d. ]# P. Z1 D% b8 k D9 ?0 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 t# r6 W6 s- o% k8 |" W* k9 FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 y6 @. ]; r. Y; f& }' Q1 |! n8 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' ?- B% a$ e) h6 Q7 s# KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ v7 K" v$ M, r& H$ @- l, h& H" [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& f0 w0 ?9 c4 c5 VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 g- B# ~- G7 H. }* a9 V+ |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ s( B5 b" X) h7 M' D! ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 h: ^0 L0 C% O4 U
0x00, 0xFF); /* configure the clock for transmitter */
0 C3 J, x( e( f; Q$ @* _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# }4 o) b2 e b& ?& f4 yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, l6 Y. S4 E% n) p! EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 y9 E3 [$ v) I0 d5 X* |- w1 _- I0x00, 0xFF);
' h* j5 A4 z9 x& j- E
) T0 S) t8 Q8 e2 t3 D4 F/* Enable synchronization of RX and TX sections */ ' v2 U* b: }* {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% h& F2 c& q" T) rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 t S9 _- O& ~+ G9 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 H' h9 O& ?( Z- K8 w** Set the serializers, Currently only one serializer is set as
- @5 N$ m. E; @! }; L** transmitter and one serializer as receiver., o R; Z9 m @7 l D0 O
*/" e- x y, F/ g3 x' W3 q6 s+ F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ z1 ?* k; [3 \5 b- I0 t% j5 hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ M$ @" R) t1 ]' R6 A5 I** Configure the McASP pins
/ S# ?% C3 ~" q! G( ], _# E** Input - Frame Sync, Clock and Serializer Rx
7 W& F$ w E& f( O/ z# _** Output - Serializer Tx is connected to the input of the codec
; m. E" @7 [3 j& z4 N: p0 I*/! \5 z/ Z9 |; k2 }6 C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ d( I4 ~) v4 ~3 G0 A! ~6 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 R* I% V8 V8 Y$ p' [9 D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- `+ `, E8 [. v! s| MCASP_PIN_ACLKX3 u7 K/ Y9 |* y% p
| MCASP_PIN_AHCLKX' j/ Y& ~% T1 y8 N- c8 P. x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( N9 ~. r, d) \+ l: H) G, zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! x+ C- M& d! H! o
| MCASP_TX_CLKFAIL $ A7 [/ j+ f) C' B5 {8 _$ ]; u- S
| MCASP_TX_SYNCERROR9 _# w) G2 X; }& @1 i4 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) Y5 j4 n% P2 m/ L @& w- V% X# || MCASP_RX_CLKFAIL! [' ?! s* s; z' B" \; @6 D
| MCASP_RX_SYNCERROR 1 ~% ?# S- D2 T! S% `
| MCASP_RX_OVERRUN);3 a& X/ X6 \# \; X' t
} static void I2SDataTxRxActivate(void)
# d3 V, A2 D0 I& P: d$ j' _2 b{
, y2 ^( n1 C) L6 @/ k9 @ K* U& q/* Start the clocks */
2 D2 L+ Q r* E9 u0 @% E3 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" c3 w' _4 N' W/ ^9 J5 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ L5 \7 U. M: |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ B+ A4 W \: i8 f3 i+ u4 m
EDMA3_TRIG_MODE_EVENT);# F1 u' l! H6 @# g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 t( l& E8 f9 _/ n( m& o- \4 l ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: U* r8 Y6 |: F# r5 kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* ` b4 b1 h& b! l; G6 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 P0 h5 _- T- j; Z9 N! Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 O0 p# `6 Z3 r- M! T# EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 D7 |' _. h) I n8 F4 ^9 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ s% V2 K4 N3 y1 s% G6 Z7 H0 n}
& @1 U! {. E: i4 x2 V! g8 f- g/ p3 [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
9 I w/ u6 M$ a+ e |