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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) Q; }% A8 {0 A* R
input mcasp_ahclkx,/ M. s+ p K& B9 n7 y
input mcasp_aclkx, X+ o1 l# [2 {& A
input axr0,, y P) y/ y) ^
0 T. |( N8 ] F+ @$ Joutput mcasp_afsr,5 g3 c Y4 p8 r2 m
output mcasp_ahclkr,4 ~# ]# I7 M9 R) Q8 P
output mcasp_aclkr,
0 D) a) R0 f/ b$ x# n% ^2 Uoutput axr1,5 `: a2 R4 X" t# |
assign mcasp_afsr = mcasp_afsx;
5 ?! z2 `/ d; a1 iassign mcasp_aclkr = mcasp_aclkx;& E6 B( r, _8 A4 d) N( ^ A: x0 U
assign mcasp_ahclkr = mcasp_ahclkx;
9 r' ^2 j* Y# ]' F% I: N8 Cassign axr1 = axr0;
8 E5 A3 d9 y8 ~5 r6 W$ w3 X% h2 L* A1 C! E+ g6 M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ c% G6 Y1 z A9 I) Z8 z
static void McASPI2SConfigure(void), _$ r: N2 Y7 O$ d) f }, J4 g8 z
{
% \& \3 }" g: D hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( N& D. S" f- [; Z* c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& B: Y, n$ A7 j7 v( f8 R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 W2 }, v9 x/ d1 OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 S7 \5 s1 u: wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; ?0 K- h# |+ |2 n7 s0 zMCASP_RX_MODE_DMA);) r) @/ T7 v; t( R0 }1 n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' p2 }" L/ \& j5 R3 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; \1 a" h4 l4 b* kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 ^) D; e9 s* lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ ~4 A$ l4 U; t/ }+ @0 [# k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 d( N' w# z$ ?5 F% ^8 j& {8 C; V t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 \" }4 d8 i/ G9 K9 d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 v% g$ M! I" g- I! Z6 l! Y& s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' q6 w5 @9 {. c# qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" d2 j" w& K2 q; @/ M% R, i0x00, 0xFF); /* configure the clock for transmitter */1 [: x3 ]+ k: y: ^/ y. t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 k$ S9 e! h% t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; F$ B8 @4 e) X5 x' a# Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; `* d4 \+ k3 O0 `: S3 s1 `2 o' d0x00, 0xFF);
$ z9 B/ R+ t1 c" u1 q6 O0 X
% w" V& q- [' q9 |2 M, }/* Enable synchronization of RX and TX sections */ * G) }/ k- s2 ?- a' L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* a) ?: _& ^" e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ v3 J ~7 Z( K7 _- Z% mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 }" k8 [+ U5 G7 \) g4 i
** Set the serializers, Currently only one serializer is set as0 v- p- d# n$ g/ x) C+ `9 J# b/ `
** transmitter and one serializer as receiver.
Q5 ~4 N0 x4 K*/( F9 u" Z4 j+ o' f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# K2 Z/ @1 s& w- y% q$ j+ _1 FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ ?1 p3 _% o+ G9 e2 G; _+ e% O** Configure the McASP pins
! g2 m2 ~3 U, h4 U8 _** Input - Frame Sync, Clock and Serializer Rx) D6 x: E: A4 ?. b$ a
** Output - Serializer Tx is connected to the input of the codec
; F9 e# E/ \+ B; ~1 ~* s*/$ D7 M, H4 _' u) c- {8 [& X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% U. y- O5 e6 \: L' ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; j7 z% b, C7 n6 O0 D* H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 n$ G b0 U- l$ j2 _/ m- H| MCASP_PIN_ACLKX
+ r& X4 H. @0 r- J/ w" G| MCASP_PIN_AHCLKX' B; o* a3 P2 ^' f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. B5 q( `# X9 y8 n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 ]- _! p# D3 u8 A- x) @| MCASP_TX_CLKFAIL
9 h2 ]8 T: \( ?; J: G2 G| MCASP_TX_SYNCERROR
7 j: j0 o4 D/ }$ }- ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" `3 H/ T# {" @5 L1 C* a| MCASP_RX_CLKFAIL
o& \- Q& w" o1 m4 x+ ?| MCASP_RX_SYNCERROR " y* L7 j4 j [( N! j* a
| MCASP_RX_OVERRUN);
* N) Z; F- ^- C/ ?} static void I2SDataTxRxActivate(void)
2 P* Q. X# U, K" H5 J4 Y, q{) U8 X" n/ L: z& Z8 w* D7 I
/* Start the clocks */
E7 {( Z: {! F4 Z" k! eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* u2 T( `4 G" i, x3 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 n+ D1 w4 M: x3 X! zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 R+ c2 f) U) M% w7 V6 VEDMA3_TRIG_MODE_EVENT);
' L- S2 ?/ b2 C( b7 `; ?* i: M6 @: A2 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % N x; D: g3 d f/ x. H Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& r; K" Z8 l0 Z9 T" b; TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ A+ s0 P7 Q6 b6 x2 p! }5 \6 d0 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# ^6 i, g0 x/ B7 V( R% ?: I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( t5 a+ `( _9 A" C) ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: j/ X( F- L. g, J6 X/ R- AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# J# ?6 ?4 M1 Z2 a: r0 X+ T
}
& f9 y- ~* }9 ~! P1 m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 Z# s( A$ R7 V0 j6 r. F" h
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