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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, r5 _* X# ~. O' W; _! Vinput mcasp_ahclkx," \9 ]/ F, L# L. L$ K0 b( b
input mcasp_aclkx,
& P4 }6 o7 w8 Binput axr0,, h& w. y( K- e/ o# X
3 H1 ^8 I0 @2 w* _7 xoutput mcasp_afsr,
7 X8 x$ ^5 |; ]7 i' ]/ Houtput mcasp_ahclkr,5 L) ~& g& N% X4 P7 X1 s5 ?* y7 u
output mcasp_aclkr,
& m7 G3 U) W7 `! P( {output axr1,
9 n7 z, v- Y* Y assign mcasp_afsr = mcasp_afsx;
; E7 |5 D* W& V* _assign mcasp_aclkr = mcasp_aclkx;) Z6 l( p+ X/ O* S# [
assign mcasp_ahclkr = mcasp_ahclkx;) {" E8 Y7 m! M/ ]% {# X
assign axr1 = axr0; , n# p, {. _; b, m3 [' z
0 U% L) a1 H. c$ h6 u* c1 V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# {3 L; Q( \3 }+ v* Mstatic void McASPI2SConfigure(void)0 G$ G; V" m, C; ^
{! ?1 |- X1 o, ], X; F. M' S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 W2 x; z3 e+ W. |! ?, [9 s3 k/ V5 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 q9 f; Z7 L* H1 Y! \. }" Q# S5 H) |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 d5 f! R9 E# S1 r" A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" }% }1 [4 m' \$ GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# A; O! R( q- w: i# O' O9 V- T$ XMCASP_RX_MODE_DMA);* Y$ j! S$ G$ F& {9 w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 b5 o6 q0 B6 Q) WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& f, g) ]5 Q M+ E7 ~ y- \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 T( h9 `: i- v; ^6 x- }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 a% N. `/ u' y1 E# q# P/ L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ d, F8 n, H) O# [ q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 d" W5 t" t' d' p) n- K! a: SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# I) e$ }0 _! j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 J+ d+ b! \/ M9 K8 C+ c, k. c/ { |/ g2 m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ k3 S0 F, S; T$ ?1 U4 R9 O! x! ^
0x00, 0xFF); /* configure the clock for transmitter */- Z/ k, G$ t( Q" v- E' h3 f$ M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. s+ J2 i$ Z1 B0 ?+ K) g0 S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : \" I; v* n; l2 C n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- l6 ^: N8 r! w+ O0x00, 0xFF);
! i. _- x! ]9 V' W
3 A6 U9 s, [; n/* Enable synchronization of RX and TX sections */
5 i3 h' S5 g1 Z/ k' r" oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 Z4 v% w3 }: K- nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" n/ d: s* ^7 x8 U4 RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% r0 u- Q) j1 e) T6 R* l5 |** Set the serializers, Currently only one serializer is set as
, R) ~# U. h0 m7 G+ H* V** transmitter and one serializer as receiver.
A$ i8 Q$ G! V*/: ^: l! \' |- G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 W9 N) c c: W( f+ {% L+ rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 d$ S# Y4 @* y/ t& A! e
** Configure the McASP pins
. B T8 r% a T% l** Input - Frame Sync, Clock and Serializer Rx0 }2 v7 t T V/ s% ?
** Output - Serializer Tx is connected to the input of the codec
2 y- L' Z$ S5 V*/
" Z8 F3 r- z! u. D2 j" VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ T7 x3 V7 A* P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 i; ~+ {& F4 N) _& z$ lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 q" D b3 d# ] b% `
| MCASP_PIN_ACLKX
% s& Q! w% p+ W4 _| MCASP_PIN_AHCLKX$ ^3 B% v7 U: X! u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# _/ Z7 [( n! {3 Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 T( n) H; ~) U& I
| MCASP_TX_CLKFAIL
. ~3 X5 x$ Q) U' C6 @| MCASP_TX_SYNCERROR
0 ]0 r' O/ ]! i/ |3 V/ H3 K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - F& G# s4 M& c4 x. ~5 U
| MCASP_RX_CLKFAIL
" ]- D; J/ p5 K2 J" Q9 ]1 C2 x| MCASP_RX_SYNCERROR + l$ L3 M& ^6 f2 K8 R* l1 E
| MCASP_RX_OVERRUN);
' |+ F, @: n" r, _} static void I2SDataTxRxActivate(void): x M) l( Z) o0 {
{
4 v/ i3 j# Y0 @* p" W9 ~/* Start the clocks */
3 o7 S8 q4 o$ PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- J# |* x1 o, f9 ]9 a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 d9 B' T4 V! j6 C9 L8 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. ~2 T2 |& d4 D4 d" Q+ I s
EDMA3_TRIG_MODE_EVENT);
; U; b; S4 T/ DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# V: Q0 g m6 ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 H5 R. Z/ i4 {/ I* N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ S2 K+ e+ b& R8 HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 {6 \) y4 q5 J/ B: \& ?) i4 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 e% d- R) c6 B) E4 m9 C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 u# P# i; H' y9 o# Q8 X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( F" v' b* X2 q
}
2 [1 M5 E; m3 S \' ` c- u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * E1 {" a( T" {, X) x3 @/ a8 {
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