|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! }- n4 E+ v, d
input mcasp_ahclkx,
) Y# S$ o' ?8 ]" ?, j( Zinput mcasp_aclkx,$ t, z+ I( ]" c" W/ M. E
input axr0,
" w' X/ \* O/ Y* a
. L, D8 B' A. x. r6 D6 zoutput mcasp_afsr,4 |1 ?7 v: h5 V- G8 P
output mcasp_ahclkr,
1 b/ W1 @! B# G3 Foutput mcasp_aclkr,4 i1 [* O4 q$ B/ K
output axr1,$ p% l) W$ }6 _) C
assign mcasp_afsr = mcasp_afsx;* }/ Y+ e# Y7 Y# }+ Q
assign mcasp_aclkr = mcasp_aclkx;
0 C/ U$ R( d% j: S4 {5 b5 |assign mcasp_ahclkr = mcasp_ahclkx;* G( o) x' _( b K
assign axr1 = axr0; 7 \8 z7 G( H0 \
% F! ]+ I* a( a l8 w( @ Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 U% z) K# O$ Y3 E! F/ C* }
static void McASPI2SConfigure(void)' @/ H% C. E+ N$ l4 S$ F4 e
{$ B8 N# T5 m! ]% i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# R/ p% T& ?/ \, MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ Q6 Y# z0 ]+ g% J* n q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! E3 e( A, l" h; f6 WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 P+ }. }3 d* F0 L$ |5 j, z% s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ h5 ~# j( a/ ]* T6 T( a: M. e% \4 }
MCASP_RX_MODE_DMA);- u# x0 ^) U( V4 m; ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 X1 J6 k7 x5 W! V7 hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// x/ _9 H% r+ H! r& R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 J4 y( w2 m" N% ?, b- B( P" t% R& fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ l/ i1 H0 A" P1 w* ?/ `: [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# q+ X: j" N! }% kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 ^" T# N$ E9 J6 Y1 h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ q! R0 p% X; s" _$ W+ [% f$ wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 z7 G/ S+ i$ {4 s7 {5 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, b6 K ^9 w% ]! v4 t( P& `1 a, [
0x00, 0xFF); /* configure the clock for transmitter */
! C& Z3 O, [# p6 G1 z7 ~5 lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ R7 x& h, K! B0 f3 g* J8 `; \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ F* V$ q' H9 R/ Q; v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! X' x+ }6 I6 ^$ g3 r% U
0x00, 0xFF);! L2 G" ~; R8 J! L7 b. I4 i
& s4 T2 i! T1 X/* Enable synchronization of RX and TX sections */ / O) C6 J4 [" Y9 T& c& X; a- R6 U$ e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! I( y0 {+ m; Q! s }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 Z6 C8 f+ \' b* F3 PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! e4 g8 P5 V% A: k# ~
** Set the serializers, Currently only one serializer is set as! a Z3 W: B2 g" T
** transmitter and one serializer as receiver./ V8 `! M* k7 U! I6 Y- ~
*/
! s+ [! o+ h4 W9 @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ N! N: _* `! r( a+ S6 N" m6 z/ fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( B" e5 t- o5 e: Y** Configure the McASP pins 3 h! ?3 p. E% M6 Q3 V* N& T
** Input - Frame Sync, Clock and Serializer Rx6 N3 i8 f, L3 C/ D6 W9 C9 k& U
** Output - Serializer Tx is connected to the input of the codec 9 i0 S, S% a: J: O& U7 @+ x# X2 k
*/
: K$ V- Q0 o- L5 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; I( Y/ B0 G- {5 c0 d) s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( J1 f$ @5 z, D. P/ O! z# YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 p K! A! ?( Z) u+ h
| MCASP_PIN_ACLKX
1 ^$ l; W1 o; o# b/ A| MCASP_PIN_AHCLKX
: f, O1 p( o- L) {6 x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ b: {% s0 B6 l8 sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 s: O+ }# A" u: c5 j/ k- K& q| MCASP_TX_CLKFAIL
* ?) }/ M! S- U5 Q7 X9 _- N/ a& P| MCASP_TX_SYNCERROR' R: Q; S, H; Y, L* c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 A9 K$ E' |! J# W2 x6 R! R t| MCASP_RX_CLKFAIL2 {. G* O# _& A4 `* T' s
| MCASP_RX_SYNCERROR e5 y+ m# {& S& P4 H
| MCASP_RX_OVERRUN);% Q5 {' J) _6 u+ W6 ]; _+ c* G
} static void I2SDataTxRxActivate(void)3 S O" M% @% t& G8 F w- z. u
{
2 t) h G" w) s, ?8 f4 ~, e+ |4 b/* Start the clocks */
M" y s* `2 x' T- D! XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 A" @0 T! F/ H8 r( s9 u9 v* `. I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! \& M2 o7 Q4 {7 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 S6 w) \/ H A! r& z
EDMA3_TRIG_MODE_EVENT);
0 j2 o3 l# `1 T8 ?" n, E) s- L# oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- V0 S( R7 ^# nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- V) X' {+ S- F/ K9 c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 ?9 }+ g( |# \& h. |2 _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. }5 R2 Q. S4 D' i5 e. cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: F; W- X7 m: ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: U7 j: s3 I. u- s$ j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" t T5 Z$ a0 l w
}
, R" G1 G3 ]: T- P+ D$ i0 Z7 X# a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 X, n5 j7 }; W/ N+ K
|