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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 H& A- a) g. }" D
input mcasp_ahclkx,
* \" Q: G4 L7 [; U4 e' Sinput mcasp_aclkx,& E; M6 F& @0 R4 o. c M
input axr0,% N4 Y. ^& c) F* x. t: j( W( a3 Q
: m( }& A* E5 v* H4 O
output mcasp_afsr,
& A5 X6 F. I0 _5 V, I6 ^- {+ boutput mcasp_ahclkr,
! |& W6 ]4 }/ q: S% g( `0 J4 V# S! uoutput mcasp_aclkr,
( _; z( n3 O# \- _# z# foutput axr1,) ^9 Y2 C: i6 D9 y
assign mcasp_afsr = mcasp_afsx;3 o( n2 K8 P/ h
assign mcasp_aclkr = mcasp_aclkx;2 ]- C; \, @+ a9 ?
assign mcasp_ahclkr = mcasp_ahclkx;
+ n, `; Y! @" a# `0 ]assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 t( `2 S' `6 u( }
static void McASPI2SConfigure(void)6 C! [$ U: }8 x$ W( e
{; k' [: o! v+ |3 q5 t! f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ w5 @6 b9 @3 |" U/ X7 j. oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 Y, i7 W1 a$ t( t! s% u' {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ ]: V7 h8 F) V C- m7 Q* _/ ]5 a$ rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ Y! S3 [5 B. e" r8 zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 F" |1 S/ O7 T5 w% sMCASP_RX_MODE_DMA);) F: w5 _8 `" [' i! G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- K% ?9 Y% F! a# XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, o( B* M+ H) K7 R! P/ }! F" W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / V. T+ f$ Y5 ?# ^1 p$ K# l- o+ ]$ g% C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( T: Z8 {) I8 x5 s; M& b3 M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 k4 a- K* \- B h4 A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" J! [: D: `$ d0 V: Q* nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& s% q. {7 ^8 q I( lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) L6 g9 Q4 e/ p; Q" v# CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 ^9 D; [, J2 B8 e+ j) q
0x00, 0xFF); /* configure the clock for transmitter */' r: R0 ^# N- E$ Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- Y" ] Y! b' d9 g0 U5 j* |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 a; F# u5 {5 O6 a/ S1 a4 {* D$ XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- R( K& [" D9 j6 j0x00, 0xFF);
( _4 M, R0 [8 b! Q6 @( m4 d4 H0 q/ r3 C K) x0 m N
/* Enable synchronization of RX and TX sections */
& `! y3 h/ j3 z; U6 |1 bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 o; Z% P: M+ y+ |; \7 y2 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) L* i# L. q6 L& yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- y. M9 p% n+ a8 q8 z+ I
** Set the serializers, Currently only one serializer is set as3 F# ~# \8 J D$ t' B* U5 h
** transmitter and one serializer as receiver.
2 E f- e/ d3 Q. x" U9 }3 g7 F8 L*/' I( N, f, L1 `1 G2 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 L5 l4 Z: h! y9 f/ o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. k+ n: G) L8 y6 {- F1 k. x3 G& G# z5 U. }** Configure the McASP pins % H/ |/ r! q0 U$ H; L: T
** Input - Frame Sync, Clock and Serializer Rx8 X' W0 g8 L( i7 I2 S
** Output - Serializer Tx is connected to the input of the codec
! w' m( F7 C+ D0 C6 ?: Z% Y*/
9 F+ I0 ^; L5 ^: S4 m4 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 w- I& Y2 T$ z$ ?: @ v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ P$ A, J* t9 H: O6 M& U) W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) E8 C7 J- t/ ~6 w$ p4 K| MCASP_PIN_ACLKX
# Z! p! Q/ s1 |1 H8 i4 w| MCASP_PIN_AHCLKX
0 L6 p2 x) a2 Z G' a7 i' p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 B# x. U+ y2 _# g1 j# FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , E; X; x* p- L5 q+ P
| MCASP_TX_CLKFAIL + T9 Z4 }% \* e8 \ Y
| MCASP_TX_SYNCERROR
# y: W0 s, ?/ J- M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " F+ M4 b5 ~4 k- _
| MCASP_RX_CLKFAIL% w' }* {1 l! Y$ W, X6 C
| MCASP_RX_SYNCERROR $ F8 n0 |) i3 X
| MCASP_RX_OVERRUN);( v& E( g% H& t9 v
} static void I2SDataTxRxActivate(void)
/ { h# N% f; b9 A2 V; M{
0 J9 }0 \# O1 v/* Start the clocks */- ]9 K% t& `- z9 {$ c. q" e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 G; N0 Y X6 }, D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 M% o# g; H3 I r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) I2 C* Y8 g7 M( G. b8 `* v
EDMA3_TRIG_MODE_EVENT);* c) S! t- [ G# v$ M/ y; o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ o! \( F9 {* z, ?! s# tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 W* V' L: R9 j, u. S: [3 {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 c9 a, x7 K# r; {8 {5 C z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; F0 V/ ~- g# C" l O& M1 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# Z5 B5 |" H( sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); m, H0 @' y! q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! u$ \/ f7 S, P9 M5 V. a
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