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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ `/ p3 F F, @6 J6 v6 Winput mcasp_ahclkx,8 ?, C5 ]( Z! S. X- s7 A# x4 l
input mcasp_aclkx,
M6 k. `* u" s" _) vinput axr0,
; X# Q4 y& B* n" I q* ~5 |, Q1 h9 c1 J% T, b/ U) {
output mcasp_afsr,' d0 c0 b* ?- U! X4 k+ l$ L
output mcasp_ahclkr,
~9 \- z% ?/ ?7 J: r* P- woutput mcasp_aclkr,1 y9 L9 e5 h9 G; k, S2 M+ `
output axr1,
! ~8 n. D& T! K& A; f' |" | assign mcasp_afsr = mcasp_afsx;% i, ~ P6 p u' I" d7 `
assign mcasp_aclkr = mcasp_aclkx;
# e) r+ c3 f) W" ?' Tassign mcasp_ahclkr = mcasp_ahclkx;9 Y3 ` c6 {( |
assign axr1 = axr0;
1 S1 j! X: h; |" x% M
. [3 G7 _8 ?1 Q1 S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# R; E8 D' W/ F# Ystatic void McASPI2SConfigure(void)7 n- r5 F) z- g0 c. m' i7 L7 O
{
: T$ [* v6 u C+ a7 ]" J7 L0 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& [( w0 [5 E+ F: `# v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* }5 l; _; S7 U1 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ v1 q3 }$ x' j3 u, {7 W) N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- ?( e% s! s: |$ hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 n1 a$ k! x6 g0 v6 C
MCASP_RX_MODE_DMA);5 [: _! H. |3 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! s/ g6 m+ y: @5 v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 G" y- p/ R. P6 C _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 F/ m p5 Q6 w# V+ A" _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 x8 d! _7 e0 }. @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, y: V @( q& T7 |$ Q. R% S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! R9 \6 k5 {7 }# C6 `; T1 B! t% i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 W6 s/ [( {1 S \! W$ P" Z- C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: a. ]( U4 }! c; a$ F3 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( F( W T% D/ T6 _/ B
0x00, 0xFF); /* configure the clock for transmitter */9 j; p, d5 _1 j. ?. P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) t- C* B9 B+ Q9 q/ }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 C: Y2 p/ L. k' {+ [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' z" Z& p! _" @. ]$ Q0x00, 0xFF);' u5 z9 I7 A) `- b6 T0 X9 Y
& D0 [5 L) ]" s% K3 v0 g/* Enable synchronization of RX and TX sections */ 8 }8 s: m0 T% F9 ^. a) J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ r5 O; Y# Y5 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# g+ e# m) E7 C8 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 p; h8 G8 y8 R! g: l( U** Set the serializers, Currently only one serializer is set as/ A5 X3 Q+ n+ S* N& T2 H# X
** transmitter and one serializer as receiver.( d A7 t: @# N) c# L; R$ t
*/
# `0 h) h/ j1 W$ u6 e S9 e7 F+ p: E9 P7 |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* g% |" y- [( F8 \" Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 B( n" x3 @8 \7 v
** Configure the McASP pins ' o$ H$ {2 ~- t
** Input - Frame Sync, Clock and Serializer Rx7 p _8 @9 B0 w
** Output - Serializer Tx is connected to the input of the codec 3 d( p$ @1 {5 g v! W/ m% f- _2 W
*/: ]2 I5 } g) @# V* T2 R: U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 a1 g: G3 D6 N# q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- H; J' ]: z. r5 x) w& a+ N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 V0 ]0 C. S7 U( u8 z5 e: D| MCASP_PIN_ACLKX: N) o2 o& ]7 _% ]3 y( ^7 v
| MCASP_PIN_AHCLKX
9 E3 Y/ s/ m% r5 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ E5 L8 d" b. q; J$ U7 B. O8 ?& eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. J$ ?, Q C6 D| MCASP_TX_CLKFAIL # w0 S9 E2 L+ h; |
| MCASP_TX_SYNCERROR X$ U4 {; ]0 m9 h. w. Q6 Z8 Z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ w7 }% u: q% z4 ?9 z| MCASP_RX_CLKFAIL# u; ^/ q) q; S( Q
| MCASP_RX_SYNCERROR
$ p" s2 {$ K7 O. G1 t1 a7 A0 y5 |. n6 K| MCASP_RX_OVERRUN);
D! A% C# J; d- A} static void I2SDataTxRxActivate(void) D$ P5 h' R+ J
{
. }: I7 K: h. p A. ^. W9 y+ k/* Start the clocks */8 v* b4 D/ |7 Q$ L( l& w) h1 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; \7 X: D5 J+ lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ @- G3 n2 A9 @* bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ ]: {: r k3 i Z1 o1 ?9 l9 h( aEDMA3_TRIG_MODE_EVENT);
2 H' r; r2 h& F: ?3 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" P) m" k5 c/ j+ Y/ N5 ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 w. b. u1 J0 ~: R8 k1 v" J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( J! a$ _) ]5 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# \! A/ |+ S% J( K/ u# H2 O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: E7 r/ V1 y7 C4 O6 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. Y. \) r! Z8 X: j! R) {# @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ p& ]$ B$ A& x0 D% \1 H/ W/ b- N
} / C1 ]" S! n; {2 w+ U2 T0 q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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