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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# S4 T1 ~! ]9 h& p( u7 h. n% k
input mcasp_ahclkx,
# Z7 [3 E! ]4 w" rinput mcasp_aclkx,2 K2 a7 W3 U& q$ W5 G$ z
input axr0,
9 T8 v; ]! F* `# n0 ~- r, p- R2 S4 Q0 J
output mcasp_afsr,) `" S: z4 c; p2 A: [
output mcasp_ahclkr,
6 ?& j8 N2 ?: D2 G5 J5 K% p. [+ Soutput mcasp_aclkr,
7 J+ _6 {" w. i# Toutput axr1,. ^) J* x8 [2 o* i0 i7 g5 y9 E
assign mcasp_afsr = mcasp_afsx;
" Q; G+ Z2 @4 X' ]& Y8 x: Aassign mcasp_aclkr = mcasp_aclkx;( H0 r& o: r+ w& X0 B! _
assign mcasp_ahclkr = mcasp_ahclkx;+ V D8 ?! m) J, n% z
assign axr1 = axr0;
' y1 n) X' `+ M8 I* e- x
( h/ k( g. H3 `* e" b! d, Q2 i2 {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . y" n" f* q! `: x# y% I, z" Q
static void McASPI2SConfigure(void)/ } K* L4 q6 `, t; J4 k" b
{& v; |* R" v- G1 ^# _ o: C) _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! I1 J! J+ G8 b0 D' b; K8 {5 d0 p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* ^. B4 i* `8 r0 W' jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 M: m* `+ A6 ?( @$ s, {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 M9 U' O/ G* N2 UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 R: s& @1 h5 A5 G1 e9 ?# @( _MCASP_RX_MODE_DMA);1 [/ E( @# b- F4 N" d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 {# t5 P4 ~7 p* X Q$ e& NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! Q+ q0 e6 |' P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 j! I, c- j/ Q) S/ x+ k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& c. o/ W4 N- L" oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# h: A, J: o2 T7 v/ T5 n @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. r, {+ d, u: @0 D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 F' G3 q @% d A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* `4 M* M4 p. A% X2 N5 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
\5 G( N5 \6 J% ~0x00, 0xFF); /* configure the clock for transmitter */
3 L! w- w7 X9 C( S9 g5 uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 v- c) q4 p6 J, k" F. D$ _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 W$ P* I, \7 \1 D0 P, @/ B9 EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- i- P) J9 k' L1 L0x00, 0xFF);% f6 j" y' o" Z& O4 v% G6 r
, p6 N$ G9 ]5 X0 M) G, E- \
/* Enable synchronization of RX and TX sections */
4 h) x9 R4 R! b7 M" dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% O' n& u9 X, X) M3 S( X# I8 {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 C' h: m3 V' `4 u2 h8 I3 `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 N C. S& {# \- u7 u** Set the serializers, Currently only one serializer is set as9 r/ a6 f) t' w
** transmitter and one serializer as receiver., j! n! e6 c5 K
*/
! W+ _9 y2 @) s6 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 J% w- X0 B, \* e- q: jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 x% L5 E% l6 Q" }) s** Configure the McASP pins 9 y8 D/ \* w% W0 e' g9 N
** Input - Frame Sync, Clock and Serializer Rx1 U. k; m# d) d9 Q
** Output - Serializer Tx is connected to the input of the codec . o( L# F" G0 S. Q( \. l& b: z2 e% t
*/
, u, X. E) I5 w0 d3 h, i: AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ w8 p. h; }/ s! O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 L" C- d' T, G' _2 L0 K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 ~8 E4 e, }$ N7 P
| MCASP_PIN_ACLKX+ b" d2 R) p2 J# H6 o
| MCASP_PIN_AHCLKX: C5 S9 x$ |; Q( s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, A) V" I- k3 }1 L% a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- P! K5 Z1 f3 t3 f" o) G) N| MCASP_TX_CLKFAIL
# o' y& d0 }1 ]0 g/ L| MCASP_TX_SYNCERROR8 e7 t }, i. m1 ~' s5 C% k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 {$ d) m& T4 q- F5 p: e| MCASP_RX_CLKFAIL
+ _6 ~: X8 I! N" w4 l, w5 J' d$ a| MCASP_RX_SYNCERROR 3 f- h, X! J6 o Z4 c" i8 [
| MCASP_RX_OVERRUN);
: n M: p8 x9 t! d} static void I2SDataTxRxActivate(void)& c* q @6 d3 p0 k. Q/ U: M
{1 v" q; r" r1 r2 r( q" M* M
/* Start the clocks */
5 } G. \9 f- _9 t+ WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: r0 F1 @$ T" q3 m9 F( FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) Z1 [! g0 S6 G- N/ C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," W6 \0 V8 s3 h$ p+ R5 w6 I
EDMA3_TRIG_MODE_EVENT);
4 I# L/ `; r% V, S! l, hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 t" w9 O1 H8 @! v$ H# b) _/ b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; k& o3 Q# t6 Z3 O0 y# LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- n6 t( q+ ^9 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& h* B n9 r% j. o. h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& b k- g/ L/ {- m$ kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' D, G' l1 k* [/ ?; h2 f4 t# n- @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) }- i' ^/ {) i}
: M" @* G3 q/ p* B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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