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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; f. X5 k1 h3 Binput mcasp_ahclkx," ]0 h. R, I s# ~
input mcasp_aclkx,) A# B+ \. G) N) b4 g
input axr0,+ N0 d( D3 `8 N
- ~9 b" x& p9 y* v6 q S
output mcasp_afsr,
3 t& p" R; A3 ~) Houtput mcasp_ahclkr,+ ]9 _- I0 Q9 i8 K) f
output mcasp_aclkr,
0 p4 o' W9 f$ n* p2 Joutput axr1,
) D# }$ }/ q' f9 Y assign mcasp_afsr = mcasp_afsx;( {# d% v8 L {. E
assign mcasp_aclkr = mcasp_aclkx;
6 Z2 b3 g( g; p# q9 I* `assign mcasp_ahclkr = mcasp_ahclkx;
5 z( |8 r8 m3 o p( B3 @3 Passign axr1 = axr0; 8 m, W5 i+ o" g/ X, P
1 O) _5 ~+ X9 b9 r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + s, w. R# ^! c- u- x
static void McASPI2SConfigure(void)% z' R4 p, X, c" l2 [
{
( P% z9 S4 B5 `$ [McASPRxReset(SOC_MCASP_0_CTRL_REGS);* q& R: m! O4 ?: e7 E3 t* w' H7 B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 G! d: Y9 m! h; q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. s. h9 j' e% P& G/ x0 w! R: k% C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ e* ]( f( \: \; n, x) kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- P+ |! L4 P4 W/ v$ x8 m- B4 J* ]( s
MCASP_RX_MODE_DMA);
- l, E: A! V3 J, j: CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% v1 H# V+ [+ U: ]3 j* t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, S& P' v4 I) s0 Y" Y. |3 O9 PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : b$ i+ w5 I7 c' z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 P" X2 T2 z k! ]+ I& `( jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 ?( U3 c) p4 u4 F, D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) [& `5 m9 \: n8 ]! ?/ Y; h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. d: g' Y6 h$ g5 u1 \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . H% N2 x8 g7 c5 m+ D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 _6 M% J S1 B4 B( P5 t0x00, 0xFF); /* configure the clock for transmitter */) w1 }! B* J. P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ H1 u1 [1 ~( z( }/ S; aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + ?; u+ |: B9 ^, G' A$ [. B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' R; h) R% y" T/ m: A
0x00, 0xFF);, {0 a1 Z; t. Y1 T! I- I. c
4 ?1 D* l5 f4 ~ {5 V6 k: w/* Enable synchronization of RX and TX sections */ # z! i. N; F$ M# ^( B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* u1 e" f ?# @( I, w9 m2 i D+ C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! _* e+ o. ?( _# V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: d! K( F% F4 Z" e- \, l
** Set the serializers, Currently only one serializer is set as
4 e9 X$ S: w9 k' t: b/ d5 ~7 K. s** transmitter and one serializer as receiver.
8 \, g& A$ Q+ G*/
# C2 B4 y! Q9 ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( i- M, K9 n7 N" |; {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 [3 A8 e! F' z' m& ` c+ }
** Configure the McASP pins ! V/ l8 _9 S. h' [& D
** Input - Frame Sync, Clock and Serializer Rx4 X) `+ Q( m p' h8 F: N7 q
** Output - Serializer Tx is connected to the input of the codec # |( g8 [9 J" h/ [) Y" ^: C
*/' w& R, v- a F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' x6 Z; w( N; J: M: cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: P8 J7 t5 O- U8 P: {" u; f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- n/ ]# r+ S+ @- P0 t| MCASP_PIN_ACLKX. c' n% k ~6 z) y5 n
| MCASP_PIN_AHCLKX
, `, c4 T. t& t: F, K- f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* _" J& x7 b4 N) r Y5 r) @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % G0 D1 T' F/ Z, b9 L6 {
| MCASP_TX_CLKFAIL
( A0 [$ Q7 t2 |2 M9 p+ L: I. G| MCASP_TX_SYNCERROR
% C1 _# K) i- a. f4 S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) c& `+ w! e& _: g4 M% b* G
| MCASP_RX_CLKFAIL
5 ~. o5 K9 U, A; [" h| MCASP_RX_SYNCERROR & j% W% m- [( x1 W
| MCASP_RX_OVERRUN);' K, L: `% V! [0 N* s# B
} static void I2SDataTxRxActivate(void)
2 A" B; Z* C- r1 K* s/ ^2 H{
. c. f B/ W2 h. p, U/* Start the clocks */9 L4 n$ B% ?2 Y+ `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# r/ ~0 Z" v4 N& a* G' V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 l/ ~! `$ g+ {* }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) y0 x6 |8 r2 ]4 K8 `EDMA3_TRIG_MODE_EVENT);, S" Z% O3 [! ~2 ^2 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + j7 |5 ^0 p; q( x W7 D" c0 i# Q) C1 @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: l8 W' q( E, L5 C. RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 V2 U( O, b* F8 ^ L3 T8 j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: I- _4 u& e$ [# ?1 r: wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 p7 Q6 C0 V6 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ c) l h$ j7 Y F0 |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. l( e8 O7 \5 Q" c* O
}
% q7 x& _0 e: u: ^5 u! ]& Z3 ~. L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; @& `! [8 n: u* `! x* P
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