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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& T1 N" a0 R/ B8 [- t& \& p
input mcasp_ahclkx,. T: g9 ?% H5 i( u3 T) s
input mcasp_aclkx," E# [" r9 x3 J) h0 B
input axr0,
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" _0 D* z6 w% M8 s i6 B- uoutput mcasp_afsr, l4 N" ]9 ~, o! [$ F3 I. f
output mcasp_ahclkr,
# y$ C6 t7 z$ j9 _5 Voutput mcasp_aclkr,# _# ~+ p" A3 q* A
output axr1,
% S3 G% H- K5 s5 N6 X* F, A assign mcasp_afsr = mcasp_afsx;
/ t8 I+ q' [& o- w- Vassign mcasp_aclkr = mcasp_aclkx;
. G4 O# ]5 `. A- Passign mcasp_ahclkr = mcasp_ahclkx;/ x e* M) f u+ U( B: ~7 Y
assign axr1 = axr0;
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3 w# X9 @# d8 r( y" i7 k; u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# x. n9 [+ i% a* j$ R* r; B, fstatic void McASPI2SConfigure(void)/ {' j! Z$ j. T( ~' j' p
{ e; F! g0 i; ~- d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) j4 _: \9 B3 d9 X& ~+ p& F/ l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( ?" D, r+ u( _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) g( w# {4 o& V2 ]8 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' {; w$ k8 P5 `5 o1 cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 U! D; ?4 z& J$ ~) }& y' P* YMCASP_RX_MODE_DMA);. M' ?- H* b5 [5 k9 x' X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 V/ i9 U* W: L! J7 vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// M! u. l4 B, k& e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 N9 k$ @( N+ E; o4 v# C" l nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 [/ h# f9 M2 R7 s( b/ G3 |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # t2 P& ~! j' C0 t- ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 L4 P% m$ O* I9 n, `; a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 Y( L; p; M: l1 M) hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! h5 O2 N3 z$ ~2 B$ o) j+ C9 @6 C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ _- X$ D0 @+ p3 I! E* Z0x00, 0xFF); /* configure the clock for transmitter */
5 Q$ _ L( T" q4 J$ w* a9 PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# E4 w! E6 R$ S7 KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! K5 S! Q2 v# W) H2 Z4 v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 N; p. i% J2 C0 H% W" R
0x00, 0xFF);
$ n" j+ t$ _5 ~9 @; z- R2 X" I! B1 P& _ _: C
/* Enable synchronization of RX and TX sections */
9 F3 F5 {# r/ lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 N( R, W, z! ~6 z6 C% mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ Z" r l. G8 s2 c6 [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ j. K( ^" x9 ~, p/ V6 F/ x7 _
** Set the serializers, Currently only one serializer is set as; G& ?5 N" c0 D5 s7 _
** transmitter and one serializer as receiver.
2 E& ` ^$ j7 X0 W* P( d$ e) ~) x*/" m9 z8 z# {7 \2 U- L9 s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. E1 g6 A! t. o1 TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 N1 z* h+ ]+ w/ G** Configure the McASP pins ; R) U( z1 I& a. R$ T- a, E6 H
** Input - Frame Sync, Clock and Serializer Rx' V1 L: d( ~1 T. N+ d
** Output - Serializer Tx is connected to the input of the codec
% T! F8 R. b3 l0 K9 Q3 x0 ` @" f*/. g* G/ \: |1 l) w! I+ K; o0 a' O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& s6 c3 S) v9 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, w: r' c% ]' _3 q# z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 [7 h7 t! M& {( S' ~. T1 @0 _| MCASP_PIN_ACLKX
0 D' J) U( S+ L$ x# g+ D- v| MCASP_PIN_AHCLKX
8 P& ~- u+ i3 N& F5 y2 k7 ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# ?: z5 m! b! w9 PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; m9 K! ~ b9 M" i) C* }| MCASP_TX_CLKFAIL
! p3 c& _' H/ y! \5 p; x" X| MCASP_TX_SYNCERROR# I4 `+ }9 R+ c% J6 b) e; @$ p2 o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 u) q4 j& O: l0 k
| MCASP_RX_CLKFAIL$ x8 z; }- X' I) j
| MCASP_RX_SYNCERROR
0 j! v4 n5 p4 S1 Q, s| MCASP_RX_OVERRUN);
( s* `8 W& d/ e) e4 c3 g6 S0 y} static void I2SDataTxRxActivate(void)9 m6 L" d- S5 ^1 u9 }8 [
{
1 |" z/ s% f* {) G2 a8 b/* Start the clocks */
7 o# E$ O- Q9 JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* X. c" c( g! s+ N# @( Z, U( M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 f, C0 V' y! F) B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- O' n% i2 z" |. F" w0 @
EDMA3_TRIG_MODE_EVENT);; c" o" P0 U2 d0 ^7 j; {+ B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , r. _" _" [1 o( q- S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 N9 M; l3 Z( U7 V3 J* SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% a4 H) Z$ t I$ U) T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 C( a6 Y8 A) a9 P0 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- I' R" ]' Z) t, |+ Q7 G) t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 U3 T0 A$ K# c5 z7 M- Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# H! Z) Z# Z* r' ?
} + }5 [5 @" _( C; _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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