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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ Y. U" v7 {. r: W/ W+ h- D+ F$ e& a
input mcasp_ahclkx,3 |: [: Q. `, G
input mcasp_aclkx,/ ]" o5 c6 {% ~& Y- t) i- Q) l4 a
input axr0,
- ^7 ~& B) P5 t7 k3 u5 ^
: E" g) [( v3 ?7 Z1 ^& foutput mcasp_afsr,
Q7 g9 ~0 [6 B; S" W" _7 Ioutput mcasp_ahclkr,
3 Y* f" o1 F' Houtput mcasp_aclkr,
' A1 A: ]2 f! K2 n8 q+ aoutput axr1,
5 Q, t% b+ C9 I/ V2 O" |! X assign mcasp_afsr = mcasp_afsx;
% |- G$ f( a& ]# u* kassign mcasp_aclkr = mcasp_aclkx;$ M/ E# G3 V( B& k* G
assign mcasp_ahclkr = mcasp_ahclkx;& r7 i, }) @% ?6 v& `; U. R
assign axr1 = axr0; . ?1 |8 g! C: N( D
5 F" [& g$ q# j. n' t% O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 A5 U& D6 V) M- astatic void McASPI2SConfigure(void)
& W; p- E9 Z4 S$ u" x! |{- @1 @! f+ c# t) e" b* ?3 ? q& r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* M5 V* A: B. f$ U T }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" H- s% ?+ V! Z0 I& J- s# |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" l6 d8 T9 k: v5 R0 p( p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ q8 J# E- h2 a7 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% x+ o7 ^, G* {% {: I0 mMCASP_RX_MODE_DMA);* q9 a" K; q: S/ Q& A4 W6 s {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ C5 |3 m6 m E6 f8 H2 v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 w4 x! I: v' o9 u" |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ m9 g2 d! N7 e; X/ ?% i9 h* BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 q) M2 c0 K M2 O e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) H+ _5 C H% Y5 T4 I; BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ O9 H0 h: q: ^# V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; Q: H2 ?, _! u3 F+ MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * [% z3 r( j* f1 c4 _1 w; o Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. Q t8 J- b& C5 T1 b
0x00, 0xFF); /* configure the clock for transmitter */
5 G2 K' o# ~5 `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- V" O; e: a# V" ^$ j# B: Z a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: \( M& p- N0 e1 m( [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 r1 O6 |1 | ^3 V' o2 ~6 i0 u0x00, 0xFF);
# G) W% @$ r ?+ d1 G" @( J) t2 q5 M- a/ [0 o2 C
/* Enable synchronization of RX and TX sections */ . K( w. u9 @ a7 q3 s3 @, ], g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 ?) u, S! ?3 h" @- sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 e9 S' _1 e5 c* u [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% }! S" o( @1 c8 z0 M8 T$ i
** Set the serializers, Currently only one serializer is set as8 r4 U: n D7 L/ `% ?5 Z$ v
** transmitter and one serializer as receiver." J5 ?, ~7 h2 z
*/) y- b8 d5 A) T# [8 [# w" d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' w9 N' r* y9 ?$ D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' i {. t, g7 G4 ^ U7 \$ l9 n
** Configure the McASP pins
3 d$ S2 q& B2 M2 [2 U3 F** Input - Frame Sync, Clock and Serializer Rx- x1 W2 {& r# R3 ~7 ~4 q; }9 y
** Output - Serializer Tx is connected to the input of the codec 0 h( x8 ?2 J8 c/ z0 S
*/0 ~& V3 J5 l% z0 B& @, S" ` n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 S: ]: B0 ~0 N' @/ V3 e0 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 L! T4 B8 P l) MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 V0 P8 a- S: r i
| MCASP_PIN_ACLKX
' { Z! \" u1 H' t6 n| MCASP_PIN_AHCLKX/ L# R" f" A! x( ]7 b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 K3 {+ q, E- D9 J) E: m9 n( T, L4 D- |) ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " `0 Y% Q! l, e9 m# x) S
| MCASP_TX_CLKFAIL
" K. s' ]. x, Y/ Q; V| MCASP_TX_SYNCERROR
9 V! @* N. ?) T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 A% G# x& `# v: g7 p* d| MCASP_RX_CLKFAIL
; E9 r1 m% d! v- u| MCASP_RX_SYNCERROR
0 B. {( s& K3 `) v( ^6 M| MCASP_RX_OVERRUN);" `8 ^' p0 K( q; ?$ [
} static void I2SDataTxRxActivate(void)# O8 Q" `9 S; L, s
{
/ E$ e7 r2 X f5 j Q# y/* Start the clocks */
( h& i8 b; G/ y! O6 h9 p! aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 W0 w$ |. B- C5 j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* M% p) e+ A0 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ Y+ U" n$ A7 l# m( M" AEDMA3_TRIG_MODE_EVENT);/ X( H9 c( ^( ~% J/ a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: e1 @( X% B" Z s. O1 dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ Q, R) x1 H4 @, i, W% c8 {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' [9 d! j- M! W8 L% p' A+ QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; R5 ~6 q/ b1 h7 |! M9 @" H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 ?7 Y: b# g! _; h& P/ m6 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 p' A4 Q3 |- e2 BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ J# C; j8 V4 P% ] m1 w7 w0 p) u: _
}
. G6 L) v" ?0 t9 I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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