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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! x/ [& F6 `& L% Binput mcasp_ahclkx,9 S3 k& o+ z% r% B$ l+ _( E
input mcasp_aclkx,% z9 F7 S% g" k \* L6 |
input axr0,
0 m! {4 ~0 O: S0 S4 p3 J3 Q! l: C {2 T' P& a
output mcasp_afsr,& ?! V9 n4 ]$ f1 [( C
output mcasp_ahclkr,
: {3 n# j' f8 D. c! w4 {output mcasp_aclkr,
( x3 F8 `% B6 g; i9 doutput axr1,- d5 m, @$ D: z- u
assign mcasp_afsr = mcasp_afsx;
" p; I% M. U0 p5 k) s2 P6 uassign mcasp_aclkr = mcasp_aclkx;5 h0 P3 D `0 O S- V: J
assign mcasp_ahclkr = mcasp_ahclkx;
* @0 r) w& _' n7 L) e9 k& w1 \assign axr1 = axr0;
% R9 \$ w8 L$ i
* @7 {3 k' k( h& z7 D4 q9 e% P/ ]& k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 h! U4 o/ G2 E& F5 l: s
static void McASPI2SConfigure(void)/ R3 Y1 }* P J+ t# f, n
{
2 f: m3 g- w& |# CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* S9 ]% g2 V# e& f P+ N" nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 J3 c' H+ v$ T" w) `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 b1 |. w3 j. W: D* p$ Q: CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 K4 D* w8 B! Q; g( xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' t* T5 g+ ]: {; R- _7 \$ T; |) t( [MCASP_RX_MODE_DMA);6 K) @' l% j) q& N$ V F8 [, A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, o2 W6 n4 h- ~' b! J0 Z+ o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 J& l' w" f. D% q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 m- r! {& B- c5 B8 A& f5 ]3 e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( k8 [* V% V& ?. c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # m" t' x q* j" t" i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* S) b0 r$ t8 H( nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" L$ i: E4 h0 |' T( n( _( I0 RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# [% K1 t. g6 sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 y7 B0 e: r9 F+ w- ~+ C
0x00, 0xFF); /* configure the clock for transmitter */) E5 @9 |9 r u/ F- {) b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, I6 z4 E- s- M5 {4 F" cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 z! |3 C* |+ b. v0 c: u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. V. h# a8 \' B9 K
0x00, 0xFF);
6 P; W8 p% |/ r- J1 Q9 p3 T3 _7 s T; [
/* Enable synchronization of RX and TX sections */ + R) j" c+ S0 n5 T9 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 D' r h6 A3 @5 }( c F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 o+ c0 @. f. |' QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' [% e! `8 P0 `' s ?6 b
** Set the serializers, Currently only one serializer is set as
2 |9 W. s/ W" ?9 }7 @6 B** transmitter and one serializer as receiver.
7 `# z: l$ [/ w$ T, u8 V*// @ C/ b' h* m [' ?* U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 [$ w2 T) a9 s6 d7 [: Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 L7 K% V' o8 y9 K) z1 g** Configure the McASP pins
) ^" ~( @7 U" V$ D# ~6 |** Input - Frame Sync, Clock and Serializer Rx
' H/ b |; J+ u5 w* r! @+ w** Output - Serializer Tx is connected to the input of the codec
$ {& g: [% r2 _. n( h" ~6 u# G3 {*/
; ?/ y3 f* {# Z$ W ~' c( O qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 {5 q: c+ g. m. p0 R1 `1 b; h! N. r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' x* _& E( k( e& x, lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& O O2 k# M4 }% m
| MCASP_PIN_ACLKX
1 b' ^; V, u: w8 l) R| MCASP_PIN_AHCLKX
* x4 n- c' |9 n& F; \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 n3 H }: O+ M1 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 d( U X1 s# c M+ Z2 K; s: B| MCASP_TX_CLKFAIL
/ @/ A0 B3 u& _1 G4 t- e" _| MCASP_TX_SYNCERROR
0 @6 U; L: o' u( b+ m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 `" g) l1 A& [| MCASP_RX_CLKFAIL
( R+ j l7 K5 \6 S" s8 `0 R| MCASP_RX_SYNCERROR
+ ~& R" t% Z8 }1 c j# ]| MCASP_RX_OVERRUN);: b N# H! z# g# w |/ u
} static void I2SDataTxRxActivate(void)
c2 W+ ~8 e; [* V3 M# P{1 I0 o5 Q: C z/ m8 d
/* Start the clocks */
/ ]# g# R- C/ \. z% p& \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 p: {) W) o* w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, u- O1 _& i# ~6 r! PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- _# k! E+ P+ ^7 p; K2 h- ~" U# n
EDMA3_TRIG_MODE_EVENT);
5 v' N2 T6 b$ ]4 @# w8 X/ PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * O6 K s3 a+ Y! L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( V7 _! b+ b' ]; b& p0 I/ U! Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" ~0 Y6 m; E4 G) B5 oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( {* R2 t1 M7 R+ g) P/ qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 d+ j$ L. f! X! q6 Q @/ [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 n$ S# E2 r& I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& w) I: a7 i9 s1 ^, G. |} 1 a8 ~& u8 r- O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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