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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, v5 Y, X! }0 c0 d. t
input mcasp_ahclkx,
# h$ ^4 D( ~7 d; Y% X3 o/ O" q; [/ ^/ E3 einput mcasp_aclkx,* d9 a3 }5 r9 z
input axr0,% G9 p+ r) |$ I- C H( Q+ w+ R
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output mcasp_afsr,$ H2 z! x \6 v8 G
output mcasp_ahclkr,
9 o l. y+ l ^1 T7 B* \. woutput mcasp_aclkr,
5 k& p6 R7 k$ J, L0 |; z Ioutput axr1,
! t' A, ~" R) m8 F9 x assign mcasp_afsr = mcasp_afsx;) }, [ s1 O* @8 [, h9 V$ f4 r
assign mcasp_aclkr = mcasp_aclkx;
1 i( O$ }4 \$ G- dassign mcasp_ahclkr = mcasp_ahclkx;: B* }9 s* X# N9 j4 J! H
assign axr1 = axr0;
+ ~$ ]$ }" O* L* N0 B( P2 C
, ~: U$ _$ }/ Z0 f3 n0 C& Y b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " v4 @+ V2 R- H) m) T3 |
static void McASPI2SConfigure(void)% S7 Z3 m7 s" ^! \ z0 ^/ r
{+ Y+ v' U, H3 e: {0 v
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 t5 b+ \9 d) ?& r' M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 }6 r v# s5 ]8 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) x! _0 \9 d( y' C+ a- N( ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 q2 a! C0 r2 k% M) ~% xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 S; r; U2 p. B* P# J; PMCASP_RX_MODE_DMA);3 @( M9 [2 A+ t4 _5 I* X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 y9 K, p' E+ E2 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 A* _2 }, D' }5 hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ {4 M! w$ d2 H0 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 l' H( n) }( h4 \0 I( P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 z5 ?- O% T. N1 ]' N) o% vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, q X D9 f( I/ J6 E" c1 A' z7 l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 `& B0 t( b6 E p+ \- v" k/ \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 l& m' s$ C: A9 Z+ R( [0 h# K/ k, ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 {! }3 r; R0 Z' q+ g% {0x00, 0xFF); /* configure the clock for transmitter */
# z5 ^5 l8 n, N1 I4 I a2 @: AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 V3 e" T+ y% n+ h1 \- \4 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' j1 j5 V* |/ k, h; B& D2 D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& c! U% e, `) U$ y$ S0 {0x00, 0xFF);
& @! K* m7 Z6 c3 ~) i$ |! M9 p3 I8 P. X* y
/* Enable synchronization of RX and TX sections */ - O& m+ J: t1 C9 O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 W( `1 T# o) k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 u1 ^$ N) J4 b* v/ ~( L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" m* z% o) A5 X( \$ B3 D& W$ [# V+ v** Set the serializers, Currently only one serializer is set as
7 U' N3 X D* O: q** transmitter and one serializer as receiver.
# f' U, U' U& O: [, b*/+ m4 J3 k7 a3 Z, {" f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 o0 e! U& n8 j6 I) d, V2 s, eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, G2 H) \5 s8 X9 |
** Configure the McASP pins 5 t: e+ k7 T' q2 a
** Input - Frame Sync, Clock and Serializer Rx( W# B8 W6 F) k u& M
** Output - Serializer Tx is connected to the input of the codec ' v7 {6 Y V7 @
*/3 k; p% X0 s9 Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. m; n5 S7 u9 x& x( `3 MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 c/ d* U- w1 D) }$ \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* G2 e7 h& s6 N| MCASP_PIN_ACLKX
+ q6 Z) u$ ?4 E8 [/ t: E| MCASP_PIN_AHCLKX
' N* @. X0 S `0 r# y# B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! d+ Z5 B( D/ B$ o' o6 D8 J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " b' t) F) ~+ m/ Q+ `/ k# `4 S
| MCASP_TX_CLKFAIL
1 V4 {; ]/ _. i9 {7 q8 I) u| MCASP_TX_SYNCERROR( ^1 |& I3 n+ a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 W! F) N" X$ ^5 a1 p| MCASP_RX_CLKFAIL
8 o0 _1 J. o; V4 v* t5 }| MCASP_RX_SYNCERROR
- {: I9 o0 H6 Z0 V0 I8 U' F, [| MCASP_RX_OVERRUN);/ N5 ?% M3 L" e
} static void I2SDataTxRxActivate(void)
1 b6 E5 i4 G% l0 z: }{
& }, O7 T+ Q- U; p: f! A/* Start the clocks */4 b) Y* U5 u4 }) R- c& w7 K6 t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
I) W( B! X+ \! c V) ]. c- v5 VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& z( s: R; t |3 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 b. N: T& t, j0 e
EDMA3_TRIG_MODE_EVENT);
4 X: k3 V( ?7 j* A; Q+ W% kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - E/ j: G2 ^7 x& e1 p% B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 B% W8 T) M9 m. A8 F$ `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ `: ?1 C- Y( S# a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ e5 ]$ P/ c5 a, I% s: X- O l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ j; d4 ] ]# O P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" H# M( A% r" H* a8 J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 j$ d4 W. @3 b. p, x8 t9 ?( P1 H: a
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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