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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# o3 }9 }: G8 h( Q' k! h C
input mcasp_ahclkx,( H) ^( c. M8 J/ E
input mcasp_aclkx,5 |1 F* O3 J! h5 t' X2 s% M
input axr0,# Z3 E3 f G4 ~. }
3 n+ m8 @$ p! Q# c+ W& Y
output mcasp_afsr,9 D. i' G' K5 t1 }0 U' R
output mcasp_ahclkr,& F: W p, [- i+ K$ ~
output mcasp_aclkr,
# N. S9 n1 M; o- {* e- Voutput axr1,6 g# [1 X; O C; w( B
assign mcasp_afsr = mcasp_afsx;' J7 v* `6 U8 G. C) p
assign mcasp_aclkr = mcasp_aclkx;4 J% F$ ~3 s% J/ n( m/ E( l
assign mcasp_ahclkr = mcasp_ahclkx;
% L6 ~* p7 u+ v2 kassign axr1 = axr0; ; m& r$ r: y9 O3 h& n F& O
" Z6 H7 R, _* Z$ C0 H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 ?- H8 n$ b& ^" ]$ m
static void McASPI2SConfigure(void)
. q8 H2 k' ~1 z9 N( r1 a+ H2 H{
4 w1 W- J6 W& d% _4 f5 ]' MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 b2 f: ^1 F/ w0 r! tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) a$ C9 L+ M* i1 ]0 }: g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- B- J% U3 B( |9 V0 z4 t+ A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; n* k1 M, {7 n0 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- m! O; ]: J0 J* ^MCASP_RX_MODE_DMA);3 U+ ]6 P. l8 _. |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( P2 M6 L9 X! C) O6 w' _( R% l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" H% n5 e! ]# ]+ E" qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 c/ `% [- O9 ~8 [! U/ O4 ^0 _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# o" t& U3 D0 h9 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - i) k5 f$ r5 O% N8 {- G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ Q8 b( V, `! _1 BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( w0 ? r6 n- {# w' I5 [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# g( Y- P6 K4 v t- u/ j6 sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ q) M8 _) J5 A# S/ T- e' E0x00, 0xFF); /* configure the clock for transmitter */
! @# q* Y3 I3 M! ^- x& nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 e- H+ |3 g; Y( m' k p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 |, v* ^& `# ~! W' I/ c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; Z3 R+ l7 a6 z; X0x00, 0xFF);0 ?; t2 w2 F) U8 |$ T
V* @# o) L3 s
/* Enable synchronization of RX and TX sections */ * b& M: [- q) f6 k. _ t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 G: v) z- H* G, w+ R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- Q' Q0 a8 z* a% d m6 I3 b( Q% |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& o& b! f/ x$ U3 \
** Set the serializers, Currently only one serializer is set as
9 U1 ?& ~8 ?' i7 z+ Z** transmitter and one serializer as receiver.
+ t0 m. r+ c: N, D*/
3 L$ ^ c1 G! a6 }9 T, O( yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 g. G5 V9 M8 f$ iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; c* f% [8 Z+ i/ M$ `* x) K+ T
** Configure the McASP pins
% v G7 O: I; o: u) H** Input - Frame Sync, Clock and Serializer Rx
0 S3 Y+ I7 o+ U2 P9 n** Output - Serializer Tx is connected to the input of the codec
3 l; v6 v% s" W% r5 @8 }5 _2 u*/
% r8 B- P" a3 I" \7 |# }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( N2 _- x" H8 ]: S) S( q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* u' w0 x6 i. L* g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. A) j- z2 ]/ i9 t| MCASP_PIN_ACLKX3 ^. V" P7 [) L2 D/ _: R1 G
| MCASP_PIN_AHCLKX' O @1 O I3 U1 q( E. E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, g* s6 ] n# U. n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 E1 e- \3 q; [3 ~: k/ C. k7 K% w| MCASP_TX_CLKFAIL ; n+ T2 c Y& \# J5 z+ X; S4 W# P X
| MCASP_TX_SYNCERROR# e: C7 z; F! \% Y. [5 j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) l6 Z7 ^; @: s7 c& c
| MCASP_RX_CLKFAIL
: |, O: Z7 W1 z0 I| MCASP_RX_SYNCERROR % Y. P1 K! Z I# n
| MCASP_RX_OVERRUN);
1 W) j9 W1 I9 U, d3 e} static void I2SDataTxRxActivate(void)% x8 E6 Z3 O% m6 M+ m/ i
{
& Y' Y9 C9 g! |& h/* Start the clocks */
+ g: n9 j$ K I7 ^# cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
`- |5 ?) H7 M6 T5 x( ?5 O, lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 p! m3 C' f* p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 s; k2 m" V. \
EDMA3_TRIG_MODE_EVENT);0 V ^" V* f$ Y: o" p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 D$ Q: Z6 z! p4 B: N# U$ eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% ^/ u) L" d6 c+ x0 Q w4 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 ?- A. f7 m/ Z1 }! y' o& P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 M4 h- E9 \0 F; E' Q7 wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# s9 C9 ^/ h5 ]5 e( I! F+ Z$ e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 W) [) \ K$ T3 | J+ l. n* LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! p" x% J. R; _9 o}
/ z. w. F! a# @1 j9 L0 ?) x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " v# G( d' W8 Z2 t
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