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本帖最后由 xdh_k7 于 2021-8-24 10:51 编辑
尤其是那些差分时钟, 我用原语转成普通始终后好像没什么用? 用ILA也无法抓到波形?- //-----------------------------------------------------------------------------
- //
- // (c) Copyright 2013 Tronlong, Inc. All rights reserved.
- //
- //-----------------------------------------------------------------------------
- `timescale 1ns / 1ps
- module tl_led_flash(
- input clk_p,
- input clk_n,
- output reg [1:0] led // led gpio output
- );
- // Delay lenght: 32_500_000, 500ms, by used 65MHz cfgmclk
- parameter DELAY_LEN = 28'd100000000; //26'd3249_9999;
- reg [27:0] delay_cnt;
- wire cfgmclk;
- //wire eos_n;
- IBUFDS IBUFDS_inst(
- .I(clk_p),
- .IB(clk_n),
- .O(cfgmclk)
- );
- //STARTUPE2 #()
- //STARTUPE2_inst (
- // .CFGMCLK(cfgmclk), // 1-bit output: Configuration internal oscillator clock output 65MHz.
- // .EOS(eos_n) // 1-bit output: Active high output signal indicating the End Of Startup.
- //);
- // Led flash with delay counter by cfgmclk
- always@(posedge cfgmclk)
- // if(!eos_n)
- // begin
- // delay_cnt <= 26'd0; // reset delay_cnt
- // led <= 2'b0; // led output low
- // end
- // else
- if(delay_cnt == DELAY_LEN)
- begin
- delay_cnt <= 26'd0; // reset delay_cnt;
- led <= ~led; // change led output status;
- end
- else
- delay_cnt <= delay_cnt + 1'b1;
- endmodule
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- create_clock -period 10.000 -name sys_clk [get_ports clk_p]
- set_property PACKAGE_PIN AA3 [get_ports clk_p]
- set_property IOSTANDARD LVDS [get_ports clk_p]
- set_property PACKAGE_PIN AF3 [get_ports {led[0]}]
- set_property PACKAGE_PIN AF2 [get_ports {led[1]}]
- set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}]
- set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}]
- # enable bitstream compression
- set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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