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楼主 |
发表于 2019-7-30 11:12:38
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always@ (posedge clk)
begin
if(count >= 32'd30_000_000)
begin
d <= ~d;
count <= 0;
end
else begin
d <= d;
count <= count + 32'd1;
end
end
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst (
.Q(datao), // 1-bit DDR output
.C(clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(d), // 1-bit data input (positive edge)
.D2(1'b0), // 1-bit data input (negative edge)
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
主要由于时钟速率过高引起,正确使用方法如此 |
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