芯片手册关于uPP接口的DMA重载transfer descriptors的叙述比较简短:
Each DMA channel allows a second descriptor to be queued while the previously programmed DMA
transfer is still running. The UPxS2.PEND bit reports whether a new set of DMA parameters may be
written to the DMA descriptor registers. Each DMA channel can have at most one active transfer and one
queued transfer. This allows each I/O channel to perform uninterrupted, consecutive transactions across
DMA transfer boundaries.
The internal DMA controller does not support automatically reloading DMA transfer descriptors. Each
successive descriptor set must be explicitly written to the UPxDn registers by software
该段说DMA控制器不支持自动重载transfer descriptors,需要手动修改UPxDn registers。问题是,手动修改UPxDn registers会影响正在运行的DMA传输吗?正确的修改操作过程是怎样的?怎么保证在当前传输结束前及时修改transfer descriptors。
|